2 * BPF Jit compiler for s390.
4 * Minimum build requirements:
6 * - HAVE_MARCH_Z196_FEATURES: laal, laalg
7 * - HAVE_MARCH_Z10_FEATURES: msfi, cgrj, clgrj
8 * - HAVE_MARCH_Z9_109_FEATURES: alfi, llilf, clfi, oilf, nilf
12 * Copyright IBM Corp. 2012,2015
14 * Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>
15 * Michael Holzheu <holzheu@linux.vnet.ibm.com>
18 #define KMSG_COMPONENT "bpf_jit"
19 #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
21 #include <linux/netdevice.h>
22 #include <linux/filter.h>
23 #include <linux/init.h>
24 #include <asm/cacheflush.h>
28 int bpf_jit_enable __read_mostly;
31 u32 seen; /* Flags to remember seen eBPF instructions */
32 u32 seen_reg[16]; /* Array to remember which registers are used */
33 u32 *addrs; /* Array with relative instruction addresses */
34 u8 *prg_buf; /* Start of program */
35 int size; /* Size of program and literal pool */
36 int size_prg; /* Size of program */
37 int prg; /* Current position in program */
38 int lit_start; /* Start of literal pool */
39 int lit; /* Current position in literal pool */
40 int base_ip; /* Base address for literal pool */
41 int ret0_ip; /* Address of return 0 */
42 int exit_ip; /* Address of exit */
45 #define BPF_SIZE_MAX 4096 /* Max size for program */
47 #define SEEN_SKB 1 /* skb access */
48 #define SEEN_MEM 2 /* use mem[] for temporary storage */
49 #define SEEN_RET0 4 /* ret0_ip points to a valid return 0 */
50 #define SEEN_LITERAL 8 /* code uses literals */
51 #define SEEN_FUNC 16 /* calls C functions */
52 #define SEEN_STACK (SEEN_FUNC | SEEN_MEM | SEEN_SKB)
57 #define REG_W0 (__MAX_BPF_REG+0) /* Work register 1 (even) */
58 #define REG_W1 (__MAX_BPF_REG+1) /* Work register 2 (odd) */
59 #define REG_SKB_DATA (__MAX_BPF_REG+2) /* SKB data register */
60 #define REG_L (__MAX_BPF_REG+3) /* Literal pool register */
61 #define REG_15 (__MAX_BPF_REG+4) /* Register 15 */
62 #define REG_0 REG_W0 /* Register 0 */
63 #define REG_2 BPF_REG_1 /* Register 2 */
64 #define REG_14 BPF_REG_0 /* Register 14 */
67 * Mapping of BPF registers to s390 registers
69 static const int reg2hex[] = {
72 /* Function parameters */
78 /* Call saved registers */
83 /* BPF stack pointer */
85 /* SKB data pointer */
87 /* Work registers for s390x backend */
94 static inline u32 reg(u32 dst_reg, u32 src_reg)
96 return reg2hex[dst_reg] << 4 | reg2hex[src_reg];
99 static inline u32 reg_high(u32 reg)
101 return reg2hex[reg] << 4;
104 static inline void reg_set_seen(struct bpf_jit *jit, u32 b1)
106 u32 r1 = reg2hex[b1];
108 if (!jit->seen_reg[r1] && r1 >= 6 && r1 <= 15)
109 jit->seen_reg[r1] = 1;
112 #define REG_SET_SEEN(b1) \
114 reg_set_seen(jit, b1); \
117 #define REG_SEEN(b1) jit->seen_reg[reg2hex[(b1)]]
120 * EMIT macros for code generation
126 *(u16 *) (jit->prg_buf + jit->prg) = op; \
130 #define EMIT2(op, b1, b2) \
132 _EMIT2(op | reg(b1, b2)); \
140 *(u32 *) (jit->prg_buf + jit->prg) = op; \
144 #define EMIT4(op, b1, b2) \
146 _EMIT4(op | reg(b1, b2)); \
151 #define EMIT4_RRF(op, b1, b2, b3) \
153 _EMIT4(op | reg_high(b3) << 8 | reg(b1, b2)); \
159 #define _EMIT4_DISP(op, disp) \
161 unsigned int __disp = (disp) & 0xfff; \
162 _EMIT4(op | __disp); \
165 #define EMIT4_DISP(op, b1, b2, disp) \
167 _EMIT4_DISP(op | reg_high(b1) << 16 | \
168 reg_high(b2) << 8, disp); \
173 #define EMIT4_IMM(op, b1, imm) \
175 unsigned int __imm = (imm) & 0xffff; \
176 _EMIT4(op | reg_high(b1) << 16 | __imm); \
180 #define EMIT4_PCREL(op, pcrel) \
182 long __pcrel = ((pcrel) >> 1) & 0xffff; \
183 _EMIT4(op | __pcrel); \
186 #define _EMIT6(op1, op2) \
188 if (jit->prg_buf) { \
189 *(u32 *) (jit->prg_buf + jit->prg) = op1; \
190 *(u16 *) (jit->prg_buf + jit->prg + 4) = op2; \
195 #define _EMIT6_DISP(op1, op2, disp) \
197 unsigned int __disp = (disp) & 0xfff; \
198 _EMIT6(op1 | __disp, op2); \
201 #define EMIT6_DISP(op1, op2, b1, b2, b3, disp) \
203 _EMIT6_DISP(op1 | reg(b1, b2) << 16 | \
204 reg_high(b3) << 8, op2, disp); \
210 #define _EMIT6_DISP_LH(op1, op2, disp) \
212 unsigned int __disp_h = ((u32)disp) & 0xff000; \
213 unsigned int __disp_l = ((u32)disp) & 0x00fff; \
214 _EMIT6(op1 | __disp_l, op2 | __disp_h >> 4); \
217 #define EMIT6_DISP_LH(op1, op2, b1, b2, b3, disp) \
219 _EMIT6_DISP_LH(op1 | reg(b1, b2) << 16 | \
220 reg_high(b3) << 8, op2, disp); \
226 #define EMIT6_PCREL(op1, op2, b1, b2, i, off, mask) \
228 /* Branch instruction needs 6 bytes */ \
229 int rel = (addrs[i + off + 1] - (addrs[i + 1] - 6)) / 2;\
230 _EMIT6(op1 | reg(b1, b2) << 16 | rel, op2 | mask); \
235 #define _EMIT6_IMM(op, imm) \
237 unsigned int __imm = (imm); \
238 _EMIT6(op | (__imm >> 16), __imm & 0xffff); \
241 #define EMIT6_IMM(op, b1, imm) \
243 _EMIT6_IMM(op | reg_high(b1) << 16, imm); \
247 #define EMIT_CONST_U32(val) \
250 ret = jit->lit - jit->base_ip; \
251 jit->seen |= SEEN_LITERAL; \
253 *(u32 *) (jit->prg_buf + jit->lit) = (u32) val; \
258 #define EMIT_CONST_U64(val) \
261 ret = jit->lit - jit->base_ip; \
262 jit->seen |= SEEN_LITERAL; \
264 *(u64 *) (jit->prg_buf + jit->lit) = (u64) val; \
269 #define EMIT_ZERO(b1) \
271 /* llgfr %dst,%dst (zero extend to 64 bit) */ \
272 EMIT4(0xb9160000, b1, b1); \
277 * Fill whole space with illegal instructions
279 static void jit_fill_hole(void *area, unsigned int size)
281 memset(area, 0, size);
285 * Save registers from "rs" (register start) to "re" (register end) on stack
287 static void save_regs(struct bpf_jit *jit, u32 rs, u32 re)
289 u32 off = 72 + (rs - 6) * 8;
292 /* stg %rs,off(%r15) */
293 _EMIT6(0xe300f000 | rs << 20 | off, 0x0024);
295 /* stmg %rs,%re,off(%r15) */
296 _EMIT6_DISP(0xeb00f000 | rs << 20 | re << 16, 0x0024, off);
300 * Restore registers from "rs" (register start) to "re" (register end) on stack
302 static void restore_regs(struct bpf_jit *jit, u32 rs, u32 re)
304 u32 off = 72 + (rs - 6) * 8;
306 if (jit->seen & SEEN_STACK)
310 /* lg %rs,off(%r15) */
311 _EMIT6(0xe300f000 | rs << 20 | off, 0x0004);
313 /* lmg %rs,%re,off(%r15) */
314 _EMIT6_DISP(0xeb00f000 | rs << 20 | re << 16, 0x0004, off);
318 * Return first seen register (from start)
320 static int get_start(struct bpf_jit *jit, int start)
324 for (i = start; i <= 15; i++) {
325 if (jit->seen_reg[i])
332 * Return last seen register (from start) (gap >= 2)
334 static int get_end(struct bpf_jit *jit, int start)
338 for (i = start; i < 15; i++) {
339 if (!jit->seen_reg[i] && !jit->seen_reg[i + 1])
342 return jit->seen_reg[15] ? 15 : 14;
346 #define REGS_RESTORE 0
348 * Save and restore clobbered registers (6-15) on stack.
349 * We save/restore registers in chunks with gap >= 2 registers.
351 static void save_restore_regs(struct bpf_jit *jit, int op)
357 rs = get_start(jit, re);
360 re = get_end(jit, rs + 1);
362 save_regs(jit, rs, re);
364 restore_regs(jit, rs, re);
370 * Emit function prologue
372 * Save registers and create stack frame if necessary.
373 * See stack frame layout desription in "bpf_jit.h"!
375 static void bpf_jit_prologue(struct bpf_jit *jit)
378 save_restore_regs(jit, REGS_SAVE);
379 /* Setup literal pool */
380 if (jit->seen & SEEN_LITERAL) {
382 EMIT2(0x0d00, REG_L, REG_0);
383 jit->base_ip = jit->prg;
385 /* Setup stack and backchain */
386 if (jit->seen & SEEN_STACK) {
387 /* lgr %bfp,%r15 (BPF frame pointer) */
388 EMIT4(0xb9040000, BPF_REG_FP, REG_15);
389 /* aghi %r15,-STK_OFF */
390 EMIT4_IMM(0xa70b0000, REG_15, -STK_OFF);
391 if (jit->seen & SEEN_FUNC)
392 /* stg %bfp,152(%r15) (backchain) */
393 EMIT6_DISP_LH(0xe3000000, 0x0024, BPF_REG_FP, REG_0,
397 * For SKB access %b1 contains the SKB pointer. For "bpf_jit.S"
398 * we store the SKB header length on the stack and the SKB data
399 * pointer in REG_SKB_DATA.
401 if (jit->seen & SEEN_SKB) {
402 /* Header length: llgf %w1,<len>(%b1) */
403 EMIT6_DISP_LH(0xe3000000, 0x0016, REG_W1, REG_0, BPF_REG_1,
404 offsetof(struct sk_buff, len));
405 /* s %w1,<data_len>(%b1) */
406 EMIT4_DISP(0x5b000000, REG_W1, BPF_REG_1,
407 offsetof(struct sk_buff, data_len));
408 /* stg %w1,ST_OFF_HLEN(%r0,%r15) */
409 EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W1, REG_0, REG_15,
411 /* lg %skb_data,data_off(%b1) */
412 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_SKB_DATA, REG_0,
413 BPF_REG_1, offsetof(struct sk_buff, data));
415 /* BPF compatibility: clear A (%b7) and X (%b8) registers */
416 if (REG_SEEN(BPF_REG_7))
418 EMIT4_IMM(0xa7090000, BPF_REG_7, 0);
419 if (REG_SEEN(BPF_REG_8))
421 EMIT4_IMM(0xa7090000, BPF_REG_8, 0);
427 static void bpf_jit_epilogue(struct bpf_jit *jit)
430 if (jit->seen & SEEN_RET0) {
431 jit->ret0_ip = jit->prg;
433 EMIT4_IMM(0xa7090000, BPF_REG_0, 0);
435 jit->exit_ip = jit->prg;
436 /* Load exit code: lgr %r2,%b0 */
437 EMIT4(0xb9040000, REG_2, BPF_REG_0);
438 /* Restore registers */
439 save_restore_regs(jit, REGS_RESTORE);
445 * Compile one eBPF instruction into s390x code
447 * NOTE: Use noinline because for gcov (-fprofile-arcs) gcc allocates a lot of
448 * stack space for the large switch statement.
450 static noinline int bpf_jit_insn(struct bpf_jit *jit, struct bpf_prog *fp, int i)
452 struct bpf_insn *insn = &fp->insnsi[i];
453 int jmp_off, last, insn_count = 1;
454 unsigned int func_addr, mask;
455 u32 dst_reg = insn->dst_reg;
456 u32 src_reg = insn->src_reg;
457 u32 *addrs = jit->addrs;
461 switch (insn->code) {
465 case BPF_ALU | BPF_MOV | BPF_X: /* dst = (u32) src */
466 /* llgfr %dst,%src */
467 EMIT4(0xb9160000, dst_reg, src_reg);
469 case BPF_ALU64 | BPF_MOV | BPF_X: /* dst = src */
471 EMIT4(0xb9040000, dst_reg, src_reg);
473 case BPF_ALU | BPF_MOV | BPF_K: /* dst = (u32) imm */
475 EMIT6_IMM(0xc00f0000, dst_reg, imm);
477 case BPF_ALU64 | BPF_MOV | BPF_K: /* dst = imm */
479 EMIT6_IMM(0xc0010000, dst_reg, imm);
484 case BPF_LD | BPF_IMM | BPF_DW: /* dst = (u64) imm */
486 /* 16 byte instruction that uses two 'struct bpf_insn' */
489 imm64 = (u64)(u32) insn[0].imm | ((u64)(u32) insn[1].imm) << 32;
490 /* lg %dst,<d(imm)>(%l) */
491 EMIT6_DISP_LH(0xe3000000, 0x0004, dst_reg, REG_0, REG_L,
492 EMIT_CONST_U64(imm64));
499 case BPF_ALU | BPF_ADD | BPF_X: /* dst = (u32) dst + (u32) src */
501 EMIT2(0x1a00, dst_reg, src_reg);
504 case BPF_ALU64 | BPF_ADD | BPF_X: /* dst = dst + src */
506 EMIT4(0xb9080000, dst_reg, src_reg);
508 case BPF_ALU | BPF_ADD | BPF_K: /* dst = (u32) dst + (u32) imm */
512 EMIT6_IMM(0xc20b0000, dst_reg, imm);
515 case BPF_ALU64 | BPF_ADD | BPF_K: /* dst = dst + imm */
519 EMIT6_IMM(0xc2080000, dst_reg, imm);
524 case BPF_ALU | BPF_SUB | BPF_X: /* dst = (u32) dst - (u32) src */
526 EMIT2(0x1b00, dst_reg, src_reg);
529 case BPF_ALU64 | BPF_SUB | BPF_X: /* dst = dst - src */
531 EMIT4(0xb9090000, dst_reg, src_reg);
533 case BPF_ALU | BPF_SUB | BPF_K: /* dst = (u32) dst - (u32) imm */
537 EMIT6_IMM(0xc20b0000, dst_reg, -imm);
540 case BPF_ALU64 | BPF_SUB | BPF_K: /* dst = dst - imm */
544 EMIT6_IMM(0xc2080000, dst_reg, -imm);
549 case BPF_ALU | BPF_MUL | BPF_X: /* dst = (u32) dst * (u32) src */
551 EMIT4(0xb2520000, dst_reg, src_reg);
554 case BPF_ALU64 | BPF_MUL | BPF_X: /* dst = dst * src */
556 EMIT4(0xb90c0000, dst_reg, src_reg);
558 case BPF_ALU | BPF_MUL | BPF_K: /* dst = (u32) dst * (u32) imm */
562 EMIT6_IMM(0xc2010000, dst_reg, imm);
565 case BPF_ALU64 | BPF_MUL | BPF_K: /* dst = dst * imm */
569 EMIT6_IMM(0xc2000000, dst_reg, imm);
574 case BPF_ALU | BPF_DIV | BPF_X: /* dst = (u32) dst / (u32) src */
575 case BPF_ALU | BPF_MOD | BPF_X: /* dst = (u32) dst % (u32) src */
577 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;
579 jit->seen |= SEEN_RET0;
580 /* ltr %src,%src (if src == 0 goto fail) */
581 EMIT2(0x1200, src_reg, src_reg);
583 EMIT4_PCREL(0xa7840000, jit->ret0_ip - jit->prg);
585 EMIT4_IMM(0xa7080000, REG_W0, 0);
587 EMIT2(0x1800, REG_W1, dst_reg);
589 EMIT4(0xb9970000, REG_W0, src_reg);
591 EMIT4(0xb9160000, dst_reg, rc_reg);
594 case BPF_ALU64 | BPF_DIV | BPF_X: /* dst = dst / src */
595 case BPF_ALU64 | BPF_MOD | BPF_X: /* dst = dst % src */
597 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;
599 jit->seen |= SEEN_RET0;
600 /* ltgr %src,%src (if src == 0 goto fail) */
601 EMIT4(0xb9020000, src_reg, src_reg);
603 EMIT4_PCREL(0xa7840000, jit->ret0_ip - jit->prg);
605 EMIT4_IMM(0xa7090000, REG_W0, 0);
607 EMIT4(0xb9040000, REG_W1, dst_reg);
609 EMIT4(0xb9870000, REG_W0, src_reg);
611 EMIT4(0xb9040000, dst_reg, rc_reg);
614 case BPF_ALU | BPF_DIV | BPF_K: /* dst = (u32) dst / (u32) imm */
615 case BPF_ALU | BPF_MOD | BPF_K: /* dst = (u32) dst % (u32) imm */
617 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;
620 if (BPF_OP(insn->code) == BPF_MOD)
622 EMIT4_IMM(0xa7090000, dst_reg, 0);
626 EMIT4_IMM(0xa7080000, REG_W0, 0);
628 EMIT2(0x1800, REG_W1, dst_reg);
629 /* dl %w0,<d(imm)>(%l) */
630 EMIT6_DISP_LH(0xe3000000, 0x0097, REG_W0, REG_0, REG_L,
631 EMIT_CONST_U32(imm));
633 EMIT4(0xb9160000, dst_reg, rc_reg);
636 case BPF_ALU64 | BPF_DIV | BPF_K: /* dst = dst / imm */
637 case BPF_ALU64 | BPF_MOD | BPF_K: /* dst = dst % imm */
639 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;
642 if (BPF_OP(insn->code) == BPF_MOD)
644 EMIT4_IMM(0xa7090000, dst_reg, 0);
648 EMIT4_IMM(0xa7090000, REG_W0, 0);
650 EMIT4(0xb9040000, REG_W1, dst_reg);
651 /* dlg %w0,<d(imm)>(%l) */
652 EMIT6_DISP_LH(0xe3000000, 0x0087, REG_W0, REG_0, REG_L,
653 EMIT_CONST_U64(imm));
655 EMIT4(0xb9040000, dst_reg, rc_reg);
661 case BPF_ALU | BPF_AND | BPF_X: /* dst = (u32) dst & (u32) src */
663 EMIT2(0x1400, dst_reg, src_reg);
666 case BPF_ALU64 | BPF_AND | BPF_X: /* dst = dst & src */
668 EMIT4(0xb9800000, dst_reg, src_reg);
670 case BPF_ALU | BPF_AND | BPF_K: /* dst = (u32) dst & (u32) imm */
672 EMIT6_IMM(0xc00b0000, dst_reg, imm);
675 case BPF_ALU64 | BPF_AND | BPF_K: /* dst = dst & imm */
676 /* ng %dst,<d(imm)>(%l) */
677 EMIT6_DISP_LH(0xe3000000, 0x0080, dst_reg, REG_0, REG_L,
678 EMIT_CONST_U64(imm));
683 case BPF_ALU | BPF_OR | BPF_X: /* dst = (u32) dst | (u32) src */
685 EMIT2(0x1600, dst_reg, src_reg);
688 case BPF_ALU64 | BPF_OR | BPF_X: /* dst = dst | src */
690 EMIT4(0xb9810000, dst_reg, src_reg);
692 case BPF_ALU | BPF_OR | BPF_K: /* dst = (u32) dst | (u32) imm */
694 EMIT6_IMM(0xc00d0000, dst_reg, imm);
697 case BPF_ALU64 | BPF_OR | BPF_K: /* dst = dst | imm */
698 /* og %dst,<d(imm)>(%l) */
699 EMIT6_DISP_LH(0xe3000000, 0x0081, dst_reg, REG_0, REG_L,
700 EMIT_CONST_U64(imm));
705 case BPF_ALU | BPF_XOR | BPF_X: /* dst = (u32) dst ^ (u32) src */
707 EMIT2(0x1700, dst_reg, src_reg);
710 case BPF_ALU64 | BPF_XOR | BPF_X: /* dst = dst ^ src */
712 EMIT4(0xb9820000, dst_reg, src_reg);
714 case BPF_ALU | BPF_XOR | BPF_K: /* dst = (u32) dst ^ (u32) imm */
718 EMIT6_IMM(0xc0070000, dst_reg, imm);
721 case BPF_ALU64 | BPF_XOR | BPF_K: /* dst = dst ^ imm */
722 /* xg %dst,<d(imm)>(%l) */
723 EMIT6_DISP_LH(0xe3000000, 0x0082, dst_reg, REG_0, REG_L,
724 EMIT_CONST_U64(imm));
729 case BPF_ALU | BPF_LSH | BPF_X: /* dst = (u32) dst << (u32) src */
730 /* sll %dst,0(%src) */
731 EMIT4_DISP(0x89000000, dst_reg, src_reg, 0);
734 case BPF_ALU64 | BPF_LSH | BPF_X: /* dst = dst << src */
735 /* sllg %dst,%dst,0(%src) */
736 EMIT6_DISP_LH(0xeb000000, 0x000d, dst_reg, dst_reg, src_reg, 0);
738 case BPF_ALU | BPF_LSH | BPF_K: /* dst = (u32) dst << (u32) imm */
741 /* sll %dst,imm(%r0) */
742 EMIT4_DISP(0x89000000, dst_reg, REG_0, imm);
745 case BPF_ALU64 | BPF_LSH | BPF_K: /* dst = dst << imm */
748 /* sllg %dst,%dst,imm(%r0) */
749 EMIT6_DISP_LH(0xeb000000, 0x000d, dst_reg, dst_reg, REG_0, imm);
754 case BPF_ALU | BPF_RSH | BPF_X: /* dst = (u32) dst >> (u32) src */
755 /* srl %dst,0(%src) */
756 EMIT4_DISP(0x88000000, dst_reg, src_reg, 0);
759 case BPF_ALU64 | BPF_RSH | BPF_X: /* dst = dst >> src */
760 /* srlg %dst,%dst,0(%src) */
761 EMIT6_DISP_LH(0xeb000000, 0x000c, dst_reg, dst_reg, src_reg, 0);
763 case BPF_ALU | BPF_RSH | BPF_K: /* dst = (u32) dst >> (u32) imm */
766 /* srl %dst,imm(%r0) */
767 EMIT4_DISP(0x88000000, dst_reg, REG_0, imm);
770 case BPF_ALU64 | BPF_RSH | BPF_K: /* dst = dst >> imm */
773 /* srlg %dst,%dst,imm(%r0) */
774 EMIT6_DISP_LH(0xeb000000, 0x000c, dst_reg, dst_reg, REG_0, imm);
779 case BPF_ALU64 | BPF_ARSH | BPF_X: /* ((s64) dst) >>= src */
780 /* srag %dst,%dst,0(%src) */
781 EMIT6_DISP_LH(0xeb000000, 0x000a, dst_reg, dst_reg, src_reg, 0);
783 case BPF_ALU64 | BPF_ARSH | BPF_K: /* ((s64) dst) >>= imm */
786 /* srag %dst,%dst,imm(%r0) */
787 EMIT6_DISP_LH(0xeb000000, 0x000a, dst_reg, dst_reg, REG_0, imm);
792 case BPF_ALU | BPF_NEG: /* dst = (u32) -dst */
794 EMIT2(0x1300, dst_reg, dst_reg);
797 case BPF_ALU64 | BPF_NEG: /* dst = -dst */
799 EMIT4(0xb9130000, dst_reg, dst_reg);
804 case BPF_ALU | BPF_END | BPF_FROM_BE:
805 /* s390 is big endian, therefore only clear high order bytes */
807 case 16: /* dst = (u16) cpu_to_be16(dst) */
808 /* llghr %dst,%dst */
809 EMIT4(0xb9850000, dst_reg, dst_reg);
811 case 32: /* dst = (u32) cpu_to_be32(dst) */
812 /* llgfr %dst,%dst */
813 EMIT4(0xb9160000, dst_reg, dst_reg);
815 case 64: /* dst = (u64) cpu_to_be64(dst) */
819 case BPF_ALU | BPF_END | BPF_FROM_LE:
821 case 16: /* dst = (u16) cpu_to_le16(dst) */
823 EMIT4(0xb91f0000, dst_reg, dst_reg);
824 /* srl %dst,16(%r0) */
825 EMIT4_DISP(0x88000000, dst_reg, REG_0, 16);
826 /* llghr %dst,%dst */
827 EMIT4(0xb9850000, dst_reg, dst_reg);
829 case 32: /* dst = (u32) cpu_to_le32(dst) */
831 EMIT4(0xb91f0000, dst_reg, dst_reg);
832 /* llgfr %dst,%dst */
833 EMIT4(0xb9160000, dst_reg, dst_reg);
835 case 64: /* dst = (u64) cpu_to_le64(dst) */
836 /* lrvgr %dst,%dst */
837 EMIT4(0xb90f0000, dst_reg, dst_reg);
844 case BPF_STX | BPF_MEM | BPF_B: /* *(u8 *)(dst + off) = src_reg */
845 /* stcy %src,off(%dst) */
846 EMIT6_DISP_LH(0xe3000000, 0x0072, src_reg, dst_reg, REG_0, off);
847 jit->seen |= SEEN_MEM;
849 case BPF_STX | BPF_MEM | BPF_H: /* (u16 *)(dst + off) = src */
850 /* sthy %src,off(%dst) */
851 EMIT6_DISP_LH(0xe3000000, 0x0070, src_reg, dst_reg, REG_0, off);
852 jit->seen |= SEEN_MEM;
854 case BPF_STX | BPF_MEM | BPF_W: /* *(u32 *)(dst + off) = src */
855 /* sty %src,off(%dst) */
856 EMIT6_DISP_LH(0xe3000000, 0x0050, src_reg, dst_reg, REG_0, off);
857 jit->seen |= SEEN_MEM;
859 case BPF_STX | BPF_MEM | BPF_DW: /* (u64 *)(dst + off) = src */
860 /* stg %src,off(%dst) */
861 EMIT6_DISP_LH(0xe3000000, 0x0024, src_reg, dst_reg, REG_0, off);
862 jit->seen |= SEEN_MEM;
864 case BPF_ST | BPF_MEM | BPF_B: /* *(u8 *)(dst + off) = imm */
866 EMIT4_IMM(0xa7080000, REG_W0, (u8) imm);
867 /* stcy %w0,off(dst) */
868 EMIT6_DISP_LH(0xe3000000, 0x0072, REG_W0, dst_reg, REG_0, off);
869 jit->seen |= SEEN_MEM;
871 case BPF_ST | BPF_MEM | BPF_H: /* (u16 *)(dst + off) = imm */
873 EMIT4_IMM(0xa7080000, REG_W0, (u16) imm);
874 /* sthy %w0,off(dst) */
875 EMIT6_DISP_LH(0xe3000000, 0x0070, REG_W0, dst_reg, REG_0, off);
876 jit->seen |= SEEN_MEM;
878 case BPF_ST | BPF_MEM | BPF_W: /* *(u32 *)(dst + off) = imm */
880 EMIT6_IMM(0xc00f0000, REG_W0, (u32) imm);
881 /* sty %w0,off(%dst) */
882 EMIT6_DISP_LH(0xe3000000, 0x0050, REG_W0, dst_reg, REG_0, off);
883 jit->seen |= SEEN_MEM;
885 case BPF_ST | BPF_MEM | BPF_DW: /* *(u64 *)(dst + off) = imm */
887 EMIT6_IMM(0xc0010000, REG_W0, imm);
888 /* stg %w0,off(%dst) */
889 EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W0, dst_reg, REG_0, off);
890 jit->seen |= SEEN_MEM;
893 * BPF_STX XADD (atomic_add)
895 case BPF_STX | BPF_XADD | BPF_W: /* *(u32 *)(dst + off) += src */
896 /* laal %w0,%src,off(%dst) */
897 EMIT6_DISP_LH(0xeb000000, 0x00fa, REG_W0, src_reg,
899 jit->seen |= SEEN_MEM;
901 case BPF_STX | BPF_XADD | BPF_DW: /* *(u64 *)(dst + off) += src */
902 /* laalg %w0,%src,off(%dst) */
903 EMIT6_DISP_LH(0xeb000000, 0x00ea, REG_W0, src_reg,
905 jit->seen |= SEEN_MEM;
910 case BPF_LDX | BPF_MEM | BPF_B: /* dst = *(u8 *)(ul) (src + off) */
911 /* llgc %dst,0(off,%src) */
912 EMIT6_DISP_LH(0xe3000000, 0x0090, dst_reg, src_reg, REG_0, off);
913 jit->seen |= SEEN_MEM;
915 case BPF_LDX | BPF_MEM | BPF_H: /* dst = *(u16 *)(ul) (src + off) */
916 /* llgh %dst,0(off,%src) */
917 EMIT6_DISP_LH(0xe3000000, 0x0091, dst_reg, src_reg, REG_0, off);
918 jit->seen |= SEEN_MEM;
920 case BPF_LDX | BPF_MEM | BPF_W: /* dst = *(u32 *)(ul) (src + off) */
921 /* llgf %dst,off(%src) */
922 jit->seen |= SEEN_MEM;
923 EMIT6_DISP_LH(0xe3000000, 0x0016, dst_reg, src_reg, REG_0, off);
925 case BPF_LDX | BPF_MEM | BPF_DW: /* dst = *(u64 *)(ul) (src + off) */
926 /* lg %dst,0(off,%src) */
927 jit->seen |= SEEN_MEM;
928 EMIT6_DISP_LH(0xe3000000, 0x0004, dst_reg, src_reg, REG_0, off);
933 case BPF_JMP | BPF_CALL:
936 * b0 = (__bpf_call_base + imm)(b1, b2, b3, b4, b5)
938 const u64 func = (u64)__bpf_call_base + imm;
940 REG_SET_SEEN(BPF_REG_5);
941 jit->seen |= SEEN_FUNC;
942 /* lg %w1,<d(imm)>(%l) */
943 EMIT6_DISP(0xe3000000, 0x0004, REG_W1, REG_0, REG_L,
944 EMIT_CONST_U64(func));
946 EMIT2(0x0d00, REG_14, REG_W1);
947 /* lgr %b0,%r2: load return value into %b0 */
948 EMIT4(0xb9040000, BPF_REG_0, REG_2);
951 case BPF_JMP | BPF_EXIT: /* return b0 */
952 last = (i == fp->len - 1) ? 1 : 0;
953 if (last && !(jit->seen & SEEN_RET0))
956 EMIT4_PCREL(0xa7f40000, jit->exit_ip - jit->prg);
959 * Branch relative (number of skipped instructions) to offset on
962 * Condition code to mask mapping:
964 * CC | Description | Mask
965 * ------------------------------
966 * 0 | Operands equal | 8
967 * 1 | First operand low | 4
968 * 2 | First operand high | 2
971 * For s390x relative branches: ip = ip + off_bytes
972 * For BPF relative branches: insn = insn + off_insns + 1
974 * For example for s390x with offset 0 we jump to the branch
975 * instruction itself (loop) and for BPF with offset 0 we
976 * branch to the instruction behind the branch.
978 case BPF_JMP | BPF_JA: /* if (true) */
979 mask = 0xf000; /* j */
981 case BPF_JMP | BPF_JSGT | BPF_K: /* ((s64) dst > (s64) imm) */
982 mask = 0x2000; /* jh */
984 case BPF_JMP | BPF_JSGE | BPF_K: /* ((s64) dst >= (s64) imm) */
985 mask = 0xa000; /* jhe */
987 case BPF_JMP | BPF_JGT | BPF_K: /* (dst_reg > imm) */
988 mask = 0x2000; /* jh */
990 case BPF_JMP | BPF_JGE | BPF_K: /* (dst_reg >= imm) */
991 mask = 0xa000; /* jhe */
993 case BPF_JMP | BPF_JNE | BPF_K: /* (dst_reg != imm) */
994 mask = 0x7000; /* jne */
996 case BPF_JMP | BPF_JEQ | BPF_K: /* (dst_reg == imm) */
997 mask = 0x8000; /* je */
999 case BPF_JMP | BPF_JSET | BPF_K: /* (dst_reg & imm) */
1000 mask = 0x7000; /* jnz */
1001 /* lgfi %w1,imm (load sign extend imm) */
1002 EMIT6_IMM(0xc0010000, REG_W1, imm);
1004 EMIT4(0xb9800000, REG_W1, dst_reg);
1007 case BPF_JMP | BPF_JSGT | BPF_X: /* ((s64) dst > (s64) src) */
1008 mask = 0x2000; /* jh */
1010 case BPF_JMP | BPF_JSGE | BPF_X: /* ((s64) dst >= (s64) src) */
1011 mask = 0xa000; /* jhe */
1013 case BPF_JMP | BPF_JGT | BPF_X: /* (dst > src) */
1014 mask = 0x2000; /* jh */
1016 case BPF_JMP | BPF_JGE | BPF_X: /* (dst >= src) */
1017 mask = 0xa000; /* jhe */
1019 case BPF_JMP | BPF_JNE | BPF_X: /* (dst != src) */
1020 mask = 0x7000; /* jne */
1022 case BPF_JMP | BPF_JEQ | BPF_X: /* (dst == src) */
1023 mask = 0x8000; /* je */
1025 case BPF_JMP | BPF_JSET | BPF_X: /* (dst & src) */
1026 mask = 0x7000; /* jnz */
1027 /* ngrk %w1,%dst,%src */
1028 EMIT4_RRF(0xb9e40000, REG_W1, dst_reg, src_reg);
1031 /* lgfi %w1,imm (load sign extend imm) */
1032 EMIT6_IMM(0xc0010000, REG_W1, imm);
1033 /* cgrj %dst,%w1,mask,off */
1034 EMIT6_PCREL(0xec000000, 0x0064, dst_reg, REG_W1, i, off, mask);
1037 /* lgfi %w1,imm (load sign extend imm) */
1038 EMIT6_IMM(0xc0010000, REG_W1, imm);
1039 /* clgrj %dst,%w1,mask,off */
1040 EMIT6_PCREL(0xec000000, 0x0065, dst_reg, REG_W1, i, off, mask);
1043 /* cgrj %dst,%src,mask,off */
1044 EMIT6_PCREL(0xec000000, 0x0064, dst_reg, src_reg, i, off, mask);
1047 /* clgrj %dst,%src,mask,off */
1048 EMIT6_PCREL(0xec000000, 0x0065, dst_reg, src_reg, i, off, mask);
1051 /* brc mask,jmp_off (branch instruction needs 4 bytes) */
1052 jmp_off = addrs[i + off + 1] - (addrs[i + 1] - 4);
1053 EMIT4_PCREL(0xa7040000 | mask << 8, jmp_off);
1058 case BPF_LD | BPF_ABS | BPF_B: /* b0 = *(u8 *) (skb->data+imm) */
1059 case BPF_LD | BPF_IND | BPF_B: /* b0 = *(u8 *) (skb->data+imm+src) */
1060 if ((BPF_MODE(insn->code) == BPF_ABS) && (imm >= 0))
1061 func_addr = __pa(sk_load_byte_pos);
1063 func_addr = __pa(sk_load_byte);
1065 case BPF_LD | BPF_ABS | BPF_H: /* b0 = *(u16 *) (skb->data+imm) */
1066 case BPF_LD | BPF_IND | BPF_H: /* b0 = *(u16 *) (skb->data+imm+src) */
1067 if ((BPF_MODE(insn->code) == BPF_ABS) && (imm >= 0))
1068 func_addr = __pa(sk_load_half_pos);
1070 func_addr = __pa(sk_load_half);
1072 case BPF_LD | BPF_ABS | BPF_W: /* b0 = *(u32 *) (skb->data+imm) */
1073 case BPF_LD | BPF_IND | BPF_W: /* b0 = *(u32 *) (skb->data+imm+src) */
1074 if ((BPF_MODE(insn->code) == BPF_ABS) && (imm >= 0))
1075 func_addr = __pa(sk_load_word_pos);
1077 func_addr = __pa(sk_load_word);
1080 jit->seen |= SEEN_SKB | SEEN_RET0 | SEEN_FUNC;
1081 REG_SET_SEEN(REG_14); /* Return address of possible func call */
1085 * BPF_REG_6 (R7) : skb pointer
1086 * REG_SKB_DATA (R12): skb data pointer
1089 * BPF_REG_2 (R3) : offset of byte(s) to fetch in skb
1090 * BPF_REG_5 (R6) : return address
1093 * BPF_REG_0 (R14): data read from skb
1095 * Scratch registers (BPF_REG_1-5)
1098 /* Call function: llilf %w1,func_addr */
1099 EMIT6_IMM(0xc00f0000, REG_W1, func_addr);
1101 /* Offset: lgfi %b2,imm */
1102 EMIT6_IMM(0xc0010000, BPF_REG_2, imm);
1103 if (BPF_MODE(insn->code) == BPF_IND)
1104 /* agfr %b2,%src (%src is s32 here) */
1105 EMIT4(0xb9180000, BPF_REG_2, src_reg);
1107 /* basr %b5,%w1 (%b5 is call saved) */
1108 EMIT2(0x0d00, BPF_REG_5, REG_W1);
1111 * Note: For fast access we jump directly after the
1112 * jnz instruction from bpf_jit.S
1115 EMIT4_PCREL(0xa7740000, jit->ret0_ip - jit->prg);
1117 default: /* too complex, give up */
1118 pr_err("Unknown opcode %02x\n", insn->code);
1125 * Compile eBPF program into s390x code
1127 static int bpf_jit_prog(struct bpf_jit *jit, struct bpf_prog *fp)
1131 jit->lit = jit->lit_start;
1134 bpf_jit_prologue(jit);
1135 for (i = 0; i < fp->len; i += insn_count) {
1136 insn_count = bpf_jit_insn(jit, fp, i);
1139 jit->addrs[i + 1] = jit->prg; /* Next instruction address */
1141 bpf_jit_epilogue(jit);
1143 jit->lit_start = jit->prg;
1144 jit->size = jit->lit;
1145 jit->size_prg = jit->prg;
1150 * Classic BPF function stub. BPF programs will be converted into
1151 * eBPF and then bpf_int_jit_compile() will be called.
1153 void bpf_jit_compile(struct bpf_prog *fp)
1158 * Compile eBPF program "fp"
1160 void bpf_int_jit_compile(struct bpf_prog *fp)
1162 struct bpf_binary_header *header;
1166 if (!bpf_jit_enable)
1168 memset(&jit, 0, sizeof(jit));
1169 jit.addrs = kcalloc(fp->len + 1, sizeof(*jit.addrs), GFP_KERNEL);
1170 if (jit.addrs == NULL)
1173 * Three initial passes:
1174 * - 1/2: Determine clobbered registers
1175 * - 3: Calculate program size and addrs arrray
1177 for (pass = 1; pass <= 3; pass++) {
1178 if (bpf_jit_prog(&jit, fp))
1182 * Final pass: Allocate and generate program
1184 if (jit.size >= BPF_SIZE_MAX)
1186 header = bpf_jit_binary_alloc(jit.size, &jit.prg_buf, 2, jit_fill_hole);
1189 if (bpf_jit_prog(&jit, fp))
1191 if (bpf_jit_enable > 1) {
1192 bpf_jit_dump(fp->len, jit.size, pass, jit.prg_buf);
1194 print_fn_code(jit.prg_buf, jit.size_prg);
1197 set_memory_ro((unsigned long)header, header->pages);
1198 fp->bpf_func = (void *) jit.prg_buf;
1208 void bpf_jit_free(struct bpf_prog *fp)
1210 unsigned long addr = (unsigned long)fp->bpf_func & PAGE_MASK;
1211 struct bpf_binary_header *header = (void *)addr;
1216 set_memory_rw(addr, header->pages);
1217 bpf_jit_binary_free(header);
1220 bpf_prog_unlock_free(fp);