arch/x86/kernel/cpu/centaur.c

   1
   2 #include <linux/sched.h>
   3 #include <linux/sched/clock.h>
   4
   5 #include <asm/cpufeature.h>
   6 #include <asm/e820.h>
   7 #include <asm/mtrr.h>
   8 #include <asm/msr.h>
   9
  10 #include "cpu.h"
  11
  12 #define ACE_PRESENT     (1 << 6)
  13 #define ACE_ENABLED     (1 << 7)
  14 #define ACE_FCR         (1 << 28)       /* MSR_VIA_FCR */
  15
  16 #define RNG_PRESENT     (1 << 2)
  17 #define RNG_ENABLED     (1 << 3)
  18 #define RNG_ENABLE      (1 << 6)        /* MSR_VIA_RNG */
  19
  20 static void init_c3(struct cpuinfo_x86 *c)
  21 {
  22         u32  lo, hi;
  23
  24         /* Test for Centaur Extended Feature Flags presence */
  25         if (cpuid_eax(0xC0000000) >= 0xC0000001) {
  26                 u32 tmp = cpuid_edx(0xC0000001);
  27
  28                 /* enable ACE unit, if present and disabled */
  29                 if ((tmp & (ACE_PRESENT | ACE_ENABLED)) == ACE_PRESENT) {
  30                         rdmsr(MSR_VIA_FCR, lo, hi);
  31                         lo |= ACE_FCR;          /* enable ACE unit */
  32                         wrmsr(MSR_VIA_FCR, lo, hi);
  33                         pr_info("CPU: Enabled ACE h/w crypto\n");
  34                 }
  35
  36                 /* enable RNG unit, if present and disabled */
  37                 if ((tmp & (RNG_PRESENT | RNG_ENABLED)) == RNG_PRESENT) {
  38                         rdmsr(MSR_VIA_RNG, lo, hi);
  39                         lo |= RNG_ENABLE;       /* enable RNG unit */
  40                         wrmsr(MSR_VIA_RNG, lo, hi);
  41                         pr_info("CPU: Enabled h/w RNG\n");
  42                 }
  43
  44                 /* store Centaur Extended Feature Flags as
  45                  * word 5 of the CPU capability bit array
  46                  */
  47                 c->x86_capability[CPUID_C000_0001_EDX] = cpuid_edx(0xC0000001);
  48         }
  49 #ifdef CONFIG_X86_32
  50         /* Cyrix III family needs CX8 & PGE explicitly enabled. */
  51         if (c->x86_model >= 6 && c->x86_model <= 13) {
  52                 rdmsr(MSR_VIA_FCR, lo, hi);
  53                 lo |= (1<<1 | 1<<7);
  54                 wrmsr(MSR_VIA_FCR, lo, hi);
  55                 set_cpu_cap(c, X86_FEATURE_CX8);
  56         }
  57
  58         /* Before Nehemiah, the C3's had 3dNOW! */
  59         if (c->x86_model >= 6 && c->x86_model < 9)
  60                 set_cpu_cap(c, X86_FEATURE_3DNOW);
  61 #endif
  62         if (c->x86 == 0x6 && c->x86_model >= 0xf) {
  63                 c->x86_cache_alignment = c->x86_clflush_size * 2;
  64                 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
  65         }
  66
  67         cpu_detect_cache_sizes(c);
  68 }
  69
  70 enum {
  71                 ECX8            = 1<<1,
  72                 EIERRINT        = 1<<2,
  73                 DPM             = 1<<3,
  74                 DMCE            = 1<<4,
  75                 DSTPCLK         = 1<<5,
  76                 ELINEAR         = 1<<6,
  77                 DSMC            = 1<<7,
  78                 DTLOCK          = 1<<8,
  79                 EDCTLB          = 1<<8,
  80                 EMMX            = 1<<9,
  81                 DPDC            = 1<<11,
  82                 EBRPRED         = 1<<12,
  83                 DIC             = 1<<13,
  84                 DDC             = 1<<14,
  85                 DNA             = 1<<15,
  86                 ERETSTK         = 1<<16,
  87                 E2MMX           = 1<<19,
  88                 EAMD3D          = 1<<20,
  89 };
  90
  91 static void early_init_centaur(struct cpuinfo_x86 *c)
  92 {
  93         switch (c->x86) {
  94 #ifdef CONFIG_X86_32
  95         case 5:
  96                 /* Emulate MTRRs using Centaur's MCR. */
  97                 set_cpu_cap(c, X86_FEATURE_CENTAUR_MCR);
  98                 break;
  99 #endif
 100         case 6:
 101                 if (c->x86_model >= 0xf)
 102                         set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
 103                 break;
 104         }
 105 #ifdef CONFIG_X86_64
 106         set_cpu_cap(c, X86_FEATURE_SYSENTER32);
 107 #endif
 108
 109         clear_sched_clock_stable();
 110 }
 111
 112 static void init_centaur(struct cpuinfo_x86 *c)
 113 {
 114 #ifdef CONFIG_X86_32
 115         char *name;
 116         u32  fcr_set = 0;
 117         u32  fcr_clr = 0;
 118         u32  lo, hi, newlo;
 119         u32  aa, bb, cc, dd;
 120
 121         /*
 122          * Bit 31 in normal CPUID used for nonstandard 3DNow ID;
 123          * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
 124          */
 125         clear_cpu_cap(c, 0*32+31);
 126 #endif
 127         early_init_centaur(c);
 128         switch (c->x86) {
 129 #ifdef CONFIG_X86_32
 130         case 5:
 131                 switch (c->x86_model) {
 132                 case 4:
 133                         name = "C6";
 134                         fcr_set = ECX8|DSMC|EDCTLB|EMMX|ERETSTK;
 135                         fcr_clr = DPDC;
 136                         pr_notice("Disabling bugged TSC.\n");
 137                         clear_cpu_cap(c, X86_FEATURE_TSC);
 138                         break;
 139                 case 8:
 140                         switch (c->x86_mask) {
 141                         default:
 142                         name = "2";
 143                                 break;
 144                         case 7 ... 9:
 145                                 name = "2A";
 146                                 break;
 147                         case 10 ... 15:
 148                                 name = "2B";
 149                                 break;
 150                         }
 151                         fcr_set = ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK|
 152                                   E2MMX|EAMD3D;
 153                         fcr_clr = DPDC;
 154                         break;
 155                 case 9:
 156                         name = "3";
 157                         fcr_set = ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK|
 158                                   E2MMX|EAMD3D;
 159                         fcr_clr = DPDC;
 160                         break;
 161                 default:
 162                         name = "??";
 163                 }
 164
 165                 rdmsr(MSR_IDT_FCR1, lo, hi);
 166                 newlo = (lo|fcr_set) & (~fcr_clr);
 167
 168                 if (newlo != lo) {
 169                         pr_info("Centaur FCR was 0x%X now 0x%X\n",
 170                                 lo, newlo);
 171                         wrmsr(MSR_IDT_FCR1, newlo, hi);
 172                 } else {
 173                         pr_info("Centaur FCR is 0x%X\n", lo);
 174                 }
 175                 /* Emulate MTRRs using Centaur's MCR. */
 176                 set_cpu_cap(c, X86_FEATURE_CENTAUR_MCR);
 177                 /* Report CX8 */
 178                 set_cpu_cap(c, X86_FEATURE_CX8);
 179                 /* Set 3DNow! on Winchip 2 and above. */
 180                 if (c->x86_model >= 8)
 181                         set_cpu_cap(c, X86_FEATURE_3DNOW);
 182                 /* See if we can find out some more. */
 183                 if (cpuid_eax(0x80000000) >= 0x80000005) {
 184                         /* Yes, we can. */
 185                         cpuid(0x80000005, &aa, &bb, &cc, &dd);
 186                         /* Add L1 data and code cache sizes. */
 187                         c->x86_cache_size = (cc>>24)+(dd>>24);
 188                 }
 189                 sprintf(c->x86_model_id, "WinChip %s", name);
 190                 break;
 191 #endif
 192         case 6:
 193                 init_c3(c);
 194                 break;
 195         }
 196 #ifdef CONFIG_X86_64
 197         set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
 198 #endif
 199 }
 200
 201 #ifdef CONFIG_X86_32
 202 static unsigned int
 203 centaur_size_cache(struct cpuinfo_x86 *c, unsigned int size)
 204 {
 205         /* VIA C3 CPUs (670-68F) need further shifting. */
 206         if ((c->x86 == 6) && ((c->x86_model == 7) || (c->x86_model == 8)))
 207                 size >>= 8;
 208
 209         /*
 210          * There's also an erratum in Nehemiah stepping 1, which
 211          * returns '65KB' instead of '64KB'
 212          *  - Note, it seems this may only be in engineering samples.
 213          */
 214         if ((c->x86 == 6) && (c->x86_model == 9) &&
 215                                 (c->x86_mask == 1) && (size == 65))
 216                 size -= 1;
 217         return size;
 218 }
 219 #endif
 220
 221 static const struct cpu_dev centaur_cpu_dev = {
 222         .c_vendor       = "Centaur",
 223         .c_ident        = { "CentaurHauls" },
 224         .c_early_init   = early_init_centaur,
 225         .c_init         = init_centaur,
 226 #ifdef CONFIG_X86_32
 227         .legacy_cache_size = centaur_size_cache,
 228 #endif
 229         .c_x86_vendor   = X86_VENDOR_CENTAUR,
 230 };
 231
 232 cpu_dev_register(centaur_cpu_dev);