2 * Machine check handler.
4 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
5 * Rest from unknown author(s).
6 * 2004 Andi Kleen. Rewrote most of it.
7 * Copyright 2008 Intel Corporation
10 #include <linux/thread_info.h>
11 #include <linux/capability.h>
12 #include <linux/miscdevice.h>
13 #include <linux/interrupt.h>
14 #include <linux/ratelimit.h>
15 #include <linux/kallsyms.h>
16 #include <linux/rcupdate.h>
17 #include <linux/kobject.h>
18 #include <linux/uaccess.h>
19 #include <linux/kdebug.h>
20 #include <linux/kernel.h>
21 #include <linux/percpu.h>
22 #include <linux/string.h>
23 #include <linux/sysdev.h>
24 #include <linux/syscore_ops.h>
25 #include <linux/delay.h>
26 #include <linux/ctype.h>
27 #include <linux/sched.h>
28 #include <linux/sysfs.h>
29 #include <linux/types.h>
30 #include <linux/slab.h>
31 #include <linux/init.h>
32 #include <linux/kmod.h>
33 #include <linux/poll.h>
34 #include <linux/nmi.h>
35 #include <linux/cpu.h>
36 #include <linux/smp.h>
39 #include <linux/debugfs.h>
41 #include <asm/processor.h>
42 #include <asm/hw_irq.h>
49 #include "mce-internal.h"
51 static DEFINE_MUTEX(mce_read_mutex);
53 #define rcu_dereference_check_mce(p) \
54 rcu_dereference_index_check((p), \
55 rcu_read_lock_sched_held() || \
56 lockdep_is_held(&mce_read_mutex))
58 #define CREATE_TRACE_POINTS
59 #include <trace/events/mce.h>
61 int mce_disabled __read_mostly;
63 #define MISC_MCELOG_MINOR 227
65 #define SPINUNIT 100 /* 100ns */
69 DEFINE_PER_CPU(unsigned, mce_exception_count);
73 * 0: always panic on uncorrected errors, log corrected errors
74 * 1: panic or SIGBUS on uncorrected errors, log corrected errors
75 * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors
76 * 3: never panic or SIGBUS, log all errors (for testing only)
78 static int tolerant __read_mostly = 1;
79 static int banks __read_mostly;
80 static int rip_msr __read_mostly;
81 static int mce_bootlog __read_mostly = -1;
82 static int monarch_timeout __read_mostly = -1;
83 static int mce_panic_timeout __read_mostly;
84 static int mce_dont_log_ce __read_mostly;
85 int mce_cmci_disabled __read_mostly;
86 int mce_ignore_ce __read_mostly;
87 int mce_ser __read_mostly;
89 struct mce_bank *mce_banks __read_mostly;
91 /* User mode helper program triggered by machine check event */
92 static unsigned long mce_need_notify;
93 static char mce_helper[128];
94 static char *mce_helper_argv[2] = { mce_helper, NULL };
96 static DECLARE_WAIT_QUEUE_HEAD(mce_wait);
97 static DEFINE_PER_CPU(struct mce, mces_seen);
98 static int cpu_missing;
101 * CPU/chipset specific EDAC code can register a notifier call here to print
102 * MCE errors in a human-readable form.
104 ATOMIC_NOTIFIER_HEAD(x86_mce_decoder_chain);
105 EXPORT_SYMBOL_GPL(x86_mce_decoder_chain);
107 /* MCA banks polled by the period polling timer for corrected events */
108 DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = {
109 [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL
112 static DEFINE_PER_CPU(struct work_struct, mce_work);
114 /* Do initial initialization of a struct mce */
115 void mce_setup(struct mce *m)
117 memset(m, 0, sizeof(struct mce));
118 m->cpu = m->extcpu = smp_processor_id();
120 /* We hope get_seconds stays lockless */
121 m->time = get_seconds();
122 m->cpuvendor = boot_cpu_data.x86_vendor;
123 m->cpuid = cpuid_eax(1);
125 m->socketid = cpu_data(m->extcpu).phys_proc_id;
127 m->apicid = cpu_data(m->extcpu).initial_apicid;
128 rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap);
131 DEFINE_PER_CPU(struct mce, injectm);
132 EXPORT_PER_CPU_SYMBOL_GPL(injectm);
135 * Lockless MCE logging infrastructure.
136 * This avoids deadlocks on printk locks without having to break locks. Also
137 * separate MCEs from kernel messages to avoid bogus bug reports.
140 static struct mce_log mcelog = {
141 .signature = MCE_LOG_SIGNATURE,
143 .recordlen = sizeof(struct mce),
146 void mce_log(struct mce *mce)
148 unsigned next, entry;
151 /* Emit the trace record: */
152 trace_mce_record(mce);
154 ret = atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, mce);
155 if (ret == NOTIFY_STOP)
161 entry = rcu_dereference_check_mce(mcelog.next);
165 * When the buffer fills up discard new entries.
166 * Assume that the earlier errors are the more
169 if (entry >= MCE_LOG_LEN) {
170 set_bit(MCE_OVERFLOW,
171 (unsigned long *)&mcelog.flags);
174 /* Old left over entry. Skip: */
175 if (mcelog.entry[entry].finished) {
183 if (cmpxchg(&mcelog.next, entry, next) == entry)
186 memcpy(mcelog.entry + entry, mce, sizeof(struct mce));
188 mcelog.entry[entry].finished = 1;
192 set_bit(0, &mce_need_notify);
195 static void print_mce(struct mce *m)
199 pr_emerg(HW_ERR "CPU %d: Machine Check Exception: %Lx Bank %d: %016Lx\n",
200 m->extcpu, m->mcgstatus, m->bank, m->status);
203 pr_emerg(HW_ERR "RIP%s %02x:<%016Lx> ",
204 !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "",
207 if (m->cs == __KERNEL_CS)
208 print_symbol("{%s}", m->ip);
212 pr_emerg(HW_ERR "TSC %llx ", m->tsc);
214 pr_cont("ADDR %llx ", m->addr);
216 pr_cont("MISC %llx ", m->misc);
219 pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n",
220 m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid);
223 * Print out human-readable details about the MCE error,
224 * (if the CPU has an implementation for that)
226 ret = atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, m);
227 if (ret == NOTIFY_STOP)
230 pr_emerg_ratelimited(HW_ERR "Run the above through 'mcelog --ascii'\n");
233 #define PANIC_TIMEOUT 5 /* 5 seconds */
235 static atomic_t mce_paniced;
237 static int fake_panic;
238 static atomic_t mce_fake_paniced;
240 /* Panic in progress. Enable interrupts and wait for final IPI */
241 static void wait_for_panic(void)
243 long timeout = PANIC_TIMEOUT*USEC_PER_SEC;
247 while (timeout-- > 0)
249 if (panic_timeout == 0)
250 panic_timeout = mce_panic_timeout;
251 panic("Panicing machine check CPU died");
254 static void mce_panic(char *msg, struct mce *final, char *exp)
260 * Make sure only one CPU runs in machine check panic
262 if (atomic_inc_return(&mce_paniced) > 1)
269 /* Don't log too much for fake panic */
270 if (atomic_inc_return(&mce_fake_paniced) > 1)
273 /* First print corrected ones that are still unlogged */
274 for (i = 0; i < MCE_LOG_LEN; i++) {
275 struct mce *m = &mcelog.entry[i];
276 if (!(m->status & MCI_STATUS_VAL))
278 if (!(m->status & MCI_STATUS_UC)) {
281 apei_err = apei_write_mce(m);
284 /* Now print uncorrected but with the final one last */
285 for (i = 0; i < MCE_LOG_LEN; i++) {
286 struct mce *m = &mcelog.entry[i];
287 if (!(m->status & MCI_STATUS_VAL))
289 if (!(m->status & MCI_STATUS_UC))
291 if (!final || memcmp(m, final, sizeof(struct mce))) {
294 apei_err = apei_write_mce(m);
300 apei_err = apei_write_mce(final);
303 pr_emerg(HW_ERR "Some CPUs didn't answer in synchronization\n");
305 pr_emerg(HW_ERR "Machine check: %s\n", exp);
307 if (panic_timeout == 0)
308 panic_timeout = mce_panic_timeout;
311 pr_emerg(HW_ERR "Fake kernel panic: %s\n", msg);
314 /* Support code for software error injection */
316 static int msr_to_offset(u32 msr)
318 unsigned bank = __this_cpu_read(injectm.bank);
321 return offsetof(struct mce, ip);
322 if (msr == MSR_IA32_MCx_STATUS(bank))
323 return offsetof(struct mce, status);
324 if (msr == MSR_IA32_MCx_ADDR(bank))
325 return offsetof(struct mce, addr);
326 if (msr == MSR_IA32_MCx_MISC(bank))
327 return offsetof(struct mce, misc);
328 if (msr == MSR_IA32_MCG_STATUS)
329 return offsetof(struct mce, mcgstatus);
333 /* MSR access wrappers used for error injection */
334 static u64 mce_rdmsrl(u32 msr)
338 if (__this_cpu_read(injectm.finished)) {
339 int offset = msr_to_offset(msr);
343 return *(u64 *)((char *)&__get_cpu_var(injectm) + offset);
346 if (rdmsrl_safe(msr, &v)) {
347 WARN_ONCE(1, "mce: Unable to read msr %d!\n", msr);
349 * Return zero in case the access faulted. This should
350 * not happen normally but can happen if the CPU does
351 * something weird, or if the code is buggy.
359 static void mce_wrmsrl(u32 msr, u64 v)
361 if (__this_cpu_read(injectm.finished)) {
362 int offset = msr_to_offset(msr);
365 *(u64 *)((char *)&__get_cpu_var(injectm) + offset) = v;
372 * Simple lockless ring to communicate PFNs from the exception handler with the
373 * process context work function. This is vastly simplified because there's
374 * only a single reader and a single writer.
376 #define MCE_RING_SIZE 16 /* we use one entry less */
379 unsigned short start;
381 unsigned long ring[MCE_RING_SIZE];
383 static DEFINE_PER_CPU(struct mce_ring, mce_ring);
385 /* Runs with CPU affinity in workqueue */
386 static int mce_ring_empty(void)
388 struct mce_ring *r = &__get_cpu_var(mce_ring);
390 return r->start == r->end;
393 static int mce_ring_get(unsigned long *pfn)
400 r = &__get_cpu_var(mce_ring);
401 if (r->start == r->end)
403 *pfn = r->ring[r->start];
404 r->start = (r->start + 1) % MCE_RING_SIZE;
411 /* Always runs in MCE context with preempt off */
412 static int mce_ring_add(unsigned long pfn)
414 struct mce_ring *r = &__get_cpu_var(mce_ring);
417 next = (r->end + 1) % MCE_RING_SIZE;
418 if (next == r->start)
420 r->ring[r->end] = pfn;
426 int mce_available(struct cpuinfo_x86 *c)
430 return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA);
433 static void mce_schedule_work(void)
435 if (!mce_ring_empty()) {
436 struct work_struct *work = &__get_cpu_var(mce_work);
437 if (!work_pending(work))
443 * Get the address of the instruction at the time of the machine check
446 static inline void mce_get_rip(struct mce *m, struct pt_regs *regs)
449 if (regs && (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV))) {
457 m->ip = mce_rdmsrl(rip_msr);
460 #ifdef CONFIG_X86_LOCAL_APIC
462 * Called after interrupts have been reenabled again
463 * when a MCE happened during an interrupts off region
466 asmlinkage void smp_mce_self_interrupt(struct pt_regs *regs)
477 static void mce_report_event(struct pt_regs *regs)
479 if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) {
482 * Triggering the work queue here is just an insurance
483 * policy in case the syscall exit notify handler
484 * doesn't run soon enough or ends up running on the
485 * wrong CPU (can happen when audit sleeps)
491 #ifdef CONFIG_X86_LOCAL_APIC
493 * Without APIC do not notify. The event will be picked
500 * When interrupts are disabled we cannot use
501 * kernel services safely. Trigger an self interrupt
502 * through the APIC to instead do the notification
503 * after interrupts are reenabled again.
505 apic->send_IPI_self(MCE_SELF_VECTOR);
508 * Wait for idle afterwards again so that we don't leave the
509 * APIC in a non idle state because the normal APIC writes
512 apic_wait_icr_idle();
516 DEFINE_PER_CPU(unsigned, mce_poll_count);
519 * Poll for corrected events or events that happened before reset.
520 * Those are just logged through /dev/mcelog.
522 * This is executed in standard interrupt context.
524 * Note: spec recommends to panic for fatal unsignalled
525 * errors here. However this would be quite problematic --
526 * we would need to reimplement the Monarch handling and
527 * it would mess up the exclusion between exception handler
528 * and poll hander -- * so we skip this for now.
529 * These cases should not happen anyways, or only when the CPU
530 * is already totally * confused. In this case it's likely it will
531 * not fully execute the machine check handler either.
533 void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
538 percpu_inc(mce_poll_count);
542 m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
543 for (i = 0; i < banks; i++) {
544 if (!mce_banks[i].ctl || !test_bit(i, *b))
553 m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
554 if (!(m.status & MCI_STATUS_VAL))
558 * Uncorrected or signalled events are handled by the exception
559 * handler when it is enabled, so don't process those here.
561 * TBD do the same check for MCI_STATUS_EN here?
563 if (!(flags & MCP_UC) &&
564 (m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)))
567 if (m.status & MCI_STATUS_MISCV)
568 m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i));
569 if (m.status & MCI_STATUS_ADDRV)
570 m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i));
572 if (!(flags & MCP_TIMESTAMP))
575 * Don't get the IP here because it's unlikely to
576 * have anything to do with the actual error location.
578 if (!(flags & MCP_DONTLOG) && !mce_dont_log_ce)
582 * Clear state for this bank.
584 mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
588 * Don't clear MCG_STATUS here because it's only defined for
594 EXPORT_SYMBOL_GPL(machine_check_poll);
597 * Do a quick check if any of the events requires a panic.
598 * This decides if we keep the events around or clear them.
600 static int mce_no_way_out(struct mce *m, char **msg)
604 for (i = 0; i < banks; i++) {
605 m->status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
606 if (mce_severity(m, tolerant, msg) >= MCE_PANIC_SEVERITY)
613 * Variable to establish order between CPUs while scanning.
614 * Each CPU spins initially until executing is equal its number.
616 static atomic_t mce_executing;
619 * Defines order of CPUs on entry. First CPU becomes Monarch.
621 static atomic_t mce_callin;
624 * Check if a timeout waiting for other CPUs happened.
626 static int mce_timed_out(u64 *t)
629 * The others already did panic for some reason.
630 * Bail out like in a timeout.
631 * rmb() to tell the compiler that system_state
632 * might have been modified by someone else.
635 if (atomic_read(&mce_paniced))
637 if (!monarch_timeout)
639 if ((s64)*t < SPINUNIT) {
640 /* CHECKME: Make panic default for 1 too? */
642 mce_panic("Timeout synchronizing machine check over CPUs",
649 touch_nmi_watchdog();
654 * The Monarch's reign. The Monarch is the CPU who entered
655 * the machine check handler first. It waits for the others to
656 * raise the exception too and then grades them. When any
657 * error is fatal panic. Only then let the others continue.
659 * The other CPUs entering the MCE handler will be controlled by the
660 * Monarch. They are called Subjects.
662 * This way we prevent any potential data corruption in a unrecoverable case
663 * and also makes sure always all CPU's errors are examined.
665 * Also this detects the case of a machine check event coming from outer
666 * space (not detected by any CPUs) In this case some external agent wants
667 * us to shut down, so panic too.
669 * The other CPUs might still decide to panic if the handler happens
670 * in a unrecoverable place, but in this case the system is in a semi-stable
671 * state and won't corrupt anything by itself. It's ok to let the others
672 * continue for a bit first.
674 * All the spin loops have timeouts; when a timeout happens a CPU
675 * typically elects itself to be Monarch.
677 static void mce_reign(void)
680 struct mce *m = NULL;
681 int global_worst = 0;
686 * This CPU is the Monarch and the other CPUs have run
687 * through their handlers.
688 * Grade the severity of the errors of all the CPUs.
690 for_each_possible_cpu(cpu) {
691 int severity = mce_severity(&per_cpu(mces_seen, cpu), tolerant,
693 if (severity > global_worst) {
695 global_worst = severity;
696 m = &per_cpu(mces_seen, cpu);
701 * Cannot recover? Panic here then.
702 * This dumps all the mces in the log buffer and stops the
705 if (m && global_worst >= MCE_PANIC_SEVERITY && tolerant < 3)
706 mce_panic("Fatal Machine check", m, msg);
709 * For UC somewhere we let the CPU who detects it handle it.
710 * Also must let continue the others, otherwise the handling
711 * CPU could deadlock on a lock.
715 * No machine check event found. Must be some external
716 * source or one CPU is hung. Panic.
718 if (global_worst <= MCE_KEEP_SEVERITY && tolerant < 3)
719 mce_panic("Machine check from unknown source", NULL, NULL);
722 * Now clear all the mces_seen so that they don't reappear on
725 for_each_possible_cpu(cpu)
726 memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce));
729 static atomic_t global_nwo;
732 * Start of Monarch synchronization. This waits until all CPUs have
733 * entered the exception handler and then determines if any of them
734 * saw a fatal event that requires panic. Then it executes them
735 * in the entry order.
736 * TBD double check parallel CPU hotunplug
738 static int mce_start(int *no_way_out)
741 int cpus = num_online_cpus();
742 u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC;
747 atomic_add(*no_way_out, &global_nwo);
749 * global_nwo should be updated before mce_callin
752 order = atomic_inc_return(&mce_callin);
757 while (atomic_read(&mce_callin) != cpus) {
758 if (mce_timed_out(&timeout)) {
759 atomic_set(&global_nwo, 0);
766 * mce_callin should be read before global_nwo
772 * Monarch: Starts executing now, the others wait.
774 atomic_set(&mce_executing, 1);
777 * Subject: Now start the scanning loop one by one in
778 * the original callin order.
779 * This way when there are any shared banks it will be
780 * only seen by one CPU before cleared, avoiding duplicates.
782 while (atomic_read(&mce_executing) < order) {
783 if (mce_timed_out(&timeout)) {
784 atomic_set(&global_nwo, 0);
792 * Cache the global no_way_out state.
794 *no_way_out = atomic_read(&global_nwo);
800 * Synchronize between CPUs after main scanning loop.
801 * This invokes the bulk of the Monarch processing.
803 static int mce_end(int order)
806 u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC;
814 * Allow others to run.
816 atomic_inc(&mce_executing);
819 /* CHECKME: Can this race with a parallel hotplug? */
820 int cpus = num_online_cpus();
823 * Monarch: Wait for everyone to go through their scanning
826 while (atomic_read(&mce_executing) <= cpus) {
827 if (mce_timed_out(&timeout))
837 * Subject: Wait for Monarch to finish.
839 while (atomic_read(&mce_executing) != 0) {
840 if (mce_timed_out(&timeout))
846 * Don't reset anything. That's done by the Monarch.
852 * Reset all global state.
855 atomic_set(&global_nwo, 0);
856 atomic_set(&mce_callin, 0);
860 * Let others run again.
862 atomic_set(&mce_executing, 0);
867 * Check if the address reported by the CPU is in a format we can parse.
868 * It would be possible to add code for most other cases, but all would
869 * be somewhat complicated (e.g. segment offset would require an instruction
870 * parser). So only support physical addresses up to page granuality for now.
872 static int mce_usable_address(struct mce *m)
874 if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV))
876 if ((m->misc & 0x3f) > PAGE_SHIFT)
878 if (((m->misc >> 6) & 7) != MCM_ADDR_PHYS)
883 static void mce_clear_state(unsigned long *toclear)
887 for (i = 0; i < banks; i++) {
888 if (test_bit(i, toclear))
889 mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
894 * The actual machine check handler. This only handles real
895 * exceptions when something got corrupted coming in through int 18.
897 * This is executed in NMI context not subject to normal locking rules. This
898 * implies that most kernel services cannot be safely used. Don't even
899 * think about putting a printk in there!
901 * On Intel systems this is entered on all CPUs in parallel through
902 * MCE broadcast. However some CPUs might be broken beyond repair,
903 * so be always careful when synchronizing with others.
905 void do_machine_check(struct pt_regs *regs, long error_code)
907 struct mce m, *final;
912 * Establish sequential order between the CPUs entering the machine
917 * If no_way_out gets set, there is no safe way to recover from this
918 * MCE. If tolerant is cranked up, we'll try anyway.
922 * If kill_it gets set, there might be a way to recover from this
926 DECLARE_BITMAP(toclear, MAX_NR_BANKS);
927 char *msg = "Unknown";
929 atomic_inc(&mce_entry);
931 percpu_inc(mce_exception_count);
933 if (notify_die(DIE_NMI, "machine check", regs, error_code,
934 18, SIGKILL) == NOTIFY_STOP)
941 m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
942 final = &__get_cpu_var(mces_seen);
945 no_way_out = mce_no_way_out(&m, &msg);
950 * When no restart IP must always kill or panic.
952 if (!(m.mcgstatus & MCG_STATUS_RIPV))
956 * Go through all the banks in exclusion of the other CPUs.
957 * This way we don't report duplicated events on shared banks
958 * because the first one to see it will clear it.
960 order = mce_start(&no_way_out);
961 for (i = 0; i < banks; i++) {
962 __clear_bit(i, toclear);
963 if (!mce_banks[i].ctl)
970 m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
971 if ((m.status & MCI_STATUS_VAL) == 0)
975 * Non uncorrected or non signaled errors are handled by
976 * machine_check_poll. Leave them alone, unless this panics.
978 if (!(m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)) &&
983 * Set taint even when machine check was not enabled.
985 add_taint(TAINT_MACHINE_CHECK);
987 severity = mce_severity(&m, tolerant, NULL);
990 * When machine check was for corrected handler don't touch,
991 * unless we're panicing.
993 if (severity == MCE_KEEP_SEVERITY && !no_way_out)
995 __set_bit(i, toclear);
996 if (severity == MCE_NO_SEVERITY) {
998 * Machine check event was not enabled. Clear, but
1005 * Kill on action required.
1007 if (severity == MCE_AR_SEVERITY)
1010 if (m.status & MCI_STATUS_MISCV)
1011 m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i));
1012 if (m.status & MCI_STATUS_ADDRV)
1013 m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i));
1016 * Action optional error. Queue address for later processing.
1017 * When the ring overflows we just ignore the AO error.
1018 * RED-PEN add some logging mechanism when
1019 * usable_address or mce_add_ring fails.
1020 * RED-PEN don't ignore overflow for tolerant == 0
1022 if (severity == MCE_AO_SEVERITY && mce_usable_address(&m))
1023 mce_ring_add(m.addr >> PAGE_SHIFT);
1025 mce_get_rip(&m, regs);
1028 if (severity > worst) {
1035 mce_clear_state(toclear);
1038 * Do most of the synchronization with other CPUs.
1039 * When there's any problem use only local no_way_out state.
1041 if (mce_end(order) < 0)
1042 no_way_out = worst >= MCE_PANIC_SEVERITY;
1045 * If we have decided that we just CAN'T continue, and the user
1046 * has not set tolerant to an insane level, give up and die.
1048 * This is mainly used in the case when the system doesn't
1049 * support MCE broadcasting or it has been disabled.
1051 if (no_way_out && tolerant < 3)
1052 mce_panic("Fatal machine check on current CPU", final, msg);
1055 * If the error seems to be unrecoverable, something should be
1056 * done. Try to kill as little as possible. If we can kill just
1057 * one task, do that. If the user has set the tolerance very
1058 * high, don't try to do anything at all.
1061 if (kill_it && tolerant < 3)
1062 force_sig(SIGBUS, current);
1064 /* notify userspace ASAP */
1065 set_thread_flag(TIF_MCE_NOTIFY);
1068 mce_report_event(regs);
1069 mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
1071 atomic_dec(&mce_entry);
1074 EXPORT_SYMBOL_GPL(do_machine_check);
1076 /* dummy to break dependency. actual code is in mm/memory-failure.c */
1077 void __attribute__((weak)) memory_failure(unsigned long pfn, int vector)
1079 printk(KERN_ERR "Action optional memory failure at %lx ignored\n", pfn);
1083 * Called after mce notification in process context. This code
1084 * is allowed to sleep. Call the high level VM handler to process
1085 * any corrupted pages.
1086 * Assume that the work queue code only calls this one at a time
1088 * Note we don't disable preemption, so this code might run on the wrong
1089 * CPU. In this case the event is picked up by the scheduled work queue.
1090 * This is merely a fast path to expedite processing in some common
1093 void mce_notify_process(void)
1097 while (mce_ring_get(&pfn))
1098 memory_failure(pfn, MCE_VECTOR);
1101 static void mce_process_work(struct work_struct *dummy)
1103 mce_notify_process();
1106 #ifdef CONFIG_X86_MCE_INTEL
1108 * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog
1109 * @cpu: The CPU on which the event occurred.
1110 * @status: Event status information
1112 * This function should be called by the thermal interrupt after the
1113 * event has been processed and the decision was made to log the event
1116 * The status parameter will be saved to the 'status' field of 'struct mce'
1117 * and historically has been the register value of the
1118 * MSR_IA32_THERMAL_STATUS (Intel) msr.
1120 void mce_log_therm_throt_event(__u64 status)
1125 m.bank = MCE_THERMAL_BANK;
1129 #endif /* CONFIG_X86_MCE_INTEL */
1132 * Periodic polling timer for "silent" machine check errors. If the
1133 * poller finds an MCE, poll 2x faster. When the poller finds no more
1134 * errors, poll 2x slower (up to check_interval seconds).
1136 static int check_interval = 5 * 60; /* 5 minutes */
1138 static DEFINE_PER_CPU(int, mce_next_interval); /* in jiffies */
1139 static DEFINE_PER_CPU(struct timer_list, mce_timer);
1141 static void mce_start_timer(unsigned long data)
1143 struct timer_list *t = &per_cpu(mce_timer, data);
1146 WARN_ON(smp_processor_id() != data);
1148 if (mce_available(__this_cpu_ptr(&cpu_info))) {
1149 machine_check_poll(MCP_TIMESTAMP,
1150 &__get_cpu_var(mce_poll_banks));
1154 * Alert userspace if needed. If we logged an MCE, reduce the
1155 * polling interval, otherwise increase the polling interval.
1157 n = &__get_cpu_var(mce_next_interval);
1158 if (mce_notify_irq())
1159 *n = max(*n/2, HZ/100);
1161 *n = min(*n*2, (int)round_jiffies_relative(check_interval*HZ));
1163 t->expires = jiffies + *n;
1164 add_timer_on(t, smp_processor_id());
1167 static void mce_do_trigger(struct work_struct *work)
1169 call_usermodehelper(mce_helper, mce_helper_argv, NULL, UMH_NO_WAIT);
1172 static DECLARE_WORK(mce_trigger_work, mce_do_trigger);
1175 * Notify the user(s) about new machine check events.
1176 * Can be called from interrupt context, but not from machine check/NMI
1179 int mce_notify_irq(void)
1181 /* Not more than two messages every minute */
1182 static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2);
1184 clear_thread_flag(TIF_MCE_NOTIFY);
1186 if (test_and_clear_bit(0, &mce_need_notify)) {
1187 wake_up_interruptible(&mce_wait);
1190 * There is no risk of missing notifications because
1191 * work_pending is always cleared before the function is
1194 if (mce_helper[0] && !work_pending(&mce_trigger_work))
1195 schedule_work(&mce_trigger_work);
1197 if (__ratelimit(&ratelimit))
1198 pr_info(HW_ERR "Machine check events logged\n");
1204 EXPORT_SYMBOL_GPL(mce_notify_irq);
1206 static int __cpuinit __mcheck_cpu_mce_banks_init(void)
1210 mce_banks = kzalloc(banks * sizeof(struct mce_bank), GFP_KERNEL);
1213 for (i = 0; i < banks; i++) {
1214 struct mce_bank *b = &mce_banks[i];
1223 * Initialize Machine Checks for a CPU.
1225 static int __cpuinit __mcheck_cpu_cap_init(void)
1230 rdmsrl(MSR_IA32_MCG_CAP, cap);
1232 b = cap & MCG_BANKCNT_MASK;
1234 printk(KERN_INFO "mce: CPU supports %d MCE banks\n", b);
1236 if (b > MAX_NR_BANKS) {
1238 "MCE: Using only %u machine check banks out of %u\n",
1243 /* Don't support asymmetric configurations today */
1244 WARN_ON(banks != 0 && b != banks);
1247 int err = __mcheck_cpu_mce_banks_init();
1253 /* Use accurate RIP reporting if available. */
1254 if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9)
1255 rip_msr = MSR_IA32_MCG_EIP;
1257 if (cap & MCG_SER_P)
1263 static void __mcheck_cpu_init_generic(void)
1265 mce_banks_t all_banks;
1270 * Log the machine checks left over from the previous reset.
1272 bitmap_fill(all_banks, MAX_NR_BANKS);
1273 machine_check_poll(MCP_UC|(!mce_bootlog ? MCP_DONTLOG : 0), &all_banks);
1275 set_in_cr4(X86_CR4_MCE);
1277 rdmsrl(MSR_IA32_MCG_CAP, cap);
1278 if (cap & MCG_CTL_P)
1279 wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
1281 for (i = 0; i < banks; i++) {
1282 struct mce_bank *b = &mce_banks[i];
1286 wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl);
1287 wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
1291 /* Add per CPU specific workarounds here */
1292 static int __cpuinit __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
1294 if (c->x86_vendor == X86_VENDOR_UNKNOWN) {
1295 pr_info("MCE: unknown CPU type - not enabling MCE support.\n");
1299 /* This should be disabled by the BIOS, but isn't always */
1300 if (c->x86_vendor == X86_VENDOR_AMD) {
1301 if (c->x86 == 15 && banks > 4) {
1303 * disable GART TBL walk error reporting, which
1304 * trips off incorrectly with the IOMMU & 3ware
1307 clear_bit(10, (unsigned long *)&mce_banks[4].ctl);
1309 if (c->x86 <= 17 && mce_bootlog < 0) {
1311 * Lots of broken BIOS around that don't clear them
1312 * by default and leave crap in there. Don't log:
1317 * Various K7s with broken bank 0 around. Always disable
1320 if (c->x86 == 6 && banks > 0)
1321 mce_banks[0].ctl = 0;
1324 if (c->x86_vendor == X86_VENDOR_INTEL) {
1326 * SDM documents that on family 6 bank 0 should not be written
1327 * because it aliases to another special BIOS controlled
1329 * But it's not aliased anymore on model 0x1a+
1330 * Don't ignore bank 0 completely because there could be a
1331 * valid event later, merely don't write CTL0.
1334 if (c->x86 == 6 && c->x86_model < 0x1A && banks > 0)
1335 mce_banks[0].init = 0;
1338 * All newer Intel systems support MCE broadcasting. Enable
1339 * synchronization with a one second timeout.
1341 if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) &&
1342 monarch_timeout < 0)
1343 monarch_timeout = USEC_PER_SEC;
1346 * There are also broken BIOSes on some Pentium M and
1349 if (c->x86 == 6 && c->x86_model <= 13 && mce_bootlog < 0)
1352 if (monarch_timeout < 0)
1353 monarch_timeout = 0;
1354 if (mce_bootlog != 0)
1355 mce_panic_timeout = 30;
1360 static void __cpuinit __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c)
1364 switch (c->x86_vendor) {
1365 case X86_VENDOR_INTEL:
1366 intel_p5_mcheck_init(c);
1368 case X86_VENDOR_CENTAUR:
1369 winchip_mcheck_init(c);
1374 static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
1376 switch (c->x86_vendor) {
1377 case X86_VENDOR_INTEL:
1378 mce_intel_feature_init(c);
1380 case X86_VENDOR_AMD:
1381 mce_amd_feature_init(c);
1388 static void __mcheck_cpu_init_timer(void)
1390 struct timer_list *t = &__get_cpu_var(mce_timer);
1391 int *n = &__get_cpu_var(mce_next_interval);
1393 setup_timer(t, mce_start_timer, smp_processor_id());
1398 *n = check_interval * HZ;
1401 t->expires = round_jiffies(jiffies + *n);
1402 add_timer_on(t, smp_processor_id());
1405 /* Handle unconfigured int18 (should never happen) */
1406 static void unexpected_machine_check(struct pt_regs *regs, long error_code)
1408 printk(KERN_ERR "CPU#%d: Unexpected int18 (Machine Check).\n",
1409 smp_processor_id());
1412 /* Call the installed machine check handler for this CPU setup. */
1413 void (*machine_check_vector)(struct pt_regs *, long error_code) =
1414 unexpected_machine_check;
1417 * Called for each booted CPU to set up machine checks.
1418 * Must be called with preempt off:
1420 void __cpuinit mcheck_cpu_init(struct cpuinfo_x86 *c)
1425 __mcheck_cpu_ancient_init(c);
1427 if (!mce_available(c))
1430 if (__mcheck_cpu_cap_init() < 0 || __mcheck_cpu_apply_quirks(c) < 0) {
1435 machine_check_vector = do_machine_check;
1437 __mcheck_cpu_init_generic();
1438 __mcheck_cpu_init_vendor(c);
1439 __mcheck_cpu_init_timer();
1440 INIT_WORK(&__get_cpu_var(mce_work), mce_process_work);
1445 * Character device to read and clear the MCE log.
1448 static DEFINE_SPINLOCK(mce_state_lock);
1449 static int open_count; /* #times opened */
1450 static int open_exclu; /* already open exclusive? */
1452 static int mce_open(struct inode *inode, struct file *file)
1454 spin_lock(&mce_state_lock);
1456 if (open_exclu || (open_count && (file->f_flags & O_EXCL))) {
1457 spin_unlock(&mce_state_lock);
1462 if (file->f_flags & O_EXCL)
1466 spin_unlock(&mce_state_lock);
1468 return nonseekable_open(inode, file);
1471 static int mce_release(struct inode *inode, struct file *file)
1473 spin_lock(&mce_state_lock);
1478 spin_unlock(&mce_state_lock);
1483 static void collect_tscs(void *data)
1485 unsigned long *cpu_tsc = (unsigned long *)data;
1487 rdtscll(cpu_tsc[smp_processor_id()]);
1490 static int mce_apei_read_done;
1492 /* Collect MCE record of previous boot in persistent storage via APEI ERST. */
1493 static int __mce_read_apei(char __user **ubuf, size_t usize)
1499 if (usize < sizeof(struct mce))
1502 rc = apei_read_mce(&m, &record_id);
1503 /* Error or no more MCE record */
1505 mce_apei_read_done = 1;
1509 if (copy_to_user(*ubuf, &m, sizeof(struct mce)))
1512 * In fact, we should have cleared the record after that has
1513 * been flushed to the disk or sent to network in
1514 * /sbin/mcelog, but we have no interface to support that now,
1515 * so just clear it to avoid duplication.
1517 rc = apei_clear_mce(record_id);
1519 mce_apei_read_done = 1;
1522 *ubuf += sizeof(struct mce);
1527 static ssize_t mce_read(struct file *filp, char __user *ubuf, size_t usize,
1530 char __user *buf = ubuf;
1531 unsigned long *cpu_tsc;
1532 unsigned prev, next;
1535 cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL);
1539 mutex_lock(&mce_read_mutex);
1541 if (!mce_apei_read_done) {
1542 err = __mce_read_apei(&buf, usize);
1543 if (err || buf != ubuf)
1547 next = rcu_dereference_check_mce(mcelog.next);
1549 /* Only supports full reads right now */
1551 if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce))
1557 for (i = prev; i < next; i++) {
1558 unsigned long start = jiffies;
1560 while (!mcelog.entry[i].finished) {
1561 if (time_after_eq(jiffies, start + 2)) {
1562 memset(mcelog.entry + i, 0,
1563 sizeof(struct mce));
1569 err |= copy_to_user(buf, mcelog.entry + i,
1570 sizeof(struct mce));
1571 buf += sizeof(struct mce);
1576 memset(mcelog.entry + prev, 0,
1577 (next - prev) * sizeof(struct mce));
1579 next = cmpxchg(&mcelog.next, prev, 0);
1580 } while (next != prev);
1582 synchronize_sched();
1585 * Collect entries that were still getting written before the
1588 on_each_cpu(collect_tscs, cpu_tsc, 1);
1590 for (i = next; i < MCE_LOG_LEN; i++) {
1591 if (mcelog.entry[i].finished &&
1592 mcelog.entry[i].tsc < cpu_tsc[mcelog.entry[i].cpu]) {
1593 err |= copy_to_user(buf, mcelog.entry+i,
1594 sizeof(struct mce));
1596 buf += sizeof(struct mce);
1597 memset(&mcelog.entry[i], 0, sizeof(struct mce));
1605 mutex_unlock(&mce_read_mutex);
1608 return err ? err : buf - ubuf;
1611 static unsigned int mce_poll(struct file *file, poll_table *wait)
1613 poll_wait(file, &mce_wait, wait);
1614 if (rcu_access_index(mcelog.next))
1615 return POLLIN | POLLRDNORM;
1616 if (!mce_apei_read_done && apei_check_mce())
1617 return POLLIN | POLLRDNORM;
1621 static long mce_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
1623 int __user *p = (int __user *)arg;
1625 if (!capable(CAP_SYS_ADMIN))
1629 case MCE_GET_RECORD_LEN:
1630 return put_user(sizeof(struct mce), p);
1631 case MCE_GET_LOG_LEN:
1632 return put_user(MCE_LOG_LEN, p);
1633 case MCE_GETCLEAR_FLAGS: {
1637 flags = mcelog.flags;
1638 } while (cmpxchg(&mcelog.flags, flags, 0) != flags);
1640 return put_user(flags, p);
1647 /* Modified in mce-inject.c, so not static or const */
1648 struct file_operations mce_chrdev_ops = {
1650 .release = mce_release,
1653 .unlocked_ioctl = mce_ioctl,
1654 .llseek = no_llseek,
1656 EXPORT_SYMBOL_GPL(mce_chrdev_ops);
1658 static struct miscdevice mce_log_device = {
1665 * mce=off Disables machine check
1666 * mce=no_cmci Disables CMCI
1667 * mce=dont_log_ce Clears corrected events silently, no log created for CEs.
1668 * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared.
1669 * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above)
1670 * monarchtimeout is how long to wait for other CPUs on machine
1671 * check, or 0 to not wait
1672 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD.
1673 * mce=nobootlog Don't log MCEs from before booting.
1675 static int __init mcheck_enable(char *str)
1683 if (!strcmp(str, "off"))
1685 else if (!strcmp(str, "no_cmci"))
1686 mce_cmci_disabled = 1;
1687 else if (!strcmp(str, "dont_log_ce"))
1688 mce_dont_log_ce = 1;
1689 else if (!strcmp(str, "ignore_ce"))
1691 else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog"))
1692 mce_bootlog = (str[0] == 'b');
1693 else if (isdigit(str[0])) {
1694 get_option(&str, &tolerant);
1697 get_option(&str, &monarch_timeout);
1700 printk(KERN_INFO "mce argument %s ignored. Please use /sys\n",
1706 __setup("mce", mcheck_enable);
1708 int __init mcheck_init(void)
1710 mcheck_intel_therm_init();
1720 * Disable machine checks on suspend and shutdown. We can't really handle
1723 static int mce_disable_error_reporting(void)
1727 for (i = 0; i < banks; i++) {
1728 struct mce_bank *b = &mce_banks[i];
1731 wrmsrl(MSR_IA32_MCx_CTL(i), 0);
1736 static int mce_suspend(void)
1738 return mce_disable_error_reporting();
1741 static void mce_shutdown(void)
1743 mce_disable_error_reporting();
1747 * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
1748 * Only one CPU is active at this time, the others get re-added later using
1751 static void mce_resume(void)
1753 __mcheck_cpu_init_generic();
1754 __mcheck_cpu_init_vendor(__this_cpu_ptr(&cpu_info));
1757 static struct syscore_ops mce_syscore_ops = {
1758 .suspend = mce_suspend,
1759 .shutdown = mce_shutdown,
1760 .resume = mce_resume,
1763 static void mce_cpu_restart(void *data)
1765 del_timer_sync(&__get_cpu_var(mce_timer));
1766 if (!mce_available(__this_cpu_ptr(&cpu_info)))
1768 __mcheck_cpu_init_generic();
1769 __mcheck_cpu_init_timer();
1772 /* Reinit MCEs after user configuration changes */
1773 static void mce_restart(void)
1775 on_each_cpu(mce_cpu_restart, NULL, 1);
1778 /* Toggle features for corrected errors */
1779 static void mce_disable_ce(void *all)
1781 if (!mce_available(__this_cpu_ptr(&cpu_info)))
1784 del_timer_sync(&__get_cpu_var(mce_timer));
1788 static void mce_enable_ce(void *all)
1790 if (!mce_available(__this_cpu_ptr(&cpu_info)))
1795 __mcheck_cpu_init_timer();
1798 static struct sysdev_class mce_sysclass = {
1799 .name = "machinecheck",
1802 DEFINE_PER_CPU(struct sys_device, mce_dev);
1805 void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
1807 static inline struct mce_bank *attr_to_bank(struct sysdev_attribute *attr)
1809 return container_of(attr, struct mce_bank, attr);
1812 static ssize_t show_bank(struct sys_device *s, struct sysdev_attribute *attr,
1815 return sprintf(buf, "%llx\n", attr_to_bank(attr)->ctl);
1818 static ssize_t set_bank(struct sys_device *s, struct sysdev_attribute *attr,
1819 const char *buf, size_t size)
1823 if (strict_strtoull(buf, 0, &new) < 0)
1826 attr_to_bank(attr)->ctl = new;
1833 show_trigger(struct sys_device *s, struct sysdev_attribute *attr, char *buf)
1835 strcpy(buf, mce_helper);
1837 return strlen(mce_helper) + 1;
1840 static ssize_t set_trigger(struct sys_device *s, struct sysdev_attribute *attr,
1841 const char *buf, size_t siz)
1845 strncpy(mce_helper, buf, sizeof(mce_helper));
1846 mce_helper[sizeof(mce_helper)-1] = 0;
1847 p = strchr(mce_helper, '\n');
1852 return strlen(mce_helper) + !!p;
1855 static ssize_t set_ignore_ce(struct sys_device *s,
1856 struct sysdev_attribute *attr,
1857 const char *buf, size_t size)
1861 if (strict_strtoull(buf, 0, &new) < 0)
1864 if (mce_ignore_ce ^ !!new) {
1866 /* disable ce features */
1867 on_each_cpu(mce_disable_ce, (void *)1, 1);
1870 /* enable ce features */
1872 on_each_cpu(mce_enable_ce, (void *)1, 1);
1878 static ssize_t set_cmci_disabled(struct sys_device *s,
1879 struct sysdev_attribute *attr,
1880 const char *buf, size_t size)
1884 if (strict_strtoull(buf, 0, &new) < 0)
1887 if (mce_cmci_disabled ^ !!new) {
1890 on_each_cpu(mce_disable_ce, NULL, 1);
1891 mce_cmci_disabled = 1;
1894 mce_cmci_disabled = 0;
1895 on_each_cpu(mce_enable_ce, NULL, 1);
1901 static ssize_t store_int_with_restart(struct sys_device *s,
1902 struct sysdev_attribute *attr,
1903 const char *buf, size_t size)
1905 ssize_t ret = sysdev_store_int(s, attr, buf, size);
1910 static SYSDEV_ATTR(trigger, 0644, show_trigger, set_trigger);
1911 static SYSDEV_INT_ATTR(tolerant, 0644, tolerant);
1912 static SYSDEV_INT_ATTR(monarch_timeout, 0644, monarch_timeout);
1913 static SYSDEV_INT_ATTR(dont_log_ce, 0644, mce_dont_log_ce);
1915 static struct sysdev_ext_attribute attr_check_interval = {
1916 _SYSDEV_ATTR(check_interval, 0644, sysdev_show_int,
1917 store_int_with_restart),
1921 static struct sysdev_ext_attribute attr_ignore_ce = {
1922 _SYSDEV_ATTR(ignore_ce, 0644, sysdev_show_int, set_ignore_ce),
1926 static struct sysdev_ext_attribute attr_cmci_disabled = {
1927 _SYSDEV_ATTR(cmci_disabled, 0644, sysdev_show_int, set_cmci_disabled),
1931 static struct sysdev_attribute *mce_attrs[] = {
1932 &attr_tolerant.attr,
1933 &attr_check_interval.attr,
1935 &attr_monarch_timeout.attr,
1936 &attr_dont_log_ce.attr,
1937 &attr_ignore_ce.attr,
1938 &attr_cmci_disabled.attr,
1942 static cpumask_var_t mce_dev_initialized;
1944 /* Per cpu sysdev init. All of the cpus still share the same ctrl bank: */
1945 static __cpuinit int mce_create_device(unsigned int cpu)
1950 if (!mce_available(&boot_cpu_data))
1953 memset(&per_cpu(mce_dev, cpu).kobj, 0, sizeof(struct kobject));
1954 per_cpu(mce_dev, cpu).id = cpu;
1955 per_cpu(mce_dev, cpu).cls = &mce_sysclass;
1957 err = sysdev_register(&per_cpu(mce_dev, cpu));
1961 for (i = 0; mce_attrs[i]; i++) {
1962 err = sysdev_create_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
1966 for (j = 0; j < banks; j++) {
1967 err = sysdev_create_file(&per_cpu(mce_dev, cpu),
1968 &mce_banks[j].attr);
1972 cpumask_set_cpu(cpu, mce_dev_initialized);
1977 sysdev_remove_file(&per_cpu(mce_dev, cpu), &mce_banks[j].attr);
1980 sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
1982 sysdev_unregister(&per_cpu(mce_dev, cpu));
1987 static __cpuinit void mce_remove_device(unsigned int cpu)
1991 if (!cpumask_test_cpu(cpu, mce_dev_initialized))
1994 for (i = 0; mce_attrs[i]; i++)
1995 sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
1997 for (i = 0; i < banks; i++)
1998 sysdev_remove_file(&per_cpu(mce_dev, cpu), &mce_banks[i].attr);
2000 sysdev_unregister(&per_cpu(mce_dev, cpu));
2001 cpumask_clear_cpu(cpu, mce_dev_initialized);
2004 /* Make sure there are no machine checks on offlined CPUs. */
2005 static void __cpuinit mce_disable_cpu(void *h)
2007 unsigned long action = *(unsigned long *)h;
2010 if (!mce_available(__this_cpu_ptr(&cpu_info)))
2013 if (!(action & CPU_TASKS_FROZEN))
2015 for (i = 0; i < banks; i++) {
2016 struct mce_bank *b = &mce_banks[i];
2019 wrmsrl(MSR_IA32_MCx_CTL(i), 0);
2023 static void __cpuinit mce_reenable_cpu(void *h)
2025 unsigned long action = *(unsigned long *)h;
2028 if (!mce_available(__this_cpu_ptr(&cpu_info)))
2031 if (!(action & CPU_TASKS_FROZEN))
2033 for (i = 0; i < banks; i++) {
2034 struct mce_bank *b = &mce_banks[i];
2037 wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl);
2041 /* Get notified when a cpu comes on/off. Be hotplug friendly. */
2042 static int __cpuinit
2043 mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu)
2045 unsigned int cpu = (unsigned long)hcpu;
2046 struct timer_list *t = &per_cpu(mce_timer, cpu);
2050 case CPU_ONLINE_FROZEN:
2051 mce_create_device(cpu);
2052 if (threshold_cpu_callback)
2053 threshold_cpu_callback(action, cpu);
2056 case CPU_DEAD_FROZEN:
2057 if (threshold_cpu_callback)
2058 threshold_cpu_callback(action, cpu);
2059 mce_remove_device(cpu);
2061 case CPU_DOWN_PREPARE:
2062 case CPU_DOWN_PREPARE_FROZEN:
2064 smp_call_function_single(cpu, mce_disable_cpu, &action, 1);
2066 case CPU_DOWN_FAILED:
2067 case CPU_DOWN_FAILED_FROZEN:
2068 if (!mce_ignore_ce && check_interval) {
2069 t->expires = round_jiffies(jiffies +
2070 __get_cpu_var(mce_next_interval));
2071 add_timer_on(t, cpu);
2073 smp_call_function_single(cpu, mce_reenable_cpu, &action, 1);
2076 /* intentionally ignoring frozen here */
2077 cmci_rediscover(cpu);
2083 static struct notifier_block mce_cpu_notifier __cpuinitdata = {
2084 .notifier_call = mce_cpu_callback,
2087 static __init void mce_init_banks(void)
2091 for (i = 0; i < banks; i++) {
2092 struct mce_bank *b = &mce_banks[i];
2093 struct sysdev_attribute *a = &b->attr;
2095 sysfs_attr_init(&a->attr);
2096 a->attr.name = b->attrname;
2097 snprintf(b->attrname, ATTR_LEN, "bank%d", i);
2099 a->attr.mode = 0644;
2100 a->show = show_bank;
2101 a->store = set_bank;
2105 static __init int mcheck_init_device(void)
2110 if (!mce_available(&boot_cpu_data))
2113 zalloc_cpumask_var(&mce_dev_initialized, GFP_KERNEL);
2117 err = sysdev_class_register(&mce_sysclass);
2121 for_each_online_cpu(i) {
2122 err = mce_create_device(i);
2127 register_syscore_ops(&mce_syscore_ops);
2128 register_hotcpu_notifier(&mce_cpu_notifier);
2129 misc_register(&mce_log_device);
2134 device_initcall(mcheck_init_device);
2137 * Old style boot options parsing. Only for compatibility.
2139 static int __init mcheck_disable(char *str)
2144 __setup("nomce", mcheck_disable);
2146 #ifdef CONFIG_DEBUG_FS
2147 struct dentry *mce_get_debugfs_dir(void)
2149 static struct dentry *dmce;
2152 dmce = debugfs_create_dir("mce", NULL);
2157 static void mce_reset(void)
2160 atomic_set(&mce_fake_paniced, 0);
2161 atomic_set(&mce_executing, 0);
2162 atomic_set(&mce_callin, 0);
2163 atomic_set(&global_nwo, 0);
2166 static int fake_panic_get(void *data, u64 *val)
2172 static int fake_panic_set(void *data, u64 val)
2179 DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops, fake_panic_get,
2180 fake_panic_set, "%llu\n");
2182 static int __init mcheck_debugfs_init(void)
2184 struct dentry *dmce, *ffake_panic;
2186 dmce = mce_get_debugfs_dir();
2189 ffake_panic = debugfs_create_file("fake_panic", 0444, dmce, NULL,
2196 late_initcall(mcheck_debugfs_init);