2 * (c) 2005, 2006 Advanced Micro Devices, Inc.
3 * Your use of this code is subject to the terms and conditions of the
4 * GNU general public license version 2. See "COPYING" or
5 * http://www.gnu.org/licenses/gpl.html
7 * Written by Jacob Shin - AMD, Inc.
9 * Support : jacob.shin@amd.com
12 * - added support for AMD Family 0x10 processors
14 * All MC4_MISCi registers are shared between multi-cores
16 #include <linux/interrupt.h>
17 #include <linux/notifier.h>
18 #include <linux/kobject.h>
19 #include <linux/percpu.h>
20 #include <linux/errno.h>
21 #include <linux/sched.h>
22 #include <linux/sysfs.h>
23 #include <linux/slab.h>
24 #include <linux/init.h>
25 #include <linux/cpu.h>
26 #include <linux/smp.h>
35 #define THRESHOLD_MAX 0xFFF
36 #define INT_TYPE_APIC 0x00020000
37 #define MASK_VALID_HI 0x80000000
38 #define MASK_CNTP_HI 0x40000000
39 #define MASK_LOCKED_HI 0x20000000
40 #define MASK_LVTOFF_HI 0x00F00000
41 #define MASK_COUNT_EN_HI 0x00080000
42 #define MASK_INT_TYPE_HI 0x00060000
43 #define MASK_OVERFLOW_HI 0x00010000
44 #define MASK_ERR_COUNT_HI 0x00000FFF
45 #define MASK_BLKPTR_LO 0xFF000000
46 #define MCG_XBLK_ADDR 0xC0000400
48 struct threshold_block {
54 bool interrupt_capable;
57 struct list_head miscj;
60 struct threshold_bank {
62 struct threshold_block *blocks;
65 static DEFINE_PER_CPU(struct threshold_bank * [NR_BANKS], threshold_banks);
67 static unsigned char shared_bank[NR_BANKS] = {
71 static DEFINE_PER_CPU(unsigned char, bank_map); /* see which banks are on */
73 static void amd_threshold_interrupt(void);
79 struct thresh_restart {
80 struct threshold_block *b;
87 static bool lvt_interrupt_supported(unsigned int bank, u32 msr_high_bits)
90 * bank 4 supports APIC LVT interrupts implicitly since forever.
96 * IntP: interrupt present; if this bit is set, the thresholding
97 * bank can generate APIC LVT interrupts
99 return msr_high_bits & BIT(28);
102 static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi)
104 int msr = (hi & MASK_LVTOFF_HI) >> 20;
107 pr_err(FW_BUG "cpu %d, failed to setup threshold interrupt "
108 "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu,
109 b->bank, b->block, b->address, hi, lo);
114 pr_err(FW_BUG "cpu %d, invalid threshold interrupt offset %d "
115 "for bank %d, block %d (MSR%08X=0x%x%08x)\n",
116 b->cpu, apic, b->bank, b->block, b->address, hi, lo);
124 * Called via smp_call_function_single(), must be called with correct
127 static void threshold_restart_bank(void *_tr)
129 struct thresh_restart *tr = _tr;
132 rdmsr(tr->b->address, lo, hi);
134 if (tr->b->threshold_limit < (hi & THRESHOLD_MAX))
135 tr->reset = 1; /* limit cannot be lower than err count */
137 if (tr->reset) { /* reset err count and overflow bit */
139 (hi & ~(MASK_ERR_COUNT_HI | MASK_OVERFLOW_HI)) |
140 (THRESHOLD_MAX - tr->b->threshold_limit);
141 } else if (tr->old_limit) { /* change limit w/o reset */
142 int new_count = (hi & THRESHOLD_MAX) +
143 (tr->old_limit - tr->b->threshold_limit);
145 hi = (hi & ~MASK_ERR_COUNT_HI) |
146 (new_count & THRESHOLD_MAX);
150 hi &= ~MASK_INT_TYPE_HI;
152 if (!tr->b->interrupt_capable)
155 if (tr->set_lvt_off) {
156 if (lvt_off_valid(tr->b, tr->lvt_off, lo, hi)) {
157 /* set new lvt offset */
158 hi &= ~MASK_LVTOFF_HI;
159 hi |= tr->lvt_off << 20;
163 if (tr->b->interrupt_enable)
168 hi |= MASK_COUNT_EN_HI;
169 wrmsr(tr->b->address, lo, hi);
172 static void mce_threshold_block_init(struct threshold_block *b, int offset)
174 struct thresh_restart tr = {
180 b->threshold_limit = THRESHOLD_MAX;
181 threshold_restart_bank(&tr);
184 static int setup_APIC_mce(int reserved, int new)
186 if (reserved < 0 && !setup_APIC_eilvt(new, THRESHOLD_APIC_VECTOR,
187 APIC_EILVT_MSG_FIX, 0))
193 /* cpu init entry point, called from mce.c with preempt off */
194 void mce_amd_feature_init(struct cpuinfo_x86 *c)
196 struct threshold_block b;
197 unsigned int cpu = smp_processor_id();
198 u32 low = 0, high = 0, address = 0;
199 unsigned int bank, block;
202 for (bank = 0; bank < NR_BANKS; ++bank) {
203 for (block = 0; block < NR_BLOCKS; ++block) {
205 address = MSR_IA32_MC0_MISC + bank * 4;
206 else if (block == 1) {
207 address = (low & MASK_BLKPTR_LO) >> 21;
211 address += MCG_XBLK_ADDR;
215 if (rdmsr_safe(address, &low, &high))
218 if (!(high & MASK_VALID_HI))
221 if (!(high & MASK_CNTP_HI) ||
222 (high & MASK_LOCKED_HI))
226 per_cpu(bank_map, cpu) |= (1 << bank);
227 if (shared_bank[bank] && c->cpu_core_id)
230 memset(&b, 0, sizeof(b));
235 b.interrupt_capable = lvt_interrupt_supported(bank, high);
237 if (b.interrupt_capable) {
238 int new = (high & MASK_LVTOFF_HI) >> 20;
239 offset = setup_APIC_mce(offset, new);
242 mce_threshold_block_init(&b, offset);
243 mce_threshold_vector = amd_threshold_interrupt;
249 * APIC Interrupt Handler
253 * threshold interrupt handler will service THRESHOLD_APIC_VECTOR.
254 * the interrupt goes off when error_count reaches threshold_limit.
255 * the handler will simply log mcelog w/ software defined bank number.
257 static void amd_threshold_interrupt(void)
259 u32 low = 0, high = 0, address = 0;
260 unsigned int bank, block;
265 /* assume first bank caused it */
266 for (bank = 0; bank < NR_BANKS; ++bank) {
267 if (!(per_cpu(bank_map, m.cpu) & (1 << bank)))
269 for (block = 0; block < NR_BLOCKS; ++block) {
271 address = MSR_IA32_MC0_MISC + bank * 4;
272 } else if (block == 1) {
273 address = (low & MASK_BLKPTR_LO) >> 21;
276 address += MCG_XBLK_ADDR;
281 if (rdmsr_safe(address, &low, &high))
284 if (!(high & MASK_VALID_HI)) {
291 if (!(high & MASK_CNTP_HI) ||
292 (high & MASK_LOCKED_HI))
296 * Log the machine check that caused the threshold
299 machine_check_poll(MCP_TIMESTAMP,
300 &__get_cpu_var(mce_poll_banks));
302 if (high & MASK_OVERFLOW_HI) {
303 rdmsrl(address, m.misc);
304 rdmsrl(MSR_IA32_MC0_STATUS + bank * 4,
306 m.bank = K8_MCE_THRESHOLD_BASE
320 struct threshold_attr {
321 struct attribute attr;
322 ssize_t (*show) (struct threshold_block *, char *);
323 ssize_t (*store) (struct threshold_block *, const char *, size_t count);
326 #define SHOW_FIELDS(name) \
327 static ssize_t show_ ## name(struct threshold_block *b, char *buf) \
329 return sprintf(buf, "%lx\n", (unsigned long) b->name); \
331 SHOW_FIELDS(interrupt_enable)
332 SHOW_FIELDS(threshold_limit)
335 store_interrupt_enable(struct threshold_block *b, const char *buf, size_t size)
337 struct thresh_restart tr;
340 if (!b->interrupt_capable)
343 if (strict_strtoul(buf, 0, &new) < 0)
346 b->interrupt_enable = !!new;
348 memset(&tr, 0, sizeof(tr));
351 smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1);
357 store_threshold_limit(struct threshold_block *b, const char *buf, size_t size)
359 struct thresh_restart tr;
362 if (strict_strtoul(buf, 0, &new) < 0)
365 if (new > THRESHOLD_MAX)
370 memset(&tr, 0, sizeof(tr));
371 tr.old_limit = b->threshold_limit;
372 b->threshold_limit = new;
375 smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1);
380 struct threshold_block_cross_cpu {
381 struct threshold_block *tb;
385 static void local_error_count_handler(void *_tbcc)
387 struct threshold_block_cross_cpu *tbcc = _tbcc;
388 struct threshold_block *b = tbcc->tb;
391 rdmsr(b->address, low, high);
392 tbcc->retval = (high & 0xFFF) - (THRESHOLD_MAX - b->threshold_limit);
395 static ssize_t show_error_count(struct threshold_block *b, char *buf)
397 struct threshold_block_cross_cpu tbcc = { .tb = b, };
399 smp_call_function_single(b->cpu, local_error_count_handler, &tbcc, 1);
400 return sprintf(buf, "%lx\n", tbcc.retval);
403 static ssize_t store_error_count(struct threshold_block *b,
404 const char *buf, size_t count)
406 struct thresh_restart tr = { .b = b, .reset = 1, .old_limit = 0 };
408 smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1);
412 #define RW_ATTR(val) \
413 static struct threshold_attr val = { \
414 .attr = {.name = __stringify(val), .mode = 0644 }, \
415 .show = show_## val, \
416 .store = store_## val, \
419 RW_ATTR(interrupt_enable);
420 RW_ATTR(threshold_limit);
421 RW_ATTR(error_count);
423 static struct attribute *default_attrs[] = {
424 &threshold_limit.attr,
426 NULL, /* possibly interrupt_enable if supported, see below */
430 #define to_block(k) container_of(k, struct threshold_block, kobj)
431 #define to_attr(a) container_of(a, struct threshold_attr, attr)
433 static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf)
435 struct threshold_block *b = to_block(kobj);
436 struct threshold_attr *a = to_attr(attr);
439 ret = a->show ? a->show(b, buf) : -EIO;
444 static ssize_t store(struct kobject *kobj, struct attribute *attr,
445 const char *buf, size_t count)
447 struct threshold_block *b = to_block(kobj);
448 struct threshold_attr *a = to_attr(attr);
451 ret = a->store ? a->store(b, buf, count) : -EIO;
456 static const struct sysfs_ops threshold_ops = {
461 static struct kobj_type threshold_ktype = {
462 .sysfs_ops = &threshold_ops,
463 .default_attrs = default_attrs,
466 static __cpuinit int allocate_threshold_blocks(unsigned int cpu,
471 struct threshold_block *b = NULL;
475 if ((bank >= NR_BANKS) || (block >= NR_BLOCKS))
478 if (rdmsr_safe_on_cpu(cpu, address, &low, &high))
481 if (!(high & MASK_VALID_HI)) {
488 if (!(high & MASK_CNTP_HI) ||
489 (high & MASK_LOCKED_HI))
492 b = kzalloc(sizeof(struct threshold_block), GFP_KERNEL);
499 b->address = address;
500 b->interrupt_enable = 0;
501 b->interrupt_capable = lvt_interrupt_supported(bank, high);
502 b->threshold_limit = THRESHOLD_MAX;
504 if (b->interrupt_capable)
505 threshold_ktype.default_attrs[2] = &interrupt_enable.attr;
507 threshold_ktype.default_attrs[2] = NULL;
509 INIT_LIST_HEAD(&b->miscj);
511 if (per_cpu(threshold_banks, cpu)[bank]->blocks) {
513 &per_cpu(threshold_banks, cpu)[bank]->blocks->miscj);
515 per_cpu(threshold_banks, cpu)[bank]->blocks = b;
518 err = kobject_init_and_add(&b->kobj, &threshold_ktype,
519 per_cpu(threshold_banks, cpu)[bank]->kobj,
525 address = (low & MASK_BLKPTR_LO) >> 21;
528 address += MCG_XBLK_ADDR;
533 err = allocate_threshold_blocks(cpu, bank, ++block, address);
538 kobject_uevent(&b->kobj, KOBJ_ADD);
544 kobject_put(&b->kobj);
551 static __cpuinit long
552 local_allocate_threshold_blocks(int cpu, unsigned int bank)
554 return allocate_threshold_blocks(cpu, bank, 0,
555 MSR_IA32_MC0_MISC + bank * 4);
558 /* symlinks sibling shared banks to first core. first core owns dir/files. */
559 static __cpuinit int threshold_create_bank(unsigned int cpu, unsigned int bank)
562 struct threshold_bank *b = NULL;
563 struct device *dev = per_cpu(mce_device, cpu);
566 sprintf(name, "threshold_bank%i", bank);
569 if (cpu_data(cpu).cpu_core_id && shared_bank[bank]) { /* symlink */
570 i = cpumask_first(cpu_llc_shared_mask(cpu));
572 /* first core not up yet */
573 if (cpu_data(i).cpu_core_id)
577 if (per_cpu(threshold_banks, cpu)[bank])
580 b = per_cpu(threshold_banks, i)[bank];
585 err = sysfs_create_link(&dev->kobj, b->kobj, name);
589 cpumask_copy(b->cpus, cpu_llc_shared_mask(cpu));
590 per_cpu(threshold_banks, cpu)[bank] = b;
596 b = kzalloc(sizeof(struct threshold_bank), GFP_KERNEL);
601 if (!zalloc_cpumask_var(&b->cpus, GFP_KERNEL)) {
607 b->kobj = kobject_create_and_add(name, &dev->kobj);
612 cpumask_setall(b->cpus);
614 cpumask_set_cpu(cpu, b->cpus);
617 per_cpu(threshold_banks, cpu)[bank] = b;
619 err = local_allocate_threshold_blocks(cpu, bank);
623 for_each_cpu(i, b->cpus) {
627 dev = per_cpu(mce_device, i);
629 err = sysfs_create_link(&dev->kobj,b->kobj, name);
633 per_cpu(threshold_banks, i)[bank] = b;
639 per_cpu(threshold_banks, cpu)[bank] = NULL;
640 free_cpumask_var(b->cpus);
646 /* create dir/files for all valid threshold banks */
647 static __cpuinit int threshold_create_device(unsigned int cpu)
652 for (bank = 0; bank < NR_BANKS; ++bank) {
653 if (!(per_cpu(bank_map, cpu) & (1 << bank)))
655 err = threshold_create_bank(cpu, bank);
664 * let's be hotplug friendly.
665 * in case of multiple core processors, the first core always takes ownership
666 * of shared sysfs dir/files, and rest of the cores will be symlinked to it.
669 static void deallocate_threshold_block(unsigned int cpu,
672 struct threshold_block *pos = NULL;
673 struct threshold_block *tmp = NULL;
674 struct threshold_bank *head = per_cpu(threshold_banks, cpu)[bank];
679 list_for_each_entry_safe(pos, tmp, &head->blocks->miscj, miscj) {
680 kobject_put(&pos->kobj);
681 list_del(&pos->miscj);
685 kfree(per_cpu(threshold_banks, cpu)[bank]->blocks);
686 per_cpu(threshold_banks, cpu)[bank]->blocks = NULL;
689 static void threshold_remove_bank(unsigned int cpu, int bank)
691 struct threshold_bank *b;
696 b = per_cpu(threshold_banks, cpu)[bank];
702 sprintf(name, "threshold_bank%i", bank);
705 /* sibling symlink */
706 if (shared_bank[bank] && b->blocks->cpu != cpu) {
707 dev = per_cpu(mce_device, cpu);
708 sysfs_remove_link(&dev->kobj, name);
709 per_cpu(threshold_banks, cpu)[bank] = NULL;
715 /* remove all sibling symlinks before unregistering */
716 for_each_cpu(i, b->cpus) {
720 dev = per_cpu(mce_device, i);
722 sysfs_remove_link(&dev->kobj, name);
723 per_cpu(threshold_banks, i)[bank] = NULL;
726 deallocate_threshold_block(cpu, bank);
729 kobject_del(b->kobj);
730 kobject_put(b->kobj);
731 free_cpumask_var(b->cpus);
733 per_cpu(threshold_banks, cpu)[bank] = NULL;
736 static void threshold_remove_device(unsigned int cpu)
740 for (bank = 0; bank < NR_BANKS; ++bank) {
741 if (!(per_cpu(bank_map, cpu) & (1 << bank)))
743 threshold_remove_bank(cpu, bank);
747 /* get notified when a cpu comes on/off */
748 static void __cpuinit
749 amd_64_threshold_cpu_callback(unsigned long action, unsigned int cpu)
753 case CPU_ONLINE_FROZEN:
754 threshold_create_device(cpu);
757 case CPU_DEAD_FROZEN:
758 threshold_remove_device(cpu);
765 static __init int threshold_init_device(void)
769 /* to hit CPUs online before the notifier is up */
770 for_each_online_cpu(lcpu) {
771 int err = threshold_create_device(lcpu);
776 threshold_cpu_callback = amd_64_threshold_cpu_callback;
780 device_initcall(threshold_init_device);