arch/x86/kernel/irq.c

   1 /*
   2  * Common interrupt code for 32 and 64 bit
   3  */
   4 #include <linux/cpu.h>
   5 #include <linux/interrupt.h>
   6 #include <linux/kernel_stat.h>
   7 #include <linux/of.h>
   8 #include <linux/seq_file.h>
   9 #include <linux/smp.h>
  10 #include <linux/ftrace.h>
  11 #include <linux/delay.h>
  12 #include <linux/export.h>
  13
  14 #include <asm/apic.h>
  15 #include <asm/io_apic.h>
  16 #include <asm/irq.h>
  17 #include <asm/idle.h>
  18 #include <asm/mce.h>
  19 #include <asm/hw_irq.h>
  20
  21 #define CREATE_TRACE_POINTS
  22 #include <asm/trace/irq_vectors.h>
  23
  24 atomic_t irq_err_count;
  25
  26 /* Function pointer for generic interrupt vector handling */
  27 void (*x86_platform_ipi_callback)(void) = NULL;
  28
  29 /*
  30  * 'what should we do if we get a hw irq event on an illegal vector'.
  31  * each architecture has to answer this themselves.
  32  */
  33 void ack_bad_irq(unsigned int irq)
  34 {
  35         if (printk_ratelimit())
  36                 pr_err("unexpected IRQ trap at vector %02x\n", irq);
  37
  38         /*
  39          * Currently unexpected vectors happen only on SMP and APIC.
  40          * We _must_ ack these because every local APIC has only N
  41          * irq slots per priority level, and a 'hanging, unacked' IRQ
  42          * holds up an irq slot - in excessive cases (when multiple
  43          * unexpected vectors occur) that might lock up the APIC
  44          * completely.
  45          * But only ack when the APIC is enabled -AK
  46          */
  47         ack_APIC_irq();
  48 }
  49
  50 #define irq_stats(x)            (&per_cpu(irq_stat, x))
  51 /*
  52  * /proc/interrupts printing for arch specific interrupts
  53  */
  54 int arch_show_interrupts(struct seq_file *p, int prec)
  55 {
  56         int j;
  57
  58         seq_printf(p, "%*s: ", prec, "NMI");
  59         for_each_online_cpu(j)
  60                 seq_printf(p, "%10u ", irq_stats(j)->__nmi_count);
  61         seq_printf(p, "  Non-maskable interrupts\n");
  62 #ifdef CONFIG_X86_LOCAL_APIC
  63         seq_printf(p, "%*s: ", prec, "LOC");
  64         for_each_online_cpu(j)
  65                 seq_printf(p, "%10u ", irq_stats(j)->apic_timer_irqs);
  66         seq_printf(p, "  Local timer interrupts\n");
  67
  68         seq_printf(p, "%*s: ", prec, "SPU");
  69         for_each_online_cpu(j)
  70                 seq_printf(p, "%10u ", irq_stats(j)->irq_spurious_count);
  71         seq_printf(p, "  Spurious interrupts\n");
  72         seq_printf(p, "%*s: ", prec, "PMI");
  73         for_each_online_cpu(j)
  74                 seq_printf(p, "%10u ", irq_stats(j)->apic_perf_irqs);
  75         seq_printf(p, "  Performance monitoring interrupts\n");
  76         seq_printf(p, "%*s: ", prec, "IWI");
  77         for_each_online_cpu(j)
  78                 seq_printf(p, "%10u ", irq_stats(j)->apic_irq_work_irqs);
  79         seq_printf(p, "  IRQ work interrupts\n");
  80         seq_printf(p, "%*s: ", prec, "RTR");
  81         for_each_online_cpu(j)
  82                 seq_printf(p, "%10u ", irq_stats(j)->icr_read_retry_count);
  83         seq_printf(p, "  APIC ICR read retries\n");
  84 #endif
  85         if (x86_platform_ipi_callback) {
  86                 seq_printf(p, "%*s: ", prec, "PLT");
  87                 for_each_online_cpu(j)
  88                         seq_printf(p, "%10u ", irq_stats(j)->x86_platform_ipis);
  89                 seq_printf(p, "  Platform interrupts\n");
  90         }
  91 #ifdef CONFIG_SMP
  92         seq_printf(p, "%*s: ", prec, "RES");
  93         for_each_online_cpu(j)
  94                 seq_printf(p, "%10u ", irq_stats(j)->irq_resched_count);
  95         seq_printf(p, "  Rescheduling interrupts\n");
  96         seq_printf(p, "%*s: ", prec, "CAL");
  97         for_each_online_cpu(j)
  98                 seq_printf(p, "%10u ", irq_stats(j)->irq_call_count -
  99                                         irq_stats(j)->irq_tlb_count);
 100         seq_printf(p, "  Function call interrupts\n");
 101         seq_printf(p, "%*s: ", prec, "TLB");
 102         for_each_online_cpu(j)
 103                 seq_printf(p, "%10u ", irq_stats(j)->irq_tlb_count);
 104         seq_printf(p, "  TLB shootdowns\n");
 105 #endif
 106 #ifdef CONFIG_X86_THERMAL_VECTOR
 107         seq_printf(p, "%*s: ", prec, "TRM");
 108         for_each_online_cpu(j)
 109                 seq_printf(p, "%10u ", irq_stats(j)->irq_thermal_count);
 110         seq_printf(p, "  Thermal event interrupts\n");
 111 #endif
 112 #ifdef CONFIG_X86_MCE_THRESHOLD
 113         seq_printf(p, "%*s: ", prec, "THR");
 114         for_each_online_cpu(j)
 115                 seq_printf(p, "%10u ", irq_stats(j)->irq_threshold_count);
 116         seq_printf(p, "  Threshold APIC interrupts\n");
 117 #endif
 118 #ifdef CONFIG_X86_MCE
 119         seq_printf(p, "%*s: ", prec, "MCE");
 120         for_each_online_cpu(j)
 121                 seq_printf(p, "%10u ", per_cpu(mce_exception_count, j));
 122         seq_printf(p, "  Machine check exceptions\n");
 123         seq_printf(p, "%*s: ", prec, "MCP");
 124         for_each_online_cpu(j)
 125                 seq_printf(p, "%10u ", per_cpu(mce_poll_count, j));
 126         seq_printf(p, "  Machine check polls\n");
 127 #endif
 128         seq_printf(p, "%*s: %10u\n", prec, "ERR", atomic_read(&irq_err_count));
 129 #if defined(CONFIG_X86_IO_APIC)
 130         seq_printf(p, "%*s: %10u\n", prec, "MIS", atomic_read(&irq_mis_count));
 131 #endif
 132         return 0;
 133 }
 134
 135 /*
 136  * /proc/stat helpers
 137  */
 138 u64 arch_irq_stat_cpu(unsigned int cpu)
 139 {
 140         u64 sum = irq_stats(cpu)->__nmi_count;
 141
 142 #ifdef CONFIG_X86_LOCAL_APIC
 143         sum += irq_stats(cpu)->apic_timer_irqs;
 144         sum += irq_stats(cpu)->irq_spurious_count;
 145         sum += irq_stats(cpu)->apic_perf_irqs;
 146         sum += irq_stats(cpu)->apic_irq_work_irqs;
 147         sum += irq_stats(cpu)->icr_read_retry_count;
 148 #endif
 149         if (x86_platform_ipi_callback)
 150                 sum += irq_stats(cpu)->x86_platform_ipis;
 151 #ifdef CONFIG_SMP
 152         sum += irq_stats(cpu)->irq_resched_count;
 153         sum += irq_stats(cpu)->irq_call_count;
 154 #endif
 155 #ifdef CONFIG_X86_THERMAL_VECTOR
 156         sum += irq_stats(cpu)->irq_thermal_count;
 157 #endif
 158 #ifdef CONFIG_X86_MCE_THRESHOLD
 159         sum += irq_stats(cpu)->irq_threshold_count;
 160 #endif
 161 #ifdef CONFIG_X86_MCE
 162         sum += per_cpu(mce_exception_count, cpu);
 163         sum += per_cpu(mce_poll_count, cpu);
 164 #endif
 165         return sum;
 166 }
 167
 168 u64 arch_irq_stat(void)
 169 {
 170         u64 sum = atomic_read(&irq_err_count);
 171         return sum;
 172 }
 173
 174
 175 /*
 176  * do_IRQ handles all normal device IRQ's (the special
 177  * SMP cross-CPU interrupts have their own specific
 178  * handlers).
 179  */
 180 __visible unsigned int __irq_entry do_IRQ(struct pt_regs *regs)
 181 {
 182         struct pt_regs *old_regs = set_irq_regs(regs);
 183
 184         /* high bit used in ret_from_ code  */
 185         unsigned vector = ~regs->orig_ax;
 186         unsigned irq;
 187
 188         irq_enter();
 189         exit_idle();
 190
 191         irq = __this_cpu_read(vector_irq[vector]);
 192
 193         if (!handle_irq(irq, regs)) {
 194                 ack_APIC_irq();
 195
 196                 if (irq != VECTOR_RETRIGGERED) {
 197                         pr_emerg_ratelimited("%s: %d.%d No irq handler for vector (irq %d)\n",
 198                                              __func__, smp_processor_id(),
 199                                              vector, irq);
 200                 } else {
 201                         __this_cpu_write(vector_irq[vector], VECTOR_UNDEFINED);
 202                 }
 203         }
 204
 205         irq_exit();
 206
 207         set_irq_regs(old_regs);
 208         return 1;
 209 }
 210
 211 /*
 212  * Handler for X86_PLATFORM_IPI_VECTOR.
 213  */
 214 void __smp_x86_platform_ipi(void)
 215 {
 216         inc_irq_stat(x86_platform_ipis);
 217
 218         if (x86_platform_ipi_callback)
 219                 x86_platform_ipi_callback();
 220 }
 221
 222 __visible void smp_x86_platform_ipi(struct pt_regs *regs)
 223 {
 224         struct pt_regs *old_regs = set_irq_regs(regs);
 225
 226         entering_ack_irq();
 227         __smp_x86_platform_ipi();
 228         exiting_irq();
 229         set_irq_regs(old_regs);
 230 }
 231
 232 #ifdef CONFIG_HAVE_KVM
 233 /*
 234  * Handler for POSTED_INTERRUPT_VECTOR.
 235  */
 236 __visible void smp_kvm_posted_intr_ipi(struct pt_regs *regs)
 237 {
 238         struct pt_regs *old_regs = set_irq_regs(regs);
 239
 240         ack_APIC_irq();
 241
 242         irq_enter();
 243
 244         exit_idle();
 245
 246         inc_irq_stat(kvm_posted_intr_ipis);
 247
 248         irq_exit();
 249
 250         set_irq_regs(old_regs);
 251 }
 252 #endif
 253
 254 __visible void smp_trace_x86_platform_ipi(struct pt_regs *regs)
 255 {
 256         struct pt_regs *old_regs = set_irq_regs(regs);
 257
 258         entering_ack_irq();
 259         trace_x86_platform_ipi_entry(X86_PLATFORM_IPI_VECTOR);
 260         __smp_x86_platform_ipi();
 261         trace_x86_platform_ipi_exit(X86_PLATFORM_IPI_VECTOR);
 262         exiting_irq();
 263         set_irq_regs(old_regs);
 264 }
 265
 266 EXPORT_SYMBOL_GPL(vector_used_by_percpu_irq);
 267
 268 #ifdef CONFIG_HOTPLUG_CPU
 269 /*
 270  * This cpu is going to be removed and its vectors migrated to the remaining
 271  * online cpus.  Check to see if there are enough vectors in the remaining cpus.
 272  * This function is protected by stop_machine().
 273  */
 274 int check_irq_vectors_for_cpu_disable(void)
 275 {
 276         int irq, cpu;
 277         unsigned int this_cpu, vector, this_count, count;
 278         struct irq_desc *desc;
 279         struct irq_data *data;
 280         struct cpumask affinity_new, online_new;
 281
 282         this_cpu = smp_processor_id();
 283         cpumask_copy(&online_new, cpu_online_mask);
 284         cpu_clear(this_cpu, online_new);
 285
 286         this_count = 0;
 287         for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
 288                 irq = __this_cpu_read(vector_irq[vector]);
 289                 if (irq >= 0) {
 290                         desc = irq_to_desc(irq);
 291                         data = irq_desc_get_irq_data(desc);
 292                         cpumask_copy(&affinity_new, data->affinity);
 293                         cpu_clear(this_cpu, affinity_new);
 294
 295                         /* Do not count inactive or per-cpu irqs. */
 296                         if (!irq_has_action(irq) || irqd_is_per_cpu(data))
 297                                 continue;
 298
 299                         /*
 300                          * A single irq may be mapped to multiple
 301                          * cpu's vector_irq[] (for example IOAPIC cluster
 302                          * mode).  In this case we have two
 303                          * possibilities:
 304                          *
 305                          * 1) the resulting affinity mask is empty; that is
 306                          * this the down'd cpu is the last cpu in the irq's
 307                          * affinity mask, or
 308                          *
 309                          * 2) the resulting affinity mask is no longer
 310                          * a subset of the online cpus but the affinity
 311                          * mask is not zero; that is the down'd cpu is the
 312                          * last online cpu in a user set affinity mask.
 313                          */
 314                         if (cpumask_empty(&affinity_new) ||
 315                             !cpumask_subset(&affinity_new, &online_new))
 316                                 this_count++;
 317                 }
 318         }
 319
 320         count = 0;
 321         for_each_online_cpu(cpu) {
 322                 if (cpu == this_cpu)
 323                         continue;
 324                 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
 325                      vector++) {
 326                         if (per_cpu(vector_irq, cpu)[vector] < 0)
 327                                 count++;
 328                 }
 329         }
 330
 331         if (count < this_count) {
 332                 pr_warn("CPU %d disable failed: CPU has %u vectors assigned and there are only %u available.\n",
 333                         this_cpu, this_count, count);
 334                 return -ERANGE;
 335         }
 336         return 0;
 337 }
 338
 339 /* A cpu has been removed from cpu_online_mask.  Reset irq affinities. */
 340 void fixup_irqs(void)
 341 {
 342         unsigned int irq, vector;
 343         static int warned;
 344         struct irq_desc *desc;
 345         struct irq_data *data;
 346         struct irq_chip *chip;
 347
 348         for_each_irq_desc(irq, desc) {
 349                 int break_affinity = 0;
 350                 int set_affinity = 1;
 351                 const struct cpumask *affinity;
 352
 353                 if (!desc)
 354                         continue;
 355                 if (irq == 2)
 356                         continue;
 357
 358                 /* interrupt's are disabled at this point */
 359                 raw_spin_lock(&desc->lock);
 360
 361                 data = irq_desc_get_irq_data(desc);
 362                 affinity = data->affinity;
 363                 if (!irq_has_action(irq) || irqd_is_per_cpu(data) ||
 364                     cpumask_subset(affinity, cpu_online_mask)) {
 365                         raw_spin_unlock(&desc->lock);
 366                         continue;
 367                 }
 368
 369                 /*
 370                  * Complete the irq move. This cpu is going down and for
 371                  * non intr-remapping case, we can't wait till this interrupt
 372                  * arrives at this cpu before completing the irq move.
 373                  */
 374                 irq_force_complete_move(irq);
 375
 376                 if (cpumask_any_and(affinity, cpu_online_mask) >= nr_cpu_ids) {
 377                         break_affinity = 1;
 378                         affinity = cpu_online_mask;
 379                 }
 380
 381                 chip = irq_data_get_irq_chip(data);
 382                 if (!irqd_can_move_in_process_context(data) && chip->irq_mask)
 383                         chip->irq_mask(data);
 384
 385                 if (chip->irq_set_affinity)
 386                         chip->irq_set_affinity(data, affinity, true);
 387                 else if (!(warned++))
 388                         set_affinity = 0;
 389
 390                 /*
 391                  * We unmask if the irq was not marked masked by the
 392                  * core code. That respects the lazy irq disable
 393                  * behaviour.
 394                  */
 395                 if (!irqd_can_move_in_process_context(data) &&
 396                     !irqd_irq_masked(data) && chip->irq_unmask)
 397                         chip->irq_unmask(data);
 398
 399                 raw_spin_unlock(&desc->lock);
 400
 401                 if (break_affinity && set_affinity)
 402                         pr_notice("Broke affinity for irq %i\n", irq);
 403                 else if (!set_affinity)
 404                         pr_notice("Cannot set affinity for irq %i\n", irq);
 405         }
 406
 407         /*
 408          * We can remove mdelay() and then send spuriuous interrupts to
 409          * new cpu targets for all the irqs that were handled previously by
 410          * this cpu. While it works, I have seen spurious interrupt messages
 411          * (nothing wrong but still...).
 412          *
 413          * So for now, retain mdelay(1) and check the IRR and then send those
 414          * interrupts to new targets as this cpu is already offlined...
 415          */
 416         mdelay(1);
 417
 418         for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
 419                 unsigned int irr;
 420
 421                 if (__this_cpu_read(vector_irq[vector]) <= VECTOR_UNDEFINED)
 422                         continue;
 423
 424                 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
 425                 if (irr  & (1 << (vector % 32))) {
 426                         irq = __this_cpu_read(vector_irq[vector]);
 427
 428                         desc = irq_to_desc(irq);
 429                         data = irq_desc_get_irq_data(desc);
 430                         chip = irq_data_get_irq_chip(data);
 431                         raw_spin_lock(&desc->lock);
 432                         if (chip->irq_retrigger) {
 433                                 chip->irq_retrigger(data);
 434                                 __this_cpu_write(vector_irq[vector], VECTOR_RETRIGGERED);
 435                         }
 436                         raw_spin_unlock(&desc->lock);
 437                 }
 438                 if (__this_cpu_read(vector_irq[vector]) != VECTOR_RETRIGGERED)
 439                         __this_cpu_write(vector_irq[vector], VECTOR_UNDEFINED);
 440         }
 441 }
 442 #endif