2 * Kernel-based Virtual Machine driver for Linux
6 * Copyright (C) 2006 Qumranet, Inc.
9 * Yaniv Kamay <yaniv@qumranet.com>
10 * Avi Kivity <avi@qumranet.com>
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
16 #include <linux/kvm_host.h>
20 #include "kvm_cache_regs.h"
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/vmalloc.h>
26 #include <linux/highmem.h>
27 #include <linux/sched.h>
28 #include <linux/ftrace_event.h>
32 #include <asm/virtext.h>
35 #define __ex(x) __kvm_handle_fault_on_reboot(x)
37 MODULE_AUTHOR("Qumranet");
38 MODULE_LICENSE("GPL");
40 #define IOPM_ALLOC_ORDER 2
41 #define MSRPM_ALLOC_ORDER 1
43 #define SEG_TYPE_LDT 2
44 #define SEG_TYPE_BUSY_TSS16 3
46 #define SVM_FEATURE_NPT (1 << 0)
47 #define SVM_FEATURE_LBRV (1 << 1)
48 #define SVM_FEATURE_SVML (1 << 2)
50 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
52 /* Turn on to get debugging output*/
53 /* #define NESTED_DEBUG */
56 #define nsvm_printk(fmt, args...) printk(KERN_INFO fmt, ## args)
58 #define nsvm_printk(fmt, args...) do {} while(0)
61 static const u32 host_save_user_msrs[] = {
63 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
66 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
69 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
78 /* These are the merged vectors */
81 /* gpa pointers to the real vectors */
84 /* cache for intercepts of the guest */
85 u16 intercept_cr_read;
86 u16 intercept_cr_write;
87 u16 intercept_dr_read;
88 u16 intercept_dr_write;
89 u32 intercept_exceptions;
97 unsigned long vmcb_pa;
98 struct svm_cpu_data *svm_data;
99 uint64_t asid_generation;
100 uint64_t sysenter_esp;
101 uint64_t sysenter_eip;
105 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
110 struct nested_state nested;
113 /* enable NPT for AMD64 and X86 with PAE */
114 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
115 static bool npt_enabled = true;
117 static bool npt_enabled = false;
121 module_param(npt, int, S_IRUGO);
123 static int nested = 0;
124 module_param(nested, int, S_IRUGO);
126 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
127 static void svm_complete_interrupts(struct vcpu_svm *svm);
129 static int nested_svm_exit_handled(struct vcpu_svm *svm, bool kvm_override);
130 static int nested_svm_vmexit(struct vcpu_svm *svm);
131 static int nested_svm_vmsave(struct vcpu_svm *svm, void *nested_vmcb,
132 void *arg2, void *opaque);
133 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
134 bool has_error_code, u32 error_code);
136 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
138 return container_of(vcpu, struct vcpu_svm, vcpu);
141 static inline bool is_nested(struct vcpu_svm *svm)
143 return svm->nested.vmcb;
146 static inline void enable_gif(struct vcpu_svm *svm)
148 svm->vcpu.arch.hflags |= HF_GIF_MASK;
151 static inline void disable_gif(struct vcpu_svm *svm)
153 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
156 static inline bool gif_set(struct vcpu_svm *svm)
158 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
161 static unsigned long iopm_base;
163 struct kvm_ldttss_desc {
166 unsigned base1 : 8, type : 5, dpl : 2, p : 1;
167 unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
170 } __attribute__((packed));
172 struct svm_cpu_data {
178 struct kvm_ldttss_desc *tss_desc;
180 struct page *save_area;
183 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
184 static uint32_t svm_features;
186 struct svm_init_data {
191 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
193 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
194 #define MSRS_RANGE_SIZE 2048
195 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
197 #define MAX_INST_SIZE 15
199 static inline u32 svm_has(u32 feat)
201 return svm_features & feat;
204 static inline void clgi(void)
206 asm volatile (__ex(SVM_CLGI));
209 static inline void stgi(void)
211 asm volatile (__ex(SVM_STGI));
214 static inline void invlpga(unsigned long addr, u32 asid)
216 asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid));
219 static inline void force_new_asid(struct kvm_vcpu *vcpu)
221 to_svm(vcpu)->asid_generation--;
224 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
226 force_new_asid(vcpu);
229 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
231 if (!npt_enabled && !(efer & EFER_LMA))
234 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
235 vcpu->arch.shadow_efer = efer;
238 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
239 bool has_error_code, u32 error_code)
241 struct vcpu_svm *svm = to_svm(vcpu);
243 /* If we are within a nested VM we'd better #VMEXIT and let the
244 guest handle the exception */
245 if (nested_svm_check_exception(svm, nr, has_error_code, error_code))
248 svm->vmcb->control.event_inj = nr
250 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
251 | SVM_EVTINJ_TYPE_EXEPT;
252 svm->vmcb->control.event_inj_err = error_code;
255 static int is_external_interrupt(u32 info)
257 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
258 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
261 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
263 struct vcpu_svm *svm = to_svm(vcpu);
266 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
267 ret |= X86_SHADOW_INT_STI | X86_SHADOW_INT_MOV_SS;
271 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
273 struct vcpu_svm *svm = to_svm(vcpu);
276 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
278 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
282 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
284 struct vcpu_svm *svm = to_svm(vcpu);
286 if (!svm->next_rip) {
287 if (emulate_instruction(vcpu, vcpu->run, 0, 0, EMULTYPE_SKIP) !=
289 printk(KERN_DEBUG "%s: NOP\n", __func__);
292 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
293 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
294 __func__, kvm_rip_read(vcpu), svm->next_rip);
296 kvm_rip_write(vcpu, svm->next_rip);
297 svm_set_interrupt_shadow(vcpu, 0);
300 static int has_svm(void)
304 if (!cpu_has_svm(&msg)) {
305 printk(KERN_INFO "has_svm: %s\n", msg);
312 static void svm_hardware_disable(void *garbage)
317 static void svm_hardware_enable(void *garbage)
320 struct svm_cpu_data *svm_data;
322 struct descriptor_table gdt_descr;
323 struct desc_struct *gdt;
324 int me = raw_smp_processor_id();
327 printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me);
330 svm_data = per_cpu(svm_data, me);
333 printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n",
338 svm_data->asid_generation = 1;
339 svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
340 svm_data->next_asid = svm_data->max_asid + 1;
342 kvm_get_gdt(&gdt_descr);
343 gdt = (struct desc_struct *)gdt_descr.base;
344 svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
346 rdmsrl(MSR_EFER, efer);
347 wrmsrl(MSR_EFER, efer | EFER_SVME);
349 wrmsrl(MSR_VM_HSAVE_PA,
350 page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
353 static void svm_cpu_uninit(int cpu)
355 struct svm_cpu_data *svm_data
356 = per_cpu(svm_data, raw_smp_processor_id());
361 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
362 __free_page(svm_data->save_area);
366 static int svm_cpu_init(int cpu)
368 struct svm_cpu_data *svm_data;
371 svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
375 svm_data->save_area = alloc_page(GFP_KERNEL);
377 if (!svm_data->save_area)
380 per_cpu(svm_data, cpu) = svm_data;
390 static void set_msr_interception(u32 *msrpm, unsigned msr,
395 for (i = 0; i < NUM_MSR_MAPS; i++) {
396 if (msr >= msrpm_ranges[i] &&
397 msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
398 u32 msr_offset = (i * MSRS_IN_RANGE + msr -
399 msrpm_ranges[i]) * 2;
401 u32 *base = msrpm + (msr_offset / 32);
402 u32 msr_shift = msr_offset % 32;
403 u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
404 *base = (*base & ~(0x3 << msr_shift)) |
412 static void svm_vcpu_init_msrpm(u32 *msrpm)
414 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
417 set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
418 set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
419 set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
420 set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
421 set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
422 set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
424 set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
425 set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
428 static void svm_enable_lbrv(struct vcpu_svm *svm)
430 u32 *msrpm = svm->msrpm;
432 svm->vmcb->control.lbr_ctl = 1;
433 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
434 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
435 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
436 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
439 static void svm_disable_lbrv(struct vcpu_svm *svm)
441 u32 *msrpm = svm->msrpm;
443 svm->vmcb->control.lbr_ctl = 0;
444 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
445 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
446 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
447 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
450 static __init int svm_hardware_setup(void)
453 struct page *iopm_pages;
457 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
462 iopm_va = page_address(iopm_pages);
463 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
464 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
466 if (boot_cpu_has(X86_FEATURE_NX))
467 kvm_enable_efer_bits(EFER_NX);
469 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
470 kvm_enable_efer_bits(EFER_FFXSR);
473 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
474 kvm_enable_efer_bits(EFER_SVME);
477 for_each_online_cpu(cpu) {
478 r = svm_cpu_init(cpu);
483 svm_features = cpuid_edx(SVM_CPUID_FUNC);
485 if (!svm_has(SVM_FEATURE_NPT))
488 if (npt_enabled && !npt) {
489 printk(KERN_INFO "kvm: Nested Paging disabled\n");
494 printk(KERN_INFO "kvm: Nested Paging enabled\n");
502 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
507 static __exit void svm_hardware_unsetup(void)
511 for_each_online_cpu(cpu)
514 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
518 static void init_seg(struct vmcb_seg *seg)
521 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
522 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
527 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
530 seg->attrib = SVM_SELECTOR_P_MASK | type;
535 static void init_vmcb(struct vcpu_svm *svm)
537 struct vmcb_control_area *control = &svm->vmcb->control;
538 struct vmcb_save_area *save = &svm->vmcb->save;
540 control->intercept_cr_read = INTERCEPT_CR0_MASK |
544 control->intercept_cr_write = INTERCEPT_CR0_MASK |
549 control->intercept_dr_read = INTERCEPT_DR0_MASK |
554 control->intercept_dr_write = INTERCEPT_DR0_MASK |
561 control->intercept_exceptions = (1 << PF_VECTOR) |
566 control->intercept = (1ULL << INTERCEPT_INTR) |
567 (1ULL << INTERCEPT_NMI) |
568 (1ULL << INTERCEPT_SMI) |
569 (1ULL << INTERCEPT_CPUID) |
570 (1ULL << INTERCEPT_INVD) |
571 (1ULL << INTERCEPT_HLT) |
572 (1ULL << INTERCEPT_INVLPG) |
573 (1ULL << INTERCEPT_INVLPGA) |
574 (1ULL << INTERCEPT_IOIO_PROT) |
575 (1ULL << INTERCEPT_MSR_PROT) |
576 (1ULL << INTERCEPT_TASK_SWITCH) |
577 (1ULL << INTERCEPT_SHUTDOWN) |
578 (1ULL << INTERCEPT_VMRUN) |
579 (1ULL << INTERCEPT_VMMCALL) |
580 (1ULL << INTERCEPT_VMLOAD) |
581 (1ULL << INTERCEPT_VMSAVE) |
582 (1ULL << INTERCEPT_STGI) |
583 (1ULL << INTERCEPT_CLGI) |
584 (1ULL << INTERCEPT_SKINIT) |
585 (1ULL << INTERCEPT_WBINVD) |
586 (1ULL << INTERCEPT_MONITOR) |
587 (1ULL << INTERCEPT_MWAIT);
589 control->iopm_base_pa = iopm_base;
590 control->msrpm_base_pa = __pa(svm->msrpm);
591 control->tsc_offset = 0;
592 control->int_ctl = V_INTR_MASKING_MASK;
600 save->cs.selector = 0xf000;
601 /* Executable/Readable Code Segment */
602 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
603 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
604 save->cs.limit = 0xffff;
606 * cs.base should really be 0xffff0000, but vmx can't handle that, so
607 * be consistent with it.
609 * Replace when we have real mode working for vmx.
611 save->cs.base = 0xf0000;
613 save->gdtr.limit = 0xffff;
614 save->idtr.limit = 0xffff;
616 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
617 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
619 save->efer = EFER_SVME;
620 save->dr6 = 0xffff0ff0;
623 save->rip = 0x0000fff0;
624 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
627 * cr0 val on cpu init should be 0x60000010, we enable cpu
628 * cache by default. the orderly way is to enable cache in bios.
630 save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP;
631 save->cr4 = X86_CR4_PAE;
635 /* Setup VMCB for Nested Paging */
636 control->nested_ctl = 1;
637 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
638 (1ULL << INTERCEPT_INVLPG));
639 control->intercept_exceptions &= ~(1 << PF_VECTOR);
640 control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK|
642 control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK|
644 save->g_pat = 0x0007040600070406ULL;
645 /* enable caching because the QEMU Bios doesn't enable it */
646 save->cr0 = X86_CR0_ET;
650 force_new_asid(&svm->vcpu);
652 svm->nested.vmcb = 0;
653 svm->vcpu.arch.hflags = 0;
658 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
660 struct vcpu_svm *svm = to_svm(vcpu);
664 if (!kvm_vcpu_is_bsp(vcpu)) {
665 kvm_rip_write(vcpu, 0);
666 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
667 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
669 vcpu->arch.regs_avail = ~0;
670 vcpu->arch.regs_dirty = ~0;
675 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
677 struct vcpu_svm *svm;
679 struct page *msrpm_pages;
680 struct page *hsave_page;
681 struct page *nested_msrpm_pages;
684 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
690 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
694 page = alloc_page(GFP_KERNEL);
701 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
705 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
706 if (!nested_msrpm_pages)
709 svm->msrpm = page_address(msrpm_pages);
710 svm_vcpu_init_msrpm(svm->msrpm);
712 hsave_page = alloc_page(GFP_KERNEL);
715 svm->nested.hsave = page_address(hsave_page);
717 svm->nested.msrpm = page_address(nested_msrpm_pages);
719 svm->vmcb = page_address(page);
720 clear_page(svm->vmcb);
721 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
722 svm->asid_generation = 0;
726 svm->vcpu.fpu_active = 1;
727 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
728 if (kvm_vcpu_is_bsp(&svm->vcpu))
729 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
734 kvm_vcpu_uninit(&svm->vcpu);
736 kmem_cache_free(kvm_vcpu_cache, svm);
741 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
743 struct vcpu_svm *svm = to_svm(vcpu);
745 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
746 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
747 __free_page(virt_to_page(svm->nested.hsave));
748 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
749 kvm_vcpu_uninit(vcpu);
750 kmem_cache_free(kvm_vcpu_cache, svm);
753 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
755 struct vcpu_svm *svm = to_svm(vcpu);
758 if (unlikely(cpu != vcpu->cpu)) {
762 * Make sure that the guest sees a monotonically
766 delta = vcpu->arch.host_tsc - tsc_this;
767 svm->vmcb->control.tsc_offset += delta;
769 kvm_migrate_timers(vcpu);
770 svm->asid_generation = 0;
773 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
774 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
777 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
779 struct vcpu_svm *svm = to_svm(vcpu);
782 ++vcpu->stat.host_state_reload;
783 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
784 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
786 rdtscll(vcpu->arch.host_tsc);
789 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
791 return to_svm(vcpu)->vmcb->save.rflags;
794 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
796 to_svm(vcpu)->vmcb->save.rflags = rflags;
799 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
802 case VCPU_EXREG_PDPTR:
803 BUG_ON(!npt_enabled);
804 load_pdptrs(vcpu, vcpu->arch.cr3);
811 static void svm_set_vintr(struct vcpu_svm *svm)
813 svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
816 static void svm_clear_vintr(struct vcpu_svm *svm)
818 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
821 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
823 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
826 case VCPU_SREG_CS: return &save->cs;
827 case VCPU_SREG_DS: return &save->ds;
828 case VCPU_SREG_ES: return &save->es;
829 case VCPU_SREG_FS: return &save->fs;
830 case VCPU_SREG_GS: return &save->gs;
831 case VCPU_SREG_SS: return &save->ss;
832 case VCPU_SREG_TR: return &save->tr;
833 case VCPU_SREG_LDTR: return &save->ldtr;
839 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
841 struct vmcb_seg *s = svm_seg(vcpu, seg);
846 static void svm_get_segment(struct kvm_vcpu *vcpu,
847 struct kvm_segment *var, int seg)
849 struct vmcb_seg *s = svm_seg(vcpu, seg);
852 var->limit = s->limit;
853 var->selector = s->selector;
854 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
855 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
856 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
857 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
858 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
859 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
860 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
861 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
863 /* AMD's VMCB does not have an explicit unusable field, so emulate it
864 * for cross vendor migration purposes by "not present"
866 var->unusable = !var->present || (var->type == 0);
871 * SVM always stores 0 for the 'G' bit in the CS selector in
872 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
873 * Intel's VMENTRY has a check on the 'G' bit.
875 var->g = s->limit > 0xfffff;
879 * Work around a bug where the busy flag in the tr selector
889 * The accessed bit must always be set in the segment
890 * descriptor cache, although it can be cleared in the
891 * descriptor, the cached bit always remains at 1. Since
892 * Intel has a check on this, set it here to support
893 * cross-vendor migration.
899 /* On AMD CPUs sometimes the DB bit in the segment
900 * descriptor is left as 1, although the whole segment has
901 * been made unusable. Clear it here to pass an Intel VMX
902 * entry check when cross vendor migrating.
910 static int svm_get_cpl(struct kvm_vcpu *vcpu)
912 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
917 static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
919 struct vcpu_svm *svm = to_svm(vcpu);
921 dt->limit = svm->vmcb->save.idtr.limit;
922 dt->base = svm->vmcb->save.idtr.base;
925 static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
927 struct vcpu_svm *svm = to_svm(vcpu);
929 svm->vmcb->save.idtr.limit = dt->limit;
930 svm->vmcb->save.idtr.base = dt->base ;
933 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
935 struct vcpu_svm *svm = to_svm(vcpu);
937 dt->limit = svm->vmcb->save.gdtr.limit;
938 dt->base = svm->vmcb->save.gdtr.base;
941 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
943 struct vcpu_svm *svm = to_svm(vcpu);
945 svm->vmcb->save.gdtr.limit = dt->limit;
946 svm->vmcb->save.gdtr.base = dt->base ;
949 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
953 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
955 struct vcpu_svm *svm = to_svm(vcpu);
958 if (vcpu->arch.shadow_efer & EFER_LME) {
959 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
960 vcpu->arch.shadow_efer |= EFER_LMA;
961 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
964 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
965 vcpu->arch.shadow_efer &= ~EFER_LMA;
966 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
973 if ((vcpu->arch.cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) {
974 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
975 vcpu->fpu_active = 1;
978 vcpu->arch.cr0 = cr0;
979 cr0 |= X86_CR0_PG | X86_CR0_WP;
980 if (!vcpu->fpu_active) {
981 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
986 * re-enable caching here because the QEMU bios
987 * does not do it - this results in some delay at
990 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
991 svm->vmcb->save.cr0 = cr0;
994 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
996 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
997 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
999 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1000 force_new_asid(vcpu);
1002 vcpu->arch.cr4 = cr4;
1005 cr4 |= host_cr4_mce;
1006 to_svm(vcpu)->vmcb->save.cr4 = cr4;
1009 static void svm_set_segment(struct kvm_vcpu *vcpu,
1010 struct kvm_segment *var, int seg)
1012 struct vcpu_svm *svm = to_svm(vcpu);
1013 struct vmcb_seg *s = svm_seg(vcpu, seg);
1015 s->base = var->base;
1016 s->limit = var->limit;
1017 s->selector = var->selector;
1021 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1022 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1023 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1024 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1025 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1026 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1027 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1028 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1030 if (seg == VCPU_SREG_CS)
1032 = (svm->vmcb->save.cs.attrib
1033 >> SVM_SELECTOR_DPL_SHIFT) & 3;
1037 static void update_db_intercept(struct kvm_vcpu *vcpu)
1039 struct vcpu_svm *svm = to_svm(vcpu);
1041 svm->vmcb->control.intercept_exceptions &=
1042 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
1044 if (vcpu->arch.singlestep)
1045 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1047 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1048 if (vcpu->guest_debug &
1049 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1050 svm->vmcb->control.intercept_exceptions |=
1052 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1053 svm->vmcb->control.intercept_exceptions |=
1056 vcpu->guest_debug = 0;
1059 static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1061 int old_debug = vcpu->guest_debug;
1062 struct vcpu_svm *svm = to_svm(vcpu);
1064 vcpu->guest_debug = dbg->control;
1066 update_db_intercept(vcpu);
1068 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1069 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1071 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1073 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
1074 svm->vmcb->save.rflags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1075 else if (old_debug & KVM_GUESTDBG_SINGLESTEP)
1076 svm->vmcb->save.rflags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1081 static void load_host_msrs(struct kvm_vcpu *vcpu)
1083 #ifdef CONFIG_X86_64
1084 wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1088 static void save_host_msrs(struct kvm_vcpu *vcpu)
1090 #ifdef CONFIG_X86_64
1091 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1095 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data)
1097 if (svm_data->next_asid > svm_data->max_asid) {
1098 ++svm_data->asid_generation;
1099 svm_data->next_asid = 1;
1100 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1103 svm->asid_generation = svm_data->asid_generation;
1104 svm->vmcb->control.asid = svm_data->next_asid++;
1107 static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
1109 struct vcpu_svm *svm = to_svm(vcpu);
1114 val = vcpu->arch.db[dr];
1117 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1118 val = vcpu->arch.dr6;
1120 val = svm->vmcb->save.dr6;
1123 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1124 val = vcpu->arch.dr7;
1126 val = svm->vmcb->save.dr7;
1135 static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
1138 struct vcpu_svm *svm = to_svm(vcpu);
1144 vcpu->arch.db[dr] = value;
1145 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1146 vcpu->arch.eff_db[dr] = value;
1149 if (vcpu->arch.cr4 & X86_CR4_DE)
1150 *exception = UD_VECTOR;
1153 if (value & 0xffffffff00000000ULL) {
1154 *exception = GP_VECTOR;
1157 vcpu->arch.dr6 = (value & DR6_VOLATILE) | DR6_FIXED_1;
1160 if (value & 0xffffffff00000000ULL) {
1161 *exception = GP_VECTOR;
1164 vcpu->arch.dr7 = (value & DR7_VOLATILE) | DR7_FIXED_1;
1165 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1166 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1167 vcpu->arch.switch_db_regs = (value & DR7_BP_EN_MASK);
1171 /* FIXME: Possible case? */
1172 printk(KERN_DEBUG "%s: unexpected dr %u\n",
1174 *exception = UD_VECTOR;
1179 static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1184 fault_address = svm->vmcb->control.exit_info_2;
1185 error_code = svm->vmcb->control.exit_info_1;
1187 trace_kvm_page_fault(fault_address, error_code);
1189 * FIXME: Tis shouldn't be necessary here, but there is a flush
1190 * missing in the MMU code. Until we find this bug, flush the
1191 * complete TLB here on an NPF
1194 svm_flush_tlb(&svm->vcpu);
1196 if (kvm_event_needs_reinjection(&svm->vcpu))
1197 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1199 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1202 static int db_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1204 if (!(svm->vcpu.guest_debug &
1205 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1206 !svm->vcpu.arch.singlestep) {
1207 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1211 if (svm->vcpu.arch.singlestep) {
1212 svm->vcpu.arch.singlestep = false;
1213 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1214 svm->vmcb->save.rflags &=
1215 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1216 update_db_intercept(&svm->vcpu);
1219 if (svm->vcpu.guest_debug &
1220 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)){
1221 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1222 kvm_run->debug.arch.pc =
1223 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1224 kvm_run->debug.arch.exception = DB_VECTOR;
1231 static int bp_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1233 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1234 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1235 kvm_run->debug.arch.exception = BP_VECTOR;
1239 static int ud_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1243 er = emulate_instruction(&svm->vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
1244 if (er != EMULATE_DONE)
1245 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1249 static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1251 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
1252 if (!(svm->vcpu.arch.cr0 & X86_CR0_TS))
1253 svm->vmcb->save.cr0 &= ~X86_CR0_TS;
1254 svm->vcpu.fpu_active = 1;
1259 static int mc_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1262 * On an #MC intercept the MCE handler is not called automatically in
1263 * the host. So do it by hand here.
1267 /* not sure if we ever come back to this point */
1272 static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1275 * VMCB is undefined after a SHUTDOWN intercept
1276 * so reinitialize it.
1278 clear_page(svm->vmcb);
1281 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1285 static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1287 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1288 int size, in, string;
1291 ++svm->vcpu.stat.io_exits;
1293 svm->next_rip = svm->vmcb->control.exit_info_2;
1295 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1298 if (emulate_instruction(&svm->vcpu,
1299 kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
1304 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1305 port = io_info >> 16;
1306 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1308 skip_emulated_instruction(&svm->vcpu);
1309 return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port);
1312 static int nmi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1317 static int intr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1319 ++svm->vcpu.stat.irq_exits;
1323 static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1328 static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1330 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1331 skip_emulated_instruction(&svm->vcpu);
1332 return kvm_emulate_halt(&svm->vcpu);
1335 static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1337 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1338 skip_emulated_instruction(&svm->vcpu);
1339 kvm_emulate_hypercall(&svm->vcpu);
1343 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1345 if (!(svm->vcpu.arch.shadow_efer & EFER_SVME)
1346 || !is_paging(&svm->vcpu)) {
1347 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1351 if (svm->vmcb->save.cpl) {
1352 kvm_inject_gp(&svm->vcpu, 0);
1359 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1360 bool has_error_code, u32 error_code)
1362 if (!is_nested(svm))
1365 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1366 svm->vmcb->control.exit_code_hi = 0;
1367 svm->vmcb->control.exit_info_1 = error_code;
1368 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1370 return nested_svm_exit_handled(svm, false);
1373 static inline int nested_svm_intr(struct vcpu_svm *svm)
1375 if (is_nested(svm)) {
1376 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1379 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1382 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1384 if (nested_svm_exit_handled(svm, false)) {
1385 nsvm_printk("VMexit -> INTR\n");
1393 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, enum km_type idx)
1397 down_read(¤t->mm->mmap_sem);
1398 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1399 up_read(¤t->mm->mmap_sem);
1401 if (is_error_page(page))
1404 return kmap_atomic(page, idx);
1407 kvm_release_page_clean(page);
1408 kvm_inject_gp(&svm->vcpu, 0);
1413 static void nested_svm_unmap(void *addr, enum km_type idx)
1420 page = kmap_atomic_to_page(addr);
1422 kunmap_atomic(addr, idx);
1423 kvm_release_page_dirty(page);
1426 static struct page *nested_svm_get_page(struct vcpu_svm *svm, u64 gpa)
1430 down_read(¤t->mm->mmap_sem);
1431 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1432 up_read(¤t->mm->mmap_sem);
1434 if (is_error_page(page)) {
1435 printk(KERN_INFO "%s: could not find page at 0x%llx\n",
1437 kvm_release_page_clean(page);
1438 kvm_inject_gp(&svm->vcpu, 0);
1444 static int nested_svm_do(struct vcpu_svm *svm,
1445 u64 arg1_gpa, u64 arg2_gpa, void *opaque,
1446 int (*handler)(struct vcpu_svm *svm,
1451 struct page *arg1_page;
1452 struct page *arg2_page = NULL;
1457 arg1_page = nested_svm_get_page(svm, arg1_gpa);
1458 if(arg1_page == NULL)
1462 arg2_page = nested_svm_get_page(svm, arg2_gpa);
1463 if(arg2_page == NULL) {
1464 kvm_release_page_clean(arg1_page);
1469 arg1 = kmap_atomic(arg1_page, KM_USER0);
1471 arg2 = kmap_atomic(arg2_page, KM_USER1);
1473 retval = handler(svm, arg1, arg2, opaque);
1475 kunmap_atomic(arg1, KM_USER0);
1477 kunmap_atomic(arg2, KM_USER1);
1479 kvm_release_page_dirty(arg1_page);
1481 kvm_release_page_dirty(arg2_page);
1486 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm,
1487 void *arg1, void *arg2,
1490 struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1491 u8 *msrpm = (u8 *)arg2;
1493 u32 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1494 u32 param = svm->vmcb->control.exit_info_1 & 1;
1496 if (!(nested_vmcb->control.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1504 case 0xc0000000 ... 0xc0001fff:
1505 t0 = (8192 + msr - 0xc0000000) * 2;
1509 case 0xc0010000 ... 0xc0011fff:
1510 t0 = (16384 + msr - 0xc0010000) * 2;
1518 if (msrpm[t1] & ((1 << param) << t0))
1524 static int nested_svm_exit_handled(struct vcpu_svm *svm, bool kvm_override)
1526 u32 exit_code = svm->vmcb->control.exit_code;
1527 bool vmexit = false;
1530 switch (exit_code) {
1534 /* For now we are always handling NPFs when using them */
1539 /* When we're shadowing, trap PFs */
1540 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1549 switch (exit_code) {
1551 if (nested_svm_do(svm, svm->nested.vmcb, svm->nested.vmcb_msrpm,
1552 NULL, nested_svm_exit_handled_msr))
1555 case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1556 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
1557 if (svm->nested.intercept_cr_read & cr_bits)
1561 case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1562 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
1563 if (svm->nested.intercept_cr_write & cr_bits)
1567 case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1568 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
1569 if (svm->nested.intercept_dr_read & dr_bits)
1573 case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1574 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
1575 if (svm->nested.intercept_dr_write & dr_bits)
1579 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1580 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
1581 if (svm->nested.intercept_exceptions & excp_bits)
1586 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
1587 nsvm_printk("exit code: 0x%x\n", exit_code);
1588 if (svm->nested.intercept & exit_bits)
1594 nsvm_printk("#VMEXIT reason=%04x\n", exit_code);
1595 nested_svm_vmexit(svm);
1601 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
1603 struct vmcb_control_area *dst = &dst_vmcb->control;
1604 struct vmcb_control_area *from = &from_vmcb->control;
1606 dst->intercept_cr_read = from->intercept_cr_read;
1607 dst->intercept_cr_write = from->intercept_cr_write;
1608 dst->intercept_dr_read = from->intercept_dr_read;
1609 dst->intercept_dr_write = from->intercept_dr_write;
1610 dst->intercept_exceptions = from->intercept_exceptions;
1611 dst->intercept = from->intercept;
1612 dst->iopm_base_pa = from->iopm_base_pa;
1613 dst->msrpm_base_pa = from->msrpm_base_pa;
1614 dst->tsc_offset = from->tsc_offset;
1615 dst->asid = from->asid;
1616 dst->tlb_ctl = from->tlb_ctl;
1617 dst->int_ctl = from->int_ctl;
1618 dst->int_vector = from->int_vector;
1619 dst->int_state = from->int_state;
1620 dst->exit_code = from->exit_code;
1621 dst->exit_code_hi = from->exit_code_hi;
1622 dst->exit_info_1 = from->exit_info_1;
1623 dst->exit_info_2 = from->exit_info_2;
1624 dst->exit_int_info = from->exit_int_info;
1625 dst->exit_int_info_err = from->exit_int_info_err;
1626 dst->nested_ctl = from->nested_ctl;
1627 dst->event_inj = from->event_inj;
1628 dst->event_inj_err = from->event_inj_err;
1629 dst->nested_cr3 = from->nested_cr3;
1630 dst->lbr_ctl = from->lbr_ctl;
1633 static int nested_svm_vmexit(struct vcpu_svm *svm)
1635 struct vmcb *nested_vmcb;
1636 struct vmcb *hsave = svm->nested.hsave;
1637 struct vmcb *vmcb = svm->vmcb;
1639 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, KM_USER0);
1643 /* Give the current vmcb to the guest */
1646 nested_vmcb->save.es = vmcb->save.es;
1647 nested_vmcb->save.cs = vmcb->save.cs;
1648 nested_vmcb->save.ss = vmcb->save.ss;
1649 nested_vmcb->save.ds = vmcb->save.ds;
1650 nested_vmcb->save.gdtr = vmcb->save.gdtr;
1651 nested_vmcb->save.idtr = vmcb->save.idtr;
1653 nested_vmcb->save.cr3 = vmcb->save.cr3;
1654 nested_vmcb->save.cr2 = vmcb->save.cr2;
1655 nested_vmcb->save.rflags = vmcb->save.rflags;
1656 nested_vmcb->save.rip = vmcb->save.rip;
1657 nested_vmcb->save.rsp = vmcb->save.rsp;
1658 nested_vmcb->save.rax = vmcb->save.rax;
1659 nested_vmcb->save.dr7 = vmcb->save.dr7;
1660 nested_vmcb->save.dr6 = vmcb->save.dr6;
1661 nested_vmcb->save.cpl = vmcb->save.cpl;
1663 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
1664 nested_vmcb->control.int_vector = vmcb->control.int_vector;
1665 nested_vmcb->control.int_state = vmcb->control.int_state;
1666 nested_vmcb->control.exit_code = vmcb->control.exit_code;
1667 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
1668 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
1669 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
1670 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
1671 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
1672 nested_vmcb->control.tlb_ctl = 0;
1673 nested_vmcb->control.event_inj = 0;
1674 nested_vmcb->control.event_inj_err = 0;
1676 /* We always set V_INTR_MASKING and remember the old value in hflags */
1677 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1678 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1680 /* Restore the original control entries */
1681 copy_vmcb_control_area(vmcb, hsave);
1683 /* Kill any pending exceptions */
1684 if (svm->vcpu.arch.exception.pending == true)
1685 nsvm_printk("WARNING: Pending Exception\n");
1687 kvm_clear_exception_queue(&svm->vcpu);
1688 kvm_clear_interrupt_queue(&svm->vcpu);
1690 /* Restore selected save entries */
1691 svm->vmcb->save.es = hsave->save.es;
1692 svm->vmcb->save.cs = hsave->save.cs;
1693 svm->vmcb->save.ss = hsave->save.ss;
1694 svm->vmcb->save.ds = hsave->save.ds;
1695 svm->vmcb->save.gdtr = hsave->save.gdtr;
1696 svm->vmcb->save.idtr = hsave->save.idtr;
1697 svm->vmcb->save.rflags = hsave->save.rflags;
1698 svm_set_efer(&svm->vcpu, hsave->save.efer);
1699 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1700 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1702 svm->vmcb->save.cr3 = hsave->save.cr3;
1703 svm->vcpu.arch.cr3 = hsave->save.cr3;
1705 kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1707 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1708 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1709 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1710 svm->vmcb->save.dr7 = 0;
1711 svm->vmcb->save.cpl = 0;
1712 svm->vmcb->control.exit_int_info = 0;
1714 /* Exit nested SVM mode */
1715 svm->nested.vmcb = 0;
1717 nested_svm_unmap(nested_vmcb, KM_USER0);
1719 kvm_mmu_reset_context(&svm->vcpu);
1720 kvm_mmu_load(&svm->vcpu);
1725 static int nested_svm_vmrun_msrpm(struct vcpu_svm *svm, void *arg1,
1726 void *arg2, void *opaque)
1729 u32 *nested_msrpm = (u32*)arg1;
1730 for (i=0; i< PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER) / 4; i++)
1731 svm->nested.msrpm[i] = svm->msrpm[i] | nested_msrpm[i];
1732 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
1737 static int nested_svm_vmrun(struct vcpu_svm *svm, void *arg1,
1738 void *arg2, void *opaque)
1740 struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1741 struct vmcb *hsave = svm->nested.hsave;
1742 struct vmcb *vmcb = svm->vmcb;
1744 /* nested_vmcb is our indicator if nested SVM is activated */
1745 svm->nested.vmcb = svm->vmcb->save.rax;
1747 /* Clear internal status */
1748 kvm_clear_exception_queue(&svm->vcpu);
1749 kvm_clear_interrupt_queue(&svm->vcpu);
1751 /* Save the old vmcb, so we don't need to pick what we save, but
1752 can restore everything when a VMEXIT occurs */
1753 hsave->save.es = vmcb->save.es;
1754 hsave->save.cs = vmcb->save.cs;
1755 hsave->save.ss = vmcb->save.ss;
1756 hsave->save.ds = vmcb->save.ds;
1757 hsave->save.gdtr = vmcb->save.gdtr;
1758 hsave->save.idtr = vmcb->save.idtr;
1759 hsave->save.efer = svm->vcpu.arch.shadow_efer;
1760 hsave->save.cr0 = svm->vcpu.arch.cr0;
1761 hsave->save.cr4 = svm->vcpu.arch.cr4;
1762 hsave->save.rflags = vmcb->save.rflags;
1763 hsave->save.rip = svm->next_rip;
1764 hsave->save.rsp = vmcb->save.rsp;
1765 hsave->save.rax = vmcb->save.rax;
1767 hsave->save.cr3 = vmcb->save.cr3;
1769 hsave->save.cr3 = svm->vcpu.arch.cr3;
1771 copy_vmcb_control_area(hsave, vmcb);
1773 if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
1774 svm->vcpu.arch.hflags |= HF_HIF_MASK;
1776 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
1778 /* Load the nested guest state */
1779 svm->vmcb->save.es = nested_vmcb->save.es;
1780 svm->vmcb->save.cs = nested_vmcb->save.cs;
1781 svm->vmcb->save.ss = nested_vmcb->save.ss;
1782 svm->vmcb->save.ds = nested_vmcb->save.ds;
1783 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
1784 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
1785 svm->vmcb->save.rflags = nested_vmcb->save.rflags;
1786 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
1787 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
1788 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
1790 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
1791 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
1793 kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
1794 kvm_mmu_reset_context(&svm->vcpu);
1796 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
1797 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
1798 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
1799 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
1800 /* In case we don't even reach vcpu_run, the fields are not updated */
1801 svm->vmcb->save.rax = nested_vmcb->save.rax;
1802 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
1803 svm->vmcb->save.rip = nested_vmcb->save.rip;
1804 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
1805 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
1806 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
1808 /* We don't want a nested guest to be more powerful than the guest,
1809 so all intercepts are ORed */
1810 svm->vmcb->control.intercept_cr_read |=
1811 nested_vmcb->control.intercept_cr_read;
1812 svm->vmcb->control.intercept_cr_write |=
1813 nested_vmcb->control.intercept_cr_write;
1814 svm->vmcb->control.intercept_dr_read |=
1815 nested_vmcb->control.intercept_dr_read;
1816 svm->vmcb->control.intercept_dr_write |=
1817 nested_vmcb->control.intercept_dr_write;
1818 svm->vmcb->control.intercept_exceptions |=
1819 nested_vmcb->control.intercept_exceptions;
1821 svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
1823 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa;
1825 /* cache intercepts */
1826 svm->nested.intercept_cr_read = nested_vmcb->control.intercept_cr_read;
1827 svm->nested.intercept_cr_write = nested_vmcb->control.intercept_cr_write;
1828 svm->nested.intercept_dr_read = nested_vmcb->control.intercept_dr_read;
1829 svm->nested.intercept_dr_write = nested_vmcb->control.intercept_dr_write;
1830 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
1831 svm->nested.intercept = nested_vmcb->control.intercept;
1833 force_new_asid(&svm->vcpu);
1834 svm->vmcb->control.exit_int_info = nested_vmcb->control.exit_int_info;
1835 svm->vmcb->control.exit_int_info_err = nested_vmcb->control.exit_int_info_err;
1836 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
1837 if (nested_vmcb->control.int_ctl & V_IRQ_MASK) {
1838 nsvm_printk("nSVM Injecting Interrupt: 0x%x\n",
1839 nested_vmcb->control.int_ctl);
1841 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
1842 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
1844 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
1846 nsvm_printk("nSVM exit_int_info: 0x%x | int_state: 0x%x\n",
1847 nested_vmcb->control.exit_int_info,
1848 nested_vmcb->control.int_state);
1850 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
1851 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
1852 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
1853 if (nested_vmcb->control.event_inj & SVM_EVTINJ_VALID)
1854 nsvm_printk("Injecting Event: 0x%x\n",
1855 nested_vmcb->control.event_inj);
1856 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
1857 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
1864 static int nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
1866 to_vmcb->save.fs = from_vmcb->save.fs;
1867 to_vmcb->save.gs = from_vmcb->save.gs;
1868 to_vmcb->save.tr = from_vmcb->save.tr;
1869 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
1870 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
1871 to_vmcb->save.star = from_vmcb->save.star;
1872 to_vmcb->save.lstar = from_vmcb->save.lstar;
1873 to_vmcb->save.cstar = from_vmcb->save.cstar;
1874 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
1875 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
1876 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
1877 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
1882 static int nested_svm_vmload(struct vcpu_svm *svm, void *nested_vmcb,
1883 void *arg2, void *opaque)
1885 return nested_svm_vmloadsave((struct vmcb *)nested_vmcb, svm->vmcb);
1888 static int nested_svm_vmsave(struct vcpu_svm *svm, void *nested_vmcb,
1889 void *arg2, void *opaque)
1891 return nested_svm_vmloadsave(svm->vmcb, (struct vmcb *)nested_vmcb);
1894 static int vmload_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1896 if (nested_svm_check_permissions(svm))
1899 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1900 skip_emulated_instruction(&svm->vcpu);
1902 nested_svm_do(svm, svm->vmcb->save.rax, 0, NULL, nested_svm_vmload);
1907 static int vmsave_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1909 if (nested_svm_check_permissions(svm))
1912 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1913 skip_emulated_instruction(&svm->vcpu);
1915 nested_svm_do(svm, svm->vmcb->save.rax, 0, NULL, nested_svm_vmsave);
1920 static int vmrun_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1922 nsvm_printk("VMrun\n");
1923 if (nested_svm_check_permissions(svm))
1926 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1927 skip_emulated_instruction(&svm->vcpu);
1929 if (nested_svm_do(svm, svm->vmcb->save.rax, 0,
1930 NULL, nested_svm_vmrun))
1933 if (nested_svm_do(svm, svm->nested.vmcb_msrpm, 0,
1934 NULL, nested_svm_vmrun_msrpm))
1940 static int stgi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1942 if (nested_svm_check_permissions(svm))
1945 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1946 skip_emulated_instruction(&svm->vcpu);
1953 static int clgi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1955 if (nested_svm_check_permissions(svm))
1958 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1959 skip_emulated_instruction(&svm->vcpu);
1963 /* After a CLGI no interrupts should come */
1964 svm_clear_vintr(svm);
1965 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1970 static int invlpga_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1972 struct kvm_vcpu *vcpu = &svm->vcpu;
1973 nsvm_printk("INVLPGA\n");
1975 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
1976 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
1978 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1979 skip_emulated_instruction(&svm->vcpu);
1983 static int invalid_op_interception(struct vcpu_svm *svm,
1984 struct kvm_run *kvm_run)
1986 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1990 static int task_switch_interception(struct vcpu_svm *svm,
1991 struct kvm_run *kvm_run)
1995 int int_type = svm->vmcb->control.exit_int_info &
1996 SVM_EXITINTINFO_TYPE_MASK;
1997 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
1999 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2001 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2003 tss_selector = (u16)svm->vmcb->control.exit_info_1;
2005 if (svm->vmcb->control.exit_info_2 &
2006 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2007 reason = TASK_SWITCH_IRET;
2008 else if (svm->vmcb->control.exit_info_2 &
2009 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2010 reason = TASK_SWITCH_JMP;
2012 reason = TASK_SWITCH_GATE;
2014 reason = TASK_SWITCH_CALL;
2016 if (reason == TASK_SWITCH_GATE) {
2018 case SVM_EXITINTINFO_TYPE_NMI:
2019 svm->vcpu.arch.nmi_injected = false;
2021 case SVM_EXITINTINFO_TYPE_EXEPT:
2022 kvm_clear_exception_queue(&svm->vcpu);
2024 case SVM_EXITINTINFO_TYPE_INTR:
2025 kvm_clear_interrupt_queue(&svm->vcpu);
2032 if (reason != TASK_SWITCH_GATE ||
2033 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2034 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2035 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2036 skip_emulated_instruction(&svm->vcpu);
2038 return kvm_task_switch(&svm->vcpu, tss_selector, reason);
2041 static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2043 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2044 kvm_emulate_cpuid(&svm->vcpu);
2048 static int iret_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2050 ++svm->vcpu.stat.nmi_window_exits;
2051 svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
2052 svm->vcpu.arch.hflags |= HF_IRET_MASK;
2056 static int invlpg_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2058 if (emulate_instruction(&svm->vcpu, kvm_run, 0, 0, 0) != EMULATE_DONE)
2059 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2063 static int emulate_on_interception(struct vcpu_svm *svm,
2064 struct kvm_run *kvm_run)
2066 if (emulate_instruction(&svm->vcpu, NULL, 0, 0, 0) != EMULATE_DONE)
2067 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2071 static int cr8_write_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2073 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2074 /* instruction emulation calls kvm_set_cr8() */
2075 emulate_instruction(&svm->vcpu, NULL, 0, 0, 0);
2076 if (irqchip_in_kernel(svm->vcpu.kvm)) {
2077 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2080 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2082 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2086 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2088 struct vcpu_svm *svm = to_svm(vcpu);
2091 case MSR_IA32_TSC: {
2095 *data = svm->vmcb->control.tsc_offset + tsc;
2099 *data = svm->vmcb->save.star;
2101 #ifdef CONFIG_X86_64
2103 *data = svm->vmcb->save.lstar;
2106 *data = svm->vmcb->save.cstar;
2108 case MSR_KERNEL_GS_BASE:
2109 *data = svm->vmcb->save.kernel_gs_base;
2111 case MSR_SYSCALL_MASK:
2112 *data = svm->vmcb->save.sfmask;
2115 case MSR_IA32_SYSENTER_CS:
2116 *data = svm->vmcb->save.sysenter_cs;
2118 case MSR_IA32_SYSENTER_EIP:
2119 *data = svm->sysenter_eip;
2121 case MSR_IA32_SYSENTER_ESP:
2122 *data = svm->sysenter_esp;
2124 /* Nobody will change the following 5 values in the VMCB so
2125 we can safely return them on rdmsr. They will always be 0
2126 until LBRV is implemented. */
2127 case MSR_IA32_DEBUGCTLMSR:
2128 *data = svm->vmcb->save.dbgctl;
2130 case MSR_IA32_LASTBRANCHFROMIP:
2131 *data = svm->vmcb->save.br_from;
2133 case MSR_IA32_LASTBRANCHTOIP:
2134 *data = svm->vmcb->save.br_to;
2136 case MSR_IA32_LASTINTFROMIP:
2137 *data = svm->vmcb->save.last_excp_from;
2139 case MSR_IA32_LASTINTTOIP:
2140 *data = svm->vmcb->save.last_excp_to;
2142 case MSR_VM_HSAVE_PA:
2143 *data = svm->nested.hsave_msr;
2148 case MSR_IA32_UCODE_REV:
2152 return kvm_get_msr_common(vcpu, ecx, data);
2157 static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2159 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2162 if (svm_get_msr(&svm->vcpu, ecx, &data))
2163 kvm_inject_gp(&svm->vcpu, 0);
2165 trace_kvm_msr_read(ecx, data);
2167 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
2168 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
2169 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2170 skip_emulated_instruction(&svm->vcpu);
2175 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2177 struct vcpu_svm *svm = to_svm(vcpu);
2180 case MSR_IA32_TSC: {
2184 svm->vmcb->control.tsc_offset = data - tsc;
2188 svm->vmcb->save.star = data;
2190 #ifdef CONFIG_X86_64
2192 svm->vmcb->save.lstar = data;
2195 svm->vmcb->save.cstar = data;
2197 case MSR_KERNEL_GS_BASE:
2198 svm->vmcb->save.kernel_gs_base = data;
2200 case MSR_SYSCALL_MASK:
2201 svm->vmcb->save.sfmask = data;
2204 case MSR_IA32_SYSENTER_CS:
2205 svm->vmcb->save.sysenter_cs = data;
2207 case MSR_IA32_SYSENTER_EIP:
2208 svm->sysenter_eip = data;
2209 svm->vmcb->save.sysenter_eip = data;
2211 case MSR_IA32_SYSENTER_ESP:
2212 svm->sysenter_esp = data;
2213 svm->vmcb->save.sysenter_esp = data;
2215 case MSR_IA32_DEBUGCTLMSR:
2216 if (!svm_has(SVM_FEATURE_LBRV)) {
2217 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2221 if (data & DEBUGCTL_RESERVED_BITS)
2224 svm->vmcb->save.dbgctl = data;
2225 if (data & (1ULL<<0))
2226 svm_enable_lbrv(svm);
2228 svm_disable_lbrv(svm);
2230 case MSR_VM_HSAVE_PA:
2231 svm->nested.hsave_msr = data;
2235 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2238 return kvm_set_msr_common(vcpu, ecx, data);
2243 static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2245 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2246 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
2247 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2249 trace_kvm_msr_write(ecx, data);
2251 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2252 if (svm_set_msr(&svm->vcpu, ecx, data))
2253 kvm_inject_gp(&svm->vcpu, 0);
2255 skip_emulated_instruction(&svm->vcpu);
2259 static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2261 if (svm->vmcb->control.exit_info_1)
2262 return wrmsr_interception(svm, kvm_run);
2264 return rdmsr_interception(svm, kvm_run);
2267 static int interrupt_window_interception(struct vcpu_svm *svm,
2268 struct kvm_run *kvm_run)
2270 svm_clear_vintr(svm);
2271 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2273 * If the user space waits to inject interrupts, exit as soon as
2276 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2277 kvm_run->request_interrupt_window &&
2278 !kvm_cpu_has_interrupt(&svm->vcpu)) {
2279 ++svm->vcpu.stat.irq_window_exits;
2280 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2287 static int (*svm_exit_handlers[])(struct vcpu_svm *svm,
2288 struct kvm_run *kvm_run) = {
2289 [SVM_EXIT_READ_CR0] = emulate_on_interception,
2290 [SVM_EXIT_READ_CR3] = emulate_on_interception,
2291 [SVM_EXIT_READ_CR4] = emulate_on_interception,
2292 [SVM_EXIT_READ_CR8] = emulate_on_interception,
2294 [SVM_EXIT_WRITE_CR0] = emulate_on_interception,
2295 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
2296 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
2297 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
2298 [SVM_EXIT_READ_DR0] = emulate_on_interception,
2299 [SVM_EXIT_READ_DR1] = emulate_on_interception,
2300 [SVM_EXIT_READ_DR2] = emulate_on_interception,
2301 [SVM_EXIT_READ_DR3] = emulate_on_interception,
2302 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
2303 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
2304 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
2305 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
2306 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
2307 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
2308 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2309 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
2310 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
2311 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
2312 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
2313 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
2314 [SVM_EXIT_INTR] = intr_interception,
2315 [SVM_EXIT_NMI] = nmi_interception,
2316 [SVM_EXIT_SMI] = nop_on_interception,
2317 [SVM_EXIT_INIT] = nop_on_interception,
2318 [SVM_EXIT_VINTR] = interrupt_window_interception,
2319 /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */
2320 [SVM_EXIT_CPUID] = cpuid_interception,
2321 [SVM_EXIT_IRET] = iret_interception,
2322 [SVM_EXIT_INVD] = emulate_on_interception,
2323 [SVM_EXIT_HLT] = halt_interception,
2324 [SVM_EXIT_INVLPG] = invlpg_interception,
2325 [SVM_EXIT_INVLPGA] = invlpga_interception,
2326 [SVM_EXIT_IOIO] = io_interception,
2327 [SVM_EXIT_MSR] = msr_interception,
2328 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
2329 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
2330 [SVM_EXIT_VMRUN] = vmrun_interception,
2331 [SVM_EXIT_VMMCALL] = vmmcall_interception,
2332 [SVM_EXIT_VMLOAD] = vmload_interception,
2333 [SVM_EXIT_VMSAVE] = vmsave_interception,
2334 [SVM_EXIT_STGI] = stgi_interception,
2335 [SVM_EXIT_CLGI] = clgi_interception,
2336 [SVM_EXIT_SKINIT] = invalid_op_interception,
2337 [SVM_EXIT_WBINVD] = emulate_on_interception,
2338 [SVM_EXIT_MONITOR] = invalid_op_interception,
2339 [SVM_EXIT_MWAIT] = invalid_op_interception,
2340 [SVM_EXIT_NPF] = pf_interception,
2343 static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
2345 struct vcpu_svm *svm = to_svm(vcpu);
2346 u32 exit_code = svm->vmcb->control.exit_code;
2348 trace_kvm_exit(exit_code, svm->vmcb->save.rip);
2350 if (is_nested(svm)) {
2351 nsvm_printk("nested handle_exit: 0x%x | 0x%lx | 0x%lx | 0x%lx\n",
2352 exit_code, svm->vmcb->control.exit_info_1,
2353 svm->vmcb->control.exit_info_2, svm->vmcb->save.rip);
2354 if (nested_svm_exit_handled(svm, true))
2358 svm_complete_interrupts(svm);
2362 if ((vcpu->arch.cr0 ^ svm->vmcb->save.cr0) & X86_CR0_PG) {
2363 svm_set_cr0(vcpu, svm->vmcb->save.cr0);
2366 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2367 vcpu->arch.cr3 = svm->vmcb->save.cr3;
2369 kvm_mmu_reset_context(vcpu);
2375 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2376 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2377 kvm_run->fail_entry.hardware_entry_failure_reason
2378 = svm->vmcb->control.exit_code;
2382 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
2383 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
2384 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH)
2385 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2387 __func__, svm->vmcb->control.exit_int_info,
2390 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
2391 || !svm_exit_handlers[exit_code]) {
2392 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2393 kvm_run->hw.hardware_exit_reason = exit_code;
2397 return svm_exit_handlers[exit_code](svm, kvm_run);
2400 static void reload_tss(struct kvm_vcpu *vcpu)
2402 int cpu = raw_smp_processor_id();
2404 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
2405 svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */
2409 static void pre_svm_run(struct vcpu_svm *svm)
2411 int cpu = raw_smp_processor_id();
2413 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
2415 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
2416 /* FIXME: handle wraparound of asid_generation */
2417 if (svm->asid_generation != svm_data->asid_generation)
2418 new_asid(svm, svm_data);
2421 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
2423 struct vcpu_svm *svm = to_svm(vcpu);
2425 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
2426 vcpu->arch.hflags |= HF_NMI_MASK;
2427 svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2428 ++vcpu->stat.nmi_injections;
2431 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
2433 struct vmcb_control_area *control;
2435 trace_kvm_inj_virq(irq);
2437 ++svm->vcpu.stat.irq_injections;
2438 control = &svm->vmcb->control;
2439 control->int_vector = irq;
2440 control->int_ctl &= ~V_INTR_PRIO_MASK;
2441 control->int_ctl |= V_IRQ_MASK |
2442 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2445 static void svm_set_irq(struct kvm_vcpu *vcpu)
2447 struct vcpu_svm *svm = to_svm(vcpu);
2449 BUG_ON(!(gif_set(svm)));
2451 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
2452 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2455 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
2457 struct vcpu_svm *svm = to_svm(vcpu);
2463 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2466 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
2468 struct vcpu_svm *svm = to_svm(vcpu);
2469 struct vmcb *vmcb = svm->vmcb;
2470 return !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2471 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
2474 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
2476 struct vcpu_svm *svm = to_svm(vcpu);
2477 struct vmcb *vmcb = svm->vmcb;
2478 return (vmcb->save.rflags & X86_EFLAGS_IF) &&
2479 !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2484 static void enable_irq_window(struct kvm_vcpu *vcpu)
2486 struct vcpu_svm *svm = to_svm(vcpu);
2487 nsvm_printk("Trying to open IRQ window\n");
2489 nested_svm_intr(svm);
2491 /* In case GIF=0 we can't rely on the CPU to tell us when
2492 * GIF becomes 1, because that's a separate STGI/VMRUN intercept.
2493 * The next time we get that intercept, this function will be
2494 * called again though and we'll get the vintr intercept. */
2497 svm_inject_irq(svm, 0x0);
2501 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2503 struct vcpu_svm *svm = to_svm(vcpu);
2505 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
2507 return; /* IRET will cause a vm exit */
2509 /* Something prevents NMI from been injected. Single step over
2510 possible problem (IRET or exception injection or interrupt
2512 vcpu->arch.singlestep = true;
2513 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2514 update_db_intercept(vcpu);
2517 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
2522 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
2524 force_new_asid(vcpu);
2527 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
2531 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
2533 struct vcpu_svm *svm = to_svm(vcpu);
2535 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
2536 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
2537 kvm_set_cr8(vcpu, cr8);
2541 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
2543 struct vcpu_svm *svm = to_svm(vcpu);
2546 cr8 = kvm_get_cr8(vcpu);
2547 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
2548 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
2551 static void svm_complete_interrupts(struct vcpu_svm *svm)
2555 u32 exitintinfo = svm->vmcb->control.exit_int_info;
2557 if (svm->vcpu.arch.hflags & HF_IRET_MASK)
2558 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
2560 svm->vcpu.arch.nmi_injected = false;
2561 kvm_clear_exception_queue(&svm->vcpu);
2562 kvm_clear_interrupt_queue(&svm->vcpu);
2564 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
2567 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
2568 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
2571 case SVM_EXITINTINFO_TYPE_NMI:
2572 svm->vcpu.arch.nmi_injected = true;
2574 case SVM_EXITINTINFO_TYPE_EXEPT:
2575 /* In case of software exception do not reinject an exception
2576 vector, but re-execute and instruction instead */
2579 if (kvm_exception_is_soft(vector))
2581 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
2582 u32 err = svm->vmcb->control.exit_int_info_err;
2583 kvm_queue_exception_e(&svm->vcpu, vector, err);
2586 kvm_queue_exception(&svm->vcpu, vector);
2588 case SVM_EXITINTINFO_TYPE_INTR:
2589 kvm_queue_interrupt(&svm->vcpu, vector, false);
2596 #ifdef CONFIG_X86_64
2602 static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2604 struct vcpu_svm *svm = to_svm(vcpu);
2609 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
2610 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
2611 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
2615 sync_lapic_to_cr8(vcpu);
2617 save_host_msrs(vcpu);
2618 fs_selector = kvm_read_fs();
2619 gs_selector = kvm_read_gs();
2620 ldt_selector = kvm_read_ldt();
2621 if (!is_nested(svm))
2622 svm->vmcb->save.cr2 = vcpu->arch.cr2;
2623 /* required for live migration with NPT */
2625 svm->vmcb->save.cr3 = vcpu->arch.cr3;
2632 "push %%"R"bp; \n\t"
2633 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
2634 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
2635 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
2636 "mov %c[rsi](%[svm]), %%"R"si \n\t"
2637 "mov %c[rdi](%[svm]), %%"R"di \n\t"
2638 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
2639 #ifdef CONFIG_X86_64
2640 "mov %c[r8](%[svm]), %%r8 \n\t"
2641 "mov %c[r9](%[svm]), %%r9 \n\t"
2642 "mov %c[r10](%[svm]), %%r10 \n\t"
2643 "mov %c[r11](%[svm]), %%r11 \n\t"
2644 "mov %c[r12](%[svm]), %%r12 \n\t"
2645 "mov %c[r13](%[svm]), %%r13 \n\t"
2646 "mov %c[r14](%[svm]), %%r14 \n\t"
2647 "mov %c[r15](%[svm]), %%r15 \n\t"
2650 /* Enter guest mode */
2652 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
2653 __ex(SVM_VMLOAD) "\n\t"
2654 __ex(SVM_VMRUN) "\n\t"
2655 __ex(SVM_VMSAVE) "\n\t"
2658 /* Save guest registers, load host registers */
2659 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
2660 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
2661 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
2662 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
2663 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
2664 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
2665 #ifdef CONFIG_X86_64
2666 "mov %%r8, %c[r8](%[svm]) \n\t"
2667 "mov %%r9, %c[r9](%[svm]) \n\t"
2668 "mov %%r10, %c[r10](%[svm]) \n\t"
2669 "mov %%r11, %c[r11](%[svm]) \n\t"
2670 "mov %%r12, %c[r12](%[svm]) \n\t"
2671 "mov %%r13, %c[r13](%[svm]) \n\t"
2672 "mov %%r14, %c[r14](%[svm]) \n\t"
2673 "mov %%r15, %c[r15](%[svm]) \n\t"
2678 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
2679 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
2680 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
2681 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
2682 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
2683 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
2684 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
2685 #ifdef CONFIG_X86_64
2686 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
2687 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
2688 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
2689 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
2690 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
2691 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
2692 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
2693 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
2696 , R"bx", R"cx", R"dx", R"si", R"di"
2697 #ifdef CONFIG_X86_64
2698 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
2702 vcpu->arch.cr2 = svm->vmcb->save.cr2;
2703 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
2704 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
2705 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
2707 kvm_load_fs(fs_selector);
2708 kvm_load_gs(gs_selector);
2709 kvm_load_ldt(ldt_selector);
2710 load_host_msrs(vcpu);
2714 local_irq_disable();
2718 sync_cr8_to_lapic(vcpu);
2723 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
2724 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
2730 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
2732 struct vcpu_svm *svm = to_svm(vcpu);
2735 svm->vmcb->control.nested_cr3 = root;
2736 force_new_asid(vcpu);
2740 svm->vmcb->save.cr3 = root;
2741 force_new_asid(vcpu);
2743 if (vcpu->fpu_active) {
2744 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
2745 svm->vmcb->save.cr0 |= X86_CR0_TS;
2746 vcpu->fpu_active = 0;
2750 static int is_disabled(void)
2754 rdmsrl(MSR_VM_CR, vm_cr);
2755 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
2762 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2765 * Patch in the VMMCALL instruction:
2767 hypercall[0] = 0x0f;
2768 hypercall[1] = 0x01;
2769 hypercall[2] = 0xd9;
2772 static void svm_check_processor_compat(void *rtn)
2777 static bool svm_cpu_has_accelerated_tpr(void)
2782 static int get_npt_level(void)
2784 #ifdef CONFIG_X86_64
2785 return PT64_ROOT_LEVEL;
2787 return PT32E_ROOT_LEVEL;
2791 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
2796 static const struct trace_print_flags svm_exit_reasons_str[] = {
2797 { SVM_EXIT_READ_CR0, "read_cr0" },
2798 { SVM_EXIT_READ_CR3, "read_cr3" },
2799 { SVM_EXIT_READ_CR4, "read_cr4" },
2800 { SVM_EXIT_READ_CR8, "read_cr8" },
2801 { SVM_EXIT_WRITE_CR0, "write_cr0" },
2802 { SVM_EXIT_WRITE_CR3, "write_cr3" },
2803 { SVM_EXIT_WRITE_CR4, "write_cr4" },
2804 { SVM_EXIT_WRITE_CR8, "write_cr8" },
2805 { SVM_EXIT_READ_DR0, "read_dr0" },
2806 { SVM_EXIT_READ_DR1, "read_dr1" },
2807 { SVM_EXIT_READ_DR2, "read_dr2" },
2808 { SVM_EXIT_READ_DR3, "read_dr3" },
2809 { SVM_EXIT_WRITE_DR0, "write_dr0" },
2810 { SVM_EXIT_WRITE_DR1, "write_dr1" },
2811 { SVM_EXIT_WRITE_DR2, "write_dr2" },
2812 { SVM_EXIT_WRITE_DR3, "write_dr3" },
2813 { SVM_EXIT_WRITE_DR5, "write_dr5" },
2814 { SVM_EXIT_WRITE_DR7, "write_dr7" },
2815 { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" },
2816 { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" },
2817 { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" },
2818 { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" },
2819 { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" },
2820 { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" },
2821 { SVM_EXIT_INTR, "interrupt" },
2822 { SVM_EXIT_NMI, "nmi" },
2823 { SVM_EXIT_SMI, "smi" },
2824 { SVM_EXIT_INIT, "init" },
2825 { SVM_EXIT_VINTR, "vintr" },
2826 { SVM_EXIT_CPUID, "cpuid" },
2827 { SVM_EXIT_INVD, "invd" },
2828 { SVM_EXIT_HLT, "hlt" },
2829 { SVM_EXIT_INVLPG, "invlpg" },
2830 { SVM_EXIT_INVLPGA, "invlpga" },
2831 { SVM_EXIT_IOIO, "io" },
2832 { SVM_EXIT_MSR, "msr" },
2833 { SVM_EXIT_TASK_SWITCH, "task_switch" },
2834 { SVM_EXIT_SHUTDOWN, "shutdown" },
2835 { SVM_EXIT_VMRUN, "vmrun" },
2836 { SVM_EXIT_VMMCALL, "hypercall" },
2837 { SVM_EXIT_VMLOAD, "vmload" },
2838 { SVM_EXIT_VMSAVE, "vmsave" },
2839 { SVM_EXIT_STGI, "stgi" },
2840 { SVM_EXIT_CLGI, "clgi" },
2841 { SVM_EXIT_SKINIT, "skinit" },
2842 { SVM_EXIT_WBINVD, "wbinvd" },
2843 { SVM_EXIT_MONITOR, "monitor" },
2844 { SVM_EXIT_MWAIT, "mwait" },
2845 { SVM_EXIT_NPF, "npf" },
2849 static bool svm_gb_page_enable(void)
2854 static struct kvm_x86_ops svm_x86_ops = {
2855 .cpu_has_kvm_support = has_svm,
2856 .disabled_by_bios = is_disabled,
2857 .hardware_setup = svm_hardware_setup,
2858 .hardware_unsetup = svm_hardware_unsetup,
2859 .check_processor_compatibility = svm_check_processor_compat,
2860 .hardware_enable = svm_hardware_enable,
2861 .hardware_disable = svm_hardware_disable,
2862 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
2864 .vcpu_create = svm_create_vcpu,
2865 .vcpu_free = svm_free_vcpu,
2866 .vcpu_reset = svm_vcpu_reset,
2868 .prepare_guest_switch = svm_prepare_guest_switch,
2869 .vcpu_load = svm_vcpu_load,
2870 .vcpu_put = svm_vcpu_put,
2872 .set_guest_debug = svm_guest_debug,
2873 .get_msr = svm_get_msr,
2874 .set_msr = svm_set_msr,
2875 .get_segment_base = svm_get_segment_base,
2876 .get_segment = svm_get_segment,
2877 .set_segment = svm_set_segment,
2878 .get_cpl = svm_get_cpl,
2879 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
2880 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
2881 .set_cr0 = svm_set_cr0,
2882 .set_cr3 = svm_set_cr3,
2883 .set_cr4 = svm_set_cr4,
2884 .set_efer = svm_set_efer,
2885 .get_idt = svm_get_idt,
2886 .set_idt = svm_set_idt,
2887 .get_gdt = svm_get_gdt,
2888 .set_gdt = svm_set_gdt,
2889 .get_dr = svm_get_dr,
2890 .set_dr = svm_set_dr,
2891 .cache_reg = svm_cache_reg,
2892 .get_rflags = svm_get_rflags,
2893 .set_rflags = svm_set_rflags,
2895 .tlb_flush = svm_flush_tlb,
2897 .run = svm_vcpu_run,
2898 .handle_exit = handle_exit,
2899 .skip_emulated_instruction = skip_emulated_instruction,
2900 .set_interrupt_shadow = svm_set_interrupt_shadow,
2901 .get_interrupt_shadow = svm_get_interrupt_shadow,
2902 .patch_hypercall = svm_patch_hypercall,
2903 .set_irq = svm_set_irq,
2904 .set_nmi = svm_inject_nmi,
2905 .queue_exception = svm_queue_exception,
2906 .interrupt_allowed = svm_interrupt_allowed,
2907 .nmi_allowed = svm_nmi_allowed,
2908 .enable_nmi_window = enable_nmi_window,
2909 .enable_irq_window = enable_irq_window,
2910 .update_cr8_intercept = update_cr8_intercept,
2912 .set_tss_addr = svm_set_tss_addr,
2913 .get_tdp_level = get_npt_level,
2914 .get_mt_mask = svm_get_mt_mask,
2916 .exit_reasons_str = svm_exit_reasons_str,
2917 .gb_page_enable = svm_gb_page_enable,
2920 static int __init svm_init(void)
2922 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
2926 static void __exit svm_exit(void)
2931 module_init(svm_init)
2932 module_exit(svm_exit)