arch/x86/kvm/svm.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  *
   8  * Authors:
   9  *   Yaniv Kamay  <yaniv@qumranet.com>
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *
  12  * This work is licensed under the terms of the GNU GPL, version 2.  See
  13  * the COPYING file in the top-level directory.
  14  *
  15  */
  16 #include <linux/kvm_host.h>
  17
  18 #include "irq.h"
  19 #include "mmu.h"
  20 #include "kvm_cache_regs.h"
  21 #include "x86.h"
  22
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/vmalloc.h>
  26 #include <linux/highmem.h>
  27 #include <linux/sched.h>
  28 #include <linux/ftrace_event.h>
  29
  30 #include <asm/desc.h>
  31
  32 #include <asm/virtext.h>
  33 #include "trace.h"
  34
  35 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  36
  37 MODULE_AUTHOR("Qumranet");
  38 MODULE_LICENSE("GPL");
  39
  40 #define IOPM_ALLOC_ORDER 2
  41 #define MSRPM_ALLOC_ORDER 1
  42
  43 #define SEG_TYPE_LDT 2
  44 #define SEG_TYPE_BUSY_TSS16 3
  45
  46 #define SVM_FEATURE_NPT  (1 << 0)
  47 #define SVM_FEATURE_LBRV (1 << 1)
  48 #define SVM_FEATURE_SVML (1 << 2)
  49
  50 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  51
  52 /* Turn on to get debugging output*/
  53 /* #define NESTED_DEBUG */
  54
  55 #ifdef NESTED_DEBUG
  56 #define nsvm_printk(fmt, args...) printk(KERN_INFO fmt, ## args)
  57 #else
  58 #define nsvm_printk(fmt, args...) do {} while(0)
  59 #endif
  60
  61 static const u32 host_save_user_msrs[] = {
  62 #ifdef CONFIG_X86_64
  63         MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
  64         MSR_FS_BASE,
  65 #endif
  66         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
  67 };
  68
  69 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
  70
  71 struct kvm_vcpu;
  72
  73 struct nested_state {
  74         struct vmcb *hsave;
  75         u64 hsave_msr;
  76         u64 vmcb;
  77
  78         /* These are the merged vectors */
  79         u32 *msrpm;
  80
  81         /* gpa pointers to the real vectors */
  82         u64 vmcb_msrpm;
  83
  84         /* cache for intercepts of the guest */
  85         u16 intercept_cr_read;
  86         u16 intercept_cr_write;
  87         u16 intercept_dr_read;
  88         u16 intercept_dr_write;
  89         u32 intercept_exceptions;
  90         u64 intercept;
  91
  92 };
  93
  94 struct vcpu_svm {
  95         struct kvm_vcpu vcpu;
  96         struct vmcb *vmcb;
  97         unsigned long vmcb_pa;
  98         struct svm_cpu_data *svm_data;
  99         uint64_t asid_generation;
 100         uint64_t sysenter_esp;
 101         uint64_t sysenter_eip;
 102
 103         u64 next_rip;
 104
 105         u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
 106         u64 host_gs_base;
 107
 108         u32 *msrpm;
 109
 110         struct nested_state nested;
 111 };
 112
 113 /* enable NPT for AMD64 and X86 with PAE */
 114 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
 115 static bool npt_enabled = true;
 116 #else
 117 static bool npt_enabled = false;
 118 #endif
 119 static int npt = 1;
 120
 121 module_param(npt, int, S_IRUGO);
 122
 123 static int nested = 0;
 124 module_param(nested, int, S_IRUGO);
 125
 126 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
 127 static void svm_complete_interrupts(struct vcpu_svm *svm);
 128
 129 static int nested_svm_exit_handled(struct vcpu_svm *svm, bool kvm_override);
 130 static int nested_svm_vmexit(struct vcpu_svm *svm);
 131 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
 132                                       bool has_error_code, u32 error_code);
 133
 134 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
 135 {
 136         return container_of(vcpu, struct vcpu_svm, vcpu);
 137 }
 138
 139 static inline bool is_nested(struct vcpu_svm *svm)
 140 {
 141         return svm->nested.vmcb;
 142 }
 143
 144 static inline void enable_gif(struct vcpu_svm *svm)
 145 {
 146         svm->vcpu.arch.hflags |= HF_GIF_MASK;
 147 }
 148
 149 static inline void disable_gif(struct vcpu_svm *svm)
 150 {
 151         svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
 152 }
 153
 154 static inline bool gif_set(struct vcpu_svm *svm)
 155 {
 156         return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
 157 }
 158
 159 static unsigned long iopm_base;
 160
 161 struct kvm_ldttss_desc {
 162         u16 limit0;
 163         u16 base0;
 164         unsigned base1 : 8, type : 5, dpl : 2, p : 1;
 165         unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
 166         u32 base3;
 167         u32 zero1;
 168 } __attribute__((packed));
 169
 170 struct svm_cpu_data {
 171         int cpu;
 172
 173         u64 asid_generation;
 174         u32 max_asid;
 175         u32 next_asid;
 176         struct kvm_ldttss_desc *tss_desc;
 177
 178         struct page *save_area;
 179 };
 180
 181 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 182 static uint32_t svm_features;
 183
 184 struct svm_init_data {
 185         int cpu;
 186         int r;
 187 };
 188
 189 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 190
 191 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 192 #define MSRS_RANGE_SIZE 2048
 193 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 194
 195 #define MAX_INST_SIZE 15
 196
 197 static inline u32 svm_has(u32 feat)
 198 {
 199         return svm_features & feat;
 200 }
 201
 202 static inline void clgi(void)
 203 {
 204         asm volatile (__ex(SVM_CLGI));
 205 }
 206
 207 static inline void stgi(void)
 208 {
 209         asm volatile (__ex(SVM_STGI));
 210 }
 211
 212 static inline void invlpga(unsigned long addr, u32 asid)
 213 {
 214         asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid));
 215 }
 216
 217 static inline void force_new_asid(struct kvm_vcpu *vcpu)
 218 {
 219         to_svm(vcpu)->asid_generation--;
 220 }
 221
 222 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
 223 {
 224         force_new_asid(vcpu);
 225 }
 226
 227 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 228 {
 229         if (!npt_enabled && !(efer & EFER_LMA))
 230                 efer &= ~EFER_LME;
 231
 232         to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
 233         vcpu->arch.shadow_efer = efer;
 234 }
 235
 236 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 237                                 bool has_error_code, u32 error_code)
 238 {
 239         struct vcpu_svm *svm = to_svm(vcpu);
 240
 241         /* If we are within a nested VM we'd better #VMEXIT and let the
 242            guest handle the exception */
 243         if (nested_svm_check_exception(svm, nr, has_error_code, error_code))
 244                 return;
 245
 246         svm->vmcb->control.event_inj = nr
 247                 | SVM_EVTINJ_VALID
 248                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 249                 | SVM_EVTINJ_TYPE_EXEPT;
 250         svm->vmcb->control.event_inj_err = error_code;
 251 }
 252
 253 static int is_external_interrupt(u32 info)
 254 {
 255         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 256         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 257 }
 258
 259 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 260 {
 261         struct vcpu_svm *svm = to_svm(vcpu);
 262         u32 ret = 0;
 263
 264         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
 265                 ret |= X86_SHADOW_INT_STI | X86_SHADOW_INT_MOV_SS;
 266         return ret & mask;
 267 }
 268
 269 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 270 {
 271         struct vcpu_svm *svm = to_svm(vcpu);
 272
 273         if (mask == 0)
 274                 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 275         else
 276                 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
 277
 278 }
 279
 280 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 281 {
 282         struct vcpu_svm *svm = to_svm(vcpu);
 283
 284         if (!svm->next_rip) {
 285                 if (emulate_instruction(vcpu, vcpu->run, 0, 0, EMULTYPE_SKIP) !=
 286                                 EMULATE_DONE)
 287                         printk(KERN_DEBUG "%s: NOP\n", __func__);
 288                 return;
 289         }
 290         if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
 291                 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
 292                        __func__, kvm_rip_read(vcpu), svm->next_rip);
 293
 294         kvm_rip_write(vcpu, svm->next_rip);
 295         svm_set_interrupt_shadow(vcpu, 0);
 296 }
 297
 298 static int has_svm(void)
 299 {
 300         const char *msg;
 301
 302         if (!cpu_has_svm(&msg)) {
 303                 printk(KERN_INFO "has_svm: %s\n", msg);
 304                 return 0;
 305         }
 306
 307         return 1;
 308 }
 309
 310 static void svm_hardware_disable(void *garbage)
 311 {
 312         cpu_svm_disable();
 313 }
 314
 315 static void svm_hardware_enable(void *garbage)
 316 {
 317
 318         struct svm_cpu_data *svm_data;
 319         uint64_t efer;
 320         struct descriptor_table gdt_descr;
 321         struct desc_struct *gdt;
 322         int me = raw_smp_processor_id();
 323
 324         if (!has_svm()) {
 325                 printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me);
 326                 return;
 327         }
 328         svm_data = per_cpu(svm_data, me);
 329
 330         if (!svm_data) {
 331                 printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n",
 332                        me);
 333                 return;
 334         }
 335
 336         svm_data->asid_generation = 1;
 337         svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 338         svm_data->next_asid = svm_data->max_asid + 1;
 339
 340         kvm_get_gdt(&gdt_descr);
 341         gdt = (struct desc_struct *)gdt_descr.base;
 342         svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 343
 344         rdmsrl(MSR_EFER, efer);
 345         wrmsrl(MSR_EFER, efer | EFER_SVME);
 346
 347         wrmsrl(MSR_VM_HSAVE_PA,
 348                page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
 349 }
 350
 351 static void svm_cpu_uninit(int cpu)
 352 {
 353         struct svm_cpu_data *svm_data
 354                 = per_cpu(svm_data, raw_smp_processor_id());
 355
 356         if (!svm_data)
 357                 return;
 358
 359         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 360         __free_page(svm_data->save_area);
 361         kfree(svm_data);
 362 }
 363
 364 static int svm_cpu_init(int cpu)
 365 {
 366         struct svm_cpu_data *svm_data;
 367         int r;
 368
 369         svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 370         if (!svm_data)
 371                 return -ENOMEM;
 372         svm_data->cpu = cpu;
 373         svm_data->save_area = alloc_page(GFP_KERNEL);
 374         r = -ENOMEM;
 375         if (!svm_data->save_area)
 376                 goto err_1;
 377
 378         per_cpu(svm_data, cpu) = svm_data;
 379
 380         return 0;
 381
 382 err_1:
 383         kfree(svm_data);
 384         return r;
 385
 386 }
 387
 388 static void set_msr_interception(u32 *msrpm, unsigned msr,
 389                                  int read, int write)
 390 {
 391         int i;
 392
 393         for (i = 0; i < NUM_MSR_MAPS; i++) {
 394                 if (msr >= msrpm_ranges[i] &&
 395                     msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
 396                         u32 msr_offset = (i * MSRS_IN_RANGE + msr -
 397                                           msrpm_ranges[i]) * 2;
 398
 399                         u32 *base = msrpm + (msr_offset / 32);
 400                         u32 msr_shift = msr_offset % 32;
 401                         u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
 402                         *base = (*base & ~(0x3 << msr_shift)) |
 403                                 (mask << msr_shift);
 404                         return;
 405                 }
 406         }
 407         BUG();
 408 }
 409
 410 static void svm_vcpu_init_msrpm(u32 *msrpm)
 411 {
 412         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 413
 414 #ifdef CONFIG_X86_64
 415         set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
 416         set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
 417         set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
 418         set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
 419         set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
 420         set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
 421 #endif
 422         set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
 423         set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
 424 }
 425
 426 static void svm_enable_lbrv(struct vcpu_svm *svm)
 427 {
 428         u32 *msrpm = svm->msrpm;
 429
 430         svm->vmcb->control.lbr_ctl = 1;
 431         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 432         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 433         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 434         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 435 }
 436
 437 static void svm_disable_lbrv(struct vcpu_svm *svm)
 438 {
 439         u32 *msrpm = svm->msrpm;
 440
 441         svm->vmcb->control.lbr_ctl = 0;
 442         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 443         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 444         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 445         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 446 }
 447
 448 static __init int svm_hardware_setup(void)
 449 {
 450         int cpu;
 451         struct page *iopm_pages;
 452         void *iopm_va;
 453         int r;
 454
 455         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
 456
 457         if (!iopm_pages)
 458                 return -ENOMEM;
 459
 460         iopm_va = page_address(iopm_pages);
 461         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
 462         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 463
 464         if (boot_cpu_has(X86_FEATURE_NX))
 465                 kvm_enable_efer_bits(EFER_NX);
 466
 467         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
 468                 kvm_enable_efer_bits(EFER_FFXSR);
 469
 470         if (nested) {
 471                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
 472                 kvm_enable_efer_bits(EFER_SVME);
 473         }
 474
 475         for_each_online_cpu(cpu) {
 476                 r = svm_cpu_init(cpu);
 477                 if (r)
 478                         goto err;
 479         }
 480
 481         svm_features = cpuid_edx(SVM_CPUID_FUNC);
 482
 483         if (!svm_has(SVM_FEATURE_NPT))
 484                 npt_enabled = false;
 485
 486         if (npt_enabled && !npt) {
 487                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
 488                 npt_enabled = false;
 489         }
 490
 491         if (npt_enabled) {
 492                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
 493                 kvm_enable_tdp();
 494         } else
 495                 kvm_disable_tdp();
 496
 497         return 0;
 498
 499 err:
 500         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
 501         iopm_base = 0;
 502         return r;
 503 }
 504
 505 static __exit void svm_hardware_unsetup(void)
 506 {
 507         int cpu;
 508
 509         for_each_online_cpu(cpu)
 510                 svm_cpu_uninit(cpu);
 511
 512         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
 513         iopm_base = 0;
 514 }
 515
 516 static void init_seg(struct vmcb_seg *seg)
 517 {
 518         seg->selector = 0;
 519         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
 520                 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
 521         seg->limit = 0xffff;
 522         seg->base = 0;
 523 }
 524
 525 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
 526 {
 527         seg->selector = 0;
 528         seg->attrib = SVM_SELECTOR_P_MASK | type;
 529         seg->limit = 0xffff;
 530         seg->base = 0;
 531 }
 532
 533 static void init_vmcb(struct vcpu_svm *svm)
 534 {
 535         struct vmcb_control_area *control = &svm->vmcb->control;
 536         struct vmcb_save_area *save = &svm->vmcb->save;
 537
 538         control->intercept_cr_read =    INTERCEPT_CR0_MASK |
 539                                         INTERCEPT_CR3_MASK |
 540                                         INTERCEPT_CR4_MASK;
 541
 542         control->intercept_cr_write =   INTERCEPT_CR0_MASK |
 543                                         INTERCEPT_CR3_MASK |
 544                                         INTERCEPT_CR4_MASK |
 545                                         INTERCEPT_CR8_MASK;
 546
 547         control->intercept_dr_read =    INTERCEPT_DR0_MASK |
 548                                         INTERCEPT_DR1_MASK |
 549                                         INTERCEPT_DR2_MASK |
 550                                         INTERCEPT_DR3_MASK;
 551
 552         control->intercept_dr_write =   INTERCEPT_DR0_MASK |
 553                                         INTERCEPT_DR1_MASK |
 554                                         INTERCEPT_DR2_MASK |
 555                                         INTERCEPT_DR3_MASK |
 556                                         INTERCEPT_DR5_MASK |
 557                                         INTERCEPT_DR7_MASK;
 558
 559         control->intercept_exceptions = (1 << PF_VECTOR) |
 560                                         (1 << UD_VECTOR) |
 561                                         (1 << MC_VECTOR);
 562
 563
 564         control->intercept =    (1ULL << INTERCEPT_INTR) |
 565                                 (1ULL << INTERCEPT_NMI) |
 566                                 (1ULL << INTERCEPT_SMI) |
 567                                 (1ULL << INTERCEPT_CPUID) |
 568                                 (1ULL << INTERCEPT_INVD) |
 569                                 (1ULL << INTERCEPT_HLT) |
 570                                 (1ULL << INTERCEPT_INVLPG) |
 571                                 (1ULL << INTERCEPT_INVLPGA) |
 572                                 (1ULL << INTERCEPT_IOIO_PROT) |
 573                                 (1ULL << INTERCEPT_MSR_PROT) |
 574                                 (1ULL << INTERCEPT_TASK_SWITCH) |
 575                                 (1ULL << INTERCEPT_SHUTDOWN) |
 576                                 (1ULL << INTERCEPT_VMRUN) |
 577                                 (1ULL << INTERCEPT_VMMCALL) |
 578                                 (1ULL << INTERCEPT_VMLOAD) |
 579                                 (1ULL << INTERCEPT_VMSAVE) |
 580                                 (1ULL << INTERCEPT_STGI) |
 581                                 (1ULL << INTERCEPT_CLGI) |
 582                                 (1ULL << INTERCEPT_SKINIT) |
 583                                 (1ULL << INTERCEPT_WBINVD) |
 584                                 (1ULL << INTERCEPT_MONITOR) |
 585                                 (1ULL << INTERCEPT_MWAIT);
 586
 587         control->iopm_base_pa = iopm_base;
 588         control->msrpm_base_pa = __pa(svm->msrpm);
 589         control->tsc_offset = 0;
 590         control->int_ctl = V_INTR_MASKING_MASK;
 591
 592         init_seg(&save->es);
 593         init_seg(&save->ss);
 594         init_seg(&save->ds);
 595         init_seg(&save->fs);
 596         init_seg(&save->gs);
 597
 598         save->cs.selector = 0xf000;
 599         /* Executable/Readable Code Segment */
 600         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
 601                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
 602         save->cs.limit = 0xffff;
 603         /*
 604          * cs.base should really be 0xffff0000, but vmx can't handle that, so
 605          * be consistent with it.
 606          *
 607          * Replace when we have real mode working for vmx.
 608          */
 609         save->cs.base = 0xf0000;
 610
 611         save->gdtr.limit = 0xffff;
 612         save->idtr.limit = 0xffff;
 613
 614         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
 615         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
 616
 617         save->efer = EFER_SVME;
 618         save->dr6 = 0xffff0ff0;
 619         save->dr7 = 0x400;
 620         save->rflags = 2;
 621         save->rip = 0x0000fff0;
 622         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
 623
 624         /*
 625          * cr0 val on cpu init should be 0x60000010, we enable cpu
 626          * cache by default. the orderly way is to enable cache in bios.
 627          */
 628         save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP;
 629         save->cr4 = X86_CR4_PAE;
 630         /* rdx = ?? */
 631
 632         if (npt_enabled) {
 633                 /* Setup VMCB for Nested Paging */
 634                 control->nested_ctl = 1;
 635                 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
 636                                         (1ULL << INTERCEPT_INVLPG));
 637                 control->intercept_exceptions &= ~(1 << PF_VECTOR);
 638                 control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK|
 639                                                 INTERCEPT_CR3_MASK);
 640                 control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK|
 641                                                  INTERCEPT_CR3_MASK);
 642                 save->g_pat = 0x0007040600070406ULL;
 643                 /* enable caching because the QEMU Bios doesn't enable it */
 644                 save->cr0 = X86_CR0_ET;
 645                 save->cr3 = 0;
 646                 save->cr4 = 0;
 647         }
 648         force_new_asid(&svm->vcpu);
 649
 650         svm->nested.vmcb = 0;
 651         svm->vcpu.arch.hflags = 0;
 652
 653         enable_gif(svm);
 654 }
 655
 656 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
 657 {
 658         struct vcpu_svm *svm = to_svm(vcpu);
 659
 660         init_vmcb(svm);
 661
 662         if (!kvm_vcpu_is_bsp(vcpu)) {
 663                 kvm_rip_write(vcpu, 0);
 664                 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
 665                 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
 666         }
 667         vcpu->arch.regs_avail = ~0;
 668         vcpu->arch.regs_dirty = ~0;
 669
 670         return 0;
 671 }
 672
 673 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
 674 {
 675         struct vcpu_svm *svm;
 676         struct page *page;
 677         struct page *msrpm_pages;
 678         struct page *hsave_page;
 679         struct page *nested_msrpm_pages;
 680         int err;
 681
 682         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
 683         if (!svm) {
 684                 err = -ENOMEM;
 685                 goto out;
 686         }
 687
 688         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
 689         if (err)
 690                 goto free_svm;
 691
 692         page = alloc_page(GFP_KERNEL);
 693         if (!page) {
 694                 err = -ENOMEM;
 695                 goto uninit;
 696         }
 697
 698         err = -ENOMEM;
 699         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 700         if (!msrpm_pages)
 701                 goto uninit;
 702
 703         nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 704         if (!nested_msrpm_pages)
 705                 goto uninit;
 706
 707         svm->msrpm = page_address(msrpm_pages);
 708         svm_vcpu_init_msrpm(svm->msrpm);
 709
 710         hsave_page = alloc_page(GFP_KERNEL);
 711         if (!hsave_page)
 712                 goto uninit;
 713         svm->nested.hsave = page_address(hsave_page);
 714
 715         svm->nested.msrpm = page_address(nested_msrpm_pages);
 716
 717         svm->vmcb = page_address(page);
 718         clear_page(svm->vmcb);
 719         svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
 720         svm->asid_generation = 0;
 721         init_vmcb(svm);
 722
 723         fx_init(&svm->vcpu);
 724         svm->vcpu.fpu_active = 1;
 725         svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
 726         if (kvm_vcpu_is_bsp(&svm->vcpu))
 727                 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
 728
 729         return &svm->vcpu;
 730
 731 uninit:
 732         kvm_vcpu_uninit(&svm->vcpu);
 733 free_svm:
 734         kmem_cache_free(kvm_vcpu_cache, svm);
 735 out:
 736         return ERR_PTR(err);
 737 }
 738
 739 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
 740 {
 741         struct vcpu_svm *svm = to_svm(vcpu);
 742
 743         __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
 744         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
 745         __free_page(virt_to_page(svm->nested.hsave));
 746         __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
 747         kvm_vcpu_uninit(vcpu);
 748         kmem_cache_free(kvm_vcpu_cache, svm);
 749 }
 750
 751 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 752 {
 753         struct vcpu_svm *svm = to_svm(vcpu);
 754         int i;
 755
 756         if (unlikely(cpu != vcpu->cpu)) {
 757                 u64 tsc_this, delta;
 758
 759                 /*
 760                  * Make sure that the guest sees a monotonically
 761                  * increasing TSC.
 762                  */
 763                 rdtscll(tsc_this);
 764                 delta = vcpu->arch.host_tsc - tsc_this;
 765                 svm->vmcb->control.tsc_offset += delta;
 766                 vcpu->cpu = cpu;
 767                 kvm_migrate_timers(vcpu);
 768                 svm->asid_generation = 0;
 769         }
 770
 771         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 772                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 773 }
 774
 775 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
 776 {
 777         struct vcpu_svm *svm = to_svm(vcpu);
 778         int i;
 779
 780         ++vcpu->stat.host_state_reload;
 781         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 782                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 783
 784         rdtscll(vcpu->arch.host_tsc);
 785 }
 786
 787 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
 788 {
 789         return to_svm(vcpu)->vmcb->save.rflags;
 790 }
 791
 792 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 793 {
 794         to_svm(vcpu)->vmcb->save.rflags = rflags;
 795 }
 796
 797 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
 798 {
 799         switch (reg) {
 800         case VCPU_EXREG_PDPTR:
 801                 BUG_ON(!npt_enabled);
 802                 load_pdptrs(vcpu, vcpu->arch.cr3);
 803                 break;
 804         default:
 805                 BUG();
 806         }
 807 }
 808
 809 static void svm_set_vintr(struct vcpu_svm *svm)
 810 {
 811         svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
 812 }
 813
 814 static void svm_clear_vintr(struct vcpu_svm *svm)
 815 {
 816         svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
 817 }
 818
 819 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
 820 {
 821         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 822
 823         switch (seg) {
 824         case VCPU_SREG_CS: return &save->cs;
 825         case VCPU_SREG_DS: return &save->ds;
 826         case VCPU_SREG_ES: return &save->es;
 827         case VCPU_SREG_FS: return &save->fs;
 828         case VCPU_SREG_GS: return &save->gs;
 829         case VCPU_SREG_SS: return &save->ss;
 830         case VCPU_SREG_TR: return &save->tr;
 831         case VCPU_SREG_LDTR: return &save->ldtr;
 832         }
 833         BUG();
 834         return NULL;
 835 }
 836
 837 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
 838 {
 839         struct vmcb_seg *s = svm_seg(vcpu, seg);
 840
 841         return s->base;
 842 }
 843
 844 static void svm_get_segment(struct kvm_vcpu *vcpu,
 845                             struct kvm_segment *var, int seg)
 846 {
 847         struct vmcb_seg *s = svm_seg(vcpu, seg);
 848
 849         var->base = s->base;
 850         var->limit = s->limit;
 851         var->selector = s->selector;
 852         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
 853         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
 854         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
 855         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
 856         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
 857         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
 858         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
 859         var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
 860
 861         /* AMD's VMCB does not have an explicit unusable field, so emulate it
 862          * for cross vendor migration purposes by "not present"
 863          */
 864         var->unusable = !var->present || (var->type == 0);
 865
 866         switch (seg) {
 867         case VCPU_SREG_CS:
 868                 /*
 869                  * SVM always stores 0 for the 'G' bit in the CS selector in
 870                  * the VMCB on a VMEXIT. This hurts cross-vendor migration:
 871                  * Intel's VMENTRY has a check on the 'G' bit.
 872                  */
 873                 var->g = s->limit > 0xfffff;
 874                 break;
 875         case VCPU_SREG_TR:
 876                 /*
 877                  * Work around a bug where the busy flag in the tr selector
 878                  * isn't exposed
 879                  */
 880                 var->type |= 0x2;
 881                 break;
 882         case VCPU_SREG_DS:
 883         case VCPU_SREG_ES:
 884         case VCPU_SREG_FS:
 885         case VCPU_SREG_GS:
 886                 /*
 887                  * The accessed bit must always be set in the segment
 888                  * descriptor cache, although it can be cleared in the
 889                  * descriptor, the cached bit always remains at 1. Since
 890                  * Intel has a check on this, set it here to support
 891                  * cross-vendor migration.
 892                  */
 893                 if (!var->unusable)
 894                         var->type |= 0x1;
 895                 break;
 896         case VCPU_SREG_SS:
 897                 /* On AMD CPUs sometimes the DB bit in the segment
 898                  * descriptor is left as 1, although the whole segment has
 899                  * been made unusable. Clear it here to pass an Intel VMX
 900                  * entry check when cross vendor migrating.
 901                  */
 902                 if (var->unusable)
 903                         var->db = 0;
 904                 break;
 905         }
 906 }
 907
 908 static int svm_get_cpl(struct kvm_vcpu *vcpu)
 909 {
 910         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 911
 912         return save->cpl;
 913 }
 914
 915 static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 916 {
 917         struct vcpu_svm *svm = to_svm(vcpu);
 918
 919         dt->limit = svm->vmcb->save.idtr.limit;
 920         dt->base = svm->vmcb->save.idtr.base;
 921 }
 922
 923 static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 924 {
 925         struct vcpu_svm *svm = to_svm(vcpu);
 926
 927         svm->vmcb->save.idtr.limit = dt->limit;
 928         svm->vmcb->save.idtr.base = dt->base ;
 929 }
 930
 931 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 932 {
 933         struct vcpu_svm *svm = to_svm(vcpu);
 934
 935         dt->limit = svm->vmcb->save.gdtr.limit;
 936         dt->base = svm->vmcb->save.gdtr.base;
 937 }
 938
 939 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 940 {
 941         struct vcpu_svm *svm = to_svm(vcpu);
 942
 943         svm->vmcb->save.gdtr.limit = dt->limit;
 944         svm->vmcb->save.gdtr.base = dt->base ;
 945 }
 946
 947 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
 948 {
 949 }
 950
 951 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
 952 {
 953         struct vcpu_svm *svm = to_svm(vcpu);
 954
 955 #ifdef CONFIG_X86_64
 956         if (vcpu->arch.shadow_efer & EFER_LME) {
 957                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
 958                         vcpu->arch.shadow_efer |= EFER_LMA;
 959                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
 960                 }
 961
 962                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
 963                         vcpu->arch.shadow_efer &= ~EFER_LMA;
 964                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
 965                 }
 966         }
 967 #endif
 968         if (npt_enabled)
 969                 goto set;
 970
 971         if ((vcpu->arch.cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) {
 972                 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
 973                 vcpu->fpu_active = 1;
 974         }
 975
 976         vcpu->arch.cr0 = cr0;
 977         cr0 |= X86_CR0_PG | X86_CR0_WP;
 978         if (!vcpu->fpu_active) {
 979                 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
 980                 cr0 |= X86_CR0_TS;
 981         }
 982 set:
 983         /*
 984          * re-enable caching here because the QEMU bios
 985          * does not do it - this results in some delay at
 986          * reboot
 987          */
 988         cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
 989         svm->vmcb->save.cr0 = cr0;
 990 }
 991
 992 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
 993 {
 994         unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
 995         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
 996
 997         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
 998                 force_new_asid(vcpu);
 999
1000         vcpu->arch.cr4 = cr4;
1001         if (!npt_enabled)
1002                 cr4 |= X86_CR4_PAE;
1003         cr4 |= host_cr4_mce;
1004         to_svm(vcpu)->vmcb->save.cr4 = cr4;
1005 }
1006
1007 static void svm_set_segment(struct kvm_vcpu *vcpu,
1008                             struct kvm_segment *var, int seg)
1009 {
1010         struct vcpu_svm *svm = to_svm(vcpu);
1011         struct vmcb_seg *s = svm_seg(vcpu, seg);
1012
1013         s->base = var->base;
1014         s->limit = var->limit;
1015         s->selector = var->selector;
1016         if (var->unusable)
1017                 s->attrib = 0;
1018         else {
1019                 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1020                 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1021                 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1022                 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1023                 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1024                 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1025                 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1026                 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1027         }
1028         if (seg == VCPU_SREG_CS)
1029                 svm->vmcb->save.cpl
1030                         = (svm->vmcb->save.cs.attrib
1031                            >> SVM_SELECTOR_DPL_SHIFT) & 3;
1032
1033 }
1034
1035 static void update_db_intercept(struct kvm_vcpu *vcpu)
1036 {
1037         struct vcpu_svm *svm = to_svm(vcpu);
1038
1039         svm->vmcb->control.intercept_exceptions &=
1040                 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
1041
1042         if (vcpu->arch.singlestep)
1043                 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1044
1045         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1046                 if (vcpu->guest_debug &
1047                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1048                         svm->vmcb->control.intercept_exceptions |=
1049                                 1 << DB_VECTOR;
1050                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1051                         svm->vmcb->control.intercept_exceptions |=
1052                                 1 << BP_VECTOR;
1053         } else
1054                 vcpu->guest_debug = 0;
1055 }
1056
1057 static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1058 {
1059         int old_debug = vcpu->guest_debug;
1060         struct vcpu_svm *svm = to_svm(vcpu);
1061
1062         vcpu->guest_debug = dbg->control;
1063
1064         update_db_intercept(vcpu);
1065
1066         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1067                 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1068         else
1069                 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1070
1071         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
1072                 svm->vmcb->save.rflags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1073         else if (old_debug & KVM_GUESTDBG_SINGLESTEP)
1074                 svm->vmcb->save.rflags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1075
1076         return 0;
1077 }
1078
1079 static void load_host_msrs(struct kvm_vcpu *vcpu)
1080 {
1081 #ifdef CONFIG_X86_64
1082         wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1083 #endif
1084 }
1085
1086 static void save_host_msrs(struct kvm_vcpu *vcpu)
1087 {
1088 #ifdef CONFIG_X86_64
1089         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1090 #endif
1091 }
1092
1093 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data)
1094 {
1095         if (svm_data->next_asid > svm_data->max_asid) {
1096                 ++svm_data->asid_generation;
1097                 svm_data->next_asid = 1;
1098                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1099         }
1100
1101         svm->asid_generation = svm_data->asid_generation;
1102         svm->vmcb->control.asid = svm_data->next_asid++;
1103 }
1104
1105 static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
1106 {
1107         struct vcpu_svm *svm = to_svm(vcpu);
1108         unsigned long val;
1109
1110         switch (dr) {
1111         case 0 ... 3:
1112                 val = vcpu->arch.db[dr];
1113                 break;
1114         case 6:
1115                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1116                         val = vcpu->arch.dr6;
1117                 else
1118                         val = svm->vmcb->save.dr6;
1119                 break;
1120         case 7:
1121                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1122                         val = vcpu->arch.dr7;
1123                 else
1124                         val = svm->vmcb->save.dr7;
1125                 break;
1126         default:
1127                 val = 0;
1128         }
1129
1130         return val;
1131 }
1132
1133 static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
1134                        int *exception)
1135 {
1136         struct vcpu_svm *svm = to_svm(vcpu);
1137
1138         *exception = 0;
1139
1140         switch (dr) {
1141         case 0 ... 3:
1142                 vcpu->arch.db[dr] = value;
1143                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1144                         vcpu->arch.eff_db[dr] = value;
1145                 return;
1146         case 4 ... 5:
1147                 if (vcpu->arch.cr4 & X86_CR4_DE)
1148                         *exception = UD_VECTOR;
1149                 return;
1150         case 6:
1151                 if (value & 0xffffffff00000000ULL) {
1152                         *exception = GP_VECTOR;
1153                         return;
1154                 }
1155                 vcpu->arch.dr6 = (value & DR6_VOLATILE) | DR6_FIXED_1;
1156                 return;
1157         case 7:
1158                 if (value & 0xffffffff00000000ULL) {
1159                         *exception = GP_VECTOR;
1160                         return;
1161                 }
1162                 vcpu->arch.dr7 = (value & DR7_VOLATILE) | DR7_FIXED_1;
1163                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1164                         svm->vmcb->save.dr7 = vcpu->arch.dr7;
1165                         vcpu->arch.switch_db_regs = (value & DR7_BP_EN_MASK);
1166                 }
1167                 return;
1168         default:
1169                 /* FIXME: Possible case? */
1170                 printk(KERN_DEBUG "%s: unexpected dr %u\n",
1171                        __func__, dr);
1172                 *exception = UD_VECTOR;
1173                 return;
1174         }
1175 }
1176
1177 static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1178 {
1179         u64 fault_address;
1180         u32 error_code;
1181
1182         fault_address  = svm->vmcb->control.exit_info_2;
1183         error_code = svm->vmcb->control.exit_info_1;
1184
1185         trace_kvm_page_fault(fault_address, error_code);
1186         /*
1187          * FIXME: Tis shouldn't be necessary here, but there is a flush
1188          * missing in the MMU code. Until we find this bug, flush the
1189          * complete TLB here on an NPF
1190          */
1191         if (npt_enabled)
1192                 svm_flush_tlb(&svm->vcpu);
1193         else {
1194                 if (kvm_event_needs_reinjection(&svm->vcpu))
1195                         kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1196         }
1197         return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1198 }
1199
1200 static int db_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1201 {
1202         if (!(svm->vcpu.guest_debug &
1203               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1204                 !svm->vcpu.arch.singlestep) {
1205                 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1206                 return 1;
1207         }
1208
1209         if (svm->vcpu.arch.singlestep) {
1210                 svm->vcpu.arch.singlestep = false;
1211                 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1212                         svm->vmcb->save.rflags &=
1213                                 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1214                 update_db_intercept(&svm->vcpu);
1215         }
1216
1217         if (svm->vcpu.guest_debug &
1218             (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)){
1219                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1220                 kvm_run->debug.arch.pc =
1221                         svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1222                 kvm_run->debug.arch.exception = DB_VECTOR;
1223                 return 0;
1224         }
1225
1226         return 1;
1227 }
1228
1229 static int bp_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1230 {
1231         kvm_run->exit_reason = KVM_EXIT_DEBUG;
1232         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1233         kvm_run->debug.arch.exception = BP_VECTOR;
1234         return 0;
1235 }
1236
1237 static int ud_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1238 {
1239         int er;
1240
1241         er = emulate_instruction(&svm->vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
1242         if (er != EMULATE_DONE)
1243                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1244         return 1;
1245 }
1246
1247 static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1248 {
1249         svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
1250         if (!(svm->vcpu.arch.cr0 & X86_CR0_TS))
1251                 svm->vmcb->save.cr0 &= ~X86_CR0_TS;
1252         svm->vcpu.fpu_active = 1;
1253
1254         return 1;
1255 }
1256
1257 static int mc_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1258 {
1259         /*
1260          * On an #MC intercept the MCE handler is not called automatically in
1261          * the host. So do it by hand here.
1262          */
1263         asm volatile (
1264                 "int $0x12\n");
1265         /* not sure if we ever come back to this point */
1266
1267         return 1;
1268 }
1269
1270 static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1271 {
1272         /*
1273          * VMCB is undefined after a SHUTDOWN intercept
1274          * so reinitialize it.
1275          */
1276         clear_page(svm->vmcb);
1277         init_vmcb(svm);
1278
1279         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1280         return 0;
1281 }
1282
1283 static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1284 {
1285         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1286         int size, in, string;
1287         unsigned port;
1288
1289         ++svm->vcpu.stat.io_exits;
1290
1291         svm->next_rip = svm->vmcb->control.exit_info_2;
1292
1293         string = (io_info & SVM_IOIO_STR_MASK) != 0;
1294
1295         if (string) {
1296                 if (emulate_instruction(&svm->vcpu,
1297                                         kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
1298                         return 0;
1299                 return 1;
1300         }
1301
1302         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1303         port = io_info >> 16;
1304         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1305
1306         skip_emulated_instruction(&svm->vcpu);
1307         return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port);
1308 }
1309
1310 static int nmi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1311 {
1312         return 1;
1313 }
1314
1315 static int intr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1316 {
1317         ++svm->vcpu.stat.irq_exits;
1318         return 1;
1319 }
1320
1321 static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1322 {
1323         return 1;
1324 }
1325
1326 static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1327 {
1328         svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1329         skip_emulated_instruction(&svm->vcpu);
1330         return kvm_emulate_halt(&svm->vcpu);
1331 }
1332
1333 static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1334 {
1335         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1336         skip_emulated_instruction(&svm->vcpu);
1337         kvm_emulate_hypercall(&svm->vcpu);
1338         return 1;
1339 }
1340
1341 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1342 {
1343         if (!(svm->vcpu.arch.shadow_efer & EFER_SVME)
1344             || !is_paging(&svm->vcpu)) {
1345                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1346                 return 1;
1347         }
1348
1349         if (svm->vmcb->save.cpl) {
1350                 kvm_inject_gp(&svm->vcpu, 0);
1351                 return 1;
1352         }
1353
1354        return 0;
1355 }
1356
1357 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1358                                       bool has_error_code, u32 error_code)
1359 {
1360         if (!is_nested(svm))
1361                 return 0;
1362
1363         svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1364         svm->vmcb->control.exit_code_hi = 0;
1365         svm->vmcb->control.exit_info_1 = error_code;
1366         svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1367
1368         return nested_svm_exit_handled(svm, false);
1369 }
1370
1371 static inline int nested_svm_intr(struct vcpu_svm *svm)
1372 {
1373         if (is_nested(svm)) {
1374                 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1375                         return 0;
1376
1377                 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1378                         return 0;
1379
1380                 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1381
1382                 if (nested_svm_exit_handled(svm, false)) {
1383                         nsvm_printk("VMexit -> INTR\n");
1384                         return 1;
1385                 }
1386         }
1387
1388         return 0;
1389 }
1390
1391 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, enum km_type idx)
1392 {
1393         struct page *page;
1394
1395         down_read(&current->mm->mmap_sem);
1396         page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1397         up_read(&current->mm->mmap_sem);
1398
1399         if (is_error_page(page))
1400                 goto error;
1401
1402         return kmap_atomic(page, idx);
1403
1404 error:
1405         kvm_release_page_clean(page);
1406         kvm_inject_gp(&svm->vcpu, 0);
1407
1408         return NULL;
1409 }
1410
1411 static void nested_svm_unmap(void *addr, enum km_type idx)
1412 {
1413         struct page *page;
1414
1415         if (!addr)
1416                 return;
1417
1418         page = kmap_atomic_to_page(addr);
1419
1420         kunmap_atomic(addr, idx);
1421         kvm_release_page_dirty(page);
1422 }
1423
1424 static bool nested_svm_exit_handled_msr(struct vcpu_svm *svm)
1425 {
1426         u32 param = svm->vmcb->control.exit_info_1 & 1;
1427         u32 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1428         bool ret = false;
1429         u32 t0, t1;
1430         u8 *msrpm;
1431
1432         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1433                 return false;
1434
1435         msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, KM_USER0);
1436
1437         if (!msrpm)
1438                 goto out;
1439
1440         switch (msr) {
1441         case 0 ... 0x1fff:
1442                 t0 = (msr * 2) % 8;
1443                 t1 = msr / 8;
1444                 break;
1445         case 0xc0000000 ... 0xc0001fff:
1446                 t0 = (8192 + msr - 0xc0000000) * 2;
1447                 t1 = (t0 / 8);
1448                 t0 %= 8;
1449                 break;
1450         case 0xc0010000 ... 0xc0011fff:
1451                 t0 = (16384 + msr - 0xc0010000) * 2;
1452                 t1 = (t0 / 8);
1453                 t0 %= 8;
1454                 break;
1455         default:
1456                 ret = true;
1457                 goto out;
1458         }
1459
1460         ret = msrpm[t1] & ((1 << param) << t0);
1461
1462 out:
1463         nested_svm_unmap(msrpm, KM_USER0);
1464
1465         return ret;
1466 }
1467
1468 static int nested_svm_exit_handled(struct vcpu_svm *svm, bool kvm_override)
1469 {
1470         u32 exit_code = svm->vmcb->control.exit_code;
1471         bool vmexit = false;
1472
1473         if (kvm_override) {
1474                 switch (exit_code) {
1475                 case SVM_EXIT_INTR:
1476                 case SVM_EXIT_NMI:
1477                         return 0;
1478                 /* For now we are always handling NPFs when using them */
1479                 case SVM_EXIT_NPF:
1480                         if (npt_enabled)
1481                                 return 0;
1482                         break;
1483                 /* When we're shadowing, trap PFs */
1484                 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1485                         if (!npt_enabled)
1486                                 return 0;
1487                         break;
1488                 default:
1489                         break;
1490                 }
1491         }
1492
1493         switch (exit_code) {
1494         case SVM_EXIT_MSR:
1495                 vmexit = nested_svm_exit_handled_msr(svm);
1496                 break;
1497         case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1498                 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
1499                 if (svm->nested.intercept_cr_read & cr_bits)
1500                         vmexit = true;
1501                 break;
1502         }
1503         case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1504                 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
1505                 if (svm->nested.intercept_cr_write & cr_bits)
1506                         vmexit = true;
1507                 break;
1508         }
1509         case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1510                 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
1511                 if (svm->nested.intercept_dr_read & dr_bits)
1512                         vmexit = true;
1513                 break;
1514         }
1515         case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1516                 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
1517                 if (svm->nested.intercept_dr_write & dr_bits)
1518                         vmexit = true;
1519                 break;
1520         }
1521         case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1522                 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
1523                 if (svm->nested.intercept_exceptions & excp_bits)
1524                         vmexit = true;
1525                 break;
1526         }
1527         default: {
1528                 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
1529                 nsvm_printk("exit code: 0x%x\n", exit_code);
1530                 if (svm->nested.intercept & exit_bits)
1531                         vmexit = true;
1532         }
1533         }
1534
1535         if (vmexit) {
1536                 nsvm_printk("#VMEXIT reason=%04x\n", exit_code);
1537                 nested_svm_vmexit(svm);
1538         }
1539
1540         return vmexit;
1541 }
1542
1543 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
1544 {
1545         struct vmcb_control_area *dst  = &dst_vmcb->control;
1546         struct vmcb_control_area *from = &from_vmcb->control;
1547
1548         dst->intercept_cr_read    = from->intercept_cr_read;
1549         dst->intercept_cr_write   = from->intercept_cr_write;
1550         dst->intercept_dr_read    = from->intercept_dr_read;
1551         dst->intercept_dr_write   = from->intercept_dr_write;
1552         dst->intercept_exceptions = from->intercept_exceptions;
1553         dst->intercept            = from->intercept;
1554         dst->iopm_base_pa         = from->iopm_base_pa;
1555         dst->msrpm_base_pa        = from->msrpm_base_pa;
1556         dst->tsc_offset           = from->tsc_offset;
1557         dst->asid                 = from->asid;
1558         dst->tlb_ctl              = from->tlb_ctl;
1559         dst->int_ctl              = from->int_ctl;
1560         dst->int_vector           = from->int_vector;
1561         dst->int_state            = from->int_state;
1562         dst->exit_code            = from->exit_code;
1563         dst->exit_code_hi         = from->exit_code_hi;
1564         dst->exit_info_1          = from->exit_info_1;
1565         dst->exit_info_2          = from->exit_info_2;
1566         dst->exit_int_info        = from->exit_int_info;
1567         dst->exit_int_info_err    = from->exit_int_info_err;
1568         dst->nested_ctl           = from->nested_ctl;
1569         dst->event_inj            = from->event_inj;
1570         dst->event_inj_err        = from->event_inj_err;
1571         dst->nested_cr3           = from->nested_cr3;
1572         dst->lbr_ctl              = from->lbr_ctl;
1573 }
1574
1575 static int nested_svm_vmexit(struct vcpu_svm *svm)
1576 {
1577         struct vmcb *nested_vmcb;
1578         struct vmcb *hsave = svm->nested.hsave;
1579         struct vmcb *vmcb = svm->vmcb;
1580
1581         nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, KM_USER0);
1582         if (!nested_vmcb)
1583                 return 1;
1584
1585         /* Give the current vmcb to the guest */
1586         disable_gif(svm);
1587
1588         nested_vmcb->save.es     = vmcb->save.es;
1589         nested_vmcb->save.cs     = vmcb->save.cs;
1590         nested_vmcb->save.ss     = vmcb->save.ss;
1591         nested_vmcb->save.ds     = vmcb->save.ds;
1592         nested_vmcb->save.gdtr   = vmcb->save.gdtr;
1593         nested_vmcb->save.idtr   = vmcb->save.idtr;
1594         if (npt_enabled)
1595                 nested_vmcb->save.cr3    = vmcb->save.cr3;
1596         nested_vmcb->save.cr2    = vmcb->save.cr2;
1597         nested_vmcb->save.rflags = vmcb->save.rflags;
1598         nested_vmcb->save.rip    = vmcb->save.rip;
1599         nested_vmcb->save.rsp    = vmcb->save.rsp;
1600         nested_vmcb->save.rax    = vmcb->save.rax;
1601         nested_vmcb->save.dr7    = vmcb->save.dr7;
1602         nested_vmcb->save.dr6    = vmcb->save.dr6;
1603         nested_vmcb->save.cpl    = vmcb->save.cpl;
1604
1605         nested_vmcb->control.int_ctl           = vmcb->control.int_ctl;
1606         nested_vmcb->control.int_vector        = vmcb->control.int_vector;
1607         nested_vmcb->control.int_state         = vmcb->control.int_state;
1608         nested_vmcb->control.exit_code         = vmcb->control.exit_code;
1609         nested_vmcb->control.exit_code_hi      = vmcb->control.exit_code_hi;
1610         nested_vmcb->control.exit_info_1       = vmcb->control.exit_info_1;
1611         nested_vmcb->control.exit_info_2       = vmcb->control.exit_info_2;
1612         nested_vmcb->control.exit_int_info     = vmcb->control.exit_int_info;
1613         nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
1614         nested_vmcb->control.tlb_ctl           = 0;
1615         nested_vmcb->control.event_inj         = 0;
1616         nested_vmcb->control.event_inj_err     = 0;
1617
1618         /* We always set V_INTR_MASKING and remember the old value in hflags */
1619         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1620                 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1621
1622         /* Restore the original control entries */
1623         copy_vmcb_control_area(vmcb, hsave);
1624
1625         /* Kill any pending exceptions */
1626         if (svm->vcpu.arch.exception.pending == true)
1627                 nsvm_printk("WARNING: Pending Exception\n");
1628
1629         kvm_clear_exception_queue(&svm->vcpu);
1630         kvm_clear_interrupt_queue(&svm->vcpu);
1631
1632         /* Restore selected save entries */
1633         svm->vmcb->save.es = hsave->save.es;
1634         svm->vmcb->save.cs = hsave->save.cs;
1635         svm->vmcb->save.ss = hsave->save.ss;
1636         svm->vmcb->save.ds = hsave->save.ds;
1637         svm->vmcb->save.gdtr = hsave->save.gdtr;
1638         svm->vmcb->save.idtr = hsave->save.idtr;
1639         svm->vmcb->save.rflags = hsave->save.rflags;
1640         svm_set_efer(&svm->vcpu, hsave->save.efer);
1641         svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1642         svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1643         if (npt_enabled) {
1644                 svm->vmcb->save.cr3 = hsave->save.cr3;
1645                 svm->vcpu.arch.cr3 = hsave->save.cr3;
1646         } else {
1647                 kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1648         }
1649         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1650         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1651         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1652         svm->vmcb->save.dr7 = 0;
1653         svm->vmcb->save.cpl = 0;
1654         svm->vmcb->control.exit_int_info = 0;
1655
1656         /* Exit nested SVM mode */
1657         svm->nested.vmcb = 0;
1658
1659         nested_svm_unmap(nested_vmcb, KM_USER0);
1660
1661         kvm_mmu_reset_context(&svm->vcpu);
1662         kvm_mmu_load(&svm->vcpu);
1663
1664         return 0;
1665 }
1666
1667 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
1668 {
1669         u32 *nested_msrpm;
1670         int i;
1671
1672         nested_msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, KM_USER0);
1673         if (!nested_msrpm)
1674                 return false;
1675
1676         for (i=0; i< PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER) / 4; i++)
1677                 svm->nested.msrpm[i] = svm->msrpm[i] | nested_msrpm[i];
1678
1679         svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
1680
1681         nested_svm_unmap(nested_msrpm, KM_USER0);
1682
1683         return true;
1684 }
1685
1686 static bool nested_svm_vmrun(struct vcpu_svm *svm)
1687 {
1688         struct vmcb *nested_vmcb;
1689         struct vmcb *hsave = svm->nested.hsave;
1690         struct vmcb *vmcb = svm->vmcb;
1691
1692         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1693         if (!nested_vmcb)
1694                 return false;
1695
1696         /* nested_vmcb is our indicator if nested SVM is activated */
1697         svm->nested.vmcb = svm->vmcb->save.rax;
1698
1699         /* Clear internal status */
1700         kvm_clear_exception_queue(&svm->vcpu);
1701         kvm_clear_interrupt_queue(&svm->vcpu);
1702
1703         /* Save the old vmcb, so we don't need to pick what we save, but
1704            can restore everything when a VMEXIT occurs */
1705         hsave->save.es     = vmcb->save.es;
1706         hsave->save.cs     = vmcb->save.cs;
1707         hsave->save.ss     = vmcb->save.ss;
1708         hsave->save.ds     = vmcb->save.ds;
1709         hsave->save.gdtr   = vmcb->save.gdtr;
1710         hsave->save.idtr   = vmcb->save.idtr;
1711         hsave->save.efer   = svm->vcpu.arch.shadow_efer;
1712         hsave->save.cr0    = svm->vcpu.arch.cr0;
1713         hsave->save.cr4    = svm->vcpu.arch.cr4;
1714         hsave->save.rflags = vmcb->save.rflags;
1715         hsave->save.rip    = svm->next_rip;
1716         hsave->save.rsp    = vmcb->save.rsp;
1717         hsave->save.rax    = vmcb->save.rax;
1718         if (npt_enabled)
1719                 hsave->save.cr3    = vmcb->save.cr3;
1720         else
1721                 hsave->save.cr3    = svm->vcpu.arch.cr3;
1722
1723         copy_vmcb_control_area(hsave, vmcb);
1724
1725         if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
1726                 svm->vcpu.arch.hflags |= HF_HIF_MASK;
1727         else
1728                 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
1729
1730         /* Load the nested guest state */
1731         svm->vmcb->save.es = nested_vmcb->save.es;
1732         svm->vmcb->save.cs = nested_vmcb->save.cs;
1733         svm->vmcb->save.ss = nested_vmcb->save.ss;
1734         svm->vmcb->save.ds = nested_vmcb->save.ds;
1735         svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
1736         svm->vmcb->save.idtr = nested_vmcb->save.idtr;
1737         svm->vmcb->save.rflags = nested_vmcb->save.rflags;
1738         svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
1739         svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
1740         svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
1741         if (npt_enabled) {
1742                 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
1743                 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
1744         } else {
1745                 kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
1746                 kvm_mmu_reset_context(&svm->vcpu);
1747         }
1748         svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
1749         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
1750         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
1751         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
1752         /* In case we don't even reach vcpu_run, the fields are not updated */
1753         svm->vmcb->save.rax = nested_vmcb->save.rax;
1754         svm->vmcb->save.rsp = nested_vmcb->save.rsp;
1755         svm->vmcb->save.rip = nested_vmcb->save.rip;
1756         svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
1757         svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
1758         svm->vmcb->save.cpl = nested_vmcb->save.cpl;
1759
1760         /* We don't want a nested guest to be more powerful than the guest,
1761            so all intercepts are ORed */
1762         svm->vmcb->control.intercept_cr_read |=
1763                 nested_vmcb->control.intercept_cr_read;
1764         svm->vmcb->control.intercept_cr_write |=
1765                 nested_vmcb->control.intercept_cr_write;
1766         svm->vmcb->control.intercept_dr_read |=
1767                 nested_vmcb->control.intercept_dr_read;
1768         svm->vmcb->control.intercept_dr_write |=
1769                 nested_vmcb->control.intercept_dr_write;
1770         svm->vmcb->control.intercept_exceptions |=
1771                 nested_vmcb->control.intercept_exceptions;
1772
1773         svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
1774
1775         svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa;
1776
1777         /* cache intercepts */
1778         svm->nested.intercept_cr_read    = nested_vmcb->control.intercept_cr_read;
1779         svm->nested.intercept_cr_write   = nested_vmcb->control.intercept_cr_write;
1780         svm->nested.intercept_dr_read    = nested_vmcb->control.intercept_dr_read;
1781         svm->nested.intercept_dr_write   = nested_vmcb->control.intercept_dr_write;
1782         svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
1783         svm->nested.intercept            = nested_vmcb->control.intercept;
1784
1785         force_new_asid(&svm->vcpu);
1786         svm->vmcb->control.exit_int_info = nested_vmcb->control.exit_int_info;
1787         svm->vmcb->control.exit_int_info_err = nested_vmcb->control.exit_int_info_err;
1788         svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
1789         if (nested_vmcb->control.int_ctl & V_IRQ_MASK) {
1790                 nsvm_printk("nSVM Injecting Interrupt: 0x%x\n",
1791                                 nested_vmcb->control.int_ctl);
1792         }
1793         if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
1794                 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
1795         else
1796                 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
1797
1798         nsvm_printk("nSVM exit_int_info: 0x%x | int_state: 0x%x\n",
1799                         nested_vmcb->control.exit_int_info,
1800                         nested_vmcb->control.int_state);
1801
1802         svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
1803         svm->vmcb->control.int_state = nested_vmcb->control.int_state;
1804         svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
1805         if (nested_vmcb->control.event_inj & SVM_EVTINJ_VALID)
1806                 nsvm_printk("Injecting Event: 0x%x\n",
1807                                 nested_vmcb->control.event_inj);
1808         svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
1809         svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
1810
1811         nested_svm_unmap(nested_vmcb, KM_USER0);
1812
1813         enable_gif(svm);
1814
1815         return true;
1816 }
1817
1818 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
1819 {
1820         to_vmcb->save.fs = from_vmcb->save.fs;
1821         to_vmcb->save.gs = from_vmcb->save.gs;
1822         to_vmcb->save.tr = from_vmcb->save.tr;
1823         to_vmcb->save.ldtr = from_vmcb->save.ldtr;
1824         to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
1825         to_vmcb->save.star = from_vmcb->save.star;
1826         to_vmcb->save.lstar = from_vmcb->save.lstar;
1827         to_vmcb->save.cstar = from_vmcb->save.cstar;
1828         to_vmcb->save.sfmask = from_vmcb->save.sfmask;
1829         to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
1830         to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
1831         to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
1832 }
1833
1834 static int vmload_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1835 {
1836         struct vmcb *nested_vmcb;
1837
1838         if (nested_svm_check_permissions(svm))
1839                 return 1;
1840
1841         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1842         skip_emulated_instruction(&svm->vcpu);
1843
1844         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1845         if (!nested_vmcb)
1846                 return 1;
1847
1848         nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
1849         nested_svm_unmap(nested_vmcb, KM_USER0);
1850
1851         return 1;
1852 }
1853
1854 static int vmsave_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1855 {
1856         struct vmcb *nested_vmcb;
1857
1858         if (nested_svm_check_permissions(svm))
1859                 return 1;
1860
1861         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1862         skip_emulated_instruction(&svm->vcpu);
1863
1864         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1865         if (!nested_vmcb)
1866                 return 1;
1867
1868         nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
1869         nested_svm_unmap(nested_vmcb, KM_USER0);
1870
1871         return 1;
1872 }
1873
1874 static int vmrun_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1875 {
1876         nsvm_printk("VMrun\n");
1877         if (nested_svm_check_permissions(svm))
1878                 return 1;
1879
1880         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1881         skip_emulated_instruction(&svm->vcpu);
1882
1883         if (!nested_svm_vmrun(svm))
1884                 return 1;
1885
1886         if (!nested_svm_vmrun_msrpm(svm))
1887                 return 1;
1888
1889         return 1;
1890 }
1891
1892 static int stgi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1893 {
1894         if (nested_svm_check_permissions(svm))
1895                 return 1;
1896
1897         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1898         skip_emulated_instruction(&svm->vcpu);
1899
1900         enable_gif(svm);
1901
1902         return 1;
1903 }
1904
1905 static int clgi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1906 {
1907         if (nested_svm_check_permissions(svm))
1908                 return 1;
1909
1910         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1911         skip_emulated_instruction(&svm->vcpu);
1912
1913         disable_gif(svm);
1914
1915         /* After a CLGI no interrupts should come */
1916         svm_clear_vintr(svm);
1917         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1918
1919         return 1;
1920 }
1921
1922 static int invlpga_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1923 {
1924         struct kvm_vcpu *vcpu = &svm->vcpu;
1925         nsvm_printk("INVLPGA\n");
1926
1927         /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
1928         kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
1929
1930         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1931         skip_emulated_instruction(&svm->vcpu);
1932         return 1;
1933 }
1934
1935 static int invalid_op_interception(struct vcpu_svm *svm,
1936                                    struct kvm_run *kvm_run)
1937 {
1938         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1939         return 1;
1940 }
1941
1942 static int task_switch_interception(struct vcpu_svm *svm,
1943                                     struct kvm_run *kvm_run)
1944 {
1945         u16 tss_selector;
1946         int reason;
1947         int int_type = svm->vmcb->control.exit_int_info &
1948                 SVM_EXITINTINFO_TYPE_MASK;
1949         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
1950         uint32_t type =
1951                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
1952         uint32_t idt_v =
1953                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
1954
1955         tss_selector = (u16)svm->vmcb->control.exit_info_1;
1956
1957         if (svm->vmcb->control.exit_info_2 &
1958             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
1959                 reason = TASK_SWITCH_IRET;
1960         else if (svm->vmcb->control.exit_info_2 &
1961                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
1962                 reason = TASK_SWITCH_JMP;
1963         else if (idt_v)
1964                 reason = TASK_SWITCH_GATE;
1965         else
1966                 reason = TASK_SWITCH_CALL;
1967
1968         if (reason == TASK_SWITCH_GATE) {
1969                 switch (type) {
1970                 case SVM_EXITINTINFO_TYPE_NMI:
1971                         svm->vcpu.arch.nmi_injected = false;
1972                         break;
1973                 case SVM_EXITINTINFO_TYPE_EXEPT:
1974                         kvm_clear_exception_queue(&svm->vcpu);
1975                         break;
1976                 case SVM_EXITINTINFO_TYPE_INTR:
1977                         kvm_clear_interrupt_queue(&svm->vcpu);
1978                         break;
1979                 default:
1980                         break;
1981                 }
1982         }
1983
1984         if (reason != TASK_SWITCH_GATE ||
1985             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
1986             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
1987              (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
1988                 skip_emulated_instruction(&svm->vcpu);
1989
1990         return kvm_task_switch(&svm->vcpu, tss_selector, reason);
1991 }
1992
1993 static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1994 {
1995         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
1996         kvm_emulate_cpuid(&svm->vcpu);
1997         return 1;
1998 }
1999
2000 static int iret_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2001 {
2002         ++svm->vcpu.stat.nmi_window_exits;
2003         svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
2004         svm->vcpu.arch.hflags |= HF_IRET_MASK;
2005         return 1;
2006 }
2007
2008 static int invlpg_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2009 {
2010         if (emulate_instruction(&svm->vcpu, kvm_run, 0, 0, 0) != EMULATE_DONE)
2011                 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2012         return 1;
2013 }
2014
2015 static int emulate_on_interception(struct vcpu_svm *svm,
2016                                    struct kvm_run *kvm_run)
2017 {
2018         if (emulate_instruction(&svm->vcpu, NULL, 0, 0, 0) != EMULATE_DONE)
2019                 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2020         return 1;
2021 }
2022
2023 static int cr8_write_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2024 {
2025         u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2026         /* instruction emulation calls kvm_set_cr8() */
2027         emulate_instruction(&svm->vcpu, NULL, 0, 0, 0);
2028         if (irqchip_in_kernel(svm->vcpu.kvm)) {
2029                 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2030                 return 1;
2031         }
2032         if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2033                 return 1;
2034         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2035         return 0;
2036 }
2037
2038 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2039 {
2040         struct vcpu_svm *svm = to_svm(vcpu);
2041
2042         switch (ecx) {
2043         case MSR_IA32_TSC: {
2044                 u64 tsc;
2045
2046                 rdtscll(tsc);
2047                 *data = svm->vmcb->control.tsc_offset + tsc;
2048                 break;
2049         }
2050         case MSR_K6_STAR:
2051                 *data = svm->vmcb->save.star;
2052                 break;
2053 #ifdef CONFIG_X86_64
2054         case MSR_LSTAR:
2055                 *data = svm->vmcb->save.lstar;
2056                 break;
2057         case MSR_CSTAR:
2058                 *data = svm->vmcb->save.cstar;
2059                 break;
2060         case MSR_KERNEL_GS_BASE:
2061                 *data = svm->vmcb->save.kernel_gs_base;
2062                 break;
2063         case MSR_SYSCALL_MASK:
2064                 *data = svm->vmcb->save.sfmask;
2065                 break;
2066 #endif
2067         case MSR_IA32_SYSENTER_CS:
2068                 *data = svm->vmcb->save.sysenter_cs;
2069                 break;
2070         case MSR_IA32_SYSENTER_EIP:
2071                 *data = svm->sysenter_eip;
2072                 break;
2073         case MSR_IA32_SYSENTER_ESP:
2074                 *data = svm->sysenter_esp;
2075                 break;
2076         /* Nobody will change the following 5 values in the VMCB so
2077            we can safely return them on rdmsr. They will always be 0
2078            until LBRV is implemented. */
2079         case MSR_IA32_DEBUGCTLMSR:
2080                 *data = svm->vmcb->save.dbgctl;
2081                 break;
2082         case MSR_IA32_LASTBRANCHFROMIP:
2083                 *data = svm->vmcb->save.br_from;
2084                 break;
2085         case MSR_IA32_LASTBRANCHTOIP:
2086                 *data = svm->vmcb->save.br_to;
2087                 break;
2088         case MSR_IA32_LASTINTFROMIP:
2089                 *data = svm->vmcb->save.last_excp_from;
2090                 break;
2091         case MSR_IA32_LASTINTTOIP:
2092                 *data = svm->vmcb->save.last_excp_to;
2093                 break;
2094         case MSR_VM_HSAVE_PA:
2095                 *data = svm->nested.hsave_msr;
2096                 break;
2097         case MSR_VM_CR:
2098                 *data = 0;
2099                 break;
2100         case MSR_IA32_UCODE_REV:
2101                 *data = 0x01000065;
2102                 break;
2103         default:
2104                 return kvm_get_msr_common(vcpu, ecx, data);
2105         }
2106         return 0;
2107 }
2108
2109 static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2110 {
2111         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2112         u64 data;
2113
2114         if (svm_get_msr(&svm->vcpu, ecx, &data))
2115                 kvm_inject_gp(&svm->vcpu, 0);
2116         else {
2117                 trace_kvm_msr_read(ecx, data);
2118
2119                 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
2120                 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
2121                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2122                 skip_emulated_instruction(&svm->vcpu);
2123         }
2124         return 1;
2125 }
2126
2127 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2128 {
2129         struct vcpu_svm *svm = to_svm(vcpu);
2130
2131         switch (ecx) {
2132         case MSR_IA32_TSC: {
2133                 u64 tsc;
2134
2135                 rdtscll(tsc);
2136                 svm->vmcb->control.tsc_offset = data - tsc;
2137                 break;
2138         }
2139         case MSR_K6_STAR:
2140                 svm->vmcb->save.star = data;
2141                 break;
2142 #ifdef CONFIG_X86_64
2143         case MSR_LSTAR:
2144                 svm->vmcb->save.lstar = data;
2145                 break;
2146         case MSR_CSTAR:
2147                 svm->vmcb->save.cstar = data;
2148                 break;
2149         case MSR_KERNEL_GS_BASE:
2150                 svm->vmcb->save.kernel_gs_base = data;
2151                 break;
2152         case MSR_SYSCALL_MASK:
2153                 svm->vmcb->save.sfmask = data;
2154                 break;
2155 #endif
2156         case MSR_IA32_SYSENTER_CS:
2157                 svm->vmcb->save.sysenter_cs = data;
2158                 break;
2159         case MSR_IA32_SYSENTER_EIP:
2160                 svm->sysenter_eip = data;
2161                 svm->vmcb->save.sysenter_eip = data;
2162                 break;
2163         case MSR_IA32_SYSENTER_ESP:
2164                 svm->sysenter_esp = data;
2165                 svm->vmcb->save.sysenter_esp = data;
2166                 break;
2167         case MSR_IA32_DEBUGCTLMSR:
2168                 if (!svm_has(SVM_FEATURE_LBRV)) {
2169                         pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2170                                         __func__, data);
2171                         break;
2172                 }
2173                 if (data & DEBUGCTL_RESERVED_BITS)
2174                         return 1;
2175
2176                 svm->vmcb->save.dbgctl = data;
2177                 if (data & (1ULL<<0))
2178                         svm_enable_lbrv(svm);
2179                 else
2180                         svm_disable_lbrv(svm);
2181                 break;
2182         case MSR_VM_HSAVE_PA:
2183                 svm->nested.hsave_msr = data;
2184                 break;
2185         case MSR_VM_CR:
2186         case MSR_VM_IGNNE:
2187                 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2188                 break;
2189         default:
2190                 return kvm_set_msr_common(vcpu, ecx, data);
2191         }
2192         return 0;
2193 }
2194
2195 static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2196 {
2197         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2198         u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
2199                 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2200
2201         trace_kvm_msr_write(ecx, data);
2202
2203         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2204         if (svm_set_msr(&svm->vcpu, ecx, data))
2205                 kvm_inject_gp(&svm->vcpu, 0);
2206         else
2207                 skip_emulated_instruction(&svm->vcpu);
2208         return 1;
2209 }
2210
2211 static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2212 {
2213         if (svm->vmcb->control.exit_info_1)
2214                 return wrmsr_interception(svm, kvm_run);
2215         else
2216                 return rdmsr_interception(svm, kvm_run);
2217 }
2218
2219 static int interrupt_window_interception(struct vcpu_svm *svm,
2220                                    struct kvm_run *kvm_run)
2221 {
2222         svm_clear_vintr(svm);
2223         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2224         /*
2225          * If the user space waits to inject interrupts, exit as soon as
2226          * possible
2227          */
2228         if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2229             kvm_run->request_interrupt_window &&
2230             !kvm_cpu_has_interrupt(&svm->vcpu)) {
2231                 ++svm->vcpu.stat.irq_window_exits;
2232                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2233                 return 0;
2234         }
2235
2236         return 1;
2237 }
2238
2239 static int (*svm_exit_handlers[])(struct vcpu_svm *svm,
2240                                       struct kvm_run *kvm_run) = {
2241         [SVM_EXIT_READ_CR0]                     = emulate_on_interception,
2242         [SVM_EXIT_READ_CR3]                     = emulate_on_interception,
2243         [SVM_EXIT_READ_CR4]                     = emulate_on_interception,
2244         [SVM_EXIT_READ_CR8]                     = emulate_on_interception,
2245         /* for now: */
2246         [SVM_EXIT_WRITE_CR0]                    = emulate_on_interception,
2247         [SVM_EXIT_WRITE_CR3]                    = emulate_on_interception,
2248         [SVM_EXIT_WRITE_CR4]                    = emulate_on_interception,
2249         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
2250         [SVM_EXIT_READ_DR0]                     = emulate_on_interception,
2251         [SVM_EXIT_READ_DR1]                     = emulate_on_interception,
2252         [SVM_EXIT_READ_DR2]                     = emulate_on_interception,
2253         [SVM_EXIT_READ_DR3]                     = emulate_on_interception,
2254         [SVM_EXIT_WRITE_DR0]                    = emulate_on_interception,
2255         [SVM_EXIT_WRITE_DR1]                    = emulate_on_interception,
2256         [SVM_EXIT_WRITE_DR2]                    = emulate_on_interception,
2257         [SVM_EXIT_WRITE_DR3]                    = emulate_on_interception,
2258         [SVM_EXIT_WRITE_DR5]                    = emulate_on_interception,
2259         [SVM_EXIT_WRITE_DR7]                    = emulate_on_interception,
2260         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
2261         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
2262         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
2263         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
2264         [SVM_EXIT_EXCP_BASE + NM_VECTOR]        = nm_interception,
2265         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
2266         [SVM_EXIT_INTR]                         = intr_interception,
2267         [SVM_EXIT_NMI]                          = nmi_interception,
2268         [SVM_EXIT_SMI]                          = nop_on_interception,
2269         [SVM_EXIT_INIT]                         = nop_on_interception,
2270         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
2271         /* [SVM_EXIT_CR0_SEL_WRITE]             = emulate_on_interception, */
2272         [SVM_EXIT_CPUID]                        = cpuid_interception,
2273         [SVM_EXIT_IRET]                         = iret_interception,
2274         [SVM_EXIT_INVD]                         = emulate_on_interception,
2275         [SVM_EXIT_HLT]                          = halt_interception,
2276         [SVM_EXIT_INVLPG]                       = invlpg_interception,
2277         [SVM_EXIT_INVLPGA]                      = invlpga_interception,
2278         [SVM_EXIT_IOIO]                         = io_interception,
2279         [SVM_EXIT_MSR]                          = msr_interception,
2280         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
2281         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
2282         [SVM_EXIT_VMRUN]                        = vmrun_interception,
2283         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
2284         [SVM_EXIT_VMLOAD]                       = vmload_interception,
2285         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
2286         [SVM_EXIT_STGI]                         = stgi_interception,
2287         [SVM_EXIT_CLGI]                         = clgi_interception,
2288         [SVM_EXIT_SKINIT]                       = invalid_op_interception,
2289         [SVM_EXIT_WBINVD]                       = emulate_on_interception,
2290         [SVM_EXIT_MONITOR]                      = invalid_op_interception,
2291         [SVM_EXIT_MWAIT]                        = invalid_op_interception,
2292         [SVM_EXIT_NPF]                          = pf_interception,
2293 };
2294
2295 static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
2296 {
2297         struct vcpu_svm *svm = to_svm(vcpu);
2298         u32 exit_code = svm->vmcb->control.exit_code;
2299
2300         trace_kvm_exit(exit_code, svm->vmcb->save.rip);
2301
2302         if (is_nested(svm)) {
2303                 nsvm_printk("nested handle_exit: 0x%x | 0x%lx | 0x%lx | 0x%lx\n",
2304                             exit_code, svm->vmcb->control.exit_info_1,
2305                             svm->vmcb->control.exit_info_2, svm->vmcb->save.rip);
2306                 if (nested_svm_exit_handled(svm, true))
2307                         return 1;
2308         }
2309
2310         svm_complete_interrupts(svm);
2311
2312         if (npt_enabled) {
2313                 int mmu_reload = 0;
2314                 if ((vcpu->arch.cr0 ^ svm->vmcb->save.cr0) & X86_CR0_PG) {
2315                         svm_set_cr0(vcpu, svm->vmcb->save.cr0);
2316                         mmu_reload = 1;
2317                 }
2318                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2319                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
2320                 if (mmu_reload) {
2321                         kvm_mmu_reset_context(vcpu);
2322                         kvm_mmu_load(vcpu);
2323                 }
2324         }
2325
2326
2327         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2328                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2329                 kvm_run->fail_entry.hardware_entry_failure_reason
2330                         = svm->vmcb->control.exit_code;
2331                 return 0;
2332         }
2333
2334         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
2335             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
2336             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH)
2337                 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2338                        "exit_code 0x%x\n",
2339                        __func__, svm->vmcb->control.exit_int_info,
2340                        exit_code);
2341
2342         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
2343             || !svm_exit_handlers[exit_code]) {
2344                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2345                 kvm_run->hw.hardware_exit_reason = exit_code;
2346                 return 0;
2347         }
2348
2349         return svm_exit_handlers[exit_code](svm, kvm_run);
2350 }
2351
2352 static void reload_tss(struct kvm_vcpu *vcpu)
2353 {
2354         int cpu = raw_smp_processor_id();
2355
2356         struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
2357         svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */
2358         load_TR_desc();
2359 }
2360
2361 static void pre_svm_run(struct vcpu_svm *svm)
2362 {
2363         int cpu = raw_smp_processor_id();
2364
2365         struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
2366
2367         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
2368         /* FIXME: handle wraparound of asid_generation */
2369         if (svm->asid_generation != svm_data->asid_generation)
2370                 new_asid(svm, svm_data);
2371 }
2372
2373 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
2374 {
2375         struct vcpu_svm *svm = to_svm(vcpu);
2376
2377         svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
2378         vcpu->arch.hflags |= HF_NMI_MASK;
2379         svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2380         ++vcpu->stat.nmi_injections;
2381 }
2382
2383 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
2384 {
2385         struct vmcb_control_area *control;
2386
2387         trace_kvm_inj_virq(irq);
2388
2389         ++svm->vcpu.stat.irq_injections;
2390         control = &svm->vmcb->control;
2391         control->int_vector = irq;
2392         control->int_ctl &= ~V_INTR_PRIO_MASK;
2393         control->int_ctl |= V_IRQ_MASK |
2394                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2395 }
2396
2397 static void svm_set_irq(struct kvm_vcpu *vcpu)
2398 {
2399         struct vcpu_svm *svm = to_svm(vcpu);
2400
2401         BUG_ON(!(gif_set(svm)));
2402
2403         svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
2404                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2405 }
2406
2407 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
2408 {
2409         struct vcpu_svm *svm = to_svm(vcpu);
2410
2411         if (irr == -1)
2412                 return;
2413
2414         if (tpr >= irr)
2415                 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2416 }
2417
2418 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
2419 {
2420         struct vcpu_svm *svm = to_svm(vcpu);
2421         struct vmcb *vmcb = svm->vmcb;
2422         return !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2423                 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
2424 }
2425
2426 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
2427 {
2428         struct vcpu_svm *svm = to_svm(vcpu);
2429         struct vmcb *vmcb = svm->vmcb;
2430         return (vmcb->save.rflags & X86_EFLAGS_IF) &&
2431                 !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2432                 gif_set(svm) &&
2433                 !is_nested(svm);
2434 }
2435
2436 static void enable_irq_window(struct kvm_vcpu *vcpu)
2437 {
2438         struct vcpu_svm *svm = to_svm(vcpu);
2439         nsvm_printk("Trying to open IRQ window\n");
2440
2441         nested_svm_intr(svm);
2442
2443         /* In case GIF=0 we can't rely on the CPU to tell us when
2444          * GIF becomes 1, because that's a separate STGI/VMRUN intercept.
2445          * The next time we get that intercept, this function will be
2446          * called again though and we'll get the vintr intercept. */
2447         if (gif_set(svm)) {
2448                 svm_set_vintr(svm);
2449                 svm_inject_irq(svm, 0x0);
2450         }
2451 }
2452
2453 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2454 {
2455         struct vcpu_svm *svm = to_svm(vcpu);
2456
2457         if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
2458             == HF_NMI_MASK)
2459                 return; /* IRET will cause a vm exit */
2460
2461         /* Something prevents NMI from been injected. Single step over
2462            possible problem (IRET or exception injection or interrupt
2463            shadow) */
2464         vcpu->arch.singlestep = true;
2465         svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2466         update_db_intercept(vcpu);
2467 }
2468
2469 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
2470 {
2471         return 0;
2472 }
2473
2474 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
2475 {
2476         force_new_asid(vcpu);
2477 }
2478
2479 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
2480 {
2481 }
2482
2483 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
2484 {
2485         struct vcpu_svm *svm = to_svm(vcpu);
2486
2487         if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
2488                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
2489                 kvm_set_cr8(vcpu, cr8);
2490         }
2491 }
2492
2493 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
2494 {
2495         struct vcpu_svm *svm = to_svm(vcpu);
2496         u64 cr8;
2497
2498         cr8 = kvm_get_cr8(vcpu);
2499         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
2500         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
2501 }
2502
2503 static void svm_complete_interrupts(struct vcpu_svm *svm)
2504 {
2505         u8 vector;
2506         int type;
2507         u32 exitintinfo = svm->vmcb->control.exit_int_info;
2508
2509         if (svm->vcpu.arch.hflags & HF_IRET_MASK)
2510                 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
2511
2512         svm->vcpu.arch.nmi_injected = false;
2513         kvm_clear_exception_queue(&svm->vcpu);
2514         kvm_clear_interrupt_queue(&svm->vcpu);
2515
2516         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
2517                 return;
2518
2519         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
2520         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
2521
2522         switch (type) {
2523         case SVM_EXITINTINFO_TYPE_NMI:
2524                 svm->vcpu.arch.nmi_injected = true;
2525                 break;
2526         case SVM_EXITINTINFO_TYPE_EXEPT:
2527                 /* In case of software exception do not reinject an exception
2528                    vector, but re-execute and instruction instead */
2529                 if (is_nested(svm))
2530                         break;
2531                 if (kvm_exception_is_soft(vector))
2532                         break;
2533                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
2534                         u32 err = svm->vmcb->control.exit_int_info_err;
2535                         kvm_queue_exception_e(&svm->vcpu, vector, err);
2536
2537                 } else
2538                         kvm_queue_exception(&svm->vcpu, vector);
2539                 break;
2540         case SVM_EXITINTINFO_TYPE_INTR:
2541                 kvm_queue_interrupt(&svm->vcpu, vector, false);
2542                 break;
2543         default:
2544                 break;
2545         }
2546 }
2547
2548 #ifdef CONFIG_X86_64
2549 #define R "r"
2550 #else
2551 #define R "e"
2552 #endif
2553
2554 static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2555 {
2556         struct vcpu_svm *svm = to_svm(vcpu);
2557         u16 fs_selector;
2558         u16 gs_selector;
2559         u16 ldt_selector;
2560
2561         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
2562         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
2563         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
2564
2565         pre_svm_run(svm);
2566
2567         sync_lapic_to_cr8(vcpu);
2568
2569         save_host_msrs(vcpu);
2570         fs_selector = kvm_read_fs();
2571         gs_selector = kvm_read_gs();
2572         ldt_selector = kvm_read_ldt();
2573         if (!is_nested(svm))
2574                 svm->vmcb->save.cr2 = vcpu->arch.cr2;
2575         /* required for live migration with NPT */
2576         if (npt_enabled)
2577                 svm->vmcb->save.cr3 = vcpu->arch.cr3;
2578
2579         clgi();
2580
2581         local_irq_enable();
2582
2583         asm volatile (
2584                 "push %%"R"bp; \n\t"
2585                 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
2586                 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
2587                 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
2588                 "mov %c[rsi](%[svm]), %%"R"si \n\t"
2589                 "mov %c[rdi](%[svm]), %%"R"di \n\t"
2590                 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
2591 #ifdef CONFIG_X86_64
2592                 "mov %c[r8](%[svm]),  %%r8  \n\t"
2593                 "mov %c[r9](%[svm]),  %%r9  \n\t"
2594                 "mov %c[r10](%[svm]), %%r10 \n\t"
2595                 "mov %c[r11](%[svm]), %%r11 \n\t"
2596                 "mov %c[r12](%[svm]), %%r12 \n\t"
2597                 "mov %c[r13](%[svm]), %%r13 \n\t"
2598                 "mov %c[r14](%[svm]), %%r14 \n\t"
2599                 "mov %c[r15](%[svm]), %%r15 \n\t"
2600 #endif
2601
2602                 /* Enter guest mode */
2603                 "push %%"R"ax \n\t"
2604                 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
2605                 __ex(SVM_VMLOAD) "\n\t"
2606                 __ex(SVM_VMRUN) "\n\t"
2607                 __ex(SVM_VMSAVE) "\n\t"
2608                 "pop %%"R"ax \n\t"
2609
2610                 /* Save guest registers, load host registers */
2611                 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
2612                 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
2613                 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
2614                 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
2615                 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
2616                 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
2617 #ifdef CONFIG_X86_64
2618                 "mov %%r8,  %c[r8](%[svm]) \n\t"
2619                 "mov %%r9,  %c[r9](%[svm]) \n\t"
2620                 "mov %%r10, %c[r10](%[svm]) \n\t"
2621                 "mov %%r11, %c[r11](%[svm]) \n\t"
2622                 "mov %%r12, %c[r12](%[svm]) \n\t"
2623                 "mov %%r13, %c[r13](%[svm]) \n\t"
2624                 "mov %%r14, %c[r14](%[svm]) \n\t"
2625                 "mov %%r15, %c[r15](%[svm]) \n\t"
2626 #endif
2627                 "pop %%"R"bp"
2628                 :
2629                 : [svm]"a"(svm),
2630                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
2631                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
2632                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
2633                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
2634                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
2635                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
2636                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
2637 #ifdef CONFIG_X86_64
2638                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
2639                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
2640                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
2641                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
2642                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
2643                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
2644                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
2645                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
2646 #endif
2647                 : "cc", "memory"
2648                 , R"bx", R"cx", R"dx", R"si", R"di"
2649 #ifdef CONFIG_X86_64
2650                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
2651 #endif
2652                 );
2653
2654         vcpu->arch.cr2 = svm->vmcb->save.cr2;
2655         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
2656         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
2657         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
2658
2659         kvm_load_fs(fs_selector);
2660         kvm_load_gs(gs_selector);
2661         kvm_load_ldt(ldt_selector);
2662         load_host_msrs(vcpu);
2663
2664         reload_tss(vcpu);
2665
2666         local_irq_disable();
2667
2668         stgi();
2669
2670         sync_cr8_to_lapic(vcpu);
2671
2672         svm->next_rip = 0;
2673
2674         if (npt_enabled) {
2675                 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
2676                 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
2677         }
2678 }
2679
2680 #undef R
2681
2682 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
2683 {
2684         struct vcpu_svm *svm = to_svm(vcpu);
2685
2686         if (npt_enabled) {
2687                 svm->vmcb->control.nested_cr3 = root;
2688                 force_new_asid(vcpu);
2689                 return;
2690         }
2691
2692         svm->vmcb->save.cr3 = root;
2693         force_new_asid(vcpu);
2694
2695         if (vcpu->fpu_active) {
2696                 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
2697                 svm->vmcb->save.cr0 |= X86_CR0_TS;
2698                 vcpu->fpu_active = 0;
2699         }
2700 }
2701
2702 static int is_disabled(void)
2703 {
2704         u64 vm_cr;
2705
2706         rdmsrl(MSR_VM_CR, vm_cr);
2707         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
2708                 return 1;
2709
2710         return 0;
2711 }
2712
2713 static void
2714 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2715 {
2716         /*
2717          * Patch in the VMMCALL instruction:
2718          */
2719         hypercall[0] = 0x0f;
2720         hypercall[1] = 0x01;
2721         hypercall[2] = 0xd9;
2722 }
2723
2724 static void svm_check_processor_compat(void *rtn)
2725 {
2726         *(int *)rtn = 0;
2727 }
2728
2729 static bool svm_cpu_has_accelerated_tpr(void)
2730 {
2731         return false;
2732 }
2733
2734 static int get_npt_level(void)
2735 {
2736 #ifdef CONFIG_X86_64
2737         return PT64_ROOT_LEVEL;
2738 #else
2739         return PT32E_ROOT_LEVEL;
2740 #endif
2741 }
2742
2743 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
2744 {
2745         return 0;
2746 }
2747
2748 static const struct trace_print_flags svm_exit_reasons_str[] = {
2749         { SVM_EXIT_READ_CR0,                    "read_cr0" },
2750         { SVM_EXIT_READ_CR3,                    "read_cr3" },
2751         { SVM_EXIT_READ_CR4,                    "read_cr4" },
2752         { SVM_EXIT_READ_CR8,                    "read_cr8" },
2753         { SVM_EXIT_WRITE_CR0,                   "write_cr0" },
2754         { SVM_EXIT_WRITE_CR3,                   "write_cr3" },
2755         { SVM_EXIT_WRITE_CR4,                   "write_cr4" },
2756         { SVM_EXIT_WRITE_CR8,                   "write_cr8" },
2757         { SVM_EXIT_READ_DR0,                    "read_dr0" },
2758         { SVM_EXIT_READ_DR1,                    "read_dr1" },
2759         { SVM_EXIT_READ_DR2,                    "read_dr2" },
2760         { SVM_EXIT_READ_DR3,                    "read_dr3" },
2761         { SVM_EXIT_WRITE_DR0,                   "write_dr0" },
2762         { SVM_EXIT_WRITE_DR1,                   "write_dr1" },
2763         { SVM_EXIT_WRITE_DR2,                   "write_dr2" },
2764         { SVM_EXIT_WRITE_DR3,                   "write_dr3" },
2765         { SVM_EXIT_WRITE_DR5,                   "write_dr5" },
2766         { SVM_EXIT_WRITE_DR7,                   "write_dr7" },
2767         { SVM_EXIT_EXCP_BASE + DB_VECTOR,       "DB excp" },
2768         { SVM_EXIT_EXCP_BASE + BP_VECTOR,       "BP excp" },
2769         { SVM_EXIT_EXCP_BASE + UD_VECTOR,       "UD excp" },
2770         { SVM_EXIT_EXCP_BASE + PF_VECTOR,       "PF excp" },
2771         { SVM_EXIT_EXCP_BASE + NM_VECTOR,       "NM excp" },
2772         { SVM_EXIT_EXCP_BASE + MC_VECTOR,       "MC excp" },
2773         { SVM_EXIT_INTR,                        "interrupt" },
2774         { SVM_EXIT_NMI,                         "nmi" },
2775         { SVM_EXIT_SMI,                         "smi" },
2776         { SVM_EXIT_INIT,                        "init" },
2777         { SVM_EXIT_VINTR,                       "vintr" },
2778         { SVM_EXIT_CPUID,                       "cpuid" },
2779         { SVM_EXIT_INVD,                        "invd" },
2780         { SVM_EXIT_HLT,                         "hlt" },
2781         { SVM_EXIT_INVLPG,                      "invlpg" },
2782         { SVM_EXIT_INVLPGA,                     "invlpga" },
2783         { SVM_EXIT_IOIO,                        "io" },
2784         { SVM_EXIT_MSR,                         "msr" },
2785         { SVM_EXIT_TASK_SWITCH,                 "task_switch" },
2786         { SVM_EXIT_SHUTDOWN,                    "shutdown" },
2787         { SVM_EXIT_VMRUN,                       "vmrun" },
2788         { SVM_EXIT_VMMCALL,                     "hypercall" },
2789         { SVM_EXIT_VMLOAD,                      "vmload" },
2790         { SVM_EXIT_VMSAVE,                      "vmsave" },
2791         { SVM_EXIT_STGI,                        "stgi" },
2792         { SVM_EXIT_CLGI,                        "clgi" },
2793         { SVM_EXIT_SKINIT,                      "skinit" },
2794         { SVM_EXIT_WBINVD,                      "wbinvd" },
2795         { SVM_EXIT_MONITOR,                     "monitor" },
2796         { SVM_EXIT_MWAIT,                       "mwait" },
2797         { SVM_EXIT_NPF,                         "npf" },
2798         { -1, NULL }
2799 };
2800
2801 static bool svm_gb_page_enable(void)
2802 {
2803         return true;
2804 }
2805
2806 static struct kvm_x86_ops svm_x86_ops = {
2807         .cpu_has_kvm_support = has_svm,
2808         .disabled_by_bios = is_disabled,
2809         .hardware_setup = svm_hardware_setup,
2810         .hardware_unsetup = svm_hardware_unsetup,
2811         .check_processor_compatibility = svm_check_processor_compat,
2812         .hardware_enable = svm_hardware_enable,
2813         .hardware_disable = svm_hardware_disable,
2814         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
2815
2816         .vcpu_create = svm_create_vcpu,
2817         .vcpu_free = svm_free_vcpu,
2818         .vcpu_reset = svm_vcpu_reset,
2819
2820         .prepare_guest_switch = svm_prepare_guest_switch,
2821         .vcpu_load = svm_vcpu_load,
2822         .vcpu_put = svm_vcpu_put,
2823
2824         .set_guest_debug = svm_guest_debug,
2825         .get_msr = svm_get_msr,
2826         .set_msr = svm_set_msr,
2827         .get_segment_base = svm_get_segment_base,
2828         .get_segment = svm_get_segment,
2829         .set_segment = svm_set_segment,
2830         .get_cpl = svm_get_cpl,
2831         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
2832         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
2833         .set_cr0 = svm_set_cr0,
2834         .set_cr3 = svm_set_cr3,
2835         .set_cr4 = svm_set_cr4,
2836         .set_efer = svm_set_efer,
2837         .get_idt = svm_get_idt,
2838         .set_idt = svm_set_idt,
2839         .get_gdt = svm_get_gdt,
2840         .set_gdt = svm_set_gdt,
2841         .get_dr = svm_get_dr,
2842         .set_dr = svm_set_dr,
2843         .cache_reg = svm_cache_reg,
2844         .get_rflags = svm_get_rflags,
2845         .set_rflags = svm_set_rflags,
2846
2847         .tlb_flush = svm_flush_tlb,
2848
2849         .run = svm_vcpu_run,
2850         .handle_exit = handle_exit,
2851         .skip_emulated_instruction = skip_emulated_instruction,
2852         .set_interrupt_shadow = svm_set_interrupt_shadow,
2853         .get_interrupt_shadow = svm_get_interrupt_shadow,
2854         .patch_hypercall = svm_patch_hypercall,
2855         .set_irq = svm_set_irq,
2856         .set_nmi = svm_inject_nmi,
2857         .queue_exception = svm_queue_exception,
2858         .interrupt_allowed = svm_interrupt_allowed,
2859         .nmi_allowed = svm_nmi_allowed,
2860         .enable_nmi_window = enable_nmi_window,
2861         .enable_irq_window = enable_irq_window,
2862         .update_cr8_intercept = update_cr8_intercept,
2863
2864         .set_tss_addr = svm_set_tss_addr,
2865         .get_tdp_level = get_npt_level,
2866         .get_mt_mask = svm_get_mt_mask,
2867
2868         .exit_reasons_str = svm_exit_reasons_str,
2869         .gb_page_enable = svm_gb_page_enable,
2870 };
2871
2872 static int __init svm_init(void)
2873 {
2874         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
2875                               THIS_MODULE);
2876 }
2877
2878 static void __exit svm_exit(void)
2879 {
2880         kvm_exit();
2881 }
2882
2883 module_init(svm_init)
2884 module_exit(svm_exit)