board/Marvell/rd6281a/rd6281a.c

   1 /*
   2  * (C) Copyright 2009
   3  * Marvell Semiconductor <www.marvell.com>
   4  * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  22  * MA 02110-1301 USA
  23  */
  24
  25 #include <common.h>
  26 #include <miiphy.h>
  27 #include <netdev.h>
  28 #include <asm/arch/kirkwood.h>
  29 #include <asm/arch/mpp.h>
  30 #include "rd6281a.h"
  31
  32 DECLARE_GLOBAL_DATA_PTR;
  33
  34 int board_init(void)
  35 {
  36         /*
  37          * default gpio configuration
  38          * There are maximum 64 gpios controlled through 2 sets of registers
  39          * the  below configuration configures mainly initial LED status
  40          */
  41         kw_config_gpio(RD6281A_OE_VAL_LOW,
  42                         RD6281A_OE_VAL_HIGH,
  43                         RD6281A_OE_LOW, RD6281A_OE_HIGH);
  44
  45         /* Multi-Purpose Pins Functionality configuration */
  46         u32 kwmpp_config[] = {
  47                 MPP0_NF_IO2,
  48                 MPP1_NF_IO3,
  49                 MPP2_NF_IO4,
  50                 MPP3_NF_IO5,
  51                 MPP4_NF_IO6,
  52                 MPP5_NF_IO7,
  53                 MPP6_SYSRST_OUTn,
  54                 MPP7_GPO,
  55                 MPP8_TW_SDA,
  56                 MPP9_TW_SCK,
  57                 MPP10_UART0_TXD,
  58                 MPP11_UART0_RXD,
  59                 MPP12_SD_CLK,
  60                 MPP13_SD_CMD,
  61                 MPP14_SD_D0,
  62                 MPP15_SD_D1,
  63                 MPP16_SD_D2,
  64                 MPP17_SD_D3,
  65                 MPP18_NF_IO0,
  66                 MPP19_NF_IO1,
  67                 MPP20_GE1_0,
  68                 MPP21_GE1_1,
  69                 MPP22_GE1_2,
  70                 MPP23_GE1_3,
  71                 MPP24_GE1_4,
  72                 MPP25_GE1_5,
  73                 MPP26_GE1_6,
  74                 MPP27_GE1_7,
  75                 MPP28_GPIO,
  76                 MPP29_GPIO,
  77                 MPP30_GE1_10,
  78                 MPP31_GE1_11,
  79                 MPP32_GE1_12,
  80                 MPP33_GE1_13,
  81                 MPP34_GE1_14,
  82                 MPP35_GPIO,
  83                 MPP36_AUDIO_SPDIFI,
  84                 MPP37_AUDIO_SPDIFO,
  85                 MPP38_GPIO,
  86                 MPP39_TDM_SPI_CS0,
  87                 MPP40_TDM_SPI_SCK,
  88                 MPP41_TDM_SPI_MISO,
  89                 MPP42_TDM_SPI_MOSI,
  90                 MPP43_TDM_CODEC_INTn,
  91                 MPP44_GPIO,
  92                 MPP45_TDM_PCLK,
  93                 MPP46_TDM_FS,
  94                 MPP47_TDM_DRX,
  95                 MPP48_TDM_DTX,
  96                 MPP49_GPIO,
  97                 0
  98         };
  99         kirkwood_mpp_conf(kwmpp_config);
 100
 101         /*
 102          * arch number of board
 103          */
 104         gd->bd->bi_arch_number = MACH_TYPE_RD88F6281;
 105
 106         /* adress of boot parameters */
 107         gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
 108
 109         return 0;
 110 }
 111
 112 int dram_init(void)
 113 {
 114         int i;
 115
 116         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
 117                 gd->bd->bi_dram[i].start = kw_sdram_bar(i);
 118                 gd->bd->bi_dram[i].size = kw_sdram_bs(i);
 119         }
 120         return 0;
 121 }
 122
 123 void mv_phy_88e1116_init(char *name)
 124 {
 125         u16 reg;
 126         u16 devadr;
 127
 128         if (miiphy_set_current_dev(name))
 129                 return;
 130
 131         /* command to read PHY dev address */
 132         if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
 133                 printf("Err..%s could not read PHY dev address\n",
 134                         __FUNCTION__);
 135                 return;
 136         }
 137
 138         /*
 139          * Enable RGMII delay on Tx and Rx for CPU port
 140          * Ref: sec 4.7.2 of chip datasheet
 141          */
 142         miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
 143         miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
 144         reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
 145         miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
 146         miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
 147
 148         /* reset the phy */
 149         if (miiphy_read (name, devadr, PHY_BMCR, &reg) != 0) {
 150                 printf("Err..(%s) PHY status read failed\n", __FUNCTION__);
 151                 return;
 152         }
 153         if (miiphy_write (name, devadr, PHY_BMCR, reg | 0x8000) != 0) {
 154                 printf("Err..(%s) PHY reset failed\n", __FUNCTION__);
 155                 return;
 156         }
 157
 158         printf("88E1116 Initialized on %s\n", name);
 159 }
 160
 161 /* Configure and enable Switch and PHY */
 162 void reset_phy(void)
 163 {
 164         /* configure and initialize switch */
 165         struct mv88e61xx_config swcfg = {
 166                 .name = "egiga0",
 167                 .vlancfg = MV88E61XX_VLANCFG_ROUTER,
 168                 .rgmii_delay = MV88E61XX_RGMII_DELAY_EN,
 169                 .led_init = MV88E61XX_LED_INIT_EN,
 170                 .portstate = MV88E61XX_PORTSTT_FORWARDING,
 171                 .cpuport = (1 << 5),
 172                 .ports_enabled = 0x3f,
 173         };
 174
 175         mv88e61xx_switch_initialize(&swcfg);
 176
 177         /* configure and initialize PHY */
 178         mv_phy_88e1116_init("egiga1");
 179 }