3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
14 * I/O Port configuration table
16 * if conf is 1, then that port pin will be configured at boot time
17 * according to the five values podr/pdir/ppar/psor/pdat for that entry
20 const iop_conf_t iop_conf_tab[4][32] = {
22 /* Port A configuration */
23 { /* conf ppar psor pdir podr pdat */
24 /* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */
25 /* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */
26 /* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */
27 /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */
28 /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */
29 /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */
30 /* PA25 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII MDIO */
31 /* PA24 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII MDC */
32 /* PA23 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII MDIO */
33 /* PA22 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII MDC */
34 /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */
35 /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */
36 /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */
37 /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */
38 /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */
39 /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */
40 /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */
41 /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */
42 /* PA13 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII TXSL1 */
43 /* PA12 */ { 1, 0, 0, 1, 0, 1 }, /* FCC2 MII TXSL0 */
44 /* PA11 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII TXSL1 */
45 /* PA10 */ { 1, 0, 0, 1, 0, 1 }, /* FCC1 MII TXSL0 */
47 /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC2 TXD */
48 /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC2 RXD */
50 /* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */
51 /* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RXD */
53 /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */
54 /* PA6 */ { 1, 0, 0, 1, 0, 1 }, /* FCC2 MII PAUSE */
55 /* PA5 */ { 1, 0, 0, 1, 0, 1 }, /* FCC1 MII PAUSE */
56 /* PA4 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII PWRDN */
57 /* PA3 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII PWRDN */
58 /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */
59 /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FCC2 MII MDINT */
60 /* PA0 */ { 1, 0, 0, 1, 0, 0 } /* FCC1 MII MDINT */
63 /* Port B configuration */
64 { /* conf ppar psor pdir podr pdat */
65 /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
66 /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
67 /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
68 /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
69 /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
70 /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
71 /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
72 /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
73 /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
74 /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
75 /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
76 /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
77 /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
78 /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
79 /* PB17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_DV */
80 /* PB16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_ER */
81 /* PB15 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_ER */
82 /* PB14 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_EN */
83 /* PB13 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII COL */
84 /* PB12 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII CRS */
85 /* PB11 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD */
86 /* PB10 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD */
87 /* PB9 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD */
88 /* PB8 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD */
89 /* PB7 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD */
90 /* PB6 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD */
91 /* PB5 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD */
92 /* PB4 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD */
93 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* PB3 */
94 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* PB2 */
95 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* PB1 */
96 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* PB0 */
100 { /* conf ppar psor pdir podr pdat */
101 /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */
102 /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */
103 /* PC29 */ { 1, 0, 0, 0, 0, 0 }, /* SCC1 CTS */
104 /* PC28 */ { 1, 0, 0, 0, 0, 0 }, /* SCC2 CTS */
105 /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */
106 /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */
107 /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */
108 /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */
109 /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* FDC37C78 DACFD */
110 /* PC22 */ { 0, 0, 0, 0, 0, 0 }, /* FDC37C78 DNFD */
111 /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RX_CLK */
112 /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII TX_CLK */
113 /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */
114 /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */
115 /* PC17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_CLK */
116 /* PC16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII TX_CLK */
118 /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */
120 /* PC15 */ { 1, 1, 0, 1, 0, 0 }, /* PC15 */
122 /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */
123 /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */
124 /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */
125 /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */
126 /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */
127 /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* FC9 */
128 /* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* PC8 */
129 /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */
130 /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */
131 /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */
132 /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */
133 /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */
134 /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */
135 /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */
136 /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* FDC37C78 DRQFD */
140 { /* conf ppar psor pdir podr pdat */
141 /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 RXD */
142 /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 TXD */
143 /* PD29 */ { 1, 0, 0, 1, 0, 0 }, /* SCC1 RTS */
144 /* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RXD */
145 /* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 TXD */
146 /* PD26 */ { 1, 0, 0, 1, 0, 0 }, /* SCC2 RTS */
147 /* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */
148 /* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */
149 /* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */
150 /* PD22 */ { 0, 0, 0, 0, 0, 0 }, /* PD22 */
151 /* PD21 */ { 0, 0, 0, 0, 0, 0 }, /* PD21 */
152 /* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* PD20 */
153 /* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */
154 /* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */
155 /* PD17 */ { 0, 0, 0, 0, 0, 0 }, /* PD17 */
156 /* PD16 */ { 0, 0, 0, 0, 0, 0 }, /* PD16 */
157 #if defined(CONFIG_SYS_I2C_SOFT)
158 /* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */
159 /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */
161 #if defined(CONFIG_HARD_I2C)
162 /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
163 /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
164 #else /* normal I/O port pins */
165 /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
166 /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
169 /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
170 /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
171 /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
172 /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
173 /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
174 /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
175 /* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */
176 /* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* PD6 */
177 /* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* PD5 */
179 /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */
181 /* PD4 */ { 1, 1, 1, 0, 0, 0 }, /* PD4 */
183 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* PD3 */
184 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* PD2 */
185 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* PD1 */
186 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* PD0 */
191 * UPMB initialization table
193 #define _NOT_USED_ 0xFFFFFFFF
195 static const uint rtc_table[] =
198 * Single Read. (Offset 0 in UPMA RAM)
200 0xfffec00, 0xfffac00, 0xfff2d00, 0xfef2800,
201 0xfaf2080, 0xfaf2080, 0xfff2400, 0x1fff6c05, /* last */
203 * Burst Read. (Offset 8 in UPMA RAM)
205 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
206 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
207 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
208 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
210 * Single Write. (Offset 18 in UPMA RAM)
212 0xfffec00, 0xfffac00, 0xfff2d00, 0xfef2800,
213 0xfaf2080, 0xfaf2080, 0xfaf2400, 0x1fbf6c05, /* last */
215 * Burst Write. (Offset 20 in UPMA RAM)
217 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
218 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
219 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
220 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
222 * Refresh (Offset 30 in UPMA RAM)
224 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
225 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
226 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
228 * Exception. (Offset 3c in UPMA RAM)
230 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
233 /* ------------------------------------------------------------------------- */
235 /* Check Board Identity:
237 int checkboard (void)
239 printf ("Board: ATC\n");
243 /* ------------------------------------------------------------------------- */
245 /* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
247 * This routine performs standard 8260 initialization sequence
248 * and calculates the available memory size. It may be called
249 * several times to try different SDRAM configurations on both
250 * 60x and local buses.
252 static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
253 ulong orx, volatile uchar * base)
255 volatile uchar c = 0xff;
256 volatile uint *sdmr_ptr;
257 volatile uint *orx_ptr;
261 /* We must be able to test a location outsize the maximum legal size
262 * to find out THAT we are outside; but this address still has to be
263 * mapped by the controller. That means, that the initial mapping has
264 * to be (at least) twice as large as the maximum expected size.
266 maxsize = (1 + (~orx | 0x7fff)) / 2;
268 /* Since CONFIG_SYS_SDRAM_BASE is always 0 (??), we assume that
269 * we are configuring CS1 if base != 0
271 sdmr_ptr = &memctl->memc_psdmr;
272 orx_ptr = &memctl->memc_or2;
277 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
279 * "At system reset, initialization software must set up the
280 * programmable parameters in the memory controller banks registers
281 * (ORx, BRx, P/LSDMR). After all memory parameters are configured,
282 * system software should execute the following initialization sequence
283 * for each SDRAM device.
285 * 1. Issue a PRECHARGE-ALL-BANKS command
286 * 2. Issue eight CBR REFRESH commands
287 * 3. Issue a MODE-SET command to initialize the mode register
289 * The initial commands are executed by setting P/LSDMR[OP] and
290 * accessing the SDRAM with a single-byte transaction."
292 * The appropriate BRx/ORx registers have already been set when we
293 * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
296 *sdmr_ptr = sdmr | PSDMR_OP_PREA;
299 *sdmr_ptr = sdmr | PSDMR_OP_CBRR;
300 for (i = 0; i < 8; i++)
303 *sdmr_ptr = sdmr | PSDMR_OP_MRW;
304 *(base + CONFIG_SYS_MRS_OFFS) = c; /* setting MR on address lines */
306 *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
309 size = get_ram_size((long *)base, maxsize);
311 *orx_ptr = orx | ~(size - 1);
316 int misc_init_r(void)
318 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
319 volatile memctl8260_t *memctl = &immap->im_memctl;
321 upmconfig(UPMA, (uint *)rtc_table, sizeof(rtc_table) / sizeof(uint));
322 memctl->memc_mamr = MxMR_RLFx_6X | MxMR_WLFx_6X | MxMR_OP_NORM;
327 phys_size_t initdram (int board_type)
329 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
330 volatile memctl8260_t *memctl = &immap->im_memctl;
332 #ifndef CONFIG_SYS_RAMBOOT
337 psize = 8 * 1024 * 1024;
339 memctl->memc_mptpr = CONFIG_SYS_MPTPR;
340 memctl->memc_psrt = CONFIG_SYS_PSRT;
342 #ifndef CONFIG_SYS_RAMBOOT
345 size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL,
346 (uchar *) CONFIG_SYS_SDRAM_BASE);
347 size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR2_9COL,
348 (uchar *) CONFIG_SYS_SDRAM_BASE);
352 printf ("(60x:9COL) ");
354 psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL,
355 (uchar *) CONFIG_SYS_SDRAM_BASE);
356 printf ("(60x:8COL) ");
359 #endif /* CONFIG_SYS_RAMBOOT */
366 #if defined(CONFIG_CMD_DOC)
369 doc_probe (CONFIG_SYS_DOC_BASE);
374 struct pci_controller hose;
376 extern void pci_mpc8250_init(struct pci_controller *);
378 void pci_init_board(void)
380 pci_mpc8250_init(&hose);