board/balloon3/balloon3.c

   1 /*
   2  * Balloon3 Support
   3  *
   4  * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <asm/arch/hardware.h>
  11 #include <asm/arch/pxa.h>
  12 #include <serial.h>
  13 #include <asm/io.h>
  14 #include <spartan3.h>
  15 #include <command.h>
  16
  17 DECLARE_GLOBAL_DATA_PTR;
  18
  19 void balloon3_init_fpga(void);
  20
  21 /*
  22  * Miscelaneous platform dependent initialisations
  23  */
  24
  25 int board_init(void)
  26 {
  27         /* We have RAM, disable cache */
  28         dcache_disable();
  29         icache_disable();
  30
  31         /* arch number of vpac270 */
  32         gd->bd->bi_arch_number = MACH_TYPE_BALLOON3;
  33
  34         /* adress of boot parameters */
  35         gd->bd->bi_boot_params = 0xa0000100;
  36
  37         /* Init the FPGA */
  38         balloon3_init_fpga();
  39
  40         return 0;
  41 }
  42
  43 int dram_init(void)
  44 {
  45         pxa2xx_dram_init();
  46         gd->ram_size = PHYS_SDRAM_1_SIZE;
  47         return 0;
  48 }
  49
  50 void dram_init_banksize(void)
  51 {
  52         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  53         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
  54         gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
  55
  56         gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
  57         gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
  58         gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
  59 }
  60
  61 #ifdef  CONFIG_CMD_USB
  62 int usb_board_init(void)
  63 {
  64         writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) &
  65                 ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
  66                 UHCHR);
  67
  68         writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
  69
  70         while (readl(UHCHR) & UHCHR_FSBIR)
  71                 ;
  72
  73         writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
  74         writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
  75
  76         /* Clear any OTG Pin Hold */
  77         if (readl(PSSR) & PSSR_OTGPH)
  78                 writel(readl(PSSR) | PSSR_OTGPH, PSSR);
  79
  80         writel(readl(UHCRHDA) & ~(0x200), UHCRHDA);
  81         writel(readl(UHCRHDA) | 0x100, UHCRHDA);
  82
  83         /* Set port power control mask bits, only 3 ports. */
  84         writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
  85
  86         /* enable port 2 */
  87         writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
  88                 UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR);
  89
  90         return 0;
  91 }
  92
  93 void usb_board_init_fail(void)
  94 {
  95         return;
  96 }
  97
  98 void usb_board_stop(void)
  99 {
 100         writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
 101         udelay(11);
 102         writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
 103
 104         writel(readl(UHCCOMS) | 1, UHCCOMS);
 105         udelay(10);
 106
 107         writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
 108
 109         return;
 110 }
 111 #endif
 112
 113 #if defined(CONFIG_FPGA)
 114 /* Toggle GPIO103 and GPIO104 --  PROGB and RDnWR */
 115 int fpga_pgm_fn(int nassert, int nflush, int cookie)
 116 {
 117         if (nassert)
 118                 writel(0x80, GPCR3);
 119         else
 120                 writel(0x80, GPSR3);
 121         if (nflush)
 122                 writel(0x100, GPCR3);
 123         else
 124                 writel(0x100, GPSR3);
 125         return nassert;
 126 }
 127
 128 /* Check GPIO83 -- INITB */
 129 int fpga_init_fn(int cookie)
 130 {
 131         return !(readl(GPLR2) & 0x80000);
 132 }
 133
 134 /* Check GPIO84 -- BUSY */
 135 int fpga_busy_fn(int cookie)
 136 {
 137         return !(readl(GPLR2) & 0x100000);
 138 }
 139
 140 /* Check GPIO111 -- DONE */
 141 int fpga_done_fn(int cookie)
 142 {
 143         return readl(GPLR3) & 0x8000;
 144 }
 145
 146 /* Configure GPIO104 as GPIO and deassert it */
 147 int fpga_pre_config_fn(int cookie)
 148 {
 149         writel(readl(GAFR3_L) & ~0x30000, GAFR3_L);
 150         writel(0x100, GPCR3);
 151         return 0;
 152 }
 153
 154 /* Configure GPIO104 as nSKTSEL */
 155 int fpga_post_config_fn(int cookie)
 156 {
 157         writel(readl(GAFR3_L) | 0x10000, GAFR3_L);
 158         return 0;
 159 }
 160
 161 /* Toggle RDnWR */
 162 int fpga_wr_fn(int nassert_write, int flush, int cookie)
 163 {
 164         udelay(1000);
 165
 166         if (nassert_write)
 167                 writel(0x100, GPCR3);
 168         else
 169                 writel(0x100, GPSR3);
 170
 171         return nassert_write;
 172 }
 173
 174 /* Write program to the FPGA */
 175 int fpga_wdata_fn(uchar data, int flush, int cookie)
 176 {
 177         writeb(data, 0x10f00000);
 178         return 0;
 179 }
 180
 181 /* Toggle Clock pin -- NO-OP */
 182 int fpga_clk_fn(int assert_clk, int flush, int cookie)
 183 {
 184         return assert_clk;
 185 }
 186
 187 /* Toggle ChipSelect pin -- NO-OP */
 188 int fpga_cs_fn(int assert_clk, int flush, int cookie)
 189 {
 190         return assert_clk;
 191 }
 192
 193 Xilinx_Spartan3_Slave_Parallel_fns balloon3_fpga_fns = {
 194         fpga_pre_config_fn,
 195         fpga_pgm_fn,
 196         fpga_init_fn,
 197         NULL,   /* err */
 198         fpga_done_fn,
 199         fpga_clk_fn,
 200         fpga_cs_fn,
 201         fpga_wr_fn,
 202         NULL,   /* rdata */
 203         fpga_wdata_fn,
 204         fpga_busy_fn,
 205         NULL,   /* abort */
 206         fpga_post_config_fn,
 207 };
 208
 209 Xilinx_desc fpga = XILINX_XC3S1000_DESC(slave_parallel,
 210                         (void *)&balloon3_fpga_fns, 0);
 211
 212 /* Initialize the FPGA */
 213 void balloon3_init_fpga(void)
 214 {
 215         fpga_init();
 216         fpga_add(fpga_xilinx, &fpga);
 217 }
 218 #else
 219 void balloon3_init_fpga(void) {}
 220 #endif /* CONFIG_FPGA */