board/freescale/mx6qsabreauto/mx6qsabreauto.c

   1 /*
   2  * Copyright (C) 2012 Freescale Semiconductor, Inc.
   3  *
   4  * Author: Fabio Estevam <fabio.estevam@freescale.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/clock.h>
  12 #include <asm/arch/imx-regs.h>
  13 #include <asm/arch/iomux.h>
  14 #include <asm/arch/mx6-pins.h>
  15 #include <asm/errno.h>
  16 #include <asm/gpio.h>
  17 #include <asm/imx-common/iomux-v3.h>
  18 #include <asm/imx-common/mxc_i2c.h>
  19 #include <asm/imx-common/boot_mode.h>
  20 #include <asm/imx-common/spi.h>
  21 #include <mmc.h>
  22 #include <fsl_esdhc.h>
  23 #include <miiphy.h>
  24 #include <netdev.h>
  25 #include <asm/arch/sys_proto.h>
  26 #include <i2c.h>
  27
  28 DECLARE_GLOBAL_DATA_PTR;
  29
  30 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  31         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  32         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  33
  34 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  35         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  36         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  37
  38 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  39         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  40
  41 #define I2C_PAD_CTRL    (PAD_CTL_PUS_100K_UP |                  \
  42         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  43         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  44
  45 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  46
  47 int dram_init(void)
  48 {
  49         gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
  50
  51         return 0;
  52 }
  53
  54 static iomux_v3_cfg_t const uart4_pads[] = {
  55         MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  56         MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  57 };
  58
  59 static iomux_v3_cfg_t const enet_pads[] = {
  60         MX6_PAD_KEY_COL1__ENET_MDIO             | MUX_PAD_CTRL(ENET_PAD_CTRL),
  61         MX6_PAD_KEY_COL2__ENET_MDC              | MUX_PAD_CTRL(ENET_PAD_CTRL),
  62         MX6_PAD_RGMII_TXC__RGMII_TXC    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  63         MX6_PAD_RGMII_TD0__RGMII_TD0    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  64         MX6_PAD_RGMII_TD1__RGMII_TD1    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  65         MX6_PAD_RGMII_TD2__RGMII_TD2    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  66         MX6_PAD_RGMII_TD3__RGMII_TD3    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  67         MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
  68         MX6_PAD_ENET_REF_CLK__ENET_TX_CLK       | MUX_PAD_CTRL(ENET_PAD_CTRL),
  69         MX6_PAD_RGMII_RXC__RGMII_RXC    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  70         MX6_PAD_RGMII_RD0__RGMII_RD0    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  71         MX6_PAD_RGMII_RD1__RGMII_RD1    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  72         MX6_PAD_RGMII_RD2__RGMII_RD2    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  73         MX6_PAD_RGMII_RD3__RGMII_RD3    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  74         MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
  75 };
  76
  77 /* I2C2 PMIC, iPod, Tuner, Codec, Touch, HDMI EDID, MIPI CSI2 card */
  78 static struct i2c_pads_info i2c_pad_info1 = {
  79         .scl = {
  80                 .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC,
  81                 .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC,
  82                 .gp = IMX_GPIO_NR(2, 30)
  83         },
  84         .sda = {
  85                 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
  86                 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
  87                 .gp = IMX_GPIO_NR(4, 13)
  88         }
  89 };
  90
  91 /*
  92  * I2C3 MLB, Port Expanders (A, B, C), Video ADC, Light Sensor,
  93  * Compass Sensor, Accelerometer, Res Touch
  94  */
  95 static struct i2c_pads_info i2c_pad_info2 = {
  96         .scl = {
  97                 .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC,
  98                 .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC,
  99                 .gp = IMX_GPIO_NR(1, 3)
 100         },
 101         .sda = {
 102                 .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
 103                 .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
 104                 .gp = IMX_GPIO_NR(3, 18)
 105         }
 106 };
 107
 108 static iomux_v3_cfg_t const i2c3_pads[] = {
 109         MX6_PAD_EIM_A24__GPIO5_IO04             | MUX_PAD_CTRL(NO_PAD_CTRL),
 110 };
 111
 112 static iomux_v3_cfg_t const port_exp[] = {
 113         MX6_PAD_SD2_DAT0__GPIO1_IO15            | MUX_PAD_CTRL(NO_PAD_CTRL),
 114 };
 115
 116 static void setup_iomux_enet(void)
 117 {
 118         imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
 119 }
 120
 121 static iomux_v3_cfg_t const usdhc3_pads[] = {
 122         MX6_PAD_SD3_CLK__SD3_CLK        | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 123         MX6_PAD_SD3_CMD__SD3_CMD        | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 124         MX6_PAD_SD3_DAT0__SD3_DATA0     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 125         MX6_PAD_SD3_DAT1__SD3_DATA1     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 126         MX6_PAD_SD3_DAT2__SD3_DATA2     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 127         MX6_PAD_SD3_DAT3__SD3_DATA3     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 128         MX6_PAD_SD3_DAT4__SD3_DATA4     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 129         MX6_PAD_SD3_DAT5__SD3_DATA5     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 130         MX6_PAD_SD3_DAT6__SD3_DATA6     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 131         MX6_PAD_SD3_DAT7__SD3_DATA7     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 132         MX6_PAD_GPIO_18__SD3_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 133         MX6_PAD_NANDF_CS2__GPIO6_IO15   | MUX_PAD_CTRL(NO_PAD_CTRL),
 134 };
 135
 136 static void setup_iomux_uart(void)
 137 {
 138         imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
 139 }
 140
 141 #ifdef CONFIG_FSL_ESDHC
 142 static struct fsl_esdhc_cfg usdhc_cfg[1] = {
 143         {USDHC3_BASE_ADDR},
 144 };
 145
 146 int board_mmc_getcd(struct mmc *mmc)
 147 {
 148         gpio_direction_input(IMX_GPIO_NR(6, 15));
 149         return !gpio_get_value(IMX_GPIO_NR(6, 15));
 150 }
 151
 152 int board_mmc_init(bd_t *bis)
 153 {
 154         imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 155
 156         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 157         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 158 }
 159 #endif
 160
 161 int mx6_rgmii_rework(struct phy_device *phydev)
 162 {
 163         unsigned short val;
 164
 165         /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
 166         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
 167         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
 168         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
 169
 170         val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
 171         val &= 0xffe3;
 172         val |= 0x18;
 173         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
 174
 175         /* introduce tx clock delay */
 176         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
 177         val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
 178         val |= 0x0100;
 179         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
 180
 181         return 0;
 182 }
 183
 184 int board_phy_config(struct phy_device *phydev)
 185 {
 186         mx6_rgmii_rework(phydev);
 187
 188         if (phydev->drv->config)
 189                 phydev->drv->config(phydev);
 190
 191         return 0;
 192 }
 193
 194 int board_eth_init(bd_t *bis)
 195 {
 196         setup_iomux_enet();
 197
 198         return cpu_eth_init(bis);
 199 }
 200
 201 #define BOARD_REV_B  0x200
 202 #define BOARD_REV_A  0x100
 203
 204 static int mx6sabre_rev(void)
 205 {
 206         /*
 207          * Get Board ID information from OCOTP_GP1[15:8]
 208          * i.MX6Q ARD RevA: 0x01
 209          * i.MX6Q ARD RevB: 0x02
 210          */
 211         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
 212         struct fuse_bank *bank = &ocotp->bank[4];
 213         struct fuse_bank4_regs *fuse =
 214                         (struct fuse_bank4_regs *)bank->fuse_regs;
 215         int reg = readl(&fuse->gp1);
 216         int ret;
 217
 218         switch (reg >> 8 & 0x0F) {
 219         case 0x02:
 220                 ret = BOARD_REV_B;
 221                 break;
 222         case 0x01:
 223         default:
 224                 ret = BOARD_REV_A;
 225                 break;
 226         }
 227
 228         return ret;
 229 }
 230
 231 u32 get_board_rev(void)
 232 {
 233         int rev = mx6sabre_rev();
 234
 235         return (get_cpu_rev() & ~(0xF << 8)) | rev;
 236 }
 237
 238 int board_early_init_f(void)
 239 {
 240         setup_iomux_uart();
 241
 242         return 0;
 243 }
 244
 245 int board_init(void)
 246 {
 247         /* address of boot parameters */
 248         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 249
 250         /* I2C 2 and 3 setup - I2C 3 hw mux with EIM */
 251         setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 252         /* I2C 3 Steer */
 253         gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
 254         imx_iomux_v3_setup_multiple_pads(i2c3_pads, ARRAY_SIZE(i2c3_pads));
 255         setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
 256
 257         gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
 258         imx_iomux_v3_setup_multiple_pads(port_exp, ARRAY_SIZE(port_exp));
 259
 260         return 0;
 261 }
 262
 263 #ifdef CONFIG_MXC_SPI
 264 int board_spi_cs_gpio(unsigned bus, unsigned cs)
 265 {
 266         return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1;
 267 }
 268 #endif
 269
 270 #ifdef CONFIG_CMD_BMODE
 271 static const struct boot_mode board_boot_modes[] = {
 272         /* 4 bit bus width */
 273         {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 274         {NULL,   0},
 275 };
 276 #endif
 277
 278 int board_late_init(void)
 279 {
 280 #ifdef CONFIG_CMD_BMODE
 281         add_board_boot_modes(board_boot_modes);
 282 #endif
 283
 284         return 0;
 285 }
 286
 287 int checkboard(void)
 288 {
 289         int rev = mx6sabre_rev();
 290         char *revname;
 291
 292         switch (rev) {
 293         case BOARD_REV_B:
 294                 revname = "B";
 295                 break;
 296         case BOARD_REV_A:
 297         default:
 298                 revname = "A";
 299                 break;
 300         }
 301
 302         printf("Board: MX6Q-Sabreauto rev%s\n", revname);
 303
 304         return 0;
 305 }