2 * Copyright (C) 2014 Gateworks Corporation
3 * Author: Tim Harvey <tharvey@gateworks.com>
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/crm_regs.h>
11 #include <asm/arch/mx6-ddr.h>
12 #include <asm/arch/mx6-pins.h>
13 #include <asm/arch/sys_proto.h>
14 #include <asm/imx-common/boot_mode.h>
15 #include <asm/imx-common/iomux-v3.h>
16 #include <asm/imx-common/mxc_i2c.h>
17 #include <environment.h>
24 DECLARE_GLOBAL_DATA_PTR;
26 #define RTT_NOM_120OHM /* use 120ohm Rtt_nom vs 60ohm (lower power) */
27 #define GSC_EEPROM_DDR_SIZE 0x2B /* enum (512,1024,2048) MB */
28 #define GSC_EEPROM_DDR_WIDTH 0x2D /* enum (32,64) bit */
30 /* configure MX6Q/DUAL mmdc DDR io registers */
31 struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
32 /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
33 .dram_sdclk_0 = 0x00020030,
34 .dram_sdclk_1 = 0x00020030,
35 .dram_cas = 0x00020030,
36 .dram_ras = 0x00020030,
37 .dram_reset = 0x00020030,
38 /* SDCKE[0:1]: 100k pull-up */
39 .dram_sdcke0 = 0x00003000,
40 .dram_sdcke1 = 0x00003000,
41 /* SDBA2: pull-up disabled */
42 .dram_sdba2 = 0x00000000,
43 /* SDODT[0:1]: 100k pull-up, 40 ohm */
44 .dram_sdodt0 = 0x00003030,
45 .dram_sdodt1 = 0x00003030,
46 /* SDQS[0:7]: Differential input, 40 ohm */
47 .dram_sdqs0 = 0x00000030,
48 .dram_sdqs1 = 0x00000030,
49 .dram_sdqs2 = 0x00000030,
50 .dram_sdqs3 = 0x00000030,
51 .dram_sdqs4 = 0x00000030,
52 .dram_sdqs5 = 0x00000030,
53 .dram_sdqs6 = 0x00000030,
54 .dram_sdqs7 = 0x00000030,
56 /* DQM[0:7]: Differential input, 40 ohm */
57 .dram_dqm0 = 0x00020030,
58 .dram_dqm1 = 0x00020030,
59 .dram_dqm2 = 0x00020030,
60 .dram_dqm3 = 0x00020030,
61 .dram_dqm4 = 0x00020030,
62 .dram_dqm5 = 0x00020030,
63 .dram_dqm6 = 0x00020030,
64 .dram_dqm7 = 0x00020030,
67 /* configure MX6Q/DUAL mmdc GRP io registers */
68 struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
70 .grp_ddr_type = 0x000c0000,
71 .grp_ddrmode_ctl = 0x00020000,
72 /* disable DDR pullups */
73 .grp_ddrpke = 0x00000000,
74 /* ADDR[00:16], SDBA[0:1]: 40 ohm */
75 .grp_addds = 0x00000030,
76 /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
77 .grp_ctlds = 0x00000030,
78 /* DATA[00:63]: Differential input, 40 ohm */
79 .grp_ddrmode = 0x00020000,
80 .grp_b0ds = 0x00000030,
81 .grp_b1ds = 0x00000030,
82 .grp_b2ds = 0x00000030,
83 .grp_b3ds = 0x00000030,
84 .grp_b4ds = 0x00000030,
85 .grp_b5ds = 0x00000030,
86 .grp_b6ds = 0x00000030,
87 .grp_b7ds = 0x00000030,
90 /* configure MX6SOLO/DUALLITE mmdc DDR io registers */
91 struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
92 /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
93 .dram_sdclk_0 = 0x00020030,
94 .dram_sdclk_1 = 0x00020030,
95 .dram_cas = 0x00020030,
96 .dram_ras = 0x00020030,
97 .dram_reset = 0x00020030,
98 /* SDCKE[0:1]: 100k pull-up */
99 .dram_sdcke0 = 0x00003000,
100 .dram_sdcke1 = 0x00003000,
101 /* SDBA2: pull-up disabled */
102 .dram_sdba2 = 0x00000000,
103 /* SDODT[0:1]: 100k pull-up, 40 ohm */
104 .dram_sdodt0 = 0x00003030,
105 .dram_sdodt1 = 0x00003030,
106 /* SDQS[0:7]: Differential input, 40 ohm */
107 .dram_sdqs0 = 0x00000030,
108 .dram_sdqs1 = 0x00000030,
109 .dram_sdqs2 = 0x00000030,
110 .dram_sdqs3 = 0x00000030,
111 .dram_sdqs4 = 0x00000030,
112 .dram_sdqs5 = 0x00000030,
113 .dram_sdqs6 = 0x00000030,
114 .dram_sdqs7 = 0x00000030,
116 /* DQM[0:7]: Differential input, 40 ohm */
117 .dram_dqm0 = 0x00020030,
118 .dram_dqm1 = 0x00020030,
119 .dram_dqm2 = 0x00020030,
120 .dram_dqm3 = 0x00020030,
121 .dram_dqm4 = 0x00020030,
122 .dram_dqm5 = 0x00020030,
123 .dram_dqm6 = 0x00020030,
124 .dram_dqm7 = 0x00020030,
127 /* configure MX6SOLO/DUALLITE mmdc GRP io registers */
128 struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
130 .grp_ddr_type = 0x000c0000,
131 /* SDQS[0:7]: Differential input, 40 ohm */
132 .grp_ddrmode_ctl = 0x00020000,
133 /* disable DDR pullups */
134 .grp_ddrpke = 0x00000000,
135 /* ADDR[00:16], SDBA[0:1]: 40 ohm */
136 .grp_addds = 0x00000030,
137 /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
138 .grp_ctlds = 0x00000030,
139 /* DATA[00:63]: Differential input, 40 ohm */
140 .grp_ddrmode = 0x00020000,
141 .grp_b0ds = 0x00000030,
142 .grp_b1ds = 0x00000030,
143 .grp_b2ds = 0x00000030,
144 .grp_b3ds = 0x00000030,
145 .grp_b4ds = 0x00000030,
146 .grp_b5ds = 0x00000030,
147 .grp_b6ds = 0x00000030,
148 .grp_b7ds = 0x00000030,
151 /* MT41K64M16JT-125 (1Gb density) */
152 static struct mx6_ddr3_cfg mt41k64m16jt_125 = {
165 /* MT41K128M16JT-125 (2Gb density) */
166 static struct mx6_ddr3_cfg mt41k128m16jt_125 = {
179 /* MT41K256M16HA-125 (4Gb density) */
180 static struct mx6_ddr3_cfg mt41k256m16ha_125 = {
194 * calibration - these are the various CPU/DDR3 combinations we support
196 static struct mx6_mmdc_calibration mx6sdl_64x16_mmdc_calib = {
197 /* write leveling calibration determine */
198 .p0_mpwldectrl0 = 0x004C004E,
199 .p0_mpwldectrl1 = 0x00440044,
200 /* Read DQS Gating calibration */
201 .p0_mpdgctrl0 = 0x42440247,
202 .p0_mpdgctrl1 = 0x02310232,
203 /* Read Calibration: DQS delay relative to DQ read access */
204 .p0_mprddlctl = 0x45424746,
205 /* Write Calibration: DQ/DM delay relative to DQS write access */
206 .p0_mpwrdlctl = 0x33382C31,
209 static struct mx6_mmdc_calibration mx6dq_256x16_mmdc_calib = {
210 /* write leveling calibration determine */
211 .p0_mpwldectrl0 = 0x001B0016,
212 .p0_mpwldectrl1 = 0x000C000E,
213 /* Read DQS Gating calibration */
214 .p0_mpdgctrl0 = 0x4324033A,
215 .p0_mpdgctrl1 = 0x00000000,
216 /* Read Calibration: DQS delay relative to DQ read access */
217 .p0_mprddlctl = 0x40403438,
218 /* Write Calibration: DQ/DM delay relative to DQS write access */
219 .p0_mpwrdlctl = 0x40403D36,
222 static struct mx6_mmdc_calibration mx6sdl_256x16_mmdc_calib = {
223 /* write leveling calibration determine */
224 .p0_mpwldectrl0 = 0x00420043,
225 .p0_mpwldectrl1 = 0x0016001A,
226 /* Read DQS Gating calibration */
227 .p0_mpdgctrl0 = 0x4238023B,
228 .p0_mpdgctrl1 = 0x00000000,
229 /* Read Calibration: DQS delay relative to DQ read access */
230 .p0_mprddlctl = 0x40404849,
231 /* Write Calibration: DQ/DM delay relative to DQS write access */
232 .p0_mpwrdlctl = 0x40402E2F,
235 static struct mx6_mmdc_calibration mx6dq_128x32_mmdc_calib = {
236 /* write leveling calibration determine */
237 .p0_mpwldectrl0 = 0x00190017,
238 .p0_mpwldectrl1 = 0x00140026,
239 /* Read DQS Gating calibration */
240 .p0_mpdgctrl0 = 0x43380347,
241 .p0_mpdgctrl1 = 0x433C034D,
242 /* Read Calibration: DQS delay relative to DQ read access */
243 .p0_mprddlctl = 0x3C313539,
244 /* Write Calibration: DQ/DM delay relative to DQS write access */
245 .p0_mpwrdlctl = 0x36393C39,
248 static struct mx6_mmdc_calibration mx6sdl_128x32_mmdc_calib = {
249 /* write leveling calibration determine */
250 .p0_mpwldectrl0 = 0x003C003C,
251 .p0_mpwldectrl1 = 0x001F002A,
252 /* Read DQS Gating calibration */
253 .p0_mpdgctrl0 = 0x42410244,
254 .p0_mpdgctrl1 = 0x4234023A,
255 /* Read Calibration: DQS delay relative to DQ read access */
256 .p0_mprddlctl = 0x484A4C4B,
257 /* Write Calibration: DQ/DM delay relative to DQS write access */
258 .p0_mpwrdlctl = 0x33342B32,
261 static struct mx6_mmdc_calibration mx6dq_128x64_mmdc_calib = {
262 /* write leveling calibration determine */
263 .p0_mpwldectrl0 = 0x00190017,
264 .p0_mpwldectrl1 = 0x00140026,
265 .p1_mpwldectrl0 = 0x0021001C,
266 .p1_mpwldectrl1 = 0x0011001D,
267 /* Read DQS Gating calibration */
268 .p0_mpdgctrl0 = 0x43380347,
269 .p0_mpdgctrl1 = 0x433C034D,
270 .p1_mpdgctrl0 = 0x032C0324,
271 .p1_mpdgctrl1 = 0x03310232,
272 /* Read Calibration: DQS delay relative to DQ read access */
273 .p0_mprddlctl = 0x3C313539,
274 .p1_mprddlctl = 0x37343141,
275 /* Write Calibration: DQ/DM delay relative to DQS write access */
276 .p0_mpwrdlctl = 0x36393C39,
277 .p1_mpwrdlctl = 0x42344438,
280 static struct mx6_mmdc_calibration mx6sdl_128x64_mmdc_calib = {
281 /* write leveling calibration determine */
282 .p0_mpwldectrl0 = 0x003C003C,
283 .p0_mpwldectrl1 = 0x001F002A,
284 .p1_mpwldectrl0 = 0x00330038,
285 .p1_mpwldectrl1 = 0x0022003F,
286 /* Read DQS Gating calibration */
287 .p0_mpdgctrl0 = 0x42410244,
288 .p0_mpdgctrl1 = 0x4234023A,
289 .p1_mpdgctrl0 = 0x022D022D,
290 .p1_mpdgctrl1 = 0x021C0228,
291 /* Read Calibration: DQS delay relative to DQ read access */
292 .p0_mprddlctl = 0x484A4C4B,
293 .p1_mprddlctl = 0x4B4D4E4B,
294 /* Write Calibration: DQ/DM delay relative to DQS write access */
295 .p0_mpwrdlctl = 0x33342B32,
296 .p1_mpwrdlctl = 0x3933332B,
299 static struct mx6_mmdc_calibration mx6dq_256x32_mmdc_calib = {
300 /* write leveling calibration determine */
301 .p0_mpwldectrl0 = 0x001E001A,
302 .p0_mpwldectrl1 = 0x0026001F,
303 /* Read DQS Gating calibration */
304 .p0_mpdgctrl0 = 0x43370349,
305 .p0_mpdgctrl1 = 0x032D0327,
306 /* Read Calibration: DQS delay relative to DQ read access */
307 .p0_mprddlctl = 0x3D303639,
308 /* Write Calibration: DQ/DM delay relative to DQS write access */
309 .p0_mpwrdlctl = 0x32363934,
312 static struct mx6_mmdc_calibration mx6sdl_256x32_mmdc_calib = {
313 /* write leveling calibration determine */
314 .p0_mpwldectrl0 = 0X00480047,
315 .p0_mpwldectrl1 = 0X003D003F,
316 /* Read DQS Gating calibration */
317 .p0_mpdgctrl0 = 0X423E0241,
318 .p0_mpdgctrl1 = 0X022B022C,
319 /* Read Calibration: DQS delay relative to DQ read access */
320 .p0_mprddlctl = 0X49454A4A,
321 /* Write Calibration: DQ/DM delay relative to DQS write access */
322 .p0_mpwrdlctl = 0X2E372C32,
325 static struct mx6_mmdc_calibration mx6dq_256x64_mmdc_calib = {
326 /* write leveling calibration determine */
327 .p0_mpwldectrl0 = 0X00220021,
328 .p0_mpwldectrl1 = 0X00200030,
329 .p1_mpwldectrl0 = 0X002D0027,
330 .p1_mpwldectrl1 = 0X00150026,
331 /* Read DQS Gating calibration */
332 .p0_mpdgctrl0 = 0x43330342,
333 .p0_mpdgctrl1 = 0x0339034A,
334 .p1_mpdgctrl0 = 0x032F0325,
335 .p1_mpdgctrl1 = 0x032F022E,
336 /* Read Calibration: DQS delay relative to DQ read access */
337 .p0_mprddlctl = 0X3A2E3437,
338 .p1_mprddlctl = 0X35312F3F,
339 /* Write Calibration: DQ/DM delay relative to DQS write access */
340 .p0_mpwrdlctl = 0X33363B37,
341 .p1_mpwrdlctl = 0X40304239,
344 static void spl_dram_init(int width, int size_mb, int board_model)
346 struct mx6_ddr3_cfg *mem = NULL;
347 struct mx6_mmdc_calibration *calib = NULL;
348 struct mx6_ddr_sysinfo sysinfo = {
349 /* width of data bus:0=16,1=32,2=64 */
351 /* config for full 4GB range so that get_mem_size() works */
352 .cs_density = 32, /* 32Gb per CS */
353 /* single chip select */
356 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
357 #ifdef RTT_NOM_120OHM
358 .rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */
360 .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */
362 .walat = 1, /* Write additional latency */
363 .ralat = 5, /* Read additional latency */
364 .mif3_mode = 3, /* Command prediction working mode */
365 .bi_on = 1, /* Bank interleaving enabled */
366 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
367 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
368 .pd_fast_exit = 1, /* enable precharge power-down fast exit */
369 .ddr_type = DDR_TYPE_DDR3,
373 * MMDC Calibration requires the following data:
374 * mx6_mmdc_calibration - board-specific calibration (routing delays)
375 * these calibration values depend on board routing, SoC, and DDR
376 * mx6_ddr_sysinfo - board-specific memory architecture (width/cs/etc)
377 * mx6_ddr_cfg - chip specific timing/layout details
379 if (width == 16 && size_mb == 128) {
380 mem = &mt41k64m16jt_125;
381 if (is_cpu_type(MXC_CPU_MX6Q))
384 calib = &mx6sdl_64x16_mmdc_calib;
385 debug("1gB density\n");
386 } else if (width == 16 && size_mb == 256) {
387 /* 1x 2Gb density chip - same calib as 2x 2Gb */
388 mem = &mt41k128m16jt_125;
389 if (is_cpu_type(MXC_CPU_MX6Q))
390 calib = &mx6dq_128x32_mmdc_calib;
392 calib = &mx6sdl_128x32_mmdc_calib;
393 debug("2gB density\n");
394 } else if (width == 16 && size_mb == 512) {
395 mem = &mt41k256m16ha_125;
396 if (is_cpu_type(MXC_CPU_MX6Q))
397 calib = &mx6dq_256x16_mmdc_calib;
399 calib = &mx6sdl_256x16_mmdc_calib;
400 debug("4gB density\n");
401 } else if (width == 32 && size_mb == 256) {
402 /* Same calib as width==16, size==128 */
403 mem = &mt41k64m16jt_125;
404 if (is_cpu_type(MXC_CPU_MX6Q))
407 calib = &mx6sdl_64x16_mmdc_calib;
408 debug("1gB density\n");
409 } else if (width == 32 && size_mb == 512) {
410 mem = &mt41k128m16jt_125;
411 if (is_cpu_type(MXC_CPU_MX6Q))
412 calib = &mx6dq_128x32_mmdc_calib;
414 calib = &mx6sdl_128x32_mmdc_calib;
415 debug("2gB density\n");
416 } else if (width == 32 && size_mb == 1024) {
417 mem = &mt41k256m16ha_125;
418 if (is_cpu_type(MXC_CPU_MX6Q))
419 calib = &mx6dq_256x32_mmdc_calib;
421 calib = &mx6sdl_256x32_mmdc_calib;
422 debug("4gB density\n");
423 } else if (width == 64 && size_mb == 512) {
424 mem = &mt41k64m16jt_125;
425 debug("1gB density\n");
426 } else if (width == 64 && size_mb == 1024) {
427 mem = &mt41k128m16jt_125;
428 if (is_cpu_type(MXC_CPU_MX6Q))
429 calib = &mx6dq_128x64_mmdc_calib;
431 calib = &mx6sdl_128x64_mmdc_calib;
432 debug("2gB density\n");
433 } else if (width == 64 && size_mb == 2048) {
434 mem = &mt41k256m16ha_125;
435 if (is_cpu_type(MXC_CPU_MX6Q))
436 calib = &mx6dq_256x64_mmdc_calib;
437 debug("4gB density\n");
440 if (!(mem && calib)) {
441 puts("Error: Invalid Calibration/Board Configuration\n");
442 printf("MEM : %s\n", mem ? "OKAY" : "NULL");
443 printf("CALIB : %s\n", calib ? "OKAY" : "NULL");
444 printf("CPUTYPE: %s\n",
445 is_cpu_type(MXC_CPU_MX6Q) ? "IMX6Q" : "IMX6DL");
446 printf("SIZE_MB: %d\n", size_mb);
447 printf("WIDTH : %d\n", width);
451 if (is_cpu_type(MXC_CPU_MX6Q))
452 mx6dq_dram_iocfg(width, &mx6dq_ddr_ioregs,
455 mx6sdl_dram_iocfg(width, &mx6sdl_ddr_ioregs,
457 mx6_dram_cfg(&sysinfo, calib, mem);
460 static void ccgr_init(void)
462 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
464 writel(0x00C03F3F, &ccm->CCGR0);
465 writel(0x0030FC03, &ccm->CCGR1);
466 writel(0x0FFFC000, &ccm->CCGR2);
467 writel(0x3FF00000, &ccm->CCGR3);
468 writel(0xFFFFF300, &ccm->CCGR4); /* enable NAND/GPMI/BCH clks */
469 writel(0x0F0000C3, &ccm->CCGR5);
470 writel(0x000003FF, &ccm->CCGR6);
473 static void gpr_init(void)
475 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
477 /* enable AXI cache for VDOA/VPU/IPU */
478 writel(0xF00000CF, &iomux->gpr[4]);
479 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
480 writel(0x007F007F, &iomux->gpr[6]);
481 writel(0x007F007F, &iomux->gpr[7]);
485 * called from C runtime startup code (arch/arm/lib/crt0.S:_main)
486 * - we have a stack and a place to store GD, both in SRAM
487 * - no variable global data is available
489 void board_init_f(ulong dummy)
491 struct ventana_board_info ventana_info;
494 /* setup clock gating */
497 /* setup AIPS and disable watchdog */
503 /* iomux and setup of i2c */
510 /* UART clocks enabled and gd valid - init serial console */
511 preloader_console_init();
513 /* read/validate EEPROM info to determine board model and SDRAM cfg */
514 board_model = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
516 /* configure model-specific gpio */
517 setup_iomux_gpio(board_model, &ventana_info);
519 /* provide some some default: 32bit 128MB */
520 if (GW_UNKNOWN == board_model)
523 /* configure MMDC for SDRAM width/size and per-model calibration */
524 spl_dram_init(8 << ventana_info.sdram_width,
525 16 << ventana_info.sdram_size,
529 memset(__bss_start, 0, __bss_end - __bss_start);
532 /* called from board_init_r after gd setup if CONFIG_SPL_BOARD_INIT defined */
533 /* its our chance to print info about boot device */
534 void spl_board_init(void)
536 /* determine boot device from SRC_SBMR1 (BOOT_CFG[4:1]) or SRC_GPR9 */
537 u32 boot_device = spl_boot_device();
539 switch (boot_device) {
540 case BOOT_DEVICE_MMC1:
541 puts("Booting from MMC\n");
543 case BOOT_DEVICE_NAND:
544 puts("Booting from NAND\n");
546 case BOOT_DEVICE_SATA:
547 puts("Booting from SATA\n");
550 puts("Unknown boot device\n");
557 #ifdef CONFIG_SPL_OS_BOOT
558 /* return 1 if we wish to boot to uboot vs os (falcon mode) */
559 int spl_start_uboot(void)
561 unsigned char ret = 1;
563 debug("%s\n", __func__);
564 #ifdef CONFIG_SPL_ENV_SUPPORT
567 debug("boot_os=%s\n", getenv("boot_os"));
568 if (getenv_yesno("boot_os") == 1)
571 /* use i2c-0:0x50:0x00 for falcon boot mode (0=linux, else uboot) */
573 gsc_i2c_read(0x50, 0x0, 1, &ret, 1);
576 gsc_boot_wd_disable();
578 debug("%s booting %s\n", __func__, ret ? "uboot" : "linux");