2 #include <configs/tx51.h>
3 #include <asm/arch/imx-regs.h>
5 #define DCDGEN(type, addr, data) .long type, addr, data
7 #define SDRAM_CLK CONFIG_SYS_SDRAM_CLK
9 #ifdef PHYS_SDRAM_2_SIZE
10 #define SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE)
12 #define SDRAM_SIZE PHYS_SDRAM_1_SIZE
15 #define REG_ESDCTL0 0x00
16 #define REG_ESDCFG0 0x04
17 #define REG_ESDCTL1 0x08
18 #define REG_ESDCFG1 0x0c
19 #define REG_ESDMISC 0x10
20 #define REG_ESDSCR 0x14
21 #define REG_ESDGPR 0x34
23 #define REG_CCGR0 0x68
24 #define REG_CCGR1 0x6c
25 #define REG_CCGR2 0x70
26 #define REG_CCGR3 0x74
27 #define REG_CCGR4 0x78
28 #define REG_CCGR5 0x7c
29 #define REG_CCGR6 0x80
30 #define REG_CMEOR 0x84
32 /* SDRAM timing setup */
36 #if SDRAM_SIZE <= SZ_128M
37 #define RA_BITS (13 - 11) /* row addr bits - 11 */
39 #define RA_BITS (14 - 11) /* row addr bits - 11 */
42 #define CA_BITS (10 - 8) /* 0-2: col addr bits - 8 3: rsrvd */
43 #define DSIZ 2 /* 0: D[31..16] 1: D[15..D0] 2: D[31..0] 3: rsrvd */
44 #define SREFR 3 /* 0: disabled 1-5: 2^n rows/clock *: rsrvd */
45 #define SRT 0 /* 0: disabled *: 1: self refr. ... */
46 #define PWDT 0 /* 0: disabled 1: precharge pwdn
47 2: pwdn after 64 clocks 3: pwdn after 128 clocks */
48 #define ESDCTL_VAL (0x80000000 | (SREFR << 28) | (RA_BITS << 24) | (CA_BITS << 20) | \
49 (DSIZ << 16) | (SRT << 14) | (PWDT << 12))
51 #define NS_TO_CK(ns) (((ns) * SDRAM_CLK + 999) / 1000)
53 .macro CK_VAL, name, clks, offs
57 .set \name, \clks - \offs
61 .macro NS_VAL, name, ns, offs
65 CK_VAL \name, NS_TO_CK(\ns), \offs
71 NS_VAL tRFC, 125, 10 /* clks - 10 (0..15) */
72 NS_VAL tXSR, 138, 25 /* clks - 25 (0..15) */
73 NS_VAL tXP, 25, 1 /* clks - 1 (0..7) */
74 CK_VAL tWTR, 1, 1 /* clks - 1 (0..1) */
75 NS_VAL tRP, 18, 2 /* clks - 2 (0..3) */
76 CK_VAL tMRD, 2, 1 /* clks - 1 (0..3) */
77 NS_VAL tWR, 15, 2 /* clks - 2 (0..1) */
78 NS_VAL tRAS, 42, 1 /* clks - 1 (0..15) */
79 NS_VAL tRRD, 12, 1 /* clks - 1 (0..3) */
80 NS_VAL tRCD, 18, 1 /* clks - 1 (0..7) */
81 NS_VAL tRC, 60, 1 /* 0: 20 *: clks - 1 (0..15) */
83 /* MT46H64M32LF-5 or -6 */
84 NS_VAL tRFC, 72, 10 /* clks - 10 (0..15) */
85 NS_VAL tXSR, 113, 25 /* clks - 25 (0..15) */
86 CK_VAL tXP, 2, 1 /* clks - 1 (0..7) */
87 CK_VAL tWTR, 2, 1 /* clks - 1 (0..1) */
88 NS_VAL tRP, 18, 2 /* clks - 2 (0..3) */
89 CK_VAL tMRD, 2, 1 /* clks - 1 (0..3) */
90 NS_VAL tWR, 15, 2 /* clks - 2 (0..1) */
91 NS_VAL tRAS, 42, 1 /* clks - 1 (0..15) */
92 NS_VAL tRRD, 12, 1 /* clks - 1 (0..3) */
93 NS_VAL tRCD, 18, 1 /* clks - 1 (0..7) */
94 NS_VAL tRC, 60, 1 /* 0: 20 *: clks - 1 (0..15) */
97 #define ESDCFG_VAL ((tRFC << 28) | (tXSR << 24) | (tXP << 21) | \
98 (tWTR << 20) | (tRP << 18) | (tMRD << 16) | \
99 (tRAS << 12) | (tRRD << 10) | (tWR << 7) | \
100 (tRCD << 4) | (tRC << 0))
102 #define ESDMISC_RALAT(n) (((n) & 0x3) << 7)
103 #define ESDMISC_DDR2_EN(n) (((n) & 0x1) << 4)
104 #define ESDMISC_DDR_EN(n) (((n) & 0x1) << 3)
105 #define ESDMISC_AP(n) (((n) & 0xf) << 16)
106 #define ESDMISC_VAL (ESDMISC_AP(10) | ESDMISC_RALAT(RALAT) | \
107 (LHD << 5) | ESDMISC_DDR2_EN(0) | ESDMISC_DDR_EN(0))
114 .long 0 // 0x97f40000 - 0x1000
118 .long 0 // hab_super_root_key
122 .long CONFIG_SYS_TEXT_BASE
124 .long 0xB17219E9 // Fixed. can't change.
126 .long dcd_end - dcd_start
128 DCDGEN(4, ESDCTL_BASE_ADDR + REG_ESDCTL0, 0x80000000)
129 DCDGEN(4, ESDCTL_BASE_ADDR + REG_ESDSCR, 0x04008008)
130 DCDGEN(4, ESDCTL_BASE_ADDR + REG_ESDSCR, 0x00008010)
131 DCDGEN(4, ESDCTL_BASE_ADDR + REG_ESDSCR, 0x00008010)
132 DCDGEN(4, ESDCTL_BASE_ADDR + REG_ESDSCR, 0x00338018)
133 DCDGEN(4, ESDCTL_BASE_ADDR + REG_ESDCTL0, ESDCTL_VAL)
134 DCDGEN(4, ESDCTL_BASE_ADDR + REG_ESDCFG0, ESDCFG_VAL)
135 #ifdef RAM_BANK1_SIZE
136 DCDGEN(4, ESDCTL_BASE_ADDR + REG_ESDCTL1, ESDCTL_VAL)
137 DCDGEN(4, ESDCTL_BASE_ADDR + REG_ESDCFG1, ESDCFG_VAL)
139 DCDGEN(4, ESDCTL_BASE_ADDR + REG_ESDGPR, 0x00020000)
140 DCDGEN(4, ESDCTL_BASE_ADDR + REG_ESDMISC, ESDMISC_VAL)
141 DCDGEN(4, ESDCTL_BASE_ADDR + REG_ESDSCR, 0x00000000)
143 DCDGEN(4, IOMUXC_BASE_ADDR + 0x508, 0x000020e0) @ EIM_SDBA2
144 DCDGEN(4, IOMUXC_BASE_ADDR + 0x50c, 0x000020e1) @ EIM_SDODT1
145 DCDGEN(4, IOMUXC_BASE_ADDR + 0x510, 0x000020e1) @ EIM_SDODT0
146 DCDGEN(4, IOMUXC_BASE_ADDR + 0x820, 0x00000040) @ (Bit6 PUE) GRP_DDRPKS
147 DCDGEN(4, IOMUXC_BASE_ADDR + 0x82c, 0x00000000) @ (Bit[1..2] DSE D[24..31]) GRP_DRAM_B4 DFT: 0x4
148 DCDGEN(4, IOMUXC_BASE_ADDR + 0x830, 0x00000000) @ (Bit9 DDR_INPUT A[0..14] CAS CS[0..1] RAS SDCKE[0..1]
149 @ SDWE SDBA[0..1]) GRP_INDDR
150 DCDGEN(4, IOMUXC_BASE_ADDR + 0x838, 0x00000080) @ (Bit7 PKE D[0..31]) GRP_PKEDDR
151 DCDGEN(4, IOMUXC_BASE_ADDR + 0x83c, 0x00000000) @ (Bit[1..2] DSE A[0..7]) GRP_DDR_A0 DFT: 0x4
152 DCDGEN(4, IOMUXC_BASE_ADDR + 0x848, 0x00000000) @ (Bit[1..2] DSE A[8..14] SDBA[0..2]) GRP_DDR_A1
153 DCDGEN(4, IOMUXC_BASE_ADDR + 0x84c, 0x00000020) @ (Bit[4..5] PUS A[0..14] CAS RAS SDBA[0..1]) GRP_DDRAPUS
154 DCDGEN(4, IOMUXC_BASE_ADDR + 0x85c, 0x00000000) @ (Bit8 HYS D[0..7]) GRP_HYSDDR0
155 DCDGEN(4, IOMUXC_BASE_ADDR + 0x864, 0x00000000) @ (Bit8 HYS D[8..15]) GRP_HYSDDR1
156 DCDGEN(4, IOMUXC_BASE_ADDR + 0x86c, 0x00000000) @ (Bit8 HYS D[16..23]) GRP_HYSDDR2
157 DCDGEN(4, IOMUXC_BASE_ADDR + 0x870, 0x00002000) @ (Bit13 A[0..14] CAS CS[0..1] D[0..31] DQM[0..3] RAS
158 @ SDCKE[0..1] SDCLK SDQS[0..3] SDWE SDBA[0..2]
159 @ SDODT[0..1]) GRP_HVDDR
160 DCDGEN(4, IOMUXC_BASE_ADDR + 0x874, 0x00000000) @ (Bit8 HYS D[24..31]) GRP_HYSDDR3
161 DCDGEN(4, IOMUXC_BASE_ADDR + 0x878, 0x00000001) @ (Bit0 SRE D[0..7]) GRP_SR_B0
162 DCDGEN(4, IOMUXC_BASE_ADDR + 0x87c, 0x00000040) @ (Bit6 PUE A[0..14] CAS RAS SDBA[0..1]) GRP_DDRAPKS
163 DCDGEN(4, IOMUXC_BASE_ADDR + 0x880, 0x00000001) @ (Bit0 SRE D[8..15]) GRP_SR_B1
164 DCDGEN(4, IOMUXC_BASE_ADDR + 0x884, 0x00000020) @ (Bit[4..5] PUS D[0..31]) GRP_DDRPUS
165 DCDGEN(4, IOMUXC_BASE_ADDR + 0x88c, 0x00000001) @ (Bit0 SRE D[16..23]) GRP_SR_B2
166 DCDGEN(4, IOMUXC_BASE_ADDR + 0x890, 0x00000080) @ (Bit7 PKE A[0..14] CAS RAS SDBA[0..1]) GRP_PKEADDR
167 DCDGEN(4, IOMUXC_BASE_ADDR + 0x89c, 0x00000001) @ (Bit0 SRE D[24..31]) GRP_SR_B4
168 DCDGEN(4, IOMUXC_BASE_ADDR + 0x8a0, 0x00000000) @ (Bit9 DDR_INPUT D[0..31] DQM[0..3]) GRP_INMODE1
169 DCDGEN(4, IOMUXC_BASE_ADDR + 0x8a4, 0x00000000) @ (Bit[1..2] DSE D[0..7]) GRP_DRAM_B0 DFT: 0x4
170 DCDGEN(4, IOMUXC_BASE_ADDR + 0x8ac, 0x00000000) @ (Bit[1..2] DSE D[8..15]) GRP_DRAM_B1 DFT: 0x4
171 DCDGEN(4, IOMUXC_BASE_ADDR + 0x8b0, 0x00000001) @ (Bit0 SRE A[0..7]) GRP_SR_A0
172 DCDGEN(4, IOMUXC_BASE_ADDR + 0x8b8, 0x00000000) @ (Bit[1..2] DSE D[16..23]) GRP_DRAM_B2 DFT: 0x4
173 DCDGEN(4, IOMUXC_BASE_ADDR + 0x8bc, 0x00000001) @ (Bit0 SRE A[8..14] SDBA[0..2]) GRP_SR_A1
175 DCDGEN(4, IOMUXC_BASE_ADDR + 0x4e4, 0x2000) @ NANDF_WE_B
176 DCDGEN(4, IOMUXC_BASE_ADDR + 0x4e8, 0x2000) @ NANDF_RE_B
177 DCDGEN(4, IOMUXC_BASE_ADDR + 0x4ec, 0x2000) @ NANDF_ALE
178 DCDGEN(4, IOMUXC_BASE_ADDR + 0x4f0, 0x2000) @ NANDF_CLE
179 DCDGEN(4, IOMUXC_BASE_ADDR + 0x4f4, 0x2000) @ NANDF_WP_B
180 DCDGEN(4, IOMUXC_BASE_ADDR + 0x4f8, 0x2000) @ NANDF_RB0
182 DCDGEN(4, IOMUXC_BASE_ADDR + 0x518, 0x0084) @ NANDF_CS0
184 DCDGEN(4, IOMUXC_BASE_ADDR + 0x538, 0x20e0) @ NANDF_RDY_INT
186 DCDGEN(4, IOMUXC_BASE_ADDR + 0x55c, 0x20a4) @ NANDF_D7
187 DCDGEN(4, IOMUXC_BASE_ADDR + 0x560, 0x20a4) @ NANDF_D6
188 DCDGEN(4, IOMUXC_BASE_ADDR + 0x564, 0x20a4) @ NANDF_D5
189 DCDGEN(4, IOMUXC_BASE_ADDR + 0x568, 0x20a4) @ NANDF_D4
190 DCDGEN(4, IOMUXC_BASE_ADDR + 0x56c, 0x20a4) @ NANDF_D3
191 DCDGEN(4, IOMUXC_BASE_ADDR + 0x570, 0x20a4) @ NANDF_D2
192 DCDGEN(4, IOMUXC_BASE_ADDR + 0x574, 0x20a4) @ NANDF_D1
193 DCDGEN(4, IOMUXC_BASE_ADDR + 0x578, 0x20a4) @ NANDF_D0
195 .ifgt dcd_end - dcd_start - 60 * 12
196 .error "DCD too large!"
199 .long CONFIG_U_BOOT_IMG_SIZE