2 * Copyright (C) 2011 Lothar Waßmann <LW@KARO-electronics.de>
3 * based on: board/freesclae/mx28_evk.c (C) 2010 Freescale Semiconductor, Inc.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <fsl_esdhc.h>
29 #include <fdt_support.h>
30 #include <asm/string.h>
33 #include <asm/arch/sys_proto.h>
34 #include <asm/arch/iomux-mx51.h>
35 #include <asm/arch/clock.h>
36 #include <asm/arch/imx-regs.h>
37 #include <asm/arch/crm_regs.h>
41 #define IMX_GPIO_NR(p, o) ((((p) - 1) << 5) | (o))
43 #define TX51_FEC_RESET_GPIO IMX_GPIO_NR(2, 14)
44 #define TX51_FEC_POWER_GPIO IMX_GPIO_NR(1, 3)
45 #define TX51_LED_GPIO IMX_GPIO_NR(4, 10)
47 DECLARE_GLOBAL_DATA_PTR;
51 GPIOF_OUTPUT_INIT_LOW,
52 GPIOF_OUTPUT_INIT_HIGH,
57 enum gpio_flags flags;
61 static int gpio_request_array(const struct gpio *gp, int count)
66 for (i = 0; i < count; i++) {
67 ret = gpio_request(gp[i].gpio, gp[i].label);
71 if (gp[i].flags == GPIOF_INPUT)
72 gpio_direction_input(gp[i].gpio);
73 else if (gp[i].flags == GPIOF_OUTPUT_INIT_LOW)
74 gpio_direction_output(gp[i].gpio, 0);
75 else if (gp[i].flags == GPIOF_OUTPUT_INIT_HIGH)
76 gpio_direction_output(gp[i].gpio, 1);
82 gpio_free(gp[i].gpio);
87 #define IOMUX_SION IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
89 static iomux_v3_cfg_t tx51_pads[] = {
90 MX51_PAD_GPIO1_0__GPIO1_0,
91 MX51_PAD_GPIO1_1__GPIO1_1,
92 MX51_PAD_GPIO1_4__GPIO1_4, /* USB PHY reset */
93 MX51_PAD_GPIO1_6__GPIO1_6, /* USBOTG OC */
94 MX51_PAD_GPIO1_7__GPIO1_7, /* USB PHY clock enable */
95 MX51_PAD_GPIO1_8__GPIO1_8, /* USBH1 VBUS enable */
96 MX51_PAD_GPIO1_9__GPIO1_9, /* USBH1 OC */
99 MX51_PAD_UART1_RXD__UART1_RXD,
100 MX51_PAD_UART1_TXD__UART1_TXD,
101 MX51_PAD_UART1_RTS__UART1_RTS,
102 MX51_PAD_UART1_CTS__UART1_CTS,
104 MX51_PAD_UART2_RXD__UART2_RXD,
105 MX51_PAD_UART2_TXD__UART2_TXD,
106 MX51_PAD_EIM_D26__UART2_RTS,
107 MX51_PAD_EIM_D25__UART2_CTS,
109 MX51_PAD_UART3_RXD__UART3_RXD,
110 MX51_PAD_UART3_TXD__UART3_TXD,
111 MX51_PAD_EIM_D18__UART3_RTS,
112 MX51_PAD_EIM_D17__UART3_CTS,
115 MX51_PAD_I2C1_DAT__GPIO4_17 | IOMUX_SION,
116 MX51_PAD_I2C1_CLK__GPIO4_16 | IOMUX_SION,
119 static const struct gpio tx51_gpios[] = {
120 { IMX_GPIO_NR(1, 0), GPIOF_OUTPUT_INIT_LOW, "unused", },
121 { IMX_GPIO_NR(1, 1), GPIOF_OUTPUT_INIT_LOW, "unused", },
122 { IMX_GPIO_NR(1, 4), GPIOF_OUTPUT_INIT_LOW, "ULPI PHY clk enable", },
123 { IMX_GPIO_NR(1, 6), GPIOF_INPUT, "USBOTG OC", },
124 { IMX_GPIO_NR(1, 7), GPIOF_OUTPUT_INIT_LOW, "ULPI PHY reset", },
125 { IMX_GPIO_NR(1, 8), GPIOF_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
126 { IMX_GPIO_NR(1, 9), GPIOF_INPUT, "USBH1 OC", },
127 { IMX_GPIO_NR(4, 17), GPIOF_INPUT, "I2C1 SDA", },
128 { IMX_GPIO_NR(4, 16), GPIOF_INPUT, "I2C1 SCL", },
131 static void tx51_module_init(void)
133 mxc_iomux_v3_setup_multiple_pads(tx51_pads, ARRAY_SIZE(tx51_pads));
134 gpio_request_array(tx51_gpios, ARRAY_SIZE(tx51_gpios));
140 static void print_reset_cause(void)
143 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
144 void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
147 printf("Reset cause: ");
149 srsr = readl(&src_regs->srsr);
150 if (srsr & 0x00001) {
151 printf("%sPOR", dlm);
154 if (srsr & 0x00004) {
155 printf("%sCSU", dlm);
158 if (srsr & 0x00008) {
159 printf("%sIPP USER", dlm);
162 if (srsr & 0x00010) {
163 u32 wrsr = readw(wdt_base + 4);
164 if (wrsr & (1 << 0)) {
165 printf("%sSOFT", dlm);
168 if (wrsr & (1 << 1)) {
169 printf("%sWDOG", dlm);
173 if (srsr & 0x00020) {
174 printf("%sJTAG HIGH-Z", dlm);
177 if (srsr & 0x00040) {
178 printf("%sJTAG SW", dlm);
181 if (srsr & 0x10000) {
182 printf("%sWARM BOOT", dlm);
191 static void print_cpuinfo(void)
195 cpurev = get_cpu_rev();
197 printf("CPU: Freescale i.MX51 rev%d.%d at %d MHz\n",
198 (cpurev & 0x000F0) >> 4,
199 (cpurev & 0x0000F) >> 0,
200 mxc_get_clock(MXC_ARM_CLK) / 1000000);
205 #ifdef CONFIG_BOARD_EARLY_INIT_F
206 int board_early_init_f(void)
208 struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)MXC_CCM_BASE;
210 writel(0xffccfffc, &ccm_regs->CCGR0);
211 writel(0x003fffff, &ccm_regs->CCGR1);
212 writel(0x030c003c, &ccm_regs->CCGR2);
213 writel(0x000000ff, &ccm_regs->CCGR3);
214 writel(0x00000000, &ccm_regs->CCGR4);
215 writel(0x003fc003, &ccm_regs->CCGR5);
216 writel(0x00000000, &ccm_regs->CCGR6);
217 writel(0x00000000, &ccm_regs->cmeor);
222 void coloured_LED_init(void)
225 gpio_set_value(TX51_LED_GPIO, 0);
230 /* Address of boot parameters */
231 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
239 /* dram_init must store complete ramsize in gd->ram_size */
240 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
243 ret = mxc_set_clock(CONFIG_SYS_MX5_HCLK,
244 CONFIG_SYS_SDRAM_CLK, MXC_DDR_CLK);
246 printf("%s: Failed to set DDR clock to %uMHz: %d\n", __func__,
247 CONFIG_SYS_SDRAM_CLK, ret);
249 debug("%s: DDR clock set to %u.%03uMHz (desig.: %u.000MHz)\n",
250 __func__, mxc_get_clock(MXC_DDR_CLK) / 1000000,
251 mxc_get_clock(MXC_DDR_CLK) / 1000 % 1000,
252 CONFIG_SYS_SDRAM_CLK);
256 void dram_init_banksize(void)
258 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
259 gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
261 #if CONFIG_NR_DRAM_BANKS > 1
262 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
263 gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
268 #ifdef CONFIG_CMD_MMC
269 int board_mmc_getcd(struct mmc *mmc)
271 struct fsl_esdhc_cfg *cfg = mmc->priv;
273 if (cfg->cd_gpio < 0)
276 return !gpio_get_value(cfg->cd_gpio);
279 static struct fsl_esdhc_cfg esdhc_cfg[] = {
281 .esdhc_base = (void __iomem *)MMC_SDHC1_BASE_ADDR,
283 .cd_gpio = IMX_GPIO_NR(3, 8),
287 .esdhc_base = (void __iomem *)MMC_SDHC2_BASE_ADDR,
289 .cd_gpio = IMX_GPIO_NR(3, 6),
294 static const iomux_v3_cfg_t mmc0_pads[] = {
295 MX51_PAD_SD1_CMD__SD1_CMD,
296 MX51_PAD_SD1_CLK__SD1_CLK,
297 MX51_PAD_SD1_DATA0__SD1_DATA0,
298 MX51_PAD_SD1_DATA1__SD1_DATA1,
299 MX51_PAD_SD1_DATA2__SD1_DATA2,
300 MX51_PAD_SD1_DATA3__SD1_DATA3,
302 MX51_PAD_DISPB2_SER_RS__GPIO3_8 |
303 MUX_PAD_CTRL(PAD_CTL_PUE | PAD_CTL_PKE),
306 static const iomux_v3_cfg_t mmc1_pads[] = {
307 MX51_PAD_SD2_CMD__SD2_CMD,
308 MX51_PAD_SD2_CLK__SD2_CLK,
309 MX51_PAD_SD2_DATA0__SD2_DATA0,
310 MX51_PAD_SD2_DATA1__SD2_DATA1,
311 MX51_PAD_SD2_DATA2__SD2_DATA2,
312 MX51_PAD_SD2_DATA3__SD2_DATA3,
314 MX51_PAD_DISPB2_SER_DIO__GPIO3_6 |
315 MUX_PAD_CTRL(PAD_CTL_PUE | PAD_CTL_PKE),
319 const iomux_v3_cfg_t *pads;
321 } mmc_pad_config[] = {
322 { mmc0_pads, ARRAY_SIZE(mmc0_pads), },
323 { mmc1_pads, ARRAY_SIZE(mmc1_pads), },
326 int board_mmc_init(bd_t *bis)
330 for (i = 0; i < ARRAY_SIZE(esdhc_cfg); i++) {
333 if (i >= CONFIG_SYS_FSL_ESDHC_NUM)
335 mxc_iomux_v3_setup_multiple_pads(mmc_pad_config[i].pads,
336 mmc_pad_config[i].count);
337 fsl_esdhc_initialize(bis, &esdhc_cfg[i]);
338 mmc = find_mmc_device(i);
341 if (board_mmc_getcd(mmc) > 0)
346 #endif /* CONFIG_CMD_MMC */
348 #ifdef CONFIG_FEC_MXC
354 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
357 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
358 struct fuse_bank *bank = &iim->bank[1];
359 struct fuse_bank1_regs *fuse = (struct fuse_bank1_regs *)bank->fuse_regs;
364 for (i = 0; i < ETH_ALEN; i++)
365 mac[ETH_ALEN - i - 1] = readl(&fuse->mac_addr[i]);
368 #define FEC_PAD_CTL (PAD_CTL_DVS | PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \
370 #define FEC_PAD_CTL2 (PAD_CTL_DVS | PAD_CTL_PKE | PAD_CTL_PUE | \
371 PAD_CTL_PUS_100K_UP | PAD_CTL_SRE_FAST)
372 #define GPIO_PAD_CTL (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
374 static iomux_v3_cfg_t tx51_fec_gpio_pads[] = {
375 NEW_PAD_CTRL(MX51_PAD_NANDF_CS3__GPIO3_19, GPIO_PAD_CTL) | IOMUX_SION,
376 NEW_PAD_CTRL(MX51_PAD_EIM_EB2__GPIO2_22, GPIO_PAD_CTL) | IOMUX_SION,
377 NEW_PAD_CTRL(MX51_PAD_NANDF_RB3__GPIO3_11, GPIO_PAD_CTL) | IOMUX_SION,
378 NEW_PAD_CTRL(MX51_PAD_NANDF_D11__GPIO3_29, GPIO_PAD_CTL) | IOMUX_SION,
379 NEW_PAD_CTRL(MX51_PAD_NANDF_D9__GPIO3_31, GPIO_PAD_CTL) | IOMUX_SION, /* RXD0/Mode0 */
380 NEW_PAD_CTRL(MX51_PAD_EIM_EB3__GPIO2_23, GPIO_PAD_CTL) | IOMUX_SION, /* RXD1/Mode1 */
381 NEW_PAD_CTRL(MX51_PAD_EIM_CS2__GPIO2_27, GPIO_PAD_CTL) | IOMUX_SION, /* RXD2/Mode2 */
382 NEW_PAD_CTRL(MX51_PAD_EIM_CS3__GPIO2_28, GPIO_PAD_CTL) | IOMUX_SION, /* RXD3/nINTSEL */
383 NEW_PAD_CTRL(MX51_PAD_EIM_CS4__GPIO2_29, GPIO_PAD_CTL) | IOMUX_SION,
384 NEW_PAD_CTRL(MX51_PAD_NANDF_RDY_INT__GPIO3_24, GPIO_PAD_CTL) | IOMUX_SION,
385 NEW_PAD_CTRL(MX51_PAD_NANDF_CS7__GPIO3_23, GPIO_PAD_CTL) | IOMUX_SION,
386 NEW_PAD_CTRL(MX51_PAD_NANDF_D8__GPIO4_0, GPIO_PAD_CTL) | IOMUX_SION,
387 NEW_PAD_CTRL(MX51_PAD_NANDF_CS4__GPIO3_20, GPIO_PAD_CTL) | IOMUX_SION,
388 NEW_PAD_CTRL(MX51_PAD_NANDF_CS5__GPIO3_21, GPIO_PAD_CTL) | IOMUX_SION,
389 NEW_PAD_CTRL(MX51_PAD_NANDF_CS6__GPIO3_22, GPIO_PAD_CTL) | IOMUX_SION,
390 NEW_PAD_CTRL(MX51_PAD_NANDF_RB2__GPIO3_10, GPIO_PAD_CTL) | IOMUX_SION,
391 NEW_PAD_CTRL(MX51_PAD_EIM_CS5__GPIO2_30, GPIO_PAD_CTL) | IOMUX_SION,
392 NEW_PAD_CTRL(MX51_PAD_NANDF_CS2__GPIO3_18, GPIO_PAD_CTL) | IOMUX_SION, /* PHY INT */
393 NEW_PAD_CTRL(MX51_PAD_EIM_A20__GPIO2_14, GPIO_PAD_CTL) | IOMUX_SION, /* PHY RESET */
394 NEW_PAD_CTRL(MX51_PAD_GPIO1_3__GPIO1_3, GPIO_PAD_CTL) | IOMUX_SION, /* PHY POWER */
397 static iomux_v3_cfg_t tx51_fec_pads[] = {
398 NEW_PAD_CTRL(MX51_PAD_NANDF_CS3__FEC_MDC, FEC_PAD_CTL),
399 NEW_PAD_CTRL(MX51_PAD_EIM_EB2__FEC_MDIO, FEC_PAD_CTL),
400 NEW_PAD_CTRL(MX51_PAD_NANDF_RB3__FEC_RX_CLK, FEC_PAD_CTL2),
401 NEW_PAD_CTRL(MX51_PAD_NANDF_D11__FEC_RX_DV, FEC_PAD_CTL2),
402 NEW_PAD_CTRL(MX51_PAD_NANDF_D9__FEC_RDATA0, FEC_PAD_CTL2),
403 NEW_PAD_CTRL(MX51_PAD_EIM_EB3__FEC_RDATA1, FEC_PAD_CTL2),
404 NEW_PAD_CTRL(MX51_PAD_EIM_CS2__FEC_RDATA2, FEC_PAD_CTL2),
405 NEW_PAD_CTRL(MX51_PAD_EIM_CS3__FEC_RDATA3, FEC_PAD_CTL2),
406 NEW_PAD_CTRL(MX51_PAD_EIM_CS4__FEC_RX_ER, FEC_PAD_CTL2),
407 NEW_PAD_CTRL(MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK, FEC_PAD_CTL2),
408 NEW_PAD_CTRL(MX51_PAD_NANDF_CS7__FEC_TX_EN, FEC_PAD_CTL),
409 NEW_PAD_CTRL(MX51_PAD_NANDF_D8__FEC_TDATA0, FEC_PAD_CTL),
410 NEW_PAD_CTRL(MX51_PAD_NANDF_CS4__FEC_TDATA1, FEC_PAD_CTL),
411 NEW_PAD_CTRL(MX51_PAD_NANDF_CS5__FEC_TDATA2, FEC_PAD_CTL),
412 NEW_PAD_CTRL(MX51_PAD_NANDF_CS6__FEC_TDATA3, FEC_PAD_CTL),
413 NEW_PAD_CTRL(MX51_PAD_NANDF_RB2__FEC_COL, FEC_PAD_CTL2),
414 NEW_PAD_CTRL(MX51_PAD_EIM_CS5__FEC_CRS, FEC_PAD_CTL),
415 NEW_PAD_CTRL(MX51_PAD_NANDF_CS2__GPIO3_18, GPIO_PAD_CTL),
416 NEW_PAD_CTRL(MX51_PAD_EIM_A20__GPIO2_14, GPIO_PAD_CTL),
417 NEW_PAD_CTRL(MX51_PAD_GPIO1_3__GPIO1_3, GPIO_PAD_CTL),
420 /* take bit 4 of PHY address from configured PHY address or
421 * set it to 0 if PHYADDR is -1 (probe for PHY)
423 #define PHYAD4 ((CONFIG_FEC_MXC_PHYADDR >> 4) & !(CONFIG_FEC_MXC_PHYADDR >> 5))
429 } tx51_fec_gpios[] = {
430 { IMX_GPIO_NR(1, 3), 1, 1, }, /* PHY power */
431 { IMX_GPIO_NR(2, 14), 1, 0, }, /* PHY reset */
432 { IMX_GPIO_NR(3, 19), 1, 0, }, /* MDC */
433 { IMX_GPIO_NR(2, 22), 1, 0, }, /* MDIO */
434 { IMX_GPIO_NR(3, 11), 0, 1, }, /* RX_CLK */
435 { IMX_GPIO_NR(3, 29), 0, 0, }, /* RX_DV */
436 { IMX_GPIO_NR(3, 31), 1, 1, }, /* RXD0/Mode0 */
437 { IMX_GPIO_NR(2, 23), 1, 1, }, /* RXD1/Mode1 */
438 { IMX_GPIO_NR(2, 27), 1, 1, }, /* RXD2/Mode2 */
439 { IMX_GPIO_NR(2, 28), 1, 1, }, /* RXD3/nINTSEL */
440 { IMX_GPIO_NR(2, 29), 0, 0, }, /* RX_ER */
441 { IMX_GPIO_NR(3, 24), 0, 0, }, /* TX_CLK */
442 { IMX_GPIO_NR(3, 23), 1, 0, }, /* TX_EN */
443 { IMX_GPIO_NR(4, 0), 1, 0, }, /* TXD0 */
444 { IMX_GPIO_NR(3, 20), 1, 0, }, /* TXD1 */
445 { IMX_GPIO_NR(3, 21), 1, 0, }, /* TXD2 */
446 { IMX_GPIO_NR(3, 22), 1, 0, }, /* TXD3 */
447 { IMX_GPIO_NR(3, 10), 1, 0, }, /* COL */
448 { IMX_GPIO_NR(2, 30), 1, PHYAD4, }, /* PHYAD4 */
449 { IMX_GPIO_NR(3, 18), 0, 1, }, /* PHY INT (TX_ER) */
452 int board_eth_init(bd_t *bis)
455 unsigned char mac[ETH_ALEN];
456 char mac_str[ETH_ALEN * 3] = "";
459 for (i = 0; i < ARRAY_SIZE(tx51_fec_gpios); i++) {
460 int gpio = tx51_fec_gpios[i].gpio;
462 debug("Setting GPIO%d_%d as output LOW\n",
463 gpio / 32 + 1, gpio % 32);
464 gpio_direction_output(gpio, 0);
466 mxc_iomux_v3_setup_multiple_pads(tx51_fec_gpio_pads,
467 ARRAY_SIZE(tx51_fec_gpio_pads));
470 /* Power on the external phy */
471 gpio_direction_output(TX51_FEC_POWER_GPIO, 1);
474 for (i = 0; i < ARRAY_SIZE(tx51_fec_gpios); i++) {
475 int gpio = tx51_fec_gpios[i].gpio;
476 int dir = tx51_fec_gpios[i].dir;
477 int val = tx51_fec_gpios[i].val;
480 gpio_direction_output(gpio, val);
482 gpio_direction_input(gpio);
487 /* Deassert RESET to the external phy */
488 gpio_set_value(TX51_FEC_RESET_GPIO, 1);
491 mxc_iomux_v3_setup_multiple_pads(tx51_fec_pads,
492 ARRAY_SIZE(tx51_fec_pads));
494 ret = cpu_eth_init(bis);
496 printf("cpu_eth_init() failed: %d\n", ret);
499 imx_get_mac_from_fuse(0, mac);
500 snprintf(mac_str, sizeof(mac_str), "%02x:%02x:%02x:%02x:%02x:%02x",
501 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
502 setenv("ethaddr", mac_str);
506 #endif /* CONFIG_FEC_MXC */
514 void show_activity(int arg)
516 static int led_state = LED_STATE_INIT;
519 if (led_state == LED_STATE_INIT) {
521 gpio_set_value(TX51_LED_GPIO, 1);
522 led_state = LED_STATE_ON;
524 if (get_timer(last) > CONFIG_SYS_HZ) {
526 if (led_state == LED_STATE_ON) {
527 gpio_set_value(TX51_LED_GPIO, 0);
529 gpio_set_value(TX51_LED_GPIO, 1);
531 led_state = 1 - led_state;
536 static const iomux_v3_cfg_t stk5_pads[] = {
538 MX51_PAD_CSI2_D13__GPIO4_10,
540 MX51_PAD_CSI2_VSYNC__GPIO4_13,
541 /* LCD POWER_ENABLE */
542 MX51_PAD_CSI2_HSYNC__GPIO4_14,
543 /* LCD Backlight (PWM) */
544 MX51_PAD_GPIO1_2__GPIO1_2,
547 static const struct gpio stk5_gpios[] = {
548 { IMX_GPIO_NR(4, 10), GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
549 { IMX_GPIO_NR(4, 13), GPIOF_OUTPUT_INIT_LOW, "LCD RESET", },
550 { IMX_GPIO_NR(4, 14), GPIOF_OUTPUT_INIT_LOW, "LCD POWER", },
551 { IMX_GPIO_NR(1, 2), GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
554 static void stk5_board_init(void)
556 mxc_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
557 gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
560 static void stk5v3_board_init(void)
565 static void stk5v5_board_init(void)
570 static void tx51_move_fdt(void)
572 unsigned long fdt_addr = getenv_ulong("fdtcontroladdr", 16, 0);
575 #ifdef CONFIG_OF_EMBED
576 fdt = _binary_dt_dtb_start;
577 #elif defined CONFIG_OF_SEPARATE
578 fdt = (void *)(_end_ofs + _TEXT_BASE);
580 if (fdt && fdt_addr != 0) {
581 if (fdt_check_header(fdt) == 0) {
582 size_t fdt_len = fdt_totalsize(fdt);
584 memmove((void *)fdt_addr, fdt, fdt_len);
586 printf("ERROR: No valid FDT found at %p\n", fdt);
591 int board_late_init(void)
593 const char *baseboard;
597 baseboard = getenv("baseboard");
601 if (strncmp(baseboard, "stk5", 4) == 0) {
602 printf("Baseboard: %s\n", baseboard);
603 if ((strlen(baseboard) == 4) ||
604 strcmp(baseboard, "stk5-v3") == 0) {
606 } else if (strcmp(baseboard, "stk5-v5") == 0) {
609 printf("WARNING: Unsupported STK5 board rev.: %s\n",
613 printf("WARNING: Unsupported baseboard: '%s'\n",
624 printf("Board: Ka-Ro TX51-%s0x%s\n",
625 TX51_MOD_PREFIX, TX51_MOD_SUFFIX);
631 unsigned long start = get_timer(0);
632 unsigned long last = gd->tbl;
633 unsigned long loop = 0;
634 unsigned long cnt = 0;
636 unsigned long elapsed = get_timer(start);
637 unsigned long diff = gd->tbl - last;
642 printf("loop %4lu: t=%08lx diff=%08lx steps=%5lu elapsed time: %lu",
643 loop, gd->tbl, diff, cnt, elapsed / CONFIG_SYS_HZ);
645 while (get_timer(start) < loop * CONFIG_SYS_HZ) {
656 #if defined(CONFIG_OF_BOARD_SETUP)
657 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
658 #include <jffs2/jffs2.h>
659 #include <mtd_node.h>
660 struct node_info nodes[] = {
661 { "fsl,imx51-nand", MTD_DEV_TYPE_NAND, },
665 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
668 static const char *tx51_touchpanels[] = {
673 static void tx51_fixup_touchpanel(void *blob)
676 const char *model = getenv("touchpanel");
678 for (i = 0; i < ARRAY_SIZE(tx51_touchpanels); i++) {
680 const char *tp = tx51_touchpanels[i];
682 if (model != NULL && strcmp(model, tp) == 0)
685 tp = strchr(tp, ',');
686 if (tp != NULL && *tp != '\0' && strcmp(model, tp + 1) == 0)
689 offs = fdt_node_offset_by_compatible(blob, -1,
690 tx51_touchpanels[i]);
692 printf("node '%s' not found: %d\n",
693 tx51_touchpanels[i], offs);
696 printf("Removing node '%s' at offset %d\n",
697 tx51_touchpanels[i], offs);
698 fdt_del_node(blob, offs);
702 void ft_board_setup(void *blob, bd_t *bd)
704 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
705 fdt_fixup_ethernet(blob);
707 tx51_fixup_touchpanel(blob);