board/lwmon5/sdram.c

   1 /*
   2  * (C) Copyright 2006
   3  * Sylvie Gohl,             AMCC/IBM, gohl.sylvie@fr.ibm.com
   4  * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
   5  * Thierry Roman,           AMCC/IBM, thierry_roman@fr.ibm.com
   6  * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
   7  * Robert Snyder,           AMCC/IBM, rob.snyder@fr.ibm.com
   8  *
   9  * (C) Copyright 2007
  10  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation; either version 2 of
  15  * the License, or (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25  * MA 02111-1307 USA
  26  */
  27
  28 /* define DEBUG for debugging output (obviously ;-)) */
  29 #if 0
  30 #define DEBUG
  31 #endif
  32
  33 #include <common.h>
  34 #include <asm/processor.h>
  35 #include <asm/mmu.h>
  36 #include <asm/io.h>
  37 #include <ppc440.h>
  38
  39 #include "sdram.h"
  40
  41 /*
  42  * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
  43  * region. Right now the cache should still be disabled in U-Boot because of the
  44  * EMAC driver, that need it's buffer descriptor to be located in non cached
  45  * memory.
  46  *
  47  * If at some time this restriction doesn't apply anymore, just define
  48  * CFG_ENABLE_SDRAM_CACHE in the board config file and this code should setup
  49  * everything correctly.
  50  */
  51 #ifdef CFG_ENABLE_SDRAM_CACHE
  52 #define MY_TLB_WORD2_I_ENABLE   0                       /* enable caching on SDRAM */
  53 #else
  54 #define MY_TLB_WORD2_I_ENABLE   TLB_WORD2_I_ENABLE      /* disable caching on SDRAM */
  55 #endif
  56
  57 void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value);
  58 void dcbz_area(u32 start_address, u32 num_bytes);
  59 void dflush(void);
  60
  61 #ifdef CONFIG_ADD_RAM_INFO
  62 static u32 is_ecc_enabled(void)
  63 {
  64         u32 val;
  65
  66         mfsdram(DDR0_22, val);
  67         val &= DDR0_22_CTRL_RAW_MASK;
  68         if (val)
  69                 return 1;
  70         else
  71                 return 0;
  72 }
  73
  74 void board_add_ram_info(int use_default)
  75 {
  76         PPC440_SYS_INFO board_cfg;
  77         u32 val;
  78
  79         if (is_ecc_enabled())
  80                 puts(" (ECC");
  81         else
  82                 puts(" (ECC not");
  83
  84         get_sys_info(&board_cfg);
  85         printf(" enabled, %d MHz", (board_cfg.freqPLB * 2) / 1000000);
  86
  87         mfsdram(DDR0_03, val);
  88         val = DDR0_03_CASLAT_DECODE(val);
  89         printf(", CL%d)", val);
  90 }
  91 #endif
  92
  93 static int wait_for_dlllock(void)
  94 {
  95         u32 val;
  96         int wait = 0;
  97
  98         /*
  99          * Wait for the DCC master delay line to finish calibration
 100          */
 101         mtdcr(ddrcfga, DDR0_17);
 102         val = DDR0_17_DLLLOCKREG_UNLOCKED;
 103
 104         while (wait != 0xffff) {
 105                 val = mfdcr(ddrcfgd);
 106                 if ((val & DDR0_17_DLLLOCKREG_MASK) == DDR0_17_DLLLOCKREG_LOCKED)
 107                         /* dlllockreg bit on */
 108                         return 0;
 109                 else
 110                         wait++;
 111         }
 112         debug("0x%04x: DDR0_17 Value (dlllockreg bit): 0x%08x\n", wait, val);
 113         debug("Waiting for dlllockreg bit to raise\n");
 114
 115         return -1;
 116 }
 117
 118 #if defined(CONFIG_DDR_DATA_EYE)
 119 int wait_for_dram_init_complete(void)
 120 {
 121         u32 val;
 122         int wait = 0;
 123
 124         /*
 125          * Wait for 'DRAM initialization complete' bit in status register
 126          */
 127         mtdcr(ddrcfga, DDR0_00);
 128
 129         while (wait != 0xffff) {
 130                 val = mfdcr(ddrcfgd);
 131                 if ((val & DDR0_00_INT_STATUS_BIT6) == DDR0_00_INT_STATUS_BIT6)
 132                         /* 'DRAM initialization complete' bit */
 133                         return 0;
 134                 else
 135                         wait++;
 136         }
 137
 138         debug("DRAM initialization complete bit in status register did not rise\n");
 139
 140         return -1;
 141 }
 142
 143 #define NUM_TRIES 64
 144 #define NUM_READS 10
 145
 146 void denali_core_search_data_eye(u32 start_addr, u32 memory_size)
 147 {
 148         int k, j;
 149         u32 val;
 150         u32 wr_dqs_shift, dqs_out_shift, dll_dqs_delay_X;
 151         u32 max_passing_cases = 0, wr_dqs_shift_with_max_passing_cases = 0;
 152         u32 passing_cases = 0, dll_dqs_delay_X_sw_val = 0;
 153         u32 dll_dqs_delay_X_start_window = 0, dll_dqs_delay_X_end_window = 0;
 154         volatile u32 *ram_pointer;
 155         u32 test[NUM_TRIES] = {
 156                 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
 157                 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
 158                 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
 159                 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
 160                 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
 161                 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
 162                 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
 163                 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
 164                 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
 165                 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
 166                 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
 167                 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
 168                 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
 169                 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
 170                 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
 171                 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 };
 172
 173         ram_pointer = (volatile u32 *)start_addr;
 174
 175         for (wr_dqs_shift = 64; wr_dqs_shift < 96; wr_dqs_shift++) {
 176                 /*for (wr_dqs_shift=1; wr_dqs_shift<96; wr_dqs_shift++) {*/
 177
 178                 /*
 179                  * De-assert 'start' parameter.
 180                  */
 181                 mtdcr(ddrcfga, DDR0_02);
 182                 val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF;
 183                 mtdcr(ddrcfgd, val);
 184
 185                 /*
 186                  * Set 'wr_dqs_shift'
 187                  */
 188                 mtdcr(ddrcfga, DDR0_09);
 189                 val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK)
 190                         | DDR0_09_WR_DQS_SHIFT_ENCODE(wr_dqs_shift);
 191                 mtdcr(ddrcfgd, val);
 192
 193                 /*
 194                  * Set 'dqs_out_shift' = wr_dqs_shift + 32
 195                  */
 196                 dqs_out_shift = wr_dqs_shift + 32;
 197                 mtdcr(ddrcfga, DDR0_22);
 198                 val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK)
 199                         | DDR0_22_DQS_OUT_SHIFT_ENCODE(dqs_out_shift);
 200                 mtdcr(ddrcfgd, val);
 201
 202                 passing_cases = 0;
 203
 204                 for (dll_dqs_delay_X = 1; dll_dqs_delay_X < 64; dll_dqs_delay_X++) {
 205                         /*for (dll_dqs_delay_X=1; dll_dqs_delay_X<128; dll_dqs_delay_X++) {*/
 206                         /*
 207                          * Set 'dll_dqs_delay_X'.
 208                          */
 209                         /* dll_dqs_delay_0 */
 210                         mtdcr(ddrcfga, DDR0_17);
 211                         val = (mfdcr(ddrcfgd) & ~DDR0_17_DLL_DQS_DELAY_0_MASK)
 212                                 | DDR0_17_DLL_DQS_DELAY_0_ENCODE(dll_dqs_delay_X);
 213                         mtdcr(ddrcfgd, val);
 214                         /* dll_dqs_delay_1 to dll_dqs_delay_4 */
 215                         mtdcr(ddrcfga, DDR0_18);
 216                         val = (mfdcr(ddrcfgd) & ~DDR0_18_DLL_DQS_DELAY_X_MASK)
 217                                 | DDR0_18_DLL_DQS_DELAY_4_ENCODE(dll_dqs_delay_X)
 218                                 | DDR0_18_DLL_DQS_DELAY_3_ENCODE(dll_dqs_delay_X)
 219                                 | DDR0_18_DLL_DQS_DELAY_2_ENCODE(dll_dqs_delay_X)
 220                                 | DDR0_18_DLL_DQS_DELAY_1_ENCODE(dll_dqs_delay_X);
 221                         mtdcr(ddrcfgd, val);
 222                         /* dll_dqs_delay_5 to dll_dqs_delay_8 */
 223                         mtdcr(ddrcfga, DDR0_19);
 224                         val = (mfdcr(ddrcfgd) & ~DDR0_19_DLL_DQS_DELAY_X_MASK)
 225                                 | DDR0_19_DLL_DQS_DELAY_8_ENCODE(dll_dqs_delay_X)
 226                                 | DDR0_19_DLL_DQS_DELAY_7_ENCODE(dll_dqs_delay_X)
 227                                 | DDR0_19_DLL_DQS_DELAY_6_ENCODE(dll_dqs_delay_X)
 228                                 | DDR0_19_DLL_DQS_DELAY_5_ENCODE(dll_dqs_delay_X);
 229                         mtdcr(ddrcfgd, val);
 230
 231                         ppcMsync();
 232                         ppcMbar();
 233
 234                         /*
 235                          * Assert 'start' parameter.
 236                          */
 237                         mtdcr(ddrcfga, DDR0_02);
 238                         val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_ON;
 239                         mtdcr(ddrcfgd, val);
 240
 241                         ppcMsync();
 242                         ppcMbar();
 243
 244                         /*
 245                          * Wait for the DCC master delay line to finish calibration
 246                          */
 247                         if (wait_for_dlllock() != 0) {
 248                                 printf("dlllock did not occur !!!\n");
 249                                 printf("denali_core_search_data_eye!!!\n");
 250                                 printf("wr_dqs_shift = %d - dll_dqs_delay_X = %d\n",
 251                                        wr_dqs_shift, dll_dqs_delay_X);
 252                                 hang();
 253                         }
 254                         ppcMsync();
 255                         ppcMbar();
 256
 257                         if (wait_for_dram_init_complete() != 0) {
 258                                 printf("dram init complete did not occur !!!\n");
 259                                 printf("denali_core_search_data_eye!!!\n");
 260                                 printf("wr_dqs_shift = %d - dll_dqs_delay_X = %d\n",
 261                                        wr_dqs_shift, dll_dqs_delay_X);
 262                                 hang();
 263                         }
 264                         udelay(100);  /* wait 100us to ensure init is really completed !!! */
 265
 266                         /* write values */
 267                         for (j=0; j<NUM_TRIES; j++) {
 268                                 ram_pointer[j] = test[j];
 269
 270                                 /* clear any cache at ram location */
 271                                 __asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
 272                         }
 273
 274                         /* read values back */
 275                         for (j=0; j<NUM_TRIES; j++) {
 276                                 for (k=0; k<NUM_READS; k++) {
 277                                         /* clear any cache at ram location */
 278                                         __asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
 279
 280                                         if (ram_pointer[j] != test[j])
 281                                                 break;
 282                                 }
 283
 284                                 /* read error */
 285                                 if (k != NUM_READS)
 286                                         break;
 287                         }
 288
 289                         /* See if the dll_dqs_delay_X value passed.*/
 290                         if (j < NUM_TRIES) {
 291                                 /* Failed */
 292                                 passing_cases = 0;
 293                                 /* break; */
 294                         } else {
 295                                 /* Passed */
 296                                 if (passing_cases == 0)
 297                                         dll_dqs_delay_X_sw_val = dll_dqs_delay_X;
 298                                 passing_cases++;
 299                                 if (passing_cases >= max_passing_cases) {
 300                                         max_passing_cases = passing_cases;
 301                                         wr_dqs_shift_with_max_passing_cases = wr_dqs_shift;
 302                                         dll_dqs_delay_X_start_window = dll_dqs_delay_X_sw_val;
 303                                         dll_dqs_delay_X_end_window = dll_dqs_delay_X;
 304                                 }
 305                         }
 306
 307                         /*
 308                          * De-assert 'start' parameter.
 309                          */
 310                         mtdcr(ddrcfga, DDR0_02);
 311                         val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF;
 312                         mtdcr(ddrcfgd, val);
 313
 314                 } /* for (dll_dqs_delay_X=0; dll_dqs_delay_X<128; dll_dqs_delay_X++) */
 315
 316         } /* for (wr_dqs_shift=0; wr_dqs_shift<96; wr_dqs_shift++) */
 317
 318         /*
 319          * Largest passing window is now detected.
 320          */
 321
 322         /* Compute dll_dqs_delay_X value */
 323         dll_dqs_delay_X = (dll_dqs_delay_X_end_window + dll_dqs_delay_X_start_window) / 2;
 324         wr_dqs_shift = wr_dqs_shift_with_max_passing_cases;
 325
 326         debug("DQS calibration - Window detected:\n");
 327         debug("max_passing_cases = %d\n", max_passing_cases);
 328         debug("wr_dqs_shift      = %d\n", wr_dqs_shift);
 329         debug("dll_dqs_delay_X   = %d\n", dll_dqs_delay_X);
 330         debug("dll_dqs_delay_X window = %d - %d\n",
 331               dll_dqs_delay_X_start_window, dll_dqs_delay_X_end_window);
 332
 333         /*
 334          * De-assert 'start' parameter.
 335          */
 336         mtdcr(ddrcfga, DDR0_02);
 337         val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF;
 338         mtdcr(ddrcfgd, val);
 339
 340         /*
 341          * Set 'wr_dqs_shift'
 342          */
 343         mtdcr(ddrcfga, DDR0_09);
 344         val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK)
 345                 | DDR0_09_WR_DQS_SHIFT_ENCODE(wr_dqs_shift);
 346         mtdcr(ddrcfgd, val);
 347         debug("DDR0_09=0x%08lx\n", val);
 348
 349         /*
 350          * Set 'dqs_out_shift' = wr_dqs_shift + 32
 351          */
 352         dqs_out_shift = wr_dqs_shift + 32;
 353         mtdcr(ddrcfga, DDR0_22);
 354         val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK)
 355                 | DDR0_22_DQS_OUT_SHIFT_ENCODE(dqs_out_shift);
 356         mtdcr(ddrcfgd, val);
 357         debug("DDR0_22=0x%08lx\n", val);
 358
 359         /*
 360          * Set 'dll_dqs_delay_X'.
 361          */
 362         /* dll_dqs_delay_0 */
 363         mtdcr(ddrcfga, DDR0_17);
 364         val = (mfdcr(ddrcfgd) & ~DDR0_17_DLL_DQS_DELAY_0_MASK)
 365                 | DDR0_17_DLL_DQS_DELAY_0_ENCODE(dll_dqs_delay_X);
 366         mtdcr(ddrcfgd, val);
 367         debug("DDR0_17=0x%08lx\n", val);
 368
 369         /* dll_dqs_delay_1 to dll_dqs_delay_4 */
 370         mtdcr(ddrcfga, DDR0_18);
 371         val = (mfdcr(ddrcfgd) & ~DDR0_18_DLL_DQS_DELAY_X_MASK)
 372                 | DDR0_18_DLL_DQS_DELAY_4_ENCODE(dll_dqs_delay_X)
 373                 | DDR0_18_DLL_DQS_DELAY_3_ENCODE(dll_dqs_delay_X)
 374                 | DDR0_18_DLL_DQS_DELAY_2_ENCODE(dll_dqs_delay_X)
 375                 | DDR0_18_DLL_DQS_DELAY_1_ENCODE(dll_dqs_delay_X);
 376         mtdcr(ddrcfgd, val);
 377         debug("DDR0_18=0x%08lx\n", val);
 378
 379         /* dll_dqs_delay_5 to dll_dqs_delay_8 */
 380         mtdcr(ddrcfga, DDR0_19);
 381         val = (mfdcr(ddrcfgd) & ~DDR0_19_DLL_DQS_DELAY_X_MASK)
 382                 | DDR0_19_DLL_DQS_DELAY_8_ENCODE(dll_dqs_delay_X)
 383                 | DDR0_19_DLL_DQS_DELAY_7_ENCODE(dll_dqs_delay_X)
 384                 | DDR0_19_DLL_DQS_DELAY_6_ENCODE(dll_dqs_delay_X)
 385                 | DDR0_19_DLL_DQS_DELAY_5_ENCODE(dll_dqs_delay_X);
 386         mtdcr(ddrcfgd, val);
 387         debug("DDR0_19=0x%08lx\n", val);
 388
 389         /*
 390          * Assert 'start' parameter.
 391          */
 392         mtdcr(ddrcfga, DDR0_02);
 393         val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_ON;
 394         mtdcr(ddrcfgd, val);
 395
 396         ppcMsync();
 397         ppcMbar();
 398
 399         /*
 400          * Wait for the DCC master delay line to finish calibration
 401          */
 402         if (wait_for_dlllock() != 0) {
 403                 printf("dlllock did not occur !!!\n");
 404                 hang();
 405         }
 406         ppcMsync();
 407         ppcMbar();
 408
 409         if (wait_for_dram_init_complete() != 0) {
 410                 printf("dram init complete did not occur !!!\n");
 411                 hang();
 412         }
 413         udelay(100);  /* wait 100us to ensure init is really completed !!! */
 414 }
 415 #endif /* CONFIG_DDR_DATA_EYE */
 416
 417 #ifdef CONFIG_DDR_ECC
 418 static void wait_ddr_idle(void)
 419 {
 420         /*
 421          * Controller idle status cannot be determined for Denali
 422          * DDR2 code. Just return here.
 423          */
 424 }
 425
 426 static void blank_string(int size)
 427 {
 428         int i;
 429
 430         for (i=0; i<size; i++)
 431                 putc('\b');
 432         for (i=0; i<size; i++)
 433                 putc(' ');
 434         for (i=0; i<size; i++)
 435                 putc('\b');
 436 }
 437
 438 static void program_ecc(u32 start_address,
 439                         u32 num_bytes,
 440                         u32 tlb_word2_i_value)
 441 {
 442         u32 current_address;
 443         u32 end_address;
 444         u32 address_increment;
 445         u32 val;
 446         char str[] = "ECC generation -";
 447         char slash[] = "\\|/-\\|/-";
 448         int loop = 0;
 449         int loopi = 0;
 450
 451         current_address = start_address;
 452
 453         sync();
 454         eieio();
 455         wait_ddr_idle();
 456
 457         if (tlb_word2_i_value == TLB_WORD2_I_ENABLE) {
 458                 /* ECC bit set method for non-cached memory */
 459                 address_increment = 4;
 460                 end_address = current_address + num_bytes;
 461
 462                 puts(str);
 463
 464                 while (current_address < end_address) {
 465                         *((u32 *)current_address) = 0x00000000;
 466                         current_address += address_increment;
 467
 468                         if ((loop++ % (2 << 20)) == 0) {
 469                                 putc('\b');
 470                                 putc(slash[loopi++ % 8]);
 471                         }
 472                 }
 473
 474                 blank_string(strlen(str));
 475         } else {
 476                 /* ECC bit set method for cached memory */
 477                 dcbz_area(start_address, num_bytes);
 478                 dflush();
 479         }
 480
 481         sync();
 482         eieio();
 483         wait_ddr_idle();
 484
 485         /* Clear error status */
 486         mfsdram(DDR0_00, val);
 487         mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL);
 488
 489         /* Set 'int_mask' parameter to functionnal value */
 490         mfsdram(DDR0_01, val);
 491         mtsdram(DDR0_01, ((val &~ DDR0_01_INT_MASK_MASK) | DDR0_01_INT_MASK_ALL_OFF));
 492
 493         sync();
 494         eieio();
 495         wait_ddr_idle();
 496 }
 497 #endif
 498
 499 static __inline__ u32 get_mcsr(void)
 500 {
 501         u32 val;
 502
 503         asm volatile("mfspr %0, 0x23c" : "=r" (val) :);
 504         return val;
 505 }
 506
 507 static __inline__ void set_mcsr(u32 val)
 508 {
 509         asm volatile("mtspr 0x23c, %0" : "=r" (val) :);
 510 }
 511
 512 /*************************************************************************
 513  *
 514  * initdram -- 440EPx's DDR controller is a DENALI Core
 515  *
 516  ************************************************************************/
 517 long int initdram (int board_type)
 518 {
 519         u32 val;
 520
 521         mtsdram(DDR0_02, 0x00000000);
 522
 523         mtsdram(DDR0_00, 0x0000190A);
 524         mtsdram(DDR0_01, 0x01000000);
 525         mtsdram(DDR0_03, 0x02030603); /* A suitable burst length was taken. CAS is right for our board */
 526
 527         mtsdram(DDR0_04, 0x0A030300);
 528         mtsdram(DDR0_05, 0x02020308);
 529         mtsdram(DDR0_06, 0x0103C812);
 530         mtsdram(DDR0_07, 0x00090100);
 531         mtsdram(DDR0_08, 0x02c80001);
 532         mtsdram(DDR0_09, 0x00011D5F);
 533         mtsdram(DDR0_10, 0x00000300);
 534         mtsdram(DDR0_11, 0x000CC800);
 535         mtsdram(DDR0_12, 0x00000003);
 536         mtsdram(DDR0_14, 0x00000000);
 537         mtsdram(DDR0_17, 0x1e000000);
 538         mtsdram(DDR0_18, 0x1e1e1e1e);
 539         mtsdram(DDR0_19, 0x1e1e1e1e);
 540         mtsdram(DDR0_20, 0x0B0B0B0B);
 541         mtsdram(DDR0_21, 0x0B0B0B0B);
 542 #ifdef CONFIG_DDR_ECC
 543         mtsdram(DDR0_22, 0x00267F0B | DDR0_22_CTRL_RAW_ECC_ENABLE); /* enable ECC       */
 544 #else
 545         mtsdram(DDR0_22, 0x00267F0B);
 546 #endif
 547
 548         mtsdram(DDR0_23, 0x01000000);
 549         mtsdram(DDR0_24, 0x01010001);
 550
 551         mtsdram(DDR0_26, 0x2D93028A);
 552         mtsdram(DDR0_27, 0x0784682B);
 553
 554         mtsdram(DDR0_28, 0x00000080);
 555         mtsdram(DDR0_31, 0x00000000);
 556         mtsdram(DDR0_42, 0x01000006);
 557
 558         mtsdram(DDR0_43, 0x030A0200);
 559         mtsdram(DDR0_44, 0x00000003);
 560         mtsdram(DDR0_02, 0x00000001); /* Activate the denali core */
 561
 562         wait_for_dlllock();
 563
 564         /*
 565          * Program tlb entries for this size (dynamic)
 566          */
 567         program_tlb(0, 0, CFG_MBYTES_SDRAM << 20, MY_TLB_WORD2_I_ENABLE);
 568
 569         /*
 570          * Setup 2nd TLB with same physical address but different virtual address
 571          * with cache enabled. This is done for fast ECC generation.
 572          */
 573         program_tlb(0, CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20, 0);
 574
 575 #ifdef CONFIG_DDR_DATA_EYE
 576         /*
 577          * Perform data eye search if requested.
 578          */
 579         denali_core_search_data_eye(CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20);
 580
 581         /*
 582          * Clear possible errors resulting from data-eye-search.
 583          * If not done, then we could get an interrupt later on when
 584          * exceptions are enabled.
 585          */
 586         val = get_mcsr();
 587         set_mcsr(val);
 588 #endif
 589
 590 #ifdef CONFIG_DDR_ECC
 591         /*
 592          * If ECC is enabled, initialize the parity bits.
 593          */
 594         program_ecc(CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20, 0);
 595 #endif
 596
 597         return (CFG_MBYTES_SDRAM << 20);
 598 }