1 /* Memory sub-system initialization code */
4 #include <asm/regdef.h>
5 #include <asm/au1x00.h>
6 #include <asm/mipsregs.h>
8 #define AU1500_SYS_ADDR 0xB1900000
9 #define sys_endian 0x0038
10 #define CP0_Config0 $16
11 #define MEM_1MS ((396000000/1000000) * 1000)
20 * Step 1) Establish CPU endian mode.
21 * NOTE: A fair amount of code is necessary on the Pb1000 to
22 * obtain the value of Switch S8.1 which is used to determine
39 /* Set DSTRB bits so switch will read correctly */
45 /* Check switch setting */
48 and t2, t2, 0x00000100
49 bne t2, zero, big_endian
54 /* Change Au1 core to little endian */
55 li t0, AU1500_SYS_ADDR
63 /* Big Endian is default so nothing to do but fall through */
68 * Step 2) Establish Status Register
69 * (set BEV, clear ERL, clear EXL, clear IE)
75 * Step 3) Establish CP0 Config0
82 * Step 4) Disable Watchpoint facilities
88 * Step 5) Disable the performance counters
90 mtc0 zero, CP0_PERFORMANCE
94 * Step 6) Establish EJTAG Debug register
100 * Step 7) Establish Cause
106 /* Establish Wired (and Random) */
110 /* First setup pll:s to make serial work ok */
111 /* We have a 12 MHz crystal */
113 li t1, 0x21 /* 396 MHz */
119 /* wait 1mS for clocks to settle */
126 li t1, 8 /* 96 MHz */
127 sw t1, 0(t0) /* aux pll */
130 /* Static memory controller */
132 /* RCE0 8MB AMD29D323 Flash */
145 /* RCE1 CPLD Board Logic */
158 /* RCE2 CPLD Board Logic */
171 /* RCE3 PCMCIA 250ns */
186 /* Set peripherals to a known state */
212 li t0, IC0_FALLINGCLR
245 li t0, IC1_FALLINGCLR
265 li t0, SYS_PININPUTEN
287 /* wait 1mS before setup */
294 * Skip memory setup if we are running from memory
298 bltz t0, skip_memsetup
302 * SDCS0 - Not used, for SMROM
303 * SDCS1 - 32MB Micron 48LCBM16A2
304 * SDCS2 - 32MB Micron 48LCBM16A2
333 li t1, 0x74000c30 /* Disable */
348 li t1, 0x76000c30 /* Enable */
367 /* wait 1mS after setup */
376 li t1, 0/*0x00008080*/