2 * Copyright 2007,2009 Wind River Systems, Inc. <www.windriver.com>
4 * Copyright 2007 Embedded Specialties, Inc.
6 * Copyright 2004, 2007 Freescale Semiconductor.
8 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include <asm/processor.h>
32 #include <asm/immap_85xx.h>
33 #include <asm/fsl_pci.h>
34 #include <asm/fsl_ddr_sdram.h>
35 #include <asm/fsl_serdes.h>
36 #include <spd_sdram.h>
41 #include <fdt_support.h>
43 DECLARE_GLOBAL_DATA_PTR;
45 void local_bus_init(void);
47 int board_early_init_f (void)
54 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
55 volatile u_char *rev= (void *)CONFIG_SYS_BD_REV;
57 printf ("Board: Wind River SBC8548 Rev. 0x%01x\n",
61 * Initialize local bus.
65 out_be32(&ecm->eedr, 0xffffffff); /* clear ecm errors */
66 out_be32(&ecm->eeer, 0xffffffff); /* enable ecm errors */
71 * Initialize Local Bus
76 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
77 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
82 get_sys_info(&sysinfo);
83 clkdiv = (in_be32(&lbc->lcrr) & LCRR_CLKDIV) * 2;
85 out_be32(&gur->lbiuiplldcr1, 0x00078080);
87 out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0);
88 } else if (clkdiv == 8) {
89 out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0);
90 } else if (clkdiv == 4) {
91 out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0);
94 setbits_be32(&lbc->lcrr, 0x00030000);
96 asm("sync;isync;msync");
98 out_be32(&lbc->ltesr, 0xffffffff); /* Clear LBC error IRQs */
99 out_be32(&lbc->lteir, 0xffffffff); /* Enable LBC error IRQs */
103 * Initialize SDRAM memory on the Local Bus.
105 void lbc_sdram_init(void)
107 #if defined(CONFIG_SYS_LBC_SDRAM_SIZE)
110 const unsigned long size = CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024;
111 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
112 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
113 uint *sdram_addr2 = (uint *)(CONFIG_SYS_LBC_SDRAM_BASE + size/2);
117 print_size(size, "\n");
120 * Setup SDRAM Base and Option Registers
122 set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
123 set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
124 set_lbc_or(4, CONFIG_SYS_OR4_PRELIM);
125 set_lbc_br(4, CONFIG_SYS_BR4_PRELIM);
127 out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
130 out_be32(&lbc->lsrt, CONFIG_SYS_LBC_LSRT);
131 out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);
135 * Issue PRECHARGE ALL command.
137 out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_PCHALL);
140 ppcDcbf((unsigned long) sdram_addr);
142 ppcDcbf((unsigned long) sdram_addr2);
146 * Issue 8 AUTO REFRESH commands.
148 for (idx = 0; idx < 8; idx++) {
149 out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_ARFRSH);
152 ppcDcbf((unsigned long) sdram_addr);
154 ppcDcbf((unsigned long) sdram_addr2);
159 * Issue 8 MODE-set command.
161 out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_MRW);
164 ppcDcbf((unsigned long) sdram_addr);
166 ppcDcbf((unsigned long) sdram_addr2);
170 * Issue RFEN command.
172 out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_RFEN);
175 ppcDcbf((unsigned long) sdram_addr);
177 ppcDcbf((unsigned long) sdram_addr2);
178 udelay(200); /* Overkill. Must wait > 200 bus cycles */
180 #endif /* enable SDRAM init */
183 #if defined(CONFIG_SYS_DRAM_TEST)
187 uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
188 uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
191 printf("Testing DRAM from 0x%08x to 0x%08x\n",
192 CONFIG_SYS_MEMTEST_START,
193 CONFIG_SYS_MEMTEST_END);
195 printf("DRAM test phase 1:\n");
196 for (p = pstart; p < pend; p++)
199 for (p = pstart; p < pend; p++) {
200 if (*p != 0xaaaaaaaa) {
201 printf ("DRAM test fails at: %08x\n", (uint) p);
206 printf("DRAM test phase 2:\n");
207 for (p = pstart; p < pend; p++)
210 for (p = pstart; p < pend; p++) {
211 if (*p != 0x55555555) {
212 printf ("DRAM test fails at: %08x\n", (uint) p);
217 printf("DRAM test passed.\n");
223 static struct pci_controller pci1_hose;
224 #endif /* CONFIG_PCI1 */
230 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
231 int first_free_busno = 0;
234 struct fsl_pci_info pci_info;
235 u32 devdisr = in_be32(&gur->devdisr);
236 u32 pordevsr = in_be32(&gur->pordevsr);
237 u32 porpllsr = in_be32(&gur->porpllsr);
239 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
240 uint pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;
241 uint pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
242 uint pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
243 uint pci_speed = CONFIG_SYS_CLK_FREQ; /* get_clock_freq() */
245 printf("PCI: Host, %d bit, %s MHz, %s, %s\n",
247 (pci_speed == 33000000) ? "33" :
248 (pci_speed == 66000000) ? "66" : "unknown",
249 pci_clk_sel ? "sync" : "async",
250 pci_arb ? "arbiter" : "external-arbiter");
252 SET_STD_PCI_INFO(pci_info, 1);
253 set_next_law(pci_info.mem_phys,
254 law_size_bits(pci_info.mem_size), pci_info.law);
255 set_next_law(pci_info.io_phys,
256 law_size_bits(pci_info.io_size), pci_info.law);
258 first_free_busno = fsl_pci_init_port(&pci_info,
259 &pci1_hose, first_free_busno);
261 printf("PCI: disabled\n");
266 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
269 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable PCI2 */
271 fsl_pcie_init_board(first_free_busno);
275 int board_eth_init(bd_t *bis)
277 tsec_standard_init(bis);
279 return 0; /* otherwise cpu_eth_init gets run */
282 int last_stage_init(void)
287 #if defined(CONFIG_OF_BOARD_SETUP)
288 void ft_board_setup(void *blob, bd_t *bd)
290 ft_cpu_setup(blob, bd);
292 #ifdef CONFIG_FSL_PCI_INIT