3 * Texas Instruments Incorporated, <www.ti.com>
5 * Balaji Krishnamoorthy <balajitk@ti.com>
6 * Aneesh V <aneesh@ti.com>
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include <asm/arch/mux_omap4.h>
33 const struct pad_conf_entry core_padconf_array[] = {
34 {GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat0 */
35 {GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat1 */
36 {GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat2 */
37 {GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat3 */
38 {GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat4 */
39 {GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat5 */
40 {GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat6 */
41 {GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat7 */
42 {GPMC_AD8, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* gpio_32 */
43 {GPMC_AD9, (PTU | IEN | M3)}, /* gpio_33 */
44 {GPMC_AD10, (PTU | IEN | M3)}, /* gpio_34 */
45 {GPMC_AD11, (PTU | IEN | M3)}, /* gpio_35 */
46 {GPMC_AD12, (PTU | IEN | M3)}, /* gpio_36 */
47 {GPMC_AD13, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_37 */
48 {GPMC_AD14, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_38 */
49 {GPMC_AD15, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_39 */
50 {GPMC_A16, (M3)}, /* gpio_40 */
51 {GPMC_A17, (PTD | M3)}, /* gpio_41 */
52 {GPMC_A18, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row6 */
53 {GPMC_A19, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row7 */
54 {GPMC_A20, (IEN | M3)}, /* gpio_44 */
55 {GPMC_A21, (M3)}, /* gpio_45 */
56 {GPMC_A22, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col6 */
57 {GPMC_A23, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col7 */
58 {GPMC_A24, (PTD | M3)}, /* gpio_48 */
59 {GPMC_A25, (PTD | M3)}, /* gpio_49 */
60 {GPMC_NCS0, (M3)}, /* gpio_50 */
61 {GPMC_NCS1, (IEN | M3)}, /* gpio_51 */
62 {GPMC_NCS2, (IEN | M3)}, /* gpio_52 */
63 {GPMC_NCS3, (IEN | M3)}, /* gpio_53 */
64 {GPMC_NWP, (M3)}, /* gpio_54 */
65 {GPMC_CLK, (PTD | M3)}, /* gpio_55 */
66 {GPMC_NADV_ALE, (M3)}, /* gpio_56 */
67 {GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)}, /* sdmmc2_clk */
68 {GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_cmd */
69 {GPMC_NBE0_CLE, (M3)}, /* gpio_59 */
70 {GPMC_NBE1, (PTD | M3)}, /* gpio_60 */
71 {GPMC_WAIT0, (PTU | IEN | M3)}, /* gpio_61 */
72 {GPMC_WAIT1, (IEN | M3)}, /* gpio_62 */
73 {C2C_DATA11, (PTD | M3)}, /* gpio_100 */
74 {C2C_DATA12, (M1)}, /* dsi1_te0 */
75 {C2C_DATA13, (PTD | M3)}, /* gpio_102 */
76 {C2C_DATA14, (M1)}, /* dsi2_te0 */
77 {C2C_DATA15, (PTD | M3)}, /* gpio_104 */
78 {HDMI_HPD, (M0)}, /* hdmi_hpd */
79 {HDMI_CEC, (M0)}, /* hdmi_cec */
80 {HDMI_DDC_SCL, (PTU | M0)}, /* hdmi_ddc_scl */
81 {HDMI_DDC_SDA, (PTU | IEN | M0)}, /* hdmi_ddc_sda */
82 {CSI21_DX0, (IEN | M0)}, /* csi21_dx0 */
83 {CSI21_DY0, (IEN | M0)}, /* csi21_dy0 */
84 {CSI21_DX1, (IEN | M0)}, /* csi21_dx1 */
85 {CSI21_DY1, (IEN | M0)}, /* csi21_dy1 */
86 {CSI21_DX2, (IEN | M0)}, /* csi21_dx2 */
87 {CSI21_DY2, (IEN | M0)}, /* csi21_dy2 */
88 {CSI21_DX3, (PTD | M7)}, /* csi21_dx3 */
89 {CSI21_DY3, (PTD | M7)}, /* csi21_dy3 */
90 {CSI21_DX4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)}, /* csi21_dx4 */
91 {CSI21_DY4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)}, /* csi21_dy4 */
92 {CSI22_DX0, (IEN | M0)}, /* csi22_dx0 */
93 {CSI22_DY0, (IEN | M0)}, /* csi22_dy0 */
94 {CSI22_DX1, (IEN | M0)}, /* csi22_dx1 */
95 {CSI22_DY1, (IEN | M0)}, /* csi22_dy1 */
96 {CAM_SHUTTER, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_shutter */
97 {CAM_STROBE, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_strobe */
98 {CAM_GLOBALRESET, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_83 */
99 {USBB1_ULPITLL_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)},/* usbb1_ulpiphy_clk */
100 {USBB1_ULPITLL_STP, (OFF_EN | OFF_OUT_PTD | M4)}, /* usbb1_ulpiphy_stp */
101 {USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dir */
102 {USBB1_ULPITLL_NXT, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_nxt */
103 {USBB1_ULPITLL_DAT0, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat0 */
104 {USBB1_ULPITLL_DAT1, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat1 */
105 {USBB1_ULPITLL_DAT2, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat2 */
106 {USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat3 */
107 {USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat4 */
108 {USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat5 */
109 {USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat6 */
110 {USBB1_ULPITLL_DAT7, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat7 */
111 {USBB1_HSIC_DATA, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_data */
112 {USBB1_HSIC_STROBE, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_strobe */
113 {USBC1_ICUSB_DP, (IEN | M0)}, /* usbc1_icusb_dp */
114 {USBC1_ICUSB_DM, (IEN | M0)}, /* usbc1_icusb_dm */
115 {SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc1_clk */
116 {SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */
117 {SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */
118 {SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */
119 {SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */
120 {SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */
121 {SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat4 */
122 {SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat5 */
123 {SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat6 */
124 {SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat7 */
125 {ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_clkx */
126 {ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dr */
127 {ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dx */
128 {ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_fsx */
129 {ABE_MCBSP1_CLKX, (IEN | M1)}, /* abe_slimbus1_clock */
130 {ABE_MCBSP1_DR, (IEN | M1)}, /* abe_slimbus1_data */
131 {ABE_MCBSP1_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp1_dx */
132 {ABE_MCBSP1_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp1_fsx */
133 {ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_ul_data */
134 {ABE_PDM_DL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_dl_data */
135 {ABE_PDM_FRAME, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_frame */
136 {ABE_PDM_LB_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_lb_clk */
137 {ABE_CLKS, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_clks */
138 {ABE_DMIC_CLK1, (M0)}, /* abe_dmic_clk1 */
139 {ABE_DMIC_DIN1, (IEN | M0)}, /* abe_dmic_din1 */
140 {ABE_DMIC_DIN2, (IEN | M0)}, /* abe_dmic_din2 */
141 {ABE_DMIC_DIN3, (IEN | M0)}, /* abe_dmic_din3 */
142 {UART2_CTS, (PTU | IEN | M0)}, /* uart2_cts */
143 {UART2_RTS, (M0)}, /* uart2_rts */
144 {UART2_RX, (PTU | IEN | M0)}, /* uart2_rx */
145 {UART2_TX, (M0)}, /* uart2_tx */
146 {HDQ_SIO, (M3)}, /* gpio_127 */
147 {I2C1_SCL, (PTU | IEN | M0)}, /* i2c1_scl */
148 {I2C1_SDA, (PTU | IEN | M0)}, /* i2c1_sda */
149 {I2C2_SCL, (PTU | IEN | M0)}, /* i2c2_scl */
150 {I2C2_SDA, (PTU | IEN | M0)}, /* i2c2_sda */
151 {I2C3_SCL, (PTU | IEN | M0)}, /* i2c3_scl */
152 {I2C3_SDA, (PTU | IEN | M0)}, /* i2c3_sda */
153 {I2C4_SCL, (PTU | IEN | M0)}, /* i2c4_scl */
154 {I2C4_SDA, (PTU | IEN | M0)}, /* i2c4_sda */
155 {MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_clk */
156 {MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_somi */
157 {MCSPI1_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_simo */
158 {MCSPI1_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_cs0 */
159 {MCSPI1_CS1, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* mcspi1_cs1 */
160 {MCSPI1_CS2, (PTU | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_139 */
161 {MCSPI1_CS3, (PTU | IEN | M3)}, /* gpio_140 */
162 {UART3_CTS_RCTX, (PTU | IEN | M0)}, /* uart3_tx */
163 {UART3_RTS_SD, (M0)}, /* uart3_rts_sd */
164 {UART3_RX_IRRX, (IEN | M0)}, /* uart3_rx */
165 {UART3_TX_IRTX, (M0)}, /* uart3_tx */
166 {SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc5_clk */
167 {SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_cmd */
168 {SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat0 */
169 {SDMMC5_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat1 */
170 {SDMMC5_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat2 */
171 {SDMMC5_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat3 */
172 {MCSPI4_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_clk */
173 {MCSPI4_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_simo */
174 {MCSPI4_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_somi */
175 {MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_cs0 */
176 {UART4_RX, (IEN | M0)}, /* uart4_rx */
177 {UART4_TX, (M0)}, /* uart4_tx */
178 {USBB2_ULPITLL_CLK, (IEN | M3)}, /* gpio_157 */
179 {USBB2_ULPITLL_STP, (IEN | M5)}, /* dispc2_data23 */
180 {USBB2_ULPITLL_DIR, (IEN | M5)}, /* dispc2_data22 */
181 {USBB2_ULPITLL_NXT, (IEN | M5)}, /* dispc2_data21 */
182 {USBB2_ULPITLL_DAT0, (IEN | M5)}, /* dispc2_data20 */
183 {USBB2_ULPITLL_DAT1, (IEN | M5)}, /* dispc2_data19 */
184 {USBB2_ULPITLL_DAT2, (IEN | M5)}, /* dispc2_data18 */
185 {USBB2_ULPITLL_DAT3, (IEN | M5)}, /* dispc2_data15 */
186 {USBB2_ULPITLL_DAT4, (IEN | M5)}, /* dispc2_data14 */
187 {USBB2_ULPITLL_DAT5, (IEN | M5)}, /* dispc2_data13 */
188 {USBB2_ULPITLL_DAT6, (IEN | M5)}, /* dispc2_data12 */
189 {USBB2_ULPITLL_DAT7, (IEN | M5)}, /* dispc2_data11 */
190 {USBB2_HSIC_DATA, (PTD | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_169 */
191 {USBB2_HSIC_STROBE, (PTD | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_170 */
192 {UNIPRO_TX0, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col0 */
193 {UNIPRO_TY0, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col1 */
194 {UNIPRO_TX1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col2 */
195 {UNIPRO_TY1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col3 */
196 {UNIPRO_TX2, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* gpio_0 */
197 {UNIPRO_TY2, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* gpio_1 */
198 {UNIPRO_RX0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row0 */
199 {UNIPRO_RY0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row1 */
200 {UNIPRO_RX1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row2 */
201 {UNIPRO_RY1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row3 */
202 {UNIPRO_RX2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row4 */
203 {UNIPRO_RY2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row5 */
204 {USBA0_OTG_CE, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* usba0_otg_ce */
205 {USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dp */
206 {USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dm */
207 {FREF_CLK1_OUT, (M0)}, /* fref_clk1_out */
208 {FREF_CLK2_OUT, (M0)}, /* fref_clk2_out */
209 {SYS_NIRQ1, (PTU | IEN | M0)}, /* sys_nirq1 */
210 {SYS_NIRQ2, (PTU | IEN | M0)}, /* sys_nirq2 */
211 {SYS_BOOT0, (PTU | IEN | M3)}, /* gpio_184 */
212 {SYS_BOOT1, (M3)}, /* gpio_185 */
213 {SYS_BOOT2, (PTD | IEN | M3)}, /* gpio_186 */
214 {SYS_BOOT3, (M3)}, /* gpio_187 */
215 {SYS_BOOT4, (M3)}, /* gpio_188 */
216 {SYS_BOOT5, (PTD | IEN | M3)}, /* gpio_189 */
217 {DPM_EMU0, (IEN | M0)}, /* dpm_emu0 */
218 {DPM_EMU1, (IEN | M0)}, /* dpm_emu1 */
219 {DPM_EMU2, (IEN | M0)}, /* dpm_emu2 */
220 {DPM_EMU3, (IEN | M5)}, /* dispc2_data10 */
221 {DPM_EMU4, (IEN | M5)}, /* dispc2_data9 */
222 {DPM_EMU5, (IEN | M5)}, /* dispc2_data16 */
223 {DPM_EMU6, (IEN | M5)}, /* dispc2_data17 */
224 {DPM_EMU7, (IEN | M5)}, /* dispc2_hsync */
225 {DPM_EMU8, (IEN | M5)}, /* dispc2_pclk */
226 {DPM_EMU9, (IEN | M5)}, /* dispc2_vsync */
227 {DPM_EMU10, (IEN | M5)}, /* dispc2_de */
228 {DPM_EMU11, (IEN | M5)}, /* dispc2_data8 */
229 {DPM_EMU12, (IEN | M5)}, /* dispc2_data7 */
230 {DPM_EMU13, (IEN | M5)}, /* dispc2_data6 */
231 {DPM_EMU14, (IEN | M5)}, /* dispc2_data5 */
232 {DPM_EMU15, (IEN | M5)}, /* dispc2_data4 */
233 {DPM_EMU16, (IEN | M5)}, /* dispc2_data3 */
234 {DPM_EMU17, (IEN | M5)}, /* dispc2_data2 */
235 {DPM_EMU18, (IEN | M5)}, /* dispc2_data1 */
236 {DPM_EMU19, (IEN | M5)}, /* dispc2_data0 */
239 const struct pad_conf_entry wkup_padconf_array[] = {
240 {PAD0_SIM_IO, (IEN | M0)}, /* sim_io */
241 {PAD1_SIM_CLK, (M0)}, /* sim_clk */
242 {PAD0_SIM_RESET, (M0)}, /* sim_reset */
243 {PAD1_SIM_CD, (PTU | IEN | M0)}, /* sim_cd */
244 {PAD0_SIM_PWRCTRL, (M0)}, /* sim_pwrctrl */
245 {PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */
246 {PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */
247 {PAD1_FREF_XTAL_IN, (M0)}, /* # */
248 {PAD0_FREF_SLICER_IN, (M0)}, /* fref_slicer_in */
249 {PAD1_FREF_CLK_IOREQ, (M0)}, /* fref_clk_ioreq */
250 {PAD0_FREF_CLK0_OUT, (M2)}, /* sys_drm_msecure */
251 {PAD1_FREF_CLK3_REQ, (PTU | IEN | M0)}, /* # */
252 {PAD0_FREF_CLK3_OUT, (M0)}, /* fref_clk3_out */
253 {PAD1_FREF_CLK4_REQ, (PTU | OFF_EN | OFF_OUT_PTU | M3)}, /* led status_1 */
254 {PAD0_FREF_CLK4_OUT, (PTU | OFF_EN | OFF_OUT_PTU | M3)}, /* led status_2 */
255 {PAD1_SYS_32K, (IEN | M0)}, /* sys_32k */
256 {PAD0_SYS_NRESPWRON, (M0)}, /* sys_nrespwron */
257 {PAD1_SYS_NRESWARM, (M0)}, /* sys_nreswarm */
258 {PAD0_SYS_PWR_REQ, (PTU | M0)}, /* sys_pwr_req */
259 {PAD1_SYS_PWRON_RESET, (M3)}, /* gpio_wk29 */
260 {PAD0_SYS_BOOT6, (IEN | M3)}, /* gpio_wk9 */
261 {PAD1_SYS_BOOT7, (IEN | M3)}, /* gpio_wk10 */