3 * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
6 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
9 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
10 * Marius Groeger <mgroeger@sysgo.de>
12 * See file CREDITS for list of people who contributed to this
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 #include <asm/arch/hardware.h>
37 DECLARE_GLOBAL_DATA_PTR;
39 /* ------------------------------------------------------------------------- */
42 * Miscelaneous platform dependent initialisations
44 extern struct serial_device serial_ffuart_device;
45 extern struct serial_device serial_btuart_device;
46 extern struct serial_device serial_stuart_device;
48 struct serial_device *default_serial_console (void)
50 return &serial_ffuart_device;
55 /* memory and cpu-speed are setup before relocation */
56 /* so we do _nothing_ here */
58 /* arch number of vpac270 */
59 gd->bd->bi_arch_number = MACH_TYPE_VPAC270;
61 /* adress of boot parameters */
62 gd->bd->bi_boot_params = 0xa0000100;
69 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
70 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
72 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
73 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
78 int usb_board_init(void)
80 writel((UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
81 ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
84 writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
86 while (readl(UHCHR) & UHCHR_FSBIR)
89 writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
90 writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
92 /* Clear any OTG Pin Hold */
93 if (readl(PSSR) & PSSR_OTGPH)
94 writel(readl(PSSR) | PSSR_OTGPH, PSSR);
96 writel(readl(UHCRHDA) & ~(0x200), UHCRHDA);
97 writel(readl(UHCRHDA) | 0x100, UHCRHDA);
99 /* Set port power control mask bits, only 3 ports. */
100 writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
103 writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
104 UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR);
109 void usb_board_init_fail(void)
114 void usb_board_stop(void)
116 writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
118 writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
120 writel(readl(UHCCOMS) | 1, UHCCOMS);
123 writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
128 #ifdef CONFIG_DRIVER_DM9000
129 int board_eth_init(bd_t *bis)
131 return dm9000_initialize(bis);