2 * Copyright 2004,2007 Freescale Semiconductor, Inc.
3 * (C) Copyright 2002, 2003 Motorola Inc.
4 * Xianghua Xiao (X.Xiao@motorola.com)
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include <asm/cache.h>
33 #if defined(CONFIG_OF_FLAT_TREE)
41 uint lcrr; /* local bus clock ratio register */
42 uint clkdiv; /* clock divider portion of lcrr */
83 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
93 case PVR_FAM(PVR_85xx):
100 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
102 get_sys_info(&sysinfo);
104 puts("Clock Configuration:\n");
105 printf(" CPU:%4lu MHz, ", sysinfo.freqProcessor / 1000000);
106 printf("CCB:%4lu MHz,\n", sysinfo.freqSystemBus / 1000000);
107 printf(" DDR:%4lu MHz, ", sysinfo.freqSystemBus / 2000000);
109 #if defined(CFG_LBC_LCRR)
113 volatile immap_t *immap = (immap_t *)CFG_IMMR;
114 volatile ccsr_lbc_t *lbc= &immap->im_lbc;
119 clkdiv = lcrr & 0x0f;
120 if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) {
121 #if defined(CONFIG_MPC8548) || defined(CONFIG_MPC8544)
123 * Yes, the entire PQ38 family use the same
124 * bit-representation for twice the clock divider values.
128 printf("LBC:%4lu MHz\n",
129 sysinfo.freqSystemBus / 1000000 / clkdiv);
131 printf("LBC: unknown (lcrr: 0x%08x)\n", lcrr);
134 if (ver == SVR_8560) {
135 printf("CPM: %lu Mhz\n",
136 sysinfo.freqSystemBus / 1000000);
139 puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n");
145 /* ------------------------------------------------------------------------- */
147 int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
154 /* e500 v2 core has reset control register */
155 volatile unsigned int * rstcr;
156 rstcr = (volatile unsigned int *)(CFG_IMMR + 0xE00B0);
157 *rstcr = 0x2; /* HRESET_REQ */
160 * Initiate hard reset in debug control register DBCR0
161 * Make sure MSR[DE] = 1
173 * Get timebase clock frequency
175 unsigned long get_tbclk (void)
180 get_sys_info(&sys_info);
181 return ((sys_info.freqSystemBus + 7L) / 8L);
185 #if defined(CONFIG_WATCHDOG)
189 int re_enable = disable_interrupts();
190 reset_85xx_watchdog();
191 if (re_enable) enable_interrupts();
195 reset_85xx_watchdog(void)
198 * Clear TSR(WIS) bit by writing 1
201 val = mfspr(SPRN_TSR);
203 mtspr(SPRN_TSR, val);
205 #endif /* CONFIG_WATCHDOG */
207 #if defined(CONFIG_DDR_ECC)
208 void dma_init(void) {
209 volatile immap_t *immap = (immap_t *)CFG_IMMR;
210 volatile ccsr_dma_t *dma = &immap->im_dma;
212 dma->satr0 = 0x02c40000;
213 dma->datr0 = 0x02c40000;
214 dma->sr0 = 0xfffffff; /* clear any errors */
215 asm("sync; isync; msync");
219 uint dma_check(void) {
220 volatile immap_t *immap = (immap_t *)CFG_IMMR;
221 volatile ccsr_dma_t *dma = &immap->im_dma;
222 volatile uint status = dma->sr0;
224 /* While the channel is busy, spin */
225 while((status & 4) == 4) {
229 /* clear MR0[CS] channel start bit */
230 dma->mr0 &= 0x00000001;
231 asm("sync;isync;msync");
234 printf ("DMA Error: status = %x\n", status);
239 int dma_xfer(void *dest, uint count, void *src) {
240 volatile immap_t *immap = (immap_t *)CFG_IMMR;
241 volatile ccsr_dma_t *dma = &immap->im_dma;
243 dma->dar0 = (uint) dest;
244 dma->sar0 = (uint) src;
246 dma->mr0 = 0xf000004;
247 asm("sync;isync;msync");
248 dma->mr0 = 0xf000005;
249 asm("sync;isync;msync");
255 #ifdef CONFIG_OF_FLAT_TREE
257 ft_cpu_setup(void *blob, bd_t *bd)
263 clock = bd->bi_busfreq;
264 p = ft_get_prop(blob, "/cpus/" OF_CPU "/bus-frequency", &len);
266 *p = cpu_to_be32(clock);
268 p = ft_get_prop(blob, "/" OF_SOC "/serial@4500/clock-frequency", &len);
270 *p = cpu_to_be32(clock);
272 p = ft_get_prop(blob, "/" OF_SOC "/serial@4600/clock-frequency", &len);
274 *p = cpu_to_be32(clock);
276 #if defined(CONFIG_MPC85XX_TSEC1)
277 p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len);
278 memcpy(p, bd->bi_enetaddr, 6);
281 #if defined(CONFIG_HAS_ETH1)
282 p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/mac-address", &len);
283 memcpy(p, bd->bi_enet1addr, 6);
286 #if defined(CONFIG_HAS_ETH2)
287 p = ft_get_prop(blob, "/" OF_SOC "/ethernet@26000/mac-address", &len);
288 memcpy(p, bd->bi_enet2addr, 6);
291 #if defined(CONFIG_HAS_ETH3)
292 p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/mac-address", &len);
293 memcpy(p, bd->bi_enet3addr, 6);