cpu/mpc85xx/fdt.c

   1 /*
   2  * Copyright 2007 Freescale Semiconductor, Inc.
   3  *
   4  * (C) Copyright 2000
   5  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #include <common.h>
  27 #include <libfdt.h>
  28 #include <fdt_support.h>
  29 #include <asm/processor.h>
  30
  31 DECLARE_GLOBAL_DATA_PTR;
  32
  33 extern void ft_qe_setup(void *blob);
  34
  35 #ifdef CONFIG_MP
  36 #include "mp.h"
  37
  38 void ft_fixup_cpu(void *blob, u64 memory_limit)
  39 {
  40         int off;
  41         ulong spin_tbl_addr = get_spin_addr();
  42         u32 bootpg, id = get_my_id();
  43
  44         /* if we have 4G or more of memory, put the boot page at 4Gb-4k */
  45         if ((u64)gd->ram_size > 0xfffff000)
  46                 bootpg = 0xfffff000;
  47         else
  48                 bootpg = gd->ram_size - 4096;
  49
  50         off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
  51         while (off != -FDT_ERR_NOTFOUND) {
  52                 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
  53
  54                 if (reg) {
  55                         if (*reg == id) {
  56                                 fdt_setprop_string(blob, off, "status", "okay");
  57                         } else {
  58                                 u64 val = *reg * SIZE_BOOT_ENTRY + spin_tbl_addr;
  59                                 val = cpu_to_fdt32(val);
  60                                 fdt_setprop_string(blob, off, "status",
  61                                                                 "disabled");
  62                                 fdt_setprop_string(blob, off, "enable-method",
  63                                                                 "spin-table");
  64                                 fdt_setprop(blob, off, "cpu-release-addr",
  65                                                 &val, sizeof(val));
  66                         }
  67                 } else {
  68                         printf ("cpu NULL\n");
  69                 }
  70                 off = fdt_node_offset_by_prop_value(blob, off,
  71                                 "device_type", "cpu", 4);
  72         }
  73
  74         /* Reserve the boot page so OSes dont use it */
  75         if ((u64)bootpg < memory_limit) {
  76                 off = fdt_add_mem_rsv(blob, bootpg, (u64)4096);
  77                 if (off < 0)
  78                         printf("%s: %s\n", __FUNCTION__, fdt_strerror(off));
  79         }
  80 }
  81 #endif
  82
  83 #ifdef CONFIG_L2_CACHE
  84 /* return size in kilobytes */
  85 static inline u32 l2cache_size(void)
  86 {
  87         volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
  88         volatile u32 l2siz_field = (l2cache->l2ctl >> 28) & 0x3;
  89         u32 ver = SVR_SOC_VER(get_svr());
  90
  91         switch (l2siz_field) {
  92         case 0x0:
  93                 break;
  94         case 0x1:
  95                 if (ver == SVR_8540 || ver == SVR_8560   ||
  96                     ver == SVR_8541 || ver == SVR_8541_E ||
  97                     ver == SVR_8555 || ver == SVR_8555_E)
  98                         return 128;
  99                 else
 100                         return 256;
 101                 break;
 102         case 0x2:
 103                 if (ver == SVR_8540 || ver == SVR_8560   ||
 104                     ver == SVR_8541 || ver == SVR_8541_E ||
 105                     ver == SVR_8555 || ver == SVR_8555_E)
 106                         return 256;
 107                 else
 108                         return 512;
 109                 break;
 110         case 0x3:
 111                 return 1024;
 112                 break;
 113         }
 114
 115         return 0;
 116 }
 117
 118 static inline void ft_fixup_l2cache(void *blob)
 119 {
 120         int len, off;
 121         u32 *ph;
 122         struct cpu_type *cpu = identify_cpu(SVR_SOC_VER(get_svr()));
 123         char compat_buf[38];
 124
 125         const u32 line_size = 32;
 126         const u32 num_ways = 8;
 127         const u32 size = l2cache_size() * 1024;
 128         const u32 num_sets = size / (line_size * num_ways);
 129
 130         off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
 131         if (off < 0) {
 132                 debug("no cpu node fount\n");
 133                 return;
 134         }
 135
 136         ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0);
 137
 138         if (ph == NULL) {
 139                 debug("no next-level-cache property\n");
 140                 return ;
 141         }
 142
 143         off = fdt_node_offset_by_phandle(blob, *ph);
 144         if (off < 0) {
 145                 printf("%s: %s\n", __func__, fdt_strerror(off));
 146                 return ;
 147         }
 148
 149         if (cpu) {
 150                 len = sprintf(compat_buf, "fsl,mpc%s-l2-cache-controller",
 151                                 cpu->name);
 152                 sprintf(&compat_buf[len + 1], "cache");
 153         }
 154         fdt_setprop(blob, off, "cache-unified", NULL, 0);
 155         fdt_setprop_cell(blob, off, "cache-block-size", line_size);
 156         fdt_setprop_cell(blob, off, "cache-size", size);
 157         fdt_setprop_cell(blob, off, "cache-sets", num_sets);
 158         fdt_setprop_cell(blob, off, "cache-level", 2);
 159         fdt_setprop(blob, off, "compatible", compat_buf, sizeof(compat_buf));
 160 }
 161 #else
 162 #define ft_fixup_l2cache(x)
 163 #endif
 164
 165 static inline void ft_fixup_cache(void *blob)
 166 {
 167         int off;
 168
 169         off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
 170
 171         while (off != -FDT_ERR_NOTFOUND) {
 172                 u32 l1cfg0 = mfspr(SPRN_L1CFG0);
 173                 u32 l1cfg1 = mfspr(SPRN_L1CFG1);
 174                 u32 isize, iline_size, inum_sets, inum_ways;
 175                 u32 dsize, dline_size, dnum_sets, dnum_ways;
 176
 177                 /* d-side config */
 178                 dsize = (l1cfg0 & 0x7ff) * 1024;
 179                 dnum_ways = ((l1cfg0 >> 11) & 0xff) + 1;
 180                 dline_size = (((l1cfg0 >> 23) & 0x3) + 1) * 32;
 181                 dnum_sets = dsize / (dline_size * dnum_ways);
 182
 183                 fdt_setprop_cell(blob, off, "d-cache-block-size", dline_size);
 184                 fdt_setprop_cell(blob, off, "d-cache-size", dsize);
 185                 fdt_setprop_cell(blob, off, "d-cache-sets", dnum_sets);
 186
 187                 /* i-side config */
 188                 isize = (l1cfg1 & 0x7ff) * 1024;
 189                 inum_ways = ((l1cfg1 >> 11) & 0xff) + 1;
 190                 iline_size = (((l1cfg1 >> 23) & 0x3) + 1) * 32;
 191                 inum_sets = isize / (iline_size * inum_ways);
 192
 193                 fdt_setprop_cell(blob, off, "i-cache-block-size", iline_size);
 194                 fdt_setprop_cell(blob, off, "i-cache-size", isize);
 195                 fdt_setprop_cell(blob, off, "i-cache-sets", inum_sets);
 196
 197                 off = fdt_node_offset_by_prop_value(blob, off,
 198                                 "device_type", "cpu", 4);
 199         }
 200
 201         ft_fixup_l2cache(blob);
 202 }
 203
 204
 205 void fdt_add_enet_stashing(void *fdt)
 206 {
 207         do_fixup_by_compat(fdt, "gianfar", "bd-stash", NULL, 0, 1);
 208
 209         do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-len", 96, 1);
 210
 211         do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-idx", 0, 1);
 212 }
 213
 214 void ft_cpu_setup(void *blob, bd_t *bd)
 215 {
 216         int off;
 217         int val;
 218         sys_info_t sysinfo;
 219
 220         /* delete crypto node if not on an E-processor */
 221         if (!IS_E_PROCESSOR(get_svr()))
 222                 fdt_fixup_crypto_node(blob, 0);
 223
 224 #if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\
 225     defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3)
 226         fdt_fixup_ethernet(blob);
 227
 228         fdt_add_enet_stashing(blob);
 229 #endif
 230
 231         do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
 232                 "timebase-frequency", bd->bi_busfreq / 8, 1);
 233         do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
 234                 "bus-frequency", bd->bi_busfreq, 1);
 235         get_sys_info(&sysinfo);
 236         off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
 237         while (off != -FDT_ERR_NOTFOUND) {
 238                 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
 239                 val = cpu_to_fdt32(sysinfo.freqProcessor[*reg]);
 240                 fdt_setprop(blob, off, "clock-frequency", &val, 4);
 241                 off = fdt_node_offset_by_prop_value(blob, off, "device_type",
 242                                                         "cpu", 4);
 243         }
 244         do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
 245                 "bus-frequency", bd->bi_busfreq, 1);
 246
 247         do_fixup_by_compat_u32(blob, "fsl,pq3-localbus",
 248                 "bus-frequency", gd->lbc_clk, 1);
 249         do_fixup_by_compat_u32(blob, "fsl,elbc",
 250                 "bus-frequency", gd->lbc_clk, 1);
 251 #ifdef CONFIG_QE
 252         ft_qe_setup(blob);
 253 #endif
 254
 255 #ifdef CONFIG_SYS_NS16550
 256         do_fixup_by_compat_u32(blob, "ns16550",
 257                 "clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
 258 #endif
 259
 260 #ifdef CONFIG_CPM2
 261         do_fixup_by_compat_u32(blob, "fsl,cpm2-scc-uart",
 262                 "current-speed", bd->bi_baudrate, 1);
 263
 264         do_fixup_by_compat_u32(blob, "fsl,cpm2-brg",
 265                 "clock-frequency", bd->bi_brgfreq, 1);
 266 #endif
 267
 268         fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
 269
 270 #ifdef CONFIG_MP
 271         ft_fixup_cpu(blob, (u64)bd->bi_memstart + (u64)bd->bi_memsize);
 272 #endif
 273
 274         ft_fixup_cache(blob);
 275 }