cpu/ppc4xx/44x_spd_ddr2.c

   1 /*
   2  * cpu/ppc4xx/44x_spd_ddr2.c
   3  * This SPD SDRAM detection code supports AMCC PPC44x cpu's with a
   4  * DDR2 controller (non Denali Core). Those are 440SP/SPe.
   5  *
   6  * (C) Copyright 2007
   7  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   8  *
   9  * COPYRIGHT   AMCC   CORPORATION 2004
  10  *
  11  * See file CREDITS for list of people who contributed to this
  12  * project.
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License as
  16  * published by the Free Software Foundation; either version 2 of
  17  * the License, or (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27  * MA 02111-1307 USA
  28  *
  29  */
  30
  31 /* define DEBUG for debugging output (obviously ;-)) */
  32 #if 0
  33 #define DEBUG
  34 #endif
  35
  36 #include <common.h>
  37 #include <command.h>
  38 #include <ppc4xx.h>
  39 #include <i2c.h>
  40 #include <asm/io.h>
  41 #include <asm/processor.h>
  42 #include <asm/mmu.h>
  43
  44 #if defined(CONFIG_SPD_EEPROM) &&                               \
  45         (defined(CONFIG_440SP) || defined(CONFIG_440SPE))
  46
  47 /*-----------------------------------------------------------------------------+
  48  * Defines
  49  *-----------------------------------------------------------------------------*/
  50 #ifndef TRUE
  51 #define TRUE            1
  52 #endif
  53 #ifndef FALSE
  54 #define FALSE           0
  55 #endif
  56
  57 #define SDRAM_DDR1      1
  58 #define SDRAM_DDR2      2
  59 #define SDRAM_NONE      0
  60
  61 #define MAXDIMMS        2
  62 #define MAXRANKS        4
  63 #define MAXBXCF         4
  64 #define MAX_SPD_BYTES   256   /* Max number of bytes on the DIMM's SPD EEPROM */
  65
  66 #define ONE_BILLION     1000000000
  67
  68 #define MULDIV64(m1, m2, d)     (u32)(((u64)(m1) * (u64)(m2)) / (u64)(d))
  69
  70 #define CMD_NOP         (7 << 19)
  71 #define CMD_PRECHARGE   (2 << 19)
  72 #define CMD_REFRESH     (1 << 19)
  73 #define CMD_EMR         (0 << 19)
  74 #define CMD_READ        (5 << 19)
  75 #define CMD_WRITE       (4 << 19)
  76
  77 #define SELECT_MR       (0 << 16)
  78 #define SELECT_EMR      (1 << 16)
  79 #define SELECT_EMR2     (2 << 16)
  80 #define SELECT_EMR3     (3 << 16)
  81
  82 /* MR */
  83 #define DLL_RESET       0x00000100
  84
  85 #define WRITE_RECOV_2   (1 << 9)
  86 #define WRITE_RECOV_3   (2 << 9)
  87 #define WRITE_RECOV_4   (3 << 9)
  88 #define WRITE_RECOV_5   (4 << 9)
  89 #define WRITE_RECOV_6   (5 << 9)
  90
  91 #define BURST_LEN_4     0x00000002
  92
  93 /* EMR */
  94 #define ODT_0_OHM       0x00000000
  95 #define ODT_50_OHM      0x00000044
  96 #define ODT_75_OHM      0x00000004
  97 #define ODT_150_OHM     0x00000040
  98
  99 #define ODS_FULL        0x00000000
 100 #define ODS_REDUCED     0x00000002
 101
 102 /* defines for ODT (On Die Termination) of the 440SP(e) DDR2 controller */
 103 #define ODT_EB0R        (0x80000000 >> 8)
 104 #define ODT_EB0W        (0x80000000 >> 7)
 105 #define CALC_ODT_R(n)   (ODT_EB0R << (n << 1))
 106 #define CALC_ODT_W(n)   (ODT_EB0W << (n << 1))
 107 #define CALC_ODT_RW(n)  (CALC_ODT_R(n) | CALC_ODT_W(n))
 108
 109 /* Defines for the Read Cycle Delay test */
 110 #define NUMMEMTESTS 8
 111 #define NUMMEMWORDS 8
 112
 113 #define CONFIG_ECC_ERROR_RESET          /* test-only: see description below, at check_ecc() */
 114
 115 /*
 116  * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
 117  * region. Right now the cache should still be disabled in U-Boot because of the
 118  * EMAC driver, that need it's buffer descriptor to be located in non cached
 119  * memory.
 120  *
 121  * If at some time this restriction doesn't apply anymore, just define
 122  * CFG_ENABLE_SDRAM_CACHE in the board config file and this code should setup
 123  * everything correctly.
 124  */
 125 #ifdef CFG_ENABLE_SDRAM_CACHE
 126 #define MY_TLB_WORD2_I_ENABLE   0                       /* enable caching on SDRAM */
 127 #else
 128 #define MY_TLB_WORD2_I_ENABLE   TLB_WORD2_I_ENABLE      /* disable caching on SDRAM */
 129 #endif
 130
 131 /* Private Structure Definitions */
 132
 133 /* enum only to ease code for cas latency setting */
 134 typedef enum ddr_cas_id {
 135         DDR_CAS_2      = 20,
 136         DDR_CAS_2_5    = 25,
 137         DDR_CAS_3      = 30,
 138         DDR_CAS_4      = 40,
 139         DDR_CAS_5      = 50
 140 } ddr_cas_id_t;
 141
 142 /*-----------------------------------------------------------------------------+
 143  * Prototypes
 144  *-----------------------------------------------------------------------------*/
 145 static unsigned long sdram_memsize(void);
 146 void program_tlb(u32 start, u32 size, u32 tlb_word2_i_value);
 147 static void get_spd_info(unsigned long *dimm_populated,
 148                          unsigned char *iic0_dimm_addr,
 149                          unsigned long num_dimm_banks);
 150 static void check_mem_type(unsigned long *dimm_populated,
 151                            unsigned char *iic0_dimm_addr,
 152                            unsigned long num_dimm_banks);
 153 static void check_frequency(unsigned long *dimm_populated,
 154                             unsigned char *iic0_dimm_addr,
 155                             unsigned long num_dimm_banks);
 156 static void check_rank_number(unsigned long *dimm_populated,
 157                               unsigned char *iic0_dimm_addr,
 158                               unsigned long num_dimm_banks);
 159 static void check_voltage_type(unsigned long *dimm_populated,
 160                                unsigned char *iic0_dimm_addr,
 161                                unsigned long num_dimm_banks);
 162 static void program_memory_queue(unsigned long *dimm_populated,
 163                                  unsigned char *iic0_dimm_addr,
 164                                  unsigned long num_dimm_banks);
 165 static void program_codt(unsigned long *dimm_populated,
 166                          unsigned char *iic0_dimm_addr,
 167                          unsigned long num_dimm_banks);
 168 static void program_mode(unsigned long *dimm_populated,
 169                          unsigned char *iic0_dimm_addr,
 170                          unsigned long num_dimm_banks,
 171                          ddr_cas_id_t *selected_cas,
 172                          int *write_recovery);
 173 static void program_tr(unsigned long *dimm_populated,
 174                        unsigned char *iic0_dimm_addr,
 175                        unsigned long num_dimm_banks);
 176 static void program_rtr(unsigned long *dimm_populated,
 177                         unsigned char *iic0_dimm_addr,
 178                         unsigned long num_dimm_banks);
 179 static void program_bxcf(unsigned long *dimm_populated,
 180                          unsigned char *iic0_dimm_addr,
 181                          unsigned long num_dimm_banks);
 182 static void program_copt1(unsigned long *dimm_populated,
 183                           unsigned char *iic0_dimm_addr,
 184                           unsigned long num_dimm_banks);
 185 static void program_initplr(unsigned long *dimm_populated,
 186                             unsigned char *iic0_dimm_addr,
 187                             unsigned long num_dimm_banks,
 188                             ddr_cas_id_t selected_cas,
 189                             int write_recovery);
 190 static unsigned long is_ecc_enabled(void);
 191 #ifdef CONFIG_DDR_ECC
 192 static void program_ecc(unsigned long *dimm_populated,
 193                         unsigned char *iic0_dimm_addr,
 194                         unsigned long num_dimm_banks,
 195                         unsigned long tlb_word2_i_value);
 196 static void program_ecc_addr(unsigned long start_address,
 197                              unsigned long num_bytes,
 198                              unsigned long tlb_word2_i_value);
 199 #endif
 200 static void program_DQS_calibration(unsigned long *dimm_populated,
 201                                     unsigned char *iic0_dimm_addr,
 202                                     unsigned long num_dimm_banks);
 203 #ifdef HARD_CODED_DQS /* calibration test with hardvalues */
 204 static void     test(void);
 205 #else
 206 static void     DQS_calibration_process(void);
 207 #endif
 208 #if defined(DEBUG)
 209 static void ppc440sp_sdram_register_dump(void);
 210 #endif
 211 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
 212 void dcbz_area(u32 start_address, u32 num_bytes);
 213 void dflush(void);
 214
 215 static u32 mfdcr_any(u32 dcr)
 216 {
 217         u32 val;
 218
 219         switch (dcr) {
 220         case SDRAM_R0BAS + 0:
 221                 val = mfdcr(SDRAM_R0BAS + 0);
 222                 break;
 223         case SDRAM_R0BAS + 1:
 224                 val = mfdcr(SDRAM_R0BAS + 1);
 225                 break;
 226         case SDRAM_R0BAS + 2:
 227                 val = mfdcr(SDRAM_R0BAS + 2);
 228                 break;
 229         case SDRAM_R0BAS + 3:
 230                 val = mfdcr(SDRAM_R0BAS + 3);
 231                 break;
 232         default:
 233                 printf("DCR %d not defined in case statement!!!\n", dcr);
 234                 val = 0; /* just to satisfy the compiler */
 235         }
 236
 237         return val;
 238 }
 239
 240 static void mtdcr_any(u32 dcr, u32 val)
 241 {
 242         switch (dcr) {
 243         case SDRAM_R0BAS + 0:
 244                 mtdcr(SDRAM_R0BAS + 0, val);
 245                 break;
 246         case SDRAM_R0BAS + 1:
 247                 mtdcr(SDRAM_R0BAS + 1, val);
 248                 break;
 249         case SDRAM_R0BAS + 2:
 250                 mtdcr(SDRAM_R0BAS + 2, val);
 251                 break;
 252         case SDRAM_R0BAS + 3:
 253                 mtdcr(SDRAM_R0BAS + 3, val);
 254                 break;
 255         default:
 256                 printf("DCR %d not defined in case statement!!!\n", dcr);
 257         }
 258 }
 259
 260 static unsigned char spd_read(uchar chip, uint addr)
 261 {
 262         unsigned char data[2];
 263
 264         if (i2c_probe(chip) == 0)
 265                 if (i2c_read(chip, addr, 1, data, 1) == 0)
 266                         return data[0];
 267
 268         return 0;
 269 }
 270
 271 /*-----------------------------------------------------------------------------+
 272  * sdram_memsize
 273  *-----------------------------------------------------------------------------*/
 274 static unsigned long sdram_memsize(void)
 275 {
 276         unsigned long mem_size;
 277         unsigned long mcopt2;
 278         unsigned long mcstat;
 279         unsigned long mb0cf;
 280         unsigned long sdsz;
 281         unsigned long i;
 282
 283         mem_size = 0;
 284
 285         mfsdram(SDRAM_MCOPT2, mcopt2);
 286         mfsdram(SDRAM_MCSTAT, mcstat);
 287
 288         /* DDR controller must be enabled and not in self-refresh. */
 289         /* Otherwise memsize is zero. */
 290         if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE)
 291             && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT)
 292             && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK))
 293                 == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) {
 294                 for (i = 0; i < MAXBXCF; i++) {
 295                         mfsdram(SDRAM_MB0CF + (i << 2), mb0cf);
 296                         /* Banks enabled */
 297                         if ((mb0cf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
 298                                 sdsz = mfdcr_any(SDRAM_R0BAS + i) & SDRAM_RXBAS_SDSZ_MASK;
 299
 300                                 switch(sdsz) {
 301                                 case SDRAM_RXBAS_SDSZ_8:
 302                                         mem_size+=8;
 303                                         break;
 304                                 case SDRAM_RXBAS_SDSZ_16:
 305                                         mem_size+=16;
 306                                         break;
 307                                 case SDRAM_RXBAS_SDSZ_32:
 308                                         mem_size+=32;
 309                                         break;
 310                                 case SDRAM_RXBAS_SDSZ_64:
 311                                         mem_size+=64;
 312                                         break;
 313                                 case SDRAM_RXBAS_SDSZ_128:
 314                                         mem_size+=128;
 315                                         break;
 316                                 case SDRAM_RXBAS_SDSZ_256:
 317                                         mem_size+=256;
 318                                         break;
 319                                 case SDRAM_RXBAS_SDSZ_512:
 320                                         mem_size+=512;
 321                                         break;
 322                                 case SDRAM_RXBAS_SDSZ_1024:
 323                                         mem_size+=1024;
 324                                         break;
 325                                 case SDRAM_RXBAS_SDSZ_2048:
 326                                         mem_size+=2048;
 327                                         break;
 328                                 case SDRAM_RXBAS_SDSZ_4096:
 329                                         mem_size+=4096;
 330                                         break;
 331                                 default:
 332                                         mem_size=0;
 333                                         break;
 334                                 }
 335                         }
 336                 }
 337         }
 338
 339         mem_size *= 1024 * 1024;
 340         return(mem_size);
 341 }
 342
 343 /*-----------------------------------------------------------------------------+
 344  * initdram.  Initializes the 440SP Memory Queue and DDR SDRAM controller.
 345  * Note: This routine runs from flash with a stack set up in the chip's
 346  * sram space.  It is important that the routine does not require .sbss, .bss or
 347  * .data sections.  It also cannot call routines that require these sections.
 348  *-----------------------------------------------------------------------------*/
 349 /*-----------------------------------------------------------------------------
 350  * Function:     initdram
 351  * Description:  Configures SDRAM memory banks for DDR operation.
 352  *               Auto Memory Configuration option reads the DDR SDRAM EEPROMs
 353  *               via the IIC bus and then configures the DDR SDRAM memory
 354  *               banks appropriately. If Auto Memory Configuration is
 355  *               not used, it is assumed that no DIMM is plugged
 356  *-----------------------------------------------------------------------------*/
 357 long int initdram(int board_type)
 358 {
 359         unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
 360         unsigned char spd0[MAX_SPD_BYTES];
 361         unsigned char spd1[MAX_SPD_BYTES];
 362         unsigned char *dimm_spd[MAXDIMMS];
 363         unsigned long dimm_populated[MAXDIMMS];
 364         unsigned long num_dimm_banks;               /* on board dimm banks */
 365         unsigned long val;
 366         ddr_cas_id_t  selected_cas;
 367         int write_recovery;
 368         unsigned long dram_size = 0;
 369
 370         num_dimm_banks = sizeof(iic0_dimm_addr);
 371
 372         /*------------------------------------------------------------------
 373          * Set up an array of SPD matrixes.
 374          *-----------------------------------------------------------------*/
 375         dimm_spd[0] = spd0;
 376         dimm_spd[1] = spd1;
 377
 378         /*------------------------------------------------------------------
 379          * Reset the DDR-SDRAM controller.
 380          *-----------------------------------------------------------------*/
 381         mtsdr(SDR0_SRST, (0x80000000 >> 10));
 382         mtsdr(SDR0_SRST, 0x00000000);
 383
 384         /*
 385          * Make sure I2C controller is initialized
 386          * before continuing.
 387          */
 388
 389         /* switch to correct I2C bus */
 390         I2C_SET_BUS(CFG_SPD_BUS_NUM);
 391         i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
 392
 393         /*------------------------------------------------------------------
 394          * Clear out the serial presence detect buffers.
 395          * Perform IIC reads from the dimm.  Fill in the spds.
 396          * Check to see if the dimm slots are populated
 397          *-----------------------------------------------------------------*/
 398         get_spd_info(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 399
 400         /*------------------------------------------------------------------
 401          * Check the memory type for the dimms plugged.
 402          *-----------------------------------------------------------------*/
 403         check_mem_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 404
 405         /*------------------------------------------------------------------
 406          * Check the frequency supported for the dimms plugged.
 407          *-----------------------------------------------------------------*/
 408         check_frequency(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 409
 410         /*------------------------------------------------------------------
 411          * Check the total rank number.
 412          *-----------------------------------------------------------------*/
 413         check_rank_number(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 414
 415         /*------------------------------------------------------------------
 416          * Check the voltage type for the dimms plugged.
 417          *-----------------------------------------------------------------*/
 418         check_voltage_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 419
 420         /*------------------------------------------------------------------
 421          * Program SDRAM controller options 2 register
 422          * Except Enabling of the memory controller.
 423          *-----------------------------------------------------------------*/
 424         mfsdram(SDRAM_MCOPT2, val);
 425         mtsdram(SDRAM_MCOPT2,
 426                 (val &
 427                  ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_PMEN_MASK |
 428                    SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_XSRP_MASK |
 429                    SDRAM_MCOPT2_ISIE_MASK))
 430                 | (SDRAM_MCOPT2_SREN_ENTER | SDRAM_MCOPT2_PMEN_DISABLE |
 431                    SDRAM_MCOPT2_IPTR_IDLE | SDRAM_MCOPT2_XSRP_ALLOW |
 432                    SDRAM_MCOPT2_ISIE_ENABLE));
 433
 434         /*------------------------------------------------------------------
 435          * Program SDRAM controller options 1 register
 436          * Note: Does not enable the memory controller.
 437          *-----------------------------------------------------------------*/
 438         program_copt1(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 439
 440         /*------------------------------------------------------------------
 441          * Set the SDRAM Controller On Die Termination Register
 442          *-----------------------------------------------------------------*/
 443         program_codt(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 444
 445         /*------------------------------------------------------------------
 446          * Program SDRAM refresh register.
 447          *-----------------------------------------------------------------*/
 448         program_rtr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 449
 450         /*------------------------------------------------------------------
 451          * Program SDRAM mode register.
 452          *-----------------------------------------------------------------*/
 453         program_mode(dimm_populated, iic0_dimm_addr, num_dimm_banks,
 454                      &selected_cas, &write_recovery);
 455
 456         /*------------------------------------------------------------------
 457          * Set the SDRAM Write Data/DM/DQS Clock Timing Reg
 458          *-----------------------------------------------------------------*/
 459         mfsdram(SDRAM_WRDTR, val);
 460         mtsdram(SDRAM_WRDTR, (val & ~(SDRAM_WRDTR_LLWP_MASK | SDRAM_WRDTR_WTR_MASK)) |
 461                 (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_90_DEG_ADV));
 462
 463         /*------------------------------------------------------------------
 464          * Set the SDRAM Clock Timing Register
 465          *-----------------------------------------------------------------*/
 466         mfsdram(SDRAM_CLKTR, val);
 467         mtsdram(SDRAM_CLKTR, (val & ~SDRAM_CLKTR_CLKP_MASK) | SDRAM_CLKTR_CLKP_0_DEG);
 468
 469         /*------------------------------------------------------------------
 470          * Program the BxCF registers.
 471          *-----------------------------------------------------------------*/
 472         program_bxcf(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 473
 474         /*------------------------------------------------------------------
 475          * Program SDRAM timing registers.
 476          *-----------------------------------------------------------------*/
 477         program_tr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 478
 479         /*------------------------------------------------------------------
 480          * Set the Extended Mode register
 481          *-----------------------------------------------------------------*/
 482         mfsdram(SDRAM_MEMODE, val);
 483         mtsdram(SDRAM_MEMODE,
 484                 (val & ~(SDRAM_MEMODE_DIC_MASK  | SDRAM_MEMODE_DLL_MASK |
 485                          SDRAM_MEMODE_RTT_MASK | SDRAM_MEMODE_DQS_MASK)) |
 486                 (SDRAM_MEMODE_DIC_NORMAL | SDRAM_MEMODE_DLL_ENABLE
 487                  | SDRAM_MEMODE_RTT_150OHM | SDRAM_MEMODE_DQS_ENABLE));
 488
 489         /*------------------------------------------------------------------
 490          * Program Initialization preload registers.
 491          *-----------------------------------------------------------------*/
 492         program_initplr(dimm_populated, iic0_dimm_addr, num_dimm_banks,
 493                         selected_cas, write_recovery);
 494
 495         /*------------------------------------------------------------------
 496          * Delay to ensure 200usec have elapsed since reset.
 497          *-----------------------------------------------------------------*/
 498         udelay(400);
 499
 500         /*------------------------------------------------------------------
 501          * Set the memory queue core base addr.
 502          *-----------------------------------------------------------------*/
 503         program_memory_queue(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 504
 505         /*------------------------------------------------------------------
 506          * Program SDRAM controller options 2 register
 507          * Enable the memory controller.
 508          *-----------------------------------------------------------------*/
 509         mfsdram(SDRAM_MCOPT2, val);
 510         mtsdram(SDRAM_MCOPT2,
 511                 (val & ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_DCEN_MASK |
 512                          SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_ISIE_MASK)) |
 513                 (SDRAM_MCOPT2_DCEN_ENABLE | SDRAM_MCOPT2_IPTR_EXECUTE));
 514
 515         /*------------------------------------------------------------------
 516          * Wait for SDRAM_CFG0_DC_EN to complete.
 517          *-----------------------------------------------------------------*/
 518         do {
 519                 mfsdram(SDRAM_MCSTAT, val);
 520         } while ((val & SDRAM_MCSTAT_MIC_MASK) == SDRAM_MCSTAT_MIC_NOTCOMP);
 521
 522         /* get installed memory size */
 523         dram_size = sdram_memsize();
 524
 525         /* and program tlb entries for this size (dynamic) */
 526         program_tlb(0, dram_size, MY_TLB_WORD2_I_ENABLE);
 527
 528         /*------------------------------------------------------------------
 529          * DQS calibration.
 530          *-----------------------------------------------------------------*/
 531         program_DQS_calibration(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 532
 533 #ifdef CONFIG_DDR_ECC
 534         /*------------------------------------------------------------------
 535          * If ecc is enabled, initialize the parity bits.
 536          *-----------------------------------------------------------------*/
 537         program_ecc(dimm_populated, iic0_dimm_addr, num_dimm_banks, MY_TLB_WORD2_I_ENABLE);
 538 #endif
 539
 540 #ifdef DEBUG
 541         ppc440sp_sdram_register_dump();
 542 #endif
 543
 544         return dram_size;
 545 }
 546
 547 static void get_spd_info(unsigned long *dimm_populated,
 548                          unsigned char *iic0_dimm_addr,
 549                          unsigned long num_dimm_banks)
 550 {
 551         unsigned long dimm_num;
 552         unsigned long dimm_found;
 553         unsigned char num_of_bytes;
 554         unsigned char total_size;
 555
 556         dimm_found = FALSE;
 557         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 558                 num_of_bytes = 0;
 559                 total_size = 0;
 560
 561                 num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0);
 562                 debug("\nspd_read(0x%x) returned %d\n",
 563                       iic0_dimm_addr[dimm_num], num_of_bytes);
 564                 total_size = spd_read(iic0_dimm_addr[dimm_num], 1);
 565                 debug("spd_read(0x%x) returned %d\n",
 566                       iic0_dimm_addr[dimm_num], total_size);
 567
 568                 if ((num_of_bytes != 0) && (total_size != 0)) {
 569                         dimm_populated[dimm_num] = TRUE;
 570                         dimm_found = TRUE;
 571                         debug("DIMM slot %lu: populated\n", dimm_num);
 572                 } else {
 573                         dimm_populated[dimm_num] = FALSE;
 574                         debug("DIMM slot %lu: Not populated\n", dimm_num);
 575                 }
 576         }
 577
 578         if (dimm_found == FALSE) {
 579                 printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
 580                 hang();
 581         }
 582 }
 583
 584 #ifdef CONFIG_ADD_RAM_INFO
 585 void board_add_ram_info(int use_default)
 586 {
 587         if (is_ecc_enabled())
 588                 puts(" (ECC enabled)");
 589         else
 590                 puts(" (ECC not enabled)");
 591 }
 592 #endif
 593
 594 /*------------------------------------------------------------------
 595  * For the memory DIMMs installed, this routine verifies that they
 596  * really are DDR specific DIMMs.
 597  *-----------------------------------------------------------------*/
 598 static void check_mem_type(unsigned long *dimm_populated,
 599                            unsigned char *iic0_dimm_addr,
 600                            unsigned long num_dimm_banks)
 601 {
 602         unsigned long dimm_num;
 603         unsigned long dimm_type;
 604
 605         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 606                 if (dimm_populated[dimm_num] == TRUE) {
 607                         dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2);
 608                         switch (dimm_type) {
 609                         case 1:
 610                                 printf("ERROR: Standard Fast Page Mode DRAM DIMM detected in "
 611                                        "slot %d.\n", (unsigned int)dimm_num);
 612                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 613                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 614                                 hang();
 615                                 break;
 616                         case 2:
 617                                 printf("ERROR: EDO DIMM detected in slot %d.\n",
 618                                        (unsigned int)dimm_num);
 619                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 620                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 621                                 hang();
 622                                 break;
 623                         case 3:
 624                                 printf("ERROR: Pipelined Nibble DIMM detected in slot %d.\n",
 625                                        (unsigned int)dimm_num);
 626                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 627                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 628                                 hang();
 629                                 break;
 630                         case 4:
 631                                 printf("ERROR: SDRAM DIMM detected in slot %d.\n",
 632                                        (unsigned int)dimm_num);
 633                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 634                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 635                                 hang();
 636                                 break;
 637                         case 5:
 638                                 printf("ERROR: Multiplexed ROM DIMM detected in slot %d.\n",
 639                                        (unsigned int)dimm_num);
 640                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 641                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 642                                 hang();
 643                                 break;
 644                         case 6:
 645                                 printf("ERROR: SGRAM DIMM detected in slot %d.\n",
 646                                        (unsigned int)dimm_num);
 647                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 648                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 649                                 hang();
 650                                 break;
 651                         case 7:
 652                                 debug("DIMM slot %d: DDR1 SDRAM detected\n", dimm_num);
 653                                 dimm_populated[dimm_num] = SDRAM_DDR1;
 654                                 break;
 655                         case 8:
 656                                 debug("DIMM slot %d: DDR2 SDRAM detected\n", dimm_num);
 657                                 dimm_populated[dimm_num] = SDRAM_DDR2;
 658                                 break;
 659                         default:
 660                                 printf("ERROR: Unknown DIMM detected in slot %d.\n",
 661                                        (unsigned int)dimm_num);
 662                                 printf("Only DDR1 and DDR2 SDRAM DIMMs are supported.\n");
 663                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 664                                 hang();
 665                                 break;
 666                         }
 667                 }
 668         }
 669         for (dimm_num = 1; dimm_num < num_dimm_banks; dimm_num++) {
 670                 if ((dimm_populated[dimm_num-1] != SDRAM_NONE)
 671                     && (dimm_populated[dimm_num]   != SDRAM_NONE)
 672                     && (dimm_populated[dimm_num-1] != dimm_populated[dimm_num])) {
 673                         printf("ERROR: DIMM's DDR1 and DDR2 type can not be mixed.\n");
 674                         hang();
 675                 }
 676         }
 677 }
 678
 679 /*------------------------------------------------------------------
 680  * For the memory DIMMs installed, this routine verifies that
 681  * frequency previously calculated is supported.
 682  *-----------------------------------------------------------------*/
 683 static void check_frequency(unsigned long *dimm_populated,
 684                             unsigned char *iic0_dimm_addr,
 685                             unsigned long num_dimm_banks)
 686 {
 687         unsigned long dimm_num;
 688         unsigned long tcyc_reg;
 689         unsigned long cycle_time;
 690         unsigned long calc_cycle_time;
 691         unsigned long sdram_freq;
 692         unsigned long sdr_ddrpll;
 693         PPC440_SYS_INFO board_cfg;
 694
 695         /*------------------------------------------------------------------
 696          * Get the board configuration info.
 697          *-----------------------------------------------------------------*/
 698         get_sys_info(&board_cfg);
 699
 700         mfsdr(SDR0_DDR0, sdr_ddrpll);
 701         sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
 702
 703         /*
 704          * calc_cycle_time is calculated from DDR frequency set by board/chip
 705          * and is expressed in multiple of 10 picoseconds
 706          * to match the way DIMM cycle time is calculated below.
 707          */
 708         calc_cycle_time = MULDIV64(ONE_BILLION, 100, sdram_freq);
 709
 710         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 711                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
 712                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
 713                         /*
 714                          * Byte 9, Cycle time for CAS Latency=X, is split into two nibbles:
 715                          * the higher order nibble (bits 4-7) designates the cycle time
 716                          * to a granularity of 1ns;
 717                          * the value presented by the lower order nibble (bits 0-3)
 718                          * has a granularity of .1ns and is added to the value designated
 719                          * by the higher nibble. In addition, four lines of the lower order
 720                          * nibble are assigned to support +.25,+.33, +.66 and +.75.
 721                          */
 722                          /* Convert from hex to decimal */
 723                         if ((tcyc_reg & 0x0F) == 0x0D)
 724                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
 725                         else if ((tcyc_reg & 0x0F) == 0x0C)
 726                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 66;
 727                         else if ((tcyc_reg & 0x0F) == 0x0B)
 728                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 33;
 729                         else if ((tcyc_reg & 0x0F) == 0x0A)
 730                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 25;
 731                         else
 732                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) +
 733                                         ((tcyc_reg & 0x0F)*10);
 734
 735                         if  (cycle_time > (calc_cycle_time + 10)) {
 736                                 /*
 737                                  * the provided sdram cycle_time is too small
 738                                  * for the available DIMM cycle_time.
 739                                  * The additionnal 100ps is here to accept a small incertainty.
 740                                  */
 741                                 printf("ERROR: DRAM DIMM detected with cycle_time %d ps in "
 742                                        "slot %d \n while calculated cycle time is %d ps.\n",
 743                                        (unsigned int)(cycle_time*10),
 744                                        (unsigned int)dimm_num,
 745                                        (unsigned int)(calc_cycle_time*10));
 746                                 printf("Replace the DIMM, or change DDR frequency via "
 747                                        "strapping bits.\n\n");
 748                                 hang();
 749                         }
 750                 }
 751         }
 752 }
 753
 754 /*------------------------------------------------------------------
 755  * For the memory DIMMs installed, this routine verifies two
 756  * ranks/banks maximum are availables.
 757  *-----------------------------------------------------------------*/
 758 static void check_rank_number(unsigned long *dimm_populated,
 759                               unsigned char *iic0_dimm_addr,
 760                               unsigned long num_dimm_banks)
 761 {
 762         unsigned long dimm_num;
 763         unsigned long dimm_rank;
 764         unsigned long total_rank = 0;
 765
 766         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 767                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
 768                         dimm_rank = spd_read(iic0_dimm_addr[dimm_num], 5);
 769                         if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
 770                                 dimm_rank = (dimm_rank & 0x0F) +1;
 771                         else
 772                                 dimm_rank = dimm_rank & 0x0F;
 773
 774
 775                         if (dimm_rank > MAXRANKS) {
 776                                 printf("ERROR: DRAM DIMM detected with %d ranks in "
 777                                        "slot %d is not supported.\n", dimm_rank, dimm_num);
 778                                 printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
 779                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 780                                 hang();
 781                         } else
 782                                 total_rank += dimm_rank;
 783                 }
 784                 if (total_rank > MAXRANKS) {
 785                         printf("ERROR: DRAM DIMM detected with a total of %d ranks "
 786                                "for all slots.\n", (unsigned int)total_rank);
 787                         printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
 788                         printf("Remove one of the DIMM modules.\n\n");
 789                         hang();
 790                 }
 791         }
 792 }
 793
 794 /*------------------------------------------------------------------
 795  * only support 2.5V modules.
 796  * This routine verifies this.
 797  *-----------------------------------------------------------------*/
 798 static void check_voltage_type(unsigned long *dimm_populated,
 799                                unsigned char *iic0_dimm_addr,
 800                                unsigned long num_dimm_banks)
 801 {
 802         unsigned long dimm_num;
 803         unsigned long voltage_type;
 804
 805         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 806                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
 807                         voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8);
 808                         switch (voltage_type) {
 809                         case 0x00:
 810                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 811                                 printf("This DIMM is 5.0 Volt/TTL.\n");
 812                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 813                                        (unsigned int)dimm_num);
 814                                 hang();
 815                                 break;
 816                         case 0x01:
 817                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 818                                 printf("This DIMM is LVTTL.\n");
 819                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 820                                        (unsigned int)dimm_num);
 821                                 hang();
 822                                 break;
 823                         case 0x02:
 824                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 825                                 printf("This DIMM is 1.5 Volt.\n");
 826                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 827                                        (unsigned int)dimm_num);
 828                                 hang();
 829                                 break;
 830                         case 0x03:
 831                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 832                                 printf("This DIMM is 3.3 Volt/TTL.\n");
 833                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 834                                        (unsigned int)dimm_num);
 835                                 hang();
 836                                 break;
 837                         case 0x04:
 838                                 /* 2.5 Voltage only for DDR1 */
 839                                 break;
 840                         case 0x05:
 841                                 /* 1.8 Voltage only for DDR2 */
 842                                 break;
 843                         default:
 844                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 845                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 846                                        (unsigned int)dimm_num);
 847                                 hang();
 848                                 break;
 849                         }
 850                 }
 851         }
 852 }
 853
 854 /*-----------------------------------------------------------------------------+
 855  * program_copt1.
 856  *-----------------------------------------------------------------------------*/
 857 static void program_copt1(unsigned long *dimm_populated,
 858                           unsigned char *iic0_dimm_addr,
 859                           unsigned long num_dimm_banks)
 860 {
 861         unsigned long dimm_num;
 862         unsigned long mcopt1;
 863         unsigned long ecc_enabled;
 864         unsigned long ecc = 0;
 865         unsigned long data_width = 0;
 866         unsigned long dimm_32bit;
 867         unsigned long dimm_64bit;
 868         unsigned long registered = 0;
 869         unsigned long attribute = 0;
 870         unsigned long buf0, buf1; /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
 871         unsigned long bankcount;
 872         unsigned long ddrtype;
 873         unsigned long val;
 874
 875 #ifdef CONFIG_DDR_ECC
 876         ecc_enabled = TRUE;
 877 #else
 878         ecc_enabled = FALSE;
 879 #endif
 880         dimm_32bit = FALSE;
 881         dimm_64bit = FALSE;
 882         buf0 = FALSE;
 883         buf1 = FALSE;
 884
 885         /*------------------------------------------------------------------
 886          * Set memory controller options reg 1, SDRAM_MCOPT1.
 887          *-----------------------------------------------------------------*/
 888         mfsdram(SDRAM_MCOPT1, val);
 889         mcopt1 = val & ~(SDRAM_MCOPT1_MCHK_MASK | SDRAM_MCOPT1_RDEN_MASK |
 890                          SDRAM_MCOPT1_PMU_MASK  | SDRAM_MCOPT1_DMWD_MASK |
 891                          SDRAM_MCOPT1_UIOS_MASK | SDRAM_MCOPT1_BCNT_MASK |
 892                          SDRAM_MCOPT1_DDR_TYPE_MASK | SDRAM_MCOPT1_RWOO_MASK |
 893                          SDRAM_MCOPT1_WOOO_MASK | SDRAM_MCOPT1_DCOO_MASK |
 894                          SDRAM_MCOPT1_DREF_MASK);
 895
 896         mcopt1 |= SDRAM_MCOPT1_QDEP;
 897         mcopt1 |= SDRAM_MCOPT1_PMU_OPEN;
 898         mcopt1 |= SDRAM_MCOPT1_RWOO_DISABLED;
 899         mcopt1 |= SDRAM_MCOPT1_WOOO_DISABLED;
 900         mcopt1 |= SDRAM_MCOPT1_DCOO_DISABLED;
 901         mcopt1 |= SDRAM_MCOPT1_DREF_NORMAL;
 902
 903         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 904                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
 905                         /* test ecc support */
 906                         ecc = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 11);
 907                         if (ecc != 0x02) /* ecc not supported */
 908                                 ecc_enabled = FALSE;
 909
 910                         /* test bank count */
 911                         bankcount = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 17);
 912                         if (bankcount == 0x04) /* bank count = 4 */
 913                                 mcopt1 |= SDRAM_MCOPT1_4_BANKS;
 914                         else /* bank count = 8 */
 915                                 mcopt1 |= SDRAM_MCOPT1_8_BANKS;
 916
 917                         /* test DDR type */
 918                         ddrtype = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2);
 919                         /* test for buffered/unbuffered, registered, differential clocks */
 920                         registered = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 20);
 921                         attribute = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 21);
 922
 923                         /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
 924                         if (dimm_num == 0) {
 925                                 if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
 926                                         mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
 927                                 if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
 928                                         mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
 929                                 if (registered == 1) { /* DDR2 always buffered */
 930                                         /* TODO: what about above  comments ? */
 931                                         mcopt1 |= SDRAM_MCOPT1_RDEN;
 932                                         buf0 = TRUE;
 933                                 } else {
 934                                         /* TODO: the mask 0x02 doesn't match Samsung def for byte 21. */
 935                                         if ((attribute & 0x02) == 0x00) {
 936                                                 /* buffered not supported */
 937                                                 buf0 = FALSE;
 938                                         } else {
 939                                                 mcopt1 |= SDRAM_MCOPT1_RDEN;
 940                                                 buf0 = TRUE;
 941                                         }
 942                                 }
 943                         }
 944                         else if (dimm_num == 1) {
 945                                 if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
 946                                         mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
 947                                 if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
 948                                         mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
 949                                 if (registered == 1) {
 950                                         /* DDR2 always buffered */
 951                                         mcopt1 |= SDRAM_MCOPT1_RDEN;
 952                                         buf1 = TRUE;
 953                                 } else {
 954                                         if ((attribute & 0x02) == 0x00) {
 955                                                 /* buffered not supported */
 956                                                 buf1 = FALSE;
 957                                         } else {
 958                                                 mcopt1 |= SDRAM_MCOPT1_RDEN;
 959                                                 buf1 = TRUE;
 960                                         }
 961                                 }
 962                         }
 963
 964                         /* Note that for DDR2 the byte 7 is reserved, but OK to keep code as is. */
 965                         data_width = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 6) +
 966                                 (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 7)) << 8);
 967
 968                         switch (data_width) {
 969                         case 72:
 970                         case 64:
 971                                 dimm_64bit = TRUE;
 972                                 break;
 973                         case 40:
 974                         case 32:
 975                                 dimm_32bit = TRUE;
 976                                 break;
 977                         default:
 978                                 printf("WARNING: Detected a DIMM with a data width of %d bits.\n",
 979                                        data_width);
 980                                 printf("Only DIMMs with 32 or 64 bit DDR-SDRAM widths are supported.\n");
 981                                 break;
 982                         }
 983                 }
 984         }
 985
 986         /* verify matching properties */
 987         if ((dimm_populated[0] != SDRAM_NONE) && (dimm_populated[1] != SDRAM_NONE)) {
 988                 if (buf0 != buf1) {
 989                         printf("ERROR: DIMM's buffered/unbuffered, registered, clocking don't match.\n");
 990                         hang();
 991                 }
 992         }
 993
 994         if ((dimm_64bit == TRUE) && (dimm_32bit == TRUE)) {
 995                 printf("ERROR: Cannot mix 32 bit and 64 bit DDR-SDRAM DIMMs together.\n");
 996                 hang();
 997         }
 998         else if ((dimm_64bit == TRUE) && (dimm_32bit == FALSE)) {
 999                 mcopt1 |= SDRAM_MCOPT1_DMWD_64;
1000         } else if ((dimm_64bit == FALSE) && (dimm_32bit == TRUE)) {
1001                 mcopt1 |= SDRAM_MCOPT1_DMWD_32;
1002         } else {
1003                 printf("ERROR: Please install only 32 or 64 bit DDR-SDRAM DIMMs.\n\n");
1004                 hang();
1005         }
1006
1007         if (ecc_enabled == TRUE)
1008                 mcopt1 |= SDRAM_MCOPT1_MCHK_GEN;
1009         else
1010                 mcopt1 |= SDRAM_MCOPT1_MCHK_NON;
1011
1012         mtsdram(SDRAM_MCOPT1, mcopt1);
1013 }
1014
1015 /*-----------------------------------------------------------------------------+
1016  * program_codt.
1017  *-----------------------------------------------------------------------------*/
1018 static void program_codt(unsigned long *dimm_populated,
1019                          unsigned char *iic0_dimm_addr,
1020                          unsigned long num_dimm_banks)
1021 {
1022         unsigned long codt;
1023         unsigned long modt0 = 0;
1024         unsigned long modt1 = 0;
1025         unsigned long modt2 = 0;
1026         unsigned long modt3 = 0;
1027         unsigned char dimm_num;
1028         unsigned char dimm_rank;
1029         unsigned char total_rank = 0;
1030         unsigned char total_dimm = 0;
1031         unsigned char dimm_type = 0;
1032         unsigned char firstSlot = 0;
1033
1034         /*------------------------------------------------------------------
1035          * Set the SDRAM Controller On Die Termination Register
1036          *-----------------------------------------------------------------*/
1037         mfsdram(SDRAM_CODT, codt);
1038         codt |= (SDRAM_CODT_IO_NMODE
1039                  & (~SDRAM_CODT_DQS_SINGLE_END
1040                     & ~SDRAM_CODT_CKSE_SINGLE_END
1041                     & ~SDRAM_CODT_FEEBBACK_RCV_SINGLE_END
1042                     & ~SDRAM_CODT_FEEBBACK_DRV_SINGLE_END));
1043
1044         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1045                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1046                         dimm_rank = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 5);
1047                         if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08) {
1048                                 dimm_rank = (dimm_rank & 0x0F) + 1;
1049                                 dimm_type = SDRAM_DDR2;
1050                         } else {
1051                                 dimm_rank = dimm_rank & 0x0F;
1052                                 dimm_type = SDRAM_DDR1;
1053                         }
1054
1055                         total_rank += dimm_rank;
1056                         total_dimm++;
1057                         if ((dimm_num == 0) && (total_dimm == 1))
1058                                 firstSlot = TRUE;
1059                         else
1060                                 firstSlot = FALSE;
1061                 }
1062         }
1063         if (dimm_type == SDRAM_DDR2) {
1064                 codt |= SDRAM_CODT_DQS_1_8_V_DDR2;
1065                 if ((total_dimm == 1) && (firstSlot == TRUE)) {
1066                         if (total_rank == 1) {
1067                                 codt |= CALC_ODT_R(0);
1068                                 modt0 = CALC_ODT_W(0);
1069                                 modt1 = 0x00000000;
1070                                 modt2 = 0x00000000;
1071                                 modt3 = 0x00000000;
1072                         }
1073                         if (total_rank == 2) {
1074                                 codt |= CALC_ODT_R(0) | CALC_ODT_R(1);
1075                                 modt0 = CALC_ODT_W(0);
1076                                 modt1 = CALC_ODT_W(0);
1077                                 modt2 = 0x00000000;
1078                                 modt3 = 0x00000000;
1079                         }
1080                 } else if ((total_dimm == 1) && (firstSlot != TRUE)) {
1081                         if (total_rank == 1) {
1082                                 codt |= CALC_ODT_R(2);
1083                                 modt0 = 0x00000000;
1084                                 modt1 = 0x00000000;
1085                                 modt2 = CALC_ODT_W(2);
1086                                 modt3 = 0x00000000;
1087                         }
1088                         if (total_rank == 2) {
1089                                 codt |= CALC_ODT_R(2) | CALC_ODT_R(3);
1090                                 modt0 = 0x00000000;
1091                                 modt1 = 0x00000000;
1092                                 modt2 = CALC_ODT_W(2);
1093                                 modt3 = CALC_ODT_W(2);
1094                         }
1095                 }
1096                 if (total_dimm == 2) {
1097                         if (total_rank == 2) {
1098                                 codt |= CALC_ODT_R(0) | CALC_ODT_R(2);
1099                                 modt0 = CALC_ODT_RW(2);
1100                                 modt1 = 0x00000000;
1101                                 modt2 = CALC_ODT_RW(0);
1102                                 modt3 = 0x00000000;
1103                         }
1104                         if (total_rank == 4) {
1105                                 codt |= CALC_ODT_R(0) | CALC_ODT_R(1) | CALC_ODT_R(2) | CALC_ODT_R(3);
1106                                 modt0 = CALC_ODT_RW(2);
1107                                 modt1 = 0x00000000;
1108                                 modt2 = CALC_ODT_RW(0);
1109                                 modt3 = 0x00000000;
1110                         }
1111                 }
1112         } else {
1113                 codt |= SDRAM_CODT_DQS_2_5_V_DDR1;
1114                 modt0 = 0x00000000;
1115                 modt1 = 0x00000000;
1116                 modt2 = 0x00000000;
1117                 modt3 = 0x00000000;
1118
1119                 if (total_dimm == 1) {
1120                         if (total_rank == 1)
1121                                 codt |= 0x00800000;
1122                         if (total_rank == 2)
1123                                 codt |= 0x02800000;
1124                 }
1125                 if (total_dimm == 2) {
1126                         if (total_rank == 2)
1127                                 codt |= 0x08800000;
1128                         if (total_rank == 4)
1129                                 codt |= 0x2a800000;
1130                 }
1131         }
1132
1133         debug("nb of dimm %d\n", total_dimm);
1134         debug("nb of rank %d\n", total_rank);
1135         if (total_dimm == 1)
1136                 debug("dimm in slot %d\n", firstSlot);
1137
1138         mtsdram(SDRAM_CODT, codt);
1139         mtsdram(SDRAM_MODT0, modt0);
1140         mtsdram(SDRAM_MODT1, modt1);
1141         mtsdram(SDRAM_MODT2, modt2);
1142         mtsdram(SDRAM_MODT3, modt3);
1143 }
1144
1145 /*-----------------------------------------------------------------------------+
1146  * program_initplr.
1147  *-----------------------------------------------------------------------------*/
1148 static void program_initplr(unsigned long *dimm_populated,
1149                             unsigned char *iic0_dimm_addr,
1150                             unsigned long num_dimm_banks,
1151                             ddr_cas_id_t selected_cas,
1152                             int write_recovery)
1153 {
1154         u32 cas = 0;
1155         u32 odt = 0;
1156         u32 ods = 0;
1157         u32 mr;
1158         u32 wr;
1159         u32 emr;
1160         u32 emr2;
1161         u32 emr3;
1162         int dimm_num;
1163         int total_dimm = 0;
1164
1165         /******************************************************
1166          ** Assumption: if more than one DIMM, all DIMMs are the same
1167          **             as already checked in check_memory_type
1168          ******************************************************/
1169
1170         if ((dimm_populated[0] == SDRAM_DDR1) || (dimm_populated[1] == SDRAM_DDR1)) {
1171                 mtsdram(SDRAM_INITPLR0, 0x81B80000);
1172                 mtsdram(SDRAM_INITPLR1, 0x81900400);
1173                 mtsdram(SDRAM_INITPLR2, 0x81810000);
1174                 mtsdram(SDRAM_INITPLR3, 0xff800162);
1175                 mtsdram(SDRAM_INITPLR4, 0x81900400);
1176                 mtsdram(SDRAM_INITPLR5, 0x86080000);
1177                 mtsdram(SDRAM_INITPLR6, 0x86080000);
1178                 mtsdram(SDRAM_INITPLR7, 0x81000062);
1179         } else if ((dimm_populated[0] == SDRAM_DDR2) || (dimm_populated[1] == SDRAM_DDR2)) {
1180                 switch (selected_cas) {
1181                 case DDR_CAS_3:
1182                         cas = 3 << 4;
1183                         break;
1184                 case DDR_CAS_4:
1185                         cas = 4 << 4;
1186                         break;
1187                 case DDR_CAS_5:
1188                         cas = 5 << 4;
1189                         break;
1190                 default:
1191                         printf("ERROR: ucode error on selected_cas value %d", selected_cas);
1192                         hang();
1193                         break;
1194                 }
1195
1196 #if 0
1197                 /*
1198                  * ToDo - Still a problem with the write recovery:
1199                  * On the Corsair CM2X512-5400C4 module, setting write recovery
1200                  * in the INITPLR reg to the value calculated in program_mode()
1201                  * results in not correctly working DDR2 memory (crash after
1202                  * relocation).
1203                  *
1204                  * So for now, set the write recovery to 3. This seems to work
1205                  * on the Corair module too.
1206                  *
1207                  * 2007-03-01, sr
1208                  */
1209                 switch (write_recovery) {
1210                 case 3:
1211                         wr = WRITE_RECOV_3;
1212                         break;
1213                 case 4:
1214                         wr = WRITE_RECOV_4;
1215                         break;
1216                 case 5:
1217                         wr = WRITE_RECOV_5;
1218                         break;
1219                 case 6:
1220                         wr = WRITE_RECOV_6;
1221                         break;
1222                 default:
1223                         printf("ERROR: write recovery not support (%d)", write_recovery);
1224                         hang();
1225                         break;
1226                 }
1227 #else
1228                 wr = WRITE_RECOV_3; /* test-only, see description above */
1229 #endif
1230
1231                 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++)
1232                         if (dimm_populated[dimm_num] != SDRAM_NONE)
1233                                 total_dimm++;
1234                 if (total_dimm == 1) {
1235                         odt = ODT_150_OHM;
1236                         ods = ODS_FULL;
1237                 } else if (total_dimm == 2) {
1238                         odt = ODT_75_OHM;
1239                         ods = ODS_REDUCED;
1240                 } else {
1241                         printf("ERROR: Unsupported number of DIMM's (%d)", total_dimm);
1242                         hang();
1243                 }
1244
1245                 mr = CMD_EMR | SELECT_MR | BURST_LEN_4 | wr | cas;
1246                 emr = CMD_EMR | SELECT_EMR | odt | ods;
1247                 emr2 = CMD_EMR | SELECT_EMR2;
1248                 emr3 = CMD_EMR | SELECT_EMR3;
1249                 mtsdram(SDRAM_INITPLR0,  0xB5000000 | CMD_NOP);         /* NOP */
1250                 udelay(1000);
1251                 mtsdram(SDRAM_INITPLR1,  0x82000400 | CMD_PRECHARGE);   /* precharge 8 DDR clock cycle */
1252                 mtsdram(SDRAM_INITPLR2,  0x80800000 | emr2);            /* EMR2 */
1253                 mtsdram(SDRAM_INITPLR3,  0x80800000 | emr3);            /* EMR3 */
1254                 mtsdram(SDRAM_INITPLR4,  0x80800000 | emr);             /* EMR DLL ENABLE */
1255                 mtsdram(SDRAM_INITPLR5,  0x80800000 | mr | DLL_RESET);  /* MR w/ DLL reset */
1256                 udelay(1000);
1257                 mtsdram(SDRAM_INITPLR6,  0x82000400 | CMD_PRECHARGE);   /* precharge 8 DDR clock cycle */
1258                 mtsdram(SDRAM_INITPLR7,  0x8a000000 | CMD_REFRESH);     /* Refresh  50 DDR clock cycle */
1259                 mtsdram(SDRAM_INITPLR8,  0x8a000000 | CMD_REFRESH);     /* Refresh  50 DDR clock cycle */
1260                 mtsdram(SDRAM_INITPLR9,  0x8a000000 | CMD_REFRESH);     /* Refresh  50 DDR clock cycle */
1261                 mtsdram(SDRAM_INITPLR10, 0x8a000000 | CMD_REFRESH);     /* Refresh  50 DDR clock cycle */
1262                 mtsdram(SDRAM_INITPLR11, 0x80000000 | mr);              /* MR w/o DLL reset */
1263                 mtsdram(SDRAM_INITPLR12, 0x80800380 | emr);             /* EMR OCD Default */
1264                 mtsdram(SDRAM_INITPLR13, 0x80800000 | emr);             /* EMR OCD Exit */
1265         } else {
1266                 printf("ERROR: ucode error as unknown DDR type in program_initplr");
1267                 hang();
1268         }
1269 }
1270
1271 /*------------------------------------------------------------------
1272  * This routine programs the SDRAM_MMODE register.
1273  * the selected_cas is an output parameter, that will be passed
1274  * by caller to call the above program_initplr( )
1275  *-----------------------------------------------------------------*/
1276 static void program_mode(unsigned long *dimm_populated,
1277                          unsigned char *iic0_dimm_addr,
1278                          unsigned long num_dimm_banks,
1279                          ddr_cas_id_t *selected_cas,
1280                          int *write_recovery)
1281 {
1282         unsigned long dimm_num;
1283         unsigned long sdram_ddr1;
1284         unsigned long t_wr_ns;
1285         unsigned long t_wr_clk;
1286         unsigned long cas_bit;
1287         unsigned long cas_index;
1288         unsigned long sdram_freq;
1289         unsigned long ddr_check;
1290         unsigned long mmode;
1291         unsigned long tcyc_reg;
1292         unsigned long cycle_2_0_clk;
1293         unsigned long cycle_2_5_clk;
1294         unsigned long cycle_3_0_clk;
1295         unsigned long cycle_4_0_clk;
1296         unsigned long cycle_5_0_clk;
1297         unsigned long max_2_0_tcyc_ns_x_100;
1298         unsigned long max_2_5_tcyc_ns_x_100;
1299         unsigned long max_3_0_tcyc_ns_x_100;
1300         unsigned long max_4_0_tcyc_ns_x_100;
1301         unsigned long max_5_0_tcyc_ns_x_100;
1302         unsigned long cycle_time_ns_x_100[3];
1303         PPC440_SYS_INFO board_cfg;
1304         unsigned char cas_2_0_available;
1305         unsigned char cas_2_5_available;
1306         unsigned char cas_3_0_available;
1307         unsigned char cas_4_0_available;
1308         unsigned char cas_5_0_available;
1309         unsigned long sdr_ddrpll;
1310
1311         /*------------------------------------------------------------------
1312          * Get the board configuration info.
1313          *-----------------------------------------------------------------*/
1314         get_sys_info(&board_cfg);
1315
1316         mfsdr(SDR0_DDR0, sdr_ddrpll);
1317         sdram_freq = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(sdr_ddrpll), 1);
1318
1319         /*------------------------------------------------------------------
1320          * Handle the timing.  We need to find the worst case timing of all
1321          * the dimm modules installed.
1322          *-----------------------------------------------------------------*/
1323         t_wr_ns = 0;
1324         cas_2_0_available = TRUE;
1325         cas_2_5_available = TRUE;
1326         cas_3_0_available = TRUE;
1327         cas_4_0_available = TRUE;
1328         cas_5_0_available = TRUE;
1329         max_2_0_tcyc_ns_x_100 = 10;
1330         max_2_5_tcyc_ns_x_100 = 10;
1331         max_3_0_tcyc_ns_x_100 = 10;
1332         max_4_0_tcyc_ns_x_100 = 10;
1333         max_5_0_tcyc_ns_x_100 = 10;
1334         sdram_ddr1 = TRUE;
1335
1336         /* loop through all the DIMM slots on the board */
1337         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1338                 /* If a dimm is installed in a particular slot ... */
1339                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1340                         if (dimm_populated[dimm_num] == SDRAM_DDR1)
1341                                 sdram_ddr1 = TRUE;
1342                         else
1343                                 sdram_ddr1 = FALSE;
1344
1345                         /* t_wr_ns = max(t_wr_ns, (unsigned long)dimm_spd[dimm_num][36] >> 2); */ /*  not used in this loop. */
1346                         cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18);
1347
1348                         /* For a particular DIMM, grab the three CAS values it supports */
1349                         for (cas_index = 0; cas_index < 3; cas_index++) {
1350                                 switch (cas_index) {
1351                                 case 0:
1352                                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
1353                                         break;
1354                                 case 1:
1355                                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 23);
1356                                         break;
1357                                 default:
1358                                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 25);
1359                                         break;
1360                                 }
1361
1362                                 if ((tcyc_reg & 0x0F) >= 10) {
1363                                         if ((tcyc_reg & 0x0F) == 0x0D) {
1364                                                 /* Convert from hex to decimal */
1365                                                 cycle_time_ns_x_100[cas_index] = (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
1366                                         } else {
1367                                                 printf("ERROR: SPD reported Tcyc is incorrect for DIMM "
1368                                                        "in slot %d\n", (unsigned int)dimm_num);
1369                                                 hang();
1370                                         }
1371                                 } else {
1372                                         /* Convert from hex to decimal */
1373                                         cycle_time_ns_x_100[cas_index] = (((tcyc_reg & 0xF0) >> 4) * 100) +
1374                                                 ((tcyc_reg & 0x0F)*10);
1375                                 }
1376                         }
1377
1378                         /* The rest of this routine determines if CAS 2.0, 2.5, 3.0, 4.0 and 5.0 are */
1379                         /* supported for a particular DIMM. */
1380                         cas_index = 0;
1381
1382                         if (sdram_ddr1) {
1383                                 /*
1384                                  * DDR devices use the following bitmask for CAS latency:
1385                                  *  Bit   7    6    5    4    3    2    1    0
1386                                  *       TBD  4.0  3.5  3.0  2.5  2.0  1.5  1.0
1387                                  */
1388                                 if (((cas_bit & 0x40) == 0x40) && (cas_index < 3) && (cycle_time_ns_x_100[cas_index] != 0)) {
1389                                         max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100, cycle_time_ns_x_100[cas_index]);
1390                                         cas_index++;
1391                                 } else {
1392                                         if (cas_index != 0)
1393                                                 cas_index++;
1394                                         cas_4_0_available = FALSE;
1395                                 }
1396
1397                                 if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) && (cycle_time_ns_x_100[cas_index] != 0)) {
1398                                         max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100, cycle_time_ns_x_100[cas_index]);
1399                                         cas_index++;
1400                                 } else {
1401                                         if (cas_index != 0)
1402                                                 cas_index++;
1403                                         cas_3_0_available = FALSE;
1404                                 }
1405
1406                                 if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) && (cycle_time_ns_x_100[cas_index] != 0)) {
1407                                         max_2_5_tcyc_ns_x_100 = max(max_2_5_tcyc_ns_x_100, cycle_time_ns_x_100[cas_index]);
1408                                         cas_index++;
1409                                 } else {
1410                                         if (cas_index != 0)
1411                                                 cas_index++;
1412                                         cas_2_5_available = FALSE;
1413                                 }
1414
1415                                 if (((cas_bit & 0x04) == 0x04) && (cas_index < 3) && (cycle_time_ns_x_100[cas_index] != 0)) {
1416                                         max_2_0_tcyc_ns_x_100 = max(max_2_0_tcyc_ns_x_100, cycle_time_ns_x_100[cas_index]);
1417                                         cas_index++;
1418                                 } else {
1419                                         if (cas_index != 0)
1420                                                 cas_index++;
1421                                         cas_2_0_available = FALSE;
1422                                 }
1423                         } else {
1424                                 /*
1425                                  * DDR2 devices use the following bitmask for CAS latency:
1426                                  *  Bit   7    6    5    4    3    2    1    0
1427                                  *       TBD  6.0  5.0  4.0  3.0  2.0  TBD  TBD
1428                                  */
1429                                 if (((cas_bit & 0x20) == 0x20) && (cas_index < 3) && (cycle_time_ns_x_100[cas_index] != 0)) {
1430                                         max_5_0_tcyc_ns_x_100 = max(max_5_0_tcyc_ns_x_100, cycle_time_ns_x_100[cas_index]);
1431                                         cas_index++;
1432                                 } else {
1433                                         if (cas_index != 0)
1434                                                 cas_index++;
1435                                         cas_5_0_available = FALSE;
1436                                 }
1437
1438                                 if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) && (cycle_time_ns_x_100[cas_index] != 0)) {
1439                                         max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100, cycle_time_ns_x_100[cas_index]);
1440                                         cas_index++;
1441                                 } else {
1442                                         if (cas_index != 0)
1443                                                 cas_index++;
1444                                         cas_4_0_available = FALSE;
1445                                 }
1446
1447                                 if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) && (cycle_time_ns_x_100[cas_index] != 0)) {
1448                                         max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100, cycle_time_ns_x_100[cas_index]);
1449                                         cas_index++;
1450                                 } else {
1451                                         if (cas_index != 0)
1452                                                 cas_index++;
1453                                         cas_3_0_available = FALSE;
1454                                 }
1455                         }
1456                 }
1457         }
1458
1459         /*------------------------------------------------------------------
1460          * Set the SDRAM mode, SDRAM_MMODE
1461          *-----------------------------------------------------------------*/
1462         mfsdram(SDRAM_MMODE, mmode);
1463         mmode = mmode & ~(SDRAM_MMODE_WR_MASK | SDRAM_MMODE_DCL_MASK);
1464
1465         /* add 10 here because of rounding problems */
1466         cycle_2_0_clk = MULDIV64(ONE_BILLION, 100, max_2_0_tcyc_ns_x_100) + 10;
1467         cycle_2_5_clk = MULDIV64(ONE_BILLION, 100, max_2_5_tcyc_ns_x_100) + 10;
1468         cycle_3_0_clk = MULDIV64(ONE_BILLION, 100, max_3_0_tcyc_ns_x_100) + 10;
1469         cycle_4_0_clk = MULDIV64(ONE_BILLION, 100, max_4_0_tcyc_ns_x_100) + 10;
1470         cycle_5_0_clk = MULDIV64(ONE_BILLION, 100, max_5_0_tcyc_ns_x_100) + 10;
1471
1472         if (sdram_ddr1 == TRUE) { /* DDR1 */
1473                 if ((cas_2_0_available == TRUE) && (sdram_freq <= cycle_2_0_clk)) {
1474                         mmode |= SDRAM_MMODE_DCL_DDR1_2_0_CLK;
1475                         *selected_cas = DDR_CAS_2;
1476                 } else if ((cas_2_5_available == TRUE) && (sdram_freq <= cycle_2_5_clk)) {
1477                         mmode |= SDRAM_MMODE_DCL_DDR1_2_5_CLK;
1478                         *selected_cas = DDR_CAS_2_5;
1479                 } else if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) {
1480                         mmode |= SDRAM_MMODE_DCL_DDR1_3_0_CLK;
1481                         *selected_cas = DDR_CAS_3;
1482                 } else {
1483                         printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
1484                         printf("Only DIMMs DDR1 with CAS latencies of 2.0, 2.5, and 3.0 are supported.\n");
1485                         printf("Make sure the PLB speed is within the supported range of the DIMMs.\n\n");
1486                         hang();
1487                 }
1488         } else { /* DDR2 */
1489                 if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) {
1490                         mmode |= SDRAM_MMODE_DCL_DDR2_3_0_CLK;
1491                         *selected_cas = DDR_CAS_3;
1492                 } else if ((cas_4_0_available == TRUE) && (sdram_freq <= cycle_4_0_clk)) {
1493                         mmode |= SDRAM_MMODE_DCL_DDR2_4_0_CLK;
1494                         *selected_cas = DDR_CAS_4;
1495                 } else if ((cas_5_0_available == TRUE) && (sdram_freq <= cycle_5_0_clk)) {
1496                         mmode |= SDRAM_MMODE_DCL_DDR2_5_0_CLK;
1497                         *selected_cas = DDR_CAS_5;
1498                 } else {
1499                         printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
1500                         printf("Only DIMMs DDR2 with CAS latencies of 3.0, 4.0, and 5.0 are supported.\n");
1501                         printf("Make sure the PLB speed is within the supported range of the DIMMs.\n");
1502                         printf("cas3=%d cas4=%d cas5=%d\n",
1503                                cas_3_0_available, cas_4_0_available, cas_5_0_available);
1504                         printf("sdram_freq=%d cycle3=%d cycle4=%d cycle5=%d\n\n",
1505                                sdram_freq, cycle_3_0_clk, cycle_4_0_clk, cycle_5_0_clk);
1506                         hang();
1507                 }
1508         }
1509
1510         if (sdram_ddr1 == TRUE)
1511                 mmode |= SDRAM_MMODE_WR_DDR1;
1512         else {
1513
1514                 /* loop through all the DIMM slots on the board */
1515                 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1516                         /* If a dimm is installed in a particular slot ... */
1517                         if (dimm_populated[dimm_num] != SDRAM_NONE)
1518                                 t_wr_ns = max(t_wr_ns,
1519                                               spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
1520                 }
1521
1522                 /*
1523                  * convert from nanoseconds to ddr clocks
1524                  * round up if necessary
1525                  */
1526                 t_wr_clk = MULDIV64(sdram_freq, t_wr_ns, ONE_BILLION);
1527                 ddr_check = MULDIV64(ONE_BILLION, t_wr_clk, t_wr_ns);
1528                 if (sdram_freq != ddr_check)
1529                         t_wr_clk++;
1530
1531                 switch (t_wr_clk) {
1532                 case 0:
1533                 case 1:
1534                 case 2:
1535                 case 3:
1536                         mmode |= SDRAM_MMODE_WR_DDR2_3_CYC;
1537                         break;
1538                 case 4:
1539                         mmode |= SDRAM_MMODE_WR_DDR2_4_CYC;
1540                         break;
1541                 case 5:
1542                         mmode |= SDRAM_MMODE_WR_DDR2_5_CYC;
1543                         break;
1544                 default:
1545                         mmode |= SDRAM_MMODE_WR_DDR2_6_CYC;
1546                         break;
1547                 }
1548                 *write_recovery = t_wr_clk;
1549         }
1550
1551         debug("CAS latency = %d\n", *selected_cas);
1552         debug("Write recovery = %d\n", *write_recovery);
1553
1554         mtsdram(SDRAM_MMODE, mmode);
1555 }
1556
1557 /*-----------------------------------------------------------------------------+
1558  * program_rtr.
1559  *-----------------------------------------------------------------------------*/
1560 static void program_rtr(unsigned long *dimm_populated,
1561                         unsigned char *iic0_dimm_addr,
1562                         unsigned long num_dimm_banks)
1563 {
1564         PPC440_SYS_INFO board_cfg;
1565         unsigned long max_refresh_rate;
1566         unsigned long dimm_num;
1567         unsigned long refresh_rate_type;
1568         unsigned long refresh_rate;
1569         unsigned long rint;
1570         unsigned long sdram_freq;
1571         unsigned long sdr_ddrpll;
1572         unsigned long val;
1573
1574         /*------------------------------------------------------------------
1575          * Get the board configuration info.
1576          *-----------------------------------------------------------------*/
1577         get_sys_info(&board_cfg);
1578
1579         /*------------------------------------------------------------------
1580          * Set the SDRAM Refresh Timing Register, SDRAM_RTR
1581          *-----------------------------------------------------------------*/
1582         mfsdr(SDR0_DDR0, sdr_ddrpll);
1583         sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
1584
1585         max_refresh_rate = 0;
1586         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1587                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1588
1589                         refresh_rate_type = spd_read(iic0_dimm_addr[dimm_num], 12);
1590                         refresh_rate_type &= 0x7F;
1591                         switch (refresh_rate_type) {
1592                         case 0:
1593                                 refresh_rate =  15625;
1594                                 break;
1595                         case 1:
1596                                 refresh_rate =   3906;
1597                                 break;
1598                         case 2:
1599                                 refresh_rate =   7812;
1600                                 break;
1601                         case 3:
1602                                 refresh_rate =  31250;
1603                                 break;
1604                         case 4:
1605                                 refresh_rate =  62500;
1606                                 break;
1607                         case 5:
1608                                 refresh_rate = 125000;
1609                                 break;
1610                         default:
1611                                 refresh_rate = 0;
1612                                 printf("ERROR: DIMM %d unsupported refresh rate/type.\n",
1613                                        (unsigned int)dimm_num);
1614                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
1615                                 hang();
1616                                 break;
1617                         }
1618
1619                         max_refresh_rate = max(max_refresh_rate, refresh_rate);
1620                 }
1621         }
1622
1623         rint = MULDIV64(sdram_freq, max_refresh_rate, ONE_BILLION);
1624         mfsdram(SDRAM_RTR, val);
1625         mtsdram(SDRAM_RTR, (val & ~SDRAM_RTR_RINT_MASK) |
1626                 (SDRAM_RTR_RINT_ENCODE(rint)));
1627 }
1628
1629 /*------------------------------------------------------------------
1630  * This routine programs the SDRAM_TRx registers.
1631  *-----------------------------------------------------------------*/
1632 static void program_tr(unsigned long *dimm_populated,
1633                        unsigned char *iic0_dimm_addr,
1634                        unsigned long num_dimm_banks)
1635 {
1636         unsigned long dimm_num;
1637         unsigned long sdram_ddr1;
1638         unsigned long t_rp_ns;
1639         unsigned long t_rcd_ns;
1640         unsigned long t_rrd_ns;
1641         unsigned long t_ras_ns;
1642         unsigned long t_rc_ns;
1643         unsigned long t_rfc_ns;
1644         unsigned long t_wpc_ns;
1645         unsigned long t_wtr_ns;
1646         unsigned long t_rpc_ns;
1647         unsigned long t_rp_clk;
1648         unsigned long t_rcd_clk;
1649         unsigned long t_rrd_clk;
1650         unsigned long t_ras_clk;
1651         unsigned long t_rc_clk;
1652         unsigned long t_rfc_clk;
1653         unsigned long t_wpc_clk;
1654         unsigned long t_wtr_clk;
1655         unsigned long t_rpc_clk;
1656         unsigned long sdtr1, sdtr2, sdtr3;
1657         unsigned long ddr_check;
1658         unsigned long sdram_freq;
1659         unsigned long sdr_ddrpll;
1660
1661         PPC440_SYS_INFO board_cfg;
1662
1663         /*------------------------------------------------------------------
1664          * Get the board configuration info.
1665          *-----------------------------------------------------------------*/
1666         get_sys_info(&board_cfg);
1667
1668         mfsdr(SDR0_DDR0, sdr_ddrpll);
1669         sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
1670
1671         /*------------------------------------------------------------------
1672          * Handle the timing.  We need to find the worst case timing of all
1673          * the dimm modules installed.
1674          *-----------------------------------------------------------------*/
1675         t_rp_ns = 0;
1676         t_rrd_ns = 0;
1677         t_rcd_ns = 0;
1678         t_ras_ns = 0;
1679         t_rc_ns = 0;
1680         t_rfc_ns = 0;
1681         t_wpc_ns = 0;
1682         t_wtr_ns = 0;
1683         t_rpc_ns = 0;
1684         sdram_ddr1 = TRUE;
1685
1686         /* loop through all the DIMM slots on the board */
1687         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1688                 /* If a dimm is installed in a particular slot ... */
1689                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1690                         if (dimm_populated[dimm_num] == SDRAM_DDR2)
1691                                 sdram_ddr1 = TRUE;
1692                         else
1693                                 sdram_ddr1 = FALSE;
1694
1695                         t_rcd_ns = max(t_rcd_ns, spd_read(iic0_dimm_addr[dimm_num], 29) >> 2);
1696                         t_rrd_ns = max(t_rrd_ns, spd_read(iic0_dimm_addr[dimm_num], 28) >> 2);
1697                         t_rp_ns  = max(t_rp_ns,  spd_read(iic0_dimm_addr[dimm_num], 27) >> 2);
1698                         t_ras_ns = max(t_ras_ns, spd_read(iic0_dimm_addr[dimm_num], 30));
1699                         t_rc_ns  = max(t_rc_ns,  spd_read(iic0_dimm_addr[dimm_num], 41));
1700                         t_rfc_ns = max(t_rfc_ns, spd_read(iic0_dimm_addr[dimm_num], 42));
1701                 }
1702         }
1703
1704         /*------------------------------------------------------------------
1705          * Set the SDRAM Timing Reg 1, SDRAM_TR1
1706          *-----------------------------------------------------------------*/
1707         mfsdram(SDRAM_SDTR1, sdtr1);
1708         sdtr1 &= ~(SDRAM_SDTR1_LDOF_MASK | SDRAM_SDTR1_RTW_MASK |
1709                    SDRAM_SDTR1_WTWO_MASK | SDRAM_SDTR1_RTRO_MASK);
1710
1711         /* default values */
1712         sdtr1 |= SDRAM_SDTR1_LDOF_2_CLK;
1713         sdtr1 |= SDRAM_SDTR1_RTW_2_CLK;
1714
1715         /* normal operations */
1716         sdtr1 |= SDRAM_SDTR1_WTWO_0_CLK;
1717         sdtr1 |= SDRAM_SDTR1_RTRO_1_CLK;
1718
1719         mtsdram(SDRAM_SDTR1, sdtr1);
1720
1721         /*------------------------------------------------------------------
1722          * Set the SDRAM Timing Reg 2, SDRAM_TR2
1723          *-----------------------------------------------------------------*/
1724         mfsdram(SDRAM_SDTR2, sdtr2);
1725         sdtr2 &= ~(SDRAM_SDTR2_RCD_MASK  | SDRAM_SDTR2_WTR_MASK |
1726                    SDRAM_SDTR2_XSNR_MASK | SDRAM_SDTR2_WPC_MASK |
1727                    SDRAM_SDTR2_RPC_MASK  | SDRAM_SDTR2_RP_MASK  |
1728                    SDRAM_SDTR2_RRD_MASK);
1729
1730         /*
1731          * convert t_rcd from nanoseconds to ddr clocks
1732          * round up if necessary
1733          */
1734         t_rcd_clk = MULDIV64(sdram_freq, t_rcd_ns, ONE_BILLION);
1735         ddr_check = MULDIV64(ONE_BILLION, t_rcd_clk, t_rcd_ns);
1736         if (sdram_freq != ddr_check)
1737                 t_rcd_clk++;
1738
1739         switch (t_rcd_clk) {
1740         case 0:
1741         case 1:
1742                 sdtr2 |= SDRAM_SDTR2_RCD_1_CLK;
1743                 break;
1744         case 2:
1745                 sdtr2 |= SDRAM_SDTR2_RCD_2_CLK;
1746                 break;
1747         case 3:
1748                 sdtr2 |= SDRAM_SDTR2_RCD_3_CLK;
1749                 break;
1750         case 4:
1751                 sdtr2 |= SDRAM_SDTR2_RCD_4_CLK;
1752                 break;
1753         default:
1754                 sdtr2 |= SDRAM_SDTR2_RCD_5_CLK;
1755                 break;
1756         }
1757
1758         if (sdram_ddr1 == TRUE) { /* DDR1 */
1759                 if (sdram_freq < 200000000) {
1760                         sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
1761                         sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
1762                         sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1763                 } else {
1764                         sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
1765                         sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
1766                         sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1767                 }
1768         } else { /* DDR2 */
1769                 /* loop through all the DIMM slots on the board */
1770                 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1771                         /* If a dimm is installed in a particular slot ... */
1772                         if (dimm_populated[dimm_num] != SDRAM_NONE) {
1773                                 t_wpc_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
1774                                 t_wtr_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 37) >> 2);
1775                                 t_rpc_ns = max(t_rpc_ns, spd_read(iic0_dimm_addr[dimm_num], 38) >> 2);
1776                         }
1777                 }
1778
1779                 /*
1780                  * convert from nanoseconds to ddr clocks
1781                  * round up if necessary
1782                  */
1783                 t_wpc_clk = MULDIV64(sdram_freq, t_wpc_ns, ONE_BILLION);
1784                 ddr_check = MULDIV64(ONE_BILLION, t_wpc_clk, t_wpc_ns);
1785                 if (sdram_freq != ddr_check)
1786                         t_wpc_clk++;
1787
1788                 switch (t_wpc_clk) {
1789                 case 0:
1790                 case 1:
1791                 case 2:
1792                         sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
1793                         break;
1794                 case 3:
1795                         sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
1796                         break;
1797                 case 4:
1798                         sdtr2 |= SDRAM_SDTR2_WPC_4_CLK;
1799                         break;
1800                 case 5:
1801                         sdtr2 |= SDRAM_SDTR2_WPC_5_CLK;
1802                         break;
1803                 default:
1804                         sdtr2 |= SDRAM_SDTR2_WPC_6_CLK;
1805                         break;
1806                 }
1807
1808                 /*
1809                  * convert from nanoseconds to ddr clocks
1810                  * round up if necessary
1811                  */
1812                 t_wtr_clk = MULDIV64(sdram_freq, t_wtr_ns, ONE_BILLION);
1813                 ddr_check = MULDIV64(ONE_BILLION, t_wtr_clk, t_wtr_ns);
1814                 if (sdram_freq != ddr_check)
1815                         t_wtr_clk++;
1816
1817                 switch (t_wtr_clk) {
1818                 case 0:
1819                 case 1:
1820                         sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
1821                         break;
1822                 case 2:
1823                         sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
1824                         break;
1825                 case 3:
1826                         sdtr2 |= SDRAM_SDTR2_WTR_3_CLK;
1827                         break;
1828                 default:
1829                         sdtr2 |= SDRAM_SDTR2_WTR_4_CLK;
1830                         break;
1831                 }
1832
1833                 /*
1834                  * convert from nanoseconds to ddr clocks
1835                  * round up if necessary
1836                  */
1837                 t_rpc_clk = MULDIV64(sdram_freq, t_rpc_ns, ONE_BILLION);
1838                 ddr_check = MULDIV64(ONE_BILLION, t_rpc_clk, t_rpc_ns);
1839                 if (sdram_freq != ddr_check)
1840                         t_rpc_clk++;
1841
1842                 switch (t_rpc_clk) {
1843                 case 0:
1844                 case 1:
1845                 case 2:
1846                         sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1847                         break;
1848                 case 3:
1849                         sdtr2 |= SDRAM_SDTR2_RPC_3_CLK;
1850                         break;
1851                 default:
1852                         sdtr2 |= SDRAM_SDTR2_RPC_4_CLK;
1853                         break;
1854                 }
1855         }
1856
1857         /* default value */
1858         sdtr2 |= SDRAM_SDTR2_XSNR_16_CLK;
1859
1860         /*
1861          * convert t_rrd from nanoseconds to ddr clocks
1862          * round up if necessary
1863          */
1864         t_rrd_clk = MULDIV64(sdram_freq, t_rrd_ns, ONE_BILLION);
1865         ddr_check = MULDIV64(ONE_BILLION, t_rrd_clk, t_rrd_ns);
1866         if (sdram_freq != ddr_check)
1867                 t_rrd_clk++;
1868
1869         if (t_rrd_clk == 3)
1870                 sdtr2 |= SDRAM_SDTR2_RRD_3_CLK;
1871         else
1872                 sdtr2 |= SDRAM_SDTR2_RRD_2_CLK;
1873
1874         /*
1875          * convert t_rp from nanoseconds to ddr clocks
1876          * round up if necessary
1877          */
1878         t_rp_clk = MULDIV64(sdram_freq, t_rp_ns, ONE_BILLION);
1879         ddr_check = MULDIV64(ONE_BILLION, t_rp_clk, t_rp_ns);
1880         if (sdram_freq != ddr_check)
1881                 t_rp_clk++;
1882
1883         switch (t_rp_clk) {
1884         case 0:
1885         case 1:
1886         case 2:
1887         case 3:
1888                 sdtr2 |= SDRAM_SDTR2_RP_3_CLK;
1889                 break;
1890         case 4:
1891                 sdtr2 |= SDRAM_SDTR2_RP_4_CLK;
1892                 break;
1893         case 5:
1894                 sdtr2 |= SDRAM_SDTR2_RP_5_CLK;
1895                 break;
1896         case 6:
1897                 sdtr2 |= SDRAM_SDTR2_RP_6_CLK;
1898                 break;
1899         default:
1900                 sdtr2 |= SDRAM_SDTR2_RP_7_CLK;
1901                 break;
1902         }
1903
1904         mtsdram(SDRAM_SDTR2, sdtr2);
1905
1906         /*------------------------------------------------------------------
1907          * Set the SDRAM Timing Reg 3, SDRAM_TR3
1908          *-----------------------------------------------------------------*/
1909         mfsdram(SDRAM_SDTR3, sdtr3);
1910         sdtr3 &= ~(SDRAM_SDTR3_RAS_MASK  | SDRAM_SDTR3_RC_MASK |
1911                    SDRAM_SDTR3_XCS_MASK | SDRAM_SDTR3_RFC_MASK);
1912
1913         /*
1914          * convert t_ras from nanoseconds to ddr clocks
1915          * round up if necessary
1916          */
1917         t_ras_clk = MULDIV64(sdram_freq, t_ras_ns, ONE_BILLION);
1918         ddr_check = MULDIV64(ONE_BILLION, t_ras_clk, t_ras_ns);
1919         if (sdram_freq != ddr_check)
1920                 t_ras_clk++;
1921
1922         sdtr3 |= SDRAM_SDTR3_RAS_ENCODE(t_ras_clk);
1923
1924         /*
1925          * convert t_rc from nanoseconds to ddr clocks
1926          * round up if necessary
1927          */
1928         t_rc_clk = MULDIV64(sdram_freq, t_rc_ns, ONE_BILLION);
1929         ddr_check = MULDIV64(ONE_BILLION, t_rc_clk, t_rc_ns);
1930         if (sdram_freq != ddr_check)
1931                 t_rc_clk++;
1932
1933         sdtr3 |= SDRAM_SDTR3_RC_ENCODE(t_rc_clk);
1934
1935         /* default xcs value */
1936         sdtr3 |= SDRAM_SDTR3_XCS;
1937
1938         /*
1939          * convert t_rfc from nanoseconds to ddr clocks
1940          * round up if necessary
1941          */
1942         t_rfc_clk = MULDIV64(sdram_freq, t_rfc_ns, ONE_BILLION);
1943         ddr_check = MULDIV64(ONE_BILLION, t_rfc_clk, t_rfc_ns);
1944         if (sdram_freq != ddr_check)
1945                 t_rfc_clk++;
1946
1947         sdtr3 |= SDRAM_SDTR3_RFC_ENCODE(t_rfc_clk);
1948
1949         mtsdram(SDRAM_SDTR3, sdtr3);
1950 }
1951
1952 /*-----------------------------------------------------------------------------+
1953  * program_bxcf.
1954  *-----------------------------------------------------------------------------*/
1955 static void program_bxcf(unsigned long *dimm_populated,
1956                          unsigned char *iic0_dimm_addr,
1957                          unsigned long num_dimm_banks)
1958 {
1959         unsigned long dimm_num;
1960         unsigned long num_col_addr;
1961         unsigned long num_ranks;
1962         unsigned long num_banks;
1963         unsigned long mode;
1964         unsigned long ind_rank;
1965         unsigned long ind;
1966         unsigned long ind_bank;
1967         unsigned long bank_0_populated;
1968
1969         /*------------------------------------------------------------------
1970          * Set the BxCF regs.  First, wipe out the bank config registers.
1971          *-----------------------------------------------------------------*/
1972         mtdcr(SDRAMC_CFGADDR, SDRAM_MB0CF);
1973         mtdcr(SDRAMC_CFGDATA, 0x00000000);
1974         mtdcr(SDRAMC_CFGADDR, SDRAM_MB1CF);
1975         mtdcr(SDRAMC_CFGDATA, 0x00000000);
1976         mtdcr(SDRAMC_CFGADDR, SDRAM_MB2CF);
1977         mtdcr(SDRAMC_CFGDATA, 0x00000000);
1978         mtdcr(SDRAMC_CFGADDR, SDRAM_MB3CF);
1979         mtdcr(SDRAMC_CFGDATA, 0x00000000);
1980
1981         mode = SDRAM_BXCF_M_BE_ENABLE;
1982
1983         bank_0_populated = 0;
1984
1985         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1986                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1987                         num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4);
1988                         num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
1989                         if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
1990                                 num_ranks = (num_ranks & 0x0F) +1;
1991                         else
1992                                 num_ranks = num_ranks & 0x0F;
1993
1994                         num_banks = spd_read(iic0_dimm_addr[dimm_num], 17);
1995
1996                         for (ind_bank = 0; ind_bank < 2; ind_bank++) {
1997                                 if (num_banks == 4)
1998                                         ind = 0;
1999                                 else
2000                                         ind = 5;
2001                                 switch (num_col_addr) {
2002                                 case 0x08:
2003                                         mode |= (SDRAM_BXCF_M_AM_0 + ind);
2004                                         break;
2005                                 case 0x09:
2006                                         mode |= (SDRAM_BXCF_M_AM_1 + ind);
2007                                         break;
2008                                 case 0x0A:
2009                                         mode |= (SDRAM_BXCF_M_AM_2 + ind);
2010                                         break;
2011                                 case 0x0B:
2012                                         mode |= (SDRAM_BXCF_M_AM_3 + ind);
2013                                         break;
2014                                 case 0x0C:
2015                                         mode |= (SDRAM_BXCF_M_AM_4 + ind);
2016                                         break;
2017                                 default:
2018                                         printf("DDR-SDRAM: DIMM %d BxCF configuration.\n",
2019                                                (unsigned int)dimm_num);
2020                                         printf("ERROR: Unsupported value for number of "
2021                                                "column addresses: %d.\n", (unsigned int)num_col_addr);
2022                                         printf("Replace the DIMM module with a supported DIMM.\n\n");
2023                                         hang();
2024                                 }
2025                         }
2026
2027                         if ((dimm_populated[dimm_num] != SDRAM_NONE)&& (dimm_num ==1))
2028                                 bank_0_populated = 1;
2029
2030                         for (ind_rank = 0; ind_rank < num_ranks; ind_rank++) {
2031                                 mtdcr(SDRAMC_CFGADDR, SDRAM_MB0CF + ((dimm_num + bank_0_populated + ind_rank) << 2));
2032                                 mtdcr(SDRAMC_CFGDATA, mode);
2033                         }
2034                 }
2035         }
2036 }
2037
2038 /*------------------------------------------------------------------
2039  * program memory queue.
2040  *-----------------------------------------------------------------*/
2041 static void program_memory_queue(unsigned long *dimm_populated,
2042                                  unsigned char *iic0_dimm_addr,
2043                                  unsigned long num_dimm_banks)
2044 {
2045         unsigned long dimm_num;
2046         unsigned long rank_base_addr;
2047         unsigned long rank_reg;
2048         unsigned long rank_size_bytes;
2049         unsigned long rank_size_id;
2050         unsigned long num_ranks;
2051         unsigned long baseadd_size;
2052         unsigned long i;
2053         unsigned long bank_0_populated = 0;
2054
2055         /*------------------------------------------------------------------
2056          * Reset the rank_base_address.
2057          *-----------------------------------------------------------------*/
2058         rank_reg   = SDRAM_R0BAS;
2059
2060         rank_base_addr = 0x00000000;
2061
2062         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
2063                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
2064                         num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
2065                         if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
2066                                 num_ranks = (num_ranks & 0x0F) + 1;
2067                         else
2068                                 num_ranks = num_ranks & 0x0F;
2069
2070                         rank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31);
2071
2072                         /*------------------------------------------------------------------
2073                          * Set the sizes
2074                          *-----------------------------------------------------------------*/
2075                         baseadd_size = 0;
2076                         rank_size_bytes = 4 * 1024 * 1024 * rank_size_id;
2077                         switch (rank_size_id) {
2078                         case 0x02:
2079                                 baseadd_size |= SDRAM_RXBAS_SDSZ_8;
2080                                 break;
2081                         case 0x04:
2082                                 baseadd_size |= SDRAM_RXBAS_SDSZ_16;
2083                                 break;
2084                         case 0x08:
2085                                 baseadd_size |= SDRAM_RXBAS_SDSZ_32;
2086                                 break;
2087                         case 0x10:
2088                                 baseadd_size |= SDRAM_RXBAS_SDSZ_64;
2089                                 break;
2090                         case 0x20:
2091                                 baseadd_size |= SDRAM_RXBAS_SDSZ_128;
2092                                 break;
2093                         case 0x40:
2094                                 baseadd_size |= SDRAM_RXBAS_SDSZ_256;
2095                                 break;
2096                         case 0x80:
2097                                 baseadd_size |= SDRAM_RXBAS_SDSZ_512;
2098                                 break;
2099                         default:
2100                                 printf("DDR-SDRAM: DIMM %d memory queue configuration.\n",
2101                                        (unsigned int)dimm_num);
2102                                 printf("ERROR: Unsupported value for the banksize: %d.\n",
2103                                        (unsigned int)rank_size_id);
2104                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
2105                                 hang();
2106                         }
2107
2108                         if ((dimm_populated[dimm_num] != SDRAM_NONE) && (dimm_num == 1))
2109                                 bank_0_populated = 1;
2110
2111                         for (i = 0; i < num_ranks; i++) {
2112                                 mtdcr_any(rank_reg+i+dimm_num+bank_0_populated,
2113                                           (SDRAM_RXBAS_SDBA_ENCODE(rank_base_addr) |
2114                                            baseadd_size));
2115                                 rank_base_addr += rank_size_bytes;
2116                         }
2117                 }
2118         }
2119 }
2120
2121 /*-----------------------------------------------------------------------------+
2122  * is_ecc_enabled.
2123  *-----------------------------------------------------------------------------*/
2124 static unsigned long is_ecc_enabled(void)
2125 {
2126         unsigned long dimm_num;
2127         unsigned long ecc;
2128         unsigned long val;
2129
2130         ecc = 0;
2131         /* loop through all the DIMM slots on the board */
2132         for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2133                 mfsdram(SDRAM_MCOPT1, val);
2134                 ecc = max(ecc, SDRAM_MCOPT1_MCHK_CHK_DECODE(val));
2135         }
2136
2137         return ecc;
2138 }
2139
2140 #ifdef CONFIG_DDR_ECC
2141 /*-----------------------------------------------------------------------------+
2142  * program_ecc.
2143  *-----------------------------------------------------------------------------*/
2144 static void program_ecc(unsigned long *dimm_populated,
2145                         unsigned char *iic0_dimm_addr,
2146                         unsigned long num_dimm_banks,
2147                         unsigned long tlb_word2_i_value)
2148 {
2149         unsigned long mcopt1;
2150         unsigned long mcopt2;
2151         unsigned long mcstat;
2152         unsigned long dimm_num;
2153         unsigned long ecc;
2154
2155         ecc = 0;
2156         /* loop through all the DIMM slots on the board */
2157         for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2158                 /* If a dimm is installed in a particular slot ... */
2159                 if (dimm_populated[dimm_num] != SDRAM_NONE)
2160                         ecc = max(ecc, spd_read(iic0_dimm_addr[dimm_num], 11));
2161         }
2162         if (ecc == 0)
2163                 return;
2164
2165         mfsdram(SDRAM_MCOPT1, mcopt1);
2166         mfsdram(SDRAM_MCOPT2, mcopt2);
2167
2168         if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) {
2169                 /* DDR controller must be enabled and not in self-refresh. */
2170                 mfsdram(SDRAM_MCSTAT, mcstat);
2171                 if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE)
2172                     && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT)
2173                     && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK))
2174                         == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) {
2175
2176                         program_ecc_addr(0, sdram_memsize(), tlb_word2_i_value);
2177                 }
2178         }
2179
2180         return;
2181 }
2182
2183 #ifdef CONFIG_ECC_ERROR_RESET
2184 /*
2185  * Check for ECC errors and reset board upon any error here
2186  *
2187  * On the Katmai 440SPe eval board, from time to time, the first
2188  * lword write access after DDR2 initializazion with ECC checking
2189  * enabled, leads to an ECC error. I couldn't find a configuration
2190  * without this happening. On my board with the current setup it
2191  * happens about 1 from 10 times.
2192  *
2193  * The ECC modules used for testing are:
2194  * - Kingston ValueRAM KVR667D2E5/512 (tested with 1 and 2 DIMM's)
2195  *
2196  * This has to get fixed for the Katmai and tested for the other
2197  * board (440SP/440SPe) that will eventually use this code in the
2198  * future.
2199  *
2200  * 2007-03-01, sr
2201  */
2202 static void check_ecc(void)
2203 {
2204         u32 val;
2205
2206         mfsdram(SDRAM_ECCCR, val);
2207         if (val != 0) {
2208                 printf("\nECC error: MCIF0_ECCES=%08lx MQ0_ESL=%08lx address=%08lx\n",
2209                        val, mfdcr(0x4c), mfdcr(0x4e));
2210                 printf("ECC error occured, resetting board...\n");
2211                 do_reset(NULL, 0, 0, NULL);
2212         }
2213 }
2214 #endif
2215
2216 static void wait_ddr_idle(void)
2217 {
2218         u32 val;
2219
2220         do {
2221                 mfsdram(SDRAM_MCSTAT, val);
2222         } while ((val & SDRAM_MCSTAT_IDLE_MASK) == SDRAM_MCSTAT_IDLE_NOT);
2223 }
2224
2225 /*-----------------------------------------------------------------------------+
2226  * program_ecc_addr.
2227  *-----------------------------------------------------------------------------*/
2228 static void program_ecc_addr(unsigned long start_address,
2229                              unsigned long num_bytes,
2230                              unsigned long tlb_word2_i_value)
2231 {
2232         unsigned long current_address;
2233         unsigned long end_address;
2234         unsigned long address_increment;
2235         unsigned long mcopt1;
2236         char str[] = "ECC generation...";
2237         int i;
2238
2239         current_address = start_address;
2240         mfsdram(SDRAM_MCOPT1, mcopt1);
2241         if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) {
2242                 mtsdram(SDRAM_MCOPT1,
2243                         (mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_GEN);
2244                 sync();
2245                 eieio();
2246                 wait_ddr_idle();
2247
2248                 puts(str);
2249                 if (tlb_word2_i_value == TLB_WORD2_I_ENABLE) {
2250                         /* ECC bit set method for non-cached memory */
2251                         if ((mcopt1 & SDRAM_MCOPT1_DMWD_MASK) == SDRAM_MCOPT1_DMWD_32)
2252                                 address_increment = 4;
2253                         else
2254                                 address_increment = 8;
2255                         end_address = current_address + num_bytes;
2256
2257                         while (current_address < end_address) {
2258                                 *((unsigned long *)current_address) = 0x00000000;
2259                                 current_address += address_increment;
2260                         }
2261                 } else {
2262                         /* ECC bit set method for cached memory */
2263                         dcbz_area(start_address, num_bytes);
2264                         dflush();
2265                 }
2266                 for (i=0; i<strlen(str); i++)
2267                         putc('\b');
2268
2269                 sync();
2270                 eieio();
2271                 wait_ddr_idle();
2272
2273                 /* clear ECC error repoting registers */
2274                 mtsdram(SDRAM_ECCCR, 0xffffffff);
2275                 mtdcr(0x4c, 0xffffffff);
2276
2277                 mtsdram(SDRAM_MCOPT1,
2278                         (mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_CHK_REP);
2279                 sync();
2280                 eieio();
2281                 wait_ddr_idle();
2282
2283 #ifdef CONFIG_ECC_ERROR_RESET
2284                 /*
2285                  * One write to 0 is enough to trigger this ECC error
2286                  * (see description above)
2287                  */
2288                 out_be32(0, 0x12345678);
2289                 check_ecc();
2290 #endif
2291         }
2292 }
2293 #endif
2294
2295 /*-----------------------------------------------------------------------------+
2296  * program_DQS_calibration.
2297  *-----------------------------------------------------------------------------*/
2298 static void program_DQS_calibration(unsigned long *dimm_populated,
2299                                     unsigned char *iic0_dimm_addr,
2300                                     unsigned long num_dimm_banks)
2301 {
2302         unsigned long val;
2303
2304 #ifdef HARD_CODED_DQS /* calibration test with hardvalues */
2305         mtsdram(SDRAM_RQDC, 0x80000037);
2306         mtsdram(SDRAM_RDCC, 0x40000000);
2307         mtsdram(SDRAM_RFDC, 0x000001DF);
2308
2309         test();
2310 #else
2311         /*------------------------------------------------------------------
2312          * Program RDCC register
2313          * Read sample cycle auto-update enable
2314          *-----------------------------------------------------------------*/
2315
2316         /*
2317          * Modified for the Katmai platform:  with some DIMMs, the DDR2
2318          * controller automatically selects the T2 read cycle, but this
2319          * proves unreliable.  Go ahead and force the DDR2 controller
2320          * to use the T4 sample and disable the automatic update of the
2321          * RDSS field.
2322          */
2323         mfsdram(SDRAM_RDCC, val);
2324         mtsdram(SDRAM_RDCC,
2325                 (val & ~(SDRAM_RDCC_RDSS_MASK | SDRAM_RDCC_RSAE_MASK))
2326                 | (SDRAM_RDCC_RDSS_T4 | SDRAM_RDCC_RSAE_DISABLE));
2327
2328         /*------------------------------------------------------------------
2329          * Program RQDC register
2330          * Internal DQS delay mechanism enable
2331          *-----------------------------------------------------------------*/
2332         mtsdram(SDRAM_RQDC, (SDRAM_RQDC_RQDE_ENABLE|SDRAM_RQDC_RQFD_ENCODE(0x38)));
2333
2334         /*------------------------------------------------------------------
2335          * Program RFDC register
2336          * Set Feedback Fractional Oversample
2337          * Auto-detect read sample cycle enable
2338          *-----------------------------------------------------------------*/
2339         mfsdram(SDRAM_RFDC, val);
2340         mtsdram(SDRAM_RFDC,
2341                 (val & ~(SDRAM_RFDC_ARSE_MASK | SDRAM_RFDC_RFOS_MASK |
2342                          SDRAM_RFDC_RFFD_MASK))
2343                 | (SDRAM_RFDC_ARSE_ENABLE | SDRAM_RFDC_RFOS_ENCODE(0) |
2344                    SDRAM_RFDC_RFFD_ENCODE(0)));
2345
2346         DQS_calibration_process();
2347 #endif
2348 }
2349
2350 static u32 short_mem_test(void)
2351 {
2352         u32 *membase;
2353         u32 bxcr_num;
2354         u32 bxcf;
2355         int i;
2356         int j;
2357         u32 test[NUMMEMTESTS][NUMMEMWORDS] = {
2358                 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
2359                  0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
2360                 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
2361                  0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
2362                 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
2363                  0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
2364                 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
2365                  0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
2366                 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
2367                  0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
2368                 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
2369                  0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
2370                 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
2371                  0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
2372                 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
2373                  0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
2374
2375         for (bxcr_num = 0; bxcr_num < MAXBXCF; bxcr_num++) {
2376                 mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf);
2377
2378                 /* Banks enabled */
2379                 if ((bxcf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
2380
2381                         /* Bank is enabled */
2382                         membase = (u32 *)(SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+bxcr_num)));
2383
2384                         /*------------------------------------------------------------------
2385                          * Run the short memory test.
2386                          *-----------------------------------------------------------------*/
2387                         for (i = 0; i < NUMMEMTESTS; i++) {
2388                                 for (j = 0; j < NUMMEMWORDS; j++) {
2389                                         membase[j] = test[i][j];
2390                                         ppcDcbf((u32)&(membase[j]));
2391                                 }
2392                                 sync();
2393                                 for (j = 0; j < NUMMEMWORDS; j++) {
2394                                         if (membase[j] != test[i][j]) {
2395                                                 ppcDcbf((u32)&(membase[j]));
2396                                                 break;
2397                                         }
2398                                         ppcDcbf((u32)&(membase[j]));
2399                                 }
2400                                 sync();
2401                                 if (j < NUMMEMWORDS)
2402                                         break;
2403                         }
2404                         if (i < NUMMEMTESTS)
2405                                 break;
2406                 }       /* if bank enabled */
2407         }               /* for bxcf_num */
2408
2409         return bxcr_num;
2410 }
2411
2412 #ifndef HARD_CODED_DQS
2413 /*-----------------------------------------------------------------------------+
2414  * DQS_calibration_process.
2415  *-----------------------------------------------------------------------------*/
2416 static void DQS_calibration_process(void)
2417 {
2418         unsigned long ecc_temp;
2419         unsigned long rfdc_reg;
2420         unsigned long rffd;
2421         unsigned long rqdc_reg;
2422         unsigned long rqfd;
2423         unsigned long bxcr_num;
2424         unsigned long val;
2425         long rqfd_average;
2426         long rffd_average;
2427         long max_start;
2428         long min_end;
2429         unsigned long begin_rqfd[MAXRANKS];
2430         unsigned long begin_rffd[MAXRANKS];
2431         unsigned long end_rqfd[MAXRANKS];
2432         unsigned long end_rffd[MAXRANKS];
2433         char window_found;
2434         unsigned long dlycal;
2435         unsigned long dly_val;
2436         unsigned long max_pass_length;
2437         unsigned long current_pass_length;
2438         unsigned long current_fail_length;
2439         unsigned long current_start;
2440         long max_end;
2441         unsigned char fail_found;
2442         unsigned char pass_found;
2443
2444         /*------------------------------------------------------------------
2445          * Test to determine the best read clock delay tuning bits.
2446          *
2447          * Before the DDR controller can be used, the read clock delay needs to be
2448          * set.  This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
2449          * This value cannot be hardcoded into the program because it changes
2450          * depending on the board's setup and environment.
2451          * To do this, all delay values are tested to see if they
2452          * work or not.  By doing this, you get groups of fails with groups of
2453          * passing values.  The idea is to find the start and end of a passing
2454          * window and take the center of it to use as the read clock delay.
2455          *
2456          * A failure has to be seen first so that when we hit a pass, we know
2457          * that it is truely the start of the window.  If we get passing values
2458          * to start off with, we don't know if we are at the start of the window.
2459          *
2460          * The code assumes that a failure will always be found.
2461          * If a failure is not found, there is no easy way to get the middle
2462          * of the passing window.  I guess we can pretty much pick any value
2463          * but some values will be better than others.  Since the lowest speed
2464          * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
2465          * from experimentation it is safe to say you will always have a failure.
2466          *-----------------------------------------------------------------*/
2467         mfsdram(SDRAM_MCOPT1, ecc_temp);
2468         ecc_temp &= SDRAM_MCOPT1_MCHK_MASK;
2469         mfsdram(SDRAM_MCOPT1, val);
2470         mtsdram(SDRAM_MCOPT1, (val & ~SDRAM_MCOPT1_MCHK_MASK) |
2471                 SDRAM_MCOPT1_MCHK_NON);
2472
2473         max_start = 0;
2474         min_end = 0;
2475         begin_rqfd[0] = 0;
2476         begin_rffd[0] = 0;
2477         begin_rqfd[1] = 0;
2478         begin_rffd[1] = 0;
2479         end_rqfd[0] = 0;
2480         end_rffd[0] = 0;
2481         end_rqfd[1] = 0;
2482         end_rffd[1] = 0;
2483         window_found = FALSE;
2484
2485         max_pass_length = 0;
2486         max_start = 0;
2487         max_end = 0;
2488         current_pass_length = 0;
2489         current_fail_length = 0;
2490         current_start = 0;
2491         window_found = FALSE;
2492         fail_found = FALSE;
2493         pass_found = FALSE;
2494
2495         /* first fix RQDC[RQFD] to an average of 80 degre phase shift to find RFDC[RFFD] */
2496         /* rqdc_reg = mfsdram(SDRAM_RQDC) & ~(SDRAM_RQDC_RQFD_MASK); */
2497
2498         /*
2499          * get the delay line calibration register value
2500          */
2501         mfsdram(SDRAM_DLCR, dlycal);
2502         dly_val = SDRAM_DLYCAL_DLCV_DECODE(dlycal) << 2;
2503
2504         for (rffd = 0; rffd <= SDRAM_RFDC_RFFD_MAX; rffd++) {
2505                 mfsdram(SDRAM_RFDC, rfdc_reg);
2506                 rfdc_reg &= ~(SDRAM_RFDC_RFFD_MASK);
2507
2508                 /*------------------------------------------------------------------
2509                  * Set the timing reg for the test.
2510                  *-----------------------------------------------------------------*/
2511                 mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd));
2512
2513                 /* do the small memory test */
2514                 bxcr_num = short_mem_test();
2515
2516                 /*------------------------------------------------------------------
2517                  * See if the rffd value passed.
2518                  *-----------------------------------------------------------------*/
2519                 if (bxcr_num == MAXBXCF) {
2520                         if (fail_found == TRUE) {
2521                                 pass_found = TRUE;
2522                                 if (current_pass_length == 0)
2523                                         current_start = rffd;
2524
2525                                 current_fail_length = 0;
2526                                 current_pass_length++;
2527
2528                                 if (current_pass_length > max_pass_length) {
2529                                         max_pass_length = current_pass_length;
2530                                         max_start = current_start;
2531                                         max_end = rffd;
2532                                 }
2533                         }
2534                 } else {
2535                         current_pass_length = 0;
2536                         current_fail_length++;
2537
2538                         if (current_fail_length >= (dly_val >> 2)) {
2539                                 if (fail_found == FALSE) {
2540                                         fail_found = TRUE;
2541                                 } else if (pass_found == TRUE) {
2542                                         window_found = TRUE;
2543                                         break;
2544                                 }
2545                         }
2546                 }
2547         }               /* for rffd */
2548
2549         /*------------------------------------------------------------------
2550          * Set the average RFFD value
2551          *-----------------------------------------------------------------*/
2552         rffd_average = ((max_start + max_end) >> 1);
2553
2554         if (rffd_average < 0)
2555                 rffd_average = 0;
2556
2557         if (rffd_average > SDRAM_RFDC_RFFD_MAX)
2558                 rffd_average = SDRAM_RFDC_RFFD_MAX;
2559         /* now fix RFDC[RFFD] found and find RQDC[RQFD] */
2560         mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd_average));
2561
2562         max_pass_length = 0;
2563         max_start = 0;
2564         max_end = 0;
2565         current_pass_length = 0;
2566         current_fail_length = 0;
2567         current_start = 0;
2568         window_found = FALSE;
2569         fail_found = FALSE;
2570         pass_found = FALSE;
2571
2572         for (rqfd = 0; rqfd <= SDRAM_RQDC_RQFD_MAX; rqfd++) {
2573                 mfsdram(SDRAM_RQDC, rqdc_reg);
2574                 rqdc_reg &= ~(SDRAM_RQDC_RQFD_MASK);
2575
2576                 /*------------------------------------------------------------------
2577                  * Set the timing reg for the test.
2578                  *-----------------------------------------------------------------*/
2579                 mtsdram(SDRAM_RQDC, rqdc_reg | SDRAM_RQDC_RQFD_ENCODE(rqfd));
2580
2581                 /* do the small memory test */
2582                 bxcr_num = short_mem_test();
2583
2584                 /*------------------------------------------------------------------
2585                  * See if the rffd value passed.
2586                  *-----------------------------------------------------------------*/
2587                 if (bxcr_num == MAXBXCF) {
2588                         if (fail_found == TRUE) {
2589                                 pass_found = TRUE;
2590                                 if (current_pass_length == 0)
2591                                         current_start = rqfd;
2592
2593                                 current_fail_length = 0;
2594                                 current_pass_length++;
2595
2596                                 if (current_pass_length > max_pass_length) {
2597                                         max_pass_length = current_pass_length;
2598                                         max_start = current_start;
2599                                         max_end = rqfd;
2600                                 }
2601                         }
2602                 } else {
2603                         current_pass_length = 0;
2604                         current_fail_length++;
2605
2606                         if (fail_found == FALSE) {
2607                                 fail_found = TRUE;
2608                         } else if (pass_found == TRUE) {
2609                                 window_found = TRUE;
2610                                 break;
2611                         }
2612                 }
2613         }
2614
2615         /*------------------------------------------------------------------
2616          * Make sure we found the valid read passing window.  Halt if not
2617          *-----------------------------------------------------------------*/
2618         if (window_found == FALSE) {
2619                 printf("ERROR: Cannot determine a common read delay for the "
2620                        "DIMM(s) installed.\n");
2621                 debug("%s[%d] ERROR : \n", __FUNCTION__,__LINE__);
2622                 hang();
2623         }
2624
2625         rqfd_average = ((max_start + max_end) >> 1);
2626
2627         if (rqfd_average < 0)
2628                 rqfd_average = 0;
2629
2630         if (rqfd_average > SDRAM_RQDC_RQFD_MAX)
2631                 rqfd_average = SDRAM_RQDC_RQFD_MAX;
2632
2633         /*------------------------------------------------------------------
2634          * Restore the ECC variable to what it originally was
2635          *-----------------------------------------------------------------*/
2636         mfsdram(SDRAM_MCOPT1, val);
2637         mtsdram(SDRAM_MCOPT1, (val & ~SDRAM_MCOPT1_MCHK_MASK) | ecc_temp);
2638
2639         mtsdram(SDRAM_RQDC,
2640                 (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
2641                 SDRAM_RQDC_RQFD_ENCODE(rqfd_average));
2642
2643         mfsdram(SDRAM_DLCR, val);
2644         debug("%s[%d] DLCR: 0x%08X\n", __FUNCTION__, __LINE__, val);
2645         mfsdram(SDRAM_RQDC, val);
2646         debug("%s[%d] RQDC: 0x%08X\n", __FUNCTION__, __LINE__, val);
2647         mfsdram(SDRAM_RFDC, val);
2648         debug("%s[%d] RFDC: 0x%08X\n", __FUNCTION__, __LINE__, val);
2649 }
2650 #else /* calibration test with hardvalues */
2651 /*-----------------------------------------------------------------------------+
2652  * DQS_calibration_process.
2653  *-----------------------------------------------------------------------------*/
2654 static void test(void)
2655 {
2656         unsigned long dimm_num;
2657         unsigned long ecc_temp;
2658         unsigned long i, j;
2659         unsigned long *membase;
2660         unsigned long bxcf[MAXRANKS];
2661         unsigned long val;
2662         char window_found;
2663         char begin_found[MAXDIMMS];
2664         char end_found[MAXDIMMS];
2665         char search_end[MAXDIMMS];
2666         unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = {
2667                 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
2668                  0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
2669                 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
2670                  0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
2671                 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
2672                  0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
2673                 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
2674                  0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
2675                 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
2676                  0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
2677                 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
2678                  0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
2679                 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
2680                  0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
2681                 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
2682                  0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
2683
2684         /*------------------------------------------------------------------
2685          * Test to determine the best read clock delay tuning bits.
2686          *
2687          * Before the DDR controller can be used, the read clock delay needs to be
2688          * set.  This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
2689          * This value cannot be hardcoded into the program because it changes
2690          * depending on the board's setup and environment.
2691          * To do this, all delay values are tested to see if they
2692          * work or not.  By doing this, you get groups of fails with groups of
2693          * passing values.  The idea is to find the start and end of a passing
2694          * window and take the center of it to use as the read clock delay.
2695          *
2696          * A failure has to be seen first so that when we hit a pass, we know
2697          * that it is truely the start of the window.  If we get passing values
2698          * to start off with, we don't know if we are at the start of the window.
2699          *
2700          * The code assumes that a failure will always be found.
2701          * If a failure is not found, there is no easy way to get the middle
2702          * of the passing window.  I guess we can pretty much pick any value
2703          * but some values will be better than others.  Since the lowest speed
2704          * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
2705          * from experimentation it is safe to say you will always have a failure.
2706          *-----------------------------------------------------------------*/
2707         mfsdram(SDRAM_MCOPT1, ecc_temp);
2708         ecc_temp &= SDRAM_MCOPT1_MCHK_MASK;
2709         mfsdram(SDRAM_MCOPT1, val);
2710         mtsdram(SDRAM_MCOPT1, (val & ~SDRAM_MCOPT1_MCHK_MASK) |
2711                 SDRAM_MCOPT1_MCHK_NON);
2712
2713         window_found = FALSE;
2714         begin_found[0] = FALSE;
2715         end_found[0] = FALSE;
2716         search_end[0] = FALSE;
2717         begin_found[1] = FALSE;
2718         end_found[1] = FALSE;
2719         search_end[1] = FALSE;
2720
2721         for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2722                 mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf[bxcr_num]);
2723
2724                 /* Banks enabled */
2725                 if ((bxcf[dimm_num] & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
2726
2727                         /* Bank is enabled */
2728                         membase =
2729                                 (unsigned long*)(SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+dimm_num)));
2730
2731                         /*------------------------------------------------------------------
2732                          * Run the short memory test.
2733                          *-----------------------------------------------------------------*/
2734                         for (i = 0; i < NUMMEMTESTS; i++) {
2735                                 for (j = 0; j < NUMMEMWORDS; j++) {
2736                                         membase[j] = test[i][j];
2737                                         ppcDcbf((u32)&(membase[j]));
2738                                 }
2739                                 sync();
2740                                 for (j = 0; j < NUMMEMWORDS; j++) {
2741                                         if (membase[j] != test[i][j]) {
2742                                                 ppcDcbf((u32)&(membase[j]));
2743                                                 break;
2744                                         }
2745                                         ppcDcbf((u32)&(membase[j]));
2746                                 }
2747                                 sync();
2748                                 if (j < NUMMEMWORDS)
2749                                         break;
2750                         }
2751
2752                         /*------------------------------------------------------------------
2753                          * See if the rffd value passed.
2754                          *-----------------------------------------------------------------*/
2755                         if (i < NUMMEMTESTS) {
2756                                 if ((end_found[dimm_num] == FALSE) &&
2757                                     (search_end[dimm_num] == TRUE)) {
2758                                         end_found[dimm_num] = TRUE;
2759                                 }
2760                                 if ((end_found[0] == TRUE) &&
2761                                     (end_found[1] == TRUE))
2762                                         break;
2763                         } else {
2764                                 if (begin_found[dimm_num] == FALSE) {
2765                                         begin_found[dimm_num] = TRUE;
2766                                         search_end[dimm_num] = TRUE;
2767                                 }
2768                         }
2769                 } else {
2770                         begin_found[dimm_num] = TRUE;
2771                         end_found[dimm_num] = TRUE;
2772                 }
2773         }
2774
2775         if ((begin_found[0] == TRUE) && (begin_found[1] == TRUE))
2776                 window_found = TRUE;
2777
2778         /*------------------------------------------------------------------
2779          * Make sure we found the valid read passing window.  Halt if not
2780          *-----------------------------------------------------------------*/
2781         if (window_found == FALSE) {
2782                 printf("ERROR: Cannot determine a common read delay for the "
2783                        "DIMM(s) installed.\n");
2784                 hang();
2785         }
2786
2787         /*------------------------------------------------------------------
2788          * Restore the ECC variable to what it originally was
2789          *-----------------------------------------------------------------*/
2790         mtsdram(SDRAM_MCOPT1,
2791                 (ppcMfdcr_sdram(SDRAM_MCOPT1) & ~SDRAM_MCOPT1_MCHK_MASK)
2792                 | ecc_temp);
2793 }
2794 #endif
2795
2796 #if defined(DEBUG)
2797 static void ppc440sp_sdram_register_dump(void)
2798 {
2799         unsigned int sdram_reg;
2800         unsigned int sdram_data;
2801         unsigned int dcr_data;
2802
2803         printf("\n  Register Dump:\n");
2804         sdram_reg = SDRAM_MCSTAT;
2805         mfsdram(sdram_reg, sdram_data);
2806         printf("        SDRAM_MCSTAT    = 0x%08X", sdram_data);
2807         sdram_reg = SDRAM_MCOPT1;
2808         mfsdram(sdram_reg, sdram_data);
2809         printf("        SDRAM_MCOPT1    = 0x%08X\n", sdram_data);
2810         sdram_reg = SDRAM_MCOPT2;
2811         mfsdram(sdram_reg, sdram_data);
2812         printf("        SDRAM_MCOPT2    = 0x%08X", sdram_data);
2813         sdram_reg = SDRAM_MODT0;
2814         mfsdram(sdram_reg, sdram_data);
2815         printf("        SDRAM_MODT0     = 0x%08X\n", sdram_data);
2816         sdram_reg = SDRAM_MODT1;
2817         mfsdram(sdram_reg, sdram_data);
2818         printf("        SDRAM_MODT1     = 0x%08X", sdram_data);
2819         sdram_reg = SDRAM_MODT2;
2820         mfsdram(sdram_reg, sdram_data);
2821         printf("        SDRAM_MODT2     = 0x%08X\n", sdram_data);
2822         sdram_reg = SDRAM_MODT3;
2823         mfsdram(sdram_reg, sdram_data);
2824         printf("        SDRAM_MODT3     = 0x%08X", sdram_data);
2825         sdram_reg = SDRAM_CODT;
2826         mfsdram(sdram_reg, sdram_data);
2827         printf("        SDRAM_CODT      = 0x%08X\n", sdram_data);
2828         sdram_reg = SDRAM_VVPR;
2829         mfsdram(sdram_reg, sdram_data);
2830         printf("        SDRAM_VVPR      = 0x%08X", sdram_data);
2831         sdram_reg = SDRAM_OPARS;
2832         mfsdram(sdram_reg, sdram_data);
2833         printf("        SDRAM_OPARS     = 0x%08X\n", sdram_data);
2834         /*
2835          * OPAR2 is only used as a trigger register.
2836          * No data is contained in this register, and reading or writing
2837          * to is can cause bad things to happen (hangs).  Just skip it
2838          * and report NA
2839          * sdram_reg = SDRAM_OPAR2;
2840          * mfsdram(sdram_reg, sdram_data);
2841          * printf("        SDRAM_OPAR2     = 0x%08X\n", sdram_data);
2842          */
2843         printf("        SDRAM_OPART     = N/A       ");
2844         sdram_reg = SDRAM_RTR;
2845         mfsdram(sdram_reg, sdram_data);
2846         printf("        SDRAM_RTR       = 0x%08X\n", sdram_data);
2847         sdram_reg = SDRAM_MB0CF;
2848         mfsdram(sdram_reg, sdram_data);
2849         printf("        SDRAM_MB0CF     = 0x%08X", sdram_data);
2850         sdram_reg = SDRAM_MB1CF;
2851         mfsdram(sdram_reg, sdram_data);
2852         printf("        SDRAM_MB1CF     = 0x%08X\n", sdram_data);
2853         sdram_reg = SDRAM_MB2CF;
2854         mfsdram(sdram_reg, sdram_data);
2855         printf("        SDRAM_MB2CF     = 0x%08X", sdram_data);
2856         sdram_reg = SDRAM_MB3CF;
2857         mfsdram(sdram_reg, sdram_data);
2858         printf("        SDRAM_MB3CF     = 0x%08X\n", sdram_data);
2859         sdram_reg = SDRAM_INITPLR0;
2860         mfsdram(sdram_reg, sdram_data);
2861         printf("        SDRAM_INITPLR0  = 0x%08X", sdram_data);
2862         sdram_reg = SDRAM_INITPLR1;
2863         mfsdram(sdram_reg, sdram_data);
2864         printf("        SDRAM_INITPLR1  = 0x%08X\n", sdram_data);
2865         sdram_reg = SDRAM_INITPLR2;
2866         mfsdram(sdram_reg, sdram_data);
2867         printf("        SDRAM_INITPLR2  = 0x%08X", sdram_data);
2868         sdram_reg = SDRAM_INITPLR3;
2869         mfsdram(sdram_reg, sdram_data);
2870         printf("        SDRAM_INITPLR3  = 0x%08X\n", sdram_data);
2871         sdram_reg = SDRAM_INITPLR4;
2872         mfsdram(sdram_reg, sdram_data);
2873         printf("        SDRAM_INITPLR4  = 0x%08X", sdram_data);
2874         sdram_reg = SDRAM_INITPLR5;
2875         mfsdram(sdram_reg, sdram_data);
2876         printf("        SDRAM_INITPLR5  = 0x%08X\n", sdram_data);
2877         sdram_reg = SDRAM_INITPLR6;
2878         mfsdram(sdram_reg, sdram_data);
2879         printf("        SDRAM_INITPLR6  = 0x%08X", sdram_data);
2880         sdram_reg = SDRAM_INITPLR7;
2881         mfsdram(sdram_reg, sdram_data);
2882         printf("        SDRAM_INITPLR7  = 0x%08X\n", sdram_data);
2883         sdram_reg = SDRAM_INITPLR8;
2884         mfsdram(sdram_reg, sdram_data);
2885         printf("        SDRAM_INITPLR8  = 0x%08X", sdram_data);
2886         sdram_reg = SDRAM_INITPLR9;
2887         mfsdram(sdram_reg, sdram_data);
2888         printf("        SDRAM_INITPLR9  = 0x%08X\n", sdram_data);
2889         sdram_reg = SDRAM_INITPLR10;
2890         mfsdram(sdram_reg, sdram_data);
2891         printf("        SDRAM_INITPLR10 = 0x%08X", sdram_data);
2892         sdram_reg = SDRAM_INITPLR11;
2893         mfsdram(sdram_reg, sdram_data);
2894         printf("        SDRAM_INITPLR11 = 0x%08X\n", sdram_data);
2895         sdram_reg = SDRAM_INITPLR12;
2896         mfsdram(sdram_reg, sdram_data);
2897         printf("        SDRAM_INITPLR12 = 0x%08X", sdram_data);
2898         sdram_reg = SDRAM_INITPLR13;
2899         mfsdram(sdram_reg, sdram_data);
2900         printf("        SDRAM_INITPLR13 = 0x%08X\n", sdram_data);
2901         sdram_reg = SDRAM_INITPLR14;
2902         mfsdram(sdram_reg, sdram_data);
2903         printf("        SDRAM_INITPLR14 = 0x%08X", sdram_data);
2904         sdram_reg = SDRAM_INITPLR15;
2905         mfsdram(sdram_reg, sdram_data);
2906         printf("        SDRAM_INITPLR15 = 0x%08X\n", sdram_data);
2907         sdram_reg = SDRAM_RQDC;
2908         mfsdram(sdram_reg, sdram_data);
2909         printf("        SDRAM_RQDC      = 0x%08X", sdram_data);
2910         sdram_reg = SDRAM_RFDC;
2911         mfsdram(sdram_reg, sdram_data);
2912         printf("        SDRAM_RFDC      = 0x%08X\n", sdram_data);
2913         sdram_reg = SDRAM_RDCC;
2914         mfsdram(sdram_reg, sdram_data);
2915         printf("        SDRAM_RDCC      = 0x%08X", sdram_data);
2916         sdram_reg = SDRAM_DLCR;
2917         mfsdram(sdram_reg, sdram_data);
2918         printf("        SDRAM_DLCR      = 0x%08X\n", sdram_data);
2919         sdram_reg = SDRAM_CLKTR;
2920         mfsdram(sdram_reg, sdram_data);
2921         printf("        SDRAM_CLKTR     = 0x%08X", sdram_data);
2922         sdram_reg = SDRAM_WRDTR;
2923         mfsdram(sdram_reg, sdram_data);
2924         printf("        SDRAM_WRDTR     = 0x%08X\n", sdram_data);
2925         sdram_reg = SDRAM_SDTR1;
2926         mfsdram(sdram_reg, sdram_data);
2927         printf("        SDRAM_SDTR1     = 0x%08X", sdram_data);
2928         sdram_reg = SDRAM_SDTR2;
2929         mfsdram(sdram_reg, sdram_data);
2930         printf("        SDRAM_SDTR2     = 0x%08X\n", sdram_data);
2931         sdram_reg = SDRAM_SDTR3;
2932         mfsdram(sdram_reg, sdram_data);
2933         printf("        SDRAM_SDTR3     = 0x%08X", sdram_data);
2934         sdram_reg = SDRAM_MMODE;
2935         mfsdram(sdram_reg, sdram_data);
2936         printf("        SDRAM_MMODE     = 0x%08X\n", sdram_data);
2937         sdram_reg = SDRAM_MEMODE;
2938         mfsdram(sdram_reg, sdram_data);
2939         printf("        SDRAM_MEMODE    = 0x%08X", sdram_data);
2940         sdram_reg = SDRAM_ECCCR;
2941         mfsdram(sdram_reg, sdram_data);
2942         printf("        SDRAM_ECCCR     = 0x%08X\n\n", sdram_data);
2943
2944         dcr_data = mfdcr(SDRAM_R0BAS);
2945         printf("        MQ0_B0BAS       = 0x%08X", dcr_data);
2946         dcr_data = mfdcr(SDRAM_R1BAS);
2947         printf("        MQ1_B0BAS       = 0x%08X\n", dcr_data);
2948         dcr_data = mfdcr(SDRAM_R2BAS);
2949         printf("        MQ2_B0BAS       = 0x%08X", dcr_data);
2950         dcr_data = mfdcr(SDRAM_R3BAS);
2951         printf("        MQ3_B0BAS       = 0x%08X\n", dcr_data);
2952 }
2953 #endif
2954 #endif /* CONFIG_SPD_EEPROM */