2 * Copyright (C) Procsys. All rights reserved.
3 * Author: Mushtaq Khan <mushtaq_k@procsys.com>
4 * <mushtaqk_921@yahoo.co.in>
6 * SPDX-License-Identifier: GPL-2.0+
8 * with the reference to ata_piix driver in kernel 2.4.32
12 * This file contains SATA controller and SATA drive initialization functions
20 #include <asm/byteorder.h>
26 #define DEBUG_SATA 0 /* For debug prints set DEBUG_SATA to 1 */
29 #define DRV_DECL /* For file specific declarations */
32 /* Macros realted to PCI */
33 #define PCI_SATA_BUS 0x00
34 #define PCI_SATA_DEV 0x1f
35 #define PCI_SATA_FUNC 0x02
37 #define PCI_SATA_BASE1 0x10
38 #define PCI_SATA_BASE2 0x14
39 #define PCI_SATA_BASE3 0x18
40 #define PCI_SATA_BASE4 0x1c
41 #define PCI_SATA_BASE5 0x20
45 #define PCI_DMA_CTL 0x48
47 #define PORT_PRESENT (1<<0)
48 #define PORT_ENABLED (1<<4)
51 u32 iobase1; /* Primary cmd block */
52 u32 iobase2; /* Primary ctl block */
53 u32 iobase3; /* Sec cmd block */
54 u32 iobase4; /* sec ctl block */
55 u32 iobase5; /* BMDMA*/
57 int pci_sata_init(void)
59 u32 bus = PCI_SATA_BUS;
60 u32 dev = PCI_SATA_DEV;
61 u32 fun = PCI_SATA_FUNC;
63 u8 lat = 0, pcibios_max_latency = 0xff;
64 u8 pmr; /* Port mapping reg */
65 u8 pi; /* Prgming Interface reg */
67 bdf = PCI_BDF(bus, dev, fun);
68 pci_read_config_dword(bdf, PCI_SATA_BASE1, &iobase1);
69 pci_read_config_dword(bdf, PCI_SATA_BASE2, &iobase2);
70 pci_read_config_dword(bdf, PCI_SATA_BASE3, &iobase3);
71 pci_read_config_dword(bdf, PCI_SATA_BASE4, &iobase4);
72 pci_read_config_dword(bdf, PCI_SATA_BASE5, &iobase5);
74 if ((iobase1 == 0xFFFFFFFF) || (iobase2 == 0xFFFFFFFF) ||
75 (iobase3 == 0xFFFFFFFF) || (iobase4 == 0xFFFFFFFF) ||
76 (iobase5 == 0xFFFFFFFF)) {
78 printf("error no base addr for SATA controller\n");
82 iobase1 &= 0xFFFFFFFE;
83 iobase2 &= 0xFFFFFFFE;
84 iobase3 &= 0xFFFFFFFE;
85 iobase4 &= 0xFFFFFFFE;
86 iobase5 &= 0xFFFFFFFE;
89 pci_read_config_byte(bdf, PCI_PMR, &pmr);
91 puts("combined mode not supported\n");
95 pci_read_config_byte(bdf, PCI_PI, &pi);
96 if ((pi & 0x05) != 0x05) {
97 puts("Sata is in Legacy mode\n");
100 puts("sata is in Native mode\n");
102 /* MASTER CFG AND IO CFG */
103 pci_read_config_word(bdf, PCI_COMMAND, &cmd);
104 cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_IO;
105 pci_write_config_word(bdf, PCI_COMMAND, cmd);
106 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
109 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
110 else if (lat > pcibios_max_latency)
111 lat = pcibios_max_latency;
112 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
117 int sata_bus_probe(int port_no)
122 mask = (PORT_PRESENT << port_no);
123 pci_read_config_word(bdf, PCI_PCS, &pcs);
124 orig_mask = (int) pcs & 0xff;
125 if ((orig_mask & mask) != mask)
131 int init_sata(int dev)
141 rv = pci_sata_init();
143 puts("pci initialization failed\n");
148 port[0].ioaddr.cmd_addr = iobase1;
149 port[0].ioaddr.altstatus_addr = port[0].ioaddr.ctl_addr =
150 iobase2 | ATA_PCI_CTL_OFS;
151 port[0].ioaddr.bmdma_addr = iobase5;
154 port[1].ioaddr.cmd_addr = iobase3;
155 port[1].ioaddr.altstatus_addr = port[1].ioaddr.ctl_addr =
156 iobase4 | ATA_PCI_CTL_OFS;
157 port[1].ioaddr.bmdma_addr = iobase5 + 0x8;
159 for (i = 0; i < CONFIG_SYS_SATA_MAXBUS; i++)
160 sata_port(&port[i].ioaddr);
162 for (i = 0; i < CONFIG_SYS_SATA_MAXBUS; i++) {
163 if (!(sata_bus_probe(i))) {
164 port[i].port_state = 0;
165 printf("SATA#%d port is not present\n", i);
167 printf("SATA#%d port is present\n", i);
168 if (sata_bus_softreset(i))
169 port[i].port_state = 0;
171 port[i].port_state = 1;
175 for (i = 0; i < CONFIG_SYS_SATA_MAXBUS; i++) {
178 if (port[i].port_state == 0)
180 for (j = 0; j < CONFIG_SYS_SATA_DEVS_PER_BUS; j++) {
182 set_Feature_cmd(i, j);
183 devno = i * CONFIG_SYS_SATA_DEVS_PER_BUS + j;
184 if ((sata_dev_desc[devno].lba > 0) &&
185 (sata_dev_desc[devno].blksz > 0)) {
186 dev_print(&sata_dev_desc[devno]);
187 /* initialize partition type */
188 init_part(&sata_dev_desc[devno]);
195 int reset_sata(int dev)
200 static inline u8 sata_inb(unsigned long ioaddr)
205 static inline void sata_outb(unsigned char val, unsigned long ioaddr)
210 static void output_data(struct sata_ioports *ioaddr, ulong * sect_buf,
213 outsw(ioaddr->data_addr, sect_buf, words << 1);
216 static int input_data(struct sata_ioports *ioaddr, ulong * sect_buf, int words)
218 insw(ioaddr->data_addr, sect_buf, words << 1);
222 static void sata_cpy(unsigned char *dst, unsigned char *src, unsigned int len)
224 unsigned char *end, *last;
229 /* reserve space for '\0' */
233 /* skip leading white space */
234 while ((*src) && (src < end) && (*src == ' '))
237 /* copy string, omitting trailing white space */
238 while ((*src) && (src < end)) {
247 int sata_bus_softreset(int num)
249 u8 dev = 0, status = 0, i;
251 port[num].dev_mask = 0;
253 for (i = 0; i < CONFIG_SYS_SATA_DEVS_PER_BUS; i++) {
254 if (!(sata_devchk(&port[num].ioaddr, i))) {
255 debug("dev_chk failed for dev#%d\n", i);
257 port[num].dev_mask |= (1 << i);
258 debug("dev_chk passed for dev#%d\n", i);
262 if (!(port[num].dev_mask)) {
263 printf("no devices on port%d\n", num);
267 dev_select(&port[num].ioaddr, dev);
269 port[num].ctl_reg = 0x08; /* Default value of control reg */
270 sata_outb(port[num].ctl_reg, port[num].ioaddr.ctl_addr);
272 sata_outb(port[num].ctl_reg | ATA_SRST, port[num].ioaddr.ctl_addr);
274 sata_outb(port[num].ctl_reg, port[num].ioaddr.ctl_addr);
277 * spec mandates ">= 2ms" before checking status.
278 * We wait 150ms, because that was the magic delay used for
279 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
280 * between when the ATA command register is written, and then
281 * status is checked. Because waiting for "a while" before
282 * checking status is fine, post SRST, we perform this magic
283 * delay here as well.
286 status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 300);
287 while ((status & ATA_BUSY)) {
289 status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 3);
292 if (status & ATA_BUSY)
293 printf("ata%u is slow to respond,plz be patient\n", num);
295 while ((status & ATA_BUSY)) {
297 status = sata_chk_status(&port[num].ioaddr);
300 if (status & ATA_BUSY) {
301 printf("ata%u failed to respond : bus reset failed\n", num);
307 void sata_identify(int num, int dev)
309 u8 cmd = 0, status = 0;
310 u8 devno = num * CONFIG_SYS_SATA_DEVS_PER_BUS + dev;
311 u16 iobuf[ATA_SECT_SIZE];
315 memset(iobuf, 0, sizeof(iobuf));
316 hd_driveid_t *iop = (hd_driveid_t *) iobuf;
323 if (!(port[num].dev_mask & mask)) {
324 printf("dev%d is not present on port#%d\n", dev, num);
328 printf("port=%d dev=%d\n", num, dev);
330 dev_select(&port[num].ioaddr, dev);
333 cmd = ATA_CMD_IDENT; /* Device Identify Command */
334 sata_outb(cmd, port[num].ioaddr.command_addr);
335 sata_inb(port[num].ioaddr.altstatus_addr);
338 status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 1000);
339 if (status & ATA_ERR) {
340 puts("\ndevice not responding\n");
341 port[num].dev_mask &= ~mask;
345 input_data(&port[num].ioaddr, (ulong *) iobuf, ATA_SECTORWORDS);
347 debug("\nata%u: dev %u cfg 49:%04x 82:%04x 83:%04x 84:%04x85:%04x"
348 "86:%04x" "87:%04x 88:%04x\n", num, dev, iobuf[49],
349 iobuf[82], iobuf[83], iobuf[84], iobuf[85], iobuf[86],
350 iobuf[87], iobuf[88]);
352 /* we require LBA and DMA support (bits 8 & 9 of word 49) */
353 if (!ata_id_has_dma(iobuf) || !ata_id_has_lba(iobuf))
354 debug("ata%u: no dma/lba\n", num);
357 if (ata_id_has_lba48(iobuf))
358 n_sectors = ata_id_u64(iobuf, 100);
360 n_sectors = ata_id_u32(iobuf, 60);
361 debug("no. of sectors %u\n", ata_id_u64(iobuf, 100));
362 debug("no. of sectors %u\n", ata_id_u32(iobuf, 60));
364 if (n_sectors == 0) {
365 port[num].dev_mask &= ~mask;
369 sata_cpy((unsigned char *)sata_dev_desc[devno].revision, iop->fw_rev,
370 sizeof(sata_dev_desc[devno].revision));
371 sata_cpy((unsigned char *)sata_dev_desc[devno].vendor, iop->model,
372 sizeof(sata_dev_desc[devno].vendor));
373 sata_cpy((unsigned char *)sata_dev_desc[devno].product, iop->serial_no,
374 sizeof(sata_dev_desc[devno].product));
375 strswab(sata_dev_desc[devno].revision);
376 strswab(sata_dev_desc[devno].vendor);
378 if ((iop->config & 0x0080) == 0x0080)
379 sata_dev_desc[devno].removable = 1;
381 sata_dev_desc[devno].removable = 0;
383 sata_dev_desc[devno].lba = iop->lba_capacity;
384 debug("lba=0x%x", sata_dev_desc[devno].lba);
387 if (iop->command_set_2 & 0x0400) {
388 sata_dev_desc[devno].lba48 = 1;
389 lba = (unsigned long long) iop->lba48_capacity[0] |
390 ((unsigned long long) iop->lba48_capacity[1] << 16) |
391 ((unsigned long long) iop->lba48_capacity[2] << 32) |
392 ((unsigned long long) iop->lba48_capacity[3] << 48);
394 sata_dev_desc[devno].lba48 = 0;
399 sata_dev_desc[devno].type = DEV_TYPE_HARDDISK;
400 sata_dev_desc[devno].blksz = ATA_BLOCKSIZE;
401 sata_dev_desc[devno].log2blksz = LOG2(sata_dev_desc[devno].blksz);
402 sata_dev_desc[devno].lun = 0; /* just to fill something in... */
405 void set_Feature_cmd(int num, int dev)
407 u8 mask = 0x00, status = 0;
414 if (!(port[num].dev_mask & mask)) {
415 debug("dev%d is not present on port#%d\n", dev, num);
419 dev_select(&port[num].ioaddr, dev);
421 sata_outb(SETFEATURES_XFER, port[num].ioaddr.feature_addr);
422 sata_outb(XFER_PIO_4, port[num].ioaddr.nsect_addr);
423 sata_outb(0, port[num].ioaddr.lbal_addr);
424 sata_outb(0, port[num].ioaddr.lbam_addr);
425 sata_outb(0, port[num].ioaddr.lbah_addr);
427 sata_outb(ATA_DEVICE_OBS, port[num].ioaddr.device_addr);
428 sata_outb(ATA_CMD_SETF, port[num].ioaddr.command_addr);
433 status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 5000);
434 if ((status & (ATA_STAT_BUSY | ATA_STAT_ERR))) {
435 printf("Error : status 0x%02x\n", status);
436 port[num].dev_mask &= ~mask;
440 void sata_port(struct sata_ioports *ioport)
442 ioport->data_addr = ioport->cmd_addr + ATA_REG_DATA;
443 ioport->error_addr = ioport->cmd_addr + ATA_REG_ERR;
444 ioport->feature_addr = ioport->cmd_addr + ATA_REG_FEATURE;
445 ioport->nsect_addr = ioport->cmd_addr + ATA_REG_NSECT;
446 ioport->lbal_addr = ioport->cmd_addr + ATA_REG_LBAL;
447 ioport->lbam_addr = ioport->cmd_addr + ATA_REG_LBAM;
448 ioport->lbah_addr = ioport->cmd_addr + ATA_REG_LBAH;
449 ioport->device_addr = ioport->cmd_addr + ATA_REG_DEVICE;
450 ioport->status_addr = ioport->cmd_addr + ATA_REG_STATUS;
451 ioport->command_addr = ioport->cmd_addr + ATA_REG_CMD;
454 int sata_devchk(struct sata_ioports *ioaddr, int dev)
458 dev_select(ioaddr, dev);
460 sata_outb(0x55, ioaddr->nsect_addr);
461 sata_outb(0xaa, ioaddr->lbal_addr);
463 sata_outb(0xaa, ioaddr->nsect_addr);
464 sata_outb(0x55, ioaddr->lbal_addr);
466 sata_outb(0x55, ioaddr->nsect_addr);
467 sata_outb(0xaa, ioaddr->lbal_addr);
469 nsect = sata_inb(ioaddr->nsect_addr);
470 lbal = sata_inb(ioaddr->lbal_addr);
472 if ((nsect == 0x55) && (lbal == 0xaa))
473 return 1; /* we found a device */
475 return 0; /* nothing found */
478 void dev_select(struct sata_ioports *ioaddr, int dev)
483 tmp = ATA_DEVICE_OBS;
485 tmp = ATA_DEVICE_OBS | ATA_DEV1;
487 sata_outb(tmp, ioaddr->device_addr);
488 sata_inb(ioaddr->altstatus_addr);
492 u8 sata_busy_wait(struct sata_ioports *ioaddr, int bits, unsigned int max)
498 status = sata_chk_status(ioaddr);
500 } while ((status & bits) && (max > 0));
505 u8 sata_chk_status(struct sata_ioports *ioaddr)
507 return sata_inb(ioaddr->status_addr);
511 ulong sata_read(int device, ulong blknr, lbaint_t blkcnt, void *buff)
513 ulong n = 0, *buffer = (ulong *)buff;
514 u8 dev = 0, num = 0, mask = 0, status = 0;
517 unsigned char lba48 = 0;
519 if (blknr & 0x0000fffff0000000) {
520 if (!sata_dev_desc[devno].lba48) {
521 printf("Drive doesn't support 48-bit addressing\n");
524 /* more than 28 bits used, use 48bit mode */
529 num = device / CONFIG_SYS_SATA_DEVS_PER_BUS;
530 /* dev on the port */
531 if (device >= CONFIG_SYS_SATA_DEVS_PER_BUS)
532 dev = device - CONFIG_SYS_SATA_DEVS_PER_BUS;
541 if (!(port[num].dev_mask & mask)) {
542 printf("dev%d is not present on port#%d\n", dev, num);
547 dev_select(&port[num].ioaddr, dev);
549 status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 500);
550 if (status & ATA_BUSY) {
551 printf("ata%u failed to respond\n", port[num].port_no);
554 while (blkcnt-- > 0) {
555 status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 500);
556 if (status & ATA_BUSY) {
557 printf("ata%u failed to respond\n", 0);
562 /* write high bits */
563 sata_outb(0, port[num].ioaddr.nsect_addr);
564 sata_outb((blknr >> 24) & 0xFF,
565 port[num].ioaddr.lbal_addr);
566 sata_outb((blknr >> 32) & 0xFF,
567 port[num].ioaddr.lbam_addr);
568 sata_outb((blknr >> 40) & 0xFF,
569 port[num].ioaddr.lbah_addr);
572 sata_outb(1, port[num].ioaddr.nsect_addr);
573 sata_outb(((blknr) >> 0) & 0xFF,
574 port[num].ioaddr.lbal_addr);
575 sata_outb((blknr >> 8) & 0xFF, port[num].ioaddr.lbam_addr);
576 sata_outb((blknr >> 16) & 0xFF, port[num].ioaddr.lbah_addr);
580 sata_outb(ATA_LBA, port[num].ioaddr.device_addr);
581 sata_outb(ATA_CMD_READ_EXT,
582 port[num].ioaddr.command_addr);
586 sata_outb(ATA_LBA | ((blknr >> 24) & 0xF),
587 port[num].ioaddr.device_addr);
588 sata_outb(ATA_CMD_READ,
589 port[num].ioaddr.command_addr);
593 /* may take up to 4 sec */
594 status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 4000);
596 if ((status & (ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR))
600 printf("Error no DRQ dev %d blk %ld: sts 0x%02x\n",
601 device, (ulong) blknr, status);
602 err = sata_inb(port[num].ioaddr.error_addr);
603 printf("Error reg = 0x%x\n", err);
606 input_data(&port[num].ioaddr, buffer, ATA_SECTORWORDS);
607 sata_inb(port[num].ioaddr.altstatus_addr);
612 buffer += ATA_SECTORWORDS;
617 ulong sata_write(int device, ulong blknr, lbaint_t blkcnt, const void *buff)
619 ulong n = 0, *buffer = (ulong *)buff;
620 unsigned char status = 0, num = 0, dev = 0, mask = 0;
623 unsigned char lba48 = 0;
625 if (blknr & 0x0000fffff0000000) {
626 if (!sata_dev_desc[devno].lba48) {
627 printf("Drive doesn't support 48-bit addressing\n");
630 /* more than 28 bits used, use 48bit mode */
635 num = device / CONFIG_SYS_SATA_DEVS_PER_BUS;
636 /* dev on the Port */
637 if (device >= CONFIG_SYS_SATA_DEVS_PER_BUS)
638 dev = device - CONFIG_SYS_SATA_DEVS_PER_BUS;
648 dev_select(&port[num].ioaddr, dev);
650 status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 500);
651 if (status & ATA_BUSY) {
652 printf("ata%u failed to respond\n", port[num].port_no);
656 while (blkcnt-- > 0) {
657 status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 500);
658 if (status & ATA_BUSY) {
659 printf("ata%u failed to respond\n",
665 /* write high bits */
666 sata_outb(0, port[num].ioaddr.nsect_addr);
667 sata_outb((blknr >> 24) & 0xFF,
668 port[num].ioaddr.lbal_addr);
669 sata_outb((blknr >> 32) & 0xFF,
670 port[num].ioaddr.lbam_addr);
671 sata_outb((blknr >> 40) & 0xFF,
672 port[num].ioaddr.lbah_addr);
675 sata_outb(1, port[num].ioaddr.nsect_addr);
676 sata_outb((blknr >> 0) & 0xFF, port[num].ioaddr.lbal_addr);
677 sata_outb((blknr >> 8) & 0xFF, port[num].ioaddr.lbam_addr);
678 sata_outb((blknr >> 16) & 0xFF, port[num].ioaddr.lbah_addr);
681 sata_outb(ATA_LBA, port[num].ioaddr.device_addr);
682 sata_outb(ATA_CMD_WRITE_EXT,
683 port[num].ioaddr.command_addr);
687 sata_outb(ATA_LBA | ((blknr >> 24) & 0xF),
688 port[num].ioaddr.device_addr);
689 sata_outb(ATA_CMD_WRITE,
690 port[num].ioaddr.command_addr);
694 /* may take up to 4 sec */
695 status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 4000);
696 if ((status & (ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR))
698 printf("Error no DRQ dev %d blk %ld: sts 0x%02x\n",
699 device, (ulong) blknr, status);
703 output_data(&port[num].ioaddr, buffer, ATA_SECTORWORDS);
704 sata_inb(port[num].ioaddr.altstatus_addr);
709 buffer += ATA_SECTORWORDS;
714 int scan_sata(int dev)