2 * TI Clock driver internal definitions
4 * Copyright (C) 2014 Texas Instruments, Inc
5 * Tero Kristo (t-kristo@ti.com)
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 #ifndef __DRIVERS_CLK_TI_CLOCK__
17 #define __DRIVERS_CLK_TI_CLOCK__
30 #define CLKF_INDEX_POWER_OF_TWO (1 << 0)
31 #define CLKF_INDEX_STARTS_AT_ONE (1 << 1)
32 #define CLKF_SET_RATE_PARENT (1 << 2)
33 #define CLKF_OMAP3 (1 << 3)
34 #define CLKF_AM35XX (1 << 4)
37 #define CLKF_SET_BIT_TO_DISABLE (1 << 5)
38 #define CLKF_INTERFACE (1 << 6)
39 #define CLKF_SSI (1 << 7)
40 #define CLKF_DSS (1 << 8)
41 #define CLKF_HSOTGUSB (1 << 9)
42 #define CLKF_WAIT (1 << 10)
43 #define CLKF_NO_WAIT (1 << 11)
44 #define CLKF_HSDIV (1 << 12)
45 #define CLKF_CLKDM (1 << 13)
48 #define CLKF_LOW_POWER_STOP (1 << 5)
49 #define CLKF_LOCK (1 << 6)
50 #define CLKF_LOW_POWER_BYPASS (1 << 7)
51 #define CLKF_PER (1 << 8)
52 #define CLKF_CORE (1 << 9)
53 #define CLKF_J_TYPE (1 << 10)
55 #define CLK(dev, con, ck) \
66 const char *clkdm_name;
76 struct list_head link;
93 struct ti_clk_divider {
104 struct ti_clk_fixed_factor {
119 struct ti_clk_composite {
120 struct ti_clk_divider *divider;
121 struct ti_clk_mux *mux;
122 struct ti_clk_gate *gate;
126 struct ti_clk_clkdm_gate {
138 const char **parents;
157 struct clk *ti_clk_register_gate(struct ti_clk *setup);
158 struct clk *ti_clk_register_interface(struct ti_clk *setup);
159 struct clk *ti_clk_register_mux(struct ti_clk *setup);
160 struct clk *ti_clk_register_divider(struct ti_clk *setup);
161 struct clk *ti_clk_register_composite(struct ti_clk *setup);
162 struct clk *ti_clk_register_dpll(struct ti_clk *setup);
164 struct clk_hw *ti_clk_build_component_div(struct ti_clk_divider *setup);
165 struct clk_hw *ti_clk_build_component_gate(struct ti_clk_gate *setup);
166 struct clk_hw *ti_clk_build_component_mux(struct ti_clk_mux *setup);
168 void ti_clk_patch_legacy_clks(struct ti_clk **patch);
169 struct clk *ti_clk_register_clk(struct ti_clk *setup);
170 int ti_clk_register_legacy_clks(struct ti_clk_alias *clks);
172 void omap2_init_clk_hw_omap_clocks(struct clk *clk);
173 int of_ti_clk_autoidle_setup(struct device_node *node);
174 void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
176 extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
177 extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
178 extern const struct clk_hw_omap_ops clkhwops_iclk;
179 extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
181 u8 omap2_init_dpll_parent(struct clk_hw *hw);
182 int omap3_noncore_dpll_enable(struct clk_hw *hw);
183 void omap3_noncore_dpll_disable(struct clk_hw *hw);
184 int omap3_noncore_dpll_set_parent(struct clk_hw *hw, u8 index);
185 int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
186 unsigned long parent_rate);
187 int omap3_noncore_dpll_set_rate_and_parent(struct clk_hw *hw,
189 unsigned long parent_rate,
191 long omap3_noncore_dpll_determine_rate(struct clk_hw *hw,
193 unsigned long min_rate,
194 unsigned long max_rate,
195 unsigned long *best_parent_rate,
196 struct clk_hw **best_parent_clk);
197 long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
198 unsigned long *parent_rate);
199 unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
200 unsigned long parent_rate);
202 unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate);
203 int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
204 unsigned long parent_rate);
205 int omap3_dpll4_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
206 unsigned long parent_rate, u8 index);
207 void omap3_clk_lock_dpll5(void);
209 unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
210 unsigned long parent_rate);
211 long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
212 unsigned long target_rate,
213 unsigned long *parent_rate);
214 long omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw,
216 unsigned long min_rate,
217 unsigned long max_rate,
218 unsigned long *best_parent_rate,
219 struct clk_hw **best_parent_clk);