1 /* linux/arch/arm/mach-exynos4/mct.c
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * EXYNOS4 MCT(Multi-Core Timer) support
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/sched.h>
14 #include <linux/interrupt.h>
15 #include <linux/irq.h>
16 #include <linux/err.h>
17 #include <linux/clk.h>
18 #include <linux/clockchips.h>
19 #include <linux/cpu.h>
20 #include <linux/platform_device.h>
21 #include <linux/delay.h>
22 #include <linux/percpu.h>
24 #include <linux/of_irq.h>
25 #include <linux/of_address.h>
26 #include <linux/clocksource.h>
28 #include <asm/mach/time.h>
30 #define EXYNOS4_MCTREG(x) (x)
31 #define EXYNOS4_MCT_G_CNT_L EXYNOS4_MCTREG(0x100)
32 #define EXYNOS4_MCT_G_CNT_U EXYNOS4_MCTREG(0x104)
33 #define EXYNOS4_MCT_G_CNT_WSTAT EXYNOS4_MCTREG(0x110)
34 #define EXYNOS4_MCT_G_COMP0_L EXYNOS4_MCTREG(0x200)
35 #define EXYNOS4_MCT_G_COMP0_U EXYNOS4_MCTREG(0x204)
36 #define EXYNOS4_MCT_G_COMP0_ADD_INCR EXYNOS4_MCTREG(0x208)
37 #define EXYNOS4_MCT_G_TCON EXYNOS4_MCTREG(0x240)
38 #define EXYNOS4_MCT_G_INT_CSTAT EXYNOS4_MCTREG(0x244)
39 #define EXYNOS4_MCT_G_INT_ENB EXYNOS4_MCTREG(0x248)
40 #define EXYNOS4_MCT_G_WSTAT EXYNOS4_MCTREG(0x24C)
41 #define _EXYNOS4_MCT_L_BASE EXYNOS4_MCTREG(0x300)
42 #define EXYNOS4_MCT_L_BASE(x) (_EXYNOS4_MCT_L_BASE + (0x100 * x))
43 #define EXYNOS4_MCT_L_MASK (0xffffff00)
45 #define MCT_L_TCNTB_OFFSET (0x00)
46 #define MCT_L_ICNTB_OFFSET (0x08)
47 #define MCT_L_TCON_OFFSET (0x20)
48 #define MCT_L_INT_CSTAT_OFFSET (0x30)
49 #define MCT_L_INT_ENB_OFFSET (0x34)
50 #define MCT_L_WSTAT_OFFSET (0x40)
51 #define MCT_G_TCON_START (1 << 8)
52 #define MCT_G_TCON_COMP0_AUTO_INC (1 << 1)
53 #define MCT_G_TCON_COMP0_ENABLE (1 << 0)
54 #define MCT_L_TCON_INTERVAL_MODE (1 << 2)
55 #define MCT_L_TCON_INT_START (1 << 1)
56 #define MCT_L_TCON_TIMER_START (1 << 0)
58 #define TICK_BASE_CNT 1
77 static void __iomem *reg_base;
78 static unsigned long clk_rate;
79 static unsigned int mct_int_type;
80 static int mct_irqs[MCT_NR_IRQS];
82 struct mct_clock_event_device {
83 struct clock_event_device evt;
88 static void exynos4_mct_write(unsigned int value, unsigned long offset)
90 unsigned long stat_addr;
94 __raw_writel(value, reg_base + offset);
96 if (likely(offset >= EXYNOS4_MCT_L_BASE(0))) {
97 stat_addr = (offset & ~EXYNOS4_MCT_L_MASK) + MCT_L_WSTAT_OFFSET;
98 switch (offset & EXYNOS4_MCT_L_MASK) {
99 case MCT_L_TCON_OFFSET:
100 mask = 1 << 3; /* L_TCON write status */
102 case MCT_L_ICNTB_OFFSET:
103 mask = 1 << 1; /* L_ICNTB write status */
105 case MCT_L_TCNTB_OFFSET:
106 mask = 1 << 0; /* L_TCNTB write status */
113 case EXYNOS4_MCT_G_TCON:
114 stat_addr = EXYNOS4_MCT_G_WSTAT;
115 mask = 1 << 16; /* G_TCON write status */
117 case EXYNOS4_MCT_G_COMP0_L:
118 stat_addr = EXYNOS4_MCT_G_WSTAT;
119 mask = 1 << 0; /* G_COMP0_L write status */
121 case EXYNOS4_MCT_G_COMP0_U:
122 stat_addr = EXYNOS4_MCT_G_WSTAT;
123 mask = 1 << 1; /* G_COMP0_U write status */
125 case EXYNOS4_MCT_G_COMP0_ADD_INCR:
126 stat_addr = EXYNOS4_MCT_G_WSTAT;
127 mask = 1 << 2; /* G_COMP0_ADD_INCR w status */
129 case EXYNOS4_MCT_G_CNT_L:
130 stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
131 mask = 1 << 0; /* G_CNT_L write status */
133 case EXYNOS4_MCT_G_CNT_U:
134 stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
135 mask = 1 << 1; /* G_CNT_U write status */
142 /* Wait maximum 1 ms until written values are applied */
143 for (i = 0; i < loops_per_jiffy / 1000 * HZ; i++)
144 if (__raw_readl(reg_base + stat_addr) & mask) {
145 __raw_writel(mask, reg_base + stat_addr);
149 panic("MCT hangs after writing %d (offset:0x%lx)\n", value, offset);
152 /* Clocksource handling */
153 static void exynos4_mct_frc_start(u32 hi, u32 lo)
157 exynos4_mct_write(lo, EXYNOS4_MCT_G_CNT_L);
158 exynos4_mct_write(hi, EXYNOS4_MCT_G_CNT_U);
160 reg = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
161 reg |= MCT_G_TCON_START;
162 exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON);
165 static cycle_t exynos4_frc_read(struct clocksource *cs)
168 u32 hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);
172 lo = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_L);
173 hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);
176 return ((cycle_t)hi << 32) | lo;
179 static void exynos4_frc_resume(struct clocksource *cs)
181 exynos4_mct_frc_start(0, 0);
184 struct clocksource mct_frc = {
187 .read = exynos4_frc_read,
188 .mask = CLOCKSOURCE_MASK(64),
189 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
190 .resume = exynos4_frc_resume,
193 static void __init exynos4_clocksource_init(void)
195 exynos4_mct_frc_start(0, 0);
197 if (clocksource_register_hz(&mct_frc, clk_rate))
198 panic("%s: can't register clocksource\n", mct_frc.name);
201 static void exynos4_mct_comp0_stop(void)
205 tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
206 tcon &= ~(MCT_G_TCON_COMP0_ENABLE | MCT_G_TCON_COMP0_AUTO_INC);
208 exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON);
209 exynos4_mct_write(0, EXYNOS4_MCT_G_INT_ENB);
212 static void exynos4_mct_comp0_start(enum clock_event_mode mode,
213 unsigned long cycles)
218 tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
220 if (mode == CLOCK_EVT_MODE_PERIODIC) {
221 tcon |= MCT_G_TCON_COMP0_AUTO_INC;
222 exynos4_mct_write(cycles, EXYNOS4_MCT_G_COMP0_ADD_INCR);
225 comp_cycle = exynos4_frc_read(&mct_frc) + cycles;
226 exynos4_mct_write((u32)comp_cycle, EXYNOS4_MCT_G_COMP0_L);
227 exynos4_mct_write((u32)(comp_cycle >> 32), EXYNOS4_MCT_G_COMP0_U);
229 exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_ENB);
231 tcon |= MCT_G_TCON_COMP0_ENABLE;
232 exynos4_mct_write(tcon , EXYNOS4_MCT_G_TCON);
235 static int exynos4_comp_set_next_event(unsigned long cycles,
236 struct clock_event_device *evt)
238 exynos4_mct_comp0_start(evt->mode, cycles);
243 static void exynos4_comp_set_mode(enum clock_event_mode mode,
244 struct clock_event_device *evt)
246 unsigned long cycles_per_jiffy;
247 exynos4_mct_comp0_stop();
250 case CLOCK_EVT_MODE_PERIODIC:
252 (((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift);
253 exynos4_mct_comp0_start(mode, cycles_per_jiffy);
256 case CLOCK_EVT_MODE_ONESHOT:
257 case CLOCK_EVT_MODE_UNUSED:
258 case CLOCK_EVT_MODE_SHUTDOWN:
259 case CLOCK_EVT_MODE_RESUME:
264 static struct clock_event_device mct_comp_device = {
266 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
268 .set_next_event = exynos4_comp_set_next_event,
269 .set_mode = exynos4_comp_set_mode,
272 static irqreturn_t exynos4_mct_comp_isr(int irq, void *dev_id)
274 struct clock_event_device *evt = dev_id;
276 exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_CSTAT);
278 evt->event_handler(evt);
283 static struct irqaction mct_comp_event_irq = {
284 .name = "mct_comp_irq",
285 .flags = IRQF_TIMER | IRQF_IRQPOLL,
286 .handler = exynos4_mct_comp_isr,
287 .dev_id = &mct_comp_device,
290 static void exynos4_clockevent_init(void)
292 mct_comp_device.cpumask = cpumask_of(0);
293 clockevents_config_and_register(&mct_comp_device, clk_rate,
295 setup_irq(mct_irqs[MCT_G0_IRQ], &mct_comp_event_irq);
298 static DEFINE_PER_CPU(struct mct_clock_event_device, percpu_mct_tick);
300 /* Clock event handling */
301 static void exynos4_mct_tick_stop(struct mct_clock_event_device *mevt)
304 unsigned long mask = MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START;
305 unsigned long offset = mevt->base + MCT_L_TCON_OFFSET;
307 tmp = __raw_readl(reg_base + offset);
310 exynos4_mct_write(tmp, offset);
314 static void exynos4_mct_tick_start(unsigned long cycles,
315 struct mct_clock_event_device *mevt)
319 exynos4_mct_tick_stop(mevt);
321 tmp = (1 << 31) | cycles; /* MCT_L_UPDATE_ICNTB */
323 /* update interrupt count buffer */
324 exynos4_mct_write(tmp, mevt->base + MCT_L_ICNTB_OFFSET);
326 /* enable MCT tick interrupt */
327 exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET);
329 tmp = __raw_readl(reg_base + mevt->base + MCT_L_TCON_OFFSET);
330 tmp |= MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START |
331 MCT_L_TCON_INTERVAL_MODE;
332 exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET);
335 static int exynos4_tick_set_next_event(unsigned long cycles,
336 struct clock_event_device *evt)
338 struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
340 exynos4_mct_tick_start(cycles, mevt);
345 static inline void exynos4_tick_set_mode(enum clock_event_mode mode,
346 struct clock_event_device *evt)
348 struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
349 unsigned long cycles_per_jiffy;
351 exynos4_mct_tick_stop(mevt);
354 case CLOCK_EVT_MODE_PERIODIC:
356 (((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift);
357 exynos4_mct_tick_start(cycles_per_jiffy, mevt);
360 case CLOCK_EVT_MODE_ONESHOT:
361 case CLOCK_EVT_MODE_UNUSED:
362 case CLOCK_EVT_MODE_SHUTDOWN:
363 case CLOCK_EVT_MODE_RESUME:
368 static int exynos4_mct_tick_clear(struct mct_clock_event_device *mevt)
370 struct clock_event_device *evt = &mevt->evt;
373 * This is for supporting oneshot mode.
374 * Mct would generate interrupt periodically
375 * without explicit stopping.
377 if (evt->mode != CLOCK_EVT_MODE_PERIODIC)
378 exynos4_mct_tick_stop(mevt);
380 /* Clear the MCT tick interrupt */
381 if (__raw_readl(reg_base + mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) {
382 exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
389 static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id)
391 struct mct_clock_event_device *mevt = dev_id;
392 struct clock_event_device *evt = &mevt->evt;
394 exynos4_mct_tick_clear(mevt);
396 evt->event_handler(evt);
401 static int exynos4_local_timer_setup(struct clock_event_device *evt)
403 struct mct_clock_event_device *mevt;
404 unsigned int cpu = smp_processor_id();
406 mevt = container_of(evt, struct mct_clock_event_device, evt);
408 mevt->base = EXYNOS4_MCT_L_BASE(cpu);
409 sprintf(mevt->name, "mct_tick%d", cpu);
411 evt->name = mevt->name;
412 evt->cpumask = cpumask_of(cpu);
413 evt->set_next_event = exynos4_tick_set_next_event;
414 evt->set_mode = exynos4_tick_set_mode;
415 evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
417 clockevents_config_and_register(evt, clk_rate / (TICK_BASE_CNT + 1),
420 exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET);
422 if (mct_int_type == MCT_INT_SPI) {
423 evt->irq = mct_irqs[MCT_L0_IRQ + cpu];
424 if (request_irq(evt->irq, exynos4_mct_tick_isr,
425 IRQF_TIMER | IRQF_NOBALANCING,
427 pr_err("exynos-mct: cannot register IRQ %d\n",
432 enable_percpu_irq(mct_irqs[MCT_L0_IRQ], 0);
438 static void exynos4_local_timer_stop(struct clock_event_device *evt)
440 evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
441 if (mct_int_type == MCT_INT_SPI)
442 free_irq(evt->irq, this_cpu_ptr(&percpu_mct_tick));
444 disable_percpu_irq(mct_irqs[MCT_L0_IRQ]);
447 static int exynos4_mct_cpu_notify(struct notifier_block *self,
448 unsigned long action, void *hcpu)
450 struct mct_clock_event_device *mevt;
454 * Grab cpu pointer in each case to avoid spurious
455 * preemptible warnings
457 switch (action & ~CPU_TASKS_FROZEN) {
459 mevt = this_cpu_ptr(&percpu_mct_tick);
460 exynos4_local_timer_setup(&mevt->evt);
463 cpu = (unsigned long)hcpu;
464 if (mct_int_type == MCT_INT_SPI)
465 irq_set_affinity(mct_irqs[MCT_L0_IRQ + cpu],
469 mevt = this_cpu_ptr(&percpu_mct_tick);
470 exynos4_local_timer_stop(&mevt->evt);
477 static struct notifier_block exynos4_mct_cpu_nb = {
478 .notifier_call = exynos4_mct_cpu_notify,
481 static void __init exynos4_timer_resources(struct device_node *np, void __iomem *base)
484 struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
485 struct clk *mct_clk, *tick_clk;
487 tick_clk = np ? of_clk_get_by_name(np, "fin_pll") :
488 clk_get(NULL, "fin_pll");
489 if (IS_ERR(tick_clk))
490 panic("%s: unable to determine tick clock rate\n", __func__);
491 clk_rate = clk_get_rate(tick_clk);
493 mct_clk = np ? of_clk_get_by_name(np, "mct") : clk_get(NULL, "mct");
495 panic("%s: unable to retrieve mct clock instance\n", __func__);
496 clk_prepare_enable(mct_clk);
500 panic("%s: unable to ioremap mct address space\n", __func__);
502 if (mct_int_type == MCT_INT_PPI) {
504 err = request_percpu_irq(mct_irqs[MCT_L0_IRQ],
505 exynos4_mct_tick_isr, "MCT",
507 WARN(err, "MCT: can't request IRQ %d (%d)\n",
508 mct_irqs[MCT_L0_IRQ], err);
510 irq_set_affinity(mct_irqs[MCT_L0_IRQ], cpumask_of(0));
513 err = register_cpu_notifier(&exynos4_mct_cpu_nb);
517 /* Immediately configure the timer on the boot CPU */
518 exynos4_local_timer_setup(&mevt->evt);
522 free_percpu_irq(mct_irqs[MCT_L0_IRQ], &percpu_mct_tick);
525 void __init mct_init(void __iomem *base, int irq_g0, int irq_l0, int irq_l1)
527 mct_irqs[MCT_G0_IRQ] = irq_g0;
528 mct_irqs[MCT_L0_IRQ] = irq_l0;
529 mct_irqs[MCT_L1_IRQ] = irq_l1;
530 mct_int_type = MCT_INT_SPI;
532 exynos4_timer_resources(NULL, base);
533 exynos4_clocksource_init();
534 exynos4_clockevent_init();
537 static void __init mct_init_dt(struct device_node *np, unsigned int int_type)
541 mct_int_type = int_type;
543 /* This driver uses only one global timer interrupt */
544 mct_irqs[MCT_G0_IRQ] = irq_of_parse_and_map(np, MCT_G0_IRQ);
547 * Find out the number of local irqs specified. The local
548 * timer irqs are specified after the four global timer
549 * irqs are specified.
552 nr_irqs = of_irq_count(np);
556 for (i = MCT_L0_IRQ; i < nr_irqs; i++)
557 mct_irqs[i] = irq_of_parse_and_map(np, i);
559 exynos4_timer_resources(np, of_iomap(np, 0));
560 exynos4_clocksource_init();
561 exynos4_clockevent_init();
565 static void __init mct_init_spi(struct device_node *np)
567 return mct_init_dt(np, MCT_INT_SPI);
570 static void __init mct_init_ppi(struct device_node *np)
572 return mct_init_dt(np, MCT_INT_PPI);
574 CLOCKSOURCE_OF_DECLARE(exynos4210, "samsung,exynos4210-mct", mct_init_spi);
575 CLOCKSOURCE_OF_DECLARE(exynos4412, "samsung,exynos4412-mct", mct_init_ppi);