drivers/cpufreq/exynos5440-cpufreq.c

   1 /*
   2  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * Amit Daniel Kachhap <amit.daniel@samsung.com>
   6  *
   7  * EXYNOS5440 - CPU frequency scaling support
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12 */
  13
  14 #include <linux/clk.h>
  15 #include <linux/cpu.h>
  16 #include <linux/cpufreq.h>
  17 #include <linux/err.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/io.h>
  20 #include <linux/module.h>
  21 #include <linux/of_address.h>
  22 #include <linux/of_irq.h>
  23 #include <linux/pm_opp.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/slab.h>
  26
  27 /* Register definitions */
  28 #define XMU_DVFS_CTRL           0x0060
  29 #define XMU_PMU_P0_7            0x0064
  30 #define XMU_C0_3_PSTATE         0x0090
  31 #define XMU_P_LIMIT             0x00a0
  32 #define XMU_P_STATUS            0x00a4
  33 #define XMU_PMUEVTEN            0x00d0
  34 #define XMU_PMUIRQEN            0x00d4
  35 #define XMU_PMUIRQ              0x00d8
  36
  37 /* PMU mask and shift definations */
  38 #define P_VALUE_MASK            0x7
  39
  40 #define XMU_DVFS_CTRL_EN_SHIFT  0
  41
  42 #define P0_7_CPUCLKDEV_SHIFT    21
  43 #define P0_7_CPUCLKDEV_MASK     0x7
  44 #define P0_7_ATBCLKDEV_SHIFT    18
  45 #define P0_7_ATBCLKDEV_MASK     0x7
  46 #define P0_7_CSCLKDEV_SHIFT     15
  47 #define P0_7_CSCLKDEV_MASK      0x7
  48 #define P0_7_CPUEMA_SHIFT       28
  49 #define P0_7_CPUEMA_MASK        0xf
  50 #define P0_7_L2EMA_SHIFT        24
  51 #define P0_7_L2EMA_MASK         0xf
  52 #define P0_7_VDD_SHIFT          8
  53 #define P0_7_VDD_MASK           0x7f
  54 #define P0_7_FREQ_SHIFT         0
  55 #define P0_7_FREQ_MASK          0xff
  56
  57 #define C0_3_PSTATE_VALID_SHIFT 8
  58 #define C0_3_PSTATE_CURR_SHIFT  4
  59 #define C0_3_PSTATE_NEW_SHIFT   0
  60
  61 #define PSTATE_CHANGED_EVTEN_SHIFT      0
  62
  63 #define PSTATE_CHANGED_IRQEN_SHIFT      0
  64
  65 #define PSTATE_CHANGED_SHIFT            0
  66
  67 /* some constant values for clock divider calculation */
  68 #define CPU_DIV_FREQ_MAX        500
  69 #define CPU_DBG_FREQ_MAX        375
  70 #define CPU_ATB_FREQ_MAX        500
  71
  72 #define PMIC_LOW_VOLT           0x30
  73 #define PMIC_HIGH_VOLT          0x28
  74
  75 #define CPUEMA_HIGH             0x2
  76 #define CPUEMA_MID              0x4
  77 #define CPUEMA_LOW              0x7
  78
  79 #define L2EMA_HIGH              0x1
  80 #define L2EMA_MID               0x3
  81 #define L2EMA_LOW               0x4
  82
  83 #define DIV_TAB_MAX     2
  84 /* frequency unit is 20MHZ */
  85 #define FREQ_UNIT       20
  86 #define MAX_VOLTAGE     1550000 /* In microvolt */
  87 #define VOLTAGE_STEP    12500   /* In microvolt */
  88
  89 #define CPUFREQ_NAME            "exynos5440_dvfs"
  90 #define DEF_TRANS_LATENCY       100000
  91
  92 enum cpufreq_level_index {
  93         L0, L1, L2, L3, L4,
  94         L5, L6, L7, L8, L9,
  95 };
  96 #define CPUFREQ_LEVEL_END       (L7 + 1)
  97
  98 struct exynos_dvfs_data {
  99         void __iomem *base;
 100         struct resource *mem;
 101         int irq;
 102         struct clk *cpu_clk;
 103         unsigned int cur_frequency;
 104         unsigned int latency;
 105         struct cpufreq_frequency_table *freq_table;
 106         unsigned int freq_count;
 107         struct device *dev;
 108         bool dvfs_enabled;
 109         struct work_struct irq_work;
 110 };
 111
 112 static struct exynos_dvfs_data *dvfs_info;
 113 static DEFINE_MUTEX(cpufreq_lock);
 114 static struct cpufreq_freqs freqs;
 115
 116 static int init_div_table(void)
 117 {
 118         struct cpufreq_frequency_table *freq_tbl = dvfs_info->freq_table;
 119         unsigned int tmp, clk_div, ema_div, freq, volt_id;
 120         int i = 0;
 121         struct dev_pm_opp *opp;
 122
 123         rcu_read_lock();
 124         for (i = 0; freq_tbl[i].frequency != CPUFREQ_TABLE_END; i++) {
 125
 126                 opp = dev_pm_opp_find_freq_exact(dvfs_info->dev,
 127                                         freq_tbl[i].frequency * 1000, true);
 128                 if (IS_ERR(opp)) {
 129                         rcu_read_unlock();
 130                         dev_err(dvfs_info->dev,
 131                                 "failed to find valid OPP for %u KHZ\n",
 132                                 freq_tbl[i].frequency);
 133                         return PTR_ERR(opp);
 134                 }
 135
 136                 freq = freq_tbl[i].frequency / 1000; /* In MHZ */
 137                 clk_div = ((freq / CPU_DIV_FREQ_MAX) & P0_7_CPUCLKDEV_MASK)
 138                                         << P0_7_CPUCLKDEV_SHIFT;
 139                 clk_div |= ((freq / CPU_ATB_FREQ_MAX) & P0_7_ATBCLKDEV_MASK)
 140                                         << P0_7_ATBCLKDEV_SHIFT;
 141                 clk_div |= ((freq / CPU_DBG_FREQ_MAX) & P0_7_CSCLKDEV_MASK)
 142                                         << P0_7_CSCLKDEV_SHIFT;
 143
 144                 /* Calculate EMA */
 145                 volt_id = dev_pm_opp_get_voltage(opp);
 146                 volt_id = (MAX_VOLTAGE - volt_id) / VOLTAGE_STEP;
 147                 if (volt_id < PMIC_HIGH_VOLT) {
 148                         ema_div = (CPUEMA_HIGH << P0_7_CPUEMA_SHIFT) |
 149                                 (L2EMA_HIGH << P0_7_L2EMA_SHIFT);
 150                 } else if (volt_id > PMIC_LOW_VOLT) {
 151                         ema_div = (CPUEMA_LOW << P0_7_CPUEMA_SHIFT) |
 152                                 (L2EMA_LOW << P0_7_L2EMA_SHIFT);
 153                 } else {
 154                         ema_div = (CPUEMA_MID << P0_7_CPUEMA_SHIFT) |
 155                                 (L2EMA_MID << P0_7_L2EMA_SHIFT);
 156                 }
 157
 158                 tmp = (clk_div | ema_div | (volt_id << P0_7_VDD_SHIFT)
 159                         | ((freq / FREQ_UNIT) << P0_7_FREQ_SHIFT));
 160
 161                 __raw_writel(tmp, dvfs_info->base + XMU_PMU_P0_7 + 4 * i);
 162         }
 163
 164         rcu_read_unlock();
 165         return 0;
 166 }
 167
 168 static void exynos_enable_dvfs(void)
 169 {
 170         unsigned int tmp, i, cpu;
 171         struct cpufreq_frequency_table *freq_table = dvfs_info->freq_table;
 172         /* Disable DVFS */
 173         __raw_writel(0, dvfs_info->base + XMU_DVFS_CTRL);
 174
 175         /* Enable PSTATE Change Event */
 176         tmp = __raw_readl(dvfs_info->base + XMU_PMUEVTEN);
 177         tmp |= (1 << PSTATE_CHANGED_EVTEN_SHIFT);
 178          __raw_writel(tmp, dvfs_info->base + XMU_PMUEVTEN);
 179
 180         /* Enable PSTATE Change IRQ */
 181         tmp = __raw_readl(dvfs_info->base + XMU_PMUIRQEN);
 182         tmp |= (1 << PSTATE_CHANGED_IRQEN_SHIFT);
 183          __raw_writel(tmp, dvfs_info->base + XMU_PMUIRQEN);
 184
 185         /* Set initial performance index */
 186         for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++)
 187                 if (freq_table[i].frequency == dvfs_info->cur_frequency)
 188                         break;
 189
 190         if (freq_table[i].frequency == CPUFREQ_TABLE_END) {
 191                 dev_crit(dvfs_info->dev, "Boot up frequency not supported\n");
 192                 /* Assign the highest frequency */
 193                 i = 0;
 194                 dvfs_info->cur_frequency = freq_table[i].frequency;
 195         }
 196
 197         dev_info(dvfs_info->dev, "Setting dvfs initial frequency = %uKHZ",
 198                                                 dvfs_info->cur_frequency);
 199
 200         for (cpu = 0; cpu < CONFIG_NR_CPUS; cpu++) {
 201                 tmp = __raw_readl(dvfs_info->base + XMU_C0_3_PSTATE + cpu * 4);
 202                 tmp &= ~(P_VALUE_MASK << C0_3_PSTATE_NEW_SHIFT);
 203                 tmp |= (i << C0_3_PSTATE_NEW_SHIFT);
 204                 __raw_writel(tmp, dvfs_info->base + XMU_C0_3_PSTATE + cpu * 4);
 205         }
 206
 207         /* Enable DVFS */
 208         __raw_writel(1 << XMU_DVFS_CTRL_EN_SHIFT,
 209                                 dvfs_info->base + XMU_DVFS_CTRL);
 210 }
 211
 212 static unsigned int exynos_getspeed(unsigned int cpu)
 213 {
 214         return dvfs_info->cur_frequency;
 215 }
 216
 217 static int exynos_target(struct cpufreq_policy *policy,
 218                           unsigned int target_freq,
 219                           unsigned int relation)
 220 {
 221         unsigned int index, tmp;
 222         int ret = 0, i;
 223         struct cpufreq_frequency_table *freq_table = dvfs_info->freq_table;
 224
 225         mutex_lock(&cpufreq_lock);
 226
 227         ret = cpufreq_frequency_table_target(policy, freq_table,
 228                                            target_freq, relation, &index);
 229         if (ret)
 230                 goto out;
 231
 232         freqs.old = dvfs_info->cur_frequency;
 233         freqs.new = freq_table[index].frequency;
 234
 235         if (freqs.old == freqs.new)
 236                 goto out;
 237
 238         cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE);
 239
 240         /* Set the target frequency in all C0_3_PSTATE register */
 241         for_each_cpu(i, policy->cpus) {
 242                 tmp = __raw_readl(dvfs_info->base + XMU_C0_3_PSTATE + i * 4);
 243                 tmp &= ~(P_VALUE_MASK << C0_3_PSTATE_NEW_SHIFT);
 244                 tmp |= (index << C0_3_PSTATE_NEW_SHIFT);
 245
 246                 __raw_writel(tmp, dvfs_info->base + XMU_C0_3_PSTATE + i * 4);
 247         }
 248 out:
 249         mutex_unlock(&cpufreq_lock);
 250         return ret;
 251 }
 252
 253 static void exynos_cpufreq_work(struct work_struct *work)
 254 {
 255         unsigned int cur_pstate, index;
 256         struct cpufreq_policy *policy = cpufreq_cpu_get(0); /* boot CPU */
 257         struct cpufreq_frequency_table *freq_table = dvfs_info->freq_table;
 258
 259         /* Ensure we can access cpufreq structures */
 260         if (unlikely(dvfs_info->dvfs_enabled == false))
 261                 goto skip_work;
 262
 263         mutex_lock(&cpufreq_lock);
 264         freqs.old = dvfs_info->cur_frequency;
 265
 266         cur_pstate = __raw_readl(dvfs_info->base + XMU_P_STATUS);
 267         if (cur_pstate >> C0_3_PSTATE_VALID_SHIFT & 0x1)
 268                 index = (cur_pstate >> C0_3_PSTATE_CURR_SHIFT) & P_VALUE_MASK;
 269         else
 270                 index = (cur_pstate >> C0_3_PSTATE_NEW_SHIFT) & P_VALUE_MASK;
 271
 272         if (likely(index < dvfs_info->freq_count)) {
 273                 freqs.new = freq_table[index].frequency;
 274                 dvfs_info->cur_frequency = freqs.new;
 275         } else {
 276                 dev_crit(dvfs_info->dev, "New frequency out of range\n");
 277                 freqs.new = dvfs_info->cur_frequency;
 278         }
 279         cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE);
 280
 281         cpufreq_cpu_put(policy);
 282         mutex_unlock(&cpufreq_lock);
 283 skip_work:
 284         enable_irq(dvfs_info->irq);
 285 }
 286
 287 static irqreturn_t exynos_cpufreq_irq(int irq, void *id)
 288 {
 289         unsigned int tmp;
 290
 291         tmp = __raw_readl(dvfs_info->base + XMU_PMUIRQ);
 292         if (tmp >> PSTATE_CHANGED_SHIFT & 0x1) {
 293                 __raw_writel(tmp, dvfs_info->base + XMU_PMUIRQ);
 294                 disable_irq_nosync(irq);
 295                 schedule_work(&dvfs_info->irq_work);
 296         }
 297         return IRQ_HANDLED;
 298 }
 299
 300 static void exynos_sort_descend_freq_table(void)
 301 {
 302         struct cpufreq_frequency_table *freq_tbl = dvfs_info->freq_table;
 303         int i = 0, index;
 304         unsigned int tmp_freq;
 305         /*
 306          * Exynos5440 clock controller state logic expects the cpufreq table to
 307          * be in descending order. But the OPP library constructs the table in
 308          * ascending order. So to make the table descending we just need to
 309          * swap the i element with the N - i element.
 310          */
 311         for (i = 0; i < dvfs_info->freq_count / 2; i++) {
 312                 index = dvfs_info->freq_count - i - 1;
 313                 tmp_freq = freq_tbl[i].frequency;
 314                 freq_tbl[i].frequency = freq_tbl[index].frequency;
 315                 freq_tbl[index].frequency = tmp_freq;
 316         }
 317 }
 318
 319 static int exynos_cpufreq_cpu_init(struct cpufreq_policy *policy)
 320 {
 321         return cpufreq_generic_init(policy, dvfs_info->freq_table,
 322                         dvfs_info->latency);
 323 }
 324
 325 static struct cpufreq_driver exynos_driver = {
 326         .flags          = CPUFREQ_STICKY,
 327         .verify         = cpufreq_generic_frequency_table_verify,
 328         .target         = exynos_target,
 329         .get            = exynos_getspeed,
 330         .init           = exynos_cpufreq_cpu_init,
 331         .exit           = cpufreq_generic_exit,
 332         .name           = CPUFREQ_NAME,
 333         .attr           = cpufreq_generic_attr,
 334 };
 335
 336 static const struct of_device_id exynos_cpufreq_match[] = {
 337         {
 338                 .compatible = "samsung,exynos5440-cpufreq",
 339         },
 340         {},
 341 };
 342 MODULE_DEVICE_TABLE(of, exynos_cpufreq_match);
 343
 344 static int exynos_cpufreq_probe(struct platform_device *pdev)
 345 {
 346         int ret = -EINVAL;
 347         struct device_node *np;
 348         struct resource res;
 349
 350         np =  pdev->dev.of_node;
 351         if (!np)
 352                 return -ENODEV;
 353
 354         dvfs_info = devm_kzalloc(&pdev->dev, sizeof(*dvfs_info), GFP_KERNEL);
 355         if (!dvfs_info) {
 356                 ret = -ENOMEM;
 357                 goto err_put_node;
 358         }
 359
 360         dvfs_info->dev = &pdev->dev;
 361
 362         ret = of_address_to_resource(np, 0, &res);
 363         if (ret)
 364                 goto err_put_node;
 365
 366         dvfs_info->base = devm_ioremap_resource(dvfs_info->dev, &res);
 367         if (IS_ERR(dvfs_info->base)) {
 368                 ret = PTR_ERR(dvfs_info->base);
 369                 goto err_put_node;
 370         }
 371
 372         dvfs_info->irq = irq_of_parse_and_map(np, 0);
 373         if (!dvfs_info->irq) {
 374                 dev_err(dvfs_info->dev, "No cpufreq irq found\n");
 375                 ret = -ENODEV;
 376                 goto err_put_node;
 377         }
 378
 379         ret = of_init_opp_table(dvfs_info->dev);
 380         if (ret) {
 381                 dev_err(dvfs_info->dev, "failed to init OPP table: %d\n", ret);
 382                 goto err_put_node;
 383         }
 384
 385         ret = dev_pm_opp_init_cpufreq_table(dvfs_info->dev,
 386                                             &dvfs_info->freq_table);
 387         if (ret) {
 388                 dev_err(dvfs_info->dev,
 389                         "failed to init cpufreq table: %d\n", ret);
 390                 goto err_put_node;
 391         }
 392         dvfs_info->freq_count = dev_pm_opp_get_opp_count(dvfs_info->dev);
 393         exynos_sort_descend_freq_table();
 394
 395         if (of_property_read_u32(np, "clock-latency", &dvfs_info->latency))
 396                 dvfs_info->latency = DEF_TRANS_LATENCY;
 397
 398         dvfs_info->cpu_clk = devm_clk_get(dvfs_info->dev, "armclk");
 399         if (IS_ERR(dvfs_info->cpu_clk)) {
 400                 dev_err(dvfs_info->dev, "Failed to get cpu clock\n");
 401                 ret = PTR_ERR(dvfs_info->cpu_clk);
 402                 goto err_free_table;
 403         }
 404
 405         dvfs_info->cur_frequency = clk_get_rate(dvfs_info->cpu_clk);
 406         if (!dvfs_info->cur_frequency) {
 407                 dev_err(dvfs_info->dev, "Failed to get clock rate\n");
 408                 ret = -EINVAL;
 409                 goto err_free_table;
 410         }
 411         dvfs_info->cur_frequency /= 1000;
 412
 413         INIT_WORK(&dvfs_info->irq_work, exynos_cpufreq_work);
 414         ret = devm_request_irq(dvfs_info->dev, dvfs_info->irq,
 415                                 exynos_cpufreq_irq, IRQF_TRIGGER_NONE,
 416                                 CPUFREQ_NAME, dvfs_info);
 417         if (ret) {
 418                 dev_err(dvfs_info->dev, "Failed to register IRQ\n");
 419                 goto err_free_table;
 420         }
 421
 422         ret = init_div_table();
 423         if (ret) {
 424                 dev_err(dvfs_info->dev, "Failed to initialise div table\n");
 425                 goto err_free_table;
 426         }
 427
 428         exynos_enable_dvfs();
 429         ret = cpufreq_register_driver(&exynos_driver);
 430         if (ret) {
 431                 dev_err(dvfs_info->dev,
 432                         "%s: failed to register cpufreq driver\n", __func__);
 433                 goto err_free_table;
 434         }
 435
 436         of_node_put(np);
 437         dvfs_info->dvfs_enabled = true;
 438         return 0;
 439
 440 err_free_table:
 441         dev_pm_opp_free_cpufreq_table(dvfs_info->dev, &dvfs_info->freq_table);
 442 err_put_node:
 443         of_node_put(np);
 444         dev_err(&pdev->dev, "%s: failed initialization\n", __func__);
 445         return ret;
 446 }
 447
 448 static int exynos_cpufreq_remove(struct platform_device *pdev)
 449 {
 450         cpufreq_unregister_driver(&exynos_driver);
 451         dev_pm_opp_free_cpufreq_table(dvfs_info->dev, &dvfs_info->freq_table);
 452         return 0;
 453 }
 454
 455 static struct platform_driver exynos_cpufreq_platdrv = {
 456         .driver = {
 457                 .name   = "exynos5440-cpufreq",
 458                 .owner  = THIS_MODULE,
 459                 .of_match_table = exynos_cpufreq_match,
 460         },
 461         .probe          = exynos_cpufreq_probe,
 462         .remove         = exynos_cpufreq_remove,
 463 };
 464 module_platform_driver(exynos_cpufreq_platdrv);
 465
 466 MODULE_AUTHOR("Amit Daniel Kachhap <amit.daniel@samsung.com>");
 467 MODULE_DESCRIPTION("Exynos5440 cpufreq driver");
 468 MODULE_LICENSE("GPL");