drivers/cpufreq/s3c64xx-cpufreq.c

   1 /*
   2  * Copyright 2009 Wolfson Microelectronics plc
   3  *
   4  * S3C64xx CPUfreq Support
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #define pr_fmt(fmt) "cpufreq: " fmt
  12
  13 #include <linux/kernel.h>
  14 #include <linux/types.h>
  15 #include <linux/init.h>
  16 #include <linux/cpufreq.h>
  17 #include <linux/clk.h>
  18 #include <linux/err.h>
  19 #include <linux/regulator/consumer.h>
  20 #include <linux/module.h>
  21
  22 static struct clk *armclk;
  23 static struct regulator *vddarm;
  24 static unsigned long regulator_latency;
  25
  26 #ifdef CONFIG_CPU_S3C6410
  27 struct s3c64xx_dvfs {
  28         unsigned int vddarm_min;
  29         unsigned int vddarm_max;
  30 };
  31
  32 static struct s3c64xx_dvfs s3c64xx_dvfs_table[] = {
  33         [0] = { 1000000, 1150000 },
  34         [1] = { 1050000, 1150000 },
  35         [2] = { 1100000, 1150000 },
  36         [3] = { 1200000, 1350000 },
  37         [4] = { 1300000, 1350000 },
  38 };
  39
  40 static struct cpufreq_frequency_table s3c64xx_freq_table[] = {
  41         { 0,  66000 },
  42         { 0, 100000 },
  43         { 0, 133000 },
  44         { 1, 200000 },
  45         { 1, 222000 },
  46         { 1, 266000 },
  47         { 2, 333000 },
  48         { 2, 400000 },
  49         { 2, 532000 },
  50         { 2, 533000 },
  51         { 3, 667000 },
  52         { 4, 800000 },
  53         { 0, CPUFREQ_TABLE_END },
  54 };
  55 #endif
  56
  57 static unsigned int s3c64xx_cpufreq_get_speed(unsigned int cpu)
  58 {
  59         if (cpu != 0)
  60                 return 0;
  61
  62         return clk_get_rate(armclk) / 1000;
  63 }
  64
  65 static int s3c64xx_cpufreq_set_target(struct cpufreq_policy *policy,
  66                                       unsigned int target_freq,
  67                                       unsigned int relation)
  68 {
  69         int ret;
  70         unsigned int i;
  71         struct cpufreq_freqs freqs;
  72         struct s3c64xx_dvfs *dvfs;
  73
  74         ret = cpufreq_frequency_table_target(policy, s3c64xx_freq_table,
  75                                              target_freq, relation, &i);
  76         if (ret != 0)
  77                 return ret;
  78
  79         freqs.old = clk_get_rate(armclk) / 1000;
  80         freqs.new = s3c64xx_freq_table[i].frequency;
  81         freqs.flags = 0;
  82         dvfs = &s3c64xx_dvfs_table[s3c64xx_freq_table[i].driver_data];
  83
  84         if (freqs.old == freqs.new)
  85                 return 0;
  86
  87         pr_debug("Transition %d-%dkHz\n", freqs.old, freqs.new);
  88
  89         cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE);
  90
  91 #ifdef CONFIG_REGULATOR
  92         if (vddarm && freqs.new > freqs.old) {
  93                 ret = regulator_set_voltage(vddarm,
  94                                             dvfs->vddarm_min,
  95                                             dvfs->vddarm_max);
  96                 if (ret != 0) {
  97                         pr_err("Failed to set VDDARM for %dkHz: %d\n",
  98                                freqs.new, ret);
  99                         freqs.new = freqs.old;
 100                         goto post_notify;
 101                 }
 102         }
 103 #endif
 104
 105         ret = clk_set_rate(armclk, freqs.new * 1000);
 106         if (ret < 0) {
 107                 pr_err("Failed to set rate %dkHz: %d\n",
 108                        freqs.new, ret);
 109                 freqs.new = freqs.old;
 110         }
 111
 112 post_notify:
 113         cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE);
 114         if (ret)
 115                 goto err;
 116
 117 #ifdef CONFIG_REGULATOR
 118         if (vddarm && freqs.new < freqs.old) {
 119                 ret = regulator_set_voltage(vddarm,
 120                                             dvfs->vddarm_min,
 121                                             dvfs->vddarm_max);
 122                 if (ret != 0) {
 123                         pr_err("Failed to set VDDARM for %dkHz: %d\n",
 124                                freqs.new, ret);
 125                         goto err_clk;
 126                 }
 127         }
 128 #endif
 129
 130         pr_debug("Set actual frequency %lukHz\n",
 131                  clk_get_rate(armclk) / 1000);
 132
 133         return 0;
 134
 135 err_clk:
 136         if (clk_set_rate(armclk, freqs.old * 1000) < 0)
 137                 pr_err("Failed to restore original clock rate\n");
 138 err:
 139         cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE);
 140
 141         return ret;
 142 }
 143
 144 #ifdef CONFIG_REGULATOR
 145 static void __init s3c64xx_cpufreq_config_regulator(void)
 146 {
 147         int count, v, i, found;
 148         struct cpufreq_frequency_table *freq;
 149         struct s3c64xx_dvfs *dvfs;
 150
 151         count = regulator_count_voltages(vddarm);
 152         if (count < 0) {
 153                 pr_err("Unable to check supported voltages\n");
 154         }
 155
 156         freq = s3c64xx_freq_table;
 157         while (count > 0 && freq->frequency != CPUFREQ_TABLE_END) {
 158                 if (freq->frequency == CPUFREQ_ENTRY_INVALID)
 159                         continue;
 160
 161                 dvfs = &s3c64xx_dvfs_table[freq->driver_data];
 162                 found = 0;
 163
 164                 for (i = 0; i < count; i++) {
 165                         v = regulator_list_voltage(vddarm, i);
 166                         if (v >= dvfs->vddarm_min && v <= dvfs->vddarm_max)
 167                                 found = 1;
 168                 }
 169
 170                 if (!found) {
 171                         pr_debug("%dkHz unsupported by regulator\n",
 172                                  freq->frequency);
 173                         freq->frequency = CPUFREQ_ENTRY_INVALID;
 174                 }
 175
 176                 freq++;
 177         }
 178
 179         /* Guess based on having to do an I2C/SPI write; in future we
 180          * will be able to query the regulator performance here. */
 181         regulator_latency = 1 * 1000 * 1000;
 182 }
 183 #endif
 184
 185 static int s3c64xx_cpufreq_driver_init(struct cpufreq_policy *policy)
 186 {
 187         int ret;
 188         struct cpufreq_frequency_table *freq;
 189
 190         if (policy->cpu != 0)
 191                 return -EINVAL;
 192
 193         if (s3c64xx_freq_table == NULL) {
 194                 pr_err("No frequency information for this CPU\n");
 195                 return -ENODEV;
 196         }
 197
 198         armclk = clk_get(NULL, "armclk");
 199         if (IS_ERR(armclk)) {
 200                 pr_err("Unable to obtain ARMCLK: %ld\n",
 201                        PTR_ERR(armclk));
 202                 return PTR_ERR(armclk);
 203         }
 204
 205 #ifdef CONFIG_REGULATOR
 206         vddarm = regulator_get(NULL, "vddarm");
 207         if (IS_ERR(vddarm)) {
 208                 ret = PTR_ERR(vddarm);
 209                 pr_err("Failed to obtain VDDARM: %d\n", ret);
 210                 pr_err("Only frequency scaling available\n");
 211                 vddarm = NULL;
 212         } else {
 213                 s3c64xx_cpufreq_config_regulator();
 214         }
 215 #endif
 216
 217         freq = s3c64xx_freq_table;
 218         while (freq->frequency != CPUFREQ_TABLE_END) {
 219                 unsigned long r;
 220
 221                 /* Check for frequencies we can generate */
 222                 r = clk_round_rate(armclk, freq->frequency * 1000);
 223                 r /= 1000;
 224                 if (r != freq->frequency) {
 225                         pr_debug("%dkHz unsupported by clock\n",
 226                                  freq->frequency);
 227                         freq->frequency = CPUFREQ_ENTRY_INVALID;
 228                 }
 229
 230                 /* If we have no regulator then assume startup
 231                  * frequency is the maximum we can support. */
 232                 if (!vddarm && freq->frequency > s3c64xx_cpufreq_get_speed(0))
 233                         freq->frequency = CPUFREQ_ENTRY_INVALID;
 234
 235                 freq++;
 236         }
 237
 238         /* Datasheet says PLL stabalisation time (if we were to use
 239          * the PLLs, which we don't currently) is ~300us worst case,
 240          * but add some fudge.
 241          */
 242         ret = cpufreq_generic_init(policy, s3c64xx_freq_table,
 243                         (500 * 1000) + regulator_latency);
 244         if (ret != 0) {
 245                 pr_err("Failed to configure frequency table: %d\n",
 246                        ret);
 247                 regulator_put(vddarm);
 248                 clk_put(armclk);
 249         }
 250
 251         return ret;
 252 }
 253
 254 static struct cpufreq_driver s3c64xx_cpufreq_driver = {
 255         .flags          = 0,
 256         .verify         = cpufreq_generic_frequency_table_verify,
 257         .target         = s3c64xx_cpufreq_set_target,
 258         .get            = s3c64xx_cpufreq_get_speed,
 259         .init           = s3c64xx_cpufreq_driver_init,
 260         .name           = "s3c",
 261 };
 262
 263 static int __init s3c64xx_cpufreq_init(void)
 264 {
 265         return cpufreq_register_driver(&s3c64xx_cpufreq_driver);
 266 }
 267 module_init(s3c64xx_cpufreq_init);