drivers/crypto/omap-sham.c

   1 /*
   2  * Cryptographic API.
   3  *
   4  * Support for OMAP SHA1/MD5 HW acceleration.
   5  *
   6  * Copyright (c) 2010 Nokia Corporation
   7  * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as published
  11  * by the Free Software Foundation.
  12  *
  13  * Some ideas are from old omap-sha1-md5.c driver.
  14  */
  15
  16 #define pr_fmt(fmt) "%s: " fmt, __func__
  17
  18 #include <linux/err.h>
  19 #include <linux/device.h>
  20 #include <linux/module.h>
  21 #include <linux/init.h>
  22 #include <linux/errno.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/kernel.h>
  25 #include <linux/clk.h>
  26 #include <linux/irq.h>
  27 #include <linux/io.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/scatterlist.h>
  30 #include <linux/dma-mapping.h>
  31 #include <linux/delay.h>
  32 #include <linux/crypto.h>
  33 #include <linux/cryptohash.h>
  34 #include <crypto/scatterwalk.h>
  35 #include <crypto/algapi.h>
  36 #include <crypto/sha.h>
  37 #include <crypto/hash.h>
  38 #include <crypto/internal/hash.h>
  39
  40 #include <plat/cpu.h>
  41 #include <plat/dma.h>
  42 #include <mach/irqs.h>
  43
  44 #define SHA_REG_DIGEST(x)               (0x00 + ((x) * 0x04))
  45 #define SHA_REG_DIN(x)                  (0x1C + ((x) * 0x04))
  46
  47 #define SHA1_MD5_BLOCK_SIZE             SHA1_BLOCK_SIZE
  48 #define MD5_DIGEST_SIZE                 16
  49
  50 #define SHA_REG_DIGCNT                  0x14
  51
  52 #define SHA_REG_CTRL                    0x18
  53 #define SHA_REG_CTRL_LENGTH             (0xFFFFFFFF << 5)
  54 #define SHA_REG_CTRL_CLOSE_HASH         (1 << 4)
  55 #define SHA_REG_CTRL_ALGO_CONST         (1 << 3)
  56 #define SHA_REG_CTRL_ALGO               (1 << 2)
  57 #define SHA_REG_CTRL_INPUT_READY        (1 << 1)
  58 #define SHA_REG_CTRL_OUTPUT_READY       (1 << 0)
  59
  60 #define SHA_REG_REV                     0x5C
  61 #define SHA_REG_REV_MAJOR               0xF0
  62 #define SHA_REG_REV_MINOR               0x0F
  63
  64 #define SHA_REG_MASK                    0x60
  65 #define SHA_REG_MASK_DMA_EN             (1 << 3)
  66 #define SHA_REG_MASK_IT_EN              (1 << 2)
  67 #define SHA_REG_MASK_SOFTRESET          (1 << 1)
  68 #define SHA_REG_AUTOIDLE                (1 << 0)
  69
  70 #define SHA_REG_SYSSTATUS               0x64
  71 #define SHA_REG_SYSSTATUS_RESETDONE     (1 << 0)
  72
  73 #define DEFAULT_TIMEOUT_INTERVAL        HZ
  74
  75 /* mostly device flags */
  76 #define FLAGS_BUSY              0
  77 #define FLAGS_FINAL             1
  78 #define FLAGS_DMA_ACTIVE        2
  79 #define FLAGS_OUTPUT_READY      3
  80 #define FLAGS_INIT              4
  81 #define FLAGS_CPU               5
  82 /* context flags */
  83 #define FLAGS_FINUP             16
  84 #define FLAGS_SG                17
  85 #define FLAGS_SHA1              18
  86 #define FLAGS_HMAC              19
  87 #define FLAGS_ERROR             20
  88
  89 #define OP_UPDATE       1
  90 #define OP_FINAL        2
  91
  92 #define OMAP_ALIGN_MASK         (sizeof(u32)-1)
  93 #define OMAP_ALIGNED            __attribute__((aligned(sizeof(u32))))
  94
  95 #define BUFLEN          PAGE_SIZE
  96
  97 struct omap_sham_dev;
  98
  99 struct omap_sham_reqctx {
 100         struct omap_sham_dev    *dd;
 101         unsigned long           flags;
 102         unsigned long           op;
 103
 104         u8                      digest[SHA1_DIGEST_SIZE] OMAP_ALIGNED;
 105         size_t                  digcnt;
 106         size_t                  bufcnt;
 107         size_t                  buflen;
 108         dma_addr_t              dma_addr;
 109
 110         /* walk state */
 111         struct scatterlist      *sg;
 112         unsigned int            offset; /* offset in current sg */
 113         unsigned int            total;  /* total request */
 114
 115         u8                      buffer[0] OMAP_ALIGNED;
 116 };
 117
 118 struct omap_sham_hmac_ctx {
 119         struct crypto_shash     *shash;
 120         u8                      ipad[SHA1_MD5_BLOCK_SIZE];
 121         u8                      opad[SHA1_MD5_BLOCK_SIZE];
 122 };
 123
 124 struct omap_sham_ctx {
 125         struct omap_sham_dev    *dd;
 126
 127         unsigned long           flags;
 128
 129         /* fallback stuff */
 130         struct crypto_shash     *fallback;
 131
 132         struct omap_sham_hmac_ctx base[0];
 133 };
 134
 135 #define OMAP_SHAM_QUEUE_LENGTH  1
 136
 137 struct omap_sham_dev {
 138         struct list_head        list;
 139         unsigned long           phys_base;
 140         struct device           *dev;
 141         void __iomem            *io_base;
 142         int                     irq;
 143         struct clk              *iclk;
 144         spinlock_t              lock;
 145         int                     err;
 146         int                     dma;
 147         int                     dma_lch;
 148         struct tasklet_struct   done_task;
 149
 150         unsigned long           flags;
 151         struct crypto_queue     queue;
 152         struct ahash_request    *req;
 153 };
 154
 155 struct omap_sham_drv {
 156         struct list_head        dev_list;
 157         spinlock_t              lock;
 158         unsigned long           flags;
 159 };
 160
 161 static struct omap_sham_drv sham = {
 162         .dev_list = LIST_HEAD_INIT(sham.dev_list),
 163         .lock = __SPIN_LOCK_UNLOCKED(sham.lock),
 164 };
 165
 166 static inline u32 omap_sham_read(struct omap_sham_dev *dd, u32 offset)
 167 {
 168         return __raw_readl(dd->io_base + offset);
 169 }
 170
 171 static inline void omap_sham_write(struct omap_sham_dev *dd,
 172                                         u32 offset, u32 value)
 173 {
 174         __raw_writel(value, dd->io_base + offset);
 175 }
 176
 177 static inline void omap_sham_write_mask(struct omap_sham_dev *dd, u32 address,
 178                                         u32 value, u32 mask)
 179 {
 180         u32 val;
 181
 182         val = omap_sham_read(dd, address);
 183         val &= ~mask;
 184         val |= value;
 185         omap_sham_write(dd, address, val);
 186 }
 187
 188 static inline int omap_sham_wait(struct omap_sham_dev *dd, u32 offset, u32 bit)
 189 {
 190         unsigned long timeout = jiffies + DEFAULT_TIMEOUT_INTERVAL;
 191
 192         while (!(omap_sham_read(dd, offset) & bit)) {
 193                 if (time_is_before_jiffies(timeout))
 194                         return -ETIMEDOUT;
 195         }
 196
 197         return 0;
 198 }
 199
 200 static void omap_sham_copy_hash(struct ahash_request *req, int out)
 201 {
 202         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 203         u32 *hash = (u32 *)ctx->digest;
 204         int i;
 205
 206         /* MD5 is almost unused. So copy sha1 size to reduce code */
 207         for (i = 0; i < SHA1_DIGEST_SIZE / sizeof(u32); i++) {
 208                 if (out)
 209                         hash[i] = omap_sham_read(ctx->dd,
 210                                                 SHA_REG_DIGEST(i));
 211                 else
 212                         omap_sham_write(ctx->dd,
 213                                         SHA_REG_DIGEST(i), hash[i]);
 214         }
 215 }
 216
 217 static void omap_sham_copy_ready_hash(struct ahash_request *req)
 218 {
 219         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 220         u32 *in = (u32 *)ctx->digest;
 221         u32 *hash = (u32 *)req->result;
 222         int i;
 223
 224         if (!hash)
 225                 return;
 226
 227         if (likely(ctx->flags & BIT(FLAGS_SHA1))) {
 228                 /* SHA1 results are in big endian */
 229                 for (i = 0; i < SHA1_DIGEST_SIZE / sizeof(u32); i++)
 230                         hash[i] = be32_to_cpu(in[i]);
 231         } else {
 232                 /* MD5 results are in little endian */
 233                 for (i = 0; i < MD5_DIGEST_SIZE / sizeof(u32); i++)
 234                         hash[i] = le32_to_cpu(in[i]);
 235         }
 236 }
 237
 238 static int omap_sham_hw_init(struct omap_sham_dev *dd)
 239 {
 240         clk_enable(dd->iclk);
 241
 242         if (!test_bit(FLAGS_INIT, &dd->flags)) {
 243                 omap_sham_write_mask(dd, SHA_REG_MASK,
 244                         SHA_REG_MASK_SOFTRESET, SHA_REG_MASK_SOFTRESET);
 245
 246                 if (omap_sham_wait(dd, SHA_REG_SYSSTATUS,
 247                                         SHA_REG_SYSSTATUS_RESETDONE))
 248                         return -ETIMEDOUT;
 249
 250                 set_bit(FLAGS_INIT, &dd->flags);
 251                 dd->err = 0;
 252         }
 253
 254         return 0;
 255 }
 256
 257 static void omap_sham_write_ctrl(struct omap_sham_dev *dd, size_t length,
 258                                  int final, int dma)
 259 {
 260         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 261         u32 val = length << 5, mask;
 262
 263         if (likely(ctx->digcnt))
 264                 omap_sham_write(dd, SHA_REG_DIGCNT, ctx->digcnt);
 265
 266         omap_sham_write_mask(dd, SHA_REG_MASK,
 267                 SHA_REG_MASK_IT_EN | (dma ? SHA_REG_MASK_DMA_EN : 0),
 268                 SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN);
 269         /*
 270          * Setting ALGO_CONST only for the first iteration
 271          * and CLOSE_HASH only for the last one.
 272          */
 273         if (ctx->flags & BIT(FLAGS_SHA1))
 274                 val |= SHA_REG_CTRL_ALGO;
 275         if (!ctx->digcnt)
 276                 val |= SHA_REG_CTRL_ALGO_CONST;
 277         if (final)
 278                 val |= SHA_REG_CTRL_CLOSE_HASH;
 279
 280         mask = SHA_REG_CTRL_ALGO_CONST | SHA_REG_CTRL_CLOSE_HASH |
 281                         SHA_REG_CTRL_ALGO | SHA_REG_CTRL_LENGTH;
 282
 283         omap_sham_write_mask(dd, SHA_REG_CTRL, val, mask);
 284 }
 285
 286 static int omap_sham_xmit_cpu(struct omap_sham_dev *dd, const u8 *buf,
 287                               size_t length, int final)
 288 {
 289         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 290         int count, len32;
 291         const u32 *buffer = (const u32 *)buf;
 292
 293         dev_dbg(dd->dev, "xmit_cpu: digcnt: %d, length: %d, final: %d\n",
 294                                                 ctx->digcnt, length, final);
 295
 296         omap_sham_write_ctrl(dd, length, final, 0);
 297
 298         /* should be non-zero before next lines to disable clocks later */
 299         ctx->digcnt += length;
 300
 301         if (omap_sham_wait(dd, SHA_REG_CTRL, SHA_REG_CTRL_INPUT_READY))
 302                 return -ETIMEDOUT;
 303
 304         if (final)
 305                 set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */
 306
 307         len32 = DIV_ROUND_UP(length, sizeof(u32));
 308
 309         for (count = 0; count < len32; count++)
 310                 omap_sham_write(dd, SHA_REG_DIN(count), buffer[count]);
 311
 312         return -EINPROGRESS;
 313 }
 314
 315 static int omap_sham_xmit_dma(struct omap_sham_dev *dd, dma_addr_t dma_addr,
 316                               size_t length, int final)
 317 {
 318         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 319         int len32;
 320
 321         dev_dbg(dd->dev, "xmit_dma: digcnt: %d, length: %d, final: %d\n",
 322                                                 ctx->digcnt, length, final);
 323
 324         len32 = DIV_ROUND_UP(length, sizeof(u32));
 325
 326         omap_set_dma_transfer_params(dd->dma_lch, OMAP_DMA_DATA_TYPE_S32, len32,
 327                         1, OMAP_DMA_SYNC_PACKET, dd->dma,
 328                                 OMAP_DMA_DST_SYNC_PREFETCH);
 329
 330         omap_set_dma_src_params(dd->dma_lch, 0, OMAP_DMA_AMODE_POST_INC,
 331                                 dma_addr, 0, 0);
 332
 333         omap_sham_write_ctrl(dd, length, final, 1);
 334
 335         ctx->digcnt += length;
 336
 337         if (final)
 338                 set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */
 339
 340         set_bit(FLAGS_DMA_ACTIVE, &dd->flags);
 341
 342         omap_start_dma(dd->dma_lch);
 343
 344         return -EINPROGRESS;
 345 }
 346
 347 static size_t omap_sham_append_buffer(struct omap_sham_reqctx *ctx,
 348                                 const u8 *data, size_t length)
 349 {
 350         size_t count = min(length, ctx->buflen - ctx->bufcnt);
 351
 352         count = min(count, ctx->total);
 353         if (count <= 0)
 354                 return 0;
 355         memcpy(ctx->buffer + ctx->bufcnt, data, count);
 356         ctx->bufcnt += count;
 357
 358         return count;
 359 }
 360
 361 static size_t omap_sham_append_sg(struct omap_sham_reqctx *ctx)
 362 {
 363         size_t count;
 364
 365         while (ctx->sg) {
 366                 count = omap_sham_append_buffer(ctx,
 367                                 sg_virt(ctx->sg) + ctx->offset,
 368                                 ctx->sg->length - ctx->offset);
 369                 if (!count)
 370                         break;
 371                 ctx->offset += count;
 372                 ctx->total -= count;
 373                 if (ctx->offset == ctx->sg->length) {
 374                         ctx->sg = sg_next(ctx->sg);
 375                         if (ctx->sg)
 376                                 ctx->offset = 0;
 377                         else
 378                                 ctx->total = 0;
 379                 }
 380         }
 381
 382         return 0;
 383 }
 384
 385 static int omap_sham_xmit_dma_map(struct omap_sham_dev *dd,
 386                                         struct omap_sham_reqctx *ctx,
 387                                         size_t length, int final)
 388 {
 389         ctx->dma_addr = dma_map_single(dd->dev, ctx->buffer, ctx->buflen,
 390                                        DMA_TO_DEVICE);
 391         if (dma_mapping_error(dd->dev, ctx->dma_addr)) {
 392                 dev_err(dd->dev, "dma %u bytes error\n", ctx->buflen);
 393                 return -EINVAL;
 394         }
 395
 396         ctx->flags &= ~BIT(FLAGS_SG);
 397
 398         /* next call does not fail... so no unmap in the case of error */
 399         return omap_sham_xmit_dma(dd, ctx->dma_addr, length, final);
 400 }
 401
 402 static int omap_sham_update_dma_slow(struct omap_sham_dev *dd)
 403 {
 404         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 405         unsigned int final;
 406         size_t count;
 407
 408         omap_sham_append_sg(ctx);
 409
 410         final = (ctx->flags & BIT(FLAGS_FINUP)) && !ctx->total;
 411
 412         dev_dbg(dd->dev, "slow: bufcnt: %u, digcnt: %d, final: %d\n",
 413                                          ctx->bufcnt, ctx->digcnt, final);
 414
 415         if (final || (ctx->bufcnt == ctx->buflen && ctx->total)) {
 416                 count = ctx->bufcnt;
 417                 ctx->bufcnt = 0;
 418                 return omap_sham_xmit_dma_map(dd, ctx, count, final);
 419         }
 420
 421         return 0;
 422 }
 423
 424 /* Start address alignment */
 425 #define SG_AA(sg)       (IS_ALIGNED(sg->offset, sizeof(u32)))
 426 /* SHA1 block size alignment */
 427 #define SG_SA(sg)       (IS_ALIGNED(sg->length, SHA1_MD5_BLOCK_SIZE))
 428
 429 static int omap_sham_update_dma_start(struct omap_sham_dev *dd)
 430 {
 431         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 432         unsigned int length, final, tail;
 433         struct scatterlist *sg;
 434
 435         if (!ctx->total)
 436                 return 0;
 437
 438         if (ctx->bufcnt || ctx->offset)
 439                 return omap_sham_update_dma_slow(dd);
 440
 441         dev_dbg(dd->dev, "fast: digcnt: %d, bufcnt: %u, total: %u\n",
 442                         ctx->digcnt, ctx->bufcnt, ctx->total);
 443
 444         sg = ctx->sg;
 445
 446         if (!SG_AA(sg))
 447                 return omap_sham_update_dma_slow(dd);
 448
 449         if (!sg_is_last(sg) && !SG_SA(sg))
 450                 /* size is not SHA1_BLOCK_SIZE aligned */
 451                 return omap_sham_update_dma_slow(dd);
 452
 453         length = min(ctx->total, sg->length);
 454
 455         if (sg_is_last(sg)) {
 456                 if (!(ctx->flags & BIT(FLAGS_FINUP))) {
 457                         /* not last sg must be SHA1_MD5_BLOCK_SIZE aligned */
 458                         tail = length & (SHA1_MD5_BLOCK_SIZE - 1);
 459                         /* without finup() we need one block to close hash */
 460                         if (!tail)
 461                                 tail = SHA1_MD5_BLOCK_SIZE;
 462                         length -= tail;
 463                 }
 464         }
 465
 466         if (!dma_map_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE)) {
 467                 dev_err(dd->dev, "dma_map_sg  error\n");
 468                 return -EINVAL;
 469         }
 470
 471         ctx->flags |= BIT(FLAGS_SG);
 472
 473         ctx->total -= length;
 474         ctx->offset = length; /* offset where to start slow */
 475
 476         final = (ctx->flags & BIT(FLAGS_FINUP)) && !ctx->total;
 477
 478         /* next call does not fail... so no unmap in the case of error */
 479         return omap_sham_xmit_dma(dd, sg_dma_address(ctx->sg), length, final);
 480 }
 481
 482 static int omap_sham_update_cpu(struct omap_sham_dev *dd)
 483 {
 484         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 485         int bufcnt;
 486
 487         omap_sham_append_sg(ctx);
 488         bufcnt = ctx->bufcnt;
 489         ctx->bufcnt = 0;
 490
 491         return omap_sham_xmit_cpu(dd, ctx->buffer, bufcnt, 1);
 492 }
 493
 494 static int omap_sham_update_dma_stop(struct omap_sham_dev *dd)
 495 {
 496         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 497
 498         omap_stop_dma(dd->dma_lch);
 499         if (ctx->flags & BIT(FLAGS_SG)) {
 500                 dma_unmap_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE);
 501                 if (ctx->sg->length == ctx->offset) {
 502                         ctx->sg = sg_next(ctx->sg);
 503                         if (ctx->sg)
 504                                 ctx->offset = 0;
 505                 }
 506         } else {
 507                 dma_unmap_single(dd->dev, ctx->dma_addr, ctx->buflen,
 508                                  DMA_TO_DEVICE);
 509         }
 510
 511         return 0;
 512 }
 513
 514 static int omap_sham_init(struct ahash_request *req)
 515 {
 516         struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
 517         struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
 518         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 519         struct omap_sham_dev *dd = NULL, *tmp;
 520
 521         spin_lock_bh(&sham.lock);
 522         if (!tctx->dd) {
 523                 list_for_each_entry(tmp, &sham.dev_list, list) {
 524                         dd = tmp;
 525                         break;
 526                 }
 527                 tctx->dd = dd;
 528         } else {
 529                 dd = tctx->dd;
 530         }
 531         spin_unlock_bh(&sham.lock);
 532
 533         ctx->dd = dd;
 534
 535         ctx->flags = 0;
 536
 537         dev_dbg(dd->dev, "init: digest size: %d\n",
 538                 crypto_ahash_digestsize(tfm));
 539
 540         if (crypto_ahash_digestsize(tfm) == SHA1_DIGEST_SIZE)
 541                 ctx->flags |= BIT(FLAGS_SHA1);
 542
 543         ctx->bufcnt = 0;
 544         ctx->digcnt = 0;
 545         ctx->buflen = BUFLEN;
 546
 547         if (tctx->flags & BIT(FLAGS_HMAC)) {
 548                 struct omap_sham_hmac_ctx *bctx = tctx->base;
 549
 550                 memcpy(ctx->buffer, bctx->ipad, SHA1_MD5_BLOCK_SIZE);
 551                 ctx->bufcnt = SHA1_MD5_BLOCK_SIZE;
 552                 ctx->flags |= BIT(FLAGS_HMAC);
 553         }
 554
 555         return 0;
 556
 557 }
 558
 559 static int omap_sham_update_req(struct omap_sham_dev *dd)
 560 {
 561         struct ahash_request *req = dd->req;
 562         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 563         int err;
 564
 565         dev_dbg(dd->dev, "update_req: total: %u, digcnt: %d, finup: %d\n",
 566                  ctx->total, ctx->digcnt, (ctx->flags & BIT(FLAGS_FINUP)) != 0);
 567
 568         if (ctx->flags & BIT(FLAGS_CPU))
 569                 err = omap_sham_update_cpu(dd);
 570         else
 571                 err = omap_sham_update_dma_start(dd);
 572
 573         /* wait for dma completion before can take more data */
 574         dev_dbg(dd->dev, "update: err: %d, digcnt: %d\n", err, ctx->digcnt);
 575
 576         return err;
 577 }
 578
 579 static int omap_sham_final_req(struct omap_sham_dev *dd)
 580 {
 581         struct ahash_request *req = dd->req;
 582         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 583         int err = 0, use_dma = 1;
 584
 585         if (ctx->bufcnt <= 64)
 586                 /* faster to handle last block with cpu */
 587                 use_dma = 0;
 588
 589         if (use_dma)
 590                 err = omap_sham_xmit_dma_map(dd, ctx, ctx->bufcnt, 1);
 591         else
 592                 err = omap_sham_xmit_cpu(dd, ctx->buffer, ctx->bufcnt, 1);
 593
 594         ctx->bufcnt = 0;
 595
 596         dev_dbg(dd->dev, "final_req: err: %d\n", err);
 597
 598         return err;
 599 }
 600
 601 static int omap_sham_finish_hmac(struct ahash_request *req)
 602 {
 603         struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
 604         struct omap_sham_hmac_ctx *bctx = tctx->base;
 605         int bs = crypto_shash_blocksize(bctx->shash);
 606         int ds = crypto_shash_digestsize(bctx->shash);
 607         struct {
 608                 struct shash_desc shash;
 609                 char ctx[crypto_shash_descsize(bctx->shash)];
 610         } desc;
 611
 612         desc.shash.tfm = bctx->shash;
 613         desc.shash.flags = 0; /* not CRYPTO_TFM_REQ_MAY_SLEEP */
 614
 615         return crypto_shash_init(&desc.shash) ?:
 616                crypto_shash_update(&desc.shash, bctx->opad, bs) ?:
 617                crypto_shash_finup(&desc.shash, req->result, ds, req->result);
 618 }
 619
 620 static int omap_sham_finish(struct ahash_request *req)
 621 {
 622         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 623         struct omap_sham_dev *dd = ctx->dd;
 624         int err = 0;
 625
 626         if (ctx->digcnt) {
 627                 omap_sham_copy_ready_hash(req);
 628                 if (ctx->flags & BIT(FLAGS_HMAC))
 629                         err = omap_sham_finish_hmac(req);
 630         }
 631
 632         dev_dbg(dd->dev, "digcnt: %d, bufcnt: %d\n", ctx->digcnt, ctx->bufcnt);
 633
 634         return err;
 635 }
 636
 637 static void omap_sham_finish_req(struct ahash_request *req, int err)
 638 {
 639         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 640         struct omap_sham_dev *dd = ctx->dd;
 641
 642         if (!err) {
 643                 omap_sham_copy_hash(req, 1);
 644                 if (test_bit(FLAGS_FINAL, &dd->flags))
 645                         err = omap_sham_finish(req);
 646         } else {
 647                 ctx->flags |= BIT(FLAGS_ERROR);
 648         }
 649
 650         clk_disable(dd->iclk);
 651         dd->flags &= ~BIT(FLAGS_BUSY);
 652
 653         if (req->base.complete)
 654                 req->base.complete(&req->base, err);
 655
 656         /* handle new request */
 657         tasklet_schedule(&dd->done_task);
 658 }
 659
 660 static int omap_sham_handle_queue(struct omap_sham_dev *dd,
 661                                   struct ahash_request *req)
 662 {
 663         struct crypto_async_request *async_req, *backlog;
 664         struct omap_sham_reqctx *ctx;
 665         unsigned long flags;
 666         int err = 0, ret = 0;
 667
 668         spin_lock_irqsave(&dd->lock, flags);
 669         if (req)
 670                 ret = ahash_enqueue_request(&dd->queue, req);
 671         if (test_bit(FLAGS_BUSY, &dd->flags)) {
 672                 spin_unlock_irqrestore(&dd->lock, flags);
 673                 return ret;
 674         }
 675         backlog = crypto_get_backlog(&dd->queue);
 676         async_req = crypto_dequeue_request(&dd->queue);
 677         if (async_req)
 678                 set_bit(FLAGS_BUSY, &dd->flags);
 679         spin_unlock_irqrestore(&dd->lock, flags);
 680
 681         if (!async_req)
 682                 return ret;
 683
 684         if (backlog)
 685                 backlog->complete(backlog, -EINPROGRESS);
 686
 687         req = ahash_request_cast(async_req);
 688         dd->req = req;
 689         ctx = ahash_request_ctx(req);
 690
 691         dev_dbg(dd->dev, "handling new req, op: %lu, nbytes: %d\n",
 692                                                 ctx->op, req->nbytes);
 693
 694         err = omap_sham_hw_init(dd);
 695         if (err)
 696                 goto err1;
 697
 698         omap_set_dma_dest_params(dd->dma_lch, 0,
 699                         OMAP_DMA_AMODE_CONSTANT,
 700                         dd->phys_base + SHA_REG_DIN(0), 0, 16);
 701
 702         omap_set_dma_dest_burst_mode(dd->dma_lch,
 703                         OMAP_DMA_DATA_BURST_16);
 704
 705         omap_set_dma_src_burst_mode(dd->dma_lch,
 706                         OMAP_DMA_DATA_BURST_4);
 707
 708         if (ctx->digcnt)
 709                 /* request has changed - restore hash */
 710                 omap_sham_copy_hash(req, 0);
 711
 712         if (ctx->op == OP_UPDATE) {
 713                 err = omap_sham_update_req(dd);
 714                 if (err != -EINPROGRESS && (ctx->flags & BIT(FLAGS_FINUP)))
 715                         /* no final() after finup() */
 716                         err = omap_sham_final_req(dd);
 717         } else if (ctx->op == OP_FINAL) {
 718                 err = omap_sham_final_req(dd);
 719         }
 720 err1:
 721         if (err != -EINPROGRESS)
 722                 /* done_task will not finish it, so do it here */
 723                 omap_sham_finish_req(req, err);
 724
 725         dev_dbg(dd->dev, "exit, err: %d\n", err);
 726
 727         return ret;
 728 }
 729
 730 static int omap_sham_enqueue(struct ahash_request *req, unsigned int op)
 731 {
 732         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 733         struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
 734         struct omap_sham_dev *dd = tctx->dd;
 735
 736         ctx->op = op;
 737
 738         return omap_sham_handle_queue(dd, req);
 739 }
 740
 741 static int omap_sham_update(struct ahash_request *req)
 742 {
 743         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 744
 745         if (!req->nbytes)
 746                 return 0;
 747
 748         ctx->total = req->nbytes;
 749         ctx->sg = req->src;
 750         ctx->offset = 0;
 751
 752         if (ctx->flags & BIT(FLAGS_FINUP)) {
 753                 if ((ctx->digcnt + ctx->bufcnt + ctx->total) < 9) {
 754                         /*
 755                         * OMAP HW accel works only with buffers >= 9
 756                         * will switch to bypass in final()
 757                         * final has the same request and data
 758                         */
 759                         omap_sham_append_sg(ctx);
 760                         return 0;
 761                 } else if (ctx->bufcnt + ctx->total <= SHA1_MD5_BLOCK_SIZE) {
 762                         /*
 763                         * faster to use CPU for short transfers
 764                         */
 765                         ctx->flags |= BIT(FLAGS_CPU);
 766                 }
 767         } else if (ctx->bufcnt + ctx->total < ctx->buflen) {
 768                 omap_sham_append_sg(ctx);
 769                 return 0;
 770         }
 771
 772         return omap_sham_enqueue(req, OP_UPDATE);
 773 }
 774
 775 static int omap_sham_shash_digest(struct crypto_shash *shash, u32 flags,
 776                                   const u8 *data, unsigned int len, u8 *out)
 777 {
 778         struct {
 779                 struct shash_desc shash;
 780                 char ctx[crypto_shash_descsize(shash)];
 781         } desc;
 782
 783         desc.shash.tfm = shash;
 784         desc.shash.flags = flags & CRYPTO_TFM_REQ_MAY_SLEEP;
 785
 786         return crypto_shash_digest(&desc.shash, data, len, out);
 787 }
 788
 789 static int omap_sham_final_shash(struct ahash_request *req)
 790 {
 791         struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
 792         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 793
 794         return omap_sham_shash_digest(tctx->fallback, req->base.flags,
 795                                       ctx->buffer, ctx->bufcnt, req->result);
 796 }
 797
 798 static int omap_sham_final(struct ahash_request *req)
 799 {
 800         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 801
 802         ctx->flags |= BIT(FLAGS_FINUP);
 803
 804         if (ctx->flags & BIT(FLAGS_ERROR))
 805                 return 0; /* uncompleted hash is not needed */
 806
 807         /* OMAP HW accel works only with buffers >= 9 */
 808         /* HMAC is always >= 9 because ipad == block size */
 809         if ((ctx->digcnt + ctx->bufcnt) < 9)
 810                 return omap_sham_final_shash(req);
 811         else if (ctx->bufcnt)
 812                 return omap_sham_enqueue(req, OP_FINAL);
 813
 814         /* copy ready hash (+ finalize hmac) */
 815         return omap_sham_finish(req);
 816 }
 817
 818 static int omap_sham_finup(struct ahash_request *req)
 819 {
 820         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 821         int err1, err2;
 822
 823         ctx->flags |= BIT(FLAGS_FINUP);
 824
 825         err1 = omap_sham_update(req);
 826         if (err1 == -EINPROGRESS || err1 == -EBUSY)
 827                 return err1;
 828         /*
 829          * final() has to be always called to cleanup resources
 830          * even if udpate() failed, except EINPROGRESS
 831          */
 832         err2 = omap_sham_final(req);
 833
 834         return err1 ?: err2;
 835 }
 836
 837 static int omap_sham_digest(struct ahash_request *req)
 838 {
 839         return omap_sham_init(req) ?: omap_sham_finup(req);
 840 }
 841
 842 static int omap_sham_setkey(struct crypto_ahash *tfm, const u8 *key,
 843                       unsigned int keylen)
 844 {
 845         struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
 846         struct omap_sham_hmac_ctx *bctx = tctx->base;
 847         int bs = crypto_shash_blocksize(bctx->shash);
 848         int ds = crypto_shash_digestsize(bctx->shash);
 849         int err, i;
 850         err = crypto_shash_setkey(tctx->fallback, key, keylen);
 851         if (err)
 852                 return err;
 853
 854         if (keylen > bs) {
 855                 err = omap_sham_shash_digest(bctx->shash,
 856                                 crypto_shash_get_flags(bctx->shash),
 857                                 key, keylen, bctx->ipad);
 858                 if (err)
 859                         return err;
 860                 keylen = ds;
 861         } else {
 862                 memcpy(bctx->ipad, key, keylen);
 863         }
 864
 865         memset(bctx->ipad + keylen, 0, bs - keylen);
 866         memcpy(bctx->opad, bctx->ipad, bs);
 867
 868         for (i = 0; i < bs; i++) {
 869                 bctx->ipad[i] ^= 0x36;
 870                 bctx->opad[i] ^= 0x5c;
 871         }
 872
 873         return err;
 874 }
 875
 876 static int omap_sham_cra_init_alg(struct crypto_tfm *tfm, const char *alg_base)
 877 {
 878         struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm);
 879         const char *alg_name = crypto_tfm_alg_name(tfm);
 880
 881         /* Allocate a fallback and abort if it failed. */
 882         tctx->fallback = crypto_alloc_shash(alg_name, 0,
 883                                             CRYPTO_ALG_NEED_FALLBACK);
 884         if (IS_ERR(tctx->fallback)) {
 885                 pr_err("omap-sham: fallback driver '%s' "
 886                                 "could not be loaded.\n", alg_name);
 887                 return PTR_ERR(tctx->fallback);
 888         }
 889
 890         crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
 891                                  sizeof(struct omap_sham_reqctx) + BUFLEN);
 892
 893         if (alg_base) {
 894                 struct omap_sham_hmac_ctx *bctx = tctx->base;
 895                 tctx->flags |= BIT(FLAGS_HMAC);
 896                 bctx->shash = crypto_alloc_shash(alg_base, 0,
 897                                                 CRYPTO_ALG_NEED_FALLBACK);
 898                 if (IS_ERR(bctx->shash)) {
 899                         pr_err("omap-sham: base driver '%s' "
 900                                         "could not be loaded.\n", alg_base);
 901                         crypto_free_shash(tctx->fallback);
 902                         return PTR_ERR(bctx->shash);
 903                 }
 904
 905         }
 906
 907         return 0;
 908 }
 909
 910 static int omap_sham_cra_init(struct crypto_tfm *tfm)
 911 {
 912         return omap_sham_cra_init_alg(tfm, NULL);
 913 }
 914
 915 static int omap_sham_cra_sha1_init(struct crypto_tfm *tfm)
 916 {
 917         return omap_sham_cra_init_alg(tfm, "sha1");
 918 }
 919
 920 static int omap_sham_cra_md5_init(struct crypto_tfm *tfm)
 921 {
 922         return omap_sham_cra_init_alg(tfm, "md5");
 923 }
 924
 925 static void omap_sham_cra_exit(struct crypto_tfm *tfm)
 926 {
 927         struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm);
 928
 929         crypto_free_shash(tctx->fallback);
 930         tctx->fallback = NULL;
 931
 932         if (tctx->flags & BIT(FLAGS_HMAC)) {
 933                 struct omap_sham_hmac_ctx *bctx = tctx->base;
 934                 crypto_free_shash(bctx->shash);
 935         }
 936 }
 937
 938 static struct ahash_alg algs[] = {
 939 {
 940         .init           = omap_sham_init,
 941         .update         = omap_sham_update,
 942         .final          = omap_sham_final,
 943         .finup          = omap_sham_finup,
 944         .digest         = omap_sham_digest,
 945         .halg.digestsize        = SHA1_DIGEST_SIZE,
 946         .halg.base      = {
 947                 .cra_name               = "sha1",
 948                 .cra_driver_name        = "omap-sha1",
 949                 .cra_priority           = 100,
 950                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
 951                                                 CRYPTO_ALG_ASYNC |
 952                                                 CRYPTO_ALG_NEED_FALLBACK,
 953                 .cra_blocksize          = SHA1_BLOCK_SIZE,
 954                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
 955                 .cra_alignmask          = 0,
 956                 .cra_module             = THIS_MODULE,
 957                 .cra_init               = omap_sham_cra_init,
 958                 .cra_exit               = omap_sham_cra_exit,
 959         }
 960 },
 961 {
 962         .init           = omap_sham_init,
 963         .update         = omap_sham_update,
 964         .final          = omap_sham_final,
 965         .finup          = omap_sham_finup,
 966         .digest         = omap_sham_digest,
 967         .halg.digestsize        = MD5_DIGEST_SIZE,
 968         .halg.base      = {
 969                 .cra_name               = "md5",
 970                 .cra_driver_name        = "omap-md5",
 971                 .cra_priority           = 100,
 972                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
 973                                                 CRYPTO_ALG_ASYNC |
 974                                                 CRYPTO_ALG_NEED_FALLBACK,
 975                 .cra_blocksize          = SHA1_BLOCK_SIZE,
 976                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
 977                 .cra_alignmask          = OMAP_ALIGN_MASK,
 978                 .cra_module             = THIS_MODULE,
 979                 .cra_init               = omap_sham_cra_init,
 980                 .cra_exit               = omap_sham_cra_exit,
 981         }
 982 },
 983 {
 984         .init           = omap_sham_init,
 985         .update         = omap_sham_update,
 986         .final          = omap_sham_final,
 987         .finup          = omap_sham_finup,
 988         .digest         = omap_sham_digest,
 989         .setkey         = omap_sham_setkey,
 990         .halg.digestsize        = SHA1_DIGEST_SIZE,
 991         .halg.base      = {
 992                 .cra_name               = "hmac(sha1)",
 993                 .cra_driver_name        = "omap-hmac-sha1",
 994                 .cra_priority           = 100,
 995                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
 996                                                 CRYPTO_ALG_ASYNC |
 997                                                 CRYPTO_ALG_NEED_FALLBACK,
 998                 .cra_blocksize          = SHA1_BLOCK_SIZE,
 999                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1000                                         sizeof(struct omap_sham_hmac_ctx),
1001                 .cra_alignmask          = OMAP_ALIGN_MASK,
1002                 .cra_module             = THIS_MODULE,
1003                 .cra_init               = omap_sham_cra_sha1_init,
1004                 .cra_exit               = omap_sham_cra_exit,
1005         }
1006 },
1007 {
1008         .init           = omap_sham_init,
1009         .update         = omap_sham_update,
1010         .final          = omap_sham_final,
1011         .finup          = omap_sham_finup,
1012         .digest         = omap_sham_digest,
1013         .setkey         = omap_sham_setkey,
1014         .halg.digestsize        = MD5_DIGEST_SIZE,
1015         .halg.base      = {
1016                 .cra_name               = "hmac(md5)",
1017                 .cra_driver_name        = "omap-hmac-md5",
1018                 .cra_priority           = 100,
1019                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1020                                                 CRYPTO_ALG_ASYNC |
1021                                                 CRYPTO_ALG_NEED_FALLBACK,
1022                 .cra_blocksize          = SHA1_BLOCK_SIZE,
1023                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1024                                         sizeof(struct omap_sham_hmac_ctx),
1025                 .cra_alignmask          = OMAP_ALIGN_MASK,
1026                 .cra_module             = THIS_MODULE,
1027                 .cra_init               = omap_sham_cra_md5_init,
1028                 .cra_exit               = omap_sham_cra_exit,
1029         }
1030 }
1031 };
1032
1033 static void omap_sham_done_task(unsigned long data)
1034 {
1035         struct omap_sham_dev *dd = (struct omap_sham_dev *)data;
1036         int ready = 0, err = 0;
1037
1038         if (!test_bit(FLAGS_BUSY, &dd->flags)) {
1039                 omap_sham_handle_queue(dd, NULL);
1040                 return;
1041         }
1042
1043         if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags))
1044                 ready = 1;
1045
1046         if (test_and_clear_bit(FLAGS_DMA_ACTIVE, &dd->flags)) {
1047                 omap_sham_update_dma_stop(dd);
1048                 if (!dd->err)
1049                         err = omap_sham_update_dma_start(dd);
1050         }
1051
1052         err = dd->err ? : err;
1053
1054         if (err != -EINPROGRESS && (ready || err)) {
1055                 dev_dbg(dd->dev, "update done: err: %d\n", err);
1056                 /* finish curent request */
1057                 omap_sham_finish_req(dd->req, err);
1058         }
1059 }
1060
1061 static irqreturn_t omap_sham_irq(int irq, void *dev_id)
1062 {
1063         struct omap_sham_dev *dd = dev_id;
1064
1065         if (unlikely(test_bit(FLAGS_FINAL, &dd->flags)))
1066                 /* final -> allow device to go to power-saving mode */
1067                 omap_sham_write_mask(dd, SHA_REG_CTRL, 0, SHA_REG_CTRL_LENGTH);
1068
1069         omap_sham_write_mask(dd, SHA_REG_CTRL, SHA_REG_CTRL_OUTPUT_READY,
1070                                  SHA_REG_CTRL_OUTPUT_READY);
1071         omap_sham_read(dd, SHA_REG_CTRL);
1072
1073         set_bit(FLAGS_OUTPUT_READY, &dd->flags);
1074         dd->err = 0;
1075         tasklet_schedule(&dd->done_task);
1076
1077         return IRQ_HANDLED;
1078 }
1079
1080 static void omap_sham_dma_callback(int lch, u16 ch_status, void *data)
1081 {
1082         struct omap_sham_dev *dd = data;
1083
1084         if (ch_status != OMAP_DMA_BLOCK_IRQ) {
1085                 pr_err("omap-sham DMA error status: 0x%hx\n", ch_status);
1086                 dd->err = -EIO;
1087                 clear_bit(FLAGS_INIT, &dd->flags);/* request to re-initialize */
1088         }
1089
1090         tasklet_schedule(&dd->done_task);
1091 }
1092
1093 static int omap_sham_dma_init(struct omap_sham_dev *dd)
1094 {
1095         int err;
1096
1097         dd->dma_lch = -1;
1098
1099         err = omap_request_dma(dd->dma, dev_name(dd->dev),
1100                         omap_sham_dma_callback, dd, &dd->dma_lch);
1101         if (err) {
1102                 dev_err(dd->dev, "Unable to request DMA channel\n");
1103                 return err;
1104         }
1105
1106         return 0;
1107 }
1108
1109 static void omap_sham_dma_cleanup(struct omap_sham_dev *dd)
1110 {
1111         if (dd->dma_lch >= 0) {
1112                 omap_free_dma(dd->dma_lch);
1113                 dd->dma_lch = -1;
1114         }
1115 }
1116
1117 static int __devinit omap_sham_probe(struct platform_device *pdev)
1118 {
1119         struct omap_sham_dev *dd;
1120         struct device *dev = &pdev->dev;
1121         struct resource *res;
1122         int err, i, j;
1123
1124         dd = kzalloc(sizeof(struct omap_sham_dev), GFP_KERNEL);
1125         if (dd == NULL) {
1126                 dev_err(dev, "unable to alloc data struct.\n");
1127                 err = -ENOMEM;
1128                 goto data_err;
1129         }
1130         dd->dev = dev;
1131         platform_set_drvdata(pdev, dd);
1132
1133         INIT_LIST_HEAD(&dd->list);
1134         spin_lock_init(&dd->lock);
1135         tasklet_init(&dd->done_task, omap_sham_done_task, (unsigned long)dd);
1136         crypto_init_queue(&dd->queue, OMAP_SHAM_QUEUE_LENGTH);
1137
1138         dd->irq = -1;
1139
1140         /* Get the base address */
1141         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1142         if (!res) {
1143                 dev_err(dev, "no MEM resource info\n");
1144                 err = -ENODEV;
1145                 goto res_err;
1146         }
1147         dd->phys_base = res->start;
1148
1149         /* Get the DMA */
1150         res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1151         if (!res) {
1152                 dev_err(dev, "no DMA resource info\n");
1153                 err = -ENODEV;
1154                 goto res_err;
1155         }
1156         dd->dma = res->start;
1157
1158         /* Get the IRQ */
1159         dd->irq = platform_get_irq(pdev,  0);
1160         if (dd->irq < 0) {
1161                 dev_err(dev, "no IRQ resource info\n");
1162                 err = dd->irq;
1163                 goto res_err;
1164         }
1165
1166         err = request_irq(dd->irq, omap_sham_irq,
1167                         IRQF_TRIGGER_LOW, dev_name(dev), dd);
1168         if (err) {
1169                 dev_err(dev, "unable to request irq.\n");
1170                 goto res_err;
1171         }
1172
1173         err = omap_sham_dma_init(dd);
1174         if (err)
1175                 goto dma_err;
1176
1177         /* Initializing the clock */
1178         dd->iclk = clk_get(dev, "ick");
1179         if (IS_ERR(dd->iclk)) {
1180                 dev_err(dev, "clock intialization failed.\n");
1181                 err = PTR_ERR(dd->iclk);
1182                 goto clk_err;
1183         }
1184
1185         dd->io_base = ioremap(dd->phys_base, SZ_4K);
1186         if (!dd->io_base) {
1187                 dev_err(dev, "can't ioremap\n");
1188                 err = -ENOMEM;
1189                 goto io_err;
1190         }
1191
1192         clk_enable(dd->iclk);
1193         dev_info(dev, "hw accel on OMAP rev %u.%u\n",
1194                 (omap_sham_read(dd, SHA_REG_REV) & SHA_REG_REV_MAJOR) >> 4,
1195                 omap_sham_read(dd, SHA_REG_REV) & SHA_REG_REV_MINOR);
1196         clk_disable(dd->iclk);
1197
1198         spin_lock(&sham.lock);
1199         list_add_tail(&dd->list, &sham.dev_list);
1200         spin_unlock(&sham.lock);
1201
1202         for (i = 0; i < ARRAY_SIZE(algs); i++) {
1203                 err = crypto_register_ahash(&algs[i]);
1204                 if (err)
1205                         goto err_algs;
1206         }
1207
1208         return 0;
1209
1210 err_algs:
1211         for (j = 0; j < i; j++)
1212                 crypto_unregister_ahash(&algs[j]);
1213         iounmap(dd->io_base);
1214 io_err:
1215         clk_put(dd->iclk);
1216 clk_err:
1217         omap_sham_dma_cleanup(dd);
1218 dma_err:
1219         if (dd->irq >= 0)
1220                 free_irq(dd->irq, dd);
1221 res_err:
1222         kfree(dd);
1223         dd = NULL;
1224 data_err:
1225         dev_err(dev, "initialization failed.\n");
1226
1227         return err;
1228 }
1229
1230 static int __devexit omap_sham_remove(struct platform_device *pdev)
1231 {
1232         static struct omap_sham_dev *dd;
1233         int i;
1234
1235         dd = platform_get_drvdata(pdev);
1236         if (!dd)
1237                 return -ENODEV;
1238         spin_lock(&sham.lock);
1239         list_del(&dd->list);
1240         spin_unlock(&sham.lock);
1241         for (i = 0; i < ARRAY_SIZE(algs); i++)
1242                 crypto_unregister_ahash(&algs[i]);
1243         tasklet_kill(&dd->done_task);
1244         iounmap(dd->io_base);
1245         clk_put(dd->iclk);
1246         omap_sham_dma_cleanup(dd);
1247         if (dd->irq >= 0)
1248                 free_irq(dd->irq, dd);
1249         kfree(dd);
1250         dd = NULL;
1251
1252         return 0;
1253 }
1254
1255 static struct platform_driver omap_sham_driver = {
1256         .probe  = omap_sham_probe,
1257         .remove = omap_sham_remove,
1258         .driver = {
1259                 .name   = "omap-sham",
1260                 .owner  = THIS_MODULE,
1261         },
1262 };
1263
1264 static int __init omap_sham_mod_init(void)
1265 {
1266         pr_info("loading %s driver\n", "omap-sham");
1267
1268         if (!cpu_class_is_omap2() ||
1269                 (omap_type() != OMAP2_DEVICE_TYPE_SEC &&
1270                         omap_type() != OMAP2_DEVICE_TYPE_EMU)) {
1271                 pr_err("Unsupported cpu\n");
1272                 return -ENODEV;
1273         }
1274
1275         return platform_driver_register(&omap_sham_driver);
1276 }
1277
1278 static void __exit omap_sham_mod_exit(void)
1279 {
1280         platform_driver_unregister(&omap_sham_driver);
1281 }
1282
1283 module_init(omap_sham_mod_init);
1284 module_exit(omap_sham_mod_exit);
1285
1286 MODULE_DESCRIPTION("OMAP SHA1/MD5 hw acceleration support.");
1287 MODULE_LICENSE("GPL v2");
1288 MODULE_AUTHOR("Dmitry Kasatkin");