drivers/dma/dma-axi-dmac.c

   1 /*
   2  * Driver for the Analog Devices AXI-DMAC core
   3  *
   4  * Copyright 2013-2015 Analog Devices Inc.
   5  *  Author: Lars-Peter Clausen <lars@metafoo.de>
   6  *
   7  * Licensed under the GPL-2.
   8  */
   9
  10 #include <linux/clk.h>
  11 #include <linux/device.h>
  12 #include <linux/dma-mapping.h>
  13 #include <linux/dmaengine.h>
  14 #include <linux/err.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/io.h>
  17 #include <linux/kernel.h>
  18 #include <linux/module.h>
  19 #include <linux/of.h>
  20 #include <linux/of_dma.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/slab.h>
  23
  24 #include <dt-bindings/dma/axi-dmac.h>
  25
  26 #include "dmaengine.h"
  27 #include "virt-dma.h"
  28
  29 /*
  30  * The AXI-DMAC is a soft IP core that is used in FPGA designs. The core has
  31  * various instantiation parameters which decided the exact feature set support
  32  * by the core.
  33  *
  34  * Each channel of the core has a source interface and a destination interface.
  35  * The number of channels and the type of the channel interfaces is selected at
  36  * configuration time. A interface can either be a connected to a central memory
  37  * interconnect, which allows access to system memory, or it can be connected to
  38  * a dedicated bus which is directly connected to a data port on a peripheral.
  39  * Given that those are configuration options of the core that are selected when
  40  * it is instantiated this means that they can not be changed by software at
  41  * runtime. By extension this means that each channel is uni-directional. It can
  42  * either be device to memory or memory to device, but not both. Also since the
  43  * device side is a dedicated data bus only connected to a single peripheral
  44  * there is no address than can or needs to be configured for the device side.
  45  */
  46
  47 #define AXI_DMAC_REG_IRQ_MASK           0x80
  48 #define AXI_DMAC_REG_IRQ_PENDING        0x84
  49 #define AXI_DMAC_REG_IRQ_SOURCE         0x88
  50
  51 #define AXI_DMAC_REG_CTRL               0x400
  52 #define AXI_DMAC_REG_TRANSFER_ID        0x404
  53 #define AXI_DMAC_REG_START_TRANSFER     0x408
  54 #define AXI_DMAC_REG_FLAGS              0x40c
  55 #define AXI_DMAC_REG_DEST_ADDRESS       0x410
  56 #define AXI_DMAC_REG_SRC_ADDRESS        0x414
  57 #define AXI_DMAC_REG_X_LENGTH           0x418
  58 #define AXI_DMAC_REG_Y_LENGTH           0x41c
  59 #define AXI_DMAC_REG_DEST_STRIDE        0x420
  60 #define AXI_DMAC_REG_SRC_STRIDE         0x424
  61 #define AXI_DMAC_REG_TRANSFER_DONE      0x428
  62 #define AXI_DMAC_REG_ACTIVE_TRANSFER_ID 0x42c
  63 #define AXI_DMAC_REG_STATUS             0x430
  64 #define AXI_DMAC_REG_CURRENT_SRC_ADDR   0x434
  65 #define AXI_DMAC_REG_CURRENT_DEST_ADDR  0x438
  66
  67 #define AXI_DMAC_CTRL_ENABLE            BIT(0)
  68 #define AXI_DMAC_CTRL_PAUSE             BIT(1)
  69
  70 #define AXI_DMAC_IRQ_SOT                BIT(0)
  71 #define AXI_DMAC_IRQ_EOT                BIT(1)
  72
  73 #define AXI_DMAC_FLAG_CYCLIC            BIT(0)
  74
  75 struct axi_dmac_sg {
  76         dma_addr_t src_addr;
  77         dma_addr_t dest_addr;
  78         unsigned int x_len;
  79         unsigned int y_len;
  80         unsigned int dest_stride;
  81         unsigned int src_stride;
  82         unsigned int id;
  83 };
  84
  85 struct axi_dmac_desc {
  86         struct virt_dma_desc vdesc;
  87         bool cyclic;
  88
  89         unsigned int num_submitted;
  90         unsigned int num_completed;
  91         unsigned int num_sgs;
  92         struct axi_dmac_sg sg[];
  93 };
  94
  95 struct axi_dmac_chan {
  96         struct virt_dma_chan vchan;
  97
  98         struct axi_dmac_desc *next_desc;
  99         struct list_head active_descs;
 100         enum dma_transfer_direction direction;
 101
 102         unsigned int src_width;
 103         unsigned int dest_width;
 104         unsigned int src_type;
 105         unsigned int dest_type;
 106
 107         unsigned int max_length;
 108         unsigned int align_mask;
 109
 110         bool hw_cyclic;
 111         bool hw_2d;
 112 };
 113
 114 struct axi_dmac {
 115         void __iomem *base;
 116         int irq;
 117
 118         struct clk *clk;
 119
 120         struct dma_device dma_dev;
 121         struct axi_dmac_chan chan;
 122
 123         struct device_dma_parameters dma_parms;
 124 };
 125
 126 static struct axi_dmac *chan_to_axi_dmac(struct axi_dmac_chan *chan)
 127 {
 128         return container_of(chan->vchan.chan.device, struct axi_dmac,
 129                 dma_dev);
 130 }
 131
 132 static struct axi_dmac_chan *to_axi_dmac_chan(struct dma_chan *c)
 133 {
 134         return container_of(c, struct axi_dmac_chan, vchan.chan);
 135 }
 136
 137 static struct axi_dmac_desc *to_axi_dmac_desc(struct virt_dma_desc *vdesc)
 138 {
 139         return container_of(vdesc, struct axi_dmac_desc, vdesc);
 140 }
 141
 142 static void axi_dmac_write(struct axi_dmac *axi_dmac, unsigned int reg,
 143         unsigned int val)
 144 {
 145         writel(val, axi_dmac->base + reg);
 146 }
 147
 148 static int axi_dmac_read(struct axi_dmac *axi_dmac, unsigned int reg)
 149 {
 150         return readl(axi_dmac->base + reg);
 151 }
 152
 153 static int axi_dmac_src_is_mem(struct axi_dmac_chan *chan)
 154 {
 155         return chan->src_type == AXI_DMAC_BUS_TYPE_AXI_MM;
 156 }
 157
 158 static int axi_dmac_dest_is_mem(struct axi_dmac_chan *chan)
 159 {
 160         return chan->dest_type == AXI_DMAC_BUS_TYPE_AXI_MM;
 161 }
 162
 163 static bool axi_dmac_check_len(struct axi_dmac_chan *chan, unsigned int len)
 164 {
 165         if (len == 0 || len > chan->max_length)
 166                 return false;
 167         if ((len & chan->align_mask) != 0) /* Not aligned */
 168                 return false;
 169         return true;
 170 }
 171
 172 static bool axi_dmac_check_addr(struct axi_dmac_chan *chan, dma_addr_t addr)
 173 {
 174         if ((addr & chan->align_mask) != 0) /* Not aligned */
 175                 return false;
 176         return true;
 177 }
 178
 179 static void axi_dmac_start_transfer(struct axi_dmac_chan *chan)
 180 {
 181         struct axi_dmac *dmac = chan_to_axi_dmac(chan);
 182         struct virt_dma_desc *vdesc;
 183         struct axi_dmac_desc *desc;
 184         struct axi_dmac_sg *sg;
 185         unsigned int flags = 0;
 186         unsigned int val;
 187
 188         val = axi_dmac_read(dmac, AXI_DMAC_REG_START_TRANSFER);
 189         if (val) /* Queue is full, wait for the next SOT IRQ */
 190                 return;
 191
 192         desc = chan->next_desc;
 193
 194         if (!desc) {
 195                 vdesc = vchan_next_desc(&chan->vchan);
 196                 if (!vdesc)
 197                         return;
 198                 list_move_tail(&vdesc->node, &chan->active_descs);
 199                 desc = to_axi_dmac_desc(vdesc);
 200         }
 201         sg = &desc->sg[desc->num_submitted];
 202
 203         desc->num_submitted++;
 204         if (desc->num_submitted == desc->num_sgs)
 205                 chan->next_desc = NULL;
 206         else
 207                 chan->next_desc = desc;
 208
 209         sg->id = axi_dmac_read(dmac, AXI_DMAC_REG_TRANSFER_ID);
 210
 211         if (axi_dmac_dest_is_mem(chan)) {
 212                 axi_dmac_write(dmac, AXI_DMAC_REG_DEST_ADDRESS, sg->dest_addr);
 213                 axi_dmac_write(dmac, AXI_DMAC_REG_DEST_STRIDE, sg->dest_stride);
 214         }
 215
 216         if (axi_dmac_src_is_mem(chan)) {
 217                 axi_dmac_write(dmac, AXI_DMAC_REG_SRC_ADDRESS, sg->src_addr);
 218                 axi_dmac_write(dmac, AXI_DMAC_REG_SRC_STRIDE, sg->src_stride);
 219         }
 220
 221         /*
 222          * If the hardware supports cyclic transfers and there is no callback to
 223          * call, enable hw cyclic mode to avoid unnecessary interrupts.
 224          */
 225         if (chan->hw_cyclic && desc->cyclic && !desc->vdesc.tx.callback)
 226                 flags |= AXI_DMAC_FLAG_CYCLIC;
 227
 228         axi_dmac_write(dmac, AXI_DMAC_REG_X_LENGTH, sg->x_len - 1);
 229         axi_dmac_write(dmac, AXI_DMAC_REG_Y_LENGTH, sg->y_len - 1);
 230         axi_dmac_write(dmac, AXI_DMAC_REG_FLAGS, flags);
 231         axi_dmac_write(dmac, AXI_DMAC_REG_START_TRANSFER, 1);
 232 }
 233
 234 static struct axi_dmac_desc *axi_dmac_active_desc(struct axi_dmac_chan *chan)
 235 {
 236         return list_first_entry_or_null(&chan->active_descs,
 237                 struct axi_dmac_desc, vdesc.node);
 238 }
 239
 240 static void axi_dmac_transfer_done(struct axi_dmac_chan *chan,
 241         unsigned int completed_transfers)
 242 {
 243         struct axi_dmac_desc *active;
 244         struct axi_dmac_sg *sg;
 245
 246         active = axi_dmac_active_desc(chan);
 247         if (!active)
 248                 return;
 249
 250         if (active->cyclic) {
 251                 vchan_cyclic_callback(&active->vdesc);
 252         } else {
 253                 do {
 254                         sg = &active->sg[active->num_completed];
 255                         if (!(BIT(sg->id) & completed_transfers))
 256                                 break;
 257                         active->num_completed++;
 258                         if (active->num_completed == active->num_sgs) {
 259                                 list_del(&active->vdesc.node);
 260                                 vchan_cookie_complete(&active->vdesc);
 261                                 active = axi_dmac_active_desc(chan);
 262                         }
 263                 } while (active);
 264         }
 265 }
 266
 267 static irqreturn_t axi_dmac_interrupt_handler(int irq, void *devid)
 268 {
 269         struct axi_dmac *dmac = devid;
 270         unsigned int pending;
 271
 272         pending = axi_dmac_read(dmac, AXI_DMAC_REG_IRQ_PENDING);
 273         axi_dmac_write(dmac, AXI_DMAC_REG_IRQ_PENDING, pending);
 274
 275         spin_lock(&dmac->chan.vchan.lock);
 276         /* One or more transfers have finished */
 277         if (pending & AXI_DMAC_IRQ_EOT) {
 278                 unsigned int completed;
 279
 280                 completed = axi_dmac_read(dmac, AXI_DMAC_REG_TRANSFER_DONE);
 281                 axi_dmac_transfer_done(&dmac->chan, completed);
 282         }
 283         /* Space has become available in the descriptor queue */
 284         if (pending & AXI_DMAC_IRQ_SOT)
 285                 axi_dmac_start_transfer(&dmac->chan);
 286         spin_unlock(&dmac->chan.vchan.lock);
 287
 288         return IRQ_HANDLED;
 289 }
 290
 291 static int axi_dmac_terminate_all(struct dma_chan *c)
 292 {
 293         struct axi_dmac_chan *chan = to_axi_dmac_chan(c);
 294         struct axi_dmac *dmac = chan_to_axi_dmac(chan);
 295         unsigned long flags;
 296         LIST_HEAD(head);
 297
 298         spin_lock_irqsave(&chan->vchan.lock, flags);
 299         axi_dmac_write(dmac, AXI_DMAC_REG_CTRL, 0);
 300         chan->next_desc = NULL;
 301         vchan_get_all_descriptors(&chan->vchan, &head);
 302         list_splice_tail_init(&chan->active_descs, &head);
 303         spin_unlock_irqrestore(&chan->vchan.lock, flags);
 304
 305         vchan_dma_desc_free_list(&chan->vchan, &head);
 306
 307         return 0;
 308 }
 309
 310 static void axi_dmac_synchronize(struct dma_chan *c)
 311 {
 312         struct axi_dmac_chan *chan = to_axi_dmac_chan(c);
 313
 314         vchan_synchronize(&chan->vchan);
 315 }
 316
 317 static void axi_dmac_issue_pending(struct dma_chan *c)
 318 {
 319         struct axi_dmac_chan *chan = to_axi_dmac_chan(c);
 320         struct axi_dmac *dmac = chan_to_axi_dmac(chan);
 321         unsigned long flags;
 322
 323         axi_dmac_write(dmac, AXI_DMAC_REG_CTRL, AXI_DMAC_CTRL_ENABLE);
 324
 325         spin_lock_irqsave(&chan->vchan.lock, flags);
 326         if (vchan_issue_pending(&chan->vchan))
 327                 axi_dmac_start_transfer(chan);
 328         spin_unlock_irqrestore(&chan->vchan.lock, flags);
 329 }
 330
 331 static struct axi_dmac_desc *axi_dmac_alloc_desc(unsigned int num_sgs)
 332 {
 333         struct axi_dmac_desc *desc;
 334
 335         desc = kzalloc(sizeof(struct axi_dmac_desc) +
 336                 sizeof(struct axi_dmac_sg) * num_sgs, GFP_NOWAIT);
 337         if (!desc)
 338                 return NULL;
 339
 340         desc->num_sgs = num_sgs;
 341
 342         return desc;
 343 }
 344
 345 static struct dma_async_tx_descriptor *axi_dmac_prep_slave_sg(
 346         struct dma_chan *c, struct scatterlist *sgl,
 347         unsigned int sg_len, enum dma_transfer_direction direction,
 348         unsigned long flags, void *context)
 349 {
 350         struct axi_dmac_chan *chan = to_axi_dmac_chan(c);
 351         struct axi_dmac_desc *desc;
 352         struct scatterlist *sg;
 353         unsigned int i;
 354
 355         if (direction != chan->direction)
 356                 return NULL;
 357
 358         desc = axi_dmac_alloc_desc(sg_len);
 359         if (!desc)
 360                 return NULL;
 361
 362         for_each_sg(sgl, sg, sg_len, i) {
 363                 if (!axi_dmac_check_addr(chan, sg_dma_address(sg)) ||
 364                     !axi_dmac_check_len(chan, sg_dma_len(sg))) {
 365                         kfree(desc);
 366                         return NULL;
 367                 }
 368
 369                 if (direction == DMA_DEV_TO_MEM)
 370                         desc->sg[i].dest_addr = sg_dma_address(sg);
 371                 else
 372                         desc->sg[i].src_addr = sg_dma_address(sg);
 373                 desc->sg[i].x_len = sg_dma_len(sg);
 374                 desc->sg[i].y_len = 1;
 375         }
 376
 377         desc->cyclic = false;
 378
 379         return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
 380 }
 381
 382 static struct dma_async_tx_descriptor *axi_dmac_prep_dma_cyclic(
 383         struct dma_chan *c, dma_addr_t buf_addr, size_t buf_len,
 384         size_t period_len, enum dma_transfer_direction direction,
 385         unsigned long flags)
 386 {
 387         struct axi_dmac_chan *chan = to_axi_dmac_chan(c);
 388         struct axi_dmac_desc *desc;
 389         unsigned int num_periods, i;
 390
 391         if (direction != chan->direction)
 392                 return NULL;
 393
 394         if (!axi_dmac_check_len(chan, buf_len) ||
 395             !axi_dmac_check_addr(chan, buf_addr))
 396                 return NULL;
 397
 398         if (period_len == 0 || buf_len % period_len)
 399                 return NULL;
 400
 401         num_periods = buf_len / period_len;
 402
 403         desc = axi_dmac_alloc_desc(num_periods);
 404         if (!desc)
 405                 return NULL;
 406
 407         for (i = 0; i < num_periods; i++) {
 408                 if (direction == DMA_DEV_TO_MEM)
 409                         desc->sg[i].dest_addr = buf_addr;
 410                 else
 411                         desc->sg[i].src_addr = buf_addr;
 412                 desc->sg[i].x_len = period_len;
 413                 desc->sg[i].y_len = 1;
 414                 buf_addr += period_len;
 415         }
 416
 417         desc->cyclic = true;
 418
 419         return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
 420 }
 421
 422 static struct dma_async_tx_descriptor *axi_dmac_prep_interleaved(
 423         struct dma_chan *c, struct dma_interleaved_template *xt,
 424         unsigned long flags)
 425 {
 426         struct axi_dmac_chan *chan = to_axi_dmac_chan(c);
 427         struct axi_dmac_desc *desc;
 428         size_t dst_icg, src_icg;
 429
 430         if (xt->frame_size != 1)
 431                 return NULL;
 432
 433         if (xt->dir != chan->direction)
 434                 return NULL;
 435
 436         if (axi_dmac_src_is_mem(chan)) {
 437                 if (!xt->src_inc || !axi_dmac_check_addr(chan, xt->src_start))
 438                         return NULL;
 439         }
 440
 441         if (axi_dmac_dest_is_mem(chan)) {
 442                 if (!xt->dst_inc || !axi_dmac_check_addr(chan, xt->dst_start))
 443                         return NULL;
 444         }
 445
 446         dst_icg = dmaengine_get_dst_icg(xt, &xt->sgl[0]);
 447         src_icg = dmaengine_get_src_icg(xt, &xt->sgl[0]);
 448
 449         if (chan->hw_2d) {
 450                 if (!axi_dmac_check_len(chan, xt->sgl[0].size) ||
 451                     !axi_dmac_check_len(chan, xt->numf))
 452                         return NULL;
 453                 if (xt->sgl[0].size + dst_icg > chan->max_length ||
 454                     xt->sgl[0].size + src_icg > chan->max_length)
 455                         return NULL;
 456         } else {
 457                 if (dst_icg != 0 || src_icg != 0)
 458                         return NULL;
 459                 if (chan->max_length / xt->sgl[0].size < xt->numf)
 460                         return NULL;
 461                 if (!axi_dmac_check_len(chan, xt->sgl[0].size * xt->numf))
 462                         return NULL;
 463         }
 464
 465         desc = axi_dmac_alloc_desc(1);
 466         if (!desc)
 467                 return NULL;
 468
 469         if (axi_dmac_src_is_mem(chan)) {
 470                 desc->sg[0].src_addr = xt->src_start;
 471                 desc->sg[0].src_stride = xt->sgl[0].size + src_icg;
 472         }
 473
 474         if (axi_dmac_dest_is_mem(chan)) {
 475                 desc->sg[0].dest_addr = xt->dst_start;
 476                 desc->sg[0].dest_stride = xt->sgl[0].size + dst_icg;
 477         }
 478
 479         if (chan->hw_2d) {
 480                 desc->sg[0].x_len = xt->sgl[0].size;
 481                 desc->sg[0].y_len = xt->numf;
 482         } else {
 483                 desc->sg[0].x_len = xt->sgl[0].size * xt->numf;
 484                 desc->sg[0].y_len = 1;
 485         }
 486
 487         return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
 488 }
 489
 490 static void axi_dmac_free_chan_resources(struct dma_chan *c)
 491 {
 492         vchan_free_chan_resources(to_virt_chan(c));
 493 }
 494
 495 static void axi_dmac_desc_free(struct virt_dma_desc *vdesc)
 496 {
 497         kfree(container_of(vdesc, struct axi_dmac_desc, vdesc));
 498 }
 499
 500 /*
 501  * The configuration stored in the devicetree matches the configuration
 502  * parameters of the peripheral instance and allows the driver to know which
 503  * features are implemented and how it should behave.
 504  */
 505 static int axi_dmac_parse_chan_dt(struct device_node *of_chan,
 506         struct axi_dmac_chan *chan)
 507 {
 508         u32 val;
 509         int ret;
 510
 511         ret = of_property_read_u32(of_chan, "reg", &val);
 512         if (ret)
 513                 return ret;
 514
 515         /* We only support 1 channel for now */
 516         if (val != 0)
 517                 return -EINVAL;
 518
 519         ret = of_property_read_u32(of_chan, "adi,source-bus-type", &val);
 520         if (ret)
 521                 return ret;
 522         if (val > AXI_DMAC_BUS_TYPE_FIFO)
 523                 return -EINVAL;
 524         chan->src_type = val;
 525
 526         ret = of_property_read_u32(of_chan, "adi,destination-bus-type", &val);
 527         if (ret)
 528                 return ret;
 529         if (val > AXI_DMAC_BUS_TYPE_FIFO)
 530                 return -EINVAL;
 531         chan->dest_type = val;
 532
 533         ret = of_property_read_u32(of_chan, "adi,source-bus-width", &val);
 534         if (ret)
 535                 return ret;
 536         chan->src_width = val / 8;
 537
 538         ret = of_property_read_u32(of_chan, "adi,destination-bus-width", &val);
 539         if (ret)
 540                 return ret;
 541         chan->dest_width = val / 8;
 542
 543         ret = of_property_read_u32(of_chan, "adi,length-width", &val);
 544         if (ret)
 545                 return ret;
 546
 547         if (val >= 32)
 548                 chan->max_length = UINT_MAX;
 549         else
 550                 chan->max_length = (1ULL << val) - 1;
 551
 552         chan->align_mask = max(chan->dest_width, chan->src_width) - 1;
 553
 554         if (axi_dmac_dest_is_mem(chan) && axi_dmac_src_is_mem(chan))
 555                 chan->direction = DMA_MEM_TO_MEM;
 556         else if (!axi_dmac_dest_is_mem(chan) && axi_dmac_src_is_mem(chan))
 557                 chan->direction = DMA_MEM_TO_DEV;
 558         else if (axi_dmac_dest_is_mem(chan) && !axi_dmac_src_is_mem(chan))
 559                 chan->direction = DMA_DEV_TO_MEM;
 560         else
 561                 chan->direction = DMA_DEV_TO_DEV;
 562
 563         chan->hw_cyclic = of_property_read_bool(of_chan, "adi,cyclic");
 564         chan->hw_2d = of_property_read_bool(of_chan, "adi,2d");
 565
 566         return 0;
 567 }
 568
 569 static int axi_dmac_probe(struct platform_device *pdev)
 570 {
 571         struct device_node *of_channels, *of_chan;
 572         struct dma_device *dma_dev;
 573         struct axi_dmac *dmac;
 574         struct resource *res;
 575         int ret;
 576
 577         dmac = devm_kzalloc(&pdev->dev, sizeof(*dmac), GFP_KERNEL);
 578         if (!dmac)
 579                 return -ENOMEM;
 580
 581         dmac->irq = platform_get_irq(pdev, 0);
 582         if (dmac->irq <= 0)
 583                 return -EINVAL;
 584
 585         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 586         dmac->base = devm_ioremap_resource(&pdev->dev, res);
 587         if (IS_ERR(dmac->base))
 588                 return PTR_ERR(dmac->base);
 589
 590         dmac->clk = devm_clk_get(&pdev->dev, NULL);
 591         if (IS_ERR(dmac->clk))
 592                 return PTR_ERR(dmac->clk);
 593
 594         INIT_LIST_HEAD(&dmac->chan.active_descs);
 595
 596         of_channels = of_get_child_by_name(pdev->dev.of_node, "adi,channels");
 597         if (of_channels == NULL)
 598                 return -ENODEV;
 599
 600         for_each_child_of_node(of_channels, of_chan) {
 601                 ret = axi_dmac_parse_chan_dt(of_chan, &dmac->chan);
 602                 if (ret) {
 603                         of_node_put(of_chan);
 604                         of_node_put(of_channels);
 605                         return -EINVAL;
 606                 }
 607         }
 608         of_node_put(of_channels);
 609
 610         pdev->dev.dma_parms = &dmac->dma_parms;
 611         dma_set_max_seg_size(&pdev->dev, dmac->chan.max_length);
 612
 613         dma_dev = &dmac->dma_dev;
 614         dma_cap_set(DMA_SLAVE, dma_dev->cap_mask);
 615         dma_cap_set(DMA_CYCLIC, dma_dev->cap_mask);
 616         dma_dev->device_free_chan_resources = axi_dmac_free_chan_resources;
 617         dma_dev->device_tx_status = dma_cookie_status;
 618         dma_dev->device_issue_pending = axi_dmac_issue_pending;
 619         dma_dev->device_prep_slave_sg = axi_dmac_prep_slave_sg;
 620         dma_dev->device_prep_dma_cyclic = axi_dmac_prep_dma_cyclic;
 621         dma_dev->device_prep_interleaved_dma = axi_dmac_prep_interleaved;
 622         dma_dev->device_terminate_all = axi_dmac_terminate_all;
 623         dma_dev->device_synchronize = axi_dmac_synchronize;
 624         dma_dev->dev = &pdev->dev;
 625         dma_dev->chancnt = 1;
 626         dma_dev->src_addr_widths = BIT(dmac->chan.src_width);
 627         dma_dev->dst_addr_widths = BIT(dmac->chan.dest_width);
 628         dma_dev->directions = BIT(dmac->chan.direction);
 629         dma_dev->residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR;
 630         INIT_LIST_HEAD(&dma_dev->channels);
 631
 632         dmac->chan.vchan.desc_free = axi_dmac_desc_free;
 633         vchan_init(&dmac->chan.vchan, dma_dev);
 634
 635         ret = clk_prepare_enable(dmac->clk);
 636         if (ret < 0)
 637                 return ret;
 638
 639         axi_dmac_write(dmac, AXI_DMAC_REG_IRQ_MASK, 0x00);
 640
 641         ret = dma_async_device_register(dma_dev);
 642         if (ret)
 643                 goto err_clk_disable;
 644
 645         ret = of_dma_controller_register(pdev->dev.of_node,
 646                 of_dma_xlate_by_chan_id, dma_dev);
 647         if (ret)
 648                 goto err_unregister_device;
 649
 650         ret = request_irq(dmac->irq, axi_dmac_interrupt_handler, 0,
 651                 dev_name(&pdev->dev), dmac);
 652         if (ret)
 653                 goto err_unregister_of;
 654
 655         platform_set_drvdata(pdev, dmac);
 656
 657         return 0;
 658
 659 err_unregister_of:
 660         of_dma_controller_free(pdev->dev.of_node);
 661 err_unregister_device:
 662         dma_async_device_unregister(&dmac->dma_dev);
 663 err_clk_disable:
 664         clk_disable_unprepare(dmac->clk);
 665
 666         return ret;
 667 }
 668
 669 static int axi_dmac_remove(struct platform_device *pdev)
 670 {
 671         struct axi_dmac *dmac = platform_get_drvdata(pdev);
 672
 673         of_dma_controller_free(pdev->dev.of_node);
 674         free_irq(dmac->irq, dmac);
 675         tasklet_kill(&dmac->chan.vchan.task);
 676         dma_async_device_unregister(&dmac->dma_dev);
 677         clk_disable_unprepare(dmac->clk);
 678
 679         return 0;
 680 }
 681
 682 static const struct of_device_id axi_dmac_of_match_table[] = {
 683         { .compatible = "adi,axi-dmac-1.00.a" },
 684         { },
 685 };
 686
 687 static struct platform_driver axi_dmac_driver = {
 688         .driver = {
 689                 .name = "dma-axi-dmac",
 690                 .of_match_table = axi_dmac_of_match_table,
 691         },
 692         .probe = axi_dmac_probe,
 693         .remove = axi_dmac_remove,
 694 };
 695 module_platform_driver(axi_dmac_driver);
 696
 697 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
 698 MODULE_DESCRIPTION("DMA controller driver for the AXI-DMAC controller");
 699 MODULE_LICENSE("GPL v2");