drivers/dma/edma.c

   1 /*
   2  * TI EDMA DMA engine driver
   3  *
   4  * Copyright 2012 Texas Instruments
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation version 2.
   9  *
  10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11  * kind, whether express or implied; without even the implied warranty
  12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/dmaengine.h>
  17 #include <linux/dma-mapping.h>
  18 #include <linux/err.h>
  19 #include <linux/init.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/list.h>
  22 #include <linux/module.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/slab.h>
  25 #include <linux/spinlock.h>
  26
  27 #include <linux/platform_data/edma.h>
  28
  29 #include "dmaengine.h"
  30 #include "virt-dma.h"
  31
  32 /*
  33  * This will go away when the private EDMA API is folded
  34  * into this driver and the platform device(s) are
  35  * instantiated in the arch code. We can only get away
  36  * with this simplification because DA8XX may not be built
  37  * in the same kernel image with other DaVinci parts. This
  38  * avoids having to sprinkle dmaengine driver platform devices
  39  * and data throughout all the existing board files.
  40  */
  41 #ifdef CONFIG_ARCH_DAVINCI_DA8XX
  42 #define EDMA_CTLRS      2
  43 #define EDMA_CHANS      32
  44 #else
  45 #define EDMA_CTLRS      1
  46 #define EDMA_CHANS      64
  47 #endif /* CONFIG_ARCH_DAVINCI_DA8XX */
  48
  49 /* Max of 16 segments per channel to conserve PaRAM slots */
  50 #define MAX_NR_SG               16
  51 #define EDMA_MAX_SLOTS          MAX_NR_SG
  52 #define EDMA_DESCRIPTORS        16
  53
  54 struct edma_desc {
  55         struct virt_dma_desc            vdesc;
  56         struct list_head                node;
  57         int                             absync;
  58         int                             pset_nr;
  59         int                             processed;
  60         struct edmacc_param             pset[0];
  61 };
  62
  63 struct edma_cc;
  64
  65 struct edma_chan {
  66         struct virt_dma_chan            vchan;
  67         struct list_head                node;
  68         struct edma_desc                *edesc;
  69         struct edma_cc                  *ecc;
  70         int                             ch_num;
  71         bool                            alloced;
  72         int                             slot[EDMA_MAX_SLOTS];
  73         struct dma_slave_config         cfg;
  74 };
  75
  76 struct edma_cc {
  77         int                             ctlr;
  78         struct dma_device               dma_slave;
  79         struct edma_chan                slave_chans[EDMA_CHANS];
  80         int                             num_slave_chans;
  81         int                             dummy_slot;
  82 };
  83
  84 static inline struct edma_cc *to_edma_cc(struct dma_device *d)
  85 {
  86         return container_of(d, struct edma_cc, dma_slave);
  87 }
  88
  89 static inline struct edma_chan *to_edma_chan(struct dma_chan *c)
  90 {
  91         return container_of(c, struct edma_chan, vchan.chan);
  92 }
  93
  94 static inline struct edma_desc
  95 *to_edma_desc(struct dma_async_tx_descriptor *tx)
  96 {
  97         return container_of(tx, struct edma_desc, vdesc.tx);
  98 }
  99
 100 static void edma_desc_free(struct virt_dma_desc *vdesc)
 101 {
 102         kfree(container_of(vdesc, struct edma_desc, vdesc));
 103 }
 104
 105 /* Dispatch a queued descriptor to the controller (caller holds lock) */
 106 static void edma_execute(struct edma_chan *echan)
 107 {
 108         struct virt_dma_desc *vdesc;
 109         struct edma_desc *edesc;
 110         struct device *dev = echan->vchan.chan.device->dev;
 111         int i, j, left, nslots;
 112
 113         /* If either we processed all psets or we're still not started */
 114         if (!echan->edesc ||
 115             echan->edesc->pset_nr == echan->edesc->processed) {
 116                 /* Get next vdesc */
 117                 vdesc = vchan_next_desc(&echan->vchan);
 118                 if (!vdesc) {
 119                         echan->edesc = NULL;
 120                         return;
 121                 }
 122                 list_del(&vdesc->node);
 123                 echan->edesc = to_edma_desc(&vdesc->tx);
 124         }
 125
 126         edesc = echan->edesc;
 127
 128         /* Find out how many left */
 129         left = edesc->pset_nr - edesc->processed;
 130         nslots = min(MAX_NR_SG, left);
 131
 132         /* Write descriptor PaRAM set(s) */
 133         for (i = 0; i < nslots; i++) {
 134                 j = i + edesc->processed;
 135                 edma_write_slot(echan->slot[i], &edesc->pset[j]);
 136                 dev_dbg(echan->vchan.chan.device->dev,
 137                         "\n pset[%d]:\n"
 138                         "  chnum\t%d\n"
 139                         "  slot\t%d\n"
 140                         "  opt\t%08x\n"
 141                         "  src\t%08x\n"
 142                         "  dst\t%08x\n"
 143                         "  abcnt\t%08x\n"
 144                         "  ccnt\t%08x\n"
 145                         "  bidx\t%08x\n"
 146                         "  cidx\t%08x\n"
 147                         "  lkrld\t%08x\n",
 148                         j, echan->ch_num, echan->slot[i],
 149                         edesc->pset[j].opt,
 150                         edesc->pset[j].src,
 151                         edesc->pset[j].dst,
 152                         edesc->pset[j].a_b_cnt,
 153                         edesc->pset[j].ccnt,
 154                         edesc->pset[j].src_dst_bidx,
 155                         edesc->pset[j].src_dst_cidx,
 156                         edesc->pset[j].link_bcntrld);
 157                 /* Link to the previous slot if not the last set */
 158                 if (i != (nslots - 1))
 159                         edma_link(echan->slot[i], echan->slot[i+1]);
 160                 /* Final pset links to the dummy pset */
 161                 else
 162                         edma_link(echan->slot[i], echan->ecc->dummy_slot);
 163         }
 164
 165         edesc->processed += nslots;
 166
 167         edma_resume(echan->ch_num);
 168
 169         if (edesc->processed <= MAX_NR_SG) {
 170                 dev_dbg(dev, "first transfer starting %d\n", echan->ch_num);
 171                 edma_start(echan->ch_num);
 172         }
 173 }
 174
 175 static int edma_terminate_all(struct edma_chan *echan)
 176 {
 177         unsigned long flags;
 178         LIST_HEAD(head);
 179
 180         spin_lock_irqsave(&echan->vchan.lock, flags);
 181
 182         /*
 183          * Stop DMA activity: we assume the callback will not be called
 184          * after edma_dma() returns (even if it does, it will see
 185          * echan->edesc is NULL and exit.)
 186          */
 187         if (echan->edesc) {
 188                 echan->edesc = NULL;
 189                 edma_stop(echan->ch_num);
 190         }
 191
 192         vchan_get_all_descriptors(&echan->vchan, &head);
 193         spin_unlock_irqrestore(&echan->vchan.lock, flags);
 194         vchan_dma_desc_free_list(&echan->vchan, &head);
 195
 196         return 0;
 197 }
 198
 199 static int edma_slave_config(struct edma_chan *echan,
 200         struct dma_slave_config *cfg)
 201 {
 202         if (cfg->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES ||
 203             cfg->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES)
 204                 return -EINVAL;
 205
 206         memcpy(&echan->cfg, cfg, sizeof(echan->cfg));
 207
 208         return 0;
 209 }
 210
 211 static int edma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 212                         unsigned long arg)
 213 {
 214         int ret = 0;
 215         struct dma_slave_config *config;
 216         struct edma_chan *echan = to_edma_chan(chan);
 217
 218         switch (cmd) {
 219         case DMA_TERMINATE_ALL:
 220                 edma_terminate_all(echan);
 221                 break;
 222         case DMA_SLAVE_CONFIG:
 223                 config = (struct dma_slave_config *)arg;
 224                 ret = edma_slave_config(echan, config);
 225                 break;
 226         default:
 227                 ret = -ENOSYS;
 228         }
 229
 230         return ret;
 231 }
 232
 233 static struct dma_async_tx_descriptor *edma_prep_slave_sg(
 234         struct dma_chan *chan, struct scatterlist *sgl,
 235         unsigned int sg_len, enum dma_transfer_direction direction,
 236         unsigned long tx_flags, void *context)
 237 {
 238         struct edma_chan *echan = to_edma_chan(chan);
 239         struct device *dev = chan->device->dev;
 240         struct edma_desc *edesc;
 241         dma_addr_t dev_addr;
 242         enum dma_slave_buswidth dev_width;
 243         u32 burst;
 244         struct scatterlist *sg;
 245         int acnt, bcnt, ccnt, src, dst, cidx;
 246         int src_bidx, dst_bidx, src_cidx, dst_cidx;
 247         int i, nslots;
 248
 249         if (unlikely(!echan || !sgl || !sg_len))
 250                 return NULL;
 251
 252         if (direction == DMA_DEV_TO_MEM) {
 253                 dev_addr = echan->cfg.src_addr;
 254                 dev_width = echan->cfg.src_addr_width;
 255                 burst = echan->cfg.src_maxburst;
 256         } else if (direction == DMA_MEM_TO_DEV) {
 257                 dev_addr = echan->cfg.dst_addr;
 258                 dev_width = echan->cfg.dst_addr_width;
 259                 burst = echan->cfg.dst_maxburst;
 260         } else {
 261                 dev_err(dev, "%s: bad direction?\n", __func__);
 262                 return NULL;
 263         }
 264
 265         if (dev_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) {
 266                 dev_err(dev, "Undefined slave buswidth\n");
 267                 return NULL;
 268         }
 269
 270         if (sg_len > MAX_NR_SG) {
 271                 dev_err(dev, "Exceeded max SG segments %d > %d\n",
 272                         sg_len, MAX_NR_SG);
 273                 return NULL;
 274         }
 275
 276         edesc = kzalloc(sizeof(*edesc) + sg_len *
 277                 sizeof(edesc->pset[0]), GFP_ATOMIC);
 278         if (!edesc) {
 279                 dev_dbg(dev, "Failed to allocate a descriptor\n");
 280                 return NULL;
 281         }
 282
 283         edesc->pset_nr = sg_len;
 284
 285         /* Allocate a PaRAM slot, if needed */
 286         nslots = min_t(unsigned, MAX_NR_SG, sg_len);
 287
 288         for (i = 0; i < nslots; i++) {
 289                 if (echan->slot[i] < 0) {
 290                         echan->slot[i] =
 291                                 edma_alloc_slot(EDMA_CTLR(echan->ch_num),
 292                                                 EDMA_SLOT_ANY);
 293                         if (echan->slot[i] < 0) {
 294                                 dev_err(dev, "Failed to allocate slot\n");
 295                                 return NULL;
 296                         }
 297                 }
 298         }
 299
 300         /* Configure PaRAM sets for each SG */
 301         for_each_sg(sgl, sg, sg_len, i) {
 302
 303                 acnt = dev_width;
 304
 305                 /*
 306                  * If the maxburst is equal to the fifo width, use
 307                  * A-synced transfers. This allows for large contiguous
 308                  * buffer transfers using only one PaRAM set.
 309                  */
 310                 if (burst == 1) {
 311                         edesc->absync = false;
 312                         ccnt = sg_dma_len(sg) / acnt / (SZ_64K - 1);
 313                         bcnt = sg_dma_len(sg) / acnt - ccnt * (SZ_64K - 1);
 314                         if (bcnt)
 315                                 ccnt++;
 316                         else
 317                                 bcnt = SZ_64K - 1;
 318                         cidx = acnt;
 319                 /*
 320                  * If maxburst is greater than the fifo address_width,
 321                  * use AB-synced transfers where A count is the fifo
 322                  * address_width and B count is the maxburst. In this
 323                  * case, we are limited to transfers of C count frames
 324                  * of (address_width * maxburst) where C count is limited
 325                  * to SZ_64K-1. This places an upper bound on the length
 326                  * of an SG segment that can be handled.
 327                  */
 328                 } else {
 329                         edesc->absync = true;
 330                         bcnt = burst;
 331                         ccnt = sg_dma_len(sg) / (acnt * bcnt);
 332                         if (ccnt > (SZ_64K - 1)) {
 333                                 dev_err(dev, "Exceeded max SG segment size\n");
 334                                 return NULL;
 335                         }
 336                         cidx = acnt * bcnt;
 337                 }
 338
 339                 if (direction == DMA_MEM_TO_DEV) {
 340                         src = sg_dma_address(sg);
 341                         dst = dev_addr;
 342                         src_bidx = acnt;
 343                         src_cidx = cidx;
 344                         dst_bidx = 0;
 345                         dst_cidx = 0;
 346                 } else {
 347                         src = dev_addr;
 348                         dst = sg_dma_address(sg);
 349                         src_bidx = 0;
 350                         src_cidx = 0;
 351                         dst_bidx = acnt;
 352                         dst_cidx = cidx;
 353                 }
 354
 355                 edesc->pset[i].opt = EDMA_TCC(EDMA_CHAN_SLOT(echan->ch_num));
 356                 /* Configure A or AB synchronized transfers */
 357                 if (edesc->absync)
 358                         edesc->pset[i].opt |= SYNCDIM;
 359
 360                 /* If this is the last in a current SG set of transactions,
 361                    enable interrupts so that next set is processed */
 362                 if (!((i+1) % MAX_NR_SG))
 363                         edesc->pset[i].opt |= TCINTEN;
 364
 365                 /* If this is the last set, enable completion interrupt flag */
 366                 if (i == sg_len - 1)
 367                         edesc->pset[i].opt |= TCINTEN;
 368
 369                 edesc->pset[i].src = src;
 370                 edesc->pset[i].dst = dst;
 371
 372                 edesc->pset[i].src_dst_bidx = (dst_bidx << 16) | src_bidx;
 373                 edesc->pset[i].src_dst_cidx = (dst_cidx << 16) | src_cidx;
 374
 375                 edesc->pset[i].a_b_cnt = bcnt << 16 | acnt;
 376                 edesc->pset[i].ccnt = ccnt;
 377                 edesc->pset[i].link_bcntrld = 0xffffffff;
 378
 379         }
 380
 381         return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
 382 }
 383
 384 static void edma_callback(unsigned ch_num, u16 ch_status, void *data)
 385 {
 386         struct edma_chan *echan = data;
 387         struct device *dev = echan->vchan.chan.device->dev;
 388         struct edma_desc *edesc;
 389         unsigned long flags;
 390
 391         /* Pause the channel */
 392         edma_pause(echan->ch_num);
 393
 394         switch (ch_status) {
 395         case DMA_COMPLETE:
 396                 spin_lock_irqsave(&echan->vchan.lock, flags);
 397
 398                 edesc = echan->edesc;
 399                 if (edesc) {
 400                         if (edesc->processed == edesc->pset_nr) {
 401                                 dev_dbg(dev, "Transfer complete, stopping channel %d\n", ch_num);
 402                                 edma_stop(echan->ch_num);
 403                                 vchan_cookie_complete(&edesc->vdesc);
 404                         } else {
 405                                 dev_dbg(dev, "Intermediate transfer complete on channel %d\n", ch_num);
 406                         }
 407
 408                         edma_execute(echan);
 409                 }
 410
 411                 spin_unlock_irqrestore(&echan->vchan.lock, flags);
 412
 413                 break;
 414         case DMA_CC_ERROR:
 415                 dev_dbg(dev, "transfer error on channel %d\n", ch_num);
 416                 break;
 417         default:
 418                 break;
 419         }
 420 }
 421
 422 /* Alloc channel resources */
 423 static int edma_alloc_chan_resources(struct dma_chan *chan)
 424 {
 425         struct edma_chan *echan = to_edma_chan(chan);
 426         struct device *dev = chan->device->dev;
 427         int ret;
 428         int a_ch_num;
 429         LIST_HEAD(descs);
 430
 431         a_ch_num = edma_alloc_channel(echan->ch_num, edma_callback,
 432                                         chan, EVENTQ_DEFAULT);
 433
 434         if (a_ch_num < 0) {
 435                 ret = -ENODEV;
 436                 goto err_no_chan;
 437         }
 438
 439         if (a_ch_num != echan->ch_num) {
 440                 dev_err(dev, "failed to allocate requested channel %u:%u\n",
 441                         EDMA_CTLR(echan->ch_num),
 442                         EDMA_CHAN_SLOT(echan->ch_num));
 443                 ret = -ENODEV;
 444                 goto err_wrong_chan;
 445         }
 446
 447         echan->alloced = true;
 448         echan->slot[0] = echan->ch_num;
 449
 450         dev_info(dev, "allocated channel for %u:%u\n",
 451                  EDMA_CTLR(echan->ch_num), EDMA_CHAN_SLOT(echan->ch_num));
 452
 453         return 0;
 454
 455 err_wrong_chan:
 456         edma_free_channel(a_ch_num);
 457 err_no_chan:
 458         return ret;
 459 }
 460
 461 /* Free channel resources */
 462 static void edma_free_chan_resources(struct dma_chan *chan)
 463 {
 464         struct edma_chan *echan = to_edma_chan(chan);
 465         struct device *dev = chan->device->dev;
 466         int i;
 467
 468         /* Terminate transfers */
 469         edma_stop(echan->ch_num);
 470
 471         vchan_free_chan_resources(&echan->vchan);
 472
 473         /* Free EDMA PaRAM slots */
 474         for (i = 1; i < EDMA_MAX_SLOTS; i++) {
 475                 if (echan->slot[i] >= 0) {
 476                         edma_free_slot(echan->slot[i]);
 477                         echan->slot[i] = -1;
 478                 }
 479         }
 480
 481         /* Free EDMA channel */
 482         if (echan->alloced) {
 483                 edma_free_channel(echan->ch_num);
 484                 echan->alloced = false;
 485         }
 486
 487         dev_info(dev, "freeing channel for %u\n", echan->ch_num);
 488 }
 489
 490 /* Send pending descriptor to hardware */
 491 static void edma_issue_pending(struct dma_chan *chan)
 492 {
 493         struct edma_chan *echan = to_edma_chan(chan);
 494         unsigned long flags;
 495
 496         spin_lock_irqsave(&echan->vchan.lock, flags);
 497         if (vchan_issue_pending(&echan->vchan) && !echan->edesc)
 498                 edma_execute(echan);
 499         spin_unlock_irqrestore(&echan->vchan.lock, flags);
 500 }
 501
 502 static size_t edma_desc_size(struct edma_desc *edesc)
 503 {
 504         int i;
 505         size_t size;
 506
 507         if (edesc->absync)
 508                 for (size = i = 0; i < edesc->pset_nr; i++)
 509                         size += (edesc->pset[i].a_b_cnt & 0xffff) *
 510                                 (edesc->pset[i].a_b_cnt >> 16) *
 511                                  edesc->pset[i].ccnt;
 512         else
 513                 size = (edesc->pset[0].a_b_cnt & 0xffff) *
 514                         (edesc->pset[0].a_b_cnt >> 16) +
 515                         (edesc->pset[0].a_b_cnt & 0xffff) *
 516                         (SZ_64K - 1) * edesc->pset[0].ccnt;
 517
 518         return size;
 519 }
 520
 521 /* Check request completion status */
 522 static enum dma_status edma_tx_status(struct dma_chan *chan,
 523                                       dma_cookie_t cookie,
 524                                       struct dma_tx_state *txstate)
 525 {
 526         struct edma_chan *echan = to_edma_chan(chan);
 527         struct virt_dma_desc *vdesc;
 528         enum dma_status ret;
 529         unsigned long flags;
 530
 531         ret = dma_cookie_status(chan, cookie, txstate);
 532         if (ret == DMA_SUCCESS || !txstate)
 533                 return ret;
 534
 535         spin_lock_irqsave(&echan->vchan.lock, flags);
 536         vdesc = vchan_find_desc(&echan->vchan, cookie);
 537         if (vdesc) {
 538                 txstate->residue = edma_desc_size(to_edma_desc(&vdesc->tx));
 539         } else if (echan->edesc && echan->edesc->vdesc.tx.cookie == cookie) {
 540                 struct edma_desc *edesc = echan->edesc;
 541                 txstate->residue = edma_desc_size(edesc);
 542         }
 543         spin_unlock_irqrestore(&echan->vchan.lock, flags);
 544
 545         return ret;
 546 }
 547
 548 static void __init edma_chan_init(struct edma_cc *ecc,
 549                                   struct dma_device *dma,
 550                                   struct edma_chan *echans)
 551 {
 552         int i, j;
 553
 554         for (i = 0; i < EDMA_CHANS; i++) {
 555                 struct edma_chan *echan = &echans[i];
 556                 echan->ch_num = EDMA_CTLR_CHAN(ecc->ctlr, i);
 557                 echan->ecc = ecc;
 558                 echan->vchan.desc_free = edma_desc_free;
 559
 560                 vchan_init(&echan->vchan, dma);
 561
 562                 INIT_LIST_HEAD(&echan->node);
 563                 for (j = 0; j < EDMA_MAX_SLOTS; j++)
 564                         echan->slot[j] = -1;
 565         }
 566 }
 567
 568 static void edma_dma_init(struct edma_cc *ecc, struct dma_device *dma,
 569                           struct device *dev)
 570 {
 571         dma->device_prep_slave_sg = edma_prep_slave_sg;
 572         dma->device_alloc_chan_resources = edma_alloc_chan_resources;
 573         dma->device_free_chan_resources = edma_free_chan_resources;
 574         dma->device_issue_pending = edma_issue_pending;
 575         dma->device_tx_status = edma_tx_status;
 576         dma->device_control = edma_control;
 577         dma->dev = dev;
 578
 579         INIT_LIST_HEAD(&dma->channels);
 580 }
 581
 582 static int edma_probe(struct platform_device *pdev)
 583 {
 584         struct edma_cc *ecc;
 585         int ret;
 586
 587         ecc = devm_kzalloc(&pdev->dev, sizeof(*ecc), GFP_KERNEL);
 588         if (!ecc) {
 589                 dev_err(&pdev->dev, "Can't allocate controller\n");
 590                 return -ENOMEM;
 591         }
 592
 593         ecc->ctlr = pdev->id;
 594         ecc->dummy_slot = edma_alloc_slot(ecc->ctlr, EDMA_SLOT_ANY);
 595         if (ecc->dummy_slot < 0) {
 596                 dev_err(&pdev->dev, "Can't allocate PaRAM dummy slot\n");
 597                 return -EIO;
 598         }
 599
 600         dma_cap_zero(ecc->dma_slave.cap_mask);
 601         dma_cap_set(DMA_SLAVE, ecc->dma_slave.cap_mask);
 602
 603         edma_dma_init(ecc, &ecc->dma_slave, &pdev->dev);
 604
 605         edma_chan_init(ecc, &ecc->dma_slave, ecc->slave_chans);
 606
 607         ret = dma_async_device_register(&ecc->dma_slave);
 608         if (ret)
 609                 goto err_reg1;
 610
 611         platform_set_drvdata(pdev, ecc);
 612
 613         dev_info(&pdev->dev, "TI EDMA DMA engine driver\n");
 614
 615         return 0;
 616
 617 err_reg1:
 618         edma_free_slot(ecc->dummy_slot);
 619         return ret;
 620 }
 621
 622 static int edma_remove(struct platform_device *pdev)
 623 {
 624         struct device *dev = &pdev->dev;
 625         struct edma_cc *ecc = dev_get_drvdata(dev);
 626
 627         dma_async_device_unregister(&ecc->dma_slave);
 628         edma_free_slot(ecc->dummy_slot);
 629
 630         return 0;
 631 }
 632
 633 static struct platform_driver edma_driver = {
 634         .probe          = edma_probe,
 635         .remove         = edma_remove,
 636         .driver = {
 637                 .name = "edma-dma-engine",
 638                 .owner = THIS_MODULE,
 639         },
 640 };
 641
 642 bool edma_filter_fn(struct dma_chan *chan, void *param)
 643 {
 644         if (chan->device->dev->driver == &edma_driver.driver) {
 645                 struct edma_chan *echan = to_edma_chan(chan);
 646                 unsigned ch_req = *(unsigned *)param;
 647                 return ch_req == echan->ch_num;
 648         }
 649         return false;
 650 }
 651 EXPORT_SYMBOL(edma_filter_fn);
 652
 653 static struct platform_device *pdev0, *pdev1;
 654
 655 static const struct platform_device_info edma_dev_info0 = {
 656         .name = "edma-dma-engine",
 657         .id = 0,
 658 };
 659
 660 static const struct platform_device_info edma_dev_info1 = {
 661         .name = "edma-dma-engine",
 662         .id = 1,
 663 };
 664
 665 static int edma_init(void)
 666 {
 667         int ret = platform_driver_register(&edma_driver);
 668
 669         if (ret == 0) {
 670                 pdev0 = platform_device_register_full(&edma_dev_info0);
 671                 if (IS_ERR(pdev0)) {
 672                         platform_driver_unregister(&edma_driver);
 673                         ret = PTR_ERR(pdev0);
 674                         goto out;
 675                 }
 676                 pdev0->dev.dma_mask = &pdev0->dev.coherent_dma_mask;
 677                 pdev0->dev.coherent_dma_mask = DMA_BIT_MASK(32);
 678         }
 679
 680         if (EDMA_CTLRS == 2) {
 681                 pdev1 = platform_device_register_full(&edma_dev_info1);
 682                 if (IS_ERR(pdev1)) {
 683                         platform_driver_unregister(&edma_driver);
 684                         platform_device_unregister(pdev0);
 685                         ret = PTR_ERR(pdev1);
 686                 }
 687                 pdev1->dev.dma_mask = &pdev1->dev.coherent_dma_mask;
 688                 pdev1->dev.coherent_dma_mask = DMA_BIT_MASK(32);
 689         }
 690
 691 out:
 692         return ret;
 693 }
 694 subsys_initcall(edma_init);
 695
 696 static void __exit edma_exit(void)
 697 {
 698         platform_device_unregister(pdev0);
 699         if (pdev1)
 700                 platform_device_unregister(pdev1);
 701         platform_driver_unregister(&edma_driver);
 702 }
 703 module_exit(edma_exit);
 704
 705 MODULE_AUTHOR("Matt Porter <mporter@ti.com>");
 706 MODULE_DESCRIPTION("TI EDMA DMA engine driver");
 707 MODULE_LICENSE("GPL v2");