2 * Copyright Altera Corporation (C) 2014-2016. All rights reserved.
3 * Copyright 2011-2012 Calxeda, Inc.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
17 * Adapted from the highbank_mc_edac driver.
20 #include <asm/cacheflush.h>
21 #include <linux/ctype.h>
22 #include <linux/delay.h>
23 #include <linux/edac.h>
24 #include <linux/genalloc.h>
25 #include <linux/interrupt.h>
26 #include <linux/irqchip/chained_irq.h>
27 #include <linux/kernel.h>
28 #include <linux/mfd/syscon.h>
29 #include <linux/of_address.h>
30 #include <linux/of_irq.h>
31 #include <linux/of_platform.h>
32 #include <linux/platform_device.h>
33 #include <linux/regmap.h>
34 #include <linux/types.h>
35 #include <linux/uaccess.h>
37 #include "altera_edac.h"
38 #include "edac_module.h"
40 #define EDAC_MOD_STR "altera_edac"
41 #define EDAC_VERSION "1"
42 #define EDAC_DEVICE "Altera"
44 static const struct altr_sdram_prv_data c5_data = {
45 .ecc_ctrl_offset = CV_CTLCFG_OFST,
46 .ecc_ctl_en_mask = CV_CTLCFG_ECC_AUTO_EN,
47 .ecc_stat_offset = CV_DRAMSTS_OFST,
48 .ecc_stat_ce_mask = CV_DRAMSTS_SBEERR,
49 .ecc_stat_ue_mask = CV_DRAMSTS_DBEERR,
50 .ecc_saddr_offset = CV_ERRADDR_OFST,
51 .ecc_daddr_offset = CV_ERRADDR_OFST,
52 .ecc_cecnt_offset = CV_SBECOUNT_OFST,
53 .ecc_uecnt_offset = CV_DBECOUNT_OFST,
54 .ecc_irq_en_offset = CV_DRAMINTR_OFST,
55 .ecc_irq_en_mask = CV_DRAMINTR_INTREN,
56 .ecc_irq_clr_offset = CV_DRAMINTR_OFST,
57 .ecc_irq_clr_mask = (CV_DRAMINTR_INTRCLR | CV_DRAMINTR_INTREN),
58 .ecc_cnt_rst_offset = CV_DRAMINTR_OFST,
59 .ecc_cnt_rst_mask = CV_DRAMINTR_INTRCLR,
60 .ce_ue_trgr_offset = CV_CTLCFG_OFST,
61 .ce_set_mask = CV_CTLCFG_GEN_SB_ERR,
62 .ue_set_mask = CV_CTLCFG_GEN_DB_ERR,
65 static const struct altr_sdram_prv_data a10_data = {
66 .ecc_ctrl_offset = A10_ECCCTRL1_OFST,
67 .ecc_ctl_en_mask = A10_ECCCTRL1_ECC_EN,
68 .ecc_stat_offset = A10_INTSTAT_OFST,
69 .ecc_stat_ce_mask = A10_INTSTAT_SBEERR,
70 .ecc_stat_ue_mask = A10_INTSTAT_DBEERR,
71 .ecc_saddr_offset = A10_SERRADDR_OFST,
72 .ecc_daddr_offset = A10_DERRADDR_OFST,
73 .ecc_irq_en_offset = A10_ERRINTEN_OFST,
74 .ecc_irq_en_mask = A10_ECC_IRQ_EN_MASK,
75 .ecc_irq_clr_offset = A10_INTSTAT_OFST,
76 .ecc_irq_clr_mask = (A10_INTSTAT_SBEERR | A10_INTSTAT_DBEERR),
77 .ecc_cnt_rst_offset = A10_ECCCTRL1_OFST,
78 .ecc_cnt_rst_mask = A10_ECC_CNT_RESET_MASK,
79 .ce_ue_trgr_offset = A10_DIAGINTTEST_OFST,
80 .ce_set_mask = A10_DIAGINT_TSERRA_MASK,
81 .ue_set_mask = A10_DIAGINT_TDERRA_MASK,
84 /*********************** EDAC Memory Controller Functions ****************/
86 /* The SDRAM controller uses the EDAC Memory Controller framework. */
88 static irqreturn_t altr_sdram_mc_err_handler(int irq, void *dev_id)
90 struct mem_ctl_info *mci = dev_id;
91 struct altr_sdram_mc_data *drvdata = mci->pvt_info;
92 const struct altr_sdram_prv_data *priv = drvdata->data;
93 u32 status, err_count = 1, err_addr;
95 regmap_read(drvdata->mc_vbase, priv->ecc_stat_offset, &status);
97 if (status & priv->ecc_stat_ue_mask) {
98 regmap_read(drvdata->mc_vbase, priv->ecc_daddr_offset,
100 if (priv->ecc_uecnt_offset)
101 regmap_read(drvdata->mc_vbase, priv->ecc_uecnt_offset,
103 panic("\nEDAC: [%d Uncorrectable errors @ 0x%08X]\n",
104 err_count, err_addr);
106 if (status & priv->ecc_stat_ce_mask) {
107 regmap_read(drvdata->mc_vbase, priv->ecc_saddr_offset,
109 if (priv->ecc_uecnt_offset)
110 regmap_read(drvdata->mc_vbase, priv->ecc_cecnt_offset,
112 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, err_count,
113 err_addr >> PAGE_SHIFT,
114 err_addr & ~PAGE_MASK, 0,
115 0, 0, -1, mci->ctl_name, "");
116 /* Clear IRQ to resume */
117 regmap_write(drvdata->mc_vbase, priv->ecc_irq_clr_offset,
118 priv->ecc_irq_clr_mask);
125 static ssize_t altr_sdr_mc_err_inject_write(struct file *file,
126 const char __user *data,
127 size_t count, loff_t *ppos)
129 struct mem_ctl_info *mci = file->private_data;
130 struct altr_sdram_mc_data *drvdata = mci->pvt_info;
131 const struct altr_sdram_prv_data *priv = drvdata->data;
133 dma_addr_t dma_handle;
136 ptemp = dma_alloc_coherent(mci->pdev, 16, &dma_handle, GFP_KERNEL);
138 dma_free_coherent(mci->pdev, 16, ptemp, dma_handle);
139 edac_printk(KERN_ERR, EDAC_MC,
140 "Inject: Buffer Allocation error\n");
144 regmap_read(drvdata->mc_vbase, priv->ce_ue_trgr_offset,
146 read_reg &= ~(priv->ce_set_mask | priv->ue_set_mask);
148 /* Error are injected by writing a word while the SBE or DBE
149 * bit in the CTLCFG register is set. Reading the word will
150 * trigger the SBE or DBE error and the corresponding IRQ.
153 edac_printk(KERN_ALERT, EDAC_MC,
154 "Inject Double bit error\n");
156 regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset,
157 (read_reg | priv->ue_set_mask));
160 edac_printk(KERN_ALERT, EDAC_MC,
161 "Inject Single bit error\n");
163 regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset,
164 (read_reg | priv->ce_set_mask));
168 ptemp[0] = 0x5A5A5A5A;
169 ptemp[1] = 0xA5A5A5A5;
171 /* Clear the error injection bits */
172 regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset, read_reg);
173 /* Ensure it has been written out */
177 * To trigger the error, we need to read the data back
178 * (the data was written with errors above).
179 * The ACCESS_ONCE macros and printk are used to prevent the
180 * the compiler optimizing these reads out.
182 reg = ACCESS_ONCE(ptemp[0]);
183 read_reg = ACCESS_ONCE(ptemp[1]);
187 edac_printk(KERN_ALERT, EDAC_MC, "Read Data [0x%X, 0x%X]\n",
190 dma_free_coherent(mci->pdev, 16, ptemp, dma_handle);
195 static const struct file_operations altr_sdr_mc_debug_inject_fops = {
197 .write = altr_sdr_mc_err_inject_write,
198 .llseek = generic_file_llseek,
201 static void altr_sdr_mc_create_debugfs_nodes(struct mem_ctl_info *mci)
203 if (!IS_ENABLED(CONFIG_EDAC_DEBUG))
209 edac_debugfs_create_file("altr_trigger", S_IWUSR, mci->debugfs, mci,
210 &altr_sdr_mc_debug_inject_fops);
213 /* Get total memory size from Open Firmware DTB */
214 static unsigned long get_total_mem(void)
216 struct device_node *np = NULL;
217 const unsigned int *reg, *reg_end;
219 unsigned long start, size, total_mem = 0;
221 for_each_node_by_type(np, "memory") {
222 aw = of_n_addr_cells(np);
223 sw = of_n_size_cells(np);
224 reg = (const unsigned int *)of_get_property(np, "reg", &len);
225 reg_end = reg + (len / sizeof(u32));
229 start = of_read_number(reg, aw);
231 size = of_read_number(reg, sw);
234 } while (reg < reg_end);
236 edac_dbg(0, "total_mem 0x%lx\n", total_mem);
240 static const struct of_device_id altr_sdram_ctrl_of_match[] = {
241 { .compatible = "altr,sdram-edac", .data = &c5_data},
242 { .compatible = "altr,sdram-edac-a10", .data = &a10_data},
245 MODULE_DEVICE_TABLE(of, altr_sdram_ctrl_of_match);
247 static int a10_init(struct regmap *mc_vbase)
249 if (regmap_update_bits(mc_vbase, A10_INTMODE_OFST,
250 A10_INTMODE_SB_INT, A10_INTMODE_SB_INT)) {
251 edac_printk(KERN_ERR, EDAC_MC,
252 "Error setting SB IRQ mode\n");
256 if (regmap_write(mc_vbase, A10_SERRCNTREG_OFST, 1)) {
257 edac_printk(KERN_ERR, EDAC_MC,
258 "Error setting trigger count\n");
265 static int a10_unmask_irq(struct platform_device *pdev, u32 mask)
267 void __iomem *sm_base;
270 if (!request_mem_region(A10_SYMAN_INTMASK_CLR, sizeof(u32),
271 dev_name(&pdev->dev))) {
272 edac_printk(KERN_ERR, EDAC_MC,
273 "Unable to request mem region\n");
277 sm_base = ioremap(A10_SYMAN_INTMASK_CLR, sizeof(u32));
279 edac_printk(KERN_ERR, EDAC_MC,
280 "Unable to ioremap device\n");
286 iowrite32(mask, sm_base);
291 release_mem_region(A10_SYMAN_INTMASK_CLR, sizeof(u32));
296 static int altr_sdram_probe(struct platform_device *pdev)
298 const struct of_device_id *id;
299 struct edac_mc_layer layers[2];
300 struct mem_ctl_info *mci;
301 struct altr_sdram_mc_data *drvdata;
302 const struct altr_sdram_prv_data *priv;
303 struct regmap *mc_vbase;
304 struct dimm_info *dimm;
306 int irq, irq2, res = 0;
307 unsigned long mem_size, irqflags = 0;
309 id = of_match_device(altr_sdram_ctrl_of_match, &pdev->dev);
313 /* Grab the register range from the sdr controller in device tree */
314 mc_vbase = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
316 if (IS_ERR(mc_vbase)) {
317 edac_printk(KERN_ERR, EDAC_MC,
318 "regmap for altr,sdr-syscon lookup failed.\n");
322 /* Check specific dependencies for the module */
323 priv = of_match_node(altr_sdram_ctrl_of_match,
324 pdev->dev.of_node)->data;
326 /* Validate the SDRAM controller has ECC enabled */
327 if (regmap_read(mc_vbase, priv->ecc_ctrl_offset, &read_reg) ||
328 ((read_reg & priv->ecc_ctl_en_mask) != priv->ecc_ctl_en_mask)) {
329 edac_printk(KERN_ERR, EDAC_MC,
330 "No ECC/ECC disabled [0x%08X]\n", read_reg);
334 /* Grab memory size from device tree. */
335 mem_size = get_total_mem();
337 edac_printk(KERN_ERR, EDAC_MC, "Unable to calculate memory size\n");
341 /* Ensure the SDRAM Interrupt is disabled */
342 if (regmap_update_bits(mc_vbase, priv->ecc_irq_en_offset,
343 priv->ecc_irq_en_mask, 0)) {
344 edac_printk(KERN_ERR, EDAC_MC,
345 "Error disabling SDRAM ECC IRQ\n");
349 /* Toggle to clear the SDRAM Error count */
350 if (regmap_update_bits(mc_vbase, priv->ecc_cnt_rst_offset,
351 priv->ecc_cnt_rst_mask,
352 priv->ecc_cnt_rst_mask)) {
353 edac_printk(KERN_ERR, EDAC_MC,
354 "Error clearing SDRAM ECC count\n");
358 if (regmap_update_bits(mc_vbase, priv->ecc_cnt_rst_offset,
359 priv->ecc_cnt_rst_mask, 0)) {
360 edac_printk(KERN_ERR, EDAC_MC,
361 "Error clearing SDRAM ECC count\n");
365 irq = platform_get_irq(pdev, 0);
367 edac_printk(KERN_ERR, EDAC_MC,
368 "No irq %d in DT\n", irq);
372 /* Arria10 has a 2nd IRQ */
373 irq2 = platform_get_irq(pdev, 1);
375 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
377 layers[0].is_virt_csrow = true;
378 layers[1].type = EDAC_MC_LAYER_CHANNEL;
380 layers[1].is_virt_csrow = false;
381 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
382 sizeof(struct altr_sdram_mc_data));
386 mci->pdev = &pdev->dev;
387 drvdata = mci->pvt_info;
388 drvdata->mc_vbase = mc_vbase;
389 drvdata->data = priv;
390 platform_set_drvdata(pdev, mci);
392 if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) {
393 edac_printk(KERN_ERR, EDAC_MC,
394 "Unable to get managed device resource\n");
399 mci->mtype_cap = MEM_FLAG_DDR3;
400 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
401 mci->edac_cap = EDAC_FLAG_SECDED;
402 mci->mod_name = EDAC_MOD_STR;
403 mci->mod_ver = EDAC_VERSION;
404 mci->ctl_name = dev_name(&pdev->dev);
405 mci->scrub_mode = SCRUB_SW_SRC;
406 mci->dev_name = dev_name(&pdev->dev);
409 dimm->nr_pages = ((mem_size - 1) >> PAGE_SHIFT) + 1;
411 dimm->dtype = DEV_X8;
412 dimm->mtype = MEM_DDR3;
413 dimm->edac_mode = EDAC_SECDED;
415 res = edac_mc_add_mc(mci);
419 /* Only the Arria10 has separate IRQs */
421 /* Arria10 specific initialization */
422 res = a10_init(mc_vbase);
426 res = devm_request_irq(&pdev->dev, irq2,
427 altr_sdram_mc_err_handler,
428 IRQF_SHARED, dev_name(&pdev->dev), mci);
430 edac_mc_printk(mci, KERN_ERR,
431 "Unable to request irq %d\n", irq2);
436 res = a10_unmask_irq(pdev, A10_DDR0_IRQ_MASK);
440 irqflags = IRQF_SHARED;
443 res = devm_request_irq(&pdev->dev, irq, altr_sdram_mc_err_handler,
444 irqflags, dev_name(&pdev->dev), mci);
446 edac_mc_printk(mci, KERN_ERR,
447 "Unable to request irq %d\n", irq);
452 /* Infrastructure ready - enable the IRQ */
453 if (regmap_update_bits(drvdata->mc_vbase, priv->ecc_irq_en_offset,
454 priv->ecc_irq_en_mask, priv->ecc_irq_en_mask)) {
455 edac_mc_printk(mci, KERN_ERR,
456 "Error enabling SDRAM ECC IRQ\n");
461 altr_sdr_mc_create_debugfs_nodes(mci);
463 devres_close_group(&pdev->dev, NULL);
468 edac_mc_del_mc(&pdev->dev);
470 devres_release_group(&pdev->dev, NULL);
473 edac_printk(KERN_ERR, EDAC_MC,
474 "EDAC Probe Failed; Error %d\n", res);
479 static int altr_sdram_remove(struct platform_device *pdev)
481 struct mem_ctl_info *mci = platform_get_drvdata(pdev);
483 edac_mc_del_mc(&pdev->dev);
485 platform_set_drvdata(pdev, NULL);
491 * If you want to suspend, need to disable EDAC by removing it
492 * from the device tree or defconfig.
495 static int altr_sdram_prepare(struct device *dev)
497 pr_err("Suspend not allowed when EDAC is enabled.\n");
502 static const struct dev_pm_ops altr_sdram_pm_ops = {
503 .prepare = altr_sdram_prepare,
507 static struct platform_driver altr_sdram_edac_driver = {
508 .probe = altr_sdram_probe,
509 .remove = altr_sdram_remove,
511 .name = "altr_sdram_edac",
513 .pm = &altr_sdram_pm_ops,
515 .of_match_table = altr_sdram_ctrl_of_match,
519 module_platform_driver(altr_sdram_edac_driver);
521 /************************* EDAC Parent Probe *************************/
523 static const struct of_device_id altr_edac_device_of_match[];
525 static const struct of_device_id altr_edac_of_match[] = {
526 { .compatible = "altr,socfpga-ecc-manager" },
529 MODULE_DEVICE_TABLE(of, altr_edac_of_match);
531 static int altr_edac_probe(struct platform_device *pdev)
533 of_platform_populate(pdev->dev.of_node, altr_edac_device_of_match,
538 static struct platform_driver altr_edac_driver = {
539 .probe = altr_edac_probe,
541 .name = "socfpga_ecc_manager",
542 .of_match_table = altr_edac_of_match,
545 module_platform_driver(altr_edac_driver);
547 /************************* EDAC Device Functions *************************/
550 * EDAC Device Functions (shared between various IPs).
551 * The discrete memories use the EDAC Device framework. The probe
552 * and error handling functions are very similar between memories
553 * so they are shared. The memory allocation and freeing for EDAC
554 * trigger testing are different for each memory.
557 static const struct edac_device_prv_data ocramecc_data;
558 static const struct edac_device_prv_data l2ecc_data;
559 static const struct edac_device_prv_data a10_ocramecc_data;
560 static const struct edac_device_prv_data a10_l2ecc_data;
562 static irqreturn_t altr_edac_device_handler(int irq, void *dev_id)
564 irqreturn_t ret_value = IRQ_NONE;
565 struct edac_device_ctl_info *dci = dev_id;
566 struct altr_edac_device_dev *drvdata = dci->pvt_info;
567 const struct edac_device_prv_data *priv = drvdata->data;
569 if (irq == drvdata->sb_irq) {
570 if (priv->ce_clear_mask)
571 writel(priv->ce_clear_mask, drvdata->base);
572 edac_device_handle_ce(dci, 0, 0, drvdata->edac_dev_name);
573 ret_value = IRQ_HANDLED;
574 } else if (irq == drvdata->db_irq) {
575 if (priv->ue_clear_mask)
576 writel(priv->ue_clear_mask, drvdata->base);
577 edac_device_handle_ue(dci, 0, 0, drvdata->edac_dev_name);
578 panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
579 ret_value = IRQ_HANDLED;
587 static ssize_t altr_edac_device_trig(struct file *file,
588 const char __user *user_buf,
589 size_t count, loff_t *ppos)
592 u32 *ptemp, i, error_mask;
596 struct edac_device_ctl_info *edac_dci = file->private_data;
597 struct altr_edac_device_dev *drvdata = edac_dci->pvt_info;
598 const struct edac_device_prv_data *priv = drvdata->data;
599 void *generic_ptr = edac_dci->dev;
601 if (!user_buf || get_user(trig_type, user_buf))
604 if (!priv->alloc_mem)
608 * Note that generic_ptr is initialized to the device * but in
609 * some alloc_functions, this is overridden and returns data.
611 ptemp = priv->alloc_mem(priv->trig_alloc_sz, &generic_ptr);
613 edac_printk(KERN_ERR, EDAC_DEVICE,
614 "Inject: Buffer Allocation error\n");
618 if (trig_type == ALTR_UE_TRIGGER_CHAR)
619 error_mask = priv->ue_set_mask;
621 error_mask = priv->ce_set_mask;
623 edac_printk(KERN_ALERT, EDAC_DEVICE,
624 "Trigger Error Mask (0x%X)\n", error_mask);
626 local_irq_save(flags);
627 /* write ECC corrupted data out. */
628 for (i = 0; i < (priv->trig_alloc_sz / sizeof(*ptemp)); i++) {
629 /* Read data so we're in the correct state */
631 if (ACCESS_ONCE(ptemp[i]))
633 /* Toggle Error bit (it is latched), leave ECC enabled */
634 writel(error_mask, (drvdata->base + priv->set_err_ofst));
635 writel(priv->ecc_enable_mask, (drvdata->base +
636 priv->set_err_ofst));
639 /* Ensure it has been written out */
641 local_irq_restore(flags);
644 edac_printk(KERN_ERR, EDAC_DEVICE, "Mem Not Cleared\n");
646 /* Read out written data. ECC error caused here */
647 for (i = 0; i < ALTR_TRIGGER_READ_WRD_CNT; i++)
648 if (ACCESS_ONCE(ptemp[i]) != i)
649 edac_printk(KERN_ERR, EDAC_DEVICE,
650 "Read doesn't match written data\n");
653 priv->free_mem(ptemp, priv->trig_alloc_sz, generic_ptr);
658 static const struct file_operations altr_edac_device_inject_fops = {
660 .write = altr_edac_device_trig,
661 .llseek = generic_file_llseek,
664 static ssize_t altr_edac_a10_device_trig(struct file *file,
665 const char __user *user_buf,
666 size_t count, loff_t *ppos);
668 static const struct file_operations altr_edac_a10_device_inject_fops = {
670 .write = altr_edac_a10_device_trig,
671 .llseek = generic_file_llseek,
674 static void altr_create_edacdev_dbgfs(struct edac_device_ctl_info *edac_dci,
675 const struct edac_device_prv_data *priv)
677 struct altr_edac_device_dev *drvdata = edac_dci->pvt_info;
679 if (!IS_ENABLED(CONFIG_EDAC_DEBUG))
682 drvdata->debugfs_dir = edac_debugfs_create_dir(drvdata->edac_dev_name);
683 if (!drvdata->debugfs_dir)
686 if (!edac_debugfs_create_file("altr_trigger", S_IWUSR,
687 drvdata->debugfs_dir, edac_dci,
689 debugfs_remove_recursive(drvdata->debugfs_dir);
692 static const struct of_device_id altr_edac_device_of_match[] = {
693 #ifdef CONFIG_EDAC_ALTERA_L2C
694 { .compatible = "altr,socfpga-l2-ecc", .data = &l2ecc_data },
696 #ifdef CONFIG_EDAC_ALTERA_OCRAM
697 { .compatible = "altr,socfpga-ocram-ecc", .data = &ocramecc_data },
701 MODULE_DEVICE_TABLE(of, altr_edac_device_of_match);
704 * altr_edac_device_probe()
705 * This is a generic EDAC device driver that will support
706 * various Altera memory devices such as the L2 cache ECC and
707 * OCRAM ECC as well as the memories for other peripherals.
708 * Module specific initialization is done by passing the
709 * function index in the device tree.
711 static int altr_edac_device_probe(struct platform_device *pdev)
713 struct edac_device_ctl_info *dci;
714 struct altr_edac_device_dev *drvdata;
717 struct device_node *np = pdev->dev.of_node;
718 char *ecc_name = (char *)np->name;
719 static int dev_instance;
721 if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) {
722 edac_printk(KERN_ERR, EDAC_DEVICE,
723 "Unable to open devm\n");
727 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
729 edac_printk(KERN_ERR, EDAC_DEVICE,
730 "Unable to get mem resource\n");
735 if (!devm_request_mem_region(&pdev->dev, r->start, resource_size(r),
736 dev_name(&pdev->dev))) {
737 edac_printk(KERN_ERR, EDAC_DEVICE,
738 "%s:Error requesting mem region\n", ecc_name);
743 dci = edac_device_alloc_ctl_info(sizeof(*drvdata), ecc_name,
744 1, ecc_name, 1, 0, NULL, 0,
748 edac_printk(KERN_ERR, EDAC_DEVICE,
749 "%s: Unable to allocate EDAC device\n", ecc_name);
754 drvdata = dci->pvt_info;
755 dci->dev = &pdev->dev;
756 platform_set_drvdata(pdev, dci);
757 drvdata->edac_dev_name = ecc_name;
759 drvdata->base = devm_ioremap(&pdev->dev, r->start, resource_size(r));
763 /* Get driver specific data for this EDAC device */
764 drvdata->data = of_match_node(altr_edac_device_of_match, np)->data;
766 /* Check specific dependencies for the module */
767 if (drvdata->data->setup) {
768 res = drvdata->data->setup(drvdata);
773 drvdata->sb_irq = platform_get_irq(pdev, 0);
774 res = devm_request_irq(&pdev->dev, drvdata->sb_irq,
775 altr_edac_device_handler,
776 0, dev_name(&pdev->dev), dci);
780 drvdata->db_irq = platform_get_irq(pdev, 1);
781 res = devm_request_irq(&pdev->dev, drvdata->db_irq,
782 altr_edac_device_handler,
783 0, dev_name(&pdev->dev), dci);
787 dci->mod_name = "Altera ECC Manager";
788 dci->dev_name = drvdata->edac_dev_name;
790 res = edac_device_add_device(dci);
794 altr_create_edacdev_dbgfs(dci, drvdata->data);
796 devres_close_group(&pdev->dev, NULL);
801 edac_device_free_ctl_info(dci);
803 devres_release_group(&pdev->dev, NULL);
804 edac_printk(KERN_ERR, EDAC_DEVICE,
805 "%s:Error setting up EDAC device: %d\n", ecc_name, res);
810 static int altr_edac_device_remove(struct platform_device *pdev)
812 struct edac_device_ctl_info *dci = platform_get_drvdata(pdev);
813 struct altr_edac_device_dev *drvdata = dci->pvt_info;
815 debugfs_remove_recursive(drvdata->debugfs_dir);
816 edac_device_del_device(&pdev->dev);
817 edac_device_free_ctl_info(dci);
822 static struct platform_driver altr_edac_device_driver = {
823 .probe = altr_edac_device_probe,
824 .remove = altr_edac_device_remove,
826 .name = "altr_edac_device",
827 .of_match_table = altr_edac_device_of_match,
830 module_platform_driver(altr_edac_device_driver);
832 /******************* Arria10 Device ECC Shared Functions *****************/
835 * Test for memory's ECC dependencies upon entry because platform specific
836 * startup should have initialized the memory and enabled the ECC.
837 * Can't turn on ECC here because accessing un-initialized memory will
838 * cause CE/UE errors possibly causing an ABORT.
840 static int __maybe_unused
841 altr_check_ecc_deps(struct altr_edac_device_dev *device)
843 void __iomem *base = device->base;
844 const struct edac_device_prv_data *prv = device->data;
846 if (readl(base + prv->ecc_en_ofst) & prv->ecc_enable_mask)
849 edac_printk(KERN_ERR, EDAC_DEVICE,
850 "%s: No ECC present or ECC disabled.\n",
851 device->edac_dev_name);
855 static irqreturn_t __maybe_unused altr_edac_a10_ecc_irq(int irq, void *dev_id)
857 struct altr_edac_device_dev *dci = dev_id;
858 void __iomem *base = dci->base;
860 if (irq == dci->sb_irq) {
861 writel(ALTR_A10_ECC_SERRPENA,
862 base + ALTR_A10_ECC_INTSTAT_OFST);
863 edac_device_handle_ce(dci->edac_dev, 0, 0, dci->edac_dev_name);
866 } else if (irq == dci->db_irq) {
867 writel(ALTR_A10_ECC_DERRPENA,
868 base + ALTR_A10_ECC_INTSTAT_OFST);
869 edac_device_handle_ue(dci->edac_dev, 0, 0, dci->edac_dev_name);
870 if (dci->data->panic)
871 panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
881 /******************* Arria10 Memory Buffer Functions *********************/
883 static inline int a10_get_irq_mask(struct device_node *np)
886 const u32 *handle = of_get_property(np, "interrupts", NULL);
890 irq = be32_to_cpup(handle);
894 static inline void ecc_set_bits(u32 bit_mask, void __iomem *ioaddr)
896 u32 value = readl(ioaddr);
899 writel(value, ioaddr);
902 static inline void ecc_clear_bits(u32 bit_mask, void __iomem *ioaddr)
904 u32 value = readl(ioaddr);
907 writel(value, ioaddr);
910 static inline int ecc_test_bits(u32 bit_mask, void __iomem *ioaddr)
912 u32 value = readl(ioaddr);
914 return (value & bit_mask) ? 1 : 0;
918 * This function uses the memory initialization block in the Arria10 ECC
919 * controller to initialize/clear the entire memory data and ECC data.
921 static int __maybe_unused altr_init_memory_port(void __iomem *ioaddr, int port)
923 int limit = ALTR_A10_ECC_INIT_WATCHDOG_10US;
924 u32 init_mask, stat_mask, clear_mask;
928 init_mask = ALTR_A10_ECC_INITB;
929 stat_mask = ALTR_A10_ECC_INITCOMPLETEB;
930 clear_mask = ALTR_A10_ECC_ERRPENB_MASK;
932 init_mask = ALTR_A10_ECC_INITA;
933 stat_mask = ALTR_A10_ECC_INITCOMPLETEA;
934 clear_mask = ALTR_A10_ECC_ERRPENA_MASK;
937 ecc_set_bits(init_mask, (ioaddr + ALTR_A10_ECC_CTRL_OFST));
939 if (ecc_test_bits(stat_mask,
940 (ioaddr + ALTR_A10_ECC_INITSTAT_OFST)))
947 /* Clear any pending ECC interrupts */
948 writel(clear_mask, (ioaddr + ALTR_A10_ECC_INTSTAT_OFST));
953 static __init int __maybe_unused
954 altr_init_a10_ecc_block(struct device_node *np, u32 irq_mask,
955 u32 ecc_ctrl_en_mask, bool dual_port)
958 void __iomem *ecc_block_base;
959 struct regmap *ecc_mgr_map;
961 struct device_node *np_eccmgr;
963 ecc_name = (char *)np->name;
965 /* Get the ECC Manager - parent of the device EDACs */
966 np_eccmgr = of_get_parent(np);
967 ecc_mgr_map = syscon_regmap_lookup_by_phandle(np_eccmgr,
968 "altr,sysmgr-syscon");
969 of_node_put(np_eccmgr);
970 if (IS_ERR(ecc_mgr_map)) {
971 edac_printk(KERN_ERR, EDAC_DEVICE,
972 "Unable to get syscon altr,sysmgr-syscon\n");
976 /* Map the ECC Block */
977 ecc_block_base = of_iomap(np, 0);
978 if (!ecc_block_base) {
979 edac_printk(KERN_ERR, EDAC_DEVICE,
980 "Unable to map %s ECC block\n", ecc_name);
985 regmap_write(ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_SET_OFST, irq_mask);
986 writel(ALTR_A10_ECC_SERRINTEN,
987 (ecc_block_base + ALTR_A10_ECC_ERRINTENR_OFST));
988 ecc_clear_bits(ecc_ctrl_en_mask,
989 (ecc_block_base + ALTR_A10_ECC_CTRL_OFST));
990 /* Ensure all writes complete */
992 /* Use HW initialization block to initialize memory for ECC */
993 ret = altr_init_memory_port(ecc_block_base, 0);
995 edac_printk(KERN_ERR, EDAC_DEVICE,
996 "ECC: cannot init %s PORTA memory\n", ecc_name);
1001 ret = altr_init_memory_port(ecc_block_base, 1);
1003 edac_printk(KERN_ERR, EDAC_DEVICE,
1004 "ECC: cannot init %s PORTB memory\n",
1010 /* Interrupt mode set to every SBERR */
1011 regmap_write(ecc_mgr_map, ALTR_A10_ECC_INTMODE_OFST,
1012 ALTR_A10_ECC_INTMODE);
1014 ecc_set_bits(ecc_ctrl_en_mask, (ecc_block_base +
1015 ALTR_A10_ECC_CTRL_OFST));
1016 writel(ALTR_A10_ECC_SERRINTEN,
1017 (ecc_block_base + ALTR_A10_ECC_ERRINTENS_OFST));
1018 regmap_write(ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_CLR_OFST, irq_mask);
1019 /* Ensure all writes complete */
1022 iounmap(ecc_block_base);
1026 static int socfpga_is_a10(void)
1028 return of_machine_is_compatible("altr,socfpga-arria10");
1031 static int validate_parent_available(struct device_node *np);
1032 static const struct of_device_id altr_edac_a10_device_of_match[];
1033 static int __init __maybe_unused altr_init_a10_ecc_device_type(char *compat)
1036 struct device_node *child, *np;
1038 if (!socfpga_is_a10())
1041 np = of_find_compatible_node(NULL, NULL,
1042 "altr,socfpga-a10-ecc-manager");
1044 edac_printk(KERN_ERR, EDAC_DEVICE, "ECC Manager not found\n");
1048 for_each_child_of_node(np, child) {
1049 const struct of_device_id *pdev_id;
1050 const struct edac_device_prv_data *prv;
1052 if (!of_device_is_available(child))
1054 if (!of_device_is_compatible(child, compat))
1057 if (validate_parent_available(child))
1060 irq = a10_get_irq_mask(child);
1064 /* Get matching node and check for valid result */
1065 pdev_id = of_match_node(altr_edac_a10_device_of_match, child);
1066 if (IS_ERR_OR_NULL(pdev_id))
1069 /* Validate private data pointer before dereferencing */
1070 prv = pdev_id->data;
1074 altr_init_a10_ecc_block(child, BIT(irq),
1075 prv->ecc_enable_mask, 0);
1082 /*********************** OCRAM EDAC Device Functions *********************/
1084 #ifdef CONFIG_EDAC_ALTERA_OCRAM
1086 static void *ocram_alloc_mem(size_t size, void **other)
1088 struct device_node *np;
1089 struct gen_pool *gp;
1092 np = of_find_compatible_node(NULL, NULL, "altr,socfpga-ocram-ecc");
1096 gp = of_gen_pool_get(np, "iram", 0);
1101 sram_addr = (void *)gen_pool_alloc(gp, size);
1105 memset(sram_addr, 0, size);
1106 /* Ensure data is written out */
1109 /* Remember this handle for freeing later */
1115 static void ocram_free_mem(void *p, size_t size, void *other)
1117 gen_pool_free((struct gen_pool *)other, (u32)p, size);
1120 static const struct edac_device_prv_data ocramecc_data = {
1121 .setup = altr_check_ecc_deps,
1122 .ce_clear_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_SERR),
1123 .ue_clear_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_DERR),
1124 .alloc_mem = ocram_alloc_mem,
1125 .free_mem = ocram_free_mem,
1126 .ecc_enable_mask = ALTR_OCR_ECC_EN,
1127 .ecc_en_ofst = ALTR_OCR_ECC_REG_OFFSET,
1128 .ce_set_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_INJS),
1129 .ue_set_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_INJD),
1130 .set_err_ofst = ALTR_OCR_ECC_REG_OFFSET,
1131 .trig_alloc_sz = ALTR_TRIG_OCRAM_BYTE_SIZE,
1132 .inject_fops = &altr_edac_device_inject_fops,
1135 static const struct edac_device_prv_data a10_ocramecc_data = {
1136 .setup = altr_check_ecc_deps,
1137 .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1138 .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1139 .irq_status_mask = A10_SYSMGR_ECC_INTSTAT_OCRAM,
1140 .ecc_enable_mask = ALTR_A10_OCRAM_ECC_EN_CTL,
1141 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1142 .ce_set_mask = ALTR_A10_ECC_TSERRA,
1143 .ue_set_mask = ALTR_A10_ECC_TDERRA,
1144 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1145 .ecc_irq_handler = altr_edac_a10_ecc_irq,
1146 .inject_fops = &altr_edac_a10_device_inject_fops,
1148 * OCRAM panic on uncorrectable error because sleep/resume
1149 * functions and FPGA contents are stored in OCRAM. Prefer
1150 * a kernel panic over executing/loading corrupted data.
1155 #endif /* CONFIG_EDAC_ALTERA_OCRAM */
1157 /********************* L2 Cache EDAC Device Functions ********************/
1159 #ifdef CONFIG_EDAC_ALTERA_L2C
1161 static void *l2_alloc_mem(size_t size, void **other)
1163 struct device *dev = *other;
1164 void *ptemp = devm_kzalloc(dev, size, GFP_KERNEL);
1169 /* Make sure everything is written out */
1173 * Clean all cache levels up to LoC (includes L2)
1174 * This ensures the corrupted data is written into
1175 * L2 cache for readback test (which causes ECC error).
1182 static void l2_free_mem(void *p, size_t size, void *other)
1184 struct device *dev = other;
1191 * altr_l2_check_deps()
1192 * Test for L2 cache ECC dependencies upon entry because
1193 * platform specific startup should have initialized the L2
1194 * memory and enabled the ECC.
1195 * Bail if ECC is not enabled.
1196 * Note that L2 Cache Enable is forced at build time.
1198 static int altr_l2_check_deps(struct altr_edac_device_dev *device)
1200 void __iomem *base = device->base;
1201 const struct edac_device_prv_data *prv = device->data;
1203 if ((readl(base) & prv->ecc_enable_mask) ==
1204 prv->ecc_enable_mask)
1207 edac_printk(KERN_ERR, EDAC_DEVICE,
1208 "L2: No ECC present, or ECC disabled\n");
1212 static irqreturn_t altr_edac_a10_l2_irq(int irq, void *dev_id)
1214 struct altr_edac_device_dev *dci = dev_id;
1216 if (irq == dci->sb_irq) {
1217 regmap_write(dci->edac->ecc_mgr_map,
1218 A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST,
1219 A10_SYSGMR_MPU_CLEAR_L2_ECC_SB);
1220 edac_device_handle_ce(dci->edac_dev, 0, 0, dci->edac_dev_name);
1223 } else if (irq == dci->db_irq) {
1224 regmap_write(dci->edac->ecc_mgr_map,
1225 A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST,
1226 A10_SYSGMR_MPU_CLEAR_L2_ECC_MB);
1227 edac_device_handle_ue(dci->edac_dev, 0, 0, dci->edac_dev_name);
1228 panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
1238 static const struct edac_device_prv_data l2ecc_data = {
1239 .setup = altr_l2_check_deps,
1242 .alloc_mem = l2_alloc_mem,
1243 .free_mem = l2_free_mem,
1244 .ecc_enable_mask = ALTR_L2_ECC_EN,
1245 .ce_set_mask = (ALTR_L2_ECC_EN | ALTR_L2_ECC_INJS),
1246 .ue_set_mask = (ALTR_L2_ECC_EN | ALTR_L2_ECC_INJD),
1247 .set_err_ofst = ALTR_L2_ECC_REG_OFFSET,
1248 .trig_alloc_sz = ALTR_TRIG_L2C_BYTE_SIZE,
1249 .inject_fops = &altr_edac_device_inject_fops,
1252 static const struct edac_device_prv_data a10_l2ecc_data = {
1253 .setup = altr_l2_check_deps,
1254 .ce_clear_mask = ALTR_A10_L2_ECC_SERR_CLR,
1255 .ue_clear_mask = ALTR_A10_L2_ECC_MERR_CLR,
1256 .irq_status_mask = A10_SYSMGR_ECC_INTSTAT_L2,
1257 .alloc_mem = l2_alloc_mem,
1258 .free_mem = l2_free_mem,
1259 .ecc_enable_mask = ALTR_A10_L2_ECC_EN_CTL,
1260 .ce_set_mask = ALTR_A10_L2_ECC_CE_INJ_MASK,
1261 .ue_set_mask = ALTR_A10_L2_ECC_UE_INJ_MASK,
1262 .set_err_ofst = ALTR_A10_L2_ECC_INJ_OFST,
1263 .ecc_irq_handler = altr_edac_a10_l2_irq,
1264 .trig_alloc_sz = ALTR_TRIG_L2C_BYTE_SIZE,
1265 .inject_fops = &altr_edac_device_inject_fops,
1268 #endif /* CONFIG_EDAC_ALTERA_L2C */
1270 /********************* Ethernet Device Functions ********************/
1272 #ifdef CONFIG_EDAC_ALTERA_ETHERNET
1274 static const struct edac_device_prv_data a10_enetecc_data = {
1275 .setup = altr_check_ecc_deps,
1276 .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1277 .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1278 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1279 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1280 .ce_set_mask = ALTR_A10_ECC_TSERRA,
1281 .ue_set_mask = ALTR_A10_ECC_TDERRA,
1282 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1283 .ecc_irq_handler = altr_edac_a10_ecc_irq,
1284 .inject_fops = &altr_edac_a10_device_inject_fops,
1287 static int __init socfpga_init_ethernet_ecc(void)
1289 return altr_init_a10_ecc_device_type("altr,socfpga-eth-mac-ecc");
1292 early_initcall(socfpga_init_ethernet_ecc);
1294 #endif /* CONFIG_EDAC_ALTERA_ETHERNET */
1296 /********************** NAND Device Functions **********************/
1298 #ifdef CONFIG_EDAC_ALTERA_NAND
1300 static const struct edac_device_prv_data a10_nandecc_data = {
1301 .setup = altr_check_ecc_deps,
1302 .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1303 .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1304 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1305 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1306 .ce_set_mask = ALTR_A10_ECC_TSERRA,
1307 .ue_set_mask = ALTR_A10_ECC_TDERRA,
1308 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1309 .ecc_irq_handler = altr_edac_a10_ecc_irq,
1310 .inject_fops = &altr_edac_a10_device_inject_fops,
1313 static int __init socfpga_init_nand_ecc(void)
1315 return altr_init_a10_ecc_device_type("altr,socfpga-nand-ecc");
1318 early_initcall(socfpga_init_nand_ecc);
1320 #endif /* CONFIG_EDAC_ALTERA_NAND */
1322 /********************** DMA Device Functions **********************/
1324 #ifdef CONFIG_EDAC_ALTERA_DMA
1326 static const struct edac_device_prv_data a10_dmaecc_data = {
1327 .setup = altr_check_ecc_deps,
1328 .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1329 .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1330 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1331 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1332 .ce_set_mask = ALTR_A10_ECC_TSERRA,
1333 .ue_set_mask = ALTR_A10_ECC_TDERRA,
1334 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1335 .ecc_irq_handler = altr_edac_a10_ecc_irq,
1336 .inject_fops = &altr_edac_a10_device_inject_fops,
1339 static int __init socfpga_init_dma_ecc(void)
1341 return altr_init_a10_ecc_device_type("altr,socfpga-dma-ecc");
1344 early_initcall(socfpga_init_dma_ecc);
1346 #endif /* CONFIG_EDAC_ALTERA_DMA */
1348 /********************** USB Device Functions **********************/
1350 #ifdef CONFIG_EDAC_ALTERA_USB
1352 static const struct edac_device_prv_data a10_usbecc_data = {
1353 .setup = altr_check_ecc_deps,
1354 .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1355 .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1356 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1357 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1358 .ce_set_mask = ALTR_A10_ECC_TSERRA,
1359 .ue_set_mask = ALTR_A10_ECC_TDERRA,
1360 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1361 .ecc_irq_handler = altr_edac_a10_ecc_irq,
1362 .inject_fops = &altr_edac_a10_device_inject_fops,
1365 static int __init socfpga_init_usb_ecc(void)
1367 return altr_init_a10_ecc_device_type("altr,socfpga-usb-ecc");
1370 early_initcall(socfpga_init_usb_ecc);
1372 #endif /* CONFIG_EDAC_ALTERA_USB */
1374 /********************** QSPI Device Functions **********************/
1376 #ifdef CONFIG_EDAC_ALTERA_QSPI
1378 static const struct edac_device_prv_data a10_qspiecc_data = {
1379 .setup = altr_check_ecc_deps,
1380 .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1381 .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1382 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1383 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1384 .ce_set_mask = ALTR_A10_ECC_TSERRA,
1385 .ue_set_mask = ALTR_A10_ECC_TDERRA,
1386 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1387 .ecc_irq_handler = altr_edac_a10_ecc_irq,
1388 .inject_fops = &altr_edac_a10_device_inject_fops,
1391 static int __init socfpga_init_qspi_ecc(void)
1393 return altr_init_a10_ecc_device_type("altr,socfpga-qspi-ecc");
1396 early_initcall(socfpga_init_qspi_ecc);
1398 #endif /* CONFIG_EDAC_ALTERA_QSPI */
1400 /********************* SDMMC Device Functions **********************/
1402 #ifdef CONFIG_EDAC_ALTERA_SDMMC
1404 static const struct edac_device_prv_data a10_sdmmceccb_data;
1405 static int altr_portb_setup(struct altr_edac_device_dev *device)
1407 struct edac_device_ctl_info *dci;
1408 struct altr_edac_device_dev *altdev;
1409 char *ecc_name = "sdmmcb-ecc";
1411 struct device_node *np;
1412 const struct edac_device_prv_data *prv = &a10_sdmmceccb_data;
1414 rc = altr_check_ecc_deps(device);
1418 np = of_find_compatible_node(NULL, NULL, "altr,socfpga-sdmmc-ecc");
1420 edac_printk(KERN_WARNING, EDAC_DEVICE, "SDMMC node not found\n");
1424 /* Create the PortB EDAC device */
1425 edac_idx = edac_device_alloc_index();
1426 dci = edac_device_alloc_ctl_info(sizeof(*altdev), ecc_name, 1,
1427 ecc_name, 1, 0, NULL, 0, edac_idx);
1429 edac_printk(KERN_ERR, EDAC_DEVICE,
1430 "%s: Unable to allocate PortB EDAC device\n",
1435 /* Initialize the PortB EDAC device structure from PortA structure */
1436 altdev = dci->pvt_info;
1439 if (!devres_open_group(&altdev->ddev, altr_portb_setup, GFP_KERNEL))
1442 /* Update PortB specific values */
1443 altdev->edac_dev_name = ecc_name;
1444 altdev->edac_idx = edac_idx;
1445 altdev->edac_dev = dci;
1447 dci->dev = &altdev->ddev;
1448 dci->ctl_name = "Altera ECC Manager";
1449 dci->mod_name = ecc_name;
1450 dci->dev_name = ecc_name;
1452 /* Update the IRQs for PortB */
1453 altdev->sb_irq = irq_of_parse_and_map(np, 2);
1454 if (!altdev->sb_irq) {
1455 edac_printk(KERN_ERR, EDAC_DEVICE, "Error PortB SBIRQ alloc\n");
1457 goto err_release_group_1;
1459 rc = devm_request_irq(&altdev->ddev, altdev->sb_irq,
1460 prv->ecc_irq_handler,
1461 IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
1464 edac_printk(KERN_ERR, EDAC_DEVICE, "PortB SBERR IRQ error\n");
1465 goto err_release_group_1;
1468 altdev->db_irq = irq_of_parse_and_map(np, 3);
1469 if (!altdev->db_irq) {
1470 edac_printk(KERN_ERR, EDAC_DEVICE, "Error PortB DBIRQ alloc\n");
1472 goto err_release_group_1;
1474 rc = devm_request_irq(&altdev->ddev, altdev->db_irq,
1475 prv->ecc_irq_handler,
1476 IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
1479 edac_printk(KERN_ERR, EDAC_DEVICE, "PortB DBERR IRQ error\n");
1480 goto err_release_group_1;
1483 rc = edac_device_add_device(dci);
1485 edac_printk(KERN_ERR, EDAC_DEVICE,
1486 "edac_device_add_device portB failed\n");
1488 goto err_release_group_1;
1490 altr_create_edacdev_dbgfs(dci, prv);
1492 list_add(&altdev->next, &altdev->edac->a10_ecc_devices);
1494 devres_remove_group(&altdev->ddev, altr_portb_setup);
1498 err_release_group_1:
1499 edac_device_free_ctl_info(dci);
1500 devres_release_group(&altdev->ddev, altr_portb_setup);
1501 edac_printk(KERN_ERR, EDAC_DEVICE,
1502 "%s:Error setting up EDAC device: %d\n", ecc_name, rc);
1506 static irqreturn_t altr_edac_a10_ecc_irq_portb(int irq, void *dev_id)
1508 struct altr_edac_device_dev *ad = dev_id;
1509 void __iomem *base = ad->base;
1510 const struct edac_device_prv_data *priv = ad->data;
1512 if (irq == ad->sb_irq) {
1513 writel(priv->ce_clear_mask,
1514 base + ALTR_A10_ECC_INTSTAT_OFST);
1515 edac_device_handle_ce(ad->edac_dev, 0, 0, ad->edac_dev_name);
1517 } else if (irq == ad->db_irq) {
1518 writel(priv->ue_clear_mask,
1519 base + ALTR_A10_ECC_INTSTAT_OFST);
1520 edac_device_handle_ue(ad->edac_dev, 0, 0, ad->edac_dev_name);
1524 WARN_ONCE(1, "Unhandled IRQ%d on Port B.", irq);
1529 static const struct edac_device_prv_data a10_sdmmcecca_data = {
1530 .setup = altr_portb_setup,
1531 .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1532 .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1533 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1534 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1535 .ce_set_mask = ALTR_A10_ECC_SERRPENA,
1536 .ue_set_mask = ALTR_A10_ECC_DERRPENA,
1537 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1538 .ecc_irq_handler = altr_edac_a10_ecc_irq,
1539 .inject_fops = &altr_edac_a10_device_inject_fops,
1542 static const struct edac_device_prv_data a10_sdmmceccb_data = {
1543 .setup = altr_portb_setup,
1544 .ce_clear_mask = ALTR_A10_ECC_SERRPENB,
1545 .ue_clear_mask = ALTR_A10_ECC_DERRPENB,
1546 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1547 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1548 .ce_set_mask = ALTR_A10_ECC_TSERRB,
1549 .ue_set_mask = ALTR_A10_ECC_TDERRB,
1550 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1551 .ecc_irq_handler = altr_edac_a10_ecc_irq_portb,
1552 .inject_fops = &altr_edac_a10_device_inject_fops,
1555 static int __init socfpga_init_sdmmc_ecc(void)
1558 struct device_node *child;
1560 if (!socfpga_is_a10())
1563 child = of_find_compatible_node(NULL, NULL, "altr,socfpga-sdmmc-ecc");
1565 edac_printk(KERN_WARNING, EDAC_DEVICE, "SDMMC node not found\n");
1569 if (!of_device_is_available(child))
1572 if (validate_parent_available(child))
1575 rc = altr_init_a10_ecc_block(child, ALTR_A10_SDMMC_IRQ_MASK,
1576 a10_sdmmcecca_data.ecc_enable_mask, 1);
1582 early_initcall(socfpga_init_sdmmc_ecc);
1584 #endif /* CONFIG_EDAC_ALTERA_SDMMC */
1586 /********************* Arria10 EDAC Device Functions *************************/
1587 static const struct of_device_id altr_edac_a10_device_of_match[] = {
1588 #ifdef CONFIG_EDAC_ALTERA_L2C
1589 { .compatible = "altr,socfpga-a10-l2-ecc", .data = &a10_l2ecc_data },
1591 #ifdef CONFIG_EDAC_ALTERA_OCRAM
1592 { .compatible = "altr,socfpga-a10-ocram-ecc",
1593 .data = &a10_ocramecc_data },
1595 #ifdef CONFIG_EDAC_ALTERA_ETHERNET
1596 { .compatible = "altr,socfpga-eth-mac-ecc",
1597 .data = &a10_enetecc_data },
1599 #ifdef CONFIG_EDAC_ALTERA_NAND
1600 { .compatible = "altr,socfpga-nand-ecc", .data = &a10_nandecc_data },
1602 #ifdef CONFIG_EDAC_ALTERA_DMA
1603 { .compatible = "altr,socfpga-dma-ecc", .data = &a10_dmaecc_data },
1605 #ifdef CONFIG_EDAC_ALTERA_USB
1606 { .compatible = "altr,socfpga-usb-ecc", .data = &a10_usbecc_data },
1608 #ifdef CONFIG_EDAC_ALTERA_QSPI
1609 { .compatible = "altr,socfpga-qspi-ecc", .data = &a10_qspiecc_data },
1611 #ifdef CONFIG_EDAC_ALTERA_SDMMC
1612 { .compatible = "altr,socfpga-sdmmc-ecc", .data = &a10_sdmmcecca_data },
1616 MODULE_DEVICE_TABLE(of, altr_edac_a10_device_of_match);
1619 * The Arria10 EDAC Device Functions differ from the Cyclone5/Arria5
1620 * because 2 IRQs are shared among the all ECC peripherals. The ECC
1621 * manager manages the IRQs and the children.
1622 * Based on xgene_edac.c peripheral code.
1625 static ssize_t altr_edac_a10_device_trig(struct file *file,
1626 const char __user *user_buf,
1627 size_t count, loff_t *ppos)
1629 struct edac_device_ctl_info *edac_dci = file->private_data;
1630 struct altr_edac_device_dev *drvdata = edac_dci->pvt_info;
1631 const struct edac_device_prv_data *priv = drvdata->data;
1632 void __iomem *set_addr = (drvdata->base + priv->set_err_ofst);
1633 unsigned long flags;
1636 if (!user_buf || get_user(trig_type, user_buf))
1639 local_irq_save(flags);
1640 if (trig_type == ALTR_UE_TRIGGER_CHAR)
1641 writel(priv->ue_set_mask, set_addr);
1643 writel(priv->ce_set_mask, set_addr);
1644 /* Ensure the interrupt test bits are set */
1646 local_irq_restore(flags);
1651 static void altr_edac_a10_irq_handler(struct irq_desc *desc)
1653 int dberr, bit, sm_offset, irq_status;
1654 struct altr_arria10_edac *edac = irq_desc_get_handler_data(desc);
1655 struct irq_chip *chip = irq_desc_get_chip(desc);
1656 int irq = irq_desc_get_irq(desc);
1658 dberr = (irq == edac->db_irq) ? 1 : 0;
1659 sm_offset = dberr ? A10_SYSMGR_ECC_INTSTAT_DERR_OFST :
1660 A10_SYSMGR_ECC_INTSTAT_SERR_OFST;
1662 chained_irq_enter(chip, desc);
1664 regmap_read(edac->ecc_mgr_map, sm_offset, &irq_status);
1666 for_each_set_bit(bit, (unsigned long *)&irq_status, 32) {
1667 irq = irq_linear_revmap(edac->domain, dberr * 32 + bit);
1669 generic_handle_irq(irq);
1672 chained_irq_exit(chip, desc);
1675 static int validate_parent_available(struct device_node *np)
1677 struct device_node *parent;
1680 /* Ensure parent device is enabled if parent node exists */
1681 parent = of_parse_phandle(np, "altr,ecc-parent", 0);
1682 if (parent && !of_device_is_available(parent))
1685 of_node_put(parent);
1689 static int altr_edac_a10_device_add(struct altr_arria10_edac *edac,
1690 struct device_node *np)
1692 struct edac_device_ctl_info *dci;
1693 struct altr_edac_device_dev *altdev;
1694 char *ecc_name = (char *)np->name;
1695 struct resource res;
1698 const struct edac_device_prv_data *prv;
1699 /* Get matching node and check for valid result */
1700 const struct of_device_id *pdev_id =
1701 of_match_node(altr_edac_a10_device_of_match, np);
1702 if (IS_ERR_OR_NULL(pdev_id))
1705 /* Get driver specific data for this EDAC device */
1706 prv = pdev_id->data;
1707 if (IS_ERR_OR_NULL(prv))
1710 if (validate_parent_available(np))
1713 if (!devres_open_group(edac->dev, altr_edac_a10_device_add, GFP_KERNEL))
1716 rc = of_address_to_resource(np, 0, &res);
1718 edac_printk(KERN_ERR, EDAC_DEVICE,
1719 "%s: no resource address\n", ecc_name);
1720 goto err_release_group;
1723 edac_idx = edac_device_alloc_index();
1724 dci = edac_device_alloc_ctl_info(sizeof(*altdev), ecc_name,
1725 1, ecc_name, 1, 0, NULL, 0,
1729 edac_printk(KERN_ERR, EDAC_DEVICE,
1730 "%s: Unable to allocate EDAC device\n", ecc_name);
1732 goto err_release_group;
1735 altdev = dci->pvt_info;
1736 dci->dev = edac->dev;
1737 altdev->edac_dev_name = ecc_name;
1738 altdev->edac_idx = edac_idx;
1739 altdev->edac = edac;
1740 altdev->edac_dev = dci;
1742 altdev->ddev = *edac->dev;
1743 dci->dev = &altdev->ddev;
1744 dci->ctl_name = "Altera ECC Manager";
1745 dci->mod_name = ecc_name;
1746 dci->dev_name = ecc_name;
1748 altdev->base = devm_ioremap_resource(edac->dev, &res);
1749 if (IS_ERR(altdev->base)) {
1750 rc = PTR_ERR(altdev->base);
1751 goto err_release_group1;
1754 /* Check specific dependencies for the module */
1755 if (altdev->data->setup) {
1756 rc = altdev->data->setup(altdev);
1758 goto err_release_group1;
1761 altdev->sb_irq = irq_of_parse_and_map(np, 0);
1762 if (!altdev->sb_irq) {
1763 edac_printk(KERN_ERR, EDAC_DEVICE, "Error allocating SBIRQ\n");
1765 goto err_release_group1;
1767 rc = devm_request_irq(edac->dev, altdev->sb_irq, prv->ecc_irq_handler,
1768 IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
1771 edac_printk(KERN_ERR, EDAC_DEVICE, "No SBERR IRQ resource\n");
1772 goto err_release_group1;
1775 altdev->db_irq = irq_of_parse_and_map(np, 1);
1776 if (!altdev->db_irq) {
1777 edac_printk(KERN_ERR, EDAC_DEVICE, "Error allocating DBIRQ\n");
1779 goto err_release_group1;
1781 rc = devm_request_irq(edac->dev, altdev->db_irq, prv->ecc_irq_handler,
1782 IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
1785 edac_printk(KERN_ERR, EDAC_DEVICE, "No DBERR IRQ resource\n");
1786 goto err_release_group1;
1789 rc = edac_device_add_device(dci);
1791 dev_err(edac->dev, "edac_device_add_device failed\n");
1793 goto err_release_group1;
1796 altr_create_edacdev_dbgfs(dci, prv);
1798 list_add(&altdev->next, &edac->a10_ecc_devices);
1800 devres_remove_group(edac->dev, altr_edac_a10_device_add);
1805 edac_device_free_ctl_info(dci);
1807 devres_release_group(edac->dev, NULL);
1808 edac_printk(KERN_ERR, EDAC_DEVICE,
1809 "%s:Error setting up EDAC device: %d\n", ecc_name, rc);
1814 static void a10_eccmgr_irq_mask(struct irq_data *d)
1816 struct altr_arria10_edac *edac = irq_data_get_irq_chip_data(d);
1818 regmap_write(edac->ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_SET_OFST,
1822 static void a10_eccmgr_irq_unmask(struct irq_data *d)
1824 struct altr_arria10_edac *edac = irq_data_get_irq_chip_data(d);
1826 regmap_write(edac->ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_CLR_OFST,
1830 static int a10_eccmgr_irqdomain_map(struct irq_domain *d, unsigned int irq,
1831 irq_hw_number_t hwirq)
1833 struct altr_arria10_edac *edac = d->host_data;
1835 irq_set_chip_and_handler(irq, &edac->irq_chip, handle_simple_irq);
1836 irq_set_chip_data(irq, edac);
1837 irq_set_noprobe(irq);
1842 static struct irq_domain_ops a10_eccmgr_ic_ops = {
1843 .map = a10_eccmgr_irqdomain_map,
1844 .xlate = irq_domain_xlate_twocell,
1847 static int altr_edac_a10_probe(struct platform_device *pdev)
1849 struct altr_arria10_edac *edac;
1850 struct device_node *child;
1852 edac = devm_kzalloc(&pdev->dev, sizeof(*edac), GFP_KERNEL);
1856 edac->dev = &pdev->dev;
1857 platform_set_drvdata(pdev, edac);
1858 INIT_LIST_HEAD(&edac->a10_ecc_devices);
1860 edac->ecc_mgr_map = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
1861 "altr,sysmgr-syscon");
1862 if (IS_ERR(edac->ecc_mgr_map)) {
1863 edac_printk(KERN_ERR, EDAC_DEVICE,
1864 "Unable to get syscon altr,sysmgr-syscon\n");
1865 return PTR_ERR(edac->ecc_mgr_map);
1868 edac->irq_chip.name = pdev->dev.of_node->name;
1869 edac->irq_chip.irq_mask = a10_eccmgr_irq_mask;
1870 edac->irq_chip.irq_unmask = a10_eccmgr_irq_unmask;
1871 edac->domain = irq_domain_add_linear(pdev->dev.of_node, 64,
1872 &a10_eccmgr_ic_ops, edac);
1873 if (!edac->domain) {
1874 dev_err(&pdev->dev, "Error adding IRQ domain\n");
1878 edac->sb_irq = platform_get_irq(pdev, 0);
1879 if (edac->sb_irq < 0) {
1880 dev_err(&pdev->dev, "No SBERR IRQ resource\n");
1881 return edac->sb_irq;
1884 irq_set_chained_handler_and_data(edac->sb_irq,
1885 altr_edac_a10_irq_handler,
1888 edac->db_irq = platform_get_irq(pdev, 1);
1889 if (edac->db_irq < 0) {
1890 dev_err(&pdev->dev, "No DBERR IRQ resource\n");
1891 return edac->db_irq;
1893 irq_set_chained_handler_and_data(edac->db_irq,
1894 altr_edac_a10_irq_handler,
1897 for_each_child_of_node(pdev->dev.of_node, child) {
1898 if (!of_device_is_available(child))
1901 if (of_device_is_compatible(child, "altr,socfpga-a10-l2-ecc") ||
1902 of_device_is_compatible(child, "altr,socfpga-a10-ocram-ecc") ||
1903 of_device_is_compatible(child, "altr,socfpga-eth-mac-ecc") ||
1904 of_device_is_compatible(child, "altr,socfpga-nand-ecc") ||
1905 of_device_is_compatible(child, "altr,socfpga-dma-ecc") ||
1906 of_device_is_compatible(child, "altr,socfpga-usb-ecc") ||
1907 of_device_is_compatible(child, "altr,socfpga-qspi-ecc") ||
1908 of_device_is_compatible(child, "altr,socfpga-sdmmc-ecc"))
1910 altr_edac_a10_device_add(edac, child);
1912 else if (of_device_is_compatible(child, "altr,sdram-edac-a10"))
1913 of_platform_populate(pdev->dev.of_node,
1914 altr_sdram_ctrl_of_match,
1921 static const struct of_device_id altr_edac_a10_of_match[] = {
1922 { .compatible = "altr,socfpga-a10-ecc-manager" },
1925 MODULE_DEVICE_TABLE(of, altr_edac_a10_of_match);
1927 static struct platform_driver altr_edac_a10_driver = {
1928 .probe = altr_edac_a10_probe,
1930 .name = "socfpga_a10_ecc_manager",
1931 .of_match_table = altr_edac_a10_of_match,
1934 module_platform_driver(altr_edac_a10_driver);
1936 MODULE_LICENSE("GPL v2");
1937 MODULE_AUTHOR("Thor Thayer");
1938 MODULE_DESCRIPTION("EDAC Driver for Altera Memories");