2 * GHES/EDAC Linux driver
4 * This file may be distributed under the terms of the GNU General Public
7 * Copyright (c) 2013 by Mauro Carvalho Chehab
9 * Red Hat Inc. http://www.redhat.com
12 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
14 #include <acpi/ghes.h>
15 #include <linux/edac.h>
16 #include <linux/dmi.h>
17 #include "edac_module.h"
18 #include <ras/ras_event.h>
20 #define GHES_EDAC_REVISION " Ver: 1.0.0"
22 struct ghes_edac_pvt {
23 struct list_head list;
25 struct mem_ctl_info *mci;
27 /* Buffers for the error handling routine */
28 char detail_location[240];
29 char other_detail[160];
33 static LIST_HEAD(ghes_reglist);
34 static DEFINE_MUTEX(ghes_edac_lock);
35 static int ghes_edac_mc_num;
38 /* Memory Device - Type 17 of SMBIOS spec */
39 struct memdev_dmi_entry {
43 u16 phys_mem_array_handle;
44 u16 mem_err_info_handle;
61 u16 conf_mem_clk_speed;
62 } __attribute__((__packed__));
64 struct ghes_edac_dimm_fill {
65 struct mem_ctl_info *mci;
69 static void ghes_edac_count_dimms(const struct dmi_header *dh, void *arg)
73 if (dh->type == DMI_ENTRY_MEM_DEVICE)
77 static void ghes_edac_dmidecode(const struct dmi_header *dh, void *arg)
79 struct ghes_edac_dimm_fill *dimm_fill = arg;
80 struct mem_ctl_info *mci = dimm_fill->mci;
82 if (dh->type == DMI_ENTRY_MEM_DEVICE) {
83 struct memdev_dmi_entry *entry = (struct memdev_dmi_entry *)dh;
84 struct dimm_info *dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms,
86 dimm_fill->count, 0, 0);
88 if (entry->size == 0xffff) {
89 pr_info("Can't get DIMM%i size\n",
91 dimm->nr_pages = MiB_TO_PAGES(32);/* Unknown */
92 } else if (entry->size == 0x7fff) {
93 dimm->nr_pages = MiB_TO_PAGES(entry->extended_size);
95 if (entry->size & 1 << 15)
96 dimm->nr_pages = MiB_TO_PAGES((entry->size &
99 dimm->nr_pages = MiB_TO_PAGES(entry->size);
102 switch (entry->memory_type) {
104 if (entry->type_detail & 1 << 13)
105 dimm->mtype = MEM_RDDR;
107 dimm->mtype = MEM_DDR;
110 if (entry->type_detail & 1 << 13)
111 dimm->mtype = MEM_RDDR2;
113 dimm->mtype = MEM_DDR2;
116 dimm->mtype = MEM_FB_DDR2;
119 if (entry->type_detail & 1 << 13)
120 dimm->mtype = MEM_RDDR3;
122 dimm->mtype = MEM_DDR3;
125 if (entry->type_detail & 1 << 6)
126 dimm->mtype = MEM_RMBS;
127 else if ((entry->type_detail & ((1 << 7) | (1 << 13)))
128 == ((1 << 7) | (1 << 13)))
129 dimm->mtype = MEM_RDR;
130 else if (entry->type_detail & 1 << 7)
131 dimm->mtype = MEM_SDR;
132 else if (entry->type_detail & 1 << 9)
133 dimm->mtype = MEM_EDO;
135 dimm->mtype = MEM_UNKNOWN;
139 * Actually, we can only detect if the memory has bits for
142 if (entry->total_width == entry->data_width)
143 dimm->edac_mode = EDAC_NONE;
145 dimm->edac_mode = EDAC_SECDED;
147 dimm->dtype = DEV_UNKNOWN;
148 dimm->grain = 128; /* Likely, worse case */
151 * FIXME: It shouldn't be hard to also fill the DIMM labels
154 if (dimm->nr_pages) {
155 edac_dbg(1, "DIMM%i: %s size = %d MB%s\n",
156 dimm_fill->count, edac_mem_types[dimm->mtype],
157 PAGES_TO_MiB(dimm->nr_pages),
158 (dimm->edac_mode != EDAC_NONE) ? "(ECC)" : "");
159 edac_dbg(2, "\ttype %d, detail 0x%02x, width %d(total %d)\n",
160 entry->memory_type, entry->type_detail,
161 entry->total_width, entry->data_width);
168 void ghes_edac_report_mem_error(struct ghes *ghes, int sev,
169 struct cper_sec_mem_err *mem_err)
171 enum hw_event_mc_err_type type;
172 struct edac_raw_error_desc *e;
173 struct mem_ctl_info *mci;
174 struct ghes_edac_pvt *pvt = NULL;
178 list_for_each_entry(pvt, &ghes_reglist, list) {
179 if (ghes == pvt->ghes)
183 pr_err("Internal error: Can't find EDAC structure\n");
187 e = &mci->error_desc;
189 /* Cleans the error report buffer */
190 memset(e, 0, sizeof (*e));
192 strcpy(e->label, "unknown label");
194 e->other_detail = pvt->other_detail;
198 *pvt->other_detail = '\0';
202 case GHES_SEV_CORRECTED:
203 type = HW_EVENT_ERR_CORRECTED;
205 case GHES_SEV_RECOVERABLE:
206 type = HW_EVENT_ERR_UNCORRECTED;
209 type = HW_EVENT_ERR_FATAL;
213 type = HW_EVENT_ERR_INFO;
216 edac_dbg(1, "error validation_bits: 0x%08llx\n",
217 (long long)mem_err->validation_bits);
219 /* Error type, mapped on e->msg */
220 if (mem_err->validation_bits & CPER_MEM_VALID_ERROR_TYPE) {
222 switch (mem_err->error_type) {
224 p += sprintf(p, "Unknown");
227 p += sprintf(p, "No error");
230 p += sprintf(p, "Single-bit ECC");
233 p += sprintf(p, "Multi-bit ECC");
236 p += sprintf(p, "Single-symbol ChipKill ECC");
239 p += sprintf(p, "Multi-symbol ChipKill ECC");
242 p += sprintf(p, "Master abort");
245 p += sprintf(p, "Target abort");
248 p += sprintf(p, "Parity Error");
251 p += sprintf(p, "Watchdog timeout");
254 p += sprintf(p, "Invalid address");
257 p += sprintf(p, "Mirror Broken");
260 p += sprintf(p, "Memory Sparing");
263 p += sprintf(p, "Scrub corrected error");
266 p += sprintf(p, "Scrub uncorrected error");
269 p += sprintf(p, "Physical Memory Map-out event");
272 p += sprintf(p, "reserved error (%d)",
273 mem_err->error_type);
276 strcpy(pvt->msg, "unknown error");
280 if (mem_err->validation_bits & CPER_MEM_VALID_PA) {
281 e->page_frame_number = mem_err->physical_addr >> PAGE_SHIFT;
282 e->offset_in_page = mem_err->physical_addr & ~PAGE_MASK;
286 if (mem_err->validation_bits & CPER_MEM_VALID_PA_MASK)
287 e->grain = ~(mem_err->physical_addr_mask & ~PAGE_MASK);
289 /* Memory error location, mapped on e->location */
291 if (mem_err->validation_bits & CPER_MEM_VALID_NODE)
292 p += sprintf(p, "node:%d ", mem_err->node);
293 if (mem_err->validation_bits & CPER_MEM_VALID_CARD)
294 p += sprintf(p, "card:%d ", mem_err->card);
295 if (mem_err->validation_bits & CPER_MEM_VALID_MODULE)
296 p += sprintf(p, "module:%d ", mem_err->module);
297 if (mem_err->validation_bits & CPER_MEM_VALID_RANK_NUMBER)
298 p += sprintf(p, "rank:%d ", mem_err->rank);
299 if (mem_err->validation_bits & CPER_MEM_VALID_BANK)
300 p += sprintf(p, "bank:%d ", mem_err->bank);
301 if (mem_err->validation_bits & CPER_MEM_VALID_ROW)
302 p += sprintf(p, "row:%d ", mem_err->row);
303 if (mem_err->validation_bits & CPER_MEM_VALID_COLUMN)
304 p += sprintf(p, "col:%d ", mem_err->column);
305 if (mem_err->validation_bits & CPER_MEM_VALID_BIT_POSITION)
306 p += sprintf(p, "bit_pos:%d ", mem_err->bit_pos);
307 if (mem_err->validation_bits & CPER_MEM_VALID_MODULE_HANDLE) {
308 const char *bank = NULL, *device = NULL;
309 dmi_memdev_name(mem_err->mem_dev_handle, &bank, &device);
310 if (bank != NULL && device != NULL)
311 p += sprintf(p, "DIMM location:%s %s ", bank, device);
313 p += sprintf(p, "DIMM DMI handle: 0x%.4x ",
314 mem_err->mem_dev_handle);
319 /* All other fields are mapped on e->other_detail */
320 p = pvt->other_detail;
321 if (mem_err->validation_bits & CPER_MEM_VALID_ERROR_STATUS) {
322 u64 status = mem_err->error_status;
324 p += sprintf(p, "status(0x%016llx): ", (long long)status);
325 switch ((status >> 8) & 0xff) {
327 p += sprintf(p, "Error detected internal to the component ");
330 p += sprintf(p, "Error detected in the bus ");
333 p += sprintf(p, "Storage error in DRAM memory ");
336 p += sprintf(p, "Storage error in TLB ");
339 p += sprintf(p, "Storage error in cache ");
342 p += sprintf(p, "Error in one or more functional units ");
345 p += sprintf(p, "component failed self test ");
348 p += sprintf(p, "Overflow or undervalue of internal queue ");
351 p += sprintf(p, "Virtual address not found on IO-TLB or IO-PDIR ");
354 p += sprintf(p, "Improper access error ");
357 p += sprintf(p, "Access to a memory address which is not mapped to any component ");
360 p += sprintf(p, "Loss of Lockstep ");
363 p += sprintf(p, "Response not associated with a request ");
366 p += sprintf(p, "Bus parity error - must also set the A, C, or D Bits ");
369 p += sprintf(p, "Detection of a PATH_ERROR ");
372 p += sprintf(p, "Bus operation timeout ");
375 p += sprintf(p, "A read was issued to data that has been poisoned ");
378 p += sprintf(p, "reserved ");
382 if (mem_err->validation_bits & CPER_MEM_VALID_REQUESTOR_ID)
383 p += sprintf(p, "requestorID: 0x%016llx ",
384 (long long)mem_err->requestor_id);
385 if (mem_err->validation_bits & CPER_MEM_VALID_RESPONDER_ID)
386 p += sprintf(p, "responderID: 0x%016llx ",
387 (long long)mem_err->responder_id);
388 if (mem_err->validation_bits & CPER_MEM_VALID_TARGET_ID)
389 p += sprintf(p, "targetID: 0x%016llx ",
390 (long long)mem_err->responder_id);
391 if (p > pvt->other_detail)
394 /* Generate the trace event */
395 grain_bits = fls_long(e->grain);
396 snprintf(pvt->detail_location, sizeof(pvt->detail_location),
397 "APEI location: %s %s", e->location, e->other_detail);
398 trace_mc_event(type, e->msg, e->label, e->error_count,
399 mci->mc_idx, e->top_layer, e->mid_layer, e->low_layer,
400 (e->page_frame_number << PAGE_SHIFT) | e->offset_in_page,
401 grain_bits, e->syndrome, pvt->detail_location);
403 /* Report the error via EDAC API */
404 edac_raw_mc_handle_error(type, mci, e);
406 EXPORT_SYMBOL_GPL(ghes_edac_report_mem_error);
408 int ghes_edac_register(struct ghes *ghes, struct device *dev)
411 int rc, num_dimm = 0;
412 struct mem_ctl_info *mci;
413 struct edac_mc_layer layers[1];
414 struct ghes_edac_pvt *pvt;
415 struct ghes_edac_dimm_fill dimm_fill;
417 /* Get the number of DIMMs */
418 dmi_walk(ghes_edac_count_dimms, &num_dimm);
420 /* Check if we've got a bogus BIOS */
426 layers[0].type = EDAC_MC_LAYER_ALL_MEM;
427 layers[0].size = num_dimm;
428 layers[0].is_virt_csrow = true;
431 * We need to serialize edac_mc_alloc() and edac_mc_add_mc(),
432 * to avoid duplicated memory controller numbers
434 mutex_lock(&ghes_edac_lock);
435 mci = edac_mc_alloc(ghes_edac_mc_num, ARRAY_SIZE(layers), layers,
438 pr_info("Can't allocate memory for EDAC data\n");
439 mutex_unlock(&ghes_edac_lock);
444 memset(pvt, 0, sizeof(*pvt));
445 list_add_tail(&pvt->list, &ghes_reglist);
450 mci->mtype_cap = MEM_FLAG_EMPTY;
451 mci->edac_ctl_cap = EDAC_FLAG_NONE;
452 mci->edac_cap = EDAC_FLAG_NONE;
453 mci->mod_name = "ghes_edac.c";
454 mci->mod_ver = GHES_EDAC_REVISION;
455 mci->ctl_name = "ghes_edac";
456 mci->dev_name = "ghes";
458 if (!ghes_edac_mc_num) {
460 pr_info("This EDAC driver relies on BIOS to enumerate memory and get error reports.\n");
461 pr_info("Unfortunately, not all BIOSes reflect the memory layout correctly.\n");
462 pr_info("So, the end result of using this driver varies from vendor to vendor.\n");
463 pr_info("If you find incorrect reports, please contact your hardware vendor\n");
464 pr_info("to correct its BIOS.\n");
465 pr_info("This system has %d DIMM sockets.\n",
468 pr_info("This system has a very crappy BIOS: It doesn't even list the DIMMS.\n");
469 pr_info("Its SMBIOS info is wrong. It is doubtful that the error report would\n");
470 pr_info("work on such system. Use this driver with caution\n");
476 * Fill DIMM info from DMI for the memory controller #0
478 * Keep it in blank for the other memory controllers, as
479 * there's no reliable way to properly credit each DIMM to
480 * the memory controller, as different BIOSes fill the
481 * DMI bank location fields on different ways
483 if (!ghes_edac_mc_num) {
486 dmi_walk(ghes_edac_dmidecode, &dimm_fill);
489 struct dimm_info *dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms,
490 mci->n_layers, 0, 0, 0);
494 dimm->mtype = MEM_UNKNOWN;
495 dimm->dtype = DEV_UNKNOWN;
496 dimm->edac_mode = EDAC_SECDED;
499 rc = edac_mc_add_mc(mci);
501 pr_info("Can't register at EDAC core\n");
503 mutex_unlock(&ghes_edac_lock);
508 mutex_unlock(&ghes_edac_lock);
511 EXPORT_SYMBOL_GPL(ghes_edac_register);
513 void ghes_edac_unregister(struct ghes *ghes)
515 struct mem_ctl_info *mci;
516 struct ghes_edac_pvt *pvt, *tmp;
518 list_for_each_entry_safe(pvt, tmp, &ghes_reglist, list) {
519 if (ghes == pvt->ghes) {
521 edac_mc_del_mc(mci->pdev);
523 list_del(&pvt->list);
527 EXPORT_SYMBOL_GPL(ghes_edac_unregister);