drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/kthread.h>
  29 #include <linux/console.h>
  30 #include <linux/slab.h>
  31 #include <linux/debugfs.h>
  32 #include <drm/drmP.h>
  33 #include <drm/drm_crtc_helper.h>
  34 #include <drm/amdgpu_drm.h>
  35 #include <linux/vgaarb.h>
  36 #include <linux/vga_switcheroo.h>
  37 #include <linux/efi.h>
  38 #include "amdgpu.h"
  39 #include "amdgpu_trace.h"
  40 #include "amdgpu_i2c.h"
  41 #include "atom.h"
  42 #include "amdgpu_atombios.h"
  43 #include "amd_pcie.h"
  44 #ifdef CONFIG_DRM_AMDGPU_CIK
  45 #include "cik.h"
  46 #endif
  47 #include "vi.h"
  48 #include "bif/bif_4_1_d.h"
  49
  50 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev);
  51 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev);
  52
  53 static const char *amdgpu_asic_name[] = {
  54         "BONAIRE",
  55         "KAVERI",
  56         "KABINI",
  57         "HAWAII",
  58         "MULLINS",
  59         "TOPAZ",
  60         "TONGA",
  61         "FIJI",
  62         "CARRIZO",
  63         "STONEY",
  64         "POLARIS10",
  65         "POLARIS11",
  66         "LAST",
  67 };
  68
  69 bool amdgpu_device_is_px(struct drm_device *dev)
  70 {
  71         struct amdgpu_device *adev = dev->dev_private;
  72
  73         if (adev->flags & AMD_IS_PX)
  74                 return true;
  75         return false;
  76 }
  77
  78 /*
  79  * MMIO register access helper functions.
  80  */
  81 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
  82                         bool always_indirect)
  83 {
  84         uint32_t ret;
  85
  86         if ((reg * 4) < adev->rmmio_size && !always_indirect)
  87                 ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
  88         else {
  89                 unsigned long flags;
  90
  91                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
  92                 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
  93                 ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
  94                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
  95         }
  96         trace_amdgpu_mm_rreg(adev->pdev->device, reg, ret);
  97         return ret;
  98 }
  99
 100 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
 101                     bool always_indirect)
 102 {
 103         trace_amdgpu_mm_wreg(adev->pdev->device, reg, v);
 104
 105         if ((reg * 4) < adev->rmmio_size && !always_indirect)
 106                 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
 107         else {
 108                 unsigned long flags;
 109
 110                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
 111                 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
 112                 writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
 113                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
 114         }
 115 }
 116
 117 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg)
 118 {
 119         if ((reg * 4) < adev->rio_mem_size)
 120                 return ioread32(adev->rio_mem + (reg * 4));
 121         else {
 122                 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
 123                 return ioread32(adev->rio_mem + (mmMM_DATA * 4));
 124         }
 125 }
 126
 127 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 128 {
 129
 130         if ((reg * 4) < adev->rio_mem_size)
 131                 iowrite32(v, adev->rio_mem + (reg * 4));
 132         else {
 133                 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
 134                 iowrite32(v, adev->rio_mem + (mmMM_DATA * 4));
 135         }
 136 }
 137
 138 /**
 139  * amdgpu_mm_rdoorbell - read a doorbell dword
 140  *
 141  * @adev: amdgpu_device pointer
 142  * @index: doorbell index
 143  *
 144  * Returns the value in the doorbell aperture at the
 145  * requested doorbell index (CIK).
 146  */
 147 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index)
 148 {
 149         if (index < adev->doorbell.num_doorbells) {
 150                 return readl(adev->doorbell.ptr + index);
 151         } else {
 152                 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
 153                 return 0;
 154         }
 155 }
 156
 157 /**
 158  * amdgpu_mm_wdoorbell - write a doorbell dword
 159  *
 160  * @adev: amdgpu_device pointer
 161  * @index: doorbell index
 162  * @v: value to write
 163  *
 164  * Writes @v to the doorbell aperture at the
 165  * requested doorbell index (CIK).
 166  */
 167 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v)
 168 {
 169         if (index < adev->doorbell.num_doorbells) {
 170                 writel(v, adev->doorbell.ptr + index);
 171         } else {
 172                 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
 173         }
 174 }
 175
 176 /**
 177  * amdgpu_invalid_rreg - dummy reg read function
 178  *
 179  * @adev: amdgpu device pointer
 180  * @reg: offset of register
 181  *
 182  * Dummy register read function.  Used for register blocks
 183  * that certain asics don't have (all asics).
 184  * Returns the value in the register.
 185  */
 186 static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg)
 187 {
 188         DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
 189         BUG();
 190         return 0;
 191 }
 192
 193 /**
 194  * amdgpu_invalid_wreg - dummy reg write function
 195  *
 196  * @adev: amdgpu device pointer
 197  * @reg: offset of register
 198  * @v: value to write to the register
 199  *
 200  * Dummy register read function.  Used for register blocks
 201  * that certain asics don't have (all asics).
 202  */
 203 static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
 204 {
 205         DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
 206                   reg, v);
 207         BUG();
 208 }
 209
 210 /**
 211  * amdgpu_block_invalid_rreg - dummy reg read function
 212  *
 213  * @adev: amdgpu device pointer
 214  * @block: offset of instance
 215  * @reg: offset of register
 216  *
 217  * Dummy register read function.  Used for register blocks
 218  * that certain asics don't have (all asics).
 219  * Returns the value in the register.
 220  */
 221 static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev,
 222                                           uint32_t block, uint32_t reg)
 223 {
 224         DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",
 225                   reg, block);
 226         BUG();
 227         return 0;
 228 }
 229
 230 /**
 231  * amdgpu_block_invalid_wreg - dummy reg write function
 232  *
 233  * @adev: amdgpu device pointer
 234  * @block: offset of instance
 235  * @reg: offset of register
 236  * @v: value to write to the register
 237  *
 238  * Dummy register read function.  Used for register blocks
 239  * that certain asics don't have (all asics).
 240  */
 241 static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev,
 242                                       uint32_t block,
 243                                       uint32_t reg, uint32_t v)
 244 {
 245         DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",
 246                   reg, block, v);
 247         BUG();
 248 }
 249
 250 static int amdgpu_vram_scratch_init(struct amdgpu_device *adev)
 251 {
 252         int r;
 253
 254         if (adev->vram_scratch.robj == NULL) {
 255                 r = amdgpu_bo_create(adev, AMDGPU_GPU_PAGE_SIZE,
 256                                      PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM,
 257                                      AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
 258                                      NULL, NULL, &adev->vram_scratch.robj);
 259                 if (r) {
 260                         return r;
 261                 }
 262         }
 263
 264         r = amdgpu_bo_reserve(adev->vram_scratch.robj, false);
 265         if (unlikely(r != 0))
 266                 return r;
 267         r = amdgpu_bo_pin(adev->vram_scratch.robj,
 268                           AMDGPU_GEM_DOMAIN_VRAM, &adev->vram_scratch.gpu_addr);
 269         if (r) {
 270                 amdgpu_bo_unreserve(adev->vram_scratch.robj);
 271                 return r;
 272         }
 273         r = amdgpu_bo_kmap(adev->vram_scratch.robj,
 274                                 (void **)&adev->vram_scratch.ptr);
 275         if (r)
 276                 amdgpu_bo_unpin(adev->vram_scratch.robj);
 277         amdgpu_bo_unreserve(adev->vram_scratch.robj);
 278
 279         return r;
 280 }
 281
 282 static void amdgpu_vram_scratch_fini(struct amdgpu_device *adev)
 283 {
 284         int r;
 285
 286         if (adev->vram_scratch.robj == NULL) {
 287                 return;
 288         }
 289         r = amdgpu_bo_reserve(adev->vram_scratch.robj, false);
 290         if (likely(r == 0)) {
 291                 amdgpu_bo_kunmap(adev->vram_scratch.robj);
 292                 amdgpu_bo_unpin(adev->vram_scratch.robj);
 293                 amdgpu_bo_unreserve(adev->vram_scratch.robj);
 294         }
 295         amdgpu_bo_unref(&adev->vram_scratch.robj);
 296 }
 297
 298 /**
 299  * amdgpu_program_register_sequence - program an array of registers.
 300  *
 301  * @adev: amdgpu_device pointer
 302  * @registers: pointer to the register array
 303  * @array_size: size of the register array
 304  *
 305  * Programs an array or registers with and and or masks.
 306  * This is a helper for setting golden registers.
 307  */
 308 void amdgpu_program_register_sequence(struct amdgpu_device *adev,
 309                                       const u32 *registers,
 310                                       const u32 array_size)
 311 {
 312         u32 tmp, reg, and_mask, or_mask;
 313         int i;
 314
 315         if (array_size % 3)
 316                 return;
 317
 318         for (i = 0; i < array_size; i +=3) {
 319                 reg = registers[i + 0];
 320                 and_mask = registers[i + 1];
 321                 or_mask = registers[i + 2];
 322
 323                 if (and_mask == 0xffffffff) {
 324                         tmp = or_mask;
 325                 } else {
 326                         tmp = RREG32(reg);
 327                         tmp &= ~and_mask;
 328                         tmp |= or_mask;
 329                 }
 330                 WREG32(reg, tmp);
 331         }
 332 }
 333
 334 void amdgpu_pci_config_reset(struct amdgpu_device *adev)
 335 {
 336         pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA);
 337 }
 338
 339 /*
 340  * GPU doorbell aperture helpers function.
 341  */
 342 /**
 343  * amdgpu_doorbell_init - Init doorbell driver information.
 344  *
 345  * @adev: amdgpu_device pointer
 346  *
 347  * Init doorbell driver information (CIK)
 348  * Returns 0 on success, error on failure.
 349  */
 350 static int amdgpu_doorbell_init(struct amdgpu_device *adev)
 351 {
 352         /* doorbell bar mapping */
 353         adev->doorbell.base = pci_resource_start(adev->pdev, 2);
 354         adev->doorbell.size = pci_resource_len(adev->pdev, 2);
 355
 356         adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32),
 357                                              AMDGPU_DOORBELL_MAX_ASSIGNMENT+1);
 358         if (adev->doorbell.num_doorbells == 0)
 359                 return -EINVAL;
 360
 361         adev->doorbell.ptr = ioremap(adev->doorbell.base, adev->doorbell.num_doorbells * sizeof(u32));
 362         if (adev->doorbell.ptr == NULL) {
 363                 return -ENOMEM;
 364         }
 365         DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)adev->doorbell.base);
 366         DRM_INFO("doorbell mmio size: %u\n", (unsigned)adev->doorbell.size);
 367
 368         return 0;
 369 }
 370
 371 /**
 372  * amdgpu_doorbell_fini - Tear down doorbell driver information.
 373  *
 374  * @adev: amdgpu_device pointer
 375  *
 376  * Tear down doorbell driver information (CIK)
 377  */
 378 static void amdgpu_doorbell_fini(struct amdgpu_device *adev)
 379 {
 380         iounmap(adev->doorbell.ptr);
 381         adev->doorbell.ptr = NULL;
 382 }
 383
 384 /**
 385  * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to
 386  *                                setup amdkfd
 387  *
 388  * @adev: amdgpu_device pointer
 389  * @aperture_base: output returning doorbell aperture base physical address
 390  * @aperture_size: output returning doorbell aperture size in bytes
 391  * @start_offset: output returning # of doorbell bytes reserved for amdgpu.
 392  *
 393  * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up,
 394  * takes doorbells required for its own rings and reports the setup to amdkfd.
 395  * amdgpu reserved doorbells are at the start of the doorbell aperture.
 396  */
 397 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
 398                                 phys_addr_t *aperture_base,
 399                                 size_t *aperture_size,
 400                                 size_t *start_offset)
 401 {
 402         /*
 403          * The first num_doorbells are used by amdgpu.
 404          * amdkfd takes whatever's left in the aperture.
 405          */
 406         if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) {
 407                 *aperture_base = adev->doorbell.base;
 408                 *aperture_size = adev->doorbell.size;
 409                 *start_offset = adev->doorbell.num_doorbells * sizeof(u32);
 410         } else {
 411                 *aperture_base = 0;
 412                 *aperture_size = 0;
 413                 *start_offset = 0;
 414         }
 415 }
 416
 417 /*
 418  * amdgpu_wb_*()
 419  * Writeback is the the method by which the the GPU updates special pages
 420  * in memory with the status of certain GPU events (fences, ring pointers,
 421  * etc.).
 422  */
 423
 424 /**
 425  * amdgpu_wb_fini - Disable Writeback and free memory
 426  *
 427  * @adev: amdgpu_device pointer
 428  *
 429  * Disables Writeback and frees the Writeback memory (all asics).
 430  * Used at driver shutdown.
 431  */
 432 static void amdgpu_wb_fini(struct amdgpu_device *adev)
 433 {
 434         if (adev->wb.wb_obj) {
 435                 if (!amdgpu_bo_reserve(adev->wb.wb_obj, false)) {
 436                         amdgpu_bo_kunmap(adev->wb.wb_obj);
 437                         amdgpu_bo_unpin(adev->wb.wb_obj);
 438                         amdgpu_bo_unreserve(adev->wb.wb_obj);
 439                 }
 440                 amdgpu_bo_unref(&adev->wb.wb_obj);
 441                 adev->wb.wb = NULL;
 442                 adev->wb.wb_obj = NULL;
 443         }
 444 }
 445
 446 /**
 447  * amdgpu_wb_init- Init Writeback driver info and allocate memory
 448  *
 449  * @adev: amdgpu_device pointer
 450  *
 451  * Disables Writeback and frees the Writeback memory (all asics).
 452  * Used at driver startup.
 453  * Returns 0 on success or an -error on failure.
 454  */
 455 static int amdgpu_wb_init(struct amdgpu_device *adev)
 456 {
 457         int r;
 458
 459         if (adev->wb.wb_obj == NULL) {
 460                 r = amdgpu_bo_create(adev, AMDGPU_MAX_WB * 4, PAGE_SIZE, true,
 461                                      AMDGPU_GEM_DOMAIN_GTT, 0,  NULL, NULL,
 462                                      &adev->wb.wb_obj);
 463                 if (r) {
 464                         dev_warn(adev->dev, "(%d) create WB bo failed\n", r);
 465                         return r;
 466                 }
 467                 r = amdgpu_bo_reserve(adev->wb.wb_obj, false);
 468                 if (unlikely(r != 0)) {
 469                         amdgpu_wb_fini(adev);
 470                         return r;
 471                 }
 472                 r = amdgpu_bo_pin(adev->wb.wb_obj, AMDGPU_GEM_DOMAIN_GTT,
 473                                 &adev->wb.gpu_addr);
 474                 if (r) {
 475                         amdgpu_bo_unreserve(adev->wb.wb_obj);
 476                         dev_warn(adev->dev, "(%d) pin WB bo failed\n", r);
 477                         amdgpu_wb_fini(adev);
 478                         return r;
 479                 }
 480                 r = amdgpu_bo_kmap(adev->wb.wb_obj, (void **)&adev->wb.wb);
 481                 amdgpu_bo_unreserve(adev->wb.wb_obj);
 482                 if (r) {
 483                         dev_warn(adev->dev, "(%d) map WB bo failed\n", r);
 484                         amdgpu_wb_fini(adev);
 485                         return r;
 486                 }
 487
 488                 adev->wb.num_wb = AMDGPU_MAX_WB;
 489                 memset(&adev->wb.used, 0, sizeof(adev->wb.used));
 490
 491                 /* clear wb memory */
 492                 memset((char *)adev->wb.wb, 0, AMDGPU_GPU_PAGE_SIZE);
 493         }
 494
 495         return 0;
 496 }
 497
 498 /**
 499  * amdgpu_wb_get - Allocate a wb entry
 500  *
 501  * @adev: amdgpu_device pointer
 502  * @wb: wb index
 503  *
 504  * Allocate a wb slot for use by the driver (all asics).
 505  * Returns 0 on success or -EINVAL on failure.
 506  */
 507 int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb)
 508 {
 509         unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb);
 510         if (offset < adev->wb.num_wb) {
 511                 __set_bit(offset, adev->wb.used);
 512                 *wb = offset;
 513                 return 0;
 514         } else {
 515                 return -EINVAL;
 516         }
 517 }
 518
 519 /**
 520  * amdgpu_wb_free - Free a wb entry
 521  *
 522  * @adev: amdgpu_device pointer
 523  * @wb: wb index
 524  *
 525  * Free a wb slot allocated for use by the driver (all asics)
 526  */
 527 void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb)
 528 {
 529         if (wb < adev->wb.num_wb)
 530                 __clear_bit(wb, adev->wb.used);
 531 }
 532
 533 /**
 534  * amdgpu_vram_location - try to find VRAM location
 535  * @adev: amdgpu device structure holding all necessary informations
 536  * @mc: memory controller structure holding memory informations
 537  * @base: base address at which to put VRAM
 538  *
 539  * Function will place try to place VRAM at base address provided
 540  * as parameter (which is so far either PCI aperture address or
 541  * for IGP TOM base address).
 542  *
 543  * If there is not enough space to fit the unvisible VRAM in the 32bits
 544  * address space then we limit the VRAM size to the aperture.
 545  *
 546  * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
 547  * this shouldn't be a problem as we are using the PCI aperture as a reference.
 548  * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
 549  * not IGP.
 550  *
 551  * Note: we use mc_vram_size as on some board we need to program the mc to
 552  * cover the whole aperture even if VRAM size is inferior to aperture size
 553  * Novell bug 204882 + along with lots of ubuntu ones
 554  *
 555  * Note: when limiting vram it's safe to overwritte real_vram_size because
 556  * we are not in case where real_vram_size is inferior to mc_vram_size (ie
 557  * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
 558  * ones)
 559  *
 560  * Note: IGP TOM addr should be the same as the aperture addr, we don't
 561  * explicitly check for that thought.
 562  *
 563  * FIXME: when reducing VRAM size align new size on power of 2.
 564  */
 565 void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base)
 566 {
 567         uint64_t limit = (uint64_t)amdgpu_vram_limit << 20;
 568
 569         mc->vram_start = base;
 570         if (mc->mc_vram_size > (adev->mc.mc_mask - base + 1)) {
 571                 dev_warn(adev->dev, "limiting VRAM to PCI aperture size\n");
 572                 mc->real_vram_size = mc->aper_size;
 573                 mc->mc_vram_size = mc->aper_size;
 574         }
 575         mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
 576         if (limit && limit < mc->real_vram_size)
 577                 mc->real_vram_size = limit;
 578         dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
 579                         mc->mc_vram_size >> 20, mc->vram_start,
 580                         mc->vram_end, mc->real_vram_size >> 20);
 581 }
 582
 583 /**
 584  * amdgpu_gtt_location - try to find GTT location
 585  * @adev: amdgpu device structure holding all necessary informations
 586  * @mc: memory controller structure holding memory informations
 587  *
 588  * Function will place try to place GTT before or after VRAM.
 589  *
 590  * If GTT size is bigger than space left then we ajust GTT size.
 591  * Thus function will never fails.
 592  *
 593  * FIXME: when reducing GTT size align new size on power of 2.
 594  */
 595 void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc)
 596 {
 597         u64 size_af, size_bf;
 598
 599         size_af = ((adev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
 600         size_bf = mc->vram_start & ~mc->gtt_base_align;
 601         if (size_bf > size_af) {
 602                 if (mc->gtt_size > size_bf) {
 603                         dev_warn(adev->dev, "limiting GTT\n");
 604                         mc->gtt_size = size_bf;
 605                 }
 606                 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
 607         } else {
 608                 if (mc->gtt_size > size_af) {
 609                         dev_warn(adev->dev, "limiting GTT\n");
 610                         mc->gtt_size = size_af;
 611                 }
 612                 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
 613         }
 614         mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
 615         dev_info(adev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
 616                         mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
 617 }
 618
 619 /*
 620  * GPU helpers function.
 621  */
 622 /**
 623  * amdgpu_card_posted - check if the hw has already been initialized
 624  *
 625  * @adev: amdgpu_device pointer
 626  *
 627  * Check if the asic has been initialized (all asics).
 628  * Used at driver startup.
 629  * Returns true if initialized or false if not.
 630  */
 631 bool amdgpu_card_posted(struct amdgpu_device *adev)
 632 {
 633         uint32_t reg;
 634
 635         /* then check MEM_SIZE, in case the crtcs are off */
 636         reg = RREG32(mmCONFIG_MEMSIZE);
 637
 638         if (reg)
 639                 return true;
 640
 641         return false;
 642
 643 }
 644
 645 /**
 646  * amdgpu_dummy_page_init - init dummy page used by the driver
 647  *
 648  * @adev: amdgpu_device pointer
 649  *
 650  * Allocate the dummy page used by the driver (all asics).
 651  * This dummy page is used by the driver as a filler for gart entries
 652  * when pages are taken out of the GART
 653  * Returns 0 on sucess, -ENOMEM on failure.
 654  */
 655 int amdgpu_dummy_page_init(struct amdgpu_device *adev)
 656 {
 657         if (adev->dummy_page.page)
 658                 return 0;
 659         adev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
 660         if (adev->dummy_page.page == NULL)
 661                 return -ENOMEM;
 662         adev->dummy_page.addr = pci_map_page(adev->pdev, adev->dummy_page.page,
 663                                         0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 664         if (pci_dma_mapping_error(adev->pdev, adev->dummy_page.addr)) {
 665                 dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n");
 666                 __free_page(adev->dummy_page.page);
 667                 adev->dummy_page.page = NULL;
 668                 return -ENOMEM;
 669         }
 670         return 0;
 671 }
 672
 673 /**
 674  * amdgpu_dummy_page_fini - free dummy page used by the driver
 675  *
 676  * @adev: amdgpu_device pointer
 677  *
 678  * Frees the dummy page used by the driver (all asics).
 679  */
 680 void amdgpu_dummy_page_fini(struct amdgpu_device *adev)
 681 {
 682         if (adev->dummy_page.page == NULL)
 683                 return;
 684         pci_unmap_page(adev->pdev, adev->dummy_page.addr,
 685                         PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 686         __free_page(adev->dummy_page.page);
 687         adev->dummy_page.page = NULL;
 688 }
 689
 690
 691 /* ATOM accessor methods */
 692 /*
 693  * ATOM is an interpreted byte code stored in tables in the vbios.  The
 694  * driver registers callbacks to access registers and the interpreter
 695  * in the driver parses the tables and executes then to program specific
 696  * actions (set display modes, asic init, etc.).  See amdgpu_atombios.c,
 697  * atombios.h, and atom.c
 698  */
 699
 700 /**
 701  * cail_pll_read - read PLL register
 702  *
 703  * @info: atom card_info pointer
 704  * @reg: PLL register offset
 705  *
 706  * Provides a PLL register accessor for the atom interpreter (r4xx+).
 707  * Returns the value of the PLL register.
 708  */
 709 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
 710 {
 711         return 0;
 712 }
 713
 714 /**
 715  * cail_pll_write - write PLL register
 716  *
 717  * @info: atom card_info pointer
 718  * @reg: PLL register offset
 719  * @val: value to write to the pll register
 720  *
 721  * Provides a PLL register accessor for the atom interpreter (r4xx+).
 722  */
 723 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
 724 {
 725
 726 }
 727
 728 /**
 729  * cail_mc_read - read MC (Memory Controller) register
 730  *
 731  * @info: atom card_info pointer
 732  * @reg: MC register offset
 733  *
 734  * Provides an MC register accessor for the atom interpreter (r4xx+).
 735  * Returns the value of the MC register.
 736  */
 737 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
 738 {
 739         return 0;
 740 }
 741
 742 /**
 743  * cail_mc_write - write MC (Memory Controller) register
 744  *
 745  * @info: atom card_info pointer
 746  * @reg: MC register offset
 747  * @val: value to write to the pll register
 748  *
 749  * Provides a MC register accessor for the atom interpreter (r4xx+).
 750  */
 751 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
 752 {
 753
 754 }
 755
 756 /**
 757  * cail_reg_write - write MMIO register
 758  *
 759  * @info: atom card_info pointer
 760  * @reg: MMIO register offset
 761  * @val: value to write to the pll register
 762  *
 763  * Provides a MMIO register accessor for the atom interpreter (r4xx+).
 764  */
 765 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
 766 {
 767         struct amdgpu_device *adev = info->dev->dev_private;
 768
 769         WREG32(reg, val);
 770 }
 771
 772 /**
 773  * cail_reg_read - read MMIO register
 774  *
 775  * @info: atom card_info pointer
 776  * @reg: MMIO register offset
 777  *
 778  * Provides an MMIO register accessor for the atom interpreter (r4xx+).
 779  * Returns the value of the MMIO register.
 780  */
 781 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
 782 {
 783         struct amdgpu_device *adev = info->dev->dev_private;
 784         uint32_t r;
 785
 786         r = RREG32(reg);
 787         return r;
 788 }
 789
 790 /**
 791  * cail_ioreg_write - write IO register
 792  *
 793  * @info: atom card_info pointer
 794  * @reg: IO register offset
 795  * @val: value to write to the pll register
 796  *
 797  * Provides a IO register accessor for the atom interpreter (r4xx+).
 798  */
 799 static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
 800 {
 801         struct amdgpu_device *adev = info->dev->dev_private;
 802
 803         WREG32_IO(reg, val);
 804 }
 805
 806 /**
 807  * cail_ioreg_read - read IO register
 808  *
 809  * @info: atom card_info pointer
 810  * @reg: IO register offset
 811  *
 812  * Provides an IO register accessor for the atom interpreter (r4xx+).
 813  * Returns the value of the IO register.
 814  */
 815 static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
 816 {
 817         struct amdgpu_device *adev = info->dev->dev_private;
 818         uint32_t r;
 819
 820         r = RREG32_IO(reg);
 821         return r;
 822 }
 823
 824 /**
 825  * amdgpu_atombios_fini - free the driver info and callbacks for atombios
 826  *
 827  * @adev: amdgpu_device pointer
 828  *
 829  * Frees the driver info and register access callbacks for the ATOM
 830  * interpreter (r4xx+).
 831  * Called at driver shutdown.
 832  */
 833 static void amdgpu_atombios_fini(struct amdgpu_device *adev)
 834 {
 835         if (adev->mode_info.atom_context) {
 836                 kfree(adev->mode_info.atom_context->scratch);
 837                 kfree(adev->mode_info.atom_context->iio);
 838         }
 839         kfree(adev->mode_info.atom_context);
 840         adev->mode_info.atom_context = NULL;
 841         kfree(adev->mode_info.atom_card_info);
 842         adev->mode_info.atom_card_info = NULL;
 843 }
 844
 845 /**
 846  * amdgpu_atombios_init - init the driver info and callbacks for atombios
 847  *
 848  * @adev: amdgpu_device pointer
 849  *
 850  * Initializes the driver info and register access callbacks for the
 851  * ATOM interpreter (r4xx+).
 852  * Returns 0 on sucess, -ENOMEM on failure.
 853  * Called at driver startup.
 854  */
 855 static int amdgpu_atombios_init(struct amdgpu_device *adev)
 856 {
 857         struct card_info *atom_card_info =
 858             kzalloc(sizeof(struct card_info), GFP_KERNEL);
 859
 860         if (!atom_card_info)
 861                 return -ENOMEM;
 862
 863         adev->mode_info.atom_card_info = atom_card_info;
 864         atom_card_info->dev = adev->ddev;
 865         atom_card_info->reg_read = cail_reg_read;
 866         atom_card_info->reg_write = cail_reg_write;
 867         /* needed for iio ops */
 868         if (adev->rio_mem) {
 869                 atom_card_info->ioreg_read = cail_ioreg_read;
 870                 atom_card_info->ioreg_write = cail_ioreg_write;
 871         } else {
 872                 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
 873                 atom_card_info->ioreg_read = cail_reg_read;
 874                 atom_card_info->ioreg_write = cail_reg_write;
 875         }
 876         atom_card_info->mc_read = cail_mc_read;
 877         atom_card_info->mc_write = cail_mc_write;
 878         atom_card_info->pll_read = cail_pll_read;
 879         atom_card_info->pll_write = cail_pll_write;
 880
 881         adev->mode_info.atom_context = amdgpu_atom_parse(atom_card_info, adev->bios);
 882         if (!adev->mode_info.atom_context) {
 883                 amdgpu_atombios_fini(adev);
 884                 return -ENOMEM;
 885         }
 886
 887         mutex_init(&adev->mode_info.atom_context->mutex);
 888         amdgpu_atombios_scratch_regs_init(adev);
 889         amdgpu_atom_allocate_fb_scratch(adev->mode_info.atom_context);
 890         return 0;
 891 }
 892
 893 /* if we get transitioned to only one device, take VGA back */
 894 /**
 895  * amdgpu_vga_set_decode - enable/disable vga decode
 896  *
 897  * @cookie: amdgpu_device pointer
 898  * @state: enable/disable vga decode
 899  *
 900  * Enable/disable vga decode (all asics).
 901  * Returns VGA resource flags.
 902  */
 903 static unsigned int amdgpu_vga_set_decode(void *cookie, bool state)
 904 {
 905         struct amdgpu_device *adev = cookie;
 906         amdgpu_asic_set_vga_state(adev, state);
 907         if (state)
 908                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 909                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 910         else
 911                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 912 }
 913
 914 /**
 915  * amdgpu_check_pot_argument - check that argument is a power of two
 916  *
 917  * @arg: value to check
 918  *
 919  * Validates that a certain argument is a power of two (all asics).
 920  * Returns true if argument is valid.
 921  */
 922 static bool amdgpu_check_pot_argument(int arg)
 923 {
 924         return (arg & (arg - 1)) == 0;
 925 }
 926
 927 /**
 928  * amdgpu_check_arguments - validate module params
 929  *
 930  * @adev: amdgpu_device pointer
 931  *
 932  * Validates certain module parameters and updates
 933  * the associated values used by the driver (all asics).
 934  */
 935 static void amdgpu_check_arguments(struct amdgpu_device *adev)
 936 {
 937         if (amdgpu_sched_jobs < 4) {
 938                 dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n",
 939                          amdgpu_sched_jobs);
 940                 amdgpu_sched_jobs = 4;
 941         } else if (!amdgpu_check_pot_argument(amdgpu_sched_jobs)){
 942                 dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n",
 943                          amdgpu_sched_jobs);
 944                 amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs);
 945         }
 946
 947         if (amdgpu_gart_size != -1) {
 948                 /* gtt size must be greater or equal to 32M */
 949                 if (amdgpu_gart_size < 32) {
 950                         dev_warn(adev->dev, "gart size (%d) too small\n",
 951                                  amdgpu_gart_size);
 952                         amdgpu_gart_size = -1;
 953                 }
 954         }
 955
 956         if (!amdgpu_check_pot_argument(amdgpu_vm_size)) {
 957                 dev_warn(adev->dev, "VM size (%d) must be a power of 2\n",
 958                          amdgpu_vm_size);
 959                 amdgpu_vm_size = 8;
 960         }
 961
 962         if (amdgpu_vm_size < 1) {
 963                 dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
 964                          amdgpu_vm_size);
 965                 amdgpu_vm_size = 8;
 966         }
 967
 968         /*
 969          * Max GPUVM size for Cayman, SI and CI are 40 bits.
 970          */
 971         if (amdgpu_vm_size > 1024) {
 972                 dev_warn(adev->dev, "VM size (%d) too large, max is 1TB\n",
 973                          amdgpu_vm_size);
 974                 amdgpu_vm_size = 8;
 975         }
 976
 977         /* defines number of bits in page table versus page directory,
 978          * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
 979          * page table and the remaining bits are in the page directory */
 980         if (amdgpu_vm_block_size == -1) {
 981
 982                 /* Total bits covered by PD + PTs */
 983                 unsigned bits = ilog2(amdgpu_vm_size) + 18;
 984
 985                 /* Make sure the PD is 4K in size up to 8GB address space.
 986                    Above that split equal between PD and PTs */
 987                 if (amdgpu_vm_size <= 8)
 988                         amdgpu_vm_block_size = bits - 9;
 989                 else
 990                         amdgpu_vm_block_size = (bits + 3) / 2;
 991
 992         } else if (amdgpu_vm_block_size < 9) {
 993                 dev_warn(adev->dev, "VM page table size (%d) too small\n",
 994                          amdgpu_vm_block_size);
 995                 amdgpu_vm_block_size = 9;
 996         }
 997
 998         if (amdgpu_vm_block_size > 24 ||
 999             (amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) {
1000                 dev_warn(adev->dev, "VM page table size (%d) too large\n",
1001                          amdgpu_vm_block_size);
1002                 amdgpu_vm_block_size = 9;
1003         }
1004 }
1005
1006 /**
1007  * amdgpu_switcheroo_set_state - set switcheroo state
1008  *
1009  * @pdev: pci dev pointer
1010  * @state: vga_switcheroo state
1011  *
1012  * Callback for the switcheroo driver.  Suspends or resumes the
1013  * the asics before or after it is powered up using ACPI methods.
1014  */
1015 static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1016 {
1017         struct drm_device *dev = pci_get_drvdata(pdev);
1018
1019         if (amdgpu_device_is_px(dev) && state == VGA_SWITCHEROO_OFF)
1020                 return;
1021
1022         if (state == VGA_SWITCHEROO_ON) {
1023                 unsigned d3_delay = dev->pdev->d3_delay;
1024
1025                 printk(KERN_INFO "amdgpu: switched on\n");
1026                 /* don't suspend or resume card normally */
1027                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1028
1029                 amdgpu_resume_kms(dev, true, true);
1030
1031                 dev->pdev->d3_delay = d3_delay;
1032
1033                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1034                 drm_kms_helper_poll_enable(dev);
1035         } else {
1036                 printk(KERN_INFO "amdgpu: switched off\n");
1037                 drm_kms_helper_poll_disable(dev);
1038                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1039                 amdgpu_suspend_kms(dev, true, true);
1040                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1041         }
1042 }
1043
1044 /**
1045  * amdgpu_switcheroo_can_switch - see if switcheroo state can change
1046  *
1047  * @pdev: pci dev pointer
1048  *
1049  * Callback for the switcheroo driver.  Check of the switcheroo
1050  * state can be changed.
1051  * Returns true if the state can be changed, false if not.
1052  */
1053 static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev)
1054 {
1055         struct drm_device *dev = pci_get_drvdata(pdev);
1056
1057         /*
1058         * FIXME: open_count is protected by drm_global_mutex but that would lead to
1059         * locking inversion with the driver load path. And the access here is
1060         * completely racy anyway. So don't bother with locking for now.
1061         */
1062         return dev->open_count == 0;
1063 }
1064
1065 static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = {
1066         .set_gpu_state = amdgpu_switcheroo_set_state,
1067         .reprobe = NULL,
1068         .can_switch = amdgpu_switcheroo_can_switch,
1069 };
1070
1071 int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
1072                                   enum amd_ip_block_type block_type,
1073                                   enum amd_clockgating_state state)
1074 {
1075         int i, r = 0;
1076
1077         for (i = 0; i < adev->num_ip_blocks; i++) {
1078                 if (adev->ip_blocks[i].type == block_type) {
1079                         r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1080                                                                             state);
1081                         if (r)
1082                                 return r;
1083                         break;
1084                 }
1085         }
1086         return r;
1087 }
1088
1089 int amdgpu_set_powergating_state(struct amdgpu_device *adev,
1090                                   enum amd_ip_block_type block_type,
1091                                   enum amd_powergating_state state)
1092 {
1093         int i, r = 0;
1094
1095         for (i = 0; i < adev->num_ip_blocks; i++) {
1096                 if (adev->ip_blocks[i].type == block_type) {
1097                         r = adev->ip_blocks[i].funcs->set_powergating_state((void *)adev,
1098                                                                             state);
1099                         if (r)
1100                                 return r;
1101                         break;
1102                 }
1103         }
1104         return r;
1105 }
1106
1107 int amdgpu_wait_for_idle(struct amdgpu_device *adev,
1108                          enum amd_ip_block_type block_type)
1109 {
1110         int i, r;
1111
1112         for (i = 0; i < adev->num_ip_blocks; i++) {
1113                 if (adev->ip_blocks[i].type == block_type) {
1114                         r = adev->ip_blocks[i].funcs->wait_for_idle((void *)adev);
1115                         if (r)
1116                                 return r;
1117                         break;
1118                 }
1119         }
1120         return 0;
1121
1122 }
1123
1124 bool amdgpu_is_idle(struct amdgpu_device *adev,
1125                     enum amd_ip_block_type block_type)
1126 {
1127         int i;
1128
1129         for (i = 0; i < adev->num_ip_blocks; i++) {
1130                 if (adev->ip_blocks[i].type == block_type)
1131                         return adev->ip_blocks[i].funcs->is_idle((void *)adev);
1132         }
1133         return true;
1134
1135 }
1136
1137 const struct amdgpu_ip_block_version * amdgpu_get_ip_block(
1138                                         struct amdgpu_device *adev,
1139                                         enum amd_ip_block_type type)
1140 {
1141         int i;
1142
1143         for (i = 0; i < adev->num_ip_blocks; i++)
1144                 if (adev->ip_blocks[i].type == type)
1145                         return &adev->ip_blocks[i];
1146
1147         return NULL;
1148 }
1149
1150 /**
1151  * amdgpu_ip_block_version_cmp
1152  *
1153  * @adev: amdgpu_device pointer
1154  * @type: enum amd_ip_block_type
1155  * @major: major version
1156  * @minor: minor version
1157  *
1158  * return 0 if equal or greater
1159  * return 1 if smaller or the ip_block doesn't exist
1160  */
1161 int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
1162                                 enum amd_ip_block_type type,
1163                                 u32 major, u32 minor)
1164 {
1165         const struct amdgpu_ip_block_version *ip_block;
1166         ip_block = amdgpu_get_ip_block(adev, type);
1167
1168         if (ip_block && ((ip_block->major > major) ||
1169                         ((ip_block->major == major) &&
1170                         (ip_block->minor >= minor))))
1171                 return 0;
1172
1173         return 1;
1174 }
1175
1176 static int amdgpu_early_init(struct amdgpu_device *adev)
1177 {
1178         int i, r;
1179
1180         switch (adev->asic_type) {
1181         case CHIP_TOPAZ:
1182         case CHIP_TONGA:
1183         case CHIP_FIJI:
1184         case CHIP_POLARIS11:
1185         case CHIP_POLARIS10:
1186         case CHIP_CARRIZO:
1187         case CHIP_STONEY:
1188                 if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY)
1189                         adev->family = AMDGPU_FAMILY_CZ;
1190                 else
1191                         adev->family = AMDGPU_FAMILY_VI;
1192
1193                 r = vi_set_ip_blocks(adev);
1194                 if (r)
1195                         return r;
1196                 break;
1197 #ifdef CONFIG_DRM_AMDGPU_CIK
1198         case CHIP_BONAIRE:
1199         case CHIP_HAWAII:
1200         case CHIP_KAVERI:
1201         case CHIP_KABINI:
1202         case CHIP_MULLINS:
1203                 if ((adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII))
1204                         adev->family = AMDGPU_FAMILY_CI;
1205                 else
1206                         adev->family = AMDGPU_FAMILY_KV;
1207
1208                 r = cik_set_ip_blocks(adev);
1209                 if (r)
1210                         return r;
1211                 break;
1212 #endif
1213         default:
1214                 /* FIXME: not supported yet */
1215                 return -EINVAL;
1216         }
1217
1218         adev->ip_block_status = kcalloc(adev->num_ip_blocks,
1219                                         sizeof(struct amdgpu_ip_block_status), GFP_KERNEL);
1220         if (adev->ip_block_status == NULL)
1221                 return -ENOMEM;
1222
1223         if (adev->ip_blocks == NULL) {
1224                 DRM_ERROR("No IP blocks found!\n");
1225                 return r;
1226         }
1227
1228         for (i = 0; i < adev->num_ip_blocks; i++) {
1229                 if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
1230                         DRM_ERROR("disabled ip block: %d\n", i);
1231                         adev->ip_block_status[i].valid = false;
1232                 } else {
1233                         if (adev->ip_blocks[i].funcs->early_init) {
1234                                 r = adev->ip_blocks[i].funcs->early_init((void *)adev);
1235                                 if (r == -ENOENT) {
1236                                         adev->ip_block_status[i].valid = false;
1237                                 } else if (r) {
1238                                         DRM_ERROR("early_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1239                                         return r;
1240                                 } else {
1241                                         adev->ip_block_status[i].valid = true;
1242                                 }
1243                         } else {
1244                                 adev->ip_block_status[i].valid = true;
1245                         }
1246                 }
1247         }
1248
1249         adev->cg_flags &= amdgpu_cg_mask;
1250         adev->pg_flags &= amdgpu_pg_mask;
1251
1252         return 0;
1253 }
1254
1255 static int amdgpu_init(struct amdgpu_device *adev)
1256 {
1257         int i, r;
1258
1259         for (i = 0; i < adev->num_ip_blocks; i++) {
1260                 if (!adev->ip_block_status[i].valid)
1261                         continue;
1262                 r = adev->ip_blocks[i].funcs->sw_init((void *)adev);
1263                 if (r) {
1264                         DRM_ERROR("sw_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1265                         return r;
1266                 }
1267                 adev->ip_block_status[i].sw = true;
1268                 /* need to do gmc hw init early so we can allocate gpu mem */
1269                 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) {
1270                         r = amdgpu_vram_scratch_init(adev);
1271                         if (r) {
1272                                 DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r);
1273                                 return r;
1274                         }
1275                         r = adev->ip_blocks[i].funcs->hw_init((void *)adev);
1276                         if (r) {
1277                                 DRM_ERROR("hw_init %d failed %d\n", i, r);
1278                                 return r;
1279                         }
1280                         r = amdgpu_wb_init(adev);
1281                         if (r) {
1282                                 DRM_ERROR("amdgpu_wb_init failed %d\n", r);
1283                                 return r;
1284                         }
1285                         adev->ip_block_status[i].hw = true;
1286                 }
1287         }
1288
1289         for (i = 0; i < adev->num_ip_blocks; i++) {
1290                 if (!adev->ip_block_status[i].sw)
1291                         continue;
1292                 /* gmc hw init is done early */
1293                 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC)
1294                         continue;
1295                 r = adev->ip_blocks[i].funcs->hw_init((void *)adev);
1296                 if (r) {
1297                         DRM_ERROR("hw_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1298                         return r;
1299                 }
1300                 adev->ip_block_status[i].hw = true;
1301         }
1302
1303         return 0;
1304 }
1305
1306 static int amdgpu_late_init(struct amdgpu_device *adev)
1307 {
1308         int i = 0, r;
1309
1310         for (i = 0; i < adev->num_ip_blocks; i++) {
1311                 if (!adev->ip_block_status[i].valid)
1312                         continue;
1313                 /* enable clockgating to save power */
1314                 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1315                                                                     AMD_CG_STATE_GATE);
1316                 if (r) {
1317                         DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1318                         return r;
1319                 }
1320                 if (adev->ip_blocks[i].funcs->late_init) {
1321                         r = adev->ip_blocks[i].funcs->late_init((void *)adev);
1322                         if (r) {
1323                                 DRM_ERROR("late_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1324                                 return r;
1325                         }
1326                 }
1327         }
1328
1329         return 0;
1330 }
1331
1332 static int amdgpu_fini(struct amdgpu_device *adev)
1333 {
1334         int i, r;
1335
1336         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1337                 if (!adev->ip_block_status[i].hw)
1338                         continue;
1339                 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) {
1340                         amdgpu_wb_fini(adev);
1341                         amdgpu_vram_scratch_fini(adev);
1342                 }
1343                 /* ungate blocks before hw fini so that we can shutdown the blocks safely */
1344                 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1345                                                                     AMD_CG_STATE_UNGATE);
1346                 if (r) {
1347                         DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1348                         return r;
1349                 }
1350                 r = adev->ip_blocks[i].funcs->hw_fini((void *)adev);
1351                 /* XXX handle errors */
1352                 if (r) {
1353                         DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1354                 }
1355                 adev->ip_block_status[i].hw = false;
1356         }
1357
1358         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1359                 if (!adev->ip_block_status[i].sw)
1360                         continue;
1361                 r = adev->ip_blocks[i].funcs->sw_fini((void *)adev);
1362                 /* XXX handle errors */
1363                 if (r) {
1364                         DRM_DEBUG("sw_fini of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1365                 }
1366                 adev->ip_block_status[i].sw = false;
1367                 adev->ip_block_status[i].valid = false;
1368         }
1369
1370         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1371                 if (adev->ip_blocks[i].funcs->late_fini)
1372                         adev->ip_blocks[i].funcs->late_fini((void *)adev);
1373         }
1374
1375         return 0;
1376 }
1377
1378 static int amdgpu_suspend(struct amdgpu_device *adev)
1379 {
1380         int i, r;
1381
1382         /* ungate SMC block first */
1383         r = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_SMC,
1384                                          AMD_CG_STATE_UNGATE);
1385         if (r) {
1386                 DRM_ERROR("set_clockgating_state(ungate) SMC failed %d\n",r);
1387         }
1388
1389         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1390                 if (!adev->ip_block_status[i].valid)
1391                         continue;
1392                 /* ungate blocks so that suspend can properly shut them down */
1393                 if (i != AMD_IP_BLOCK_TYPE_SMC) {
1394                         r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1395                                                                             AMD_CG_STATE_UNGATE);
1396                         if (r) {
1397                                 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1398                         }
1399                 }
1400                 /* XXX handle errors */
1401                 r = adev->ip_blocks[i].funcs->suspend(adev);
1402                 /* XXX handle errors */
1403                 if (r) {
1404                         DRM_ERROR("suspend of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1405                 }
1406         }
1407
1408         return 0;
1409 }
1410
1411 static int amdgpu_resume(struct amdgpu_device *adev)
1412 {
1413         int i, r;
1414
1415         for (i = 0; i < adev->num_ip_blocks; i++) {
1416                 if (!adev->ip_block_status[i].valid)
1417                         continue;
1418                 r = adev->ip_blocks[i].funcs->resume(adev);
1419                 if (r) {
1420                         DRM_ERROR("resume of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1421                         return r;
1422                 }
1423         }
1424
1425         return 0;
1426 }
1427
1428 static bool amdgpu_device_is_virtual(void)
1429 {
1430 #ifdef CONFIG_X86
1431         return boot_cpu_has(X86_FEATURE_HYPERVISOR);
1432 #else
1433         return false;
1434 #endif
1435 }
1436
1437 /**
1438  * amdgpu_device_init - initialize the driver
1439  *
1440  * @adev: amdgpu_device pointer
1441  * @pdev: drm dev pointer
1442  * @pdev: pci dev pointer
1443  * @flags: driver flags
1444  *
1445  * Initializes the driver info and hw (all asics).
1446  * Returns 0 for success or an error on failure.
1447  * Called at driver startup.
1448  */
1449 int amdgpu_device_init(struct amdgpu_device *adev,
1450                        struct drm_device *ddev,
1451                        struct pci_dev *pdev,
1452                        uint32_t flags)
1453 {
1454         int r, i;
1455         bool runtime = false;
1456
1457         adev->shutdown = false;
1458         adev->dev = &pdev->dev;
1459         adev->ddev = ddev;
1460         adev->pdev = pdev;
1461         adev->flags = flags;
1462         adev->asic_type = flags & AMD_ASIC_MASK;
1463         adev->is_atom_bios = false;
1464         adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT;
1465         adev->mc.gtt_size = 512 * 1024 * 1024;
1466         adev->accel_working = false;
1467         adev->num_rings = 0;
1468         adev->mman.buffer_funcs = NULL;
1469         adev->mman.buffer_funcs_ring = NULL;
1470         adev->vm_manager.vm_pte_funcs = NULL;
1471         adev->vm_manager.vm_pte_num_rings = 0;
1472         adev->gart.gart_funcs = NULL;
1473         adev->fence_context = fence_context_alloc(AMDGPU_MAX_RINGS);
1474
1475         adev->smc_rreg = &amdgpu_invalid_rreg;
1476         adev->smc_wreg = &amdgpu_invalid_wreg;
1477         adev->pcie_rreg = &amdgpu_invalid_rreg;
1478         adev->pcie_wreg = &amdgpu_invalid_wreg;
1479         adev->uvd_ctx_rreg = &amdgpu_invalid_rreg;
1480         adev->uvd_ctx_wreg = &amdgpu_invalid_wreg;
1481         adev->didt_rreg = &amdgpu_invalid_rreg;
1482         adev->didt_wreg = &amdgpu_invalid_wreg;
1483         adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg;
1484         adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg;
1485
1486         DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
1487                  amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device,
1488                  pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
1489
1490         /* mutex initialization are all done here so we
1491          * can recall function without having locking issues */
1492         mutex_init(&adev->vm_manager.lock);
1493         atomic_set(&adev->irq.ih.lock, 0);
1494         mutex_init(&adev->pm.mutex);
1495         mutex_init(&adev->gfx.gpu_clock_mutex);
1496         mutex_init(&adev->srbm_mutex);
1497         mutex_init(&adev->grbm_idx_mutex);
1498         mutex_init(&adev->mn_lock);
1499         hash_init(adev->mn_hash);
1500
1501         amdgpu_check_arguments(adev);
1502
1503         /* Registers mapping */
1504         /* TODO: block userspace mapping of io register */
1505         spin_lock_init(&adev->mmio_idx_lock);
1506         spin_lock_init(&adev->smc_idx_lock);
1507         spin_lock_init(&adev->pcie_idx_lock);
1508         spin_lock_init(&adev->uvd_ctx_idx_lock);
1509         spin_lock_init(&adev->didt_idx_lock);
1510         spin_lock_init(&adev->audio_endpt_idx_lock);
1511
1512         adev->rmmio_base = pci_resource_start(adev->pdev, 5);
1513         adev->rmmio_size = pci_resource_len(adev->pdev, 5);
1514         adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);
1515         if (adev->rmmio == NULL) {
1516                 return -ENOMEM;
1517         }
1518         DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
1519         DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size);
1520
1521         /* doorbell bar mapping */
1522         amdgpu_doorbell_init(adev);
1523
1524         /* io port mapping */
1525         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1526                 if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) {
1527                         adev->rio_mem_size = pci_resource_len(adev->pdev, i);
1528                         adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size);
1529                         break;
1530                 }
1531         }
1532         if (adev->rio_mem == NULL)
1533                 DRM_ERROR("Unable to find PCI I/O BAR\n");
1534
1535         /* early init functions */
1536         r = amdgpu_early_init(adev);
1537         if (r)
1538                 return r;
1539
1540         /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
1541         /* this will fail for cards that aren't VGA class devices, just
1542          * ignore it */
1543         vga_client_register(adev->pdev, adev, NULL, amdgpu_vga_set_decode);
1544
1545         if (amdgpu_runtime_pm == 1)
1546                 runtime = true;
1547         if (amdgpu_device_is_px(ddev))
1548                 runtime = true;
1549         vga_switcheroo_register_client(adev->pdev, &amdgpu_switcheroo_ops, runtime);
1550         if (runtime)
1551                 vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain);
1552
1553         /* Read BIOS */
1554         if (!amdgpu_get_bios(adev)) {
1555                 r = -EINVAL;
1556                 goto failed;
1557         }
1558         /* Must be an ATOMBIOS */
1559         if (!adev->is_atom_bios) {
1560                 dev_err(adev->dev, "Expecting atombios for GPU\n");
1561                 r = -EINVAL;
1562                 goto failed;
1563         }
1564         r = amdgpu_atombios_init(adev);
1565         if (r) {
1566                 dev_err(adev->dev, "amdgpu_atombios_init failed\n");
1567                 goto failed;
1568         }
1569
1570         /* See if the asic supports SR-IOV */
1571         adev->virtualization.supports_sr_iov =
1572                 amdgpu_atombios_has_gpu_virtualization_table(adev);
1573
1574         /* Check if we are executing in a virtualized environment */
1575         adev->virtualization.is_virtual = amdgpu_device_is_virtual();
1576         adev->virtualization.caps = amdgpu_asic_get_virtual_caps(adev);
1577
1578         /* Post card if necessary */
1579         if (!amdgpu_card_posted(adev) ||
1580             (adev->virtualization.is_virtual &&
1581              !(adev->virtualization.caps & AMDGPU_VIRT_CAPS_SRIOV_EN))) {
1582                 if (!adev->bios) {
1583                         dev_err(adev->dev, "Card not posted and no BIOS - ignoring\n");
1584                         r = -EINVAL;
1585                         goto failed;
1586                 }
1587                 DRM_INFO("GPU not posted. posting now...\n");
1588                 amdgpu_atom_asic_init(adev->mode_info.atom_context);
1589         }
1590
1591         /* Initialize clocks */
1592         r = amdgpu_atombios_get_clock_info(adev);
1593         if (r) {
1594                 dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n");
1595                 goto failed;
1596         }
1597         /* init i2c buses */
1598         amdgpu_atombios_i2c_init(adev);
1599
1600         /* Fence driver */
1601         r = amdgpu_fence_driver_init(adev);
1602         if (r) {
1603                 dev_err(adev->dev, "amdgpu_fence_driver_init failed\n");
1604                 goto failed;
1605         }
1606
1607         /* init the mode config */
1608         drm_mode_config_init(adev->ddev);
1609
1610         r = amdgpu_init(adev);
1611         if (r) {
1612                 dev_err(adev->dev, "amdgpu_init failed\n");
1613                 amdgpu_fini(adev);
1614                 goto failed;
1615         }
1616
1617         adev->accel_working = true;
1618
1619         amdgpu_fbdev_init(adev);
1620
1621         r = amdgpu_ib_pool_init(adev);
1622         if (r) {
1623                 dev_err(adev->dev, "IB initialization failed (%d).\n", r);
1624                 goto failed;
1625         }
1626
1627         r = amdgpu_ib_ring_tests(adev);
1628         if (r)
1629                 DRM_ERROR("ib ring test failed (%d).\n", r);
1630
1631         r = amdgpu_gem_debugfs_init(adev);
1632         if (r) {
1633                 DRM_ERROR("registering gem debugfs failed (%d).\n", r);
1634         }
1635
1636         r = amdgpu_debugfs_regs_init(adev);
1637         if (r) {
1638                 DRM_ERROR("registering register debugfs failed (%d).\n", r);
1639         }
1640
1641         r = amdgpu_debugfs_firmware_init(adev);
1642         if (r) {
1643                 DRM_ERROR("registering firmware debugfs failed (%d).\n", r);
1644                 return r;
1645         }
1646
1647         if ((amdgpu_testing & 1)) {
1648                 if (adev->accel_working)
1649                         amdgpu_test_moves(adev);
1650                 else
1651                         DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n");
1652         }
1653         if ((amdgpu_testing & 2)) {
1654                 if (adev->accel_working)
1655                         amdgpu_test_syncing(adev);
1656                 else
1657                         DRM_INFO("amdgpu: acceleration disabled, skipping sync tests\n");
1658         }
1659         if (amdgpu_benchmarking) {
1660                 if (adev->accel_working)
1661                         amdgpu_benchmark(adev, amdgpu_benchmarking);
1662                 else
1663                         DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n");
1664         }
1665
1666         /* enable clockgating, etc. after ib tests, etc. since some blocks require
1667          * explicit gating rather than handling it automatically.
1668          */
1669         r = amdgpu_late_init(adev);
1670         if (r) {
1671                 dev_err(adev->dev, "amdgpu_late_init failed\n");
1672                 goto failed;
1673         }
1674
1675         return 0;
1676
1677 failed:
1678         if (runtime)
1679                 vga_switcheroo_fini_domain_pm_ops(adev->dev);
1680         return r;
1681 }
1682
1683 static void amdgpu_debugfs_remove_files(struct amdgpu_device *adev);
1684
1685 /**
1686  * amdgpu_device_fini - tear down the driver
1687  *
1688  * @adev: amdgpu_device pointer
1689  *
1690  * Tear down the driver info (all asics).
1691  * Called at driver shutdown.
1692  */
1693 void amdgpu_device_fini(struct amdgpu_device *adev)
1694 {
1695         int r;
1696
1697         DRM_INFO("amdgpu: finishing device.\n");
1698         adev->shutdown = true;
1699         /* evict vram memory */
1700         amdgpu_bo_evict_vram(adev);
1701         amdgpu_ib_pool_fini(adev);
1702         amdgpu_fence_driver_fini(adev);
1703         amdgpu_fbdev_fini(adev);
1704         r = amdgpu_fini(adev);
1705         kfree(adev->ip_block_status);
1706         adev->ip_block_status = NULL;
1707         adev->accel_working = false;
1708         /* free i2c buses */
1709         amdgpu_i2c_fini(adev);
1710         amdgpu_atombios_fini(adev);
1711         kfree(adev->bios);
1712         adev->bios = NULL;
1713         vga_switcheroo_unregister_client(adev->pdev);
1714         if (adev->flags & AMD_IS_PX)
1715                 vga_switcheroo_fini_domain_pm_ops(adev->dev);
1716         vga_client_register(adev->pdev, NULL, NULL, NULL);
1717         if (adev->rio_mem)
1718                 pci_iounmap(adev->pdev, adev->rio_mem);
1719         adev->rio_mem = NULL;
1720         iounmap(adev->rmmio);
1721         adev->rmmio = NULL;
1722         amdgpu_doorbell_fini(adev);
1723         amdgpu_debugfs_regs_cleanup(adev);
1724         amdgpu_debugfs_remove_files(adev);
1725 }
1726
1727
1728 /*
1729  * Suspend & resume.
1730  */
1731 /**
1732  * amdgpu_suspend_kms - initiate device suspend
1733  *
1734  * @pdev: drm dev pointer
1735  * @state: suspend state
1736  *
1737  * Puts the hw in the suspend state (all asics).
1738  * Returns 0 for success or an error on failure.
1739  * Called at driver suspend.
1740  */
1741 int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon)
1742 {
1743         struct amdgpu_device *adev;
1744         struct drm_crtc *crtc;
1745         struct drm_connector *connector;
1746         int r;
1747
1748         if (dev == NULL || dev->dev_private == NULL) {
1749                 return -ENODEV;
1750         }
1751
1752         adev = dev->dev_private;
1753
1754         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1755                 return 0;
1756
1757         drm_kms_helper_poll_disable(dev);
1758
1759         /* turn off display hw */
1760         drm_modeset_lock_all(dev);
1761         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1762                 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
1763         }
1764         drm_modeset_unlock_all(dev);
1765
1766         /* unpin the front buffers and cursors */
1767         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1768                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1769                 struct amdgpu_framebuffer *rfb = to_amdgpu_framebuffer(crtc->primary->fb);
1770                 struct amdgpu_bo *robj;
1771
1772                 if (amdgpu_crtc->cursor_bo) {
1773                         struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
1774                         r = amdgpu_bo_reserve(aobj, false);
1775                         if (r == 0) {
1776                                 amdgpu_bo_unpin(aobj);
1777                                 amdgpu_bo_unreserve(aobj);
1778                         }
1779                 }
1780
1781                 if (rfb == NULL || rfb->obj == NULL) {
1782                         continue;
1783                 }
1784                 robj = gem_to_amdgpu_bo(rfb->obj);
1785                 /* don't unpin kernel fb objects */
1786                 if (!amdgpu_fbdev_robj_is_fb(adev, robj)) {
1787                         r = amdgpu_bo_reserve(robj, false);
1788                         if (r == 0) {
1789                                 amdgpu_bo_unpin(robj);
1790                                 amdgpu_bo_unreserve(robj);
1791                         }
1792                 }
1793         }
1794         /* evict vram memory */
1795         amdgpu_bo_evict_vram(adev);
1796
1797         amdgpu_fence_driver_suspend(adev);
1798
1799         r = amdgpu_suspend(adev);
1800
1801         /* evict remaining vram memory */
1802         amdgpu_bo_evict_vram(adev);
1803
1804         pci_save_state(dev->pdev);
1805         if (suspend) {
1806                 /* Shut down the device */
1807                 pci_disable_device(dev->pdev);
1808                 pci_set_power_state(dev->pdev, PCI_D3hot);
1809         }
1810
1811         if (fbcon) {
1812                 console_lock();
1813                 amdgpu_fbdev_set_suspend(adev, 1);
1814                 console_unlock();
1815         }
1816         return 0;
1817 }
1818
1819 /**
1820  * amdgpu_resume_kms - initiate device resume
1821  *
1822  * @pdev: drm dev pointer
1823  *
1824  * Bring the hw back to operating state (all asics).
1825  * Returns 0 for success or an error on failure.
1826  * Called at driver resume.
1827  */
1828 int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon)
1829 {
1830         struct drm_connector *connector;
1831         struct amdgpu_device *adev = dev->dev_private;
1832         struct drm_crtc *crtc;
1833         int r;
1834
1835         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1836                 return 0;
1837
1838         if (fbcon) {
1839                 console_lock();
1840         }
1841         if (resume) {
1842                 pci_set_power_state(dev->pdev, PCI_D0);
1843                 pci_restore_state(dev->pdev);
1844                 if (pci_enable_device(dev->pdev)) {
1845                         if (fbcon)
1846                                 console_unlock();
1847                         return -1;
1848                 }
1849         }
1850
1851         /* post card */
1852         if (!amdgpu_card_posted(adev))
1853                 amdgpu_atom_asic_init(adev->mode_info.atom_context);
1854
1855         r = amdgpu_resume(adev);
1856         if (r)
1857                 DRM_ERROR("amdgpu_resume failed (%d).\n", r);
1858
1859         amdgpu_fence_driver_resume(adev);
1860
1861         if (resume) {
1862                 r = amdgpu_ib_ring_tests(adev);
1863                 if (r)
1864                         DRM_ERROR("ib ring test failed (%d).\n", r);
1865         }
1866
1867         r = amdgpu_late_init(adev);
1868         if (r)
1869                 return r;
1870
1871         /* pin cursors */
1872         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1873                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1874
1875                 if (amdgpu_crtc->cursor_bo) {
1876                         struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
1877                         r = amdgpu_bo_reserve(aobj, false);
1878                         if (r == 0) {
1879                                 r = amdgpu_bo_pin(aobj,
1880                                                   AMDGPU_GEM_DOMAIN_VRAM,
1881                                                   &amdgpu_crtc->cursor_addr);
1882                                 if (r != 0)
1883                                         DRM_ERROR("Failed to pin cursor BO (%d)\n", r);
1884                                 amdgpu_bo_unreserve(aobj);
1885                         }
1886                 }
1887         }
1888
1889         /* blat the mode back in */
1890         if (fbcon) {
1891                 drm_helper_resume_force_mode(dev);
1892                 /* turn on display hw */
1893                 drm_modeset_lock_all(dev);
1894                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1895                         drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
1896                 }
1897                 drm_modeset_unlock_all(dev);
1898         }
1899
1900         drm_kms_helper_poll_enable(dev);
1901         drm_helper_hpd_irq_event(dev);
1902
1903         if (fbcon) {
1904                 amdgpu_fbdev_set_suspend(adev, 0);
1905                 console_unlock();
1906         }
1907
1908         return 0;
1909 }
1910
1911 /**
1912  * amdgpu_gpu_reset - reset the asic
1913  *
1914  * @adev: amdgpu device pointer
1915  *
1916  * Attempt the reset the GPU if it has hung (all asics).
1917  * Returns 0 for success or an error on failure.
1918  */
1919 int amdgpu_gpu_reset(struct amdgpu_device *adev)
1920 {
1921         unsigned ring_sizes[AMDGPU_MAX_RINGS];
1922         uint32_t *ring_data[AMDGPU_MAX_RINGS];
1923
1924         bool saved = false;
1925
1926         int i, r;
1927         int resched;
1928
1929         atomic_inc(&adev->gpu_reset_counter);
1930
1931         /* evict vram memory */
1932         amdgpu_bo_evict_vram(adev);
1933
1934         /* block scheduler */
1935         for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
1936                 struct amdgpu_ring *ring = adev->rings[i];
1937
1938                 if (!ring)
1939                         continue;
1940                 kthread_park(ring->sched.thread);
1941         }
1942
1943         /* block TTM */
1944         resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev);
1945
1946         r = amdgpu_suspend(adev);
1947
1948         for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
1949                 struct amdgpu_ring *ring = adev->rings[i];
1950                 if (!ring)
1951                         continue;
1952
1953                 ring_sizes[i] = amdgpu_ring_backup(ring, &ring_data[i]);
1954                 if (ring_sizes[i]) {
1955                         saved = true;
1956                         dev_info(adev->dev, "Saved %d dwords of commands "
1957                                  "on ring %d.\n", ring_sizes[i], i);
1958                 }
1959         }
1960
1961 retry:
1962         r = amdgpu_asic_reset(adev);
1963         /* post card */
1964         amdgpu_atom_asic_init(adev->mode_info.atom_context);
1965
1966         if (!r) {
1967                 dev_info(adev->dev, "GPU reset succeeded, trying to resume\n");
1968                 r = amdgpu_resume(adev);
1969         }
1970
1971         if (!r) {
1972                 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
1973                         struct amdgpu_ring *ring = adev->rings[i];
1974                         if (!ring)
1975                                 continue;
1976                         kthread_unpark(ring->sched.thread);
1977                         amdgpu_ring_restore(ring, ring_sizes[i], ring_data[i]);
1978                         ring_sizes[i] = 0;
1979                         ring_data[i] = NULL;
1980                 }
1981
1982                 r = amdgpu_ib_ring_tests(adev);
1983                 if (r) {
1984                         dev_err(adev->dev, "ib ring test failed (%d).\n", r);
1985                         if (saved) {
1986                                 saved = false;
1987                                 r = amdgpu_suspend(adev);
1988                                 goto retry;
1989                         }
1990                 }
1991         } else {
1992                 amdgpu_fence_driver_force_completion(adev);
1993                 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
1994                         if (adev->rings[i]) {
1995                                 kthread_unpark(adev->rings[i]->sched.thread);
1996                                 kfree(ring_data[i]);
1997                         }
1998                 }
1999         }
2000
2001         drm_helper_resume_force_mode(adev->ddev);
2002
2003         ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched);
2004         if (r) {
2005                 /* bad news, how to tell it to userspace ? */
2006                 dev_info(adev->dev, "GPU reset failed\n");
2007         }
2008         amdgpu_irq_gpu_reset_resume_helper(adev);
2009
2010         return r;
2011 }
2012
2013 void amdgpu_get_pcie_info(struct amdgpu_device *adev)
2014 {
2015         u32 mask;
2016         int ret;
2017
2018         if (amdgpu_pcie_gen_cap)
2019                 adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
2020
2021         if (amdgpu_pcie_lane_cap)
2022                 adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap;
2023
2024         /* covers APUs as well */
2025         if (pci_is_root_bus(adev->pdev->bus)) {
2026                 if (adev->pm.pcie_gen_mask == 0)
2027                         adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
2028                 if (adev->pm.pcie_mlw_mask == 0)
2029                         adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
2030                 return;
2031         }
2032
2033         if (adev->pm.pcie_gen_mask == 0) {
2034                 ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
2035                 if (!ret) {
2036                         adev->pm.pcie_gen_mask = (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
2037                                                   CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
2038                                                   CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
2039
2040                         if (mask & DRM_PCIE_SPEED_25)
2041                                 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
2042                         if (mask & DRM_PCIE_SPEED_50)
2043                                 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2;
2044                         if (mask & DRM_PCIE_SPEED_80)
2045                                 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3;
2046                 } else {
2047                         adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
2048                 }
2049         }
2050         if (adev->pm.pcie_mlw_mask == 0) {
2051                 ret = drm_pcie_get_max_link_width(adev->ddev, &mask);
2052                 if (!ret) {
2053                         switch (mask) {
2054                         case 32:
2055                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
2056                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
2057                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
2058                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
2059                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2060                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2061                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2062                                 break;
2063                         case 16:
2064                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
2065                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
2066                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
2067                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2068                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2069                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2070                                 break;
2071                         case 12:
2072                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
2073                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
2074                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2075                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2076                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2077                                 break;
2078                         case 8:
2079                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
2080                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2081                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2082                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2083                                 break;
2084                         case 4:
2085                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2086                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2087                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2088                                 break;
2089                         case 2:
2090                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2091                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2092                                 break;
2093                         case 1:
2094                                 adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
2095                                 break;
2096                         default:
2097                                 break;
2098                         }
2099                 } else {
2100                         adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
2101                 }
2102         }
2103 }
2104
2105 /*
2106  * Debugfs
2107  */
2108 int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
2109                              const struct drm_info_list *files,
2110                              unsigned nfiles)
2111 {
2112         unsigned i;
2113
2114         for (i = 0; i < adev->debugfs_count; i++) {
2115                 if (adev->debugfs[i].files == files) {
2116                         /* Already registered */
2117                         return 0;
2118                 }
2119         }
2120
2121         i = adev->debugfs_count + 1;
2122         if (i > AMDGPU_DEBUGFS_MAX_COMPONENTS) {
2123                 DRM_ERROR("Reached maximum number of debugfs components.\n");
2124                 DRM_ERROR("Report so we increase "
2125                           "AMDGPU_DEBUGFS_MAX_COMPONENTS.\n");
2126                 return -EINVAL;
2127         }
2128         adev->debugfs[adev->debugfs_count].files = files;
2129         adev->debugfs[adev->debugfs_count].num_files = nfiles;
2130         adev->debugfs_count = i;
2131 #if defined(CONFIG_DEBUG_FS)
2132         drm_debugfs_create_files(files, nfiles,
2133                                  adev->ddev->control->debugfs_root,
2134                                  adev->ddev->control);
2135         drm_debugfs_create_files(files, nfiles,
2136                                  adev->ddev->primary->debugfs_root,
2137                                  adev->ddev->primary);
2138 #endif
2139         return 0;
2140 }
2141
2142 static void amdgpu_debugfs_remove_files(struct amdgpu_device *adev)
2143 {
2144 #if defined(CONFIG_DEBUG_FS)
2145         unsigned i;
2146
2147         for (i = 0; i < adev->debugfs_count; i++) {
2148                 drm_debugfs_remove_files(adev->debugfs[i].files,
2149                                          adev->debugfs[i].num_files,
2150                                          adev->ddev->control);
2151                 drm_debugfs_remove_files(adev->debugfs[i].files,
2152                                          adev->debugfs[i].num_files,
2153                                          adev->ddev->primary);
2154         }
2155 #endif
2156 }
2157
2158 #if defined(CONFIG_DEBUG_FS)
2159
2160 static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf,
2161                                         size_t size, loff_t *pos)
2162 {
2163         struct amdgpu_device *adev = f->f_inode->i_private;
2164         ssize_t result = 0;
2165         int r;
2166
2167         if (size & 0x3 || *pos & 0x3)
2168                 return -EINVAL;
2169
2170         while (size) {
2171                 uint32_t value;
2172
2173                 if (*pos > adev->rmmio_size)
2174                         return result;
2175
2176                 value = RREG32(*pos >> 2);
2177                 r = put_user(value, (uint32_t *)buf);
2178                 if (r)
2179                         return r;
2180
2181                 result += 4;
2182                 buf += 4;
2183                 *pos += 4;
2184                 size -= 4;
2185         }
2186
2187         return result;
2188 }
2189
2190 static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf,
2191                                          size_t size, loff_t *pos)
2192 {
2193         struct amdgpu_device *adev = f->f_inode->i_private;
2194         ssize_t result = 0;
2195         int r;
2196
2197         if (size & 0x3 || *pos & 0x3)
2198                 return -EINVAL;
2199
2200         while (size) {
2201                 uint32_t value;
2202
2203                 if (*pos > adev->rmmio_size)
2204                         return result;
2205
2206                 r = get_user(value, (uint32_t *)buf);
2207                 if (r)
2208                         return r;
2209
2210                 WREG32(*pos >> 2, value);
2211
2212                 result += 4;
2213                 buf += 4;
2214                 *pos += 4;
2215                 size -= 4;
2216         }
2217
2218         return result;
2219 }
2220
2221 static ssize_t amdgpu_debugfs_regs_pcie_read(struct file *f, char __user *buf,
2222                                         size_t size, loff_t *pos)
2223 {
2224         struct amdgpu_device *adev = f->f_inode->i_private;
2225         ssize_t result = 0;
2226         int r;
2227
2228         if (size & 0x3 || *pos & 0x3)
2229                 return -EINVAL;
2230
2231         while (size) {
2232                 uint32_t value;
2233
2234                 value = RREG32_PCIE(*pos >> 2);
2235                 r = put_user(value, (uint32_t *)buf);
2236                 if (r)
2237                         return r;
2238
2239                 result += 4;
2240                 buf += 4;
2241                 *pos += 4;
2242                 size -= 4;
2243         }
2244
2245         return result;
2246 }
2247
2248 static ssize_t amdgpu_debugfs_regs_pcie_write(struct file *f, const char __user *buf,
2249                                          size_t size, loff_t *pos)
2250 {
2251         struct amdgpu_device *adev = f->f_inode->i_private;
2252         ssize_t result = 0;
2253         int r;
2254
2255         if (size & 0x3 || *pos & 0x3)
2256                 return -EINVAL;
2257
2258         while (size) {
2259                 uint32_t value;
2260
2261                 r = get_user(value, (uint32_t *)buf);
2262                 if (r)
2263                         return r;
2264
2265                 WREG32_PCIE(*pos >> 2, value);
2266
2267                 result += 4;
2268                 buf += 4;
2269                 *pos += 4;
2270                 size -= 4;
2271         }
2272
2273         return result;
2274 }
2275
2276 static ssize_t amdgpu_debugfs_regs_didt_read(struct file *f, char __user *buf,
2277                                         size_t size, loff_t *pos)
2278 {
2279         struct amdgpu_device *adev = f->f_inode->i_private;
2280         ssize_t result = 0;
2281         int r;
2282
2283         if (size & 0x3 || *pos & 0x3)
2284                 return -EINVAL;
2285
2286         while (size) {
2287                 uint32_t value;
2288
2289                 value = RREG32_DIDT(*pos >> 2);
2290                 r = put_user(value, (uint32_t *)buf);
2291                 if (r)
2292                         return r;
2293
2294                 result += 4;
2295                 buf += 4;
2296                 *pos += 4;
2297                 size -= 4;
2298         }
2299
2300         return result;
2301 }
2302
2303 static ssize_t amdgpu_debugfs_regs_didt_write(struct file *f, const char __user *buf,
2304                                          size_t size, loff_t *pos)
2305 {
2306         struct amdgpu_device *adev = f->f_inode->i_private;
2307         ssize_t result = 0;
2308         int r;
2309
2310         if (size & 0x3 || *pos & 0x3)
2311                 return -EINVAL;
2312
2313         while (size) {
2314                 uint32_t value;
2315
2316                 r = get_user(value, (uint32_t *)buf);
2317                 if (r)
2318                         return r;
2319
2320                 WREG32_DIDT(*pos >> 2, value);
2321
2322                 result += 4;
2323                 buf += 4;
2324                 *pos += 4;
2325                 size -= 4;
2326         }
2327
2328         return result;
2329 }
2330
2331 static ssize_t amdgpu_debugfs_regs_smc_read(struct file *f, char __user *buf,
2332                                         size_t size, loff_t *pos)
2333 {
2334         struct amdgpu_device *adev = f->f_inode->i_private;
2335         ssize_t result = 0;
2336         int r;
2337
2338         if (size & 0x3 || *pos & 0x3)
2339                 return -EINVAL;
2340
2341         while (size) {
2342                 uint32_t value;
2343
2344                 value = RREG32_SMC(*pos >> 2);
2345                 r = put_user(value, (uint32_t *)buf);
2346                 if (r)
2347                         return r;
2348
2349                 result += 4;
2350                 buf += 4;
2351                 *pos += 4;
2352                 size -= 4;
2353         }
2354
2355         return result;
2356 }
2357
2358 static ssize_t amdgpu_debugfs_regs_smc_write(struct file *f, const char __user *buf,
2359                                          size_t size, loff_t *pos)
2360 {
2361         struct amdgpu_device *adev = f->f_inode->i_private;
2362         ssize_t result = 0;
2363         int r;
2364
2365         if (size & 0x3 || *pos & 0x3)
2366                 return -EINVAL;
2367
2368         while (size) {
2369                 uint32_t value;
2370
2371                 r = get_user(value, (uint32_t *)buf);
2372                 if (r)
2373                         return r;
2374
2375                 WREG32_SMC(*pos >> 2, value);
2376
2377                 result += 4;
2378                 buf += 4;
2379                 *pos += 4;
2380                 size -= 4;
2381         }
2382
2383         return result;
2384 }
2385
2386 static const struct file_operations amdgpu_debugfs_regs_fops = {
2387         .owner = THIS_MODULE,
2388         .read = amdgpu_debugfs_regs_read,
2389         .write = amdgpu_debugfs_regs_write,
2390         .llseek = default_llseek
2391 };
2392 static const struct file_operations amdgpu_debugfs_regs_didt_fops = {
2393         .owner = THIS_MODULE,
2394         .read = amdgpu_debugfs_regs_didt_read,
2395         .write = amdgpu_debugfs_regs_didt_write,
2396         .llseek = default_llseek
2397 };
2398 static const struct file_operations amdgpu_debugfs_regs_pcie_fops = {
2399         .owner = THIS_MODULE,
2400         .read = amdgpu_debugfs_regs_pcie_read,
2401         .write = amdgpu_debugfs_regs_pcie_write,
2402         .llseek = default_llseek
2403 };
2404 static const struct file_operations amdgpu_debugfs_regs_smc_fops = {
2405         .owner = THIS_MODULE,
2406         .read = amdgpu_debugfs_regs_smc_read,
2407         .write = amdgpu_debugfs_regs_smc_write,
2408         .llseek = default_llseek
2409 };
2410
2411 static const struct file_operations *debugfs_regs[] = {
2412         &amdgpu_debugfs_regs_fops,
2413         &amdgpu_debugfs_regs_didt_fops,
2414         &amdgpu_debugfs_regs_pcie_fops,
2415         &amdgpu_debugfs_regs_smc_fops,
2416 };
2417
2418 static const char *debugfs_regs_names[] = {
2419         "amdgpu_regs",
2420         "amdgpu_regs_didt",
2421         "amdgpu_regs_pcie",
2422         "amdgpu_regs_smc",
2423 };
2424
2425 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
2426 {
2427         struct drm_minor *minor = adev->ddev->primary;
2428         struct dentry *ent, *root = minor->debugfs_root;
2429         unsigned i, j;
2430
2431         for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {
2432                 ent = debugfs_create_file(debugfs_regs_names[i],
2433                                           S_IFREG | S_IRUGO, root,
2434                                           adev, debugfs_regs[i]);
2435                 if (IS_ERR(ent)) {
2436                         for (j = 0; j < i; j++) {
2437                                 debugfs_remove(adev->debugfs_regs[i]);
2438                                 adev->debugfs_regs[i] = NULL;
2439                         }
2440                         return PTR_ERR(ent);
2441                 }
2442
2443                 if (!i)
2444                         i_size_write(ent->d_inode, adev->rmmio_size);
2445                 adev->debugfs_regs[i] = ent;
2446         }
2447
2448         return 0;
2449 }
2450
2451 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev)
2452 {
2453         unsigned i;
2454
2455         for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {
2456                 if (adev->debugfs_regs[i]) {
2457                         debugfs_remove(adev->debugfs_regs[i]);
2458                         adev->debugfs_regs[i] = NULL;
2459                 }
2460         }
2461 }
2462
2463 int amdgpu_debugfs_init(struct drm_minor *minor)
2464 {
2465         return 0;
2466 }
2467
2468 void amdgpu_debugfs_cleanup(struct drm_minor *minor)
2469 {
2470 }
2471 #else
2472 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
2473 {
2474         return 0;
2475 }
2476 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) { }
2477 #endif