2 * Copyright 2016 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/firmware.h>
24 #include <linux/slab.h>
25 #include <linux/module.h>
28 #include "amdgpu_atombios.h"
29 #include "amdgpu_ih.h"
30 #include "amdgpu_uvd.h"
31 #include "amdgpu_vce.h"
32 #include "amdgpu_ucode.h"
33 #include "amdgpu_psp.h"
37 #include "vega10/soc15ip.h"
38 #include "vega10/UVD/uvd_7_0_offset.h"
39 #include "vega10/GC/gc_9_0_offset.h"
40 #include "vega10/GC/gc_9_0_sh_mask.h"
41 #include "vega10/SDMA0/sdma0_4_0_offset.h"
42 #include "vega10/SDMA1/sdma1_4_0_offset.h"
43 #include "vega10/HDP/hdp_4_0_offset.h"
44 #include "vega10/HDP/hdp_4_0_sh_mask.h"
45 #include "vega10/MP/mp_9_0_offset.h"
46 #include "vega10/MP/mp_9_0_sh_mask.h"
47 #include "vega10/SMUIO/smuio_9_0_offset.h"
48 #include "vega10/SMUIO/smuio_9_0_sh_mask.h"
51 #include "soc15_common.h"
54 #include "gfxhub_v1_0.h"
55 #include "mmhub_v1_0.h"
56 #include "vega10_ih.h"
57 #include "sdma_v4_0.h"
60 #include "amdgpu_powerplay.h"
61 #include "dce_virtual.h"
64 MODULE_FIRMWARE("amdgpu/vega10_smc.bin");
66 #define mmFabricConfigAccessControl 0x0410
67 #define mmFabricConfigAccessControl_BASE_IDX 0
68 #define mmFabricConfigAccessControl_DEFAULT 0x00000000
69 //FabricConfigAccessControl
70 #define FabricConfigAccessControl__CfgRegInstAccEn__SHIFT 0x0
71 #define FabricConfigAccessControl__CfgRegInstAccRegLock__SHIFT 0x1
72 #define FabricConfigAccessControl__CfgRegInstID__SHIFT 0x10
73 #define FabricConfigAccessControl__CfgRegInstAccEn_MASK 0x00000001L
74 #define FabricConfigAccessControl__CfgRegInstAccRegLock_MASK 0x00000002L
75 #define FabricConfigAccessControl__CfgRegInstID_MASK 0x00FF0000L
78 #define mmDF_PIE_AON0_DfGlobalClkGater 0x00fc
79 #define mmDF_PIE_AON0_DfGlobalClkGater_BASE_IDX 0
80 //DF_PIE_AON0_DfGlobalClkGater
81 #define DF_PIE_AON0_DfGlobalClkGater__MGCGMode__SHIFT 0x0
82 #define DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK 0x0000000FL
86 DF_MGCG_ENABLE_00_CYCLE_DELAY =1,
87 DF_MGCG_ENABLE_01_CYCLE_DELAY =2,
88 DF_MGCG_ENABLE_15_CYCLE_DELAY =13,
89 DF_MGCG_ENABLE_31_CYCLE_DELAY =14,
90 DF_MGCG_ENABLE_63_CYCLE_DELAY =15
93 #define mmMP0_MISC_CGTT_CTRL0 0x01b9
94 #define mmMP0_MISC_CGTT_CTRL0_BASE_IDX 0
95 #define mmMP0_MISC_LIGHT_SLEEP_CTRL 0x01ba
96 #define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX 0
99 * Indirect registers accessor
101 static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg)
103 unsigned long flags, address, data;
105 struct nbio_pcie_index_data *nbio_pcie_id;
107 if (adev->asic_type == CHIP_VEGA10)
108 nbio_pcie_id = &nbio_v6_1_pcie_index_data;
112 address = nbio_pcie_id->index_offset;
113 data = nbio_pcie_id->data_offset;
115 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
116 WREG32(address, reg);
117 (void)RREG32(address);
119 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
123 static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
125 unsigned long flags, address, data;
126 struct nbio_pcie_index_data *nbio_pcie_id;
128 if (adev->asic_type == CHIP_VEGA10)
129 nbio_pcie_id = &nbio_v6_1_pcie_index_data;
133 address = nbio_pcie_id->index_offset;
134 data = nbio_pcie_id->data_offset;
136 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
137 WREG32(address, reg);
138 (void)RREG32(address);
141 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
144 static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
146 unsigned long flags, address, data;
149 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
150 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
152 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
153 WREG32(address, ((reg) & 0x1ff));
155 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
159 static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
161 unsigned long flags, address, data;
163 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
164 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
166 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
167 WREG32(address, ((reg) & 0x1ff));
169 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
172 static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg)
174 unsigned long flags, address, data;
177 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
178 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
180 spin_lock_irqsave(&adev->didt_idx_lock, flags);
181 WREG32(address, (reg));
183 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
187 static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
189 unsigned long flags, address, data;
191 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
192 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
194 spin_lock_irqsave(&adev->didt_idx_lock, flags);
195 WREG32(address, (reg));
197 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
200 static u32 soc15_get_config_memsize(struct amdgpu_device *adev)
202 return nbio_v6_1_get_memsize(adev);
205 static const u32 vega10_golden_init[] =
209 static void soc15_init_golden_registers(struct amdgpu_device *adev)
211 /* Some of the registers might be dependent on GRBM_GFX_INDEX */
212 mutex_lock(&adev->grbm_idx_mutex);
214 switch (adev->asic_type) {
216 amdgpu_program_register_sequence(adev,
218 (const u32)ARRAY_SIZE(vega10_golden_init));
223 mutex_unlock(&adev->grbm_idx_mutex);
225 static u32 soc15_get_xclk(struct amdgpu_device *adev)
227 if (adev->asic_type == CHIP_VEGA10)
228 return adev->clock.spll.reference_freq/4;
230 return adev->clock.spll.reference_freq;
234 void soc15_grbm_select(struct amdgpu_device *adev,
235 u32 me, u32 pipe, u32 queue, u32 vmid)
237 u32 grbm_gfx_cntl = 0;
238 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
239 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
240 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
241 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
243 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl);
246 static void soc15_vga_set_state(struct amdgpu_device *adev, bool state)
251 static bool soc15_read_disabled_bios(struct amdgpu_device *adev)
257 static bool soc15_read_bios_from_rom(struct amdgpu_device *adev,
258 u8 *bios, u32 length_bytes)
265 if (length_bytes == 0)
267 /* APU vbios image is part of sbios image */
268 if (adev->flags & AMD_IS_APU)
271 dw_ptr = (u32 *)bios;
272 length_dw = ALIGN(length_bytes, 4) / 4;
274 /* set rom index to 0 */
275 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0);
276 /* read out the rom data */
277 for (i = 0; i < length_dw; i++)
278 dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA));
283 static struct amdgpu_allowed_register_entry vega10_allowed_read_registers[] = {
287 static struct amdgpu_allowed_register_entry soc15_allowed_read_registers[] = {
288 { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS), false},
289 { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS2), false},
290 { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE0), false},
291 { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE1), false},
292 { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE2), false},
293 { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE3), false},
294 { SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_STATUS_REG), false},
295 { SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_STATUS_REG), false},
296 { SOC15_REG_OFFSET(GC, 0, mmCP_STAT), false},
297 { SOC15_REG_OFFSET(GC, 0, mmCP_STALLED_STAT1), false},
298 { SOC15_REG_OFFSET(GC, 0, mmCP_STALLED_STAT2), false},
299 { SOC15_REG_OFFSET(GC, 0, mmCP_STALLED_STAT3), false},
300 { SOC15_REG_OFFSET(GC, 0, mmCP_CPF_BUSY_STAT), false},
301 { SOC15_REG_OFFSET(GC, 0, mmCP_CPF_STALLED_STAT1), false},
302 { SOC15_REG_OFFSET(GC, 0, mmCP_CPF_STATUS), false},
303 { SOC15_REG_OFFSET(GC, 0, mmCP_CPC_STALLED_STAT1), false},
304 { SOC15_REG_OFFSET(GC, 0, mmCP_CPC_STATUS), false},
305 { SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG), false},
308 static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
309 u32 sh_num, u32 reg_offset)
313 mutex_lock(&adev->grbm_idx_mutex);
314 if (se_num != 0xffffffff || sh_num != 0xffffffff)
315 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
317 val = RREG32(reg_offset);
319 if (se_num != 0xffffffff || sh_num != 0xffffffff)
320 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
321 mutex_unlock(&adev->grbm_idx_mutex);
325 static uint32_t soc15_get_register_value(struct amdgpu_device *adev,
326 bool indexed, u32 se_num,
327 u32 sh_num, u32 reg_offset)
330 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset);
332 switch (reg_offset) {
333 case SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG):
334 return adev->gfx.config.gb_addr_config;
336 return RREG32(reg_offset);
341 static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
342 u32 sh_num, u32 reg_offset, u32 *value)
344 struct amdgpu_allowed_register_entry *asic_register_table = NULL;
345 struct amdgpu_allowed_register_entry *asic_register_entry;
349 switch (adev->asic_type) {
351 asic_register_table = vega10_allowed_read_registers;
352 size = ARRAY_SIZE(vega10_allowed_read_registers);
358 if (asic_register_table) {
359 for (i = 0; i < size; i++) {
360 asic_register_entry = asic_register_table + i;
361 if (reg_offset != asic_register_entry->reg_offset)
363 if (!asic_register_entry->untouched)
364 *value = soc15_get_register_value(adev,
365 asic_register_entry->grbm_indexed,
366 se_num, sh_num, reg_offset);
371 for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) {
372 if (reg_offset != soc15_allowed_read_registers[i].reg_offset)
375 if (!soc15_allowed_read_registers[i].untouched)
376 *value = soc15_get_register_value(adev,
377 soc15_allowed_read_registers[i].grbm_indexed,
378 se_num, sh_num, reg_offset);
384 static void soc15_gpu_pci_config_reset(struct amdgpu_device *adev)
388 dev_info(adev->dev, "GPU pci config reset\n");
391 pci_clear_master(adev->pdev);
393 amdgpu_pci_config_reset(adev);
397 /* wait for asic to come out of reset */
398 for (i = 0; i < adev->usec_timeout; i++) {
399 if (nbio_v6_1_get_memsize(adev) != 0xffffffff)
406 static int soc15_asic_reset(struct amdgpu_device *adev)
408 amdgpu_atombios_scratch_regs_engine_hung(adev, true);
410 soc15_gpu_pci_config_reset(adev);
412 amdgpu_atombios_scratch_regs_engine_hung(adev, false);
417 /*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
418 u32 cntl_reg, u32 status_reg)
423 static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
427 r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
431 r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
436 static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
443 static void soc15_pcie_gen3_enable(struct amdgpu_device *adev)
445 if (pci_is_root_bus(adev->pdev->bus))
448 if (amdgpu_pcie_gen2 == 0)
451 if (adev->flags & AMD_IS_APU)
454 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
455 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
461 static void soc15_program_aspm(struct amdgpu_device *adev)
464 if (amdgpu_aspm == 0)
470 static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev,
473 nbio_v6_1_enable_doorbell_aperture(adev, enable);
474 nbio_v6_1_enable_doorbell_selfring_aperture(adev, enable);
477 static const struct amdgpu_ip_block_version vega10_common_ip_block =
479 .type = AMD_IP_BLOCK_TYPE_COMMON,
483 .funcs = &soc15_common_ip_funcs,
486 int soc15_set_ip_blocks(struct amdgpu_device *adev)
488 nbio_v6_1_detect_hw_virt(adev);
490 if (amdgpu_sriov_vf(adev))
491 adev->virt.ops = &xgpu_ai_virt_ops;
493 switch (adev->asic_type) {
495 amdgpu_ip_block_add(adev, &vega10_common_ip_block);
496 amdgpu_ip_block_add(adev, &gfxhub_v1_0_ip_block);
497 amdgpu_ip_block_add(adev, &mmhub_v1_0_ip_block);
498 amdgpu_ip_block_add(adev, &gmc_v9_0_ip_block);
499 amdgpu_ip_block_add(adev, &vega10_ih_ip_block);
500 if (amdgpu_fw_load_type == 2 || amdgpu_fw_load_type == -1)
501 amdgpu_ip_block_add(adev, &psp_v3_1_ip_block);
502 if (!amdgpu_sriov_vf(adev))
503 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
504 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
505 amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
506 amdgpu_ip_block_add(adev, &gfx_v9_0_ip_block);
507 amdgpu_ip_block_add(adev, &sdma_v4_0_ip_block);
508 if (!amdgpu_sriov_vf(adev))
509 amdgpu_ip_block_add(adev, &uvd_v7_0_ip_block);
510 amdgpu_ip_block_add(adev, &vce_v4_0_ip_block);
519 static uint32_t soc15_get_rev_id(struct amdgpu_device *adev)
521 return nbio_v6_1_get_rev_id(adev);
525 int gmc_v9_0_mc_wait_for_idle(struct amdgpu_device *adev)
527 /* to be implemented in MC IP*/
531 static const struct amdgpu_asic_funcs soc15_asic_funcs =
533 .read_disabled_bios = &soc15_read_disabled_bios,
534 .read_bios_from_rom = &soc15_read_bios_from_rom,
535 .read_register = &soc15_read_register,
536 .reset = &soc15_asic_reset,
537 .set_vga_state = &soc15_vga_set_state,
538 .get_xclk = &soc15_get_xclk,
539 .set_uvd_clocks = &soc15_set_uvd_clocks,
540 .set_vce_clocks = &soc15_set_vce_clocks,
541 .get_config_memsize = &soc15_get_config_memsize,
544 static int soc15_common_early_init(void *handle)
546 bool psp_enabled = false;
547 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
549 adev->smc_rreg = NULL;
550 adev->smc_wreg = NULL;
551 adev->pcie_rreg = &soc15_pcie_rreg;
552 adev->pcie_wreg = &soc15_pcie_wreg;
553 adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg;
554 adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg;
555 adev->didt_rreg = &soc15_didt_rreg;
556 adev->didt_wreg = &soc15_didt_wreg;
558 adev->asic_funcs = &soc15_asic_funcs;
560 if (amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP) &&
561 (amdgpu_ip_block_mask & (1 << AMD_IP_BLOCK_TYPE_PSP)))
564 if (amdgpu_sriov_vf(adev)) {
565 amdgpu_virt_init_setting(adev);
566 xgpu_ai_mailbox_set_irq_funcs(adev);
570 * nbio need be used for both sdma and gfx9, but only
573 switch(adev->asic_type) {
575 nbio_v6_1_init(adev);
581 adev->rev_id = soc15_get_rev_id(adev);
582 adev->external_rev_id = 0xFF;
583 switch (adev->asic_type) {
585 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
586 AMD_CG_SUPPORT_GFX_MGLS |
587 AMD_CG_SUPPORT_GFX_RLC_LS |
588 AMD_CG_SUPPORT_GFX_CP_LS |
589 AMD_CG_SUPPORT_GFX_3D_CGCG |
590 AMD_CG_SUPPORT_GFX_3D_CGLS |
591 AMD_CG_SUPPORT_GFX_CGCG |
592 AMD_CG_SUPPORT_GFX_CGLS |
593 AMD_CG_SUPPORT_BIF_MGCG |
594 AMD_CG_SUPPORT_BIF_LS |
595 AMD_CG_SUPPORT_HDP_LS |
596 AMD_CG_SUPPORT_DRM_MGCG |
597 AMD_CG_SUPPORT_DRM_LS |
598 AMD_CG_SUPPORT_ROM_MGCG |
599 AMD_CG_SUPPORT_DF_MGCG |
600 AMD_CG_SUPPORT_SDMA_MGCG |
601 AMD_CG_SUPPORT_SDMA_LS |
602 AMD_CG_SUPPORT_MC_MGCG |
603 AMD_CG_SUPPORT_MC_LS;
605 adev->external_rev_id = 0x1;
608 /* FIXME: not supported yet */
612 adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type);
614 amdgpu_get_pcie_info(adev);
619 static int soc15_common_late_init(void *handle)
621 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
623 if (amdgpu_sriov_vf(adev))
624 xgpu_ai_mailbox_get_irq(adev);
629 static int soc15_common_sw_init(void *handle)
631 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
633 if (amdgpu_sriov_vf(adev))
634 xgpu_ai_mailbox_add_irq_id(adev);
639 static int soc15_common_sw_fini(void *handle)
644 static int soc15_common_hw_init(void *handle)
646 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
648 /* move the golden regs per IP block */
649 soc15_init_golden_registers(adev);
650 /* enable pcie gen2/3 link */
651 soc15_pcie_gen3_enable(adev);
653 soc15_program_aspm(adev);
654 /* enable the doorbell aperture */
655 soc15_enable_doorbell_aperture(adev, true);
660 static int soc15_common_hw_fini(void *handle)
662 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
664 /* disable the doorbell aperture */
665 soc15_enable_doorbell_aperture(adev, false);
666 if (amdgpu_sriov_vf(adev))
667 xgpu_ai_mailbox_put_irq(adev);
672 static int soc15_common_suspend(void *handle)
674 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
676 return soc15_common_hw_fini(adev);
679 static int soc15_common_resume(void *handle)
681 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
683 return soc15_common_hw_init(adev);
686 static bool soc15_common_is_idle(void *handle)
691 static int soc15_common_wait_for_idle(void *handle)
696 static int soc15_common_soft_reset(void *handle)
701 static void soc15_update_hdp_light_sleep(struct amdgpu_device *adev, bool enable)
705 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
707 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
708 data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
710 data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
713 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data);
716 static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable)
720 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
722 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG))
723 data &= ~(0x01000000 |
732 data |= (0x01000000 |
742 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data);
745 static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable)
749 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
751 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS))
757 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data);
760 static void soc15_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev,
765 def = data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
767 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG))
768 data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
769 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK);
771 data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
772 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK;
775 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0), data);
778 static void soc15_update_df_medium_grain_clock_gating(struct amdgpu_device *adev,
783 /* Put DF on broadcast mode */
784 data = RREG32(SOC15_REG_OFFSET(DF, 0, mmFabricConfigAccessControl));
785 data &= ~FabricConfigAccessControl__CfgRegInstAccEn_MASK;
786 WREG32(SOC15_REG_OFFSET(DF, 0, mmFabricConfigAccessControl), data);
788 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DF_MGCG)) {
789 data = RREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater));
790 data &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
791 data |= DF_MGCG_ENABLE_15_CYCLE_DELAY;
792 WREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater), data);
794 data = RREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater));
795 data &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
796 data |= DF_MGCG_DISABLE;
797 WREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater), data);
800 WREG32(SOC15_REG_OFFSET(DF, 0, mmFabricConfigAccessControl),
801 mmFabricConfigAccessControl_DEFAULT);
804 static int soc15_common_set_clockgating_state(void *handle,
805 enum amd_clockgating_state state)
807 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
809 if (amdgpu_sriov_vf(adev))
812 switch (adev->asic_type) {
814 nbio_v6_1_update_medium_grain_clock_gating(adev,
815 state == AMD_CG_STATE_GATE ? true : false);
816 nbio_v6_1_update_medium_grain_light_sleep(adev,
817 state == AMD_CG_STATE_GATE ? true : false);
818 soc15_update_hdp_light_sleep(adev,
819 state == AMD_CG_STATE_GATE ? true : false);
820 soc15_update_drm_clock_gating(adev,
821 state == AMD_CG_STATE_GATE ? true : false);
822 soc15_update_drm_light_sleep(adev,
823 state == AMD_CG_STATE_GATE ? true : false);
824 soc15_update_rom_medium_grain_clock_gating(adev,
825 state == AMD_CG_STATE_GATE ? true : false);
826 soc15_update_df_medium_grain_clock_gating(adev,
827 state == AMD_CG_STATE_GATE ? true : false);
835 static void soc15_common_get_clockgating_state(void *handle, u32 *flags)
837 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
840 if (amdgpu_sriov_vf(adev))
843 nbio_v6_1_get_clockgating_state(adev, flags);
845 /* AMD_CG_SUPPORT_HDP_LS */
846 data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
847 if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK)
848 *flags |= AMD_CG_SUPPORT_HDP_LS;
850 /* AMD_CG_SUPPORT_DRM_MGCG */
851 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
852 if (!(data & 0x01000000))
853 *flags |= AMD_CG_SUPPORT_DRM_MGCG;
855 /* AMD_CG_SUPPORT_DRM_LS */
856 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
858 *flags |= AMD_CG_SUPPORT_DRM_LS;
860 /* AMD_CG_SUPPORT_ROM_MGCG */
861 data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
862 if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK))
863 *flags |= AMD_CG_SUPPORT_ROM_MGCG;
865 /* AMD_CG_SUPPORT_DF_MGCG */
866 data = RREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater));
867 if (data & DF_MGCG_ENABLE_15_CYCLE_DELAY)
868 *flags |= AMD_CG_SUPPORT_DF_MGCG;
871 static int soc15_common_set_powergating_state(void *handle,
872 enum amd_powergating_state state)
878 const struct amd_ip_funcs soc15_common_ip_funcs = {
879 .name = "soc15_common",
880 .early_init = soc15_common_early_init,
881 .late_init = soc15_common_late_init,
882 .sw_init = soc15_common_sw_init,
883 .sw_fini = soc15_common_sw_fini,
884 .hw_init = soc15_common_hw_init,
885 .hw_fini = soc15_common_hw_fini,
886 .suspend = soc15_common_suspend,
887 .resume = soc15_common_resume,
888 .is_idle = soc15_common_is_idle,
889 .wait_for_idle = soc15_common_wait_for_idle,
890 .soft_reset = soc15_common_soft_reset,
891 .set_clockgating_state = soc15_common_set_clockgating_state,
892 .set_powergating_state = soc15_common_set_powergating_state,
893 .get_clockgating_state= soc15_common_get_clockgating_state,