2 * Copyright 2016 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #ifndef SMU9_DRIVER_IF_H
25 #define SMU9_DRIVER_IF_H
30 * SMU TEAM: Always increment the interface version if
31 * any structure is changed in this file
33 #define SMU9_DRIVER_IF_VERSION 0xB
35 #define PPTABLE_V10_SMU_VERSION 1
37 #define NUM_GFXCLK_DPM_LEVELS 8
38 #define NUM_UVD_DPM_LEVELS 8
39 #define NUM_VCE_DPM_LEVELS 8
40 #define NUM_MP0CLK_DPM_LEVELS 8
41 #define NUM_UCLK_DPM_LEVELS 4
42 #define NUM_SOCCLK_DPM_LEVELS 8
43 #define NUM_DCEFCLK_DPM_LEVELS 8
44 #define NUM_LINK_LEVELS 2
46 #define MAX_GFXCLK_DPM_LEVEL (NUM_GFXCLK_DPM_LEVELS - 1)
47 #define MAX_UVD_DPM_LEVEL (NUM_UVD_DPM_LEVELS - 1)
48 #define MAX_VCE_DPM_LEVEL (NUM_VCE_DPM_LEVELS - 1)
49 #define MAX_MP0CLK_DPM_LEVEL (NUM_MP0CLK_DPM_LEVELS - 1)
50 #define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1)
51 #define MAX_SOCCLK_DPM_LEVEL (NUM_SOCCLK_DPM_LEVELS - 1)
52 #define MAX_DCEFCLK_DPM_LEVEL (NUM_DCEFCLK_DPM_LEVELS - 1)
53 #define MAX_LINK_DPM_LEVEL (NUM_LINK_LEVELS - 1)
55 #define MIN_GFXCLK_DPM_LEVEL 0
56 #define MIN_UVD_DPM_LEVEL 0
57 #define MIN_VCE_DPM_LEVEL 0
58 #define MIN_MP0CLK_DPM_LEVEL 0
59 #define MIN_UCLK_DPM_LEVEL 0
60 #define MIN_SOCCLK_DPM_LEVEL 0
61 #define MIN_DCEFCLK_DPM_LEVEL 0
62 #define MIN_LINK_DPM_LEVEL 0
64 #define NUM_EVV_VOLTAGE_LEVELS 8
65 #define MAX_EVV_VOLTAGE_LEVEL (NUM_EVV_VOLTAGE_LEVELS - 1)
66 #define MIN_EVV_VOLTAGE_LEVEL 0
68 #define NUM_PSP_LEVEL_MAP 4
71 #define PPSMC_GeminiModeNone 0 /* Single GPU board */
72 #define PPSMC_GeminiModeMaster 1 /* Master GPU on a Gemini board */
73 #define PPSMC_GeminiModeSlave 2 /* Slave GPU on a Gemini board */
75 /* Voltage Modes for DPMs */
76 #define VOLTAGE_MODE_AVFS_INTERPOLATE 0
77 #define VOLTAGE_MODE_AVFS_WORST_CASE 1
78 #define VOLTAGE_MODE_STATIC 2
81 uint32_t FbMult; /* Feedback Multiplier, bit 8:0 int, bit 15:12 post_div, bit 31:16 frac */
82 uint32_t SsFbMult; /* Spread FB Mult: bit 8:0 int, bit 31:16 frac */
85 uint8_t Did; /* DID */
110 #define NUM_DSPCLK_LEVELS 8
121 uint16_t Freq; /* in MHz */
122 uint16_t Vid; /* min voltage in SVI2 VID */
123 } DisplayClockTable_t;
127 uint16_t SocketPowerLimit; /* Watts */
128 uint16_t TdcLimit; /* Amps */
129 uint16_t EdcLimit; /* Amps */
130 uint16_t TedgeLimit; /* Celcius */
131 uint16_t ThotspotLimit; /* Celcius */
132 uint16_t ThbmLimit; /* Celcius */
133 uint16_t Tvr_socLimit; /* Celcius */
134 uint16_t Tvr_memLimit; /* Celcius */
135 uint16_t Tliquid1Limit; /* Celcius */
136 uint16_t Tliquid2Limit; /* Celcius */
137 uint16_t TplxLimit; /* Celcius */
138 uint16_t LoadLineResistance; /* in mOhms */
139 uint32_t FitLimit; /* Failures in time (failures per million parts over the defined lifetime) */
141 /* External Component Communication Settings */
142 uint8_t Liquid1_I2C_address;
143 uint8_t Liquid2_I2C_address;
144 uint8_t Vr_I2C_address;
145 uint8_t Plx_I2C_address;
149 uint32_t GeminiApertureHigh;
150 uint32_t GeminiApertureLow;
152 uint8_t Liquid_I2C_LineSCL;
153 uint8_t Liquid_I2C_LineSDA;
154 uint8_t Vr_I2C_LineSCL;
155 uint8_t Vr_I2C_LineSDA;
156 uint8_t Plx_I2C_LineSCL;
157 uint8_t Plx_I2C_LineSDA;
161 uint8_t UlvOffsetVid; /* SVI2 VID */
162 uint8_t UlvSmnclkDid; /* DID for ULV mode. 0 means CLK will not be modified in ULV. */
163 uint8_t UlvMp1clkDid; /* DID for ULV mode. 0 means CLK will not be modified in ULV. */
164 uint8_t UlvGfxclkBypass; /* 1 to turn off/bypass Gfxclk during ULV, 0 to leave Gfxclk on during ULV */
166 /* VDDCR_SOC Voltages */
167 uint8_t SocVid[NUM_EVV_VOLTAGE_LEVELS];
169 /* This is the minimum voltage needed to run the SOC. */
170 uint8_t MinVoltageVid; /* Minimum Voltage ("Vmin") of ASIC */
171 uint8_t MaxVoltageVid; /* Maximum Voltage allowable */
172 uint8_t MaxVidStep; /* Max VID step that SMU will request. Multiple steps are taken if voltage change exceeds this value. */
175 uint8_t UlvPhaseSheddingPsi0; /* set this to 1 to set PSI0/1 to 1 in ULV mode */
176 uint8_t UlvPhaseSheddingPsi1; /* set this to 1 to set PSI0/1 to 1 in ULV mode */
177 uint8_t padding8_2[2];
179 /* SOC Frequencies */
180 PllSetting_t GfxclkLevel [NUM_GFXCLK_DPM_LEVELS];
182 uint8_t SocclkDid [NUM_SOCCLK_DPM_LEVELS]; /* DID */
183 uint8_t SocDpmVoltageIndex [NUM_SOCCLK_DPM_LEVELS];
185 uint8_t VclkDid [NUM_UVD_DPM_LEVELS]; /* DID */
186 uint8_t DclkDid [NUM_UVD_DPM_LEVELS]; /* DID */
187 uint8_t UvdDpmVoltageIndex [NUM_UVD_DPM_LEVELS];
189 uint8_t EclkDid [NUM_VCE_DPM_LEVELS]; /* DID */
190 uint8_t VceDpmVoltageIndex [NUM_VCE_DPM_LEVELS];
192 uint8_t Mp0clkDid [NUM_MP0CLK_DPM_LEVELS]; /* DID */
193 uint8_t Mp0DpmVoltageIndex [NUM_MP0CLK_DPM_LEVELS];
195 DisplayClockTable_t DisplayClockTable[DSPCLK_COUNT][NUM_DSPCLK_LEVELS];
196 QuadraticInt_t DisplayClock2Gfxclk[DSPCLK_COUNT];
198 uint8_t GfxDpmVoltageMode;
199 uint8_t SocDpmVoltageMode;
200 uint8_t UclkDpmVoltageMode;
201 uint8_t UvdDpmVoltageMode;
203 uint8_t VceDpmVoltageMode;
204 uint8_t Mp0DpmVoltageMode;
205 uint8_t DisplayDpmVoltageMode;
208 uint16_t GfxclkSlewRate;
211 uint32_t LowGfxclkInterruptThreshold; /* in units of 10KHz */
213 /* Alpha parameters for clock averages. ("255"=1) */
214 uint8_t GfxclkAverageAlpha;
215 uint8_t SocclkAverageAlpha;
216 uint8_t UclkAverageAlpha;
217 uint8_t GfxActivityAverageAlpha;
220 uint8_t MemVid[NUM_UCLK_DPM_LEVELS]; /* VID */
221 PllSetting_t UclkLevel[NUM_UCLK_DPM_LEVELS]; /* Full PLL settings */
222 uint8_t MemSocVoltageIndex[NUM_UCLK_DPM_LEVELS];
223 uint8_t LowestUclkReservedForUlv; /* Set this to 1 if UCLK DPM0 is reserved for ULV-mode only */
224 uint8_t paddingUclk[3];
225 uint16_t NumMemoryChannels; /* Used for memory bandwidth calculations */
226 uint16_t MemoryChannelWidth; /* Used for memory bandwidth calculations */
229 uint8_t CksEnable[NUM_GFXCLK_DPM_LEVELS];
230 uint8_t CksVidOffset[NUM_GFXCLK_DPM_LEVELS];
232 /* MP0 Mapping Table */
233 uint8_t PspLevelMap[NUM_PSP_LEVEL_MAP];
235 /* Link DPM Settings */
236 uint8_t PcieGenSpeed[NUM_LINK_LEVELS]; /* 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 */
237 uint8_t PcieLaneCount[NUM_LINK_LEVELS]; /* 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 */
238 uint8_t LclkDid[NUM_LINK_LEVELS]; /* Leave at 0 to use hardcoded values in FW */
239 uint8_t paddingLinkDpm[2];
242 uint16_t FanStopTemp; /* Celcius */
243 uint16_t FanStartTemp; /* Celcius */
245 uint16_t FanGainEdge;
246 uint16_t FanGainHotspot;
247 uint16_t FanGainLiquid;
248 uint16_t FanGainVrVddc;
249 uint16_t FanGainVrMvdd;
253 uint16_t FanAcousticLimitRpm;
254 uint16_t FanThrottlingRpm;
255 uint16_t FanMaximumRpm;
256 uint16_t FanTargetTemperature;
257 uint16_t FanTargetGfxclk;
258 uint8_t FanZeroRpmEnable;
261 /* The following are AFC override parameters. Leave at 0 to use FW defaults. */
262 int16_t FuzzyFan_ErrorSetDelta;
263 int16_t FuzzyFan_ErrorRateSetDelta;
264 int16_t FuzzyFan_PwmSetDelta;
265 uint16_t FuzzyFan_Reserved;
268 uint8_t AcDcGpio; /* GPIO pin configured for AC/DC switching */
269 uint8_t AcDcPolarity; /* GPIO polarity for AC/DC switching */
270 uint8_t VR0HotGpio; /* GPIO pin configured for VR0 HOT event */
271 uint8_t VR0HotPolarity; /* GPIO polarity for VR0 HOT event */
272 uint8_t VR1HotGpio; /* GPIO pin configured for VR1 HOT event */
273 uint8_t VR1HotPolarity; /* GPIO polarity for VR1 HOT event */
274 uint8_t Padding1; /* replace GPIO pin configured for CTF */
275 uint8_t Padding2; /* replace GPIO polarity for CTF */
277 /* LED Display Settings */
278 uint8_t LedPin0; /* GPIO number for LedPin[0] */
279 uint8_t LedPin1; /* GPIO number for LedPin[1] */
280 uint8_t LedPin2; /* GPIO number for LedPin[2] */
284 uint8_t OverrideBtcGbCksOn;
285 uint8_t OverrideAvfsGbCksOn;
286 uint8_t PaddingAvfs8[2];
288 GbVdroopTable_t BtcGbVdroopTableCksOn;
289 GbVdroopTable_t BtcGbVdroopTableCksOff;
291 QuadraticInt_t AvfsGbCksOn; /* Replacement equation */
292 QuadraticInt_t AvfsGbCksOff; /* Replacement equation */
294 uint8_t StaticVoltageOffsetVid[NUM_GFXCLK_DPM_LEVELS]; /* This values are added on to the final voltage calculation */
296 /* Ageing Guardband Parameters */
297 uint32_t AConstant[3];
298 uint16_t DC_tol_sigma;
299 uint16_t Platform_mean;
300 uint16_t Platform_sigma;
301 uint16_t PSM_Age_CompFactor;
303 uint32_t DpmLevelPowerDelta;
305 uint32_t Reserved[19];
307 /* Padding - ignore */
308 uint32_t MmHubPadding[7]; /* SMU internal use */
313 uint16_t MinClock; // This is either DCEFCLK or SOCCLK (in MHz)
314 uint16_t MaxClock; // This is either DCEFCLK or SOCCLK (in MHz)
320 } WatermarkRowGeneric_t;
322 #define NUM_WM_RANGES 4
332 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
334 uint32_t MmHubPadding[7]; /* SMU internal use */
337 #ifdef PPTABLE_V10_SMU_VERSION
339 float AvfsGbCksOn[NUM_GFXCLK_DPM_LEVELS];
340 float AcBtcGbCksOn[NUM_GFXCLK_DPM_LEVELS];
341 float AvfsGbCksOff[NUM_GFXCLK_DPM_LEVELS];
342 float AcBtcGbCksOff[NUM_GFXCLK_DPM_LEVELS];
345 uint32_t MmHubPadding[7]; /* SMU internal use */
349 uint32_t AvfsGbCksOn[NUM_GFXCLK_DPM_LEVELS];
350 uint32_t AcBtcGbCksOn[NUM_GFXCLK_DPM_LEVELS];
351 uint32_t AvfsGbCksOff[NUM_GFXCLK_DPM_LEVELS];
352 uint32_t AcBtcGbCksOff[NUM_GFXCLK_DPM_LEVELS];
355 uint32_t MmHubPadding[7]; /* SMU internal use */
360 uint16_t avgPsmCount[30];
361 uint16_t minPsmCount[30];
362 float avgPsmVoltage[30];
363 float minPsmVoltage[30];
365 uint32_t MmHubPadding[7]; /* SMU internal use */
373 uint32_t VFT0_m1; /* Q16.16 */
374 uint32_t VFT0_m2; /* Q16.16 */
375 uint32_t VFT0_b; /* Q16.16 */
377 uint32_t VFT1_m1; /* Q16.16 */
378 uint32_t VFT1_m2; /* Q16.16 */
379 uint32_t VFT1_b; /* Q16.16 */
381 uint32_t VFT2_m1; /* Q16.16 */
382 uint32_t VFT2_m2; /* Q16.16 */
383 uint32_t VFT2_b; /* Q16.16 */
385 uint32_t AvfsGb0_m1; /* Q16.16 */
386 uint32_t AvfsGb0_m2; /* Q16.16 */
387 uint32_t AvfsGb0_b; /* Q16.16 */
389 uint32_t AcBtcGb_m1; /* Q16.16 */
390 uint32_t AcBtcGb_m2; /* Q16.16 */
391 uint32_t AcBtcGb_b; /* Q16.16 */
393 uint32_t AvfsTempCold;
394 uint32_t AvfsTempMid;
395 uint32_t AvfsTempHot;
397 uint32_t InversionVoltage; /* in mV with 2 fractional bits */
399 uint32_t P2V_m1; /* Q16.16 */
400 uint32_t P2V_m2; /* Q16.16 */
401 uint32_t P2V_b; /* Q16.16 */
403 uint32_t P2VCharzFreq; /* in 10KHz units */
405 uint32_t EnabledAvfsModules;
407 uint32_t MmHubPadding[7]; /* SMU internal use */
408 } AvfsFuseOverride_t;
410 /* These defines are used with the following messages:
411 * SMC_MSG_TransferTableDram2Smu
412 * SMC_MSG_TransferTableSmu2Dram
414 #define TABLE_PPTABLE 0
415 #define TABLE_WATERMARKS 1
417 #define TABLE_AVFS_PSM_DEBUG 3
418 #define TABLE_AVFS_FUSE_OVERRIDE 4
419 #define TABLE_PMSTATUSLOG 5
420 #define TABLE_COUNT 6
422 /* These defines are used with the SMC_MSG_SetUclkFastSwitch message. */
423 #define UCLK_SWITCH_SLOW 0
424 #define UCLK_SWITCH_FAST 1
426 /* GFX DIDT Configuration */
427 #define SQ_Enable_MASK 0x1
428 #define SQ_IR_MASK 0x2
429 #define SQ_PCC_MASK 0x4
430 #define SQ_EDC_MASK 0x8
432 #define TCP_Enable_MASK 0x100
433 #define TCP_IR_MASK 0x200
434 #define TCP_PCC_MASK 0x400
435 #define TCP_EDC_MASK 0x800
437 #define TD_Enable_MASK 0x10000
438 #define TD_IR_MASK 0x20000
439 #define TD_PCC_MASK 0x40000
440 #define TD_EDC_MASK 0x80000
442 #define DB_Enable_MASK 0x1000000
443 #define DB_IR_MASK 0x2000000
444 #define DB_PCC_MASK 0x4000000
445 #define DB_EDC_MASK 0x8000000
447 #define SQ_Enable_SHIFT 0
448 #define SQ_IR_SHIFT 1
449 #define SQ_PCC_SHIFT 2
450 #define SQ_EDC_SHIFT 3
452 #define TCP_Enable_SHIFT 8
453 #define TCP_IR_SHIFT 9
454 #define TCP_PCC_SHIFT 10
455 #define TCP_EDC_SHIFT 11
457 #define TD_Enable_SHIFT 16
458 #define TD_IR_SHIFT 17
459 #define TD_PCC_SHIFT 18
460 #define TD_EDC_SHIFT 19
462 #define DB_Enable_SHIFT 24
463 #define DB_IR_SHIFT 25
464 #define DB_PCC_SHIFT 26
465 #define DB_EDC_SHIFT 27