2 * Copyright 2015 Advanced Micro Devices, Inc.
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5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #ifndef _GPU_SCHEDULER_H_
25 #define _GPU_SCHEDULER_H_
27 #include <linux/kfifo.h>
28 #include <linux/dma-fence.h>
30 struct amd_gpu_scheduler;
34 * A scheduler entity is a wrapper around a job queue or a group
35 * of other entities. Entities take turns emitting jobs from their
36 * job queues to corresponding hardware ring based on scheduling
39 struct amd_sched_entity {
40 struct list_head list;
41 struct amd_sched_rq *rq;
42 struct amd_gpu_scheduler *sched;
44 spinlock_t queue_lock;
45 struct kfifo job_queue;
48 uint64_t fence_context;
50 struct dma_fence *dependency;
51 struct dma_fence_cb cb;
55 * Run queue is a set of entities scheduling command submissions for
56 * one specific ring. It implements the scheduling policy that selects
57 * the next entity to emit commands from.
61 struct list_head entities;
62 struct amd_sched_entity *current_entity;
65 struct amd_sched_fence {
66 struct dma_fence scheduled;
67 struct dma_fence finished;
68 struct dma_fence_cb cb;
69 struct dma_fence *parent;
70 struct amd_gpu_scheduler *sched;
75 struct amd_sched_job {
76 struct amd_gpu_scheduler *sched;
77 struct amd_sched_entity *s_entity;
78 struct amd_sched_fence *s_fence;
79 struct dma_fence_cb finish_cb;
80 struct work_struct finish_work;
81 struct list_head node;
82 struct delayed_work work_tdr;
86 extern const struct dma_fence_ops amd_sched_fence_ops_scheduled;
87 extern const struct dma_fence_ops amd_sched_fence_ops_finished;
88 static inline struct amd_sched_fence *to_amd_sched_fence(struct dma_fence *f)
90 if (f->ops == &amd_sched_fence_ops_scheduled)
91 return container_of(f, struct amd_sched_fence, scheduled);
93 if (f->ops == &amd_sched_fence_ops_finished)
94 return container_of(f, struct amd_sched_fence, finished);
100 * Define the backend operations called by the scheduler,
101 * these functions should be implemented in driver side
103 struct amd_sched_backend_ops {
104 struct dma_fence *(*dependency)(struct amd_sched_job *sched_job);
105 struct dma_fence *(*run_job)(struct amd_sched_job *sched_job);
106 void (*timedout_job)(struct amd_sched_job *sched_job);
107 void (*free_job)(struct amd_sched_job *sched_job);
110 enum amd_sched_priority {
111 AMD_SCHED_PRIORITY_MIN,
112 AMD_SCHED_PRIORITY_NORMAL = AMD_SCHED_PRIORITY_MIN,
113 AMD_SCHED_PRIORITY_KERNEL,
114 AMD_SCHED_PRIORITY_MAX
118 * One scheduler is implemented for each hardware ring
120 struct amd_gpu_scheduler {
121 const struct amd_sched_backend_ops *ops;
122 uint32_t hw_submission_limit;
125 struct amd_sched_rq sched_rq[AMD_SCHED_PRIORITY_MAX];
126 wait_queue_head_t wake_up_worker;
127 wait_queue_head_t job_scheduled;
128 atomic_t hw_rq_count;
129 atomic64_t job_id_count;
130 struct task_struct *thread;
131 struct list_head ring_mirror_list;
132 spinlock_t job_list_lock;
135 int amd_sched_init(struct amd_gpu_scheduler *sched,
136 const struct amd_sched_backend_ops *ops,
137 uint32_t hw_submission, long timeout, const char *name);
138 void amd_sched_fini(struct amd_gpu_scheduler *sched);
140 int amd_sched_entity_init(struct amd_gpu_scheduler *sched,
141 struct amd_sched_entity *entity,
142 struct amd_sched_rq *rq,
144 void amd_sched_entity_fini(struct amd_gpu_scheduler *sched,
145 struct amd_sched_entity *entity);
146 void amd_sched_entity_push_job(struct amd_sched_job *sched_job);
148 int amd_sched_fence_slab_init(void);
149 void amd_sched_fence_slab_fini(void);
151 struct amd_sched_fence *amd_sched_fence_create(
152 struct amd_sched_entity *s_entity, void *owner);
153 void amd_sched_fence_scheduled(struct amd_sched_fence *fence);
154 void amd_sched_fence_finished(struct amd_sched_fence *fence);
155 int amd_sched_job_init(struct amd_sched_job *job,
156 struct amd_gpu_scheduler *sched,
157 struct amd_sched_entity *entity,
159 void amd_sched_hw_job_reset(struct amd_gpu_scheduler *sched);
160 void amd_sched_job_recovery(struct amd_gpu_scheduler *sched);
161 bool amd_sched_dependency_optimized(struct dma_fence* fence,
162 struct amd_sched_entity *entity);