drivers/gpu/drm/armada/armada_crtc.c

   1 /*
   2  * Copyright (C) 2012 Russell King
   3  *  Rewritten from the dovefb driver, and Armada510 manuals.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  */
   9 #include <linux/clk.h>
  10 #include <linux/component.h>
  11 #include <linux/of_device.h>
  12 #include <linux/platform_device.h>
  13 #include <drm/drmP.h>
  14 #include <drm/drm_crtc_helper.h>
  15 #include <drm/drm_plane_helper.h>
  16 #include "armada_crtc.h"
  17 #include "armada_drm.h"
  18 #include "armada_fb.h"
  19 #include "armada_gem.h"
  20 #include "armada_hw.h"
  21 #include "armada_trace.h"
  22
  23 struct armada_frame_work {
  24         struct armada_plane_work work;
  25         struct drm_pending_vblank_event *event;
  26         struct armada_regs regs[4];
  27         struct drm_framebuffer *old_fb;
  28 };
  29
  30 enum csc_mode {
  31         CSC_AUTO = 0,
  32         CSC_YUV_CCIR601 = 1,
  33         CSC_YUV_CCIR709 = 2,
  34         CSC_RGB_COMPUTER = 1,
  35         CSC_RGB_STUDIO = 2,
  36 };
  37
  38 static const uint32_t armada_primary_formats[] = {
  39         DRM_FORMAT_UYVY,
  40         DRM_FORMAT_YUYV,
  41         DRM_FORMAT_VYUY,
  42         DRM_FORMAT_YVYU,
  43         DRM_FORMAT_ARGB8888,
  44         DRM_FORMAT_ABGR8888,
  45         DRM_FORMAT_XRGB8888,
  46         DRM_FORMAT_XBGR8888,
  47         DRM_FORMAT_RGB888,
  48         DRM_FORMAT_BGR888,
  49         DRM_FORMAT_ARGB1555,
  50         DRM_FORMAT_ABGR1555,
  51         DRM_FORMAT_RGB565,
  52         DRM_FORMAT_BGR565,
  53 };
  54
  55 /*
  56  * A note about interlacing.  Let's consider HDMI 1920x1080i.
  57  * The timing parameters we have from X are:
  58  *  Hact HsyA HsyI Htot  Vact VsyA VsyI Vtot
  59  *  1920 2448 2492 2640  1080 1084 1094 1125
  60  * Which get translated to:
  61  *  Hact HsyA HsyI Htot  Vact VsyA VsyI Vtot
  62  *  1920 2448 2492 2640   540  542  547  562
  63  *
  64  * This is how it is defined by CEA-861-D - line and pixel numbers are
  65  * referenced to the rising edge of VSYNC and HSYNC.  Total clocks per
  66  * line: 2640.  The odd frame, the first active line is at line 21, and
  67  * the even frame, the first active line is 584.
  68  *
  69  * LN:    560     561     562     563             567     568    569
  70  * DE:    ~~~|____________________________//__________________________
  71  * HSYNC: ____|~|_____|~|_____|~|_____|~|_//__|~|_____|~|_____|~|_____
  72  * VSYNC: _________________________|~~~~~~//~~~~~~~~~~~~~~~|__________
  73  *  22 blanking lines.  VSYNC at 1320 (referenced to the HSYNC rising edge).
  74  *
  75  * LN:    1123   1124    1125      1               5       6      7
  76  * DE:    ~~~|____________________________//__________________________
  77  * HSYNC: ____|~|_____|~|_____|~|_____|~|_//__|~|_____|~|_____|~|_____
  78  * VSYNC: ____________________|~~~~~~~~~~~//~~~~~~~~~~|_______________
  79  *  23 blanking lines
  80  *
  81  * The Armada LCD Controller line and pixel numbers are, like X timings,
  82  * referenced to the top left of the active frame.
  83  *
  84  * So, translating these to our LCD controller:
  85  *  Odd frame, 563 total lines, VSYNC at line 543-548, pixel 1128.
  86  *  Even frame, 562 total lines, VSYNC at line 542-547, pixel 2448.
  87  * Note: Vsync front porch remains constant!
  88  *
  89  * if (odd_frame) {
  90  *   vtotal = mode->crtc_vtotal + 1;
  91  *   vbackporch = mode->crtc_vsync_start - mode->crtc_vdisplay + 1;
  92  *   vhorizpos = mode->crtc_hsync_start - mode->crtc_htotal / 2
  93  * } else {
  94  *   vtotal = mode->crtc_vtotal;
  95  *   vbackporch = mode->crtc_vsync_start - mode->crtc_vdisplay;
  96  *   vhorizpos = mode->crtc_hsync_start;
  97  * }
  98  * vfrontporch = mode->crtc_vtotal - mode->crtc_vsync_end;
  99  *
 100  * So, we need to reprogram these registers on each vsync event:
 101  *  LCD_SPU_V_PORCH, LCD_SPU_ADV_REG, LCD_SPUT_V_H_TOTAL
 102  *
 103  * Note: we do not use the frame done interrupts because these appear
 104  * to happen too early, and lead to jitter on the display (presumably
 105  * they occur at the end of the last active line, before the vsync back
 106  * porch, which we're reprogramming.)
 107  */
 108
 109 void
 110 armada_drm_crtc_update_regs(struct armada_crtc *dcrtc, struct armada_regs *regs)
 111 {
 112         while (regs->offset != ~0) {
 113                 void __iomem *reg = dcrtc->base + regs->offset;
 114                 uint32_t val;
 115
 116                 val = regs->mask;
 117                 if (val != 0)
 118                         val &= readl_relaxed(reg);
 119                 writel_relaxed(val | regs->val, reg);
 120                 ++regs;
 121         }
 122 }
 123
 124 #define dpms_blanked(dpms)      ((dpms) != DRM_MODE_DPMS_ON)
 125
 126 static void armada_drm_crtc_update(struct armada_crtc *dcrtc)
 127 {
 128         uint32_t dumb_ctrl;
 129
 130         dumb_ctrl = dcrtc->cfg_dumb_ctrl;
 131
 132         if (!dpms_blanked(dcrtc->dpms))
 133                 dumb_ctrl |= CFG_DUMB_ENA;
 134
 135         /*
 136          * When the dumb interface isn't in DUMB24_RGB888_0 mode, it might
 137          * be using SPI or GPIO.  If we set this to DUMB_BLANK, we will
 138          * force LCD_D[23:0] to output blank color, overriding the GPIO or
 139          * SPI usage.  So leave it as-is unless in DUMB24_RGB888_0 mode.
 140          */
 141         if (dpms_blanked(dcrtc->dpms) &&
 142             (dumb_ctrl & DUMB_MASK) == DUMB24_RGB888_0) {
 143                 dumb_ctrl &= ~DUMB_MASK;
 144                 dumb_ctrl |= DUMB_BLANK;
 145         }
 146
 147         /*
 148          * The documentation doesn't indicate what the normal state of
 149          * the sync signals are.  Sebastian Hesselbart kindly probed
 150          * these signals on his board to determine their state.
 151          *
 152          * The non-inverted state of the sync signals is active high.
 153          * Setting these bits makes the appropriate signal active low.
 154          */
 155         if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NCSYNC)
 156                 dumb_ctrl |= CFG_INV_CSYNC;
 157         if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NHSYNC)
 158                 dumb_ctrl |= CFG_INV_HSYNC;
 159         if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NVSYNC)
 160                 dumb_ctrl |= CFG_INV_VSYNC;
 161
 162         if (dcrtc->dumb_ctrl != dumb_ctrl) {
 163                 dcrtc->dumb_ctrl = dumb_ctrl;
 164                 writel_relaxed(dumb_ctrl, dcrtc->base + LCD_SPU_DUMB_CTRL);
 165         }
 166 }
 167
 168 void armada_drm_plane_calc_addrs(u32 *addrs, struct drm_framebuffer *fb,
 169         int x, int y)
 170 {
 171         u32 addr = drm_fb_obj(fb)->dev_addr;
 172         u32 pixel_format = fb->pixel_format;
 173         int num_planes = drm_format_num_planes(pixel_format);
 174         int i;
 175
 176         if (num_planes > 3)
 177                 num_planes = 3;
 178
 179         for (i = 0; i < num_planes; i++)
 180                 addrs[i] = addr + fb->offsets[i] + y * fb->pitches[i] +
 181                              x * drm_format_plane_cpp(pixel_format, i);
 182         for (; i < 3; i++)
 183                 addrs[i] = 0;
 184 }
 185
 186 static unsigned armada_drm_crtc_calc_fb(struct drm_framebuffer *fb,
 187         int x, int y, struct armada_regs *regs, bool interlaced)
 188 {
 189         unsigned pitch = fb->pitches[0];
 190         u32 addrs[3], addr_odd, addr_even;
 191         unsigned i = 0;
 192
 193         DRM_DEBUG_DRIVER("pitch %u x %d y %d bpp %d\n",
 194                 pitch, x, y, fb->bits_per_pixel);
 195
 196         armada_drm_plane_calc_addrs(addrs, fb, x, y);
 197
 198         addr_odd = addr_even = addrs[0];
 199
 200         if (interlaced) {
 201                 addr_even += pitch;
 202                 pitch *= 2;
 203         }
 204
 205         /* write offset, base, and pitch */
 206         armada_reg_queue_set(regs, i, addr_odd, LCD_CFG_GRA_START_ADDR0);
 207         armada_reg_queue_set(regs, i, addr_even, LCD_CFG_GRA_START_ADDR1);
 208         armada_reg_queue_mod(regs, i, pitch, 0xffff, LCD_CFG_GRA_PITCH);
 209
 210         return i;
 211 }
 212
 213 static void armada_drm_plane_work_run(struct armada_crtc *dcrtc,
 214         struct drm_plane *plane)
 215 {
 216         struct armada_plane *dplane = drm_to_armada_plane(plane);
 217         struct armada_plane_work *work = xchg(&dplane->work, NULL);
 218
 219         /* Handle any pending frame work. */
 220         if (work) {
 221                 work->fn(dcrtc, dplane, work);
 222                 drm_crtc_vblank_put(&dcrtc->crtc);
 223         }
 224
 225         wake_up(&dplane->frame_wait);
 226 }
 227
 228 int armada_drm_plane_work_queue(struct armada_crtc *dcrtc,
 229         struct armada_plane *plane, struct armada_plane_work *work)
 230 {
 231         int ret;
 232
 233         ret = drm_crtc_vblank_get(&dcrtc->crtc);
 234         if (ret) {
 235                 DRM_ERROR("failed to acquire vblank counter\n");
 236                 return ret;
 237         }
 238
 239         ret = cmpxchg(&plane->work, NULL, work) ? -EBUSY : 0;
 240         if (ret)
 241                 drm_crtc_vblank_put(&dcrtc->crtc);
 242
 243         return ret;
 244 }
 245
 246 int armada_drm_plane_work_wait(struct armada_plane *plane, long timeout)
 247 {
 248         return wait_event_timeout(plane->frame_wait, !plane->work, timeout);
 249 }
 250
 251 struct armada_plane_work *armada_drm_plane_work_cancel(
 252         struct armada_crtc *dcrtc, struct armada_plane *plane)
 253 {
 254         struct armada_plane_work *work = xchg(&plane->work, NULL);
 255
 256         if (work)
 257                 drm_crtc_vblank_put(&dcrtc->crtc);
 258
 259         return work;
 260 }
 261
 262 static int armada_drm_crtc_queue_frame_work(struct armada_crtc *dcrtc,
 263         struct armada_frame_work *work)
 264 {
 265         struct armada_plane *plane = drm_to_armada_plane(dcrtc->crtc.primary);
 266
 267         return armada_drm_plane_work_queue(dcrtc, plane, &work->work);
 268 }
 269
 270 static void armada_drm_crtc_complete_frame_work(struct armada_crtc *dcrtc,
 271         struct armada_plane *plane, struct armada_plane_work *work)
 272 {
 273         struct armada_frame_work *fwork = container_of(work, struct armada_frame_work, work);
 274         struct drm_device *dev = dcrtc->crtc.dev;
 275         unsigned long flags;
 276
 277         spin_lock_irqsave(&dcrtc->irq_lock, flags);
 278         armada_drm_crtc_update_regs(dcrtc, fwork->regs);
 279         spin_unlock_irqrestore(&dcrtc->irq_lock, flags);
 280
 281         if (fwork->event) {
 282                 spin_lock_irqsave(&dev->event_lock, flags);
 283                 drm_crtc_send_vblank_event(&dcrtc->crtc, fwork->event);
 284                 spin_unlock_irqrestore(&dev->event_lock, flags);
 285         }
 286
 287         /* Finally, queue the process-half of the cleanup. */
 288         __armada_drm_queue_unref_work(dcrtc->crtc.dev, fwork->old_fb);
 289         kfree(fwork);
 290 }
 291
 292 static void armada_drm_crtc_finish_fb(struct armada_crtc *dcrtc,
 293         struct drm_framebuffer *fb, bool force)
 294 {
 295         struct armada_frame_work *work;
 296
 297         if (!fb)
 298                 return;
 299
 300         if (force) {
 301                 /* Display is disabled, so just drop the old fb */
 302                 drm_framebuffer_unreference(fb);
 303                 return;
 304         }
 305
 306         work = kmalloc(sizeof(*work), GFP_KERNEL);
 307         if (work) {
 308                 int i = 0;
 309                 work->work.fn = armada_drm_crtc_complete_frame_work;
 310                 work->event = NULL;
 311                 work->old_fb = fb;
 312                 armada_reg_queue_end(work->regs, i);
 313
 314                 if (armada_drm_crtc_queue_frame_work(dcrtc, work) == 0)
 315                         return;
 316
 317                 kfree(work);
 318         }
 319
 320         /*
 321          * Oops - just drop the reference immediately and hope for
 322          * the best.  The worst that will happen is the buffer gets
 323          * reused before it has finished being displayed.
 324          */
 325         drm_framebuffer_unreference(fb);
 326 }
 327
 328 static void armada_drm_vblank_off(struct armada_crtc *dcrtc)
 329 {
 330         /*
 331          * Tell the DRM core that vblank IRQs aren't going to happen for
 332          * a while.  This cleans up any pending vblank events for us.
 333          */
 334         drm_crtc_vblank_off(&dcrtc->crtc);
 335         armada_drm_plane_work_run(dcrtc, dcrtc->crtc.primary);
 336 }
 337
 338 void armada_drm_crtc_gamma_set(struct drm_crtc *crtc, u16 r, u16 g, u16 b,
 339         int idx)
 340 {
 341 }
 342
 343 void armada_drm_crtc_gamma_get(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
 344         int idx)
 345 {
 346 }
 347
 348 /* The mode_config.mutex will be held for this call */
 349 static void armada_drm_crtc_dpms(struct drm_crtc *crtc, int dpms)
 350 {
 351         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 352
 353         if (dcrtc->dpms != dpms) {
 354                 dcrtc->dpms = dpms;
 355                 if (!IS_ERR(dcrtc->clk) && !dpms_blanked(dpms))
 356                         WARN_ON(clk_prepare_enable(dcrtc->clk));
 357                 armada_drm_crtc_update(dcrtc);
 358                 if (!IS_ERR(dcrtc->clk) && dpms_blanked(dpms))
 359                         clk_disable_unprepare(dcrtc->clk);
 360                 if (dpms_blanked(dpms))
 361                         armada_drm_vblank_off(dcrtc);
 362                 else
 363                         drm_crtc_vblank_on(&dcrtc->crtc);
 364         }
 365 }
 366
 367 /*
 368  * Prepare for a mode set.  Turn off overlay to ensure that we don't end
 369  * up with the overlay size being bigger than the active screen size.
 370  * We rely upon X refreshing this state after the mode set has completed.
 371  *
 372  * The mode_config.mutex will be held for this call
 373  */
 374 static void armada_drm_crtc_prepare(struct drm_crtc *crtc)
 375 {
 376         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 377         struct drm_plane *plane;
 378
 379         /*
 380          * If we have an overlay plane associated with this CRTC, disable
 381          * it before the modeset to avoid its coordinates being outside
 382          * the new mode parameters.
 383          */
 384         plane = dcrtc->plane;
 385         if (plane)
 386                 drm_plane_force_disable(plane);
 387 }
 388
 389 /* The mode_config.mutex will be held for this call */
 390 static void armada_drm_crtc_commit(struct drm_crtc *crtc)
 391 {
 392         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 393
 394         if (dcrtc->dpms != DRM_MODE_DPMS_ON) {
 395                 dcrtc->dpms = DRM_MODE_DPMS_ON;
 396                 armada_drm_crtc_update(dcrtc);
 397         }
 398 }
 399
 400 /* The mode_config.mutex will be held for this call */
 401 static bool armada_drm_crtc_mode_fixup(struct drm_crtc *crtc,
 402         const struct drm_display_mode *mode, struct drm_display_mode *adj)
 403 {
 404         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 405         int ret;
 406
 407         /* We can't do interlaced modes if we don't have the SPU_ADV_REG */
 408         if (!dcrtc->variant->has_spu_adv_reg &&
 409             adj->flags & DRM_MODE_FLAG_INTERLACE)
 410                 return false;
 411
 412         /* Check whether the display mode is possible */
 413         ret = dcrtc->variant->compute_clock(dcrtc, adj, NULL);
 414         if (ret)
 415                 return false;
 416
 417         return true;
 418 }
 419
 420 static void armada_drm_crtc_irq(struct armada_crtc *dcrtc, u32 stat)
 421 {
 422         void __iomem *base = dcrtc->base;
 423         struct drm_plane *ovl_plane;
 424
 425         if (stat & DMA_FF_UNDERFLOW)
 426                 DRM_ERROR("video underflow on crtc %u\n", dcrtc->num);
 427         if (stat & GRA_FF_UNDERFLOW)
 428                 DRM_ERROR("graphics underflow on crtc %u\n", dcrtc->num);
 429
 430         if (stat & VSYNC_IRQ)
 431                 drm_crtc_handle_vblank(&dcrtc->crtc);
 432
 433         spin_lock(&dcrtc->irq_lock);
 434         ovl_plane = dcrtc->plane;
 435         if (ovl_plane)
 436                 armada_drm_plane_work_run(dcrtc, ovl_plane);
 437
 438         if (stat & GRA_FRAME_IRQ && dcrtc->interlaced) {
 439                 int i = stat & GRA_FRAME_IRQ0 ? 0 : 1;
 440                 uint32_t val;
 441
 442                 writel_relaxed(dcrtc->v[i].spu_v_porch, base + LCD_SPU_V_PORCH);
 443                 writel_relaxed(dcrtc->v[i].spu_v_h_total,
 444                                base + LCD_SPUT_V_H_TOTAL);
 445
 446                 val = readl_relaxed(base + LCD_SPU_ADV_REG);
 447                 val &= ~(ADV_VSYNC_L_OFF | ADV_VSYNC_H_OFF | ADV_VSYNCOFFEN);
 448                 val |= dcrtc->v[i].spu_adv_reg;
 449                 writel_relaxed(val, base + LCD_SPU_ADV_REG);
 450         }
 451
 452         if (stat & DUMB_FRAMEDONE && dcrtc->cursor_update) {
 453                 writel_relaxed(dcrtc->cursor_hw_pos,
 454                                base + LCD_SPU_HWC_OVSA_HPXL_VLN);
 455                 writel_relaxed(dcrtc->cursor_hw_sz,
 456                                base + LCD_SPU_HWC_HPXL_VLN);
 457                 armada_updatel(CFG_HWC_ENA,
 458                                CFG_HWC_ENA | CFG_HWC_1BITMOD | CFG_HWC_1BITENA,
 459                                base + LCD_SPU_DMA_CTRL0);
 460                 dcrtc->cursor_update = false;
 461                 armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
 462         }
 463
 464         spin_unlock(&dcrtc->irq_lock);
 465
 466         if (stat & GRA_FRAME_IRQ)
 467                 armada_drm_plane_work_run(dcrtc, dcrtc->crtc.primary);
 468 }
 469
 470 static irqreturn_t armada_drm_irq(int irq, void *arg)
 471 {
 472         struct armada_crtc *dcrtc = arg;
 473         u32 v, stat = readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR);
 474
 475         /*
 476          * This is rediculous - rather than writing bits to clear, we
 477          * have to set the actual status register value.  This is racy.
 478          */
 479         writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ISR);
 480
 481         trace_armada_drm_irq(&dcrtc->crtc, stat);
 482
 483         /* Mask out those interrupts we haven't enabled */
 484         v = stat & dcrtc->irq_ena;
 485
 486         if (v & (VSYNC_IRQ|GRA_FRAME_IRQ|DUMB_FRAMEDONE)) {
 487                 armada_drm_crtc_irq(dcrtc, stat);
 488                 return IRQ_HANDLED;
 489         }
 490         return IRQ_NONE;
 491 }
 492
 493 /* These are locked by dev->vbl_lock */
 494 void armada_drm_crtc_disable_irq(struct armada_crtc *dcrtc, u32 mask)
 495 {
 496         if (dcrtc->irq_ena & mask) {
 497                 dcrtc->irq_ena &= ~mask;
 498                 writel(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA);
 499         }
 500 }
 501
 502 void armada_drm_crtc_enable_irq(struct armada_crtc *dcrtc, u32 mask)
 503 {
 504         if ((dcrtc->irq_ena & mask) != mask) {
 505                 dcrtc->irq_ena |= mask;
 506                 writel(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA);
 507                 if (readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR) & mask)
 508                         writel(0, dcrtc->base + LCD_SPU_IRQ_ISR);
 509         }
 510 }
 511
 512 static uint32_t armada_drm_crtc_calculate_csc(struct armada_crtc *dcrtc)
 513 {
 514         struct drm_display_mode *adj = &dcrtc->crtc.mode;
 515         uint32_t val = 0;
 516
 517         if (dcrtc->csc_yuv_mode == CSC_YUV_CCIR709)
 518                 val |= CFG_CSC_YUV_CCIR709;
 519         if (dcrtc->csc_rgb_mode == CSC_RGB_STUDIO)
 520                 val |= CFG_CSC_RGB_STUDIO;
 521
 522         /*
 523          * In auto mode, set the colorimetry, based upon the HDMI spec.
 524          * 1280x720p, 1920x1080p and 1920x1080i use ITU709, others use
 525          * ITU601.  It may be more appropriate to set this depending on
 526          * the source - but what if the graphic frame is YUV and the
 527          * video frame is RGB?
 528          */
 529         if ((adj->hdisplay == 1280 && adj->vdisplay == 720 &&
 530              !(adj->flags & DRM_MODE_FLAG_INTERLACE)) ||
 531             (adj->hdisplay == 1920 && adj->vdisplay == 1080)) {
 532                 if (dcrtc->csc_yuv_mode == CSC_AUTO)
 533                         val |= CFG_CSC_YUV_CCIR709;
 534         }
 535
 536         /*
 537          * We assume we're connected to a TV-like device, so the YUV->RGB
 538          * conversion should produce a limited range.  We should set this
 539          * depending on the connectors attached to this CRTC, and what
 540          * kind of device they report being connected.
 541          */
 542         if (dcrtc->csc_rgb_mode == CSC_AUTO)
 543                 val |= CFG_CSC_RGB_STUDIO;
 544
 545         return val;
 546 }
 547
 548 static void armada_drm_primary_set(struct drm_crtc *crtc,
 549         struct drm_plane *plane, int x, int y)
 550 {
 551         struct armada_plane_state *state = &drm_to_armada_plane(plane)->state;
 552         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 553         struct armada_regs regs[8];
 554         bool interlaced = dcrtc->interlaced;
 555         unsigned i;
 556         u32 ctrl0;
 557
 558         i = armada_drm_crtc_calc_fb(plane->fb, x, y, regs, interlaced);
 559
 560         armada_reg_queue_set(regs, i, state->dst_yx, LCD_SPU_GRA_OVSA_HPXL_VLN);
 561         armada_reg_queue_set(regs, i, state->src_hw, LCD_SPU_GRA_HPXL_VLN);
 562         armada_reg_queue_set(regs, i, state->dst_hw, LCD_SPU_GZM_HPXL_VLN);
 563
 564         ctrl0 = state->ctrl0;
 565         if (interlaced)
 566                 ctrl0 |= CFG_GRA_FTOGGLE;
 567
 568         armada_reg_queue_mod(regs, i, ctrl0, CFG_GRAFORMAT |
 569                              CFG_GRA_MOD(CFG_SWAPRB | CFG_SWAPUV |
 570                                          CFG_SWAPYU | CFG_YUV2RGB) |
 571                              CFG_PALETTE_ENA | CFG_GRA_FTOGGLE,
 572                              LCD_SPU_DMA_CTRL0);
 573         armada_reg_queue_end(regs, i);
 574         armada_drm_crtc_update_regs(dcrtc, regs);
 575 }
 576
 577 /* The mode_config.mutex will be held for this call */
 578 static int armada_drm_crtc_mode_set(struct drm_crtc *crtc,
 579         struct drm_display_mode *mode, struct drm_display_mode *adj,
 580         int x, int y, struct drm_framebuffer *old_fb)
 581 {
 582         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 583         struct armada_regs regs[17];
 584         uint32_t lm, rm, tm, bm, val, sclk;
 585         unsigned long flags;
 586         unsigned i;
 587         bool interlaced;
 588
 589         drm_framebuffer_reference(crtc->primary->fb);
 590
 591         interlaced = !!(adj->flags & DRM_MODE_FLAG_INTERLACE);
 592
 593         val = CFG_GRA_ENA | CFG_GRA_HSMOOTH;
 594         val |= CFG_GRA_FMT(drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->fmt);
 595         val |= CFG_GRA_MOD(drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->mod);
 596
 597         if (drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->fmt > CFG_420)
 598                 val |= CFG_PALETTE_ENA;
 599
 600         drm_to_armada_plane(crtc->primary)->state.ctrl0 = val;
 601         drm_to_armada_plane(crtc->primary)->state.src_hw =
 602         drm_to_armada_plane(crtc->primary)->state.dst_hw =
 603                 adj->crtc_vdisplay << 16 | adj->crtc_hdisplay;
 604         drm_to_armada_plane(crtc->primary)->state.dst_yx = 0;
 605
 606         i = 0;
 607         rm = adj->crtc_hsync_start - adj->crtc_hdisplay;
 608         lm = adj->crtc_htotal - adj->crtc_hsync_end;
 609         bm = adj->crtc_vsync_start - adj->crtc_vdisplay;
 610         tm = adj->crtc_vtotal - adj->crtc_vsync_end;
 611
 612         DRM_DEBUG_DRIVER("H: %d %d %d %d lm %d rm %d\n",
 613                 adj->crtc_hdisplay,
 614                 adj->crtc_hsync_start,
 615                 adj->crtc_hsync_end,
 616                 adj->crtc_htotal, lm, rm);
 617         DRM_DEBUG_DRIVER("V: %d %d %d %d tm %d bm %d\n",
 618                 adj->crtc_vdisplay,
 619                 adj->crtc_vsync_start,
 620                 adj->crtc_vsync_end,
 621                 adj->crtc_vtotal, tm, bm);
 622
 623         /* Wait for pending flips to complete */
 624         armada_drm_plane_work_wait(drm_to_armada_plane(dcrtc->crtc.primary),
 625                                    MAX_SCHEDULE_TIMEOUT);
 626
 627         drm_crtc_vblank_off(crtc);
 628
 629         val = dcrtc->dumb_ctrl & ~CFG_DUMB_ENA;
 630         if (val != dcrtc->dumb_ctrl) {
 631                 dcrtc->dumb_ctrl = val;
 632                 writel_relaxed(val, dcrtc->base + LCD_SPU_DUMB_CTRL);
 633         }
 634
 635         /*
 636          * If we are blanked, we would have disabled the clock.  Re-enable
 637          * it so that compute_clock() does the right thing.
 638          */
 639         if (!IS_ERR(dcrtc->clk) && dpms_blanked(dcrtc->dpms))
 640                 WARN_ON(clk_prepare_enable(dcrtc->clk));
 641
 642         /* Now compute the divider for real */
 643         dcrtc->variant->compute_clock(dcrtc, adj, &sclk);
 644
 645         /* Ensure graphic fifo is enabled */
 646         armada_reg_queue_mod(regs, i, 0, CFG_PDWN64x66, LCD_SPU_SRAM_PARA1);
 647         armada_reg_queue_set(regs, i, sclk, LCD_CFG_SCLK_DIV);
 648
 649         if (interlaced ^ dcrtc->interlaced) {
 650                 if (adj->flags & DRM_MODE_FLAG_INTERLACE)
 651                         drm_crtc_vblank_get(&dcrtc->crtc);
 652                 else
 653                         drm_crtc_vblank_put(&dcrtc->crtc);
 654                 dcrtc->interlaced = interlaced;
 655         }
 656
 657         spin_lock_irqsave(&dcrtc->irq_lock, flags);
 658
 659         /* Even interlaced/progressive frame */
 660         dcrtc->v[1].spu_v_h_total = adj->crtc_vtotal << 16 |
 661                                     adj->crtc_htotal;
 662         dcrtc->v[1].spu_v_porch = tm << 16 | bm;
 663         val = adj->crtc_hsync_start;
 664         dcrtc->v[1].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN |
 665                 dcrtc->variant->spu_adv_reg;
 666
 667         if (interlaced) {
 668                 /* Odd interlaced frame */
 669                 dcrtc->v[0].spu_v_h_total = dcrtc->v[1].spu_v_h_total +
 670                                                 (1 << 16);
 671                 dcrtc->v[0].spu_v_porch = dcrtc->v[1].spu_v_porch + 1;
 672                 val = adj->crtc_hsync_start - adj->crtc_htotal / 2;
 673                 dcrtc->v[0].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN |
 674                         dcrtc->variant->spu_adv_reg;
 675         } else {
 676                 dcrtc->v[0] = dcrtc->v[1];
 677         }
 678
 679         val = adj->crtc_vdisplay << 16 | adj->crtc_hdisplay;
 680
 681         armada_reg_queue_set(regs, i, val, LCD_SPU_V_H_ACTIVE);
 682         armada_reg_queue_set(regs, i, (lm << 16) | rm, LCD_SPU_H_PORCH);
 683         armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_porch, LCD_SPU_V_PORCH);
 684         armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_h_total,
 685                            LCD_SPUT_V_H_TOTAL);
 686
 687         if (dcrtc->variant->has_spu_adv_reg) {
 688                 armada_reg_queue_mod(regs, i, dcrtc->v[0].spu_adv_reg,
 689                                      ADV_VSYNC_L_OFF | ADV_VSYNC_H_OFF |
 690                                      ADV_VSYNCOFFEN, LCD_SPU_ADV_REG);
 691         }
 692
 693         val = adj->flags & DRM_MODE_FLAG_NVSYNC ? CFG_VSYNC_INV : 0;
 694         armada_reg_queue_mod(regs, i, val, CFG_VSYNC_INV, LCD_SPU_DMA_CTRL1);
 695
 696         val = dcrtc->spu_iopad_ctrl | armada_drm_crtc_calculate_csc(dcrtc);
 697         armada_reg_queue_set(regs, i, val, LCD_SPU_IOPAD_CONTROL);
 698         armada_reg_queue_end(regs, i);
 699
 700         armada_drm_crtc_update_regs(dcrtc, regs);
 701
 702         armada_drm_primary_set(crtc, crtc->primary, x, y);
 703         spin_unlock_irqrestore(&dcrtc->irq_lock, flags);
 704
 705         armada_drm_crtc_update(dcrtc);
 706
 707         drm_crtc_vblank_on(crtc);
 708         armada_drm_crtc_finish_fb(dcrtc, old_fb, dpms_blanked(dcrtc->dpms));
 709
 710         return 0;
 711 }
 712
 713 /* The mode_config.mutex will be held for this call */
 714 static int armada_drm_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
 715         struct drm_framebuffer *old_fb)
 716 {
 717         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 718         struct armada_regs regs[4];
 719         unsigned i;
 720
 721         i = armada_drm_crtc_calc_fb(crtc->primary->fb, crtc->x, crtc->y, regs,
 722                                     dcrtc->interlaced);
 723         armada_reg_queue_end(regs, i);
 724
 725         /* Wait for pending flips to complete */
 726         armada_drm_plane_work_wait(drm_to_armada_plane(dcrtc->crtc.primary),
 727                                    MAX_SCHEDULE_TIMEOUT);
 728
 729         /* Take a reference to the new fb as we're using it */
 730         drm_framebuffer_reference(crtc->primary->fb);
 731
 732         /* Update the base in the CRTC */
 733         armada_drm_crtc_update_regs(dcrtc, regs);
 734
 735         /* Drop our previously held reference */
 736         armada_drm_crtc_finish_fb(dcrtc, old_fb, dpms_blanked(dcrtc->dpms));
 737
 738         return 0;
 739 }
 740
 741 void armada_drm_crtc_plane_disable(struct armada_crtc *dcrtc,
 742         struct drm_plane *plane)
 743 {
 744         u32 sram_para1, dma_ctrl0_mask;
 745
 746         /*
 747          * Drop our reference on any framebuffer attached to this plane.
 748          * We don't need to NULL this out as drm_plane_force_disable(),
 749          * and __setplane_internal() will do so for an overlay plane, and
 750          * __drm_helper_disable_unused_functions() will do so for the
 751          * primary plane.
 752          */
 753         if (plane->fb)
 754                 drm_framebuffer_unreference(plane->fb);
 755
 756         /* Power down the Y/U/V FIFOs */
 757         sram_para1 = CFG_PDWN16x66 | CFG_PDWN32x66;
 758
 759         /* Power down most RAMs and FIFOs if this is the primary plane */
 760         if (plane->type == DRM_PLANE_TYPE_PRIMARY) {
 761                 sram_para1 |= CFG_PDWN256x32 | CFG_PDWN256x24 | CFG_PDWN256x8 |
 762                               CFG_PDWN32x32 | CFG_PDWN64x66;
 763                 dma_ctrl0_mask = CFG_GRA_ENA;
 764         } else {
 765                 dma_ctrl0_mask = CFG_DMA_ENA;
 766         }
 767
 768         spin_lock_irq(&dcrtc->irq_lock);
 769         armada_updatel(0, dma_ctrl0_mask, dcrtc->base + LCD_SPU_DMA_CTRL0);
 770         spin_unlock_irq(&dcrtc->irq_lock);
 771
 772         armada_updatel(sram_para1, 0, dcrtc->base + LCD_SPU_SRAM_PARA1);
 773 }
 774
 775 /* The mode_config.mutex will be held for this call */
 776 static void armada_drm_crtc_disable(struct drm_crtc *crtc)
 777 {
 778         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 779
 780         armada_drm_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
 781         armada_drm_crtc_plane_disable(dcrtc, crtc->primary);
 782 }
 783
 784 static const struct drm_crtc_helper_funcs armada_crtc_helper_funcs = {
 785         .dpms           = armada_drm_crtc_dpms,
 786         .prepare        = armada_drm_crtc_prepare,
 787         .commit         = armada_drm_crtc_commit,
 788         .mode_fixup     = armada_drm_crtc_mode_fixup,
 789         .mode_set       = armada_drm_crtc_mode_set,
 790         .mode_set_base  = armada_drm_crtc_mode_set_base,
 791         .disable        = armada_drm_crtc_disable,
 792 };
 793
 794 static void armada_load_cursor_argb(void __iomem *base, uint32_t *pix,
 795         unsigned stride, unsigned width, unsigned height)
 796 {
 797         uint32_t addr;
 798         unsigned y;
 799
 800         addr = SRAM_HWC32_RAM1;
 801         for (y = 0; y < height; y++) {
 802                 uint32_t *p = &pix[y * stride];
 803                 unsigned x;
 804
 805                 for (x = 0; x < width; x++, p++) {
 806                         uint32_t val = *p;
 807
 808                         val = (val & 0xff00ff00) |
 809                               (val & 0x000000ff) << 16 |
 810                               (val & 0x00ff0000) >> 16;
 811
 812                         writel_relaxed(val,
 813                                        base + LCD_SPU_SRAM_WRDAT);
 814                         writel_relaxed(addr | SRAM_WRITE,
 815                                        base + LCD_SPU_SRAM_CTRL);
 816                         readl_relaxed(base + LCD_SPU_HWC_OVSA_HPXL_VLN);
 817                         addr += 1;
 818                         if ((addr & 0x00ff) == 0)
 819                                 addr += 0xf00;
 820                         if ((addr & 0x30ff) == 0)
 821                                 addr = SRAM_HWC32_RAM2;
 822                 }
 823         }
 824 }
 825
 826 static void armada_drm_crtc_cursor_tran(void __iomem *base)
 827 {
 828         unsigned addr;
 829
 830         for (addr = 0; addr < 256; addr++) {
 831                 /* write the default value */
 832                 writel_relaxed(0x55555555, base + LCD_SPU_SRAM_WRDAT);
 833                 writel_relaxed(addr | SRAM_WRITE | SRAM_HWC32_TRAN,
 834                                base + LCD_SPU_SRAM_CTRL);
 835         }
 836 }
 837
 838 static int armada_drm_crtc_cursor_update(struct armada_crtc *dcrtc, bool reload)
 839 {
 840         uint32_t xoff, xscr, w = dcrtc->cursor_w, s;
 841         uint32_t yoff, yscr, h = dcrtc->cursor_h;
 842         uint32_t para1;
 843
 844         /*
 845          * Calculate the visible width and height of the cursor,
 846          * screen position, and the position in the cursor bitmap.
 847          */
 848         if (dcrtc->cursor_x < 0) {
 849                 xoff = -dcrtc->cursor_x;
 850                 xscr = 0;
 851                 w -= min(xoff, w);
 852         } else if (dcrtc->cursor_x + w > dcrtc->crtc.mode.hdisplay) {
 853                 xoff = 0;
 854                 xscr = dcrtc->cursor_x;
 855                 w = max_t(int, dcrtc->crtc.mode.hdisplay - dcrtc->cursor_x, 0);
 856         } else {
 857                 xoff = 0;
 858                 xscr = dcrtc->cursor_x;
 859         }
 860
 861         if (dcrtc->cursor_y < 0) {
 862                 yoff = -dcrtc->cursor_y;
 863                 yscr = 0;
 864                 h -= min(yoff, h);
 865         } else if (dcrtc->cursor_y + h > dcrtc->crtc.mode.vdisplay) {
 866                 yoff = 0;
 867                 yscr = dcrtc->cursor_y;
 868                 h = max_t(int, dcrtc->crtc.mode.vdisplay - dcrtc->cursor_y, 0);
 869         } else {
 870                 yoff = 0;
 871                 yscr = dcrtc->cursor_y;
 872         }
 873
 874         /* On interlaced modes, the vertical cursor size must be halved */
 875         s = dcrtc->cursor_w;
 876         if (dcrtc->interlaced) {
 877                 s *= 2;
 878                 yscr /= 2;
 879                 h /= 2;
 880         }
 881
 882         if (!dcrtc->cursor_obj || !h || !w) {
 883                 spin_lock_irq(&dcrtc->irq_lock);
 884                 armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
 885                 dcrtc->cursor_update = false;
 886                 armada_updatel(0, CFG_HWC_ENA, dcrtc->base + LCD_SPU_DMA_CTRL0);
 887                 spin_unlock_irq(&dcrtc->irq_lock);
 888                 return 0;
 889         }
 890
 891         para1 = readl_relaxed(dcrtc->base + LCD_SPU_SRAM_PARA1);
 892         armada_updatel(CFG_CSB_256x32, CFG_CSB_256x32 | CFG_PDWN256x32,
 893                        dcrtc->base + LCD_SPU_SRAM_PARA1);
 894
 895         /*
 896          * Initialize the transparency if the SRAM was powered down.
 897          * We must also reload the cursor data as well.
 898          */
 899         if (!(para1 & CFG_CSB_256x32)) {
 900                 armada_drm_crtc_cursor_tran(dcrtc->base);
 901                 reload = true;
 902         }
 903
 904         if (dcrtc->cursor_hw_sz != (h << 16 | w)) {
 905                 spin_lock_irq(&dcrtc->irq_lock);
 906                 armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
 907                 dcrtc->cursor_update = false;
 908                 armada_updatel(0, CFG_HWC_ENA, dcrtc->base + LCD_SPU_DMA_CTRL0);
 909                 spin_unlock_irq(&dcrtc->irq_lock);
 910                 reload = true;
 911         }
 912         if (reload) {
 913                 struct armada_gem_object *obj = dcrtc->cursor_obj;
 914                 uint32_t *pix;
 915                 /* Set the top-left corner of the cursor image */
 916                 pix = obj->addr;
 917                 pix += yoff * s + xoff;
 918                 armada_load_cursor_argb(dcrtc->base, pix, s, w, h);
 919         }
 920
 921         /* Reload the cursor position, size and enable in the IRQ handler */
 922         spin_lock_irq(&dcrtc->irq_lock);
 923         dcrtc->cursor_hw_pos = yscr << 16 | xscr;
 924         dcrtc->cursor_hw_sz = h << 16 | w;
 925         dcrtc->cursor_update = true;
 926         armada_drm_crtc_enable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
 927         spin_unlock_irq(&dcrtc->irq_lock);
 928
 929         return 0;
 930 }
 931
 932 static void cursor_update(void *data)
 933 {
 934         armada_drm_crtc_cursor_update(data, true);
 935 }
 936
 937 static int armada_drm_crtc_cursor_set(struct drm_crtc *crtc,
 938         struct drm_file *file, uint32_t handle, uint32_t w, uint32_t h)
 939 {
 940         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 941         struct armada_gem_object *obj = NULL;
 942         int ret;
 943
 944         /* If no cursor support, replicate drm's return value */
 945         if (!dcrtc->variant->has_spu_adv_reg)
 946                 return -ENXIO;
 947
 948         if (handle && w > 0 && h > 0) {
 949                 /* maximum size is 64x32 or 32x64 */
 950                 if (w > 64 || h > 64 || (w > 32 && h > 32))
 951                         return -ENOMEM;
 952
 953                 obj = armada_gem_object_lookup(file, handle);
 954                 if (!obj)
 955                         return -ENOENT;
 956
 957                 /* Must be a kernel-mapped object */
 958                 if (!obj->addr) {
 959                         drm_gem_object_unreference_unlocked(&obj->obj);
 960                         return -EINVAL;
 961                 }
 962
 963                 if (obj->obj.size < w * h * 4) {
 964                         DRM_ERROR("buffer is too small\n");
 965                         drm_gem_object_unreference_unlocked(&obj->obj);
 966                         return -ENOMEM;
 967                 }
 968         }
 969
 970         if (dcrtc->cursor_obj) {
 971                 dcrtc->cursor_obj->update = NULL;
 972                 dcrtc->cursor_obj->update_data = NULL;
 973                 drm_gem_object_unreference_unlocked(&dcrtc->cursor_obj->obj);
 974         }
 975         dcrtc->cursor_obj = obj;
 976         dcrtc->cursor_w = w;
 977         dcrtc->cursor_h = h;
 978         ret = armada_drm_crtc_cursor_update(dcrtc, true);
 979         if (obj) {
 980                 obj->update_data = dcrtc;
 981                 obj->update = cursor_update;
 982         }
 983
 984         return ret;
 985 }
 986
 987 static int armada_drm_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
 988 {
 989         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 990         int ret;
 991
 992         /* If no cursor support, replicate drm's return value */
 993         if (!dcrtc->variant->has_spu_adv_reg)
 994                 return -EFAULT;
 995
 996         dcrtc->cursor_x = x;
 997         dcrtc->cursor_y = y;
 998         ret = armada_drm_crtc_cursor_update(dcrtc, false);
 999
1000         return ret;
1001 }
1002
1003 static void armada_drm_crtc_destroy(struct drm_crtc *crtc)
1004 {
1005         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
1006         struct armada_private *priv = crtc->dev->dev_private;
1007
1008         if (dcrtc->cursor_obj)
1009                 drm_gem_object_unreference_unlocked(&dcrtc->cursor_obj->obj);
1010
1011         priv->dcrtc[dcrtc->num] = NULL;
1012         drm_crtc_cleanup(&dcrtc->crtc);
1013
1014         if (!IS_ERR(dcrtc->clk))
1015                 clk_disable_unprepare(dcrtc->clk);
1016
1017         writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ENA);
1018
1019         of_node_put(dcrtc->crtc.port);
1020
1021         kfree(dcrtc);
1022 }
1023
1024 /*
1025  * The mode_config lock is held here, to prevent races between this
1026  * and a mode_set.
1027  */
1028 static int armada_drm_crtc_page_flip(struct drm_crtc *crtc,
1029         struct drm_framebuffer *fb, struct drm_pending_vblank_event *event, uint32_t page_flip_flags)
1030 {
1031         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
1032         struct armada_frame_work *work;
1033         unsigned i;
1034         int ret;
1035
1036         /* We don't support changing the pixel format */
1037         if (fb->pixel_format != crtc->primary->fb->pixel_format)
1038                 return -EINVAL;
1039
1040         work = kmalloc(sizeof(*work), GFP_KERNEL);
1041         if (!work)
1042                 return -ENOMEM;
1043
1044         work->work.fn = armada_drm_crtc_complete_frame_work;
1045         work->event = event;
1046         work->old_fb = dcrtc->crtc.primary->fb;
1047
1048         i = armada_drm_crtc_calc_fb(fb, crtc->x, crtc->y, work->regs,
1049                                     dcrtc->interlaced);
1050         armada_reg_queue_end(work->regs, i);
1051
1052         /*
1053          * Ensure that we hold a reference on the new framebuffer.
1054          * This has to match the behaviour in mode_set.
1055          */
1056         drm_framebuffer_reference(fb);
1057
1058         ret = armada_drm_crtc_queue_frame_work(dcrtc, work);
1059         if (ret) {
1060                 /* Undo our reference above */
1061                 drm_framebuffer_unreference(fb);
1062                 kfree(work);
1063                 return ret;
1064         }
1065
1066         /*
1067          * Don't take a reference on the new framebuffer;
1068          * drm_mode_page_flip_ioctl() has already grabbed a reference and
1069          * will _not_ drop that reference on successful return from this
1070          * function.  Simply mark this new framebuffer as the current one.
1071          */
1072         dcrtc->crtc.primary->fb = fb;
1073
1074         /*
1075          * Finally, if the display is blanked, we won't receive an
1076          * interrupt, so complete it now.
1077          */
1078         if (dpms_blanked(dcrtc->dpms))
1079                 armada_drm_plane_work_run(dcrtc, dcrtc->crtc.primary);
1080
1081         return 0;
1082 }
1083
1084 static int
1085 armada_drm_crtc_set_property(struct drm_crtc *crtc,
1086         struct drm_property *property, uint64_t val)
1087 {
1088         struct armada_private *priv = crtc->dev->dev_private;
1089         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
1090         bool update_csc = false;
1091
1092         if (property == priv->csc_yuv_prop) {
1093                 dcrtc->csc_yuv_mode = val;
1094                 update_csc = true;
1095         } else if (property == priv->csc_rgb_prop) {
1096                 dcrtc->csc_rgb_mode = val;
1097                 update_csc = true;
1098         }
1099
1100         if (update_csc) {
1101                 uint32_t val;
1102
1103                 val = dcrtc->spu_iopad_ctrl |
1104                       armada_drm_crtc_calculate_csc(dcrtc);
1105                 writel_relaxed(val, dcrtc->base + LCD_SPU_IOPAD_CONTROL);
1106         }
1107
1108         return 0;
1109 }
1110
1111 static const struct drm_crtc_funcs armada_crtc_funcs = {
1112         .cursor_set     = armada_drm_crtc_cursor_set,
1113         .cursor_move    = armada_drm_crtc_cursor_move,
1114         .destroy        = armada_drm_crtc_destroy,
1115         .set_config     = drm_crtc_helper_set_config,
1116         .page_flip      = armada_drm_crtc_page_flip,
1117         .set_property   = armada_drm_crtc_set_property,
1118 };
1119
1120 static const struct drm_plane_funcs armada_primary_plane_funcs = {
1121         .update_plane   = drm_primary_helper_update,
1122         .disable_plane  = drm_primary_helper_disable,
1123         .destroy        = drm_primary_helper_destroy,
1124 };
1125
1126 int armada_drm_plane_init(struct armada_plane *plane)
1127 {
1128         init_waitqueue_head(&plane->frame_wait);
1129
1130         return 0;
1131 }
1132
1133 static struct drm_prop_enum_list armada_drm_csc_yuv_enum_list[] = {
1134         { CSC_AUTO,        "Auto" },
1135         { CSC_YUV_CCIR601, "CCIR601" },
1136         { CSC_YUV_CCIR709, "CCIR709" },
1137 };
1138
1139 static struct drm_prop_enum_list armada_drm_csc_rgb_enum_list[] = {
1140         { CSC_AUTO,         "Auto" },
1141         { CSC_RGB_COMPUTER, "Computer system" },
1142         { CSC_RGB_STUDIO,   "Studio" },
1143 };
1144
1145 static int armada_drm_crtc_create_properties(struct drm_device *dev)
1146 {
1147         struct armada_private *priv = dev->dev_private;
1148
1149         if (priv->csc_yuv_prop)
1150                 return 0;
1151
1152         priv->csc_yuv_prop = drm_property_create_enum(dev, 0,
1153                                 "CSC_YUV", armada_drm_csc_yuv_enum_list,
1154                                 ARRAY_SIZE(armada_drm_csc_yuv_enum_list));
1155         priv->csc_rgb_prop = drm_property_create_enum(dev, 0,
1156                                 "CSC_RGB", armada_drm_csc_rgb_enum_list,
1157                                 ARRAY_SIZE(armada_drm_csc_rgb_enum_list));
1158
1159         if (!priv->csc_yuv_prop || !priv->csc_rgb_prop)
1160                 return -ENOMEM;
1161
1162         return 0;
1163 }
1164
1165 static int armada_drm_crtc_create(struct drm_device *drm, struct device *dev,
1166         struct resource *res, int irq, const struct armada_variant *variant,
1167         struct device_node *port)
1168 {
1169         struct armada_private *priv = drm->dev_private;
1170         struct armada_crtc *dcrtc;
1171         struct armada_plane *primary;
1172         void __iomem *base;
1173         int ret;
1174
1175         ret = armada_drm_crtc_create_properties(drm);
1176         if (ret)
1177                 return ret;
1178
1179         base = devm_ioremap_resource(dev, res);
1180         if (IS_ERR(base))
1181                 return PTR_ERR(base);
1182
1183         dcrtc = kzalloc(sizeof(*dcrtc), GFP_KERNEL);
1184         if (!dcrtc) {
1185                 DRM_ERROR("failed to allocate Armada crtc\n");
1186                 return -ENOMEM;
1187         }
1188
1189         if (dev != drm->dev)
1190                 dev_set_drvdata(dev, dcrtc);
1191
1192         dcrtc->variant = variant;
1193         dcrtc->base = base;
1194         dcrtc->num = drm->mode_config.num_crtc;
1195         dcrtc->clk = ERR_PTR(-EINVAL);
1196         dcrtc->csc_yuv_mode = CSC_AUTO;
1197         dcrtc->csc_rgb_mode = CSC_AUTO;
1198         dcrtc->cfg_dumb_ctrl = DUMB24_RGB888_0;
1199         dcrtc->spu_iopad_ctrl = CFG_VSCALE_LN_EN | CFG_IOPAD_DUMB24;
1200         spin_lock_init(&dcrtc->irq_lock);
1201         dcrtc->irq_ena = CLEAN_SPU_IRQ_ISR;
1202
1203         /* Initialize some registers which we don't otherwise set */
1204         writel_relaxed(0x00000001, dcrtc->base + LCD_CFG_SCLK_DIV);
1205         writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_BLANKCOLOR);
1206         writel_relaxed(dcrtc->spu_iopad_ctrl,
1207                        dcrtc->base + LCD_SPU_IOPAD_CONTROL);
1208         writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_SRAM_PARA0);
1209         writel_relaxed(CFG_PDWN256x32 | CFG_PDWN256x24 | CFG_PDWN256x8 |
1210                        CFG_PDWN32x32 | CFG_PDWN16x66 | CFG_PDWN32x66 |
1211                        CFG_PDWN64x66, dcrtc->base + LCD_SPU_SRAM_PARA1);
1212         writel_relaxed(0x2032ff81, dcrtc->base + LCD_SPU_DMA_CTRL1);
1213         writel_relaxed(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA);
1214         writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ISR);
1215
1216         ret = devm_request_irq(dev, irq, armada_drm_irq, 0, "armada_drm_crtc",
1217                                dcrtc);
1218         if (ret < 0) {
1219                 kfree(dcrtc);
1220                 return ret;
1221         }
1222
1223         if (dcrtc->variant->init) {
1224                 ret = dcrtc->variant->init(dcrtc, dev);
1225                 if (ret) {
1226                         kfree(dcrtc);
1227                         return ret;
1228                 }
1229         }
1230
1231         /* Ensure AXI pipeline is enabled */
1232         armada_updatel(CFG_ARBFAST_ENA, 0, dcrtc->base + LCD_SPU_DMA_CTRL0);
1233
1234         priv->dcrtc[dcrtc->num] = dcrtc;
1235
1236         dcrtc->crtc.port = port;
1237
1238         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
1239         if (!primary)
1240                 return -ENOMEM;
1241
1242         ret = armada_drm_plane_init(primary);
1243         if (ret) {
1244                 kfree(primary);
1245                 return ret;
1246         }
1247
1248         ret = drm_universal_plane_init(drm, &primary->base, 0,
1249                                        &armada_primary_plane_funcs,
1250                                        armada_primary_formats,
1251                                        ARRAY_SIZE(armada_primary_formats),
1252                                        DRM_PLANE_TYPE_PRIMARY, NULL);
1253         if (ret) {
1254                 kfree(primary);
1255                 return ret;
1256         }
1257
1258         ret = drm_crtc_init_with_planes(drm, &dcrtc->crtc, &primary->base, NULL,
1259                                         &armada_crtc_funcs, NULL);
1260         if (ret)
1261                 goto err_crtc_init;
1262
1263         drm_crtc_helper_add(&dcrtc->crtc, &armada_crtc_helper_funcs);
1264
1265         drm_object_attach_property(&dcrtc->crtc.base, priv->csc_yuv_prop,
1266                                    dcrtc->csc_yuv_mode);
1267         drm_object_attach_property(&dcrtc->crtc.base, priv->csc_rgb_prop,
1268                                    dcrtc->csc_rgb_mode);
1269
1270         return armada_overlay_plane_create(drm, 1 << dcrtc->num);
1271
1272 err_crtc_init:
1273         primary->base.funcs->destroy(&primary->base);
1274         return ret;
1275 }
1276
1277 static int
1278 armada_lcd_bind(struct device *dev, struct device *master, void *data)
1279 {
1280         struct platform_device *pdev = to_platform_device(dev);
1281         struct drm_device *drm = data;
1282         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1283         int irq = platform_get_irq(pdev, 0);
1284         const struct armada_variant *variant;
1285         struct device_node *port = NULL;
1286
1287         if (irq < 0)
1288                 return irq;
1289
1290         if (!dev->of_node) {
1291                 const struct platform_device_id *id;
1292
1293                 id = platform_get_device_id(pdev);
1294                 if (!id)
1295                         return -ENXIO;
1296
1297                 variant = (const struct armada_variant *)id->driver_data;
1298         } else {
1299                 const struct of_device_id *match;
1300                 struct device_node *np, *parent = dev->of_node;
1301
1302                 match = of_match_device(dev->driver->of_match_table, dev);
1303                 if (!match)
1304                         return -ENXIO;
1305
1306                 np = of_get_child_by_name(parent, "ports");
1307                 if (np)
1308                         parent = np;
1309                 port = of_get_child_by_name(parent, "port");
1310                 of_node_put(np);
1311                 if (!port) {
1312                         dev_err(dev, "no port node found in %s\n",
1313                                 parent->full_name);
1314                         return -ENXIO;
1315                 }
1316
1317                 variant = match->data;
1318         }
1319
1320         return armada_drm_crtc_create(drm, dev, res, irq, variant, port);
1321 }
1322
1323 static void
1324 armada_lcd_unbind(struct device *dev, struct device *master, void *data)
1325 {
1326         struct armada_crtc *dcrtc = dev_get_drvdata(dev);
1327
1328         armada_drm_crtc_destroy(&dcrtc->crtc);
1329 }
1330
1331 static const struct component_ops armada_lcd_ops = {
1332         .bind = armada_lcd_bind,
1333         .unbind = armada_lcd_unbind,
1334 };
1335
1336 static int armada_lcd_probe(struct platform_device *pdev)
1337 {
1338         return component_add(&pdev->dev, &armada_lcd_ops);
1339 }
1340
1341 static int armada_lcd_remove(struct platform_device *pdev)
1342 {
1343         component_del(&pdev->dev, &armada_lcd_ops);
1344         return 0;
1345 }
1346
1347 static struct of_device_id armada_lcd_of_match[] = {
1348         {
1349                 .compatible     = "marvell,dove-lcd",
1350                 .data           = &armada510_ops,
1351         },
1352         {}
1353 };
1354 MODULE_DEVICE_TABLE(of, armada_lcd_of_match);
1355
1356 static const struct platform_device_id armada_lcd_platform_ids[] = {
1357         {
1358                 .name           = "armada-lcd",
1359                 .driver_data    = (unsigned long)&armada510_ops,
1360         }, {
1361                 .name           = "armada-510-lcd",
1362                 .driver_data    = (unsigned long)&armada510_ops,
1363         },
1364         { },
1365 };
1366 MODULE_DEVICE_TABLE(platform, armada_lcd_platform_ids);
1367
1368 struct platform_driver armada_lcd_platform_driver = {
1369         .probe  = armada_lcd_probe,
1370         .remove = armada_lcd_remove,
1371         .driver = {
1372                 .name   = "armada-lcd",
1373                 .owner  =  THIS_MODULE,
1374                 .of_match_table = armada_lcd_of_match,
1375         },
1376         .id_table = armada_lcd_platform_ids,
1377 };