2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/swap.h>
35 #include <linux/pci.h>
37 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
39 static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
40 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
41 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
42 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
44 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
47 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
48 static int i915_gem_object_wait_rendering(struct drm_gem_object *obj);
49 static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
51 static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
52 static int i915_gem_evict_something(struct drm_device *dev, int min_size);
53 static int i915_gem_evict_from_inactive_list(struct drm_device *dev);
54 static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
55 struct drm_i915_gem_pwrite *args,
56 struct drm_file *file_priv);
58 static LIST_HEAD(shrink_list);
59 static DEFINE_SPINLOCK(shrink_list_lock);
61 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
64 drm_i915_private_t *dev_priv = dev->dev_private;
67 (start & (PAGE_SIZE - 1)) != 0 ||
68 (end & (PAGE_SIZE - 1)) != 0) {
72 drm_mm_init(&dev_priv->mm.gtt_space, start,
75 dev->gtt_total = (uint32_t) (end - start);
81 i915_gem_init_ioctl(struct drm_device *dev, void *data,
82 struct drm_file *file_priv)
84 struct drm_i915_gem_init *args = data;
87 mutex_lock(&dev->struct_mutex);
88 ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end);
89 mutex_unlock(&dev->struct_mutex);
95 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
96 struct drm_file *file_priv)
98 struct drm_i915_gem_get_aperture *args = data;
100 if (!(dev->driver->driver_features & DRIVER_GEM))
103 args->aper_size = dev->gtt_total;
104 args->aper_available_size = (args->aper_size -
105 atomic_read(&dev->pin_memory));
112 * Creates a new mm object and returns a handle to it.
115 i915_gem_create_ioctl(struct drm_device *dev, void *data,
116 struct drm_file *file_priv)
118 struct drm_i915_gem_create *args = data;
119 struct drm_gem_object *obj;
123 args->size = roundup(args->size, PAGE_SIZE);
125 /* Allocate the new object */
126 obj = drm_gem_object_alloc(dev, args->size);
130 ret = drm_gem_handle_create(file_priv, obj, &handle);
131 mutex_lock(&dev->struct_mutex);
132 drm_gem_object_handle_unreference(obj);
133 mutex_unlock(&dev->struct_mutex);
138 args->handle = handle;
144 fast_shmem_read(struct page **pages,
145 loff_t page_base, int page_offset,
152 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
155 unwritten = __copy_to_user_inatomic(data, vaddr + page_offset, length);
156 kunmap_atomic(vaddr, KM_USER0);
164 static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj)
166 drm_i915_private_t *dev_priv = obj->dev->dev_private;
167 struct drm_i915_gem_object *obj_priv = obj->driver_private;
169 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
170 obj_priv->tiling_mode != I915_TILING_NONE;
174 slow_shmem_copy(struct page *dst_page,
176 struct page *src_page,
180 char *dst_vaddr, *src_vaddr;
182 dst_vaddr = kmap_atomic(dst_page, KM_USER0);
183 if (dst_vaddr == NULL)
186 src_vaddr = kmap_atomic(src_page, KM_USER1);
187 if (src_vaddr == NULL) {
188 kunmap_atomic(dst_vaddr, KM_USER0);
192 memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
194 kunmap_atomic(src_vaddr, KM_USER1);
195 kunmap_atomic(dst_vaddr, KM_USER0);
201 slow_shmem_bit17_copy(struct page *gpu_page,
203 struct page *cpu_page,
208 char *gpu_vaddr, *cpu_vaddr;
210 /* Use the unswizzled path if this page isn't affected. */
211 if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
213 return slow_shmem_copy(cpu_page, cpu_offset,
214 gpu_page, gpu_offset, length);
216 return slow_shmem_copy(gpu_page, gpu_offset,
217 cpu_page, cpu_offset, length);
220 gpu_vaddr = kmap_atomic(gpu_page, KM_USER0);
221 if (gpu_vaddr == NULL)
224 cpu_vaddr = kmap_atomic(cpu_page, KM_USER1);
225 if (cpu_vaddr == NULL) {
226 kunmap_atomic(gpu_vaddr, KM_USER0);
230 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
231 * XORing with the other bits (A9 for Y, A9 and A10 for X)
234 int cacheline_end = ALIGN(gpu_offset + 1, 64);
235 int this_length = min(cacheline_end - gpu_offset, length);
236 int swizzled_gpu_offset = gpu_offset ^ 64;
239 memcpy(cpu_vaddr + cpu_offset,
240 gpu_vaddr + swizzled_gpu_offset,
243 memcpy(gpu_vaddr + swizzled_gpu_offset,
244 cpu_vaddr + cpu_offset,
247 cpu_offset += this_length;
248 gpu_offset += this_length;
249 length -= this_length;
252 kunmap_atomic(cpu_vaddr, KM_USER1);
253 kunmap_atomic(gpu_vaddr, KM_USER0);
259 * This is the fast shmem pread path, which attempts to copy_from_user directly
260 * from the backing pages of the object to the user's address space. On a
261 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
264 i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj,
265 struct drm_i915_gem_pread *args,
266 struct drm_file *file_priv)
268 struct drm_i915_gem_object *obj_priv = obj->driver_private;
270 loff_t offset, page_base;
271 char __user *user_data;
272 int page_offset, page_length;
275 user_data = (char __user *) (uintptr_t) args->data_ptr;
278 mutex_lock(&dev->struct_mutex);
280 ret = i915_gem_object_get_pages(obj, 0);
284 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
289 obj_priv = obj->driver_private;
290 offset = args->offset;
293 /* Operation in this page
295 * page_base = page offset within aperture
296 * page_offset = offset within page
297 * page_length = bytes to copy for this page
299 page_base = (offset & ~(PAGE_SIZE-1));
300 page_offset = offset & (PAGE_SIZE-1);
301 page_length = remain;
302 if ((page_offset + remain) > PAGE_SIZE)
303 page_length = PAGE_SIZE - page_offset;
305 ret = fast_shmem_read(obj_priv->pages,
306 page_base, page_offset,
307 user_data, page_length);
311 remain -= page_length;
312 user_data += page_length;
313 offset += page_length;
317 i915_gem_object_put_pages(obj);
319 mutex_unlock(&dev->struct_mutex);
325 i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj)
329 ret = i915_gem_object_get_pages(obj, __GFP_NORETRY | __GFP_NOWARN);
331 /* If we've insufficient memory to map in the pages, attempt
332 * to make some space by throwing out some old buffers.
334 if (ret == -ENOMEM) {
335 struct drm_device *dev = obj->dev;
337 ret = i915_gem_evict_something(dev, obj->size);
341 ret = i915_gem_object_get_pages(obj, 0);
348 * This is the fallback shmem pread path, which allocates temporary storage
349 * in kernel space to copy_to_user into outside of the struct_mutex, so we
350 * can copy out of the object's backing pages while holding the struct mutex
351 * and not take page faults.
354 i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj,
355 struct drm_i915_gem_pread *args,
356 struct drm_file *file_priv)
358 struct drm_i915_gem_object *obj_priv = obj->driver_private;
359 struct mm_struct *mm = current->mm;
360 struct page **user_pages;
362 loff_t offset, pinned_pages, i;
363 loff_t first_data_page, last_data_page, num_pages;
364 int shmem_page_index, shmem_page_offset;
365 int data_page_index, data_page_offset;
368 uint64_t data_ptr = args->data_ptr;
369 int do_bit17_swizzling;
373 /* Pin the user pages containing the data. We can't fault while
374 * holding the struct mutex, yet we want to hold it while
375 * dereferencing the user data.
377 first_data_page = data_ptr / PAGE_SIZE;
378 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
379 num_pages = last_data_page - first_data_page + 1;
381 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
382 if (user_pages == NULL)
385 down_read(&mm->mmap_sem);
386 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
387 num_pages, 1, 0, user_pages, NULL);
388 up_read(&mm->mmap_sem);
389 if (pinned_pages < num_pages) {
391 goto fail_put_user_pages;
394 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
396 mutex_lock(&dev->struct_mutex);
398 ret = i915_gem_object_get_pages_or_evict(obj);
402 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
407 obj_priv = obj->driver_private;
408 offset = args->offset;
411 /* Operation in this page
413 * shmem_page_index = page number within shmem file
414 * shmem_page_offset = offset within page in shmem file
415 * data_page_index = page number in get_user_pages return
416 * data_page_offset = offset with data_page_index page.
417 * page_length = bytes to copy for this page
419 shmem_page_index = offset / PAGE_SIZE;
420 shmem_page_offset = offset & ~PAGE_MASK;
421 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
422 data_page_offset = data_ptr & ~PAGE_MASK;
424 page_length = remain;
425 if ((shmem_page_offset + page_length) > PAGE_SIZE)
426 page_length = PAGE_SIZE - shmem_page_offset;
427 if ((data_page_offset + page_length) > PAGE_SIZE)
428 page_length = PAGE_SIZE - data_page_offset;
430 if (do_bit17_swizzling) {
431 ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
433 user_pages[data_page_index],
438 ret = slow_shmem_copy(user_pages[data_page_index],
440 obj_priv->pages[shmem_page_index],
447 remain -= page_length;
448 data_ptr += page_length;
449 offset += page_length;
453 i915_gem_object_put_pages(obj);
455 mutex_unlock(&dev->struct_mutex);
457 for (i = 0; i < pinned_pages; i++) {
458 SetPageDirty(user_pages[i]);
459 page_cache_release(user_pages[i]);
461 drm_free_large(user_pages);
467 * Reads data from the object referenced by handle.
469 * On error, the contents of *data are undefined.
472 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
473 struct drm_file *file_priv)
475 struct drm_i915_gem_pread *args = data;
476 struct drm_gem_object *obj;
477 struct drm_i915_gem_object *obj_priv;
480 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
483 obj_priv = obj->driver_private;
485 /* Bounds check source.
487 * XXX: This could use review for overflow issues...
489 if (args->offset > obj->size || args->size > obj->size ||
490 args->offset + args->size > obj->size) {
491 drm_gem_object_unreference(obj);
495 if (i915_gem_object_needs_bit17_swizzle(obj)) {
496 ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv);
498 ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv);
500 ret = i915_gem_shmem_pread_slow(dev, obj, args,
504 drm_gem_object_unreference(obj);
509 /* This is the fast write path which cannot handle
510 * page faults in the source data
514 fast_user_write(struct io_mapping *mapping,
515 loff_t page_base, int page_offset,
516 char __user *user_data,
520 unsigned long unwritten;
522 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
523 unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
525 io_mapping_unmap_atomic(vaddr_atomic);
531 /* Here's the write path which can sleep for
536 slow_kernel_write(struct io_mapping *mapping,
537 loff_t gtt_base, int gtt_offset,
538 struct page *user_page, int user_offset,
541 char *src_vaddr, *dst_vaddr;
542 unsigned long unwritten;
544 dst_vaddr = io_mapping_map_atomic_wc(mapping, gtt_base);
545 src_vaddr = kmap_atomic(user_page, KM_USER1);
546 unwritten = __copy_from_user_inatomic_nocache(dst_vaddr + gtt_offset,
547 src_vaddr + user_offset,
549 kunmap_atomic(src_vaddr, KM_USER1);
550 io_mapping_unmap_atomic(dst_vaddr);
557 fast_shmem_write(struct page **pages,
558 loff_t page_base, int page_offset,
563 unsigned long unwritten;
565 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
568 unwritten = __copy_from_user_inatomic(vaddr + page_offset, data, length);
569 kunmap_atomic(vaddr, KM_USER0);
577 * This is the fast pwrite path, where we copy the data directly from the
578 * user into the GTT, uncached.
581 i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
582 struct drm_i915_gem_pwrite *args,
583 struct drm_file *file_priv)
585 struct drm_i915_gem_object *obj_priv = obj->driver_private;
586 drm_i915_private_t *dev_priv = dev->dev_private;
588 loff_t offset, page_base;
589 char __user *user_data;
590 int page_offset, page_length;
593 user_data = (char __user *) (uintptr_t) args->data_ptr;
595 if (!access_ok(VERIFY_READ, user_data, remain))
599 mutex_lock(&dev->struct_mutex);
600 ret = i915_gem_object_pin(obj, 0);
602 mutex_unlock(&dev->struct_mutex);
605 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
609 obj_priv = obj->driver_private;
610 offset = obj_priv->gtt_offset + args->offset;
613 /* Operation in this page
615 * page_base = page offset within aperture
616 * page_offset = offset within page
617 * page_length = bytes to copy for this page
619 page_base = (offset & ~(PAGE_SIZE-1));
620 page_offset = offset & (PAGE_SIZE-1);
621 page_length = remain;
622 if ((page_offset + remain) > PAGE_SIZE)
623 page_length = PAGE_SIZE - page_offset;
625 ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base,
626 page_offset, user_data, page_length);
628 /* If we get a fault while copying data, then (presumably) our
629 * source page isn't available. Return the error and we'll
630 * retry in the slow path.
635 remain -= page_length;
636 user_data += page_length;
637 offset += page_length;
641 i915_gem_object_unpin(obj);
642 mutex_unlock(&dev->struct_mutex);
648 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
649 * the memory and maps it using kmap_atomic for copying.
651 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
652 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
655 i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
656 struct drm_i915_gem_pwrite *args,
657 struct drm_file *file_priv)
659 struct drm_i915_gem_object *obj_priv = obj->driver_private;
660 drm_i915_private_t *dev_priv = dev->dev_private;
662 loff_t gtt_page_base, offset;
663 loff_t first_data_page, last_data_page, num_pages;
664 loff_t pinned_pages, i;
665 struct page **user_pages;
666 struct mm_struct *mm = current->mm;
667 int gtt_page_offset, data_page_offset, data_page_index, page_length;
669 uint64_t data_ptr = args->data_ptr;
673 /* Pin the user pages containing the data. We can't fault while
674 * holding the struct mutex, and all of the pwrite implementations
675 * want to hold it while dereferencing the user data.
677 first_data_page = data_ptr / PAGE_SIZE;
678 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
679 num_pages = last_data_page - first_data_page + 1;
681 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
682 if (user_pages == NULL)
685 down_read(&mm->mmap_sem);
686 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
687 num_pages, 0, 0, user_pages, NULL);
688 up_read(&mm->mmap_sem);
689 if (pinned_pages < num_pages) {
691 goto out_unpin_pages;
694 mutex_lock(&dev->struct_mutex);
695 ret = i915_gem_object_pin(obj, 0);
699 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
701 goto out_unpin_object;
703 obj_priv = obj->driver_private;
704 offset = obj_priv->gtt_offset + args->offset;
707 /* Operation in this page
709 * gtt_page_base = page offset within aperture
710 * gtt_page_offset = offset within page in aperture
711 * data_page_index = page number in get_user_pages return
712 * data_page_offset = offset with data_page_index page.
713 * page_length = bytes to copy for this page
715 gtt_page_base = offset & PAGE_MASK;
716 gtt_page_offset = offset & ~PAGE_MASK;
717 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
718 data_page_offset = data_ptr & ~PAGE_MASK;
720 page_length = remain;
721 if ((gtt_page_offset + page_length) > PAGE_SIZE)
722 page_length = PAGE_SIZE - gtt_page_offset;
723 if ((data_page_offset + page_length) > PAGE_SIZE)
724 page_length = PAGE_SIZE - data_page_offset;
726 ret = slow_kernel_write(dev_priv->mm.gtt_mapping,
727 gtt_page_base, gtt_page_offset,
728 user_pages[data_page_index],
732 /* If we get a fault while copying data, then (presumably) our
733 * source page isn't available. Return the error and we'll
734 * retry in the slow path.
737 goto out_unpin_object;
739 remain -= page_length;
740 offset += page_length;
741 data_ptr += page_length;
745 i915_gem_object_unpin(obj);
747 mutex_unlock(&dev->struct_mutex);
749 for (i = 0; i < pinned_pages; i++)
750 page_cache_release(user_pages[i]);
751 drm_free_large(user_pages);
757 * This is the fast shmem pwrite path, which attempts to directly
758 * copy_from_user into the kmapped pages backing the object.
761 i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
762 struct drm_i915_gem_pwrite *args,
763 struct drm_file *file_priv)
765 struct drm_i915_gem_object *obj_priv = obj->driver_private;
767 loff_t offset, page_base;
768 char __user *user_data;
769 int page_offset, page_length;
772 user_data = (char __user *) (uintptr_t) args->data_ptr;
775 mutex_lock(&dev->struct_mutex);
777 ret = i915_gem_object_get_pages(obj, 0);
781 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
785 obj_priv = obj->driver_private;
786 offset = args->offset;
790 /* Operation in this page
792 * page_base = page offset within aperture
793 * page_offset = offset within page
794 * page_length = bytes to copy for this page
796 page_base = (offset & ~(PAGE_SIZE-1));
797 page_offset = offset & (PAGE_SIZE-1);
798 page_length = remain;
799 if ((page_offset + remain) > PAGE_SIZE)
800 page_length = PAGE_SIZE - page_offset;
802 ret = fast_shmem_write(obj_priv->pages,
803 page_base, page_offset,
804 user_data, page_length);
808 remain -= page_length;
809 user_data += page_length;
810 offset += page_length;
814 i915_gem_object_put_pages(obj);
816 mutex_unlock(&dev->struct_mutex);
822 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
823 * the memory and maps it using kmap_atomic for copying.
825 * This avoids taking mmap_sem for faulting on the user's address while the
826 * struct_mutex is held.
829 i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
830 struct drm_i915_gem_pwrite *args,
831 struct drm_file *file_priv)
833 struct drm_i915_gem_object *obj_priv = obj->driver_private;
834 struct mm_struct *mm = current->mm;
835 struct page **user_pages;
837 loff_t offset, pinned_pages, i;
838 loff_t first_data_page, last_data_page, num_pages;
839 int shmem_page_index, shmem_page_offset;
840 int data_page_index, data_page_offset;
843 uint64_t data_ptr = args->data_ptr;
844 int do_bit17_swizzling;
848 /* Pin the user pages containing the data. We can't fault while
849 * holding the struct mutex, and all of the pwrite implementations
850 * want to hold it while dereferencing the user data.
852 first_data_page = data_ptr / PAGE_SIZE;
853 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
854 num_pages = last_data_page - first_data_page + 1;
856 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
857 if (user_pages == NULL)
860 down_read(&mm->mmap_sem);
861 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
862 num_pages, 0, 0, user_pages, NULL);
863 up_read(&mm->mmap_sem);
864 if (pinned_pages < num_pages) {
866 goto fail_put_user_pages;
869 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
871 mutex_lock(&dev->struct_mutex);
873 ret = i915_gem_object_get_pages_or_evict(obj);
877 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
881 obj_priv = obj->driver_private;
882 offset = args->offset;
886 /* Operation in this page
888 * shmem_page_index = page number within shmem file
889 * shmem_page_offset = offset within page in shmem file
890 * data_page_index = page number in get_user_pages return
891 * data_page_offset = offset with data_page_index page.
892 * page_length = bytes to copy for this page
894 shmem_page_index = offset / PAGE_SIZE;
895 shmem_page_offset = offset & ~PAGE_MASK;
896 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
897 data_page_offset = data_ptr & ~PAGE_MASK;
899 page_length = remain;
900 if ((shmem_page_offset + page_length) > PAGE_SIZE)
901 page_length = PAGE_SIZE - shmem_page_offset;
902 if ((data_page_offset + page_length) > PAGE_SIZE)
903 page_length = PAGE_SIZE - data_page_offset;
905 if (do_bit17_swizzling) {
906 ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
908 user_pages[data_page_index],
913 ret = slow_shmem_copy(obj_priv->pages[shmem_page_index],
915 user_pages[data_page_index],
922 remain -= page_length;
923 data_ptr += page_length;
924 offset += page_length;
928 i915_gem_object_put_pages(obj);
930 mutex_unlock(&dev->struct_mutex);
932 for (i = 0; i < pinned_pages; i++)
933 page_cache_release(user_pages[i]);
934 drm_free_large(user_pages);
940 * Writes data to the object referenced by handle.
942 * On error, the contents of the buffer that were to be modified are undefined.
945 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
946 struct drm_file *file_priv)
948 struct drm_i915_gem_pwrite *args = data;
949 struct drm_gem_object *obj;
950 struct drm_i915_gem_object *obj_priv;
953 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
956 obj_priv = obj->driver_private;
958 /* Bounds check destination.
960 * XXX: This could use review for overflow issues...
962 if (args->offset > obj->size || args->size > obj->size ||
963 args->offset + args->size > obj->size) {
964 drm_gem_object_unreference(obj);
968 /* We can only do the GTT pwrite on untiled buffers, as otherwise
969 * it would end up going through the fenced access, and we'll get
970 * different detiling behavior between reading and writing.
971 * pread/pwrite currently are reading and writing from the CPU
972 * perspective, requiring manual detiling by the client.
974 if (obj_priv->phys_obj)
975 ret = i915_gem_phys_pwrite(dev, obj, args, file_priv);
976 else if (obj_priv->tiling_mode == I915_TILING_NONE &&
977 dev->gtt_total != 0) {
978 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file_priv);
979 if (ret == -EFAULT) {
980 ret = i915_gem_gtt_pwrite_slow(dev, obj, args,
983 } else if (i915_gem_object_needs_bit17_swizzle(obj)) {
984 ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file_priv);
986 ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file_priv);
987 if (ret == -EFAULT) {
988 ret = i915_gem_shmem_pwrite_slow(dev, obj, args,
995 DRM_INFO("pwrite failed %d\n", ret);
998 drm_gem_object_unreference(obj);
1004 * Called when user space prepares to use an object with the CPU, either
1005 * through the mmap ioctl's mapping or a GTT mapping.
1008 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1009 struct drm_file *file_priv)
1011 struct drm_i915_private *dev_priv = dev->dev_private;
1012 struct drm_i915_gem_set_domain *args = data;
1013 struct drm_gem_object *obj;
1014 struct drm_i915_gem_object *obj_priv;
1015 uint32_t read_domains = args->read_domains;
1016 uint32_t write_domain = args->write_domain;
1019 if (!(dev->driver->driver_features & DRIVER_GEM))
1022 /* Only handle setting domains to types used by the CPU. */
1023 if (write_domain & I915_GEM_GPU_DOMAINS)
1026 if (read_domains & I915_GEM_GPU_DOMAINS)
1029 /* Having something in the write domain implies it's in the read
1030 * domain, and only that read domain. Enforce that in the request.
1032 if (write_domain != 0 && read_domains != write_domain)
1035 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1038 obj_priv = obj->driver_private;
1040 mutex_lock(&dev->struct_mutex);
1042 intel_mark_busy(dev, obj);
1045 DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n",
1046 obj, obj->size, read_domains, write_domain);
1048 if (read_domains & I915_GEM_DOMAIN_GTT) {
1049 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1051 /* Update the LRU on the fence for the CPU access that's
1054 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1055 list_move_tail(&obj_priv->fence_list,
1056 &dev_priv->mm.fence_list);
1059 /* Silently promote "you're not bound, there was nothing to do"
1060 * to success, since the client was just asking us to
1061 * make sure everything was done.
1066 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1069 drm_gem_object_unreference(obj);
1070 mutex_unlock(&dev->struct_mutex);
1075 * Called when user space has done writes to this buffer
1078 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1079 struct drm_file *file_priv)
1081 struct drm_i915_gem_sw_finish *args = data;
1082 struct drm_gem_object *obj;
1083 struct drm_i915_gem_object *obj_priv;
1086 if (!(dev->driver->driver_features & DRIVER_GEM))
1089 mutex_lock(&dev->struct_mutex);
1090 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1092 mutex_unlock(&dev->struct_mutex);
1097 DRM_INFO("%s: sw_finish %d (%p %zd)\n",
1098 __func__, args->handle, obj, obj->size);
1100 obj_priv = obj->driver_private;
1102 /* Pinned buffers may be scanout, so flush the cache */
1103 if (obj_priv->pin_count)
1104 i915_gem_object_flush_cpu_write_domain(obj);
1106 drm_gem_object_unreference(obj);
1107 mutex_unlock(&dev->struct_mutex);
1112 * Maps the contents of an object, returning the address it is mapped
1115 * While the mapping holds a reference on the contents of the object, it doesn't
1116 * imply a ref on the object itself.
1119 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1120 struct drm_file *file_priv)
1122 struct drm_i915_gem_mmap *args = data;
1123 struct drm_gem_object *obj;
1127 if (!(dev->driver->driver_features & DRIVER_GEM))
1130 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1134 offset = args->offset;
1136 down_write(¤t->mm->mmap_sem);
1137 addr = do_mmap(obj->filp, 0, args->size,
1138 PROT_READ | PROT_WRITE, MAP_SHARED,
1140 up_write(¤t->mm->mmap_sem);
1141 mutex_lock(&dev->struct_mutex);
1142 drm_gem_object_unreference(obj);
1143 mutex_unlock(&dev->struct_mutex);
1144 if (IS_ERR((void *)addr))
1147 args->addr_ptr = (uint64_t) addr;
1153 * i915_gem_fault - fault a page into the GTT
1154 * vma: VMA in question
1157 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1158 * from userspace. The fault handler takes care of binding the object to
1159 * the GTT (if needed), allocating and programming a fence register (again,
1160 * only if needed based on whether the old reg is still valid or the object
1161 * is tiled) and inserting a new PTE into the faulting process.
1163 * Note that the faulting process may involve evicting existing objects
1164 * from the GTT and/or fence registers to make room. So performance may
1165 * suffer if the GTT working set is large or there are few fence registers
1168 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1170 struct drm_gem_object *obj = vma->vm_private_data;
1171 struct drm_device *dev = obj->dev;
1172 struct drm_i915_private *dev_priv = dev->dev_private;
1173 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1174 pgoff_t page_offset;
1177 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1179 /* We don't use vmf->pgoff since that has the fake offset */
1180 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1183 /* Now bind it into the GTT if needed */
1184 mutex_lock(&dev->struct_mutex);
1185 if (!obj_priv->gtt_space) {
1186 ret = i915_gem_object_bind_to_gtt(obj, 0);
1190 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1192 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1197 /* Need a new fence register? */
1198 if (obj_priv->tiling_mode != I915_TILING_NONE) {
1199 ret = i915_gem_object_get_fence_reg(obj);
1204 pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
1207 /* Finally, remap it using the new GTT offset */
1208 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1210 mutex_unlock(&dev->struct_mutex);
1215 return VM_FAULT_NOPAGE;
1218 return VM_FAULT_OOM;
1220 return VM_FAULT_SIGBUS;
1225 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1226 * @obj: obj in question
1228 * GEM memory mapping works by handing back to userspace a fake mmap offset
1229 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1230 * up the object based on the offset and sets up the various memory mapping
1233 * This routine allocates and attaches a fake offset for @obj.
1236 i915_gem_create_mmap_offset(struct drm_gem_object *obj)
1238 struct drm_device *dev = obj->dev;
1239 struct drm_gem_mm *mm = dev->mm_private;
1240 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1241 struct drm_map_list *list;
1242 struct drm_local_map *map;
1245 /* Set the object up for mmap'ing */
1246 list = &obj->map_list;
1247 list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
1252 map->type = _DRM_GEM;
1253 map->size = obj->size;
1256 /* Get a DRM GEM mmap offset allocated... */
1257 list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1258 obj->size / PAGE_SIZE, 0, 0);
1259 if (!list->file_offset_node) {
1260 DRM_ERROR("failed to allocate offset for bo %d\n", obj->name);
1265 list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1266 obj->size / PAGE_SIZE, 0);
1267 if (!list->file_offset_node) {
1272 list->hash.key = list->file_offset_node->start;
1273 if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) {
1274 DRM_ERROR("failed to add to map hash\n");
1279 /* By now we should be all set, any drm_mmap request on the offset
1280 * below will get to our mmap & fault handler */
1281 obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT;
1286 drm_mm_put_block(list->file_offset_node);
1294 * i915_gem_release_mmap - remove physical page mappings
1295 * @obj: obj in question
1297 * Preserve the reservation of the mmaping with the DRM core code, but
1298 * relinquish ownership of the pages back to the system.
1300 * It is vital that we remove the page mapping if we have mapped a tiled
1301 * object through the GTT and then lose the fence register due to
1302 * resource pressure. Similarly if the object has been moved out of the
1303 * aperture, than pages mapped into userspace must be revoked. Removing the
1304 * mapping will then trigger a page fault on the next user access, allowing
1305 * fixup by i915_gem_fault().
1308 i915_gem_release_mmap(struct drm_gem_object *obj)
1310 struct drm_device *dev = obj->dev;
1311 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1313 if (dev->dev_mapping)
1314 unmap_mapping_range(dev->dev_mapping,
1315 obj_priv->mmap_offset, obj->size, 1);
1319 i915_gem_free_mmap_offset(struct drm_gem_object *obj)
1321 struct drm_device *dev = obj->dev;
1322 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1323 struct drm_gem_mm *mm = dev->mm_private;
1324 struct drm_map_list *list;
1326 list = &obj->map_list;
1327 drm_ht_remove_item(&mm->offset_hash, &list->hash);
1329 if (list->file_offset_node) {
1330 drm_mm_put_block(list->file_offset_node);
1331 list->file_offset_node = NULL;
1339 obj_priv->mmap_offset = 0;
1343 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1344 * @obj: object to check
1346 * Return the required GTT alignment for an object, taking into account
1347 * potential fence register mapping if needed.
1350 i915_gem_get_gtt_alignment(struct drm_gem_object *obj)
1352 struct drm_device *dev = obj->dev;
1353 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1357 * Minimum alignment is 4k (GTT page size), but might be greater
1358 * if a fence register is needed for the object.
1360 if (IS_I965G(dev) || obj_priv->tiling_mode == I915_TILING_NONE)
1364 * Previous chips need to be aligned to the size of the smallest
1365 * fence register that can contain the object.
1372 for (i = start; i < obj->size; i <<= 1)
1379 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1381 * @data: GTT mapping ioctl data
1382 * @file_priv: GEM object info
1384 * Simply returns the fake offset to userspace so it can mmap it.
1385 * The mmap call will end up in drm_gem_mmap(), which will set things
1386 * up so we can get faults in the handler above.
1388 * The fault handler will take care of binding the object into the GTT
1389 * (since it may have been evicted to make room for something), allocating
1390 * a fence register, and mapping the appropriate aperture address into
1394 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1395 struct drm_file *file_priv)
1397 struct drm_i915_gem_mmap_gtt *args = data;
1398 struct drm_i915_private *dev_priv = dev->dev_private;
1399 struct drm_gem_object *obj;
1400 struct drm_i915_gem_object *obj_priv;
1403 if (!(dev->driver->driver_features & DRIVER_GEM))
1406 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1410 mutex_lock(&dev->struct_mutex);
1412 obj_priv = obj->driver_private;
1414 if (obj_priv->madv != I915_MADV_WILLNEED) {
1415 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1416 drm_gem_object_unreference(obj);
1417 mutex_unlock(&dev->struct_mutex);
1422 if (!obj_priv->mmap_offset) {
1423 ret = i915_gem_create_mmap_offset(obj);
1425 drm_gem_object_unreference(obj);
1426 mutex_unlock(&dev->struct_mutex);
1431 args->offset = obj_priv->mmap_offset;
1434 * Pull it into the GTT so that we have a page list (makes the
1435 * initial fault faster and any subsequent flushing possible).
1437 if (!obj_priv->agp_mem) {
1438 ret = i915_gem_object_bind_to_gtt(obj, 0);
1440 drm_gem_object_unreference(obj);
1441 mutex_unlock(&dev->struct_mutex);
1444 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1447 drm_gem_object_unreference(obj);
1448 mutex_unlock(&dev->struct_mutex);
1454 i915_gem_object_put_pages(struct drm_gem_object *obj)
1456 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1457 int page_count = obj->size / PAGE_SIZE;
1460 BUG_ON(obj_priv->pages_refcount == 0);
1461 BUG_ON(obj_priv->madv == __I915_MADV_PURGED);
1463 if (--obj_priv->pages_refcount != 0)
1466 if (obj_priv->tiling_mode != I915_TILING_NONE)
1467 i915_gem_object_save_bit_17_swizzle(obj);
1469 if (obj_priv->madv == I915_MADV_DONTNEED)
1470 obj_priv->dirty = 0;
1472 for (i = 0; i < page_count; i++) {
1473 if (obj_priv->pages[i] == NULL)
1476 if (obj_priv->dirty)
1477 set_page_dirty(obj_priv->pages[i]);
1479 if (obj_priv->madv == I915_MADV_WILLNEED)
1480 mark_page_accessed(obj_priv->pages[i]);
1482 page_cache_release(obj_priv->pages[i]);
1484 obj_priv->dirty = 0;
1486 drm_free_large(obj_priv->pages);
1487 obj_priv->pages = NULL;
1491 i915_gem_object_move_to_active(struct drm_gem_object *obj, uint32_t seqno)
1493 struct drm_device *dev = obj->dev;
1494 drm_i915_private_t *dev_priv = dev->dev_private;
1495 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1497 /* Add a reference if we're newly entering the active list. */
1498 if (!obj_priv->active) {
1499 drm_gem_object_reference(obj);
1500 obj_priv->active = 1;
1502 /* Move from whatever list we were on to the tail of execution. */
1503 spin_lock(&dev_priv->mm.active_list_lock);
1504 list_move_tail(&obj_priv->list,
1505 &dev_priv->mm.active_list);
1506 spin_unlock(&dev_priv->mm.active_list_lock);
1507 obj_priv->last_rendering_seqno = seqno;
1511 i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
1513 struct drm_device *dev = obj->dev;
1514 drm_i915_private_t *dev_priv = dev->dev_private;
1515 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1517 BUG_ON(!obj_priv->active);
1518 list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list);
1519 obj_priv->last_rendering_seqno = 0;
1522 /* Immediately discard the backing storage */
1524 i915_gem_object_truncate(struct drm_gem_object *obj)
1526 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1527 struct inode *inode;
1529 inode = obj->filp->f_path.dentry->d_inode;
1530 if (inode->i_op->truncate)
1531 inode->i_op->truncate (inode);
1533 obj_priv->madv = __I915_MADV_PURGED;
1537 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv)
1539 return obj_priv->madv == I915_MADV_DONTNEED;
1543 i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
1545 struct drm_device *dev = obj->dev;
1546 drm_i915_private_t *dev_priv = dev->dev_private;
1547 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1549 i915_verify_inactive(dev, __FILE__, __LINE__);
1550 if (obj_priv->pin_count != 0)
1551 list_del_init(&obj_priv->list);
1553 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1555 obj_priv->last_rendering_seqno = 0;
1556 if (obj_priv->active) {
1557 obj_priv->active = 0;
1558 drm_gem_object_unreference(obj);
1560 i915_verify_inactive(dev, __FILE__, __LINE__);
1564 * Creates a new sequence number, emitting a write of it to the status page
1565 * plus an interrupt, which will trigger i915_user_interrupt_handler.
1567 * Must be called with struct_lock held.
1569 * Returned sequence numbers are nonzero on success.
1572 i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
1573 uint32_t flush_domains)
1575 drm_i915_private_t *dev_priv = dev->dev_private;
1576 struct drm_i915_file_private *i915_file_priv = NULL;
1577 struct drm_i915_gem_request *request;
1582 if (file_priv != NULL)
1583 i915_file_priv = file_priv->driver_priv;
1585 request = kzalloc(sizeof(*request), GFP_KERNEL);
1586 if (request == NULL)
1589 /* Grab the seqno we're going to make this request be, and bump the
1590 * next (skipping 0 so it can be the reserved no-seqno value).
1592 seqno = dev_priv->mm.next_gem_seqno;
1593 dev_priv->mm.next_gem_seqno++;
1594 if (dev_priv->mm.next_gem_seqno == 0)
1595 dev_priv->mm.next_gem_seqno++;
1598 OUT_RING(MI_STORE_DWORD_INDEX);
1599 OUT_RING(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1602 OUT_RING(MI_USER_INTERRUPT);
1605 DRM_DEBUG("%d\n", seqno);
1607 request->seqno = seqno;
1608 request->emitted_jiffies = jiffies;
1609 was_empty = list_empty(&dev_priv->mm.request_list);
1610 list_add_tail(&request->list, &dev_priv->mm.request_list);
1611 if (i915_file_priv) {
1612 list_add_tail(&request->client_list,
1613 &i915_file_priv->mm.request_list);
1615 INIT_LIST_HEAD(&request->client_list);
1618 /* Associate any objects on the flushing list matching the write
1619 * domain we're flushing with our flush.
1621 if (flush_domains != 0) {
1622 struct drm_i915_gem_object *obj_priv, *next;
1624 list_for_each_entry_safe(obj_priv, next,
1625 &dev_priv->mm.flushing_list, list) {
1626 struct drm_gem_object *obj = obj_priv->obj;
1628 if ((obj->write_domain & flush_domains) ==
1629 obj->write_domain) {
1630 uint32_t old_write_domain = obj->write_domain;
1632 obj->write_domain = 0;
1633 i915_gem_object_move_to_active(obj, seqno);
1635 trace_i915_gem_object_change_domain(obj,
1643 if (!dev_priv->mm.suspended) {
1644 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
1646 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1652 * Command execution barrier
1654 * Ensures that all commands in the ring are finished
1655 * before signalling the CPU
1658 i915_retire_commands(struct drm_device *dev)
1660 drm_i915_private_t *dev_priv = dev->dev_private;
1661 uint32_t cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
1662 uint32_t flush_domains = 0;
1665 /* The sampler always gets flushed on i965 (sigh) */
1667 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
1670 OUT_RING(0); /* noop */
1672 return flush_domains;
1676 * Moves buffers associated only with the given active seqno from the active
1677 * to inactive list, potentially freeing them.
1680 i915_gem_retire_request(struct drm_device *dev,
1681 struct drm_i915_gem_request *request)
1683 drm_i915_private_t *dev_priv = dev->dev_private;
1685 trace_i915_gem_request_retire(dev, request->seqno);
1687 /* Move any buffers on the active list that are no longer referenced
1688 * by the ringbuffer to the flushing/inactive lists as appropriate.
1690 spin_lock(&dev_priv->mm.active_list_lock);
1691 while (!list_empty(&dev_priv->mm.active_list)) {
1692 struct drm_gem_object *obj;
1693 struct drm_i915_gem_object *obj_priv;
1695 obj_priv = list_first_entry(&dev_priv->mm.active_list,
1696 struct drm_i915_gem_object,
1698 obj = obj_priv->obj;
1700 /* If the seqno being retired doesn't match the oldest in the
1701 * list, then the oldest in the list must still be newer than
1704 if (obj_priv->last_rendering_seqno != request->seqno)
1708 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1709 __func__, request->seqno, obj);
1712 if (obj->write_domain != 0)
1713 i915_gem_object_move_to_flushing(obj);
1715 /* Take a reference on the object so it won't be
1716 * freed while the spinlock is held. The list
1717 * protection for this spinlock is safe when breaking
1718 * the lock like this since the next thing we do
1719 * is just get the head of the list again.
1721 drm_gem_object_reference(obj);
1722 i915_gem_object_move_to_inactive(obj);
1723 spin_unlock(&dev_priv->mm.active_list_lock);
1724 drm_gem_object_unreference(obj);
1725 spin_lock(&dev_priv->mm.active_list_lock);
1729 spin_unlock(&dev_priv->mm.active_list_lock);
1733 * Returns true if seq1 is later than seq2.
1736 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1738 return (int32_t)(seq1 - seq2) >= 0;
1742 i915_get_gem_seqno(struct drm_device *dev)
1744 drm_i915_private_t *dev_priv = dev->dev_private;
1746 return READ_HWSP(dev_priv, I915_GEM_HWS_INDEX);
1750 * This function clears the request list as sequence numbers are passed.
1753 i915_gem_retire_requests(struct drm_device *dev)
1755 drm_i915_private_t *dev_priv = dev->dev_private;
1758 if (!dev_priv->hw_status_page || list_empty(&dev_priv->mm.request_list))
1761 seqno = i915_get_gem_seqno(dev);
1763 while (!list_empty(&dev_priv->mm.request_list)) {
1764 struct drm_i915_gem_request *request;
1765 uint32_t retiring_seqno;
1767 request = list_first_entry(&dev_priv->mm.request_list,
1768 struct drm_i915_gem_request,
1770 retiring_seqno = request->seqno;
1772 if (i915_seqno_passed(seqno, retiring_seqno) ||
1773 atomic_read(&dev_priv->mm.wedged)) {
1774 i915_gem_retire_request(dev, request);
1776 list_del(&request->list);
1777 list_del(&request->client_list);
1783 if (unlikely (dev_priv->trace_irq_seqno &&
1784 i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) {
1785 i915_user_irq_put(dev);
1786 dev_priv->trace_irq_seqno = 0;
1791 i915_gem_retire_work_handler(struct work_struct *work)
1793 drm_i915_private_t *dev_priv;
1794 struct drm_device *dev;
1796 dev_priv = container_of(work, drm_i915_private_t,
1797 mm.retire_work.work);
1798 dev = dev_priv->dev;
1800 mutex_lock(&dev->struct_mutex);
1801 i915_gem_retire_requests(dev);
1802 if (!dev_priv->mm.suspended &&
1803 !list_empty(&dev_priv->mm.request_list))
1804 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1805 mutex_unlock(&dev->struct_mutex);
1809 * Waits for a sequence number to be signaled, and cleans up the
1810 * request and object lists appropriately for that event.
1813 i915_wait_request(struct drm_device *dev, uint32_t seqno)
1815 drm_i915_private_t *dev_priv = dev->dev_private;
1821 if (atomic_read(&dev_priv->mm.wedged))
1824 if (!i915_seqno_passed(i915_get_gem_seqno(dev), seqno)) {
1826 ier = I915_READ(DEIER) | I915_READ(GTIER);
1828 ier = I915_READ(IER);
1830 DRM_ERROR("something (likely vbetool) disabled "
1831 "interrupts, re-enabling\n");
1832 i915_driver_irq_preinstall(dev);
1833 i915_driver_irq_postinstall(dev);
1836 trace_i915_gem_request_wait_begin(dev, seqno);
1838 dev_priv->mm.waiting_gem_seqno = seqno;
1839 i915_user_irq_get(dev);
1840 ret = wait_event_interruptible(dev_priv->irq_queue,
1841 i915_seqno_passed(i915_get_gem_seqno(dev),
1843 atomic_read(&dev_priv->mm.wedged));
1844 i915_user_irq_put(dev);
1845 dev_priv->mm.waiting_gem_seqno = 0;
1847 trace_i915_gem_request_wait_end(dev, seqno);
1849 if (atomic_read(&dev_priv->mm.wedged))
1852 if (ret && ret != -ERESTARTSYS)
1853 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
1854 __func__, ret, seqno, i915_get_gem_seqno(dev));
1856 /* Directly dispatch request retiring. While we have the work queue
1857 * to handle this, the waiter on a request often wants an associated
1858 * buffer to have made it to the inactive list, and we would need
1859 * a separate wait queue to handle that.
1862 i915_gem_retire_requests(dev);
1868 i915_gem_flush(struct drm_device *dev,
1869 uint32_t invalidate_domains,
1870 uint32_t flush_domains)
1872 drm_i915_private_t *dev_priv = dev->dev_private;
1877 DRM_INFO("%s: invalidate %08x flush %08x\n", __func__,
1878 invalidate_domains, flush_domains);
1880 trace_i915_gem_request_flush(dev, dev_priv->mm.next_gem_seqno,
1881 invalidate_domains, flush_domains);
1883 if (flush_domains & I915_GEM_DOMAIN_CPU)
1884 drm_agp_chipset_flush(dev);
1886 if ((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) {
1888 * read/write caches:
1890 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
1891 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
1892 * also flushed at 2d versus 3d pipeline switches.
1896 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
1897 * MI_READ_FLUSH is set, and is always flushed on 965.
1899 * I915_GEM_DOMAIN_COMMAND may not exist?
1901 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
1902 * invalidated when MI_EXE_FLUSH is set.
1904 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
1905 * invalidated with every MI_FLUSH.
1909 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
1910 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
1911 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
1912 * are flushed at any MI_FLUSH.
1915 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
1916 if ((invalidate_domains|flush_domains) &
1917 I915_GEM_DOMAIN_RENDER)
1918 cmd &= ~MI_NO_WRITE_FLUSH;
1919 if (!IS_I965G(dev)) {
1921 * On the 965, the sampler cache always gets flushed
1922 * and this bit is reserved.
1924 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
1925 cmd |= MI_READ_FLUSH;
1927 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
1928 cmd |= MI_EXE_FLUSH;
1931 DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd);
1935 OUT_RING(0); /* noop */
1941 * Ensures that all rendering to the object has completed and the object is
1942 * safe to unbind from the GTT or access from the CPU.
1945 i915_gem_object_wait_rendering(struct drm_gem_object *obj)
1947 struct drm_device *dev = obj->dev;
1948 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1951 /* This function only exists to support waiting for existing rendering,
1952 * not for emitting required flushes.
1954 BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0);
1956 /* If there is rendering queued on the buffer being evicted, wait for
1959 if (obj_priv->active) {
1961 DRM_INFO("%s: object %p wait for seqno %08x\n",
1962 __func__, obj, obj_priv->last_rendering_seqno);
1964 ret = i915_wait_request(dev, obj_priv->last_rendering_seqno);
1973 * Unbinds an object from the GTT aperture.
1976 i915_gem_object_unbind(struct drm_gem_object *obj)
1978 struct drm_device *dev = obj->dev;
1979 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1983 DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj);
1984 DRM_INFO("gtt_space %p\n", obj_priv->gtt_space);
1986 if (obj_priv->gtt_space == NULL)
1989 if (obj_priv->pin_count != 0) {
1990 DRM_ERROR("Attempting to unbind pinned buffer\n");
1994 /* blow away mappings if mapped through GTT */
1995 i915_gem_release_mmap(obj);
1997 /* Move the object to the CPU domain to ensure that
1998 * any possible CPU writes while it's not in the GTT
1999 * are flushed when we go to remap it. This will
2000 * also ensure that all pending GPU writes are finished
2003 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
2005 if (ret != -ERESTARTSYS)
2006 DRM_ERROR("set_domain failed: %d\n", ret);
2010 BUG_ON(obj_priv->active);
2012 /* release the fence reg _after_ flushing */
2013 if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
2014 i915_gem_clear_fence_reg(obj);
2016 if (obj_priv->agp_mem != NULL) {
2017 drm_unbind_agp(obj_priv->agp_mem);
2018 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
2019 obj_priv->agp_mem = NULL;
2022 i915_gem_object_put_pages(obj);
2023 BUG_ON(obj_priv->pages_refcount);
2025 if (obj_priv->gtt_space) {
2026 atomic_dec(&dev->gtt_count);
2027 atomic_sub(obj->size, &dev->gtt_memory);
2029 drm_mm_put_block(obj_priv->gtt_space);
2030 obj_priv->gtt_space = NULL;
2033 /* Remove ourselves from the LRU list if present. */
2034 if (!list_empty(&obj_priv->list))
2035 list_del_init(&obj_priv->list);
2037 if (i915_gem_object_is_purgeable(obj_priv))
2038 i915_gem_object_truncate(obj);
2040 trace_i915_gem_object_unbind(obj);
2045 static struct drm_gem_object *
2046 i915_gem_find_inactive_object(struct drm_device *dev, int min_size)
2048 drm_i915_private_t *dev_priv = dev->dev_private;
2049 struct drm_i915_gem_object *obj_priv;
2050 struct drm_gem_object *best = NULL;
2051 struct drm_gem_object *first = NULL;
2053 /* Try to find the smallest clean object */
2054 list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, list) {
2055 struct drm_gem_object *obj = obj_priv->obj;
2056 if (obj->size >= min_size) {
2057 if ((!obj_priv->dirty ||
2058 i915_gem_object_is_purgeable(obj_priv)) &&
2059 (!best || obj->size < best->size)) {
2061 if (best->size == min_size)
2069 return best ? best : first;
2073 i915_gem_evict_everything(struct drm_device *dev)
2075 drm_i915_private_t *dev_priv = dev->dev_private;
2080 spin_lock(&dev_priv->mm.active_list_lock);
2081 lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2082 list_empty(&dev_priv->mm.flushing_list) &&
2083 list_empty(&dev_priv->mm.active_list));
2084 spin_unlock(&dev_priv->mm.active_list_lock);
2089 /* Flush everything (on to the inactive lists) and evict */
2090 i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
2091 seqno = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS);
2095 ret = i915_wait_request(dev, seqno);
2099 ret = i915_gem_evict_from_inactive_list(dev);
2103 spin_lock(&dev_priv->mm.active_list_lock);
2104 lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2105 list_empty(&dev_priv->mm.flushing_list) &&
2106 list_empty(&dev_priv->mm.active_list));
2107 spin_unlock(&dev_priv->mm.active_list_lock);
2108 BUG_ON(!lists_empty);
2114 i915_gem_evict_something(struct drm_device *dev, int min_size)
2116 drm_i915_private_t *dev_priv = dev->dev_private;
2117 struct drm_gem_object *obj;
2121 i915_gem_retire_requests(dev);
2123 /* If there's an inactive buffer available now, grab it
2126 obj = i915_gem_find_inactive_object(dev, min_size);
2128 struct drm_i915_gem_object *obj_priv;
2131 DRM_INFO("%s: evicting %p\n", __func__, obj);
2133 obj_priv = obj->driver_private;
2134 BUG_ON(obj_priv->pin_count != 0);
2135 BUG_ON(obj_priv->active);
2137 /* Wait on the rendering and unbind the buffer. */
2138 return i915_gem_object_unbind(obj);
2141 /* If we didn't get anything, but the ring is still processing
2142 * things, wait for the next to finish and hopefully leave us
2143 * a buffer to evict.
2145 if (!list_empty(&dev_priv->mm.request_list)) {
2146 struct drm_i915_gem_request *request;
2148 request = list_first_entry(&dev_priv->mm.request_list,
2149 struct drm_i915_gem_request,
2152 ret = i915_wait_request(dev, request->seqno);
2159 /* If we didn't have anything on the request list but there
2160 * are buffers awaiting a flush, emit one and try again.
2161 * When we wait on it, those buffers waiting for that flush
2162 * will get moved to inactive.
2164 if (!list_empty(&dev_priv->mm.flushing_list)) {
2165 struct drm_i915_gem_object *obj_priv;
2167 /* Find an object that we can immediately reuse */
2168 list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list, list) {
2169 obj = obj_priv->obj;
2170 if (obj->size >= min_size)
2182 seqno = i915_add_request(dev, NULL, obj->write_domain);
2186 ret = i915_wait_request(dev, seqno);
2194 /* If we didn't do any of the above, there's no single buffer
2195 * large enough to swap out for the new one, so just evict
2196 * everything and start again. (This should be rare.)
2198 if (!list_empty (&dev_priv->mm.inactive_list))
2199 return i915_gem_evict_from_inactive_list(dev);
2201 return i915_gem_evict_everything(dev);
2206 i915_gem_object_get_pages(struct drm_gem_object *obj,
2209 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2211 struct address_space *mapping;
2212 struct inode *inode;
2216 if (obj_priv->pages_refcount++ != 0)
2219 /* Get the list of pages out of our struct file. They'll be pinned
2220 * at this point until we release them.
2222 page_count = obj->size / PAGE_SIZE;
2223 BUG_ON(obj_priv->pages != NULL);
2224 obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *));
2225 if (obj_priv->pages == NULL) {
2226 obj_priv->pages_refcount--;
2230 inode = obj->filp->f_path.dentry->d_inode;
2231 mapping = inode->i_mapping;
2232 for (i = 0; i < page_count; i++) {
2233 page = read_cache_page_gfp(mapping, i,
2234 mapping_gfp_mask (mapping) |
2238 ret = PTR_ERR(page);
2239 i915_gem_object_put_pages(obj);
2242 obj_priv->pages[i] = page;
2245 if (obj_priv->tiling_mode != I915_TILING_NONE)
2246 i915_gem_object_do_bit_17_swizzle(obj);
2251 static void i965_write_fence_reg(struct drm_i915_fence_reg *reg)
2253 struct drm_gem_object *obj = reg->obj;
2254 struct drm_device *dev = obj->dev;
2255 drm_i915_private_t *dev_priv = dev->dev_private;
2256 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2257 int regnum = obj_priv->fence_reg;
2260 val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2262 val |= obj_priv->gtt_offset & 0xfffff000;
2263 val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2264 if (obj_priv->tiling_mode == I915_TILING_Y)
2265 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2266 val |= I965_FENCE_REG_VALID;
2268 I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val);
2271 static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
2273 struct drm_gem_object *obj = reg->obj;
2274 struct drm_device *dev = obj->dev;
2275 drm_i915_private_t *dev_priv = dev->dev_private;
2276 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2277 int regnum = obj_priv->fence_reg;
2279 uint32_t fence_reg, val;
2282 if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
2283 (obj_priv->gtt_offset & (obj->size - 1))) {
2284 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
2285 __func__, obj_priv->gtt_offset, obj->size);
2289 if (obj_priv->tiling_mode == I915_TILING_Y &&
2290 HAS_128_BYTE_Y_TILING(dev))
2295 /* Note: pitch better be a power of two tile widths */
2296 pitch_val = obj_priv->stride / tile_width;
2297 pitch_val = ffs(pitch_val) - 1;
2299 val = obj_priv->gtt_offset;
2300 if (obj_priv->tiling_mode == I915_TILING_Y)
2301 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2302 val |= I915_FENCE_SIZE_BITS(obj->size);
2303 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2304 val |= I830_FENCE_REG_VALID;
2307 fence_reg = FENCE_REG_830_0 + (regnum * 4);
2309 fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4);
2310 I915_WRITE(fence_reg, val);
2313 static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
2315 struct drm_gem_object *obj = reg->obj;
2316 struct drm_device *dev = obj->dev;
2317 drm_i915_private_t *dev_priv = dev->dev_private;
2318 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2319 int regnum = obj_priv->fence_reg;
2322 uint32_t fence_size_bits;
2324 if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) ||
2325 (obj_priv->gtt_offset & (obj->size - 1))) {
2326 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
2327 __func__, obj_priv->gtt_offset);
2331 pitch_val = obj_priv->stride / 128;
2332 pitch_val = ffs(pitch_val) - 1;
2333 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2335 val = obj_priv->gtt_offset;
2336 if (obj_priv->tiling_mode == I915_TILING_Y)
2337 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2338 fence_size_bits = I830_FENCE_SIZE_BITS(obj->size);
2339 WARN_ON(fence_size_bits & ~0x00000f00);
2340 val |= fence_size_bits;
2341 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2342 val |= I830_FENCE_REG_VALID;
2344 I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
2348 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2349 * @obj: object to map through a fence reg
2351 * When mapping objects through the GTT, userspace wants to be able to write
2352 * to them without having to worry about swizzling if the object is tiled.
2354 * This function walks the fence regs looking for a free one for @obj,
2355 * stealing one if it can't find any.
2357 * It then sets up the reg based on the object's properties: address, pitch
2358 * and tiling format.
2361 i915_gem_object_get_fence_reg(struct drm_gem_object *obj)
2363 struct drm_device *dev = obj->dev;
2364 struct drm_i915_private *dev_priv = dev->dev_private;
2365 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2366 struct drm_i915_fence_reg *reg = NULL;
2367 struct drm_i915_gem_object *old_obj_priv = NULL;
2370 /* Just update our place in the LRU if our fence is getting used. */
2371 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
2372 list_move_tail(&obj_priv->fence_list, &dev_priv->mm.fence_list);
2376 switch (obj_priv->tiling_mode) {
2377 case I915_TILING_NONE:
2378 WARN(1, "allocating a fence for non-tiled object?\n");
2381 if (!obj_priv->stride)
2383 WARN((obj_priv->stride & (512 - 1)),
2384 "object 0x%08x is X tiled but has non-512B pitch\n",
2385 obj_priv->gtt_offset);
2388 if (!obj_priv->stride)
2390 WARN((obj_priv->stride & (128 - 1)),
2391 "object 0x%08x is Y tiled but has non-128B pitch\n",
2392 obj_priv->gtt_offset);
2396 /* First try to find a free reg */
2398 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2399 reg = &dev_priv->fence_regs[i];
2403 old_obj_priv = reg->obj->driver_private;
2404 if (!old_obj_priv->pin_count)
2408 /* None available, try to steal one or wait for a user to finish */
2409 if (i == dev_priv->num_fence_regs) {
2410 struct drm_gem_object *old_obj = NULL;
2415 list_for_each_entry(old_obj_priv, &dev_priv->mm.fence_list,
2417 old_obj = old_obj_priv->obj;
2419 if (old_obj_priv->pin_count)
2422 /* Take a reference, as otherwise the wait_rendering
2423 * below may cause the object to get freed out from
2426 drm_gem_object_reference(old_obj);
2428 /* i915 uses fences for GPU access to tiled buffers */
2429 if (IS_I965G(dev) || !old_obj_priv->active)
2432 /* This brings the object to the head of the LRU if it
2433 * had been written to. The only way this should
2434 * result in us waiting longer than the expected
2435 * optimal amount of time is if there was a
2436 * fence-using buffer later that was read-only.
2438 i915_gem_object_flush_gpu_write_domain(old_obj);
2439 ret = i915_gem_object_wait_rendering(old_obj);
2441 drm_gem_object_unreference(old_obj);
2449 * Zap this virtual mapping so we can set up a fence again
2450 * for this object next time we need it.
2452 i915_gem_release_mmap(old_obj);
2454 i = old_obj_priv->fence_reg;
2455 reg = &dev_priv->fence_regs[i];
2457 old_obj_priv->fence_reg = I915_FENCE_REG_NONE;
2458 list_del_init(&old_obj_priv->fence_list);
2460 drm_gem_object_unreference(old_obj);
2463 obj_priv->fence_reg = i;
2464 list_add_tail(&obj_priv->fence_list, &dev_priv->mm.fence_list);
2469 i965_write_fence_reg(reg);
2470 else if (IS_I9XX(dev))
2471 i915_write_fence_reg(reg);
2473 i830_write_fence_reg(reg);
2475 trace_i915_gem_object_get_fence(obj, i, obj_priv->tiling_mode);
2481 * i915_gem_clear_fence_reg - clear out fence register info
2482 * @obj: object to clear
2484 * Zeroes out the fence register itself and clears out the associated
2485 * data structures in dev_priv and obj_priv.
2488 i915_gem_clear_fence_reg(struct drm_gem_object *obj)
2490 struct drm_device *dev = obj->dev;
2491 drm_i915_private_t *dev_priv = dev->dev_private;
2492 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2495 I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
2499 if (obj_priv->fence_reg < 8)
2500 fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4;
2502 fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg -
2505 I915_WRITE(fence_reg, 0);
2508 dev_priv->fence_regs[obj_priv->fence_reg].obj = NULL;
2509 obj_priv->fence_reg = I915_FENCE_REG_NONE;
2510 list_del_init(&obj_priv->fence_list);
2514 * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2515 * to the buffer to finish, and then resets the fence register.
2516 * @obj: tiled object holding a fence register.
2518 * Zeroes out the fence register itself and clears out the associated
2519 * data structures in dev_priv and obj_priv.
2522 i915_gem_object_put_fence_reg(struct drm_gem_object *obj)
2524 struct drm_device *dev = obj->dev;
2525 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2527 if (obj_priv->fence_reg == I915_FENCE_REG_NONE)
2530 /* On the i915, GPU access to tiled buffers is via a fence,
2531 * therefore we must wait for any outstanding access to complete
2532 * before clearing the fence.
2534 if (!IS_I965G(dev)) {
2537 i915_gem_object_flush_gpu_write_domain(obj);
2538 i915_gem_object_flush_gtt_write_domain(obj);
2539 ret = i915_gem_object_wait_rendering(obj);
2544 i915_gem_clear_fence_reg (obj);
2550 * Finds free space in the GTT aperture and binds the object there.
2553 i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2555 struct drm_device *dev = obj->dev;
2556 drm_i915_private_t *dev_priv = dev->dev_private;
2557 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2558 struct drm_mm_node *free_space;
2559 gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN;
2562 if (obj_priv->madv != I915_MADV_WILLNEED) {
2563 DRM_ERROR("Attempting to bind a purgeable object\n");
2568 alignment = i915_gem_get_gtt_alignment(obj);
2569 if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) {
2570 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2575 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2576 obj->size, alignment, 0);
2577 if (free_space != NULL) {
2578 obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
2580 if (obj_priv->gtt_space != NULL) {
2581 obj_priv->gtt_space->private = obj;
2582 obj_priv->gtt_offset = obj_priv->gtt_space->start;
2585 if (obj_priv->gtt_space == NULL) {
2586 /* If the gtt is empty and we're still having trouble
2587 * fitting our object in, we're out of memory.
2590 DRM_INFO("%s: GTT full, evicting something\n", __func__);
2592 ret = i915_gem_evict_something(dev, obj->size);
2600 DRM_INFO("Binding object of size %zd at 0x%08x\n",
2601 obj->size, obj_priv->gtt_offset);
2603 ret = i915_gem_object_get_pages(obj, gfpmask);
2605 drm_mm_put_block(obj_priv->gtt_space);
2606 obj_priv->gtt_space = NULL;
2608 if (ret == -ENOMEM) {
2609 /* first try to clear up some space from the GTT */
2610 ret = i915_gem_evict_something(dev, obj->size);
2612 /* now try to shrink everyone else */
2627 /* Create an AGP memory structure pointing at our pages, and bind it
2630 obj_priv->agp_mem = drm_agp_bind_pages(dev,
2632 obj->size >> PAGE_SHIFT,
2633 obj_priv->gtt_offset,
2634 obj_priv->agp_type);
2635 if (obj_priv->agp_mem == NULL) {
2636 i915_gem_object_put_pages(obj);
2637 drm_mm_put_block(obj_priv->gtt_space);
2638 obj_priv->gtt_space = NULL;
2640 ret = i915_gem_evict_something(dev, obj->size);
2646 atomic_inc(&dev->gtt_count);
2647 atomic_add(obj->size, &dev->gtt_memory);
2649 /* Assert that the object is not currently in any GPU domain. As it
2650 * wasn't in the GTT, there shouldn't be any way it could have been in
2653 BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS);
2654 BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS);
2656 trace_i915_gem_object_bind(obj, obj_priv->gtt_offset);
2662 i915_gem_clflush_object(struct drm_gem_object *obj)
2664 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2666 /* If we don't have a page list set up, then we're not pinned
2667 * to GPU, and we can ignore the cache flush because it'll happen
2668 * again at bind time.
2670 if (obj_priv->pages == NULL)
2673 trace_i915_gem_object_clflush(obj);
2675 drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE);
2678 /** Flushes any GPU write domain for the object if it's dirty. */
2680 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
2682 struct drm_device *dev = obj->dev;
2684 uint32_t old_write_domain;
2686 if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
2689 /* Queue the GPU write cache flushing we need. */
2690 old_write_domain = obj->write_domain;
2691 i915_gem_flush(dev, 0, obj->write_domain);
2692 seqno = i915_add_request(dev, NULL, obj->write_domain);
2693 obj->write_domain = 0;
2694 i915_gem_object_move_to_active(obj, seqno);
2696 trace_i915_gem_object_change_domain(obj,
2701 /** Flushes the GTT write domain for the object if it's dirty. */
2703 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
2705 uint32_t old_write_domain;
2707 if (obj->write_domain != I915_GEM_DOMAIN_GTT)
2710 /* No actual flushing is required for the GTT write domain. Writes
2711 * to it immediately go to main memory as far as we know, so there's
2712 * no chipset flush. It also doesn't land in render cache.
2714 old_write_domain = obj->write_domain;
2715 obj->write_domain = 0;
2717 trace_i915_gem_object_change_domain(obj,
2722 /** Flushes the CPU write domain for the object if it's dirty. */
2724 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
2726 struct drm_device *dev = obj->dev;
2727 uint32_t old_write_domain;
2729 if (obj->write_domain != I915_GEM_DOMAIN_CPU)
2732 i915_gem_clflush_object(obj);
2733 drm_agp_chipset_flush(dev);
2734 old_write_domain = obj->write_domain;
2735 obj->write_domain = 0;
2737 trace_i915_gem_object_change_domain(obj,
2743 * Moves a single object to the GTT read, and possibly write domain.
2745 * This function returns when the move is complete, including waiting on
2749 i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
2751 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2752 uint32_t old_write_domain, old_read_domains;
2755 /* Not valid to be called on unbound objects. */
2756 if (obj_priv->gtt_space == NULL)
2759 i915_gem_object_flush_gpu_write_domain(obj);
2760 /* Wait on any GPU rendering and flushing to occur. */
2761 ret = i915_gem_object_wait_rendering(obj);
2765 old_write_domain = obj->write_domain;
2766 old_read_domains = obj->read_domains;
2768 /* If we're writing through the GTT domain, then CPU and GPU caches
2769 * will need to be invalidated at next use.
2772 obj->read_domains &= I915_GEM_DOMAIN_GTT;
2774 i915_gem_object_flush_cpu_write_domain(obj);
2776 /* It should now be out of any other write domains, and we can update
2777 * the domain values for our changes.
2779 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2780 obj->read_domains |= I915_GEM_DOMAIN_GTT;
2782 obj->write_domain = I915_GEM_DOMAIN_GTT;
2783 obj_priv->dirty = 1;
2786 trace_i915_gem_object_change_domain(obj,
2794 * Moves a single object to the CPU read, and possibly write domain.
2796 * This function returns when the move is complete, including waiting on
2800 i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
2802 uint32_t old_write_domain, old_read_domains;
2805 i915_gem_object_flush_gpu_write_domain(obj);
2806 /* Wait on any GPU rendering and flushing to occur. */
2807 ret = i915_gem_object_wait_rendering(obj);
2811 i915_gem_object_flush_gtt_write_domain(obj);
2813 /* If we have a partially-valid cache of the object in the CPU,
2814 * finish invalidating it and free the per-page flags.
2816 i915_gem_object_set_to_full_cpu_read_domain(obj);
2818 old_write_domain = obj->write_domain;
2819 old_read_domains = obj->read_domains;
2821 /* Flush the CPU cache if it's still invalid. */
2822 if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2823 i915_gem_clflush_object(obj);
2825 obj->read_domains |= I915_GEM_DOMAIN_CPU;
2828 /* It should now be out of any other write domains, and we can update
2829 * the domain values for our changes.
2831 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2833 /* If we're writing through the CPU, then the GPU read domains will
2834 * need to be invalidated at next use.
2837 obj->read_domains &= I915_GEM_DOMAIN_CPU;
2838 obj->write_domain = I915_GEM_DOMAIN_CPU;
2841 trace_i915_gem_object_change_domain(obj,
2849 * Set the next domain for the specified object. This
2850 * may not actually perform the necessary flushing/invaliding though,
2851 * as that may want to be batched with other set_domain operations
2853 * This is (we hope) the only really tricky part of gem. The goal
2854 * is fairly simple -- track which caches hold bits of the object
2855 * and make sure they remain coherent. A few concrete examples may
2856 * help to explain how it works. For shorthand, we use the notation
2857 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
2858 * a pair of read and write domain masks.
2860 * Case 1: the batch buffer
2866 * 5. Unmapped from GTT
2869 * Let's take these a step at a time
2872 * Pages allocated from the kernel may still have
2873 * cache contents, so we set them to (CPU, CPU) always.
2874 * 2. Written by CPU (using pwrite)
2875 * The pwrite function calls set_domain (CPU, CPU) and
2876 * this function does nothing (as nothing changes)
2878 * This function asserts that the object is not
2879 * currently in any GPU-based read or write domains
2881 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
2882 * As write_domain is zero, this function adds in the
2883 * current read domains (CPU+COMMAND, 0).
2884 * flush_domains is set to CPU.
2885 * invalidate_domains is set to COMMAND
2886 * clflush is run to get data out of the CPU caches
2887 * then i915_dev_set_domain calls i915_gem_flush to
2888 * emit an MI_FLUSH and drm_agp_chipset_flush
2889 * 5. Unmapped from GTT
2890 * i915_gem_object_unbind calls set_domain (CPU, CPU)
2891 * flush_domains and invalidate_domains end up both zero
2892 * so no flushing/invalidating happens
2896 * Case 2: The shared render buffer
2900 * 3. Read/written by GPU
2901 * 4. set_domain to (CPU,CPU)
2902 * 5. Read/written by CPU
2903 * 6. Read/written by GPU
2906 * Same as last example, (CPU, CPU)
2908 * Nothing changes (assertions find that it is not in the GPU)
2909 * 3. Read/written by GPU
2910 * execbuffer calls set_domain (RENDER, RENDER)
2911 * flush_domains gets CPU
2912 * invalidate_domains gets GPU
2914 * MI_FLUSH and drm_agp_chipset_flush
2915 * 4. set_domain (CPU, CPU)
2916 * flush_domains gets GPU
2917 * invalidate_domains gets CPU
2918 * wait_rendering (obj) to make sure all drawing is complete.
2919 * This will include an MI_FLUSH to get the data from GPU
2921 * clflush (obj) to invalidate the CPU cache
2922 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
2923 * 5. Read/written by CPU
2924 * cache lines are loaded and dirtied
2925 * 6. Read written by GPU
2926 * Same as last GPU access
2928 * Case 3: The constant buffer
2933 * 4. Updated (written) by CPU again
2942 * flush_domains = CPU
2943 * invalidate_domains = RENDER
2946 * drm_agp_chipset_flush
2947 * 4. Updated (written) by CPU again
2949 * flush_domains = 0 (no previous write domain)
2950 * invalidate_domains = 0 (no new read domains)
2953 * flush_domains = CPU
2954 * invalidate_domains = RENDER
2957 * drm_agp_chipset_flush
2960 i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
2962 struct drm_device *dev = obj->dev;
2963 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2964 uint32_t invalidate_domains = 0;
2965 uint32_t flush_domains = 0;
2966 uint32_t old_read_domains;
2968 BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU);
2969 BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU);
2971 intel_mark_busy(dev, obj);
2974 DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
2976 obj->read_domains, obj->pending_read_domains,
2977 obj->write_domain, obj->pending_write_domain);
2980 * If the object isn't moving to a new write domain,
2981 * let the object stay in multiple read domains
2983 if (obj->pending_write_domain == 0)
2984 obj->pending_read_domains |= obj->read_domains;
2986 obj_priv->dirty = 1;
2989 * Flush the current write domain if
2990 * the new read domains don't match. Invalidate
2991 * any read domains which differ from the old
2994 if (obj->write_domain &&
2995 obj->write_domain != obj->pending_read_domains) {
2996 flush_domains |= obj->write_domain;
2997 invalidate_domains |=
2998 obj->pending_read_domains & ~obj->write_domain;
3001 * Invalidate any read caches which may have
3002 * stale data. That is, any new read domains.
3004 invalidate_domains |= obj->pending_read_domains & ~obj->read_domains;
3005 if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) {
3007 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
3008 __func__, flush_domains, invalidate_domains);
3010 i915_gem_clflush_object(obj);
3013 old_read_domains = obj->read_domains;
3015 /* The actual obj->write_domain will be updated with
3016 * pending_write_domain after we emit the accumulated flush for all
3017 * of our domain changes in execbuffers (which clears objects'
3018 * write_domains). So if we have a current write domain that we
3019 * aren't changing, set pending_write_domain to that.
3021 if (flush_domains == 0 && obj->pending_write_domain == 0)
3022 obj->pending_write_domain = obj->write_domain;
3023 obj->read_domains = obj->pending_read_domains;
3025 dev->invalidate_domains |= invalidate_domains;
3026 dev->flush_domains |= flush_domains;
3028 DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
3030 obj->read_domains, obj->write_domain,
3031 dev->invalidate_domains, dev->flush_domains);
3034 trace_i915_gem_object_change_domain(obj,
3040 * Moves the object from a partially CPU read to a full one.
3042 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3043 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3046 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj)
3048 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3050 if (!obj_priv->page_cpu_valid)
3053 /* If we're partially in the CPU read domain, finish moving it in.
3055 if (obj->read_domains & I915_GEM_DOMAIN_CPU) {
3058 for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) {
3059 if (obj_priv->page_cpu_valid[i])
3061 drm_clflush_pages(obj_priv->pages + i, 1);
3065 /* Free the page_cpu_valid mappings which are now stale, whether
3066 * or not we've got I915_GEM_DOMAIN_CPU.
3068 kfree(obj_priv->page_cpu_valid);
3069 obj_priv->page_cpu_valid = NULL;
3073 * Set the CPU read domain on a range of the object.
3075 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3076 * not entirely valid. The page_cpu_valid member of the object flags which
3077 * pages have been flushed, and will be respected by
3078 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3079 * of the whole object.
3081 * This function returns when the move is complete, including waiting on
3085 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
3086 uint64_t offset, uint64_t size)
3088 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3089 uint32_t old_read_domains;
3092 if (offset == 0 && size == obj->size)
3093 return i915_gem_object_set_to_cpu_domain(obj, 0);
3095 i915_gem_object_flush_gpu_write_domain(obj);
3096 /* Wait on any GPU rendering and flushing to occur. */
3097 ret = i915_gem_object_wait_rendering(obj);
3100 i915_gem_object_flush_gtt_write_domain(obj);
3102 /* If we're already fully in the CPU read domain, we're done. */
3103 if (obj_priv->page_cpu_valid == NULL &&
3104 (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0)
3107 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3108 * newly adding I915_GEM_DOMAIN_CPU
3110 if (obj_priv->page_cpu_valid == NULL) {
3111 obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE,
3113 if (obj_priv->page_cpu_valid == NULL)
3115 } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0)
3116 memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE);
3118 /* Flush the cache on any pages that are still invalid from the CPU's
3121 for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
3123 if (obj_priv->page_cpu_valid[i])
3126 drm_clflush_pages(obj_priv->pages + i, 1);
3128 obj_priv->page_cpu_valid[i] = 1;
3131 /* It should now be out of any other write domains, and we can update
3132 * the domain values for our changes.
3134 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3136 old_read_domains = obj->read_domains;
3137 obj->read_domains |= I915_GEM_DOMAIN_CPU;
3139 trace_i915_gem_object_change_domain(obj,
3147 * Pin an object to the GTT and evaluate the relocations landing in it.
3150 i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
3151 struct drm_file *file_priv,
3152 struct drm_i915_gem_exec_object *entry,
3153 struct drm_i915_gem_relocation_entry *relocs)
3155 struct drm_device *dev = obj->dev;
3156 drm_i915_private_t *dev_priv = dev->dev_private;
3157 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3159 void __iomem *reloc_page;
3161 /* Choose the GTT offset for our buffer and put it there. */
3162 ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
3166 entry->offset = obj_priv->gtt_offset;
3168 /* Apply the relocations, using the GTT aperture to avoid cache
3169 * flushing requirements.
3171 for (i = 0; i < entry->relocation_count; i++) {
3172 struct drm_i915_gem_relocation_entry *reloc= &relocs[i];
3173 struct drm_gem_object *target_obj;
3174 struct drm_i915_gem_object *target_obj_priv;
3175 uint32_t reloc_val, reloc_offset;
3176 uint32_t __iomem *reloc_entry;
3178 target_obj = drm_gem_object_lookup(obj->dev, file_priv,
3179 reloc->target_handle);
3180 if (target_obj == NULL) {
3181 i915_gem_object_unpin(obj);
3184 target_obj_priv = target_obj->driver_private;
3187 DRM_INFO("%s: obj %p offset %08x target %d "
3188 "read %08x write %08x gtt %08x "
3189 "presumed %08x delta %08x\n",
3192 (int) reloc->offset,
3193 (int) reloc->target_handle,
3194 (int) reloc->read_domains,
3195 (int) reloc->write_domain,
3196 (int) target_obj_priv->gtt_offset,
3197 (int) reloc->presumed_offset,
3201 /* The target buffer should have appeared before us in the
3202 * exec_object list, so it should have a GTT space bound by now.
3204 if (target_obj_priv->gtt_space == NULL) {
3205 DRM_ERROR("No GTT space found for object %d\n",
3206 reloc->target_handle);
3207 drm_gem_object_unreference(target_obj);
3208 i915_gem_object_unpin(obj);
3212 /* Validate that the target is in a valid r/w GPU domain */
3213 if (reloc->write_domain & I915_GEM_DOMAIN_CPU ||
3214 reloc->read_domains & I915_GEM_DOMAIN_CPU) {
3215 DRM_ERROR("reloc with read/write CPU domains: "
3216 "obj %p target %d offset %d "
3217 "read %08x write %08x",
3218 obj, reloc->target_handle,
3219 (int) reloc->offset,
3220 reloc->read_domains,
3221 reloc->write_domain);
3222 drm_gem_object_unreference(target_obj);
3223 i915_gem_object_unpin(obj);
3226 if (reloc->write_domain && target_obj->pending_write_domain &&
3227 reloc->write_domain != target_obj->pending_write_domain) {
3228 DRM_ERROR("Write domain conflict: "
3229 "obj %p target %d offset %d "
3230 "new %08x old %08x\n",
3231 obj, reloc->target_handle,
3232 (int) reloc->offset,
3233 reloc->write_domain,
3234 target_obj->pending_write_domain);
3235 drm_gem_object_unreference(target_obj);
3236 i915_gem_object_unpin(obj);
3240 target_obj->pending_read_domains |= reloc->read_domains;
3241 target_obj->pending_write_domain |= reloc->write_domain;
3243 /* If the relocation already has the right value in it, no
3244 * more work needs to be done.
3246 if (target_obj_priv->gtt_offset == reloc->presumed_offset) {
3247 drm_gem_object_unreference(target_obj);
3251 /* Check that the relocation address is valid... */
3252 if (reloc->offset > obj->size - 4) {
3253 DRM_ERROR("Relocation beyond object bounds: "
3254 "obj %p target %d offset %d size %d.\n",
3255 obj, reloc->target_handle,
3256 (int) reloc->offset, (int) obj->size);
3257 drm_gem_object_unreference(target_obj);
3258 i915_gem_object_unpin(obj);
3261 if (reloc->offset & 3) {
3262 DRM_ERROR("Relocation not 4-byte aligned: "
3263 "obj %p target %d offset %d.\n",
3264 obj, reloc->target_handle,
3265 (int) reloc->offset);
3266 drm_gem_object_unreference(target_obj);
3267 i915_gem_object_unpin(obj);
3271 /* and points to somewhere within the target object. */
3272 if (reloc->delta >= target_obj->size) {
3273 DRM_ERROR("Relocation beyond target object bounds: "
3274 "obj %p target %d delta %d size %d.\n",
3275 obj, reloc->target_handle,
3276 (int) reloc->delta, (int) target_obj->size);
3277 drm_gem_object_unreference(target_obj);
3278 i915_gem_object_unpin(obj);
3282 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
3284 drm_gem_object_unreference(target_obj);
3285 i915_gem_object_unpin(obj);
3289 /* Map the page containing the relocation we're going to
3292 reloc_offset = obj_priv->gtt_offset + reloc->offset;
3293 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
3296 reloc_entry = (uint32_t __iomem *)(reloc_page +
3297 (reloc_offset & (PAGE_SIZE - 1)));
3298 reloc_val = target_obj_priv->gtt_offset + reloc->delta;
3301 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
3302 obj, (unsigned int) reloc->offset,
3303 readl(reloc_entry), reloc_val);
3305 writel(reloc_val, reloc_entry);
3306 io_mapping_unmap_atomic(reloc_page);
3308 /* The updated presumed offset for this entry will be
3309 * copied back out to the user.
3311 reloc->presumed_offset = target_obj_priv->gtt_offset;
3313 drm_gem_object_unreference(target_obj);
3318 i915_gem_dump_object(obj, 128, __func__, ~0);
3323 /** Dispatch a batchbuffer to the ring
3326 i915_dispatch_gem_execbuffer(struct drm_device *dev,
3327 struct drm_i915_gem_execbuffer *exec,
3328 struct drm_clip_rect *cliprects,
3329 uint64_t exec_offset)
3331 drm_i915_private_t *dev_priv = dev->dev_private;
3332 int nbox = exec->num_cliprects;
3334 uint32_t exec_start, exec_len;
3337 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3338 exec_len = (uint32_t) exec->batch_len;
3340 trace_i915_gem_request_submit(dev, dev_priv->mm.next_gem_seqno + 1);
3342 count = nbox ? nbox : 1;
3344 for (i = 0; i < count; i++) {
3346 int ret = i915_emit_box(dev, cliprects, i,
3347 exec->DR1, exec->DR4);
3352 if (IS_I830(dev) || IS_845G(dev)) {
3354 OUT_RING(MI_BATCH_BUFFER);
3355 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
3356 OUT_RING(exec_start + exec_len - 4);
3361 if (IS_I965G(dev)) {
3362 OUT_RING(MI_BATCH_BUFFER_START |
3364 MI_BATCH_NON_SECURE_I965);
3365 OUT_RING(exec_start);
3367 OUT_RING(MI_BATCH_BUFFER_START |
3369 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
3375 /* XXX breadcrumb */
3379 /* Throttle our rendering by waiting until the ring has completed our requests
3380 * emitted over 20 msec ago.
3382 * Note that if we were to use the current jiffies each time around the loop,
3383 * we wouldn't escape the function with any frames outstanding if the time to
3384 * render a frame was over 20ms.
3386 * This should get us reasonable parallelism between CPU and GPU but also
3387 * relatively low latency when blocking on a particular request to finish.
3390 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
3392 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
3394 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3396 mutex_lock(&dev->struct_mutex);
3397 while (!list_empty(&i915_file_priv->mm.request_list)) {
3398 struct drm_i915_gem_request *request;
3400 request = list_first_entry(&i915_file_priv->mm.request_list,
3401 struct drm_i915_gem_request,
3404 if (time_after_eq(request->emitted_jiffies, recent_enough))
3407 ret = i915_wait_request(dev, request->seqno);
3411 mutex_unlock(&dev->struct_mutex);
3417 i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object *exec_list,
3418 uint32_t buffer_count,
3419 struct drm_i915_gem_relocation_entry **relocs)
3421 uint32_t reloc_count = 0, reloc_index = 0, i;
3425 for (i = 0; i < buffer_count; i++) {
3426 if (reloc_count + exec_list[i].relocation_count < reloc_count)
3428 reloc_count += exec_list[i].relocation_count;
3431 *relocs = drm_calloc_large(reloc_count, sizeof(**relocs));
3432 if (*relocs == NULL)
3435 for (i = 0; i < buffer_count; i++) {
3436 struct drm_i915_gem_relocation_entry __user *user_relocs;
3438 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3440 ret = copy_from_user(&(*relocs)[reloc_index],
3442 exec_list[i].relocation_count *
3445 drm_free_large(*relocs);
3450 reloc_index += exec_list[i].relocation_count;
3457 i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object *exec_list,
3458 uint32_t buffer_count,
3459 struct drm_i915_gem_relocation_entry *relocs)
3461 uint32_t reloc_count = 0, i;
3464 for (i = 0; i < buffer_count; i++) {
3465 struct drm_i915_gem_relocation_entry __user *user_relocs;
3468 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3470 unwritten = copy_to_user(user_relocs,
3471 &relocs[reloc_count],
3472 exec_list[i].relocation_count *
3480 reloc_count += exec_list[i].relocation_count;
3484 drm_free_large(relocs);
3490 i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer *exec,
3491 uint64_t exec_offset)
3493 uint32_t exec_start, exec_len;
3495 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3496 exec_len = (uint32_t) exec->batch_len;
3498 if ((exec_start | exec_len) & 0x7)
3508 i915_gem_execbuffer(struct drm_device *dev, void *data,
3509 struct drm_file *file_priv)
3511 drm_i915_private_t *dev_priv = dev->dev_private;
3512 struct drm_i915_gem_execbuffer *args = data;
3513 struct drm_i915_gem_exec_object *exec_list = NULL;
3514 struct drm_gem_object **object_list = NULL;
3515 struct drm_gem_object *batch_obj;
3516 struct drm_i915_gem_object *obj_priv;
3517 struct drm_clip_rect *cliprects = NULL;
3518 struct drm_i915_gem_relocation_entry *relocs;
3519 int ret, ret2, i, pinned = 0;
3520 uint64_t exec_offset;
3521 uint32_t seqno, flush_domains, reloc_index;
3525 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3526 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3529 if (args->buffer_count < 1) {
3530 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3533 /* Copy in the exec list from userland */
3534 exec_list = drm_calloc_large(sizeof(*exec_list), args->buffer_count);
3535 object_list = drm_calloc_large(sizeof(*object_list), args->buffer_count);
3536 if (exec_list == NULL || object_list == NULL) {
3537 DRM_ERROR("Failed to allocate exec or object list "
3539 args->buffer_count);
3543 ret = copy_from_user(exec_list,
3544 (struct drm_i915_relocation_entry __user *)
3545 (uintptr_t) args->buffers_ptr,
3546 sizeof(*exec_list) * args->buffer_count);
3548 DRM_ERROR("copy %d exec entries failed %d\n",
3549 args->buffer_count, ret);
3553 if (args->num_cliprects != 0) {
3554 cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects),
3556 if (cliprects == NULL)
3559 ret = copy_from_user(cliprects,
3560 (struct drm_clip_rect __user *)
3561 (uintptr_t) args->cliprects_ptr,
3562 sizeof(*cliprects) * args->num_cliprects);
3564 DRM_ERROR("copy %d cliprects failed: %d\n",
3565 args->num_cliprects, ret);
3570 ret = i915_gem_get_relocs_from_user(exec_list, args->buffer_count,
3575 mutex_lock(&dev->struct_mutex);
3577 i915_verify_inactive(dev, __FILE__, __LINE__);
3579 if (atomic_read(&dev_priv->mm.wedged)) {
3580 DRM_ERROR("Execbuf while wedged\n");
3581 mutex_unlock(&dev->struct_mutex);
3586 if (dev_priv->mm.suspended) {
3587 DRM_ERROR("Execbuf while VT-switched.\n");
3588 mutex_unlock(&dev->struct_mutex);
3593 /* Look up object handles */
3594 for (i = 0; i < args->buffer_count; i++) {
3595 object_list[i] = drm_gem_object_lookup(dev, file_priv,
3596 exec_list[i].handle);
3597 if (object_list[i] == NULL) {
3598 DRM_ERROR("Invalid object handle %d at index %d\n",
3599 exec_list[i].handle, i);
3604 obj_priv = object_list[i]->driver_private;
3605 if (obj_priv->in_execbuffer) {
3606 DRM_ERROR("Object %p appears more than once in object list\n",
3611 obj_priv->in_execbuffer = true;
3614 /* Pin and relocate */
3615 for (pin_tries = 0; ; pin_tries++) {
3619 for (i = 0; i < args->buffer_count; i++) {
3620 object_list[i]->pending_read_domains = 0;
3621 object_list[i]->pending_write_domain = 0;
3622 ret = i915_gem_object_pin_and_relocate(object_list[i],
3625 &relocs[reloc_index]);
3629 reloc_index += exec_list[i].relocation_count;
3635 /* error other than GTT full, or we've already tried again */
3636 if (ret != -ENOSPC || pin_tries >= 1) {
3637 if (ret != -ERESTARTSYS) {
3638 unsigned long long total_size = 0;
3639 for (i = 0; i < args->buffer_count; i++)
3640 total_size += object_list[i]->size;
3641 DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes: %d\n",
3642 pinned+1, args->buffer_count,
3644 DRM_ERROR("%d objects [%d pinned], "
3645 "%d object bytes [%d pinned], "
3646 "%d/%d gtt bytes\n",
3647 atomic_read(&dev->object_count),
3648 atomic_read(&dev->pin_count),
3649 atomic_read(&dev->object_memory),
3650 atomic_read(&dev->pin_memory),
3651 atomic_read(&dev->gtt_memory),
3657 /* unpin all of our buffers */
3658 for (i = 0; i < pinned; i++)
3659 i915_gem_object_unpin(object_list[i]);
3662 /* evict everyone we can from the aperture */
3663 ret = i915_gem_evict_everything(dev);
3664 if (ret && ret != -ENOSPC)
3668 /* Set the pending read domains for the batch buffer to COMMAND */
3669 batch_obj = object_list[args->buffer_count-1];
3670 if (batch_obj->pending_write_domain) {
3671 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3675 batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
3677 /* Sanity check the batch buffer, prior to moving objects */
3678 exec_offset = exec_list[args->buffer_count - 1].offset;
3679 ret = i915_gem_check_execbuffer (args, exec_offset);
3681 DRM_ERROR("execbuf with invalid offset/length\n");
3685 i915_verify_inactive(dev, __FILE__, __LINE__);
3687 /* Zero the global flush/invalidate flags. These
3688 * will be modified as new domains are computed
3691 dev->invalidate_domains = 0;
3692 dev->flush_domains = 0;
3694 for (i = 0; i < args->buffer_count; i++) {
3695 struct drm_gem_object *obj = object_list[i];
3697 /* Compute new gpu domains and update invalidate/flush */
3698 i915_gem_object_set_to_gpu_domain(obj);
3701 i915_verify_inactive(dev, __FILE__, __LINE__);
3703 if (dev->invalidate_domains | dev->flush_domains) {
3705 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3707 dev->invalidate_domains,
3708 dev->flush_domains);
3711 dev->invalidate_domains,
3712 dev->flush_domains);
3713 if (dev->flush_domains)
3714 (void)i915_add_request(dev, file_priv,
3715 dev->flush_domains);
3718 for (i = 0; i < args->buffer_count; i++) {
3719 struct drm_gem_object *obj = object_list[i];
3720 uint32_t old_write_domain = obj->write_domain;
3722 obj->write_domain = obj->pending_write_domain;
3723 trace_i915_gem_object_change_domain(obj,
3728 i915_verify_inactive(dev, __FILE__, __LINE__);
3731 for (i = 0; i < args->buffer_count; i++) {
3732 i915_gem_object_check_coherency(object_list[i],
3733 exec_list[i].handle);
3738 i915_gem_dump_object(batch_obj,
3744 /* Exec the batchbuffer */
3745 ret = i915_dispatch_gem_execbuffer(dev, args, cliprects, exec_offset);
3747 DRM_ERROR("dispatch failed %d\n", ret);
3752 * Ensure that the commands in the batch buffer are
3753 * finished before the interrupt fires
3755 flush_domains = i915_retire_commands(dev);
3757 i915_verify_inactive(dev, __FILE__, __LINE__);
3760 * Get a seqno representing the execution of the current buffer,
3761 * which we can wait on. We would like to mitigate these interrupts,
3762 * likely by only creating seqnos occasionally (so that we have
3763 * *some* interrupts representing completion of buffers that we can
3764 * wait on when trying to clear up gtt space).
3766 seqno = i915_add_request(dev, file_priv, flush_domains);
3768 for (i = 0; i < args->buffer_count; i++) {
3769 struct drm_gem_object *obj = object_list[i];
3771 i915_gem_object_move_to_active(obj, seqno);
3773 DRM_INFO("%s: move to exec list %p\n", __func__, obj);
3777 i915_dump_lru(dev, __func__);
3780 i915_verify_inactive(dev, __FILE__, __LINE__);
3783 for (i = 0; i < pinned; i++)
3784 i915_gem_object_unpin(object_list[i]);
3786 for (i = 0; i < args->buffer_count; i++) {
3787 if (object_list[i]) {
3788 obj_priv = object_list[i]->driver_private;
3789 obj_priv->in_execbuffer = false;
3791 drm_gem_object_unreference(object_list[i]);
3794 mutex_unlock(&dev->struct_mutex);
3797 /* Copy the new buffer offsets back to the user's exec list. */
3798 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
3799 (uintptr_t) args->buffers_ptr,
3801 sizeof(*exec_list) * args->buffer_count);
3804 DRM_ERROR("failed to copy %d exec entries "
3805 "back to user (%d)\n",
3806 args->buffer_count, ret);
3810 /* Copy the updated relocations out regardless of current error
3811 * state. Failure to update the relocs would mean that the next
3812 * time userland calls execbuf, it would do so with presumed offset
3813 * state that didn't match the actual object state.
3815 ret2 = i915_gem_put_relocs_to_user(exec_list, args->buffer_count,
3818 DRM_ERROR("Failed to copy relocations back out: %d\n", ret2);
3825 drm_free_large(object_list);
3826 drm_free_large(exec_list);
3833 i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
3835 struct drm_device *dev = obj->dev;
3836 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3839 i915_verify_inactive(dev, __FILE__, __LINE__);
3840 if (obj_priv->gtt_space == NULL) {
3841 ret = i915_gem_object_bind_to_gtt(obj, alignment);
3846 * Pre-965 chips need a fence register set up in order to
3847 * properly handle tiled surfaces.
3849 if (!IS_I965G(dev) && obj_priv->tiling_mode != I915_TILING_NONE) {
3850 ret = i915_gem_object_get_fence_reg(obj);
3852 if (ret != -EBUSY && ret != -ERESTARTSYS)
3853 DRM_ERROR("Failure to install fence: %d\n",
3858 obj_priv->pin_count++;
3860 /* If the object is not active and not pending a flush,
3861 * remove it from the inactive list
3863 if (obj_priv->pin_count == 1) {
3864 atomic_inc(&dev->pin_count);
3865 atomic_add(obj->size, &dev->pin_memory);
3866 if (!obj_priv->active &&
3867 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0 &&
3868 !list_empty(&obj_priv->list))
3869 list_del_init(&obj_priv->list);
3871 i915_verify_inactive(dev, __FILE__, __LINE__);
3877 i915_gem_object_unpin(struct drm_gem_object *obj)
3879 struct drm_device *dev = obj->dev;
3880 drm_i915_private_t *dev_priv = dev->dev_private;
3881 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3883 i915_verify_inactive(dev, __FILE__, __LINE__);
3884 obj_priv->pin_count--;
3885 BUG_ON(obj_priv->pin_count < 0);
3886 BUG_ON(obj_priv->gtt_space == NULL);
3888 /* If the object is no longer pinned, and is
3889 * neither active nor being flushed, then stick it on
3892 if (obj_priv->pin_count == 0) {
3893 if (!obj_priv->active &&
3894 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
3895 list_move_tail(&obj_priv->list,
3896 &dev_priv->mm.inactive_list);
3897 atomic_dec(&dev->pin_count);
3898 atomic_sub(obj->size, &dev->pin_memory);
3900 i915_verify_inactive(dev, __FILE__, __LINE__);
3904 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3905 struct drm_file *file_priv)
3907 struct drm_i915_gem_pin *args = data;
3908 struct drm_gem_object *obj;
3909 struct drm_i915_gem_object *obj_priv;
3912 mutex_lock(&dev->struct_mutex);
3914 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
3916 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
3918 mutex_unlock(&dev->struct_mutex);
3921 obj_priv = obj->driver_private;
3923 if (obj_priv->madv != I915_MADV_WILLNEED) {
3924 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3925 drm_gem_object_unreference(obj);
3926 mutex_unlock(&dev->struct_mutex);
3930 if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) {
3931 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3933 drm_gem_object_unreference(obj);
3934 mutex_unlock(&dev->struct_mutex);
3938 obj_priv->user_pin_count++;
3939 obj_priv->pin_filp = file_priv;
3940 if (obj_priv->user_pin_count == 1) {
3941 ret = i915_gem_object_pin(obj, args->alignment);
3943 drm_gem_object_unreference(obj);
3944 mutex_unlock(&dev->struct_mutex);
3949 /* XXX - flush the CPU caches for pinned objects
3950 * as the X server doesn't manage domains yet
3952 i915_gem_object_flush_cpu_write_domain(obj);
3953 args->offset = obj_priv->gtt_offset;
3954 drm_gem_object_unreference(obj);
3955 mutex_unlock(&dev->struct_mutex);
3961 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3962 struct drm_file *file_priv)
3964 struct drm_i915_gem_pin *args = data;
3965 struct drm_gem_object *obj;
3966 struct drm_i915_gem_object *obj_priv;
3968 mutex_lock(&dev->struct_mutex);
3970 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
3972 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
3974 mutex_unlock(&dev->struct_mutex);
3978 obj_priv = obj->driver_private;
3979 if (obj_priv->pin_filp != file_priv) {
3980 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3982 drm_gem_object_unreference(obj);
3983 mutex_unlock(&dev->struct_mutex);
3986 obj_priv->user_pin_count--;
3987 if (obj_priv->user_pin_count == 0) {
3988 obj_priv->pin_filp = NULL;
3989 i915_gem_object_unpin(obj);
3992 drm_gem_object_unreference(obj);
3993 mutex_unlock(&dev->struct_mutex);
3998 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3999 struct drm_file *file_priv)
4001 struct drm_i915_gem_busy *args = data;
4002 struct drm_gem_object *obj;
4003 struct drm_i915_gem_object *obj_priv;
4005 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4007 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
4012 mutex_lock(&dev->struct_mutex);
4013 /* Update the active list for the hardware's current position.
4014 * Otherwise this only updates on a delayed timer or when irqs are
4015 * actually unmasked, and our working set ends up being larger than
4018 i915_gem_retire_requests(dev);
4020 obj_priv = obj->driver_private;
4021 /* Don't count being on the flushing list against the object being
4022 * done. Otherwise, a buffer left on the flushing list but not getting
4023 * flushed (because nobody's flushing that domain) won't ever return
4024 * unbusy and get reused by libdrm's bo cache. The other expected
4025 * consumer of this interface, OpenGL's occlusion queries, also specs
4026 * that the objects get unbusy "eventually" without any interference.
4028 args->busy = obj_priv->active && obj_priv->last_rendering_seqno != 0;
4030 drm_gem_object_unreference(obj);
4031 mutex_unlock(&dev->struct_mutex);
4036 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4037 struct drm_file *file_priv)
4039 return i915_gem_ring_throttle(dev, file_priv);
4043 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4044 struct drm_file *file_priv)
4046 struct drm_i915_gem_madvise *args = data;
4047 struct drm_gem_object *obj;
4048 struct drm_i915_gem_object *obj_priv;
4050 switch (args->madv) {
4051 case I915_MADV_DONTNEED:
4052 case I915_MADV_WILLNEED:
4058 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4060 DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n",
4065 mutex_lock(&dev->struct_mutex);
4066 obj_priv = obj->driver_private;
4068 if (obj_priv->pin_count) {
4069 drm_gem_object_unreference(obj);
4070 mutex_unlock(&dev->struct_mutex);
4072 DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n");
4076 if (obj_priv->madv != __I915_MADV_PURGED)
4077 obj_priv->madv = args->madv;
4079 /* if the object is no longer bound, discard its backing storage */
4080 if (i915_gem_object_is_purgeable(obj_priv) &&
4081 obj_priv->gtt_space == NULL)
4082 i915_gem_object_truncate(obj);
4084 args->retained = obj_priv->madv != __I915_MADV_PURGED;
4086 drm_gem_object_unreference(obj);
4087 mutex_unlock(&dev->struct_mutex);
4092 int i915_gem_init_object(struct drm_gem_object *obj)
4094 struct drm_i915_gem_object *obj_priv;
4096 obj_priv = kzalloc(sizeof(*obj_priv), GFP_KERNEL);
4097 if (obj_priv == NULL)
4101 * We've just allocated pages from the kernel,
4102 * so they've just been written by the CPU with
4103 * zeros. They'll need to be clflushed before we
4104 * use them with the GPU.
4106 obj->write_domain = I915_GEM_DOMAIN_CPU;
4107 obj->read_domains = I915_GEM_DOMAIN_CPU;
4109 obj_priv->agp_type = AGP_USER_MEMORY;
4111 obj->driver_private = obj_priv;
4112 obj_priv->obj = obj;
4113 obj_priv->fence_reg = I915_FENCE_REG_NONE;
4114 INIT_LIST_HEAD(&obj_priv->list);
4115 INIT_LIST_HEAD(&obj_priv->fence_list);
4116 obj_priv->madv = I915_MADV_WILLNEED;
4118 trace_i915_gem_object_create(obj);
4123 void i915_gem_free_object(struct drm_gem_object *obj)
4125 struct drm_device *dev = obj->dev;
4126 struct drm_i915_gem_object *obj_priv = obj->driver_private;
4128 trace_i915_gem_object_destroy(obj);
4130 while (obj_priv->pin_count > 0)
4131 i915_gem_object_unpin(obj);
4133 if (obj_priv->phys_obj)
4134 i915_gem_detach_phys_object(dev, obj);
4136 i915_gem_object_unbind(obj);
4138 if (obj_priv->mmap_offset)
4139 i915_gem_free_mmap_offset(obj);
4141 kfree(obj_priv->page_cpu_valid);
4142 kfree(obj_priv->bit_17);
4143 kfree(obj->driver_private);
4146 /** Unbinds all inactive objects. */
4148 i915_gem_evict_from_inactive_list(struct drm_device *dev)
4150 drm_i915_private_t *dev_priv = dev->dev_private;
4152 while (!list_empty(&dev_priv->mm.inactive_list)) {
4153 struct drm_gem_object *obj;
4156 obj = list_first_entry(&dev_priv->mm.inactive_list,
4157 struct drm_i915_gem_object,
4160 ret = i915_gem_object_unbind(obj);
4162 DRM_ERROR("Error unbinding object: %d\n", ret);
4171 i915_gem_idle(struct drm_device *dev)
4173 drm_i915_private_t *dev_priv = dev->dev_private;
4174 uint32_t seqno, cur_seqno, last_seqno;
4177 mutex_lock(&dev->struct_mutex);
4179 if (dev_priv->mm.suspended || dev_priv->ring.ring_obj == NULL) {
4180 mutex_unlock(&dev->struct_mutex);
4184 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4185 * We need to replace this with a semaphore, or something.
4187 dev_priv->mm.suspended = 1;
4188 del_timer(&dev_priv->hangcheck_timer);
4190 /* Cancel the retire work handler, wait for it to finish if running
4192 mutex_unlock(&dev->struct_mutex);
4193 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4194 mutex_lock(&dev->struct_mutex);
4196 i915_kernel_lost_context(dev);
4198 /* Flush the GPU along with all non-CPU write domains
4200 i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
4201 seqno = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS);
4204 mutex_unlock(&dev->struct_mutex);
4208 dev_priv->mm.waiting_gem_seqno = seqno;
4212 cur_seqno = i915_get_gem_seqno(dev);
4213 if (i915_seqno_passed(cur_seqno, seqno))
4215 if (last_seqno == cur_seqno) {
4216 if (stuck++ > 100) {
4217 DRM_ERROR("hardware wedged\n");
4218 atomic_set(&dev_priv->mm.wedged, 1);
4219 DRM_WAKEUP(&dev_priv->irq_queue);
4224 last_seqno = cur_seqno;
4226 dev_priv->mm.waiting_gem_seqno = 0;
4228 i915_gem_retire_requests(dev);
4230 spin_lock(&dev_priv->mm.active_list_lock);
4231 if (!atomic_read(&dev_priv->mm.wedged)) {
4232 /* Active and flushing should now be empty as we've
4233 * waited for a sequence higher than any pending execbuffer
4235 WARN_ON(!list_empty(&dev_priv->mm.active_list));
4236 WARN_ON(!list_empty(&dev_priv->mm.flushing_list));
4237 /* Request should now be empty as we've also waited
4238 * for the last request in the list
4240 WARN_ON(!list_empty(&dev_priv->mm.request_list));
4243 /* Empty the active and flushing lists to inactive. If there's
4244 * anything left at this point, it means that we're wedged and
4245 * nothing good's going to happen by leaving them there. So strip
4246 * the GPU domains and just stuff them onto inactive.
4248 while (!list_empty(&dev_priv->mm.active_list)) {
4249 struct drm_gem_object *obj;
4250 uint32_t old_write_domain;
4252 obj = list_first_entry(&dev_priv->mm.active_list,
4253 struct drm_i915_gem_object,
4255 old_write_domain = obj->write_domain;
4256 obj->write_domain &= ~I915_GEM_GPU_DOMAINS;
4257 i915_gem_object_move_to_inactive(obj);
4259 trace_i915_gem_object_change_domain(obj,
4263 spin_unlock(&dev_priv->mm.active_list_lock);
4265 while (!list_empty(&dev_priv->mm.flushing_list)) {
4266 struct drm_gem_object *obj;
4267 uint32_t old_write_domain;
4269 obj = list_first_entry(&dev_priv->mm.flushing_list,
4270 struct drm_i915_gem_object,
4272 old_write_domain = obj->write_domain;
4273 obj->write_domain &= ~I915_GEM_GPU_DOMAINS;
4274 i915_gem_object_move_to_inactive(obj);
4276 trace_i915_gem_object_change_domain(obj,
4282 /* Move all inactive buffers out of the GTT. */
4283 ret = i915_gem_evict_from_inactive_list(dev);
4284 WARN_ON(!list_empty(&dev_priv->mm.inactive_list));
4286 mutex_unlock(&dev->struct_mutex);
4290 i915_gem_cleanup_ringbuffer(dev);
4291 mutex_unlock(&dev->struct_mutex);
4297 i915_gem_init_hws(struct drm_device *dev)
4299 drm_i915_private_t *dev_priv = dev->dev_private;
4300 struct drm_gem_object *obj;
4301 struct drm_i915_gem_object *obj_priv;
4304 /* If we need a physical address for the status page, it's already
4305 * initialized at driver load time.
4307 if (!I915_NEED_GFX_HWS(dev))
4310 obj = drm_gem_object_alloc(dev, 4096);
4312 DRM_ERROR("Failed to allocate status page\n");
4315 obj_priv = obj->driver_private;
4316 obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
4318 ret = i915_gem_object_pin(obj, 4096);
4320 drm_gem_object_unreference(obj);
4324 dev_priv->status_gfx_addr = obj_priv->gtt_offset;
4326 dev_priv->hw_status_page = kmap(obj_priv->pages[0]);
4327 if (dev_priv->hw_status_page == NULL) {
4328 DRM_ERROR("Failed to map status page.\n");
4329 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
4330 i915_gem_object_unpin(obj);
4331 drm_gem_object_unreference(obj);
4334 dev_priv->hws_obj = obj;
4335 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
4336 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
4337 I915_READ(HWS_PGA); /* posting read */
4338 DRM_DEBUG("hws offset: 0x%08x\n", dev_priv->status_gfx_addr);
4344 i915_gem_cleanup_hws(struct drm_device *dev)
4346 drm_i915_private_t *dev_priv = dev->dev_private;
4347 struct drm_gem_object *obj;
4348 struct drm_i915_gem_object *obj_priv;
4350 if (dev_priv->hws_obj == NULL)
4353 obj = dev_priv->hws_obj;
4354 obj_priv = obj->driver_private;
4356 kunmap(obj_priv->pages[0]);
4357 i915_gem_object_unpin(obj);
4358 drm_gem_object_unreference(obj);
4359 dev_priv->hws_obj = NULL;
4361 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
4362 dev_priv->hw_status_page = NULL;
4364 /* Write high address into HWS_PGA when disabling. */
4365 I915_WRITE(HWS_PGA, 0x1ffff000);
4369 i915_gem_init_ringbuffer(struct drm_device *dev)
4371 drm_i915_private_t *dev_priv = dev->dev_private;
4372 struct drm_gem_object *obj;
4373 struct drm_i915_gem_object *obj_priv;
4374 drm_i915_ring_buffer_t *ring = &dev_priv->ring;
4378 ret = i915_gem_init_hws(dev);
4382 obj = drm_gem_object_alloc(dev, 128 * 1024);
4384 DRM_ERROR("Failed to allocate ringbuffer\n");
4385 i915_gem_cleanup_hws(dev);
4388 obj_priv = obj->driver_private;
4390 ret = i915_gem_object_pin(obj, 4096);
4392 drm_gem_object_unreference(obj);
4393 i915_gem_cleanup_hws(dev);
4397 /* Set up the kernel mapping for the ring. */
4398 ring->Size = obj->size;
4400 ring->map.offset = dev->agp->base + obj_priv->gtt_offset;
4401 ring->map.size = obj->size;
4403 ring->map.flags = 0;
4406 drm_core_ioremap_wc(&ring->map, dev);
4407 if (ring->map.handle == NULL) {
4408 DRM_ERROR("Failed to map ringbuffer.\n");
4409 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
4410 i915_gem_object_unpin(obj);
4411 drm_gem_object_unreference(obj);
4412 i915_gem_cleanup_hws(dev);
4415 ring->ring_obj = obj;
4416 ring->virtual_start = ring->map.handle;
4418 /* Stop the ring if it's running. */
4419 I915_WRITE(PRB0_CTL, 0);
4420 I915_WRITE(PRB0_TAIL, 0);
4421 I915_WRITE(PRB0_HEAD, 0);
4423 /* Initialize the ring. */
4424 I915_WRITE(PRB0_START, obj_priv->gtt_offset);
4425 head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4427 /* G45 ring initialization fails to reset head to zero */
4429 DRM_ERROR("Ring head not reset to zero "
4430 "ctl %08x head %08x tail %08x start %08x\n",
4431 I915_READ(PRB0_CTL),
4432 I915_READ(PRB0_HEAD),
4433 I915_READ(PRB0_TAIL),
4434 I915_READ(PRB0_START));
4435 I915_WRITE(PRB0_HEAD, 0);
4437 DRM_ERROR("Ring head forced to zero "
4438 "ctl %08x head %08x tail %08x start %08x\n",
4439 I915_READ(PRB0_CTL),
4440 I915_READ(PRB0_HEAD),
4441 I915_READ(PRB0_TAIL),
4442 I915_READ(PRB0_START));
4445 I915_WRITE(PRB0_CTL,
4446 ((obj->size - 4096) & RING_NR_PAGES) |
4450 head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4452 /* If the head is still not zero, the ring is dead */
4454 DRM_ERROR("Ring initialization failed "
4455 "ctl %08x head %08x tail %08x start %08x\n",
4456 I915_READ(PRB0_CTL),
4457 I915_READ(PRB0_HEAD),
4458 I915_READ(PRB0_TAIL),
4459 I915_READ(PRB0_START));
4463 /* Update our cache of the ring state */
4464 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4465 i915_kernel_lost_context(dev);
4467 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4468 ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
4469 ring->space = ring->head - (ring->tail + 8);
4470 if (ring->space < 0)
4471 ring->space += ring->Size;
4478 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4480 drm_i915_private_t *dev_priv = dev->dev_private;
4482 if (dev_priv->ring.ring_obj == NULL)
4485 drm_core_ioremapfree(&dev_priv->ring.map, dev);
4487 i915_gem_object_unpin(dev_priv->ring.ring_obj);
4488 drm_gem_object_unreference(dev_priv->ring.ring_obj);
4489 dev_priv->ring.ring_obj = NULL;
4490 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
4492 i915_gem_cleanup_hws(dev);
4496 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4497 struct drm_file *file_priv)
4499 drm_i915_private_t *dev_priv = dev->dev_private;
4502 if (drm_core_check_feature(dev, DRIVER_MODESET))
4505 if (atomic_read(&dev_priv->mm.wedged)) {
4506 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4507 atomic_set(&dev_priv->mm.wedged, 0);
4510 mutex_lock(&dev->struct_mutex);
4511 dev_priv->mm.suspended = 0;
4513 ret = i915_gem_init_ringbuffer(dev);
4515 mutex_unlock(&dev->struct_mutex);
4519 spin_lock(&dev_priv->mm.active_list_lock);
4520 BUG_ON(!list_empty(&dev_priv->mm.active_list));
4521 spin_unlock(&dev_priv->mm.active_list_lock);
4523 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
4524 BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
4525 BUG_ON(!list_empty(&dev_priv->mm.request_list));
4526 mutex_unlock(&dev->struct_mutex);
4528 drm_irq_install(dev);
4534 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4535 struct drm_file *file_priv)
4537 if (drm_core_check_feature(dev, DRIVER_MODESET))
4540 drm_irq_uninstall(dev);
4541 return i915_gem_idle(dev);
4545 i915_gem_lastclose(struct drm_device *dev)
4549 if (drm_core_check_feature(dev, DRIVER_MODESET))
4552 ret = i915_gem_idle(dev);
4554 DRM_ERROR("failed to idle hardware: %d\n", ret);
4558 i915_gem_load(struct drm_device *dev)
4561 drm_i915_private_t *dev_priv = dev->dev_private;
4563 spin_lock_init(&dev_priv->mm.active_list_lock);
4564 INIT_LIST_HEAD(&dev_priv->mm.active_list);
4565 INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
4566 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4567 INIT_LIST_HEAD(&dev_priv->mm.request_list);
4568 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4569 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4570 i915_gem_retire_work_handler);
4571 dev_priv->mm.next_gem_seqno = 1;
4573 spin_lock(&shrink_list_lock);
4574 list_add(&dev_priv->mm.shrink_list, &shrink_list);
4575 spin_unlock(&shrink_list_lock);
4577 /* Old X drivers will take 0-2 for front, back, depth buffers */
4578 dev_priv->fence_reg_start = 3;
4580 if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4581 dev_priv->num_fence_regs = 16;
4583 dev_priv->num_fence_regs = 8;
4585 /* Initialize fence registers to zero */
4586 if (IS_I965G(dev)) {
4587 for (i = 0; i < 16; i++)
4588 I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0);
4590 for (i = 0; i < 8; i++)
4591 I915_WRITE(FENCE_REG_830_0 + (i * 4), 0);
4592 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4593 for (i = 0; i < 8; i++)
4594 I915_WRITE(FENCE_REG_945_8 + (i * 4), 0);
4597 i915_gem_detect_bit_6_swizzle(dev);
4601 * Create a physically contiguous memory object for this object
4602 * e.g. for cursor + overlay regs
4604 int i915_gem_init_phys_object(struct drm_device *dev,
4607 drm_i915_private_t *dev_priv = dev->dev_private;
4608 struct drm_i915_gem_phys_object *phys_obj;
4611 if (dev_priv->mm.phys_objs[id - 1] || !size)
4614 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4620 phys_obj->handle = drm_pci_alloc(dev, size, 0);
4621 if (!phys_obj->handle) {
4626 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4629 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4637 void i915_gem_free_phys_object(struct drm_device *dev, int id)
4639 drm_i915_private_t *dev_priv = dev->dev_private;
4640 struct drm_i915_gem_phys_object *phys_obj;
4642 if (!dev_priv->mm.phys_objs[id - 1])
4645 phys_obj = dev_priv->mm.phys_objs[id - 1];
4646 if (phys_obj->cur_obj) {
4647 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4651 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4653 drm_pci_free(dev, phys_obj->handle);
4655 dev_priv->mm.phys_objs[id - 1] = NULL;
4658 void i915_gem_free_all_phys_object(struct drm_device *dev)
4662 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4663 i915_gem_free_phys_object(dev, i);
4666 void i915_gem_detach_phys_object(struct drm_device *dev,
4667 struct drm_gem_object *obj)
4669 struct drm_i915_gem_object *obj_priv;
4674 obj_priv = obj->driver_private;
4675 if (!obj_priv->phys_obj)
4678 ret = i915_gem_object_get_pages(obj, 0);
4682 page_count = obj->size / PAGE_SIZE;
4684 for (i = 0; i < page_count; i++) {
4685 char *dst = kmap_atomic(obj_priv->pages[i], KM_USER0);
4686 char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4688 memcpy(dst, src, PAGE_SIZE);
4689 kunmap_atomic(dst, KM_USER0);
4691 drm_clflush_pages(obj_priv->pages, page_count);
4692 drm_agp_chipset_flush(dev);
4694 i915_gem_object_put_pages(obj);
4696 obj_priv->phys_obj->cur_obj = NULL;
4697 obj_priv->phys_obj = NULL;
4701 i915_gem_attach_phys_object(struct drm_device *dev,
4702 struct drm_gem_object *obj, int id)
4704 drm_i915_private_t *dev_priv = dev->dev_private;
4705 struct drm_i915_gem_object *obj_priv;
4710 if (id > I915_MAX_PHYS_OBJECT)
4713 obj_priv = obj->driver_private;
4715 if (obj_priv->phys_obj) {
4716 if (obj_priv->phys_obj->id == id)
4718 i915_gem_detach_phys_object(dev, obj);
4722 /* create a new object */
4723 if (!dev_priv->mm.phys_objs[id - 1]) {
4724 ret = i915_gem_init_phys_object(dev, id,
4727 DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size);
4732 /* bind to the object */
4733 obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1];
4734 obj_priv->phys_obj->cur_obj = obj;
4736 ret = i915_gem_object_get_pages(obj, 0);
4738 DRM_ERROR("failed to get page list\n");
4742 page_count = obj->size / PAGE_SIZE;
4744 for (i = 0; i < page_count; i++) {
4745 char *src = kmap_atomic(obj_priv->pages[i], KM_USER0);
4746 char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4748 memcpy(dst, src, PAGE_SIZE);
4749 kunmap_atomic(src, KM_USER0);
4752 i915_gem_object_put_pages(obj);
4760 i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
4761 struct drm_i915_gem_pwrite *args,
4762 struct drm_file *file_priv)
4764 struct drm_i915_gem_object *obj_priv = obj->driver_private;
4767 char __user *user_data;
4769 user_data = (char __user *) (uintptr_t) args->data_ptr;
4770 obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset;
4772 DRM_DEBUG("obj_addr %p, %lld\n", obj_addr, args->size);
4773 ret = copy_from_user(obj_addr, user_data, args->size);
4777 drm_agp_chipset_flush(dev);
4781 void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv)
4783 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
4785 /* Clean up our request list when the client is going away, so that
4786 * later retire_requests won't dereference our soon-to-be-gone
4789 mutex_lock(&dev->struct_mutex);
4790 while (!list_empty(&i915_file_priv->mm.request_list))
4791 list_del_init(i915_file_priv->mm.request_list.next);
4792 mutex_unlock(&dev->struct_mutex);
4796 i915_gem_shrink(int nr_to_scan, gfp_t gfp_mask)
4798 drm_i915_private_t *dev_priv, *next_dev;
4799 struct drm_i915_gem_object *obj_priv, *next_obj;
4801 int would_deadlock = 1;
4803 /* "fast-path" to count number of available objects */
4804 if (nr_to_scan == 0) {
4805 spin_lock(&shrink_list_lock);
4806 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
4807 struct drm_device *dev = dev_priv->dev;
4809 if (mutex_trylock(&dev->struct_mutex)) {
4810 list_for_each_entry(obj_priv,
4811 &dev_priv->mm.inactive_list,
4814 mutex_unlock(&dev->struct_mutex);
4817 spin_unlock(&shrink_list_lock);
4819 return (cnt / 100) * sysctl_vfs_cache_pressure;
4822 spin_lock(&shrink_list_lock);
4824 /* first scan for clean buffers */
4825 list_for_each_entry_safe(dev_priv, next_dev,
4826 &shrink_list, mm.shrink_list) {
4827 struct drm_device *dev = dev_priv->dev;
4829 if (! mutex_trylock(&dev->struct_mutex))
4832 spin_unlock(&shrink_list_lock);
4834 i915_gem_retire_requests(dev);
4836 list_for_each_entry_safe(obj_priv, next_obj,
4837 &dev_priv->mm.inactive_list,
4839 if (i915_gem_object_is_purgeable(obj_priv)) {
4840 i915_gem_object_unbind(obj_priv->obj);
4841 if (--nr_to_scan <= 0)
4846 spin_lock(&shrink_list_lock);
4847 mutex_unlock(&dev->struct_mutex);
4851 if (nr_to_scan <= 0)
4855 /* second pass, evict/count anything still on the inactive list */
4856 list_for_each_entry_safe(dev_priv, next_dev,
4857 &shrink_list, mm.shrink_list) {
4858 struct drm_device *dev = dev_priv->dev;
4860 if (! mutex_trylock(&dev->struct_mutex))
4863 spin_unlock(&shrink_list_lock);
4865 list_for_each_entry_safe(obj_priv, next_obj,
4866 &dev_priv->mm.inactive_list,
4868 if (nr_to_scan > 0) {
4869 i915_gem_object_unbind(obj_priv->obj);
4875 spin_lock(&shrink_list_lock);
4876 mutex_unlock(&dev->struct_mutex);
4881 spin_unlock(&shrink_list_lock);
4886 return (cnt / 100) * sysctl_vfs_cache_pressure;
4891 static struct shrinker shrinker = {
4892 .shrink = i915_gem_shrink,
4893 .seeks = DEFAULT_SEEKS,
4897 i915_gem_shrinker_init(void)
4899 register_shrinker(&shrinker);
4903 i915_gem_shrinker_exit(void)
4905 unregister_shrinker(&shrinker);