drivers/gpu/drm/i915/i915_gem.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include "drmP.h"
  29 #include "drm.h"
  30 #include "i915_drm.h"
  31 #include "i915_drv.h"
  32 #include <linux/swap.h>
  33
  34 static int
  35 i915_gem_object_set_domain(struct drm_gem_object *obj,
  36                             uint32_t read_domains,
  37                             uint32_t write_domain);
  38 static int
  39 i915_gem_object_set_domain_range(struct drm_gem_object *obj,
  40                                  uint64_t offset,
  41                                  uint64_t size,
  42                                  uint32_t read_domains,
  43                                  uint32_t write_domain);
  44 static int
  45 i915_gem_set_domain(struct drm_gem_object *obj,
  46                     struct drm_file *file_priv,
  47                     uint32_t read_domains,
  48                     uint32_t write_domain);
  49 static int i915_gem_object_get_page_list(struct drm_gem_object *obj);
  50 static void i915_gem_object_free_page_list(struct drm_gem_object *obj);
  51 static int i915_gem_object_wait_rendering(struct drm_gem_object *obj);
  52
  53 static void
  54 i915_gem_cleanup_ringbuffer(struct drm_device *dev);
  55
  56 int
  57 i915_gem_init_ioctl(struct drm_device *dev, void *data,
  58                     struct drm_file *file_priv)
  59 {
  60         drm_i915_private_t *dev_priv = dev->dev_private;
  61         struct drm_i915_gem_init *args = data;
  62
  63         mutex_lock(&dev->struct_mutex);
  64
  65         if (args->gtt_start >= args->gtt_end ||
  66             (args->gtt_start & (PAGE_SIZE - 1)) != 0 ||
  67             (args->gtt_end & (PAGE_SIZE - 1)) != 0) {
  68                 mutex_unlock(&dev->struct_mutex);
  69                 return -EINVAL;
  70         }
  71
  72         drm_mm_init(&dev_priv->mm.gtt_space, args->gtt_start,
  73             args->gtt_end - args->gtt_start);
  74
  75         dev->gtt_total = (uint32_t) (args->gtt_end - args->gtt_start);
  76
  77         mutex_unlock(&dev->struct_mutex);
  78
  79         return 0;
  80 }
  81
  82 int
  83 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
  84                             struct drm_file *file_priv)
  85 {
  86         drm_i915_private_t *dev_priv = dev->dev_private;
  87         struct drm_i915_gem_get_aperture *args = data;
  88         struct drm_i915_gem_object *obj_priv;
  89
  90         if (!(dev->driver->driver_features & DRIVER_GEM))
  91                 return -ENODEV;
  92
  93         args->aper_size = dev->gtt_total;
  94         args->aper_available_size = args->aper_size;
  95
  96         list_for_each_entry(obj_priv, &dev_priv->mm.active_list, list) {
  97                 if (obj_priv->pin_count > 0)
  98                         args->aper_available_size -= obj_priv->obj->size;
  99         }
 100
 101         return 0;
 102 }
 103
 104
 105 /**
 106  * Creates a new mm object and returns a handle to it.
 107  */
 108 int
 109 i915_gem_create_ioctl(struct drm_device *dev, void *data,
 110                       struct drm_file *file_priv)
 111 {
 112         struct drm_i915_gem_create *args = data;
 113         struct drm_gem_object *obj;
 114         int handle, ret;
 115
 116         args->size = roundup(args->size, PAGE_SIZE);
 117
 118         /* Allocate the new object */
 119         obj = drm_gem_object_alloc(dev, args->size);
 120         if (obj == NULL)
 121                 return -ENOMEM;
 122
 123         ret = drm_gem_handle_create(file_priv, obj, &handle);
 124         mutex_lock(&dev->struct_mutex);
 125         drm_gem_object_handle_unreference(obj);
 126         mutex_unlock(&dev->struct_mutex);
 127
 128         if (ret)
 129                 return ret;
 130
 131         args->handle = handle;
 132
 133         return 0;
 134 }
 135
 136 /**
 137  * Reads data from the object referenced by handle.
 138  *
 139  * On error, the contents of *data are undefined.
 140  */
 141 int
 142 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
 143                      struct drm_file *file_priv)
 144 {
 145         struct drm_i915_gem_pread *args = data;
 146         struct drm_gem_object *obj;
 147         struct drm_i915_gem_object *obj_priv;
 148         ssize_t read;
 149         loff_t offset;
 150         int ret;
 151
 152         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
 153         if (obj == NULL)
 154                 return -EBADF;
 155         obj_priv = obj->driver_private;
 156
 157         /* Bounds check source.
 158          *
 159          * XXX: This could use review for overflow issues...
 160          */
 161         if (args->offset > obj->size || args->size > obj->size ||
 162             args->offset + args->size > obj->size) {
 163                 drm_gem_object_unreference(obj);
 164                 return -EINVAL;
 165         }
 166
 167         mutex_lock(&dev->struct_mutex);
 168
 169         ret = i915_gem_object_set_domain_range(obj, args->offset, args->size,
 170                                                I915_GEM_DOMAIN_CPU, 0);
 171         if (ret != 0) {
 172                 drm_gem_object_unreference(obj);
 173                 mutex_unlock(&dev->struct_mutex);
 174                 return ret;
 175         }
 176
 177         offset = args->offset;
 178
 179         read = vfs_read(obj->filp, (char __user *)(uintptr_t)args->data_ptr,
 180                         args->size, &offset);
 181         if (read != args->size) {
 182                 drm_gem_object_unreference(obj);
 183                 mutex_unlock(&dev->struct_mutex);
 184                 if (read < 0)
 185                         return read;
 186                 else
 187                         return -EINVAL;
 188         }
 189
 190         drm_gem_object_unreference(obj);
 191         mutex_unlock(&dev->struct_mutex);
 192
 193         return 0;
 194 }
 195
 196 /*
 197  * Try to write quickly with an atomic kmap. Return true on success.
 198  *
 199  * If this fails (which includes a partial write), we'll redo the whole
 200  * thing with the slow version.
 201  *
 202  * This is a workaround for the low performance of iounmap (approximate
 203  * 10% cpu cost on normal 3D workloads).  kmap_atomic on HIGHMEM kernels
 204  * happens to let us map card memory without taking IPIs.  When the vmap
 205  * rework lands we should be able to dump this hack.
 206  */
 207 static inline int fast_user_write(unsigned long pfn, char __user *user_data,
 208                                   int l, int o)
 209 {
 210 #ifdef CONFIG_HIGHMEM
 211         unsigned long unwritten;
 212         char *vaddr_atomic;
 213
 214         vaddr_atomic = kmap_atomic_pfn(pfn, KM_USER0);
 215 #if WATCH_PWRITE
 216         DRM_INFO("pwrite i %d o %d l %d pfn %ld vaddr %p\n",
 217                  i, o, l, pfn, vaddr_atomic);
 218 #endif
 219         unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + o, user_data, l);
 220         kunmap_atomic(vaddr_atomic, KM_USER0);
 221         return !unwritten;
 222 #else
 223         return 0;
 224 #endif
 225 }
 226
 227 static int
 228 i915_gem_gtt_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
 229                     struct drm_i915_gem_pwrite *args,
 230                     struct drm_file *file_priv)
 231 {
 232         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 233         ssize_t remain;
 234         loff_t offset;
 235         char __user *user_data;
 236         int ret = 0;
 237
 238         user_data = (char __user *) (uintptr_t) args->data_ptr;
 239         remain = args->size;
 240         if (!access_ok(VERIFY_READ, user_data, remain))
 241                 return -EFAULT;
 242
 243
 244         mutex_lock(&dev->struct_mutex);
 245         ret = i915_gem_object_pin(obj, 0);
 246         if (ret) {
 247                 mutex_unlock(&dev->struct_mutex);
 248                 return ret;
 249         }
 250         ret = i915_gem_set_domain(obj, file_priv,
 251                                   I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
 252         if (ret)
 253                 goto fail;
 254
 255         obj_priv = obj->driver_private;
 256         offset = obj_priv->gtt_offset + args->offset;
 257         obj_priv->dirty = 1;
 258
 259         while (remain > 0) {
 260                 unsigned long pfn;
 261                 int i, o, l;
 262
 263                 /* Operation in this page
 264                  *
 265                  * i = page number
 266                  * o = offset within page
 267                  * l = bytes to copy
 268                  */
 269                 i = offset >> PAGE_SHIFT;
 270                 o = offset & (PAGE_SIZE-1);
 271                 l = remain;
 272                 if ((o + l) > PAGE_SIZE)
 273                         l = PAGE_SIZE - o;
 274
 275                 pfn = (dev->agp->base >> PAGE_SHIFT) + i;
 276
 277                 if (!fast_user_write(pfn, user_data, l, o)) {
 278                         unsigned long unwritten;
 279                         char __iomem *vaddr;
 280
 281                         vaddr = ioremap_wc(pfn << PAGE_SHIFT, PAGE_SIZE);
 282 #if WATCH_PWRITE
 283                         DRM_INFO("pwrite slow i %d o %d l %d "
 284                                  "pfn %ld vaddr %p\n",
 285                                  i, o, l, pfn, vaddr);
 286 #endif
 287                         if (vaddr == NULL) {
 288                                 ret = -EFAULT;
 289                                 goto fail;
 290                         }
 291                         unwritten = __copy_from_user(vaddr + o, user_data, l);
 292 #if WATCH_PWRITE
 293                         DRM_INFO("unwritten %ld\n", unwritten);
 294 #endif
 295                         iounmap(vaddr);
 296                         if (unwritten) {
 297                                 ret = -EFAULT;
 298                                 goto fail;
 299                         }
 300                 }
 301
 302                 remain -= l;
 303                 user_data += l;
 304                 offset += l;
 305         }
 306 #if WATCH_PWRITE && 1
 307         i915_gem_clflush_object(obj);
 308         i915_gem_dump_object(obj, args->offset + args->size, __func__, ~0);
 309         i915_gem_clflush_object(obj);
 310 #endif
 311
 312 fail:
 313         i915_gem_object_unpin(obj);
 314         mutex_unlock(&dev->struct_mutex);
 315
 316         return ret;
 317 }
 318
 319 static int
 320 i915_gem_shmem_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
 321                       struct drm_i915_gem_pwrite *args,
 322                       struct drm_file *file_priv)
 323 {
 324         int ret;
 325         loff_t offset;
 326         ssize_t written;
 327
 328         mutex_lock(&dev->struct_mutex);
 329
 330         ret = i915_gem_set_domain(obj, file_priv,
 331                                   I915_GEM_DOMAIN_CPU, I915_GEM_DOMAIN_CPU);
 332         if (ret) {
 333                 mutex_unlock(&dev->struct_mutex);
 334                 return ret;
 335         }
 336
 337         offset = args->offset;
 338
 339         written = vfs_write(obj->filp,
 340                             (char __user *)(uintptr_t) args->data_ptr,
 341                             args->size, &offset);
 342         if (written != args->size) {
 343                 mutex_unlock(&dev->struct_mutex);
 344                 if (written < 0)
 345                         return written;
 346                 else
 347                         return -EINVAL;
 348         }
 349
 350         mutex_unlock(&dev->struct_mutex);
 351
 352         return 0;
 353 }
 354
 355 /**
 356  * Writes data to the object referenced by handle.
 357  *
 358  * On error, the contents of the buffer that were to be modified are undefined.
 359  */
 360 int
 361 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
 362                       struct drm_file *file_priv)
 363 {
 364         struct drm_i915_gem_pwrite *args = data;
 365         struct drm_gem_object *obj;
 366         struct drm_i915_gem_object *obj_priv;
 367         int ret = 0;
 368
 369         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
 370         if (obj == NULL)
 371                 return -EBADF;
 372         obj_priv = obj->driver_private;
 373
 374         /* Bounds check destination.
 375          *
 376          * XXX: This could use review for overflow issues...
 377          */
 378         if (args->offset > obj->size || args->size > obj->size ||
 379             args->offset + args->size > obj->size) {
 380                 drm_gem_object_unreference(obj);
 381                 return -EINVAL;
 382         }
 383
 384         /* We can only do the GTT pwrite on untiled buffers, as otherwise
 385          * it would end up going through the fenced access, and we'll get
 386          * different detiling behavior between reading and writing.
 387          * pread/pwrite currently are reading and writing from the CPU
 388          * perspective, requiring manual detiling by the client.
 389          */
 390         if (obj_priv->tiling_mode == I915_TILING_NONE &&
 391             dev->gtt_total != 0)
 392                 ret = i915_gem_gtt_pwrite(dev, obj, args, file_priv);
 393         else
 394                 ret = i915_gem_shmem_pwrite(dev, obj, args, file_priv);
 395
 396 #if WATCH_PWRITE
 397         if (ret)
 398                 DRM_INFO("pwrite failed %d\n", ret);
 399 #endif
 400
 401         drm_gem_object_unreference(obj);
 402
 403         return ret;
 404 }
 405
 406 /**
 407  * Called when user space prepares to use an object
 408  */
 409 int
 410 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
 411                           struct drm_file *file_priv)
 412 {
 413         struct drm_i915_gem_set_domain *args = data;
 414         struct drm_gem_object *obj;
 415         int ret;
 416
 417         if (!(dev->driver->driver_features & DRIVER_GEM))
 418                 return -ENODEV;
 419
 420         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
 421         if (obj == NULL)
 422                 return -EBADF;
 423
 424         mutex_lock(&dev->struct_mutex);
 425 #if WATCH_BUF
 426         DRM_INFO("set_domain_ioctl %p(%d), %08x %08x\n",
 427                  obj, obj->size, args->read_domains, args->write_domain);
 428 #endif
 429         ret = i915_gem_set_domain(obj, file_priv,
 430                                   args->read_domains, args->write_domain);
 431         drm_gem_object_unreference(obj);
 432         mutex_unlock(&dev->struct_mutex);
 433         return ret;
 434 }
 435
 436 /**
 437  * Called when user space has done writes to this buffer
 438  */
 439 int
 440 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
 441                       struct drm_file *file_priv)
 442 {
 443         struct drm_i915_gem_sw_finish *args = data;
 444         struct drm_gem_object *obj;
 445         struct drm_i915_gem_object *obj_priv;
 446         int ret = 0;
 447
 448         if (!(dev->driver->driver_features & DRIVER_GEM))
 449                 return -ENODEV;
 450
 451         mutex_lock(&dev->struct_mutex);
 452         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
 453         if (obj == NULL) {
 454                 mutex_unlock(&dev->struct_mutex);
 455                 return -EBADF;
 456         }
 457
 458 #if WATCH_BUF
 459         DRM_INFO("%s: sw_finish %d (%p %d)\n",
 460                  __func__, args->handle, obj, obj->size);
 461 #endif
 462         obj_priv = obj->driver_private;
 463
 464         /* Pinned buffers may be scanout, so flush the cache */
 465         if ((obj->write_domain & I915_GEM_DOMAIN_CPU) && obj_priv->pin_count) {
 466                 i915_gem_clflush_object(obj);
 467                 drm_agp_chipset_flush(dev);
 468         }
 469         drm_gem_object_unreference(obj);
 470         mutex_unlock(&dev->struct_mutex);
 471         return ret;
 472 }
 473
 474 /**
 475  * Maps the contents of an object, returning the address it is mapped
 476  * into.
 477  *
 478  * While the mapping holds a reference on the contents of the object, it doesn't
 479  * imply a ref on the object itself.
 480  */
 481 int
 482 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
 483                    struct drm_file *file_priv)
 484 {
 485         struct drm_i915_gem_mmap *args = data;
 486         struct drm_gem_object *obj;
 487         loff_t offset;
 488         unsigned long addr;
 489
 490         if (!(dev->driver->driver_features & DRIVER_GEM))
 491                 return -ENODEV;
 492
 493         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
 494         if (obj == NULL)
 495                 return -EBADF;
 496
 497         offset = args->offset;
 498
 499         down_write(&current->mm->mmap_sem);
 500         addr = do_mmap(obj->filp, 0, args->size,
 501                        PROT_READ | PROT_WRITE, MAP_SHARED,
 502                        args->offset);
 503         up_write(&current->mm->mmap_sem);
 504         mutex_lock(&dev->struct_mutex);
 505         drm_gem_object_unreference(obj);
 506         mutex_unlock(&dev->struct_mutex);
 507         if (IS_ERR((void *)addr))
 508                 return addr;
 509
 510         args->addr_ptr = (uint64_t) addr;
 511
 512         return 0;
 513 }
 514
 515 static void
 516 i915_gem_object_free_page_list(struct drm_gem_object *obj)
 517 {
 518         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 519         int page_count = obj->size / PAGE_SIZE;
 520         int i;
 521
 522         if (obj_priv->page_list == NULL)
 523                 return;
 524
 525
 526         for (i = 0; i < page_count; i++)
 527                 if (obj_priv->page_list[i] != NULL) {
 528                         if (obj_priv->dirty)
 529                                 set_page_dirty(obj_priv->page_list[i]);
 530                         mark_page_accessed(obj_priv->page_list[i]);
 531                         page_cache_release(obj_priv->page_list[i]);
 532                 }
 533         obj_priv->dirty = 0;
 534
 535         drm_free(obj_priv->page_list,
 536                  page_count * sizeof(struct page *),
 537                  DRM_MEM_DRIVER);
 538         obj_priv->page_list = NULL;
 539 }
 540
 541 static void
 542 i915_gem_object_move_to_active(struct drm_gem_object *obj)
 543 {
 544         struct drm_device *dev = obj->dev;
 545         drm_i915_private_t *dev_priv = dev->dev_private;
 546         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 547
 548         /* Add a reference if we're newly entering the active list. */
 549         if (!obj_priv->active) {
 550                 drm_gem_object_reference(obj);
 551                 obj_priv->active = 1;
 552         }
 553         /* Move from whatever list we were on to the tail of execution. */
 554         list_move_tail(&obj_priv->list,
 555                        &dev_priv->mm.active_list);
 556 }
 557
 558
 559 static void
 560 i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
 561 {
 562         struct drm_device *dev = obj->dev;
 563         drm_i915_private_t *dev_priv = dev->dev_private;
 564         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 565
 566         i915_verify_inactive(dev, __FILE__, __LINE__);
 567         if (obj_priv->pin_count != 0)
 568                 list_del_init(&obj_priv->list);
 569         else
 570                 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
 571
 572         if (obj_priv->active) {
 573                 obj_priv->active = 0;
 574                 drm_gem_object_unreference(obj);
 575         }
 576         i915_verify_inactive(dev, __FILE__, __LINE__);
 577 }
 578
 579 /**
 580  * Creates a new sequence number, emitting a write of it to the status page
 581  * plus an interrupt, which will trigger i915_user_interrupt_handler.
 582  *
 583  * Must be called with struct_lock held.
 584  *
 585  * Returned sequence numbers are nonzero on success.
 586  */
 587 static uint32_t
 588 i915_add_request(struct drm_device *dev, uint32_t flush_domains)
 589 {
 590         drm_i915_private_t *dev_priv = dev->dev_private;
 591         struct drm_i915_gem_request *request;
 592         uint32_t seqno;
 593         int was_empty;
 594         RING_LOCALS;
 595
 596         request = drm_calloc(1, sizeof(*request), DRM_MEM_DRIVER);
 597         if (request == NULL)
 598                 return 0;
 599
 600         /* Grab the seqno we're going to make this request be, and bump the
 601          * next (skipping 0 so it can be the reserved no-seqno value).
 602          */
 603         seqno = dev_priv->mm.next_gem_seqno;
 604         dev_priv->mm.next_gem_seqno++;
 605         if (dev_priv->mm.next_gem_seqno == 0)
 606                 dev_priv->mm.next_gem_seqno++;
 607
 608         BEGIN_LP_RING(4);
 609         OUT_RING(MI_STORE_DWORD_INDEX);
 610         OUT_RING(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 611         OUT_RING(seqno);
 612
 613         OUT_RING(MI_USER_INTERRUPT);
 614         ADVANCE_LP_RING();
 615
 616         DRM_DEBUG("%d\n", seqno);
 617
 618         request->seqno = seqno;
 619         request->emitted_jiffies = jiffies;
 620         request->flush_domains = flush_domains;
 621         was_empty = list_empty(&dev_priv->mm.request_list);
 622         list_add_tail(&request->list, &dev_priv->mm.request_list);
 623
 624         if (was_empty && !dev_priv->mm.suspended)
 625                 schedule_delayed_work(&dev_priv->mm.retire_work, HZ);
 626         return seqno;
 627 }
 628
 629 /**
 630  * Command execution barrier
 631  *
 632  * Ensures that all commands in the ring are finished
 633  * before signalling the CPU
 634  */
 635 static uint32_t
 636 i915_retire_commands(struct drm_device *dev)
 637 {
 638         drm_i915_private_t *dev_priv = dev->dev_private;
 639         uint32_t cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
 640         uint32_t flush_domains = 0;
 641         RING_LOCALS;
 642
 643         /* The sampler always gets flushed on i965 (sigh) */
 644         if (IS_I965G(dev))
 645                 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
 646         BEGIN_LP_RING(2);
 647         OUT_RING(cmd);
 648         OUT_RING(0); /* noop */
 649         ADVANCE_LP_RING();
 650         return flush_domains;
 651 }
 652
 653 /**
 654  * Moves buffers associated only with the given active seqno from the active
 655  * to inactive list, potentially freeing them.
 656  */
 657 static void
 658 i915_gem_retire_request(struct drm_device *dev,
 659                         struct drm_i915_gem_request *request)
 660 {
 661         drm_i915_private_t *dev_priv = dev->dev_private;
 662
 663         /* Move any buffers on the active list that are no longer referenced
 664          * by the ringbuffer to the flushing/inactive lists as appropriate.
 665          */
 666         while (!list_empty(&dev_priv->mm.active_list)) {
 667                 struct drm_gem_object *obj;
 668                 struct drm_i915_gem_object *obj_priv;
 669
 670                 obj_priv = list_first_entry(&dev_priv->mm.active_list,
 671                                             struct drm_i915_gem_object,
 672                                             list);
 673                 obj = obj_priv->obj;
 674
 675                 /* If the seqno being retired doesn't match the oldest in the
 676                  * list, then the oldest in the list must still be newer than
 677                  * this seqno.
 678                  */
 679                 if (obj_priv->last_rendering_seqno != request->seqno)
 680                         return;
 681 #if WATCH_LRU
 682                 DRM_INFO("%s: retire %d moves to inactive list %p\n",
 683                          __func__, request->seqno, obj);
 684 #endif
 685
 686                 if (obj->write_domain != 0) {
 687                         list_move_tail(&obj_priv->list,
 688                                        &dev_priv->mm.flushing_list);
 689                 } else {
 690                         i915_gem_object_move_to_inactive(obj);
 691                 }
 692         }
 693
 694         if (request->flush_domains != 0) {
 695                 struct drm_i915_gem_object *obj_priv, *next;
 696
 697                 /* Clear the write domain and activity from any buffers
 698                  * that are just waiting for a flush matching the one retired.
 699                  */
 700                 list_for_each_entry_safe(obj_priv, next,
 701                                          &dev_priv->mm.flushing_list, list) {
 702                         struct drm_gem_object *obj = obj_priv->obj;
 703
 704                         if (obj->write_domain & request->flush_domains) {
 705                                 obj->write_domain = 0;
 706                                 i915_gem_object_move_to_inactive(obj);
 707                         }
 708                 }
 709
 710         }
 711 }
 712
 713 /**
 714  * Returns true if seq1 is later than seq2.
 715  */
 716 static int
 717 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
 718 {
 719         return (int32_t)(seq1 - seq2) >= 0;
 720 }
 721
 722 uint32_t
 723 i915_get_gem_seqno(struct drm_device *dev)
 724 {
 725         drm_i915_private_t *dev_priv = dev->dev_private;
 726
 727         return READ_HWSP(dev_priv, I915_GEM_HWS_INDEX);
 728 }
 729
 730 /**
 731  * This function clears the request list as sequence numbers are passed.
 732  */
 733 void
 734 i915_gem_retire_requests(struct drm_device *dev)
 735 {
 736         drm_i915_private_t *dev_priv = dev->dev_private;
 737         uint32_t seqno;
 738
 739         seqno = i915_get_gem_seqno(dev);
 740
 741         while (!list_empty(&dev_priv->mm.request_list)) {
 742                 struct drm_i915_gem_request *request;
 743                 uint32_t retiring_seqno;
 744
 745                 request = list_first_entry(&dev_priv->mm.request_list,
 746                                            struct drm_i915_gem_request,
 747                                            list);
 748                 retiring_seqno = request->seqno;
 749
 750                 if (i915_seqno_passed(seqno, retiring_seqno) ||
 751                     dev_priv->mm.wedged) {
 752                         i915_gem_retire_request(dev, request);
 753
 754                         list_del(&request->list);
 755                         drm_free(request, sizeof(*request), DRM_MEM_DRIVER);
 756                 } else
 757                         break;
 758         }
 759 }
 760
 761 void
 762 i915_gem_retire_work_handler(struct work_struct *work)
 763 {
 764         drm_i915_private_t *dev_priv;
 765         struct drm_device *dev;
 766
 767         dev_priv = container_of(work, drm_i915_private_t,
 768                                 mm.retire_work.work);
 769         dev = dev_priv->dev;
 770
 771         mutex_lock(&dev->struct_mutex);
 772         i915_gem_retire_requests(dev);
 773         if (!dev_priv->mm.suspended &&
 774             !list_empty(&dev_priv->mm.request_list))
 775                 schedule_delayed_work(&dev_priv->mm.retire_work, HZ);
 776         mutex_unlock(&dev->struct_mutex);
 777 }
 778
 779 /**
 780  * Waits for a sequence number to be signaled, and cleans up the
 781  * request and object lists appropriately for that event.
 782  */
 783 static int
 784 i915_wait_request(struct drm_device *dev, uint32_t seqno)
 785 {
 786         drm_i915_private_t *dev_priv = dev->dev_private;
 787         int ret = 0;
 788
 789         BUG_ON(seqno == 0);
 790
 791         if (!i915_seqno_passed(i915_get_gem_seqno(dev), seqno)) {
 792                 dev_priv->mm.waiting_gem_seqno = seqno;
 793                 i915_user_irq_get(dev);
 794                 ret = wait_event_interruptible(dev_priv->irq_queue,
 795                                                i915_seqno_passed(i915_get_gem_seqno(dev),
 796                                                                  seqno) ||
 797                                                dev_priv->mm.wedged);
 798                 i915_user_irq_put(dev);
 799                 dev_priv->mm.waiting_gem_seqno = 0;
 800         }
 801         if (dev_priv->mm.wedged)
 802                 ret = -EIO;
 803
 804         if (ret && ret != -ERESTARTSYS)
 805                 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
 806                           __func__, ret, seqno, i915_get_gem_seqno(dev));
 807
 808         /* Directly dispatch request retiring.  While we have the work queue
 809          * to handle this, the waiter on a request often wants an associated
 810          * buffer to have made it to the inactive list, and we would need
 811          * a separate wait queue to handle that.
 812          */
 813         if (ret == 0)
 814                 i915_gem_retire_requests(dev);
 815
 816         return ret;
 817 }
 818
 819 static void
 820 i915_gem_flush(struct drm_device *dev,
 821                uint32_t invalidate_domains,
 822                uint32_t flush_domains)
 823 {
 824         drm_i915_private_t *dev_priv = dev->dev_private;
 825         uint32_t cmd;
 826         RING_LOCALS;
 827
 828 #if WATCH_EXEC
 829         DRM_INFO("%s: invalidate %08x flush %08x\n", __func__,
 830                   invalidate_domains, flush_domains);
 831 #endif
 832
 833         if (flush_domains & I915_GEM_DOMAIN_CPU)
 834                 drm_agp_chipset_flush(dev);
 835
 836         if ((invalidate_domains | flush_domains) & ~(I915_GEM_DOMAIN_CPU |
 837                                                      I915_GEM_DOMAIN_GTT)) {
 838                 /*
 839                  * read/write caches:
 840                  *
 841                  * I915_GEM_DOMAIN_RENDER is always invalidated, but is
 842                  * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
 843                  * also flushed at 2d versus 3d pipeline switches.
 844                  *
 845                  * read-only caches:
 846                  *
 847                  * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
 848                  * MI_READ_FLUSH is set, and is always flushed on 965.
 849                  *
 850                  * I915_GEM_DOMAIN_COMMAND may not exist?
 851                  *
 852                  * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
 853                  * invalidated when MI_EXE_FLUSH is set.
 854                  *
 855                  * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
 856                  * invalidated with every MI_FLUSH.
 857                  *
 858                  * TLBs:
 859                  *
 860                  * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
 861                  * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
 862                  * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
 863                  * are flushed at any MI_FLUSH.
 864                  */
 865
 866                 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
 867                 if ((invalidate_domains|flush_domains) &
 868                     I915_GEM_DOMAIN_RENDER)
 869                         cmd &= ~MI_NO_WRITE_FLUSH;
 870                 if (!IS_I965G(dev)) {
 871                         /*
 872                          * On the 965, the sampler cache always gets flushed
 873                          * and this bit is reserved.
 874                          */
 875                         if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
 876                                 cmd |= MI_READ_FLUSH;
 877                 }
 878                 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
 879                         cmd |= MI_EXE_FLUSH;
 880
 881 #if WATCH_EXEC
 882                 DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd);
 883 #endif
 884                 BEGIN_LP_RING(2);
 885                 OUT_RING(cmd);
 886                 OUT_RING(0); /* noop */
 887                 ADVANCE_LP_RING();
 888         }
 889 }
 890
 891 /**
 892  * Ensures that all rendering to the object has completed and the object is
 893  * safe to unbind from the GTT or access from the CPU.
 894  */
 895 static int
 896 i915_gem_object_wait_rendering(struct drm_gem_object *obj)
 897 {
 898         struct drm_device *dev = obj->dev;
 899         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 900         int ret;
 901
 902         /* If there are writes queued to the buffer, flush and
 903          * create a new seqno to wait for.
 904          */
 905         if (obj->write_domain & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT)) {
 906                 uint32_t write_domain = obj->write_domain;
 907 #if WATCH_BUF
 908                 DRM_INFO("%s: flushing object %p from write domain %08x\n",
 909                           __func__, obj, write_domain);
 910 #endif
 911                 i915_gem_flush(dev, 0, write_domain);
 912
 913                 i915_gem_object_move_to_active(obj);
 914                 obj_priv->last_rendering_seqno = i915_add_request(dev,
 915                                                                   write_domain);
 916                 BUG_ON(obj_priv->last_rendering_seqno == 0);
 917 #if WATCH_LRU
 918                 DRM_INFO("%s: flush moves to exec list %p\n", __func__, obj);
 919 #endif
 920         }
 921
 922         /* If there is rendering queued on the buffer being evicted, wait for
 923          * it.
 924          */
 925         if (obj_priv->active) {
 926 #if WATCH_BUF
 927                 DRM_INFO("%s: object %p wait for seqno %08x\n",
 928                           __func__, obj, obj_priv->last_rendering_seqno);
 929 #endif
 930                 ret = i915_wait_request(dev, obj_priv->last_rendering_seqno);
 931                 if (ret != 0)
 932                         return ret;
 933         }
 934
 935         return 0;
 936 }
 937
 938 /**
 939  * Unbinds an object from the GTT aperture.
 940  */
 941 static int
 942 i915_gem_object_unbind(struct drm_gem_object *obj)
 943 {
 944         struct drm_device *dev = obj->dev;
 945         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 946         int ret = 0;
 947
 948 #if WATCH_BUF
 949         DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj);
 950         DRM_INFO("gtt_space %p\n", obj_priv->gtt_space);
 951 #endif
 952         if (obj_priv->gtt_space == NULL)
 953                 return 0;
 954
 955         if (obj_priv->pin_count != 0) {
 956                 DRM_ERROR("Attempting to unbind pinned buffer\n");
 957                 return -EINVAL;
 958         }
 959
 960         /* Wait for any rendering to complete
 961          */
 962         ret = i915_gem_object_wait_rendering(obj);
 963         if (ret) {
 964                 DRM_ERROR("wait_rendering failed: %d\n", ret);
 965                 return ret;
 966         }
 967
 968         /* Move the object to the CPU domain to ensure that
 969          * any possible CPU writes while it's not in the GTT
 970          * are flushed when we go to remap it. This will
 971          * also ensure that all pending GPU writes are finished
 972          * before we unbind.
 973          */
 974         ret = i915_gem_object_set_domain(obj, I915_GEM_DOMAIN_CPU,
 975                                          I915_GEM_DOMAIN_CPU);
 976         if (ret) {
 977                 DRM_ERROR("set_domain failed: %d\n", ret);
 978                 return ret;
 979         }
 980
 981         if (obj_priv->agp_mem != NULL) {
 982                 drm_unbind_agp(obj_priv->agp_mem);
 983                 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
 984                 obj_priv->agp_mem = NULL;
 985         }
 986
 987         BUG_ON(obj_priv->active);
 988
 989         i915_gem_object_free_page_list(obj);
 990
 991         if (obj_priv->gtt_space) {
 992                 atomic_dec(&dev->gtt_count);
 993                 atomic_sub(obj->size, &dev->gtt_memory);
 994
 995                 drm_mm_put_block(obj_priv->gtt_space);
 996                 obj_priv->gtt_space = NULL;
 997         }
 998
 999         /* Remove ourselves from the LRU list if present. */
1000         if (!list_empty(&obj_priv->list))
1001                 list_del_init(&obj_priv->list);
1002
1003         return 0;
1004 }
1005
1006 static int
1007 i915_gem_evict_something(struct drm_device *dev)
1008 {
1009         drm_i915_private_t *dev_priv = dev->dev_private;
1010         struct drm_gem_object *obj;
1011         struct drm_i915_gem_object *obj_priv;
1012         int ret = 0;
1013
1014         for (;;) {
1015                 /* If there's an inactive buffer available now, grab it
1016                  * and be done.
1017                  */
1018                 if (!list_empty(&dev_priv->mm.inactive_list)) {
1019                         obj_priv = list_first_entry(&dev_priv->mm.inactive_list,
1020                                                     struct drm_i915_gem_object,
1021                                                     list);
1022                         obj = obj_priv->obj;
1023                         BUG_ON(obj_priv->pin_count != 0);
1024 #if WATCH_LRU
1025                         DRM_INFO("%s: evicting %p\n", __func__, obj);
1026 #endif
1027                         BUG_ON(obj_priv->active);
1028
1029                         /* Wait on the rendering and unbind the buffer. */
1030                         ret = i915_gem_object_unbind(obj);
1031                         break;
1032                 }
1033
1034                 /* If we didn't get anything, but the ring is still processing
1035                  * things, wait for one of those things to finish and hopefully
1036                  * leave us a buffer to evict.
1037                  */
1038                 if (!list_empty(&dev_priv->mm.request_list)) {
1039                         struct drm_i915_gem_request *request;
1040
1041                         request = list_first_entry(&dev_priv->mm.request_list,
1042                                                    struct drm_i915_gem_request,
1043                                                    list);
1044
1045                         ret = i915_wait_request(dev, request->seqno);
1046                         if (ret)
1047                                 break;
1048
1049                         /* if waiting caused an object to become inactive,
1050                          * then loop around and wait for it. Otherwise, we
1051                          * assume that waiting freed and unbound something,
1052                          * so there should now be some space in the GTT
1053                          */
1054                         if (!list_empty(&dev_priv->mm.inactive_list))
1055                                 continue;
1056                         break;
1057                 }
1058
1059                 /* If we didn't have anything on the request list but there
1060                  * are buffers awaiting a flush, emit one and try again.
1061                  * When we wait on it, those buffers waiting for that flush
1062                  * will get moved to inactive.
1063                  */
1064                 if (!list_empty(&dev_priv->mm.flushing_list)) {
1065                         obj_priv = list_first_entry(&dev_priv->mm.flushing_list,
1066                                                     struct drm_i915_gem_object,
1067                                                     list);
1068                         obj = obj_priv->obj;
1069
1070                         i915_gem_flush(dev,
1071                                        obj->write_domain,
1072                                        obj->write_domain);
1073                         i915_add_request(dev, obj->write_domain);
1074
1075                         obj = NULL;
1076                         continue;
1077                 }
1078
1079                 DRM_ERROR("inactive empty %d request empty %d "
1080                           "flushing empty %d\n",
1081                           list_empty(&dev_priv->mm.inactive_list),
1082                           list_empty(&dev_priv->mm.request_list),
1083                           list_empty(&dev_priv->mm.flushing_list));
1084                 /* If we didn't do any of the above, there's nothing to be done
1085                  * and we just can't fit it in.
1086                  */
1087                 return -ENOMEM;
1088         }
1089         return ret;
1090 }
1091
1092 static int
1093 i915_gem_object_get_page_list(struct drm_gem_object *obj)
1094 {
1095         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1096         int page_count, i;
1097         struct address_space *mapping;
1098         struct inode *inode;
1099         struct page *page;
1100         int ret;
1101
1102         if (obj_priv->page_list)
1103                 return 0;
1104
1105         /* Get the list of pages out of our struct file.  They'll be pinned
1106          * at this point until we release them.
1107          */
1108         page_count = obj->size / PAGE_SIZE;
1109         BUG_ON(obj_priv->page_list != NULL);
1110         obj_priv->page_list = drm_calloc(page_count, sizeof(struct page *),
1111                                          DRM_MEM_DRIVER);
1112         if (obj_priv->page_list == NULL) {
1113                 DRM_ERROR("Faled to allocate page list\n");
1114                 return -ENOMEM;
1115         }
1116
1117         inode = obj->filp->f_path.dentry->d_inode;
1118         mapping = inode->i_mapping;
1119         for (i = 0; i < page_count; i++) {
1120                 page = read_mapping_page(mapping, i, NULL);
1121                 if (IS_ERR(page)) {
1122                         ret = PTR_ERR(page);
1123                         DRM_ERROR("read_mapping_page failed: %d\n", ret);
1124                         i915_gem_object_free_page_list(obj);
1125                         return ret;
1126                 }
1127                 obj_priv->page_list[i] = page;
1128         }
1129         return 0;
1130 }
1131
1132 /**
1133  * Finds free space in the GTT aperture and binds the object there.
1134  */
1135 static int
1136 i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
1137 {
1138         struct drm_device *dev = obj->dev;
1139         drm_i915_private_t *dev_priv = dev->dev_private;
1140         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1141         struct drm_mm_node *free_space;
1142         int page_count, ret;
1143
1144         if (alignment == 0)
1145                 alignment = PAGE_SIZE;
1146         if (alignment & (PAGE_SIZE - 1)) {
1147                 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
1148                 return -EINVAL;
1149         }
1150
1151  search_free:
1152         free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
1153                                         obj->size, alignment, 0);
1154         if (free_space != NULL) {
1155                 obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
1156                                                        alignment);
1157                 if (obj_priv->gtt_space != NULL) {
1158                         obj_priv->gtt_space->private = obj;
1159                         obj_priv->gtt_offset = obj_priv->gtt_space->start;
1160                 }
1161         }
1162         if (obj_priv->gtt_space == NULL) {
1163                 /* If the gtt is empty and we're still having trouble
1164                  * fitting our object in, we're out of memory.
1165                  */
1166 #if WATCH_LRU
1167                 DRM_INFO("%s: GTT full, evicting something\n", __func__);
1168 #endif
1169                 if (list_empty(&dev_priv->mm.inactive_list) &&
1170                     list_empty(&dev_priv->mm.flushing_list) &&
1171                     list_empty(&dev_priv->mm.active_list)) {
1172                         DRM_ERROR("GTT full, but LRU list empty\n");
1173                         return -ENOMEM;
1174                 }
1175
1176                 ret = i915_gem_evict_something(dev);
1177                 if (ret != 0) {
1178                         DRM_ERROR("Failed to evict a buffer %d\n", ret);
1179                         return ret;
1180                 }
1181                 goto search_free;
1182         }
1183
1184 #if WATCH_BUF
1185         DRM_INFO("Binding object of size %d at 0x%08x\n",
1186                  obj->size, obj_priv->gtt_offset);
1187 #endif
1188         ret = i915_gem_object_get_page_list(obj);
1189         if (ret) {
1190                 drm_mm_put_block(obj_priv->gtt_space);
1191                 obj_priv->gtt_space = NULL;
1192                 return ret;
1193         }
1194
1195         page_count = obj->size / PAGE_SIZE;
1196         /* Create an AGP memory structure pointing at our pages, and bind it
1197          * into the GTT.
1198          */
1199         obj_priv->agp_mem = drm_agp_bind_pages(dev,
1200                                                obj_priv->page_list,
1201                                                page_count,
1202                                                obj_priv->gtt_offset,
1203                                                obj_priv->agp_type);
1204         if (obj_priv->agp_mem == NULL) {
1205                 i915_gem_object_free_page_list(obj);
1206                 drm_mm_put_block(obj_priv->gtt_space);
1207                 obj_priv->gtt_space = NULL;
1208                 return -ENOMEM;
1209         }
1210         atomic_inc(&dev->gtt_count);
1211         atomic_add(obj->size, &dev->gtt_memory);
1212
1213         /* Assert that the object is not currently in any GPU domain. As it
1214          * wasn't in the GTT, there shouldn't be any way it could have been in
1215          * a GPU cache
1216          */
1217         BUG_ON(obj->read_domains & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT));
1218         BUG_ON(obj->write_domain & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT));
1219
1220         return 0;
1221 }
1222
1223 void
1224 i915_gem_clflush_object(struct drm_gem_object *obj)
1225 {
1226         struct drm_i915_gem_object      *obj_priv = obj->driver_private;
1227
1228         /* If we don't have a page list set up, then we're not pinned
1229          * to GPU, and we can ignore the cache flush because it'll happen
1230          * again at bind time.
1231          */
1232         if (obj_priv->page_list == NULL)
1233                 return;
1234
1235         drm_clflush_pages(obj_priv->page_list, obj->size / PAGE_SIZE);
1236 }
1237
1238 /*
1239  * Set the next domain for the specified object. This
1240  * may not actually perform the necessary flushing/invaliding though,
1241  * as that may want to be batched with other set_domain operations
1242  *
1243  * This is (we hope) the only really tricky part of gem. The goal
1244  * is fairly simple -- track which caches hold bits of the object
1245  * and make sure they remain coherent. A few concrete examples may
1246  * help to explain how it works. For shorthand, we use the notation
1247  * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
1248  * a pair of read and write domain masks.
1249  *
1250  * Case 1: the batch buffer
1251  *
1252  *      1. Allocated
1253  *      2. Written by CPU
1254  *      3. Mapped to GTT
1255  *      4. Read by GPU
1256  *      5. Unmapped from GTT
1257  *      6. Freed
1258  *
1259  *      Let's take these a step at a time
1260  *
1261  *      1. Allocated
1262  *              Pages allocated from the kernel may still have
1263  *              cache contents, so we set them to (CPU, CPU) always.
1264  *      2. Written by CPU (using pwrite)
1265  *              The pwrite function calls set_domain (CPU, CPU) and
1266  *              this function does nothing (as nothing changes)
1267  *      3. Mapped by GTT
1268  *              This function asserts that the object is not
1269  *              currently in any GPU-based read or write domains
1270  *      4. Read by GPU
1271  *              i915_gem_execbuffer calls set_domain (COMMAND, 0).
1272  *              As write_domain is zero, this function adds in the
1273  *              current read domains (CPU+COMMAND, 0).
1274  *              flush_domains is set to CPU.
1275  *              invalidate_domains is set to COMMAND
1276  *              clflush is run to get data out of the CPU caches
1277  *              then i915_dev_set_domain calls i915_gem_flush to
1278  *              emit an MI_FLUSH and drm_agp_chipset_flush
1279  *      5. Unmapped from GTT
1280  *              i915_gem_object_unbind calls set_domain (CPU, CPU)
1281  *              flush_domains and invalidate_domains end up both zero
1282  *              so no flushing/invalidating happens
1283  *      6. Freed
1284  *              yay, done
1285  *
1286  * Case 2: The shared render buffer
1287  *
1288  *      1. Allocated
1289  *      2. Mapped to GTT
1290  *      3. Read/written by GPU
1291  *      4. set_domain to (CPU,CPU)
1292  *      5. Read/written by CPU
1293  *      6. Read/written by GPU
1294  *
1295  *      1. Allocated
1296  *              Same as last example, (CPU, CPU)
1297  *      2. Mapped to GTT
1298  *              Nothing changes (assertions find that it is not in the GPU)
1299  *      3. Read/written by GPU
1300  *              execbuffer calls set_domain (RENDER, RENDER)
1301  *              flush_domains gets CPU
1302  *              invalidate_domains gets GPU
1303  *              clflush (obj)
1304  *              MI_FLUSH and drm_agp_chipset_flush
1305  *      4. set_domain (CPU, CPU)
1306  *              flush_domains gets GPU
1307  *              invalidate_domains gets CPU
1308  *              wait_rendering (obj) to make sure all drawing is complete.
1309  *              This will include an MI_FLUSH to get the data from GPU
1310  *              to memory
1311  *              clflush (obj) to invalidate the CPU cache
1312  *              Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
1313  *      5. Read/written by CPU
1314  *              cache lines are loaded and dirtied
1315  *      6. Read written by GPU
1316  *              Same as last GPU access
1317  *
1318  * Case 3: The constant buffer
1319  *
1320  *      1. Allocated
1321  *      2. Written by CPU
1322  *      3. Read by GPU
1323  *      4. Updated (written) by CPU again
1324  *      5. Read by GPU
1325  *
1326  *      1. Allocated
1327  *              (CPU, CPU)
1328  *      2. Written by CPU
1329  *              (CPU, CPU)
1330  *      3. Read by GPU
1331  *              (CPU+RENDER, 0)
1332  *              flush_domains = CPU
1333  *              invalidate_domains = RENDER
1334  *              clflush (obj)
1335  *              MI_FLUSH
1336  *              drm_agp_chipset_flush
1337  *      4. Updated (written) by CPU again
1338  *              (CPU, CPU)
1339  *              flush_domains = 0 (no previous write domain)
1340  *              invalidate_domains = 0 (no new read domains)
1341  *      5. Read by GPU
1342  *              (CPU+RENDER, 0)
1343  *              flush_domains = CPU
1344  *              invalidate_domains = RENDER
1345  *              clflush (obj)
1346  *              MI_FLUSH
1347  *              drm_agp_chipset_flush
1348  */
1349 static int
1350 i915_gem_object_set_domain(struct drm_gem_object *obj,
1351                             uint32_t read_domains,
1352                             uint32_t write_domain)
1353 {
1354         struct drm_device               *dev = obj->dev;
1355         struct drm_i915_gem_object      *obj_priv = obj->driver_private;
1356         uint32_t                        invalidate_domains = 0;
1357         uint32_t                        flush_domains = 0;
1358         int                             ret;
1359
1360 #if WATCH_BUF
1361         DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
1362                  __func__, obj,
1363                  obj->read_domains, read_domains,
1364                  obj->write_domain, write_domain);
1365 #endif
1366         /*
1367          * If the object isn't moving to a new write domain,
1368          * let the object stay in multiple read domains
1369          */
1370         if (write_domain == 0)
1371                 read_domains |= obj->read_domains;
1372         else
1373                 obj_priv->dirty = 1;
1374
1375         /*
1376          * Flush the current write domain if
1377          * the new read domains don't match. Invalidate
1378          * any read domains which differ from the old
1379          * write domain
1380          */
1381         if (obj->write_domain && obj->write_domain != read_domains) {
1382                 flush_domains |= obj->write_domain;
1383                 invalidate_domains |= read_domains & ~obj->write_domain;
1384         }
1385         /*
1386          * Invalidate any read caches which may have
1387          * stale data. That is, any new read domains.
1388          */
1389         invalidate_domains |= read_domains & ~obj->read_domains;
1390         if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) {
1391 #if WATCH_BUF
1392                 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
1393                          __func__, flush_domains, invalidate_domains);
1394 #endif
1395                 /*
1396                  * If we're invaliding the CPU cache and flushing a GPU cache,
1397                  * then pause for rendering so that the GPU caches will be
1398                  * flushed before the cpu cache is invalidated
1399                  */
1400                 if ((invalidate_domains & I915_GEM_DOMAIN_CPU) &&
1401                     (flush_domains & ~(I915_GEM_DOMAIN_CPU |
1402                                        I915_GEM_DOMAIN_GTT))) {
1403                         ret = i915_gem_object_wait_rendering(obj);
1404                         if (ret)
1405                                 return ret;
1406                 }
1407                 i915_gem_clflush_object(obj);
1408         }
1409
1410         if ((write_domain | flush_domains) != 0)
1411                 obj->write_domain = write_domain;
1412
1413         /* If we're invalidating the CPU domain, clear the per-page CPU
1414          * domain list as well.
1415          */
1416         if (obj_priv->page_cpu_valid != NULL &&
1417             (write_domain != 0 ||
1418              read_domains & I915_GEM_DOMAIN_CPU)) {
1419                 drm_free(obj_priv->page_cpu_valid, obj->size / PAGE_SIZE,
1420                          DRM_MEM_DRIVER);
1421                 obj_priv->page_cpu_valid = NULL;
1422         }
1423         obj->read_domains = read_domains;
1424
1425         dev->invalidate_domains |= invalidate_domains;
1426         dev->flush_domains |= flush_domains;
1427 #if WATCH_BUF
1428         DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
1429                  __func__,
1430                  obj->read_domains, obj->write_domain,
1431                  dev->invalidate_domains, dev->flush_domains);
1432 #endif
1433         return 0;
1434 }
1435
1436 /**
1437  * Set the read/write domain on a range of the object.
1438  *
1439  * Currently only implemented for CPU reads, otherwise drops to normal
1440  * i915_gem_object_set_domain().
1441  */
1442 static int
1443 i915_gem_object_set_domain_range(struct drm_gem_object *obj,
1444                                  uint64_t offset,
1445                                  uint64_t size,
1446                                  uint32_t read_domains,
1447                                  uint32_t write_domain)
1448 {
1449         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1450         int ret, i;
1451
1452         if (obj->read_domains & I915_GEM_DOMAIN_CPU)
1453                 return 0;
1454
1455         if (read_domains != I915_GEM_DOMAIN_CPU ||
1456             write_domain != 0)
1457                 return i915_gem_object_set_domain(obj,
1458                                                   read_domains, write_domain);
1459
1460         /* Wait on any GPU rendering to the object to be flushed. */
1461         if (obj->write_domain & ~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT)) {
1462                 ret = i915_gem_object_wait_rendering(obj);
1463                 if (ret)
1464                         return ret;
1465         }
1466
1467         if (obj_priv->page_cpu_valid == NULL) {
1468                 obj_priv->page_cpu_valid = drm_calloc(1, obj->size / PAGE_SIZE,
1469                                                       DRM_MEM_DRIVER);
1470         }
1471
1472         /* Flush the cache on any pages that are still invalid from the CPU's
1473          * perspective.
1474          */
1475         for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE; i++) {
1476                 if (obj_priv->page_cpu_valid[i])
1477                         continue;
1478
1479                 drm_clflush_pages(obj_priv->page_list + i, 1);
1480
1481                 obj_priv->page_cpu_valid[i] = 1;
1482         }
1483
1484         return 0;
1485 }
1486
1487 /**
1488  * Once all of the objects have been set in the proper domain,
1489  * perform the necessary flush and invalidate operations.
1490  *
1491  * Returns the write domains flushed, for use in flush tracking.
1492  */
1493 static uint32_t
1494 i915_gem_dev_set_domain(struct drm_device *dev)
1495 {
1496         uint32_t flush_domains = dev->flush_domains;
1497
1498         /*
1499          * Now that all the buffers are synced to the proper domains,
1500          * flush and invalidate the collected domains
1501          */
1502         if (dev->invalidate_domains | dev->flush_domains) {
1503 #if WATCH_EXEC
1504                 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
1505                           __func__,
1506                          dev->invalidate_domains,
1507                          dev->flush_domains);
1508 #endif
1509                 i915_gem_flush(dev,
1510                                dev->invalidate_domains,
1511                                dev->flush_domains);
1512                 dev->invalidate_domains = 0;
1513                 dev->flush_domains = 0;
1514         }
1515
1516         return flush_domains;
1517 }
1518
1519 /**
1520  * Pin an object to the GTT and evaluate the relocations landing in it.
1521  */
1522 static int
1523 i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
1524                                  struct drm_file *file_priv,
1525                                  struct drm_i915_gem_exec_object *entry)
1526 {
1527         struct drm_device *dev = obj->dev;
1528         struct drm_i915_gem_relocation_entry reloc;
1529         struct drm_i915_gem_relocation_entry __user *relocs;
1530         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1531         int i, ret;
1532         uint32_t last_reloc_offset = -1;
1533         void __iomem *reloc_page = NULL;
1534
1535         /* Choose the GTT offset for our buffer and put it there. */
1536         ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
1537         if (ret)
1538                 return ret;
1539
1540         entry->offset = obj_priv->gtt_offset;
1541
1542         relocs = (struct drm_i915_gem_relocation_entry __user *)
1543                  (uintptr_t) entry->relocs_ptr;
1544         /* Apply the relocations, using the GTT aperture to avoid cache
1545          * flushing requirements.
1546          */
1547         for (i = 0; i < entry->relocation_count; i++) {
1548                 struct drm_gem_object *target_obj;
1549                 struct drm_i915_gem_object *target_obj_priv;
1550                 uint32_t reloc_val, reloc_offset;
1551                 uint32_t __iomem *reloc_entry;
1552
1553                 ret = copy_from_user(&reloc, relocs + i, sizeof(reloc));
1554                 if (ret != 0) {
1555                         i915_gem_object_unpin(obj);
1556                         return ret;
1557                 }
1558
1559                 target_obj = drm_gem_object_lookup(obj->dev, file_priv,
1560                                                    reloc.target_handle);
1561                 if (target_obj == NULL) {
1562                         i915_gem_object_unpin(obj);
1563                         return -EBADF;
1564                 }
1565                 target_obj_priv = target_obj->driver_private;
1566
1567                 /* The target buffer should have appeared before us in the
1568                  * exec_object list, so it should have a GTT space bound by now.
1569                  */
1570                 if (target_obj_priv->gtt_space == NULL) {
1571                         DRM_ERROR("No GTT space found for object %d\n",
1572                                   reloc.target_handle);
1573                         drm_gem_object_unreference(target_obj);
1574                         i915_gem_object_unpin(obj);
1575                         return -EINVAL;
1576                 }
1577
1578                 if (reloc.offset > obj->size - 4) {
1579                         DRM_ERROR("Relocation beyond object bounds: "
1580                                   "obj %p target %d offset %d size %d.\n",
1581                                   obj, reloc.target_handle,
1582                                   (int) reloc.offset, (int) obj->size);
1583                         drm_gem_object_unreference(target_obj);
1584                         i915_gem_object_unpin(obj);
1585                         return -EINVAL;
1586                 }
1587                 if (reloc.offset & 3) {
1588                         DRM_ERROR("Relocation not 4-byte aligned: "
1589                                   "obj %p target %d offset %d.\n",
1590                                   obj, reloc.target_handle,
1591                                   (int) reloc.offset);
1592                         drm_gem_object_unreference(target_obj);
1593                         i915_gem_object_unpin(obj);
1594                         return -EINVAL;
1595                 }
1596
1597                 if (reloc.write_domain && target_obj->pending_write_domain &&
1598                     reloc.write_domain != target_obj->pending_write_domain) {
1599                         DRM_ERROR("Write domain conflict: "
1600                                   "obj %p target %d offset %d "
1601                                   "new %08x old %08x\n",
1602                                   obj, reloc.target_handle,
1603                                   (int) reloc.offset,
1604                                   reloc.write_domain,
1605                                   target_obj->pending_write_domain);
1606                         drm_gem_object_unreference(target_obj);
1607                         i915_gem_object_unpin(obj);
1608                         return -EINVAL;
1609                 }
1610
1611 #if WATCH_RELOC
1612                 DRM_INFO("%s: obj %p offset %08x target %d "
1613                          "read %08x write %08x gtt %08x "
1614                          "presumed %08x delta %08x\n",
1615                          __func__,
1616                          obj,
1617                          (int) reloc.offset,
1618                          (int) reloc.target_handle,
1619                          (int) reloc.read_domains,
1620                          (int) reloc.write_domain,
1621                          (int) target_obj_priv->gtt_offset,
1622                          (int) reloc.presumed_offset,
1623                          reloc.delta);
1624 #endif
1625
1626                 target_obj->pending_read_domains |= reloc.read_domains;
1627                 target_obj->pending_write_domain |= reloc.write_domain;
1628
1629                 /* If the relocation already has the right value in it, no
1630                  * more work needs to be done.
1631                  */
1632                 if (target_obj_priv->gtt_offset == reloc.presumed_offset) {
1633                         drm_gem_object_unreference(target_obj);
1634                         continue;
1635                 }
1636
1637                 /* Now that we're going to actually write some data in,
1638                  * make sure that any rendering using this buffer's contents
1639                  * is completed.
1640                  */
1641                 i915_gem_object_wait_rendering(obj);
1642
1643                 /* As we're writing through the gtt, flush
1644                  * any CPU writes before we write the relocations
1645                  */
1646                 if (obj->write_domain & I915_GEM_DOMAIN_CPU) {
1647                         i915_gem_clflush_object(obj);
1648                         drm_agp_chipset_flush(dev);
1649                         obj->write_domain = 0;
1650                 }
1651
1652                 /* Map the page containing the relocation we're going to
1653                  * perform.
1654                  */
1655                 reloc_offset = obj_priv->gtt_offset + reloc.offset;
1656                 if (reloc_page == NULL ||
1657                     (last_reloc_offset & ~(PAGE_SIZE - 1)) !=
1658                     (reloc_offset & ~(PAGE_SIZE - 1))) {
1659                         if (reloc_page != NULL)
1660                                 iounmap(reloc_page);
1661
1662                         reloc_page = ioremap_wc(dev->agp->base +
1663                                                 (reloc_offset &
1664                                                  ~(PAGE_SIZE - 1)),
1665                                                 PAGE_SIZE);
1666                         last_reloc_offset = reloc_offset;
1667                         if (reloc_page == NULL) {
1668                                 drm_gem_object_unreference(target_obj);
1669                                 i915_gem_object_unpin(obj);
1670                                 return -ENOMEM;
1671                         }
1672                 }
1673
1674                 reloc_entry = (uint32_t __iomem *)(reloc_page +
1675                                            (reloc_offset & (PAGE_SIZE - 1)));
1676                 reloc_val = target_obj_priv->gtt_offset + reloc.delta;
1677
1678 #if WATCH_BUF
1679                 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
1680                           obj, (unsigned int) reloc.offset,
1681                           readl(reloc_entry), reloc_val);
1682 #endif
1683                 writel(reloc_val, reloc_entry);
1684
1685                 /* Write the updated presumed offset for this entry back out
1686                  * to the user.
1687                  */
1688                 reloc.presumed_offset = target_obj_priv->gtt_offset;
1689                 ret = copy_to_user(relocs + i, &reloc, sizeof(reloc));
1690                 if (ret != 0) {
1691                         drm_gem_object_unreference(target_obj);
1692                         i915_gem_object_unpin(obj);
1693                         return ret;
1694                 }
1695
1696                 drm_gem_object_unreference(target_obj);
1697         }
1698
1699         if (reloc_page != NULL)
1700                 iounmap(reloc_page);
1701
1702 #if WATCH_BUF
1703         if (0)
1704                 i915_gem_dump_object(obj, 128, __func__, ~0);
1705 #endif
1706         return 0;
1707 }
1708
1709 /** Dispatch a batchbuffer to the ring
1710  */
1711 static int
1712 i915_dispatch_gem_execbuffer(struct drm_device *dev,
1713                               struct drm_i915_gem_execbuffer *exec,
1714                               uint64_t exec_offset)
1715 {
1716         drm_i915_private_t *dev_priv = dev->dev_private;
1717         struct drm_clip_rect __user *boxes = (struct drm_clip_rect __user *)
1718                                              (uintptr_t) exec->cliprects_ptr;
1719         int nbox = exec->num_cliprects;
1720         int i = 0, count;
1721         uint32_t        exec_start, exec_len;
1722         RING_LOCALS;
1723
1724         exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
1725         exec_len = (uint32_t) exec->batch_len;
1726
1727         if ((exec_start | exec_len) & 0x7) {
1728                 DRM_ERROR("alignment\n");
1729                 return -EINVAL;
1730         }
1731
1732         if (!exec_start)
1733                 return -EINVAL;
1734
1735         count = nbox ? nbox : 1;
1736
1737         for (i = 0; i < count; i++) {
1738                 if (i < nbox) {
1739                         int ret = i915_emit_box(dev, boxes, i,
1740                                                 exec->DR1, exec->DR4);
1741                         if (ret)
1742                                 return ret;
1743                 }
1744
1745                 if (IS_I830(dev) || IS_845G(dev)) {
1746                         BEGIN_LP_RING(4);
1747                         OUT_RING(MI_BATCH_BUFFER);
1748                         OUT_RING(exec_start | MI_BATCH_NON_SECURE);
1749                         OUT_RING(exec_start + exec_len - 4);
1750                         OUT_RING(0);
1751                         ADVANCE_LP_RING();
1752                 } else {
1753                         BEGIN_LP_RING(2);
1754                         if (IS_I965G(dev)) {
1755                                 OUT_RING(MI_BATCH_BUFFER_START |
1756                                          (2 << 6) |
1757                                          MI_BATCH_NON_SECURE_I965);
1758                                 OUT_RING(exec_start);
1759                         } else {
1760                                 OUT_RING(MI_BATCH_BUFFER_START |
1761                                          (2 << 6));
1762                                 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
1763                         }
1764                         ADVANCE_LP_RING();
1765                 }
1766         }
1767
1768         /* XXX breadcrumb */
1769         return 0;
1770 }
1771
1772 /* Throttle our rendering by waiting until the ring has completed our requests
1773  * emitted over 20 msec ago.
1774  *
1775  * This should get us reasonable parallelism between CPU and GPU but also
1776  * relatively low latency when blocking on a particular request to finish.
1777  */
1778 static int
1779 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
1780 {
1781         struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
1782         int ret = 0;
1783         uint32_t seqno;
1784
1785         mutex_lock(&dev->struct_mutex);
1786         seqno = i915_file_priv->mm.last_gem_throttle_seqno;
1787         i915_file_priv->mm.last_gem_throttle_seqno =
1788                 i915_file_priv->mm.last_gem_seqno;
1789         if (seqno)
1790                 ret = i915_wait_request(dev, seqno);
1791         mutex_unlock(&dev->struct_mutex);
1792         return ret;
1793 }
1794
1795 int
1796 i915_gem_execbuffer(struct drm_device *dev, void *data,
1797                     struct drm_file *file_priv)
1798 {
1799         drm_i915_private_t *dev_priv = dev->dev_private;
1800         struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
1801         struct drm_i915_gem_execbuffer *args = data;
1802         struct drm_i915_gem_exec_object *exec_list = NULL;
1803         struct drm_gem_object **object_list = NULL;
1804         struct drm_gem_object *batch_obj;
1805         int ret, i, pinned = 0;
1806         uint64_t exec_offset;
1807         uint32_t seqno, flush_domains;
1808
1809 #if WATCH_EXEC
1810         DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
1811                   (int) args->buffers_ptr, args->buffer_count, args->batch_len);
1812 #endif
1813
1814         if (args->buffer_count < 1) {
1815                 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
1816                 return -EINVAL;
1817         }
1818         /* Copy in the exec list from userland */
1819         exec_list = drm_calloc(sizeof(*exec_list), args->buffer_count,
1820                                DRM_MEM_DRIVER);
1821         object_list = drm_calloc(sizeof(*object_list), args->buffer_count,
1822                                  DRM_MEM_DRIVER);
1823         if (exec_list == NULL || object_list == NULL) {
1824                 DRM_ERROR("Failed to allocate exec or object list "
1825                           "for %d buffers\n",
1826                           args->buffer_count);
1827                 ret = -ENOMEM;
1828                 goto pre_mutex_err;
1829         }
1830         ret = copy_from_user(exec_list,
1831                              (struct drm_i915_relocation_entry __user *)
1832                              (uintptr_t) args->buffers_ptr,
1833                              sizeof(*exec_list) * args->buffer_count);
1834         if (ret != 0) {
1835                 DRM_ERROR("copy %d exec entries failed %d\n",
1836                           args->buffer_count, ret);
1837                 goto pre_mutex_err;
1838         }
1839
1840         mutex_lock(&dev->struct_mutex);
1841
1842         i915_verify_inactive(dev, __FILE__, __LINE__);
1843
1844         if (dev_priv->mm.wedged) {
1845                 DRM_ERROR("Execbuf while wedged\n");
1846                 mutex_unlock(&dev->struct_mutex);
1847                 return -EIO;
1848         }
1849
1850         if (dev_priv->mm.suspended) {
1851                 DRM_ERROR("Execbuf while VT-switched.\n");
1852                 mutex_unlock(&dev->struct_mutex);
1853                 return -EBUSY;
1854         }
1855
1856         /* Zero the gloabl flush/invalidate flags. These
1857          * will be modified as each object is bound to the
1858          * gtt
1859          */
1860         dev->invalidate_domains = 0;
1861         dev->flush_domains = 0;
1862
1863         /* Look up object handles and perform the relocations */
1864         for (i = 0; i < args->buffer_count; i++) {
1865                 object_list[i] = drm_gem_object_lookup(dev, file_priv,
1866                                                        exec_list[i].handle);
1867                 if (object_list[i] == NULL) {
1868                         DRM_ERROR("Invalid object handle %d at index %d\n",
1869                                    exec_list[i].handle, i);
1870                         ret = -EBADF;
1871                         goto err;
1872                 }
1873
1874                 object_list[i]->pending_read_domains = 0;
1875                 object_list[i]->pending_write_domain = 0;
1876                 ret = i915_gem_object_pin_and_relocate(object_list[i],
1877                                                        file_priv,
1878                                                        &exec_list[i]);
1879                 if (ret) {
1880                         DRM_ERROR("object bind and relocate failed %d\n", ret);
1881                         goto err;
1882                 }
1883                 pinned = i + 1;
1884         }
1885
1886         /* Set the pending read domains for the batch buffer to COMMAND */
1887         batch_obj = object_list[args->buffer_count-1];
1888         batch_obj->pending_read_domains = I915_GEM_DOMAIN_COMMAND;
1889         batch_obj->pending_write_domain = 0;
1890
1891         i915_verify_inactive(dev, __FILE__, __LINE__);
1892
1893         for (i = 0; i < args->buffer_count; i++) {
1894                 struct drm_gem_object *obj = object_list[i];
1895                 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1896
1897                 if (obj_priv->gtt_space == NULL) {
1898                         /* We evicted the buffer in the process of validating
1899                          * our set of buffers in.  We could try to recover by
1900                          * kicking them everything out and trying again from
1901                          * the start.
1902                          */
1903                         ret = -ENOMEM;
1904                         goto err;
1905                 }
1906
1907                 /* make sure all previous memory operations have passed */
1908                 ret = i915_gem_object_set_domain(obj,
1909                                                  obj->pending_read_domains,
1910                                                  obj->pending_write_domain);
1911                 if (ret)
1912                         goto err;
1913         }
1914
1915         i915_verify_inactive(dev, __FILE__, __LINE__);
1916
1917         /* Flush/invalidate caches and chipset buffer */
1918         flush_domains = i915_gem_dev_set_domain(dev);
1919
1920         i915_verify_inactive(dev, __FILE__, __LINE__);
1921
1922 #if WATCH_COHERENCY
1923         for (i = 0; i < args->buffer_count; i++) {
1924                 i915_gem_object_check_coherency(object_list[i],
1925                                                 exec_list[i].handle);
1926         }
1927 #endif
1928
1929         exec_offset = exec_list[args->buffer_count - 1].offset;
1930
1931 #if WATCH_EXEC
1932         i915_gem_dump_object(object_list[args->buffer_count - 1],
1933                               args->batch_len,
1934                               __func__,
1935                               ~0);
1936 #endif
1937
1938         (void)i915_add_request(dev, flush_domains);
1939
1940         /* Exec the batchbuffer */
1941         ret = i915_dispatch_gem_execbuffer(dev, args, exec_offset);
1942         if (ret) {
1943                 DRM_ERROR("dispatch failed %d\n", ret);
1944                 goto err;
1945         }
1946
1947         /*
1948          * Ensure that the commands in the batch buffer are
1949          * finished before the interrupt fires
1950          */
1951         flush_domains = i915_retire_commands(dev);
1952
1953         i915_verify_inactive(dev, __FILE__, __LINE__);
1954
1955         /*
1956          * Get a seqno representing the execution of the current buffer,
1957          * which we can wait on.  We would like to mitigate these interrupts,
1958          * likely by only creating seqnos occasionally (so that we have
1959          * *some* interrupts representing completion of buffers that we can
1960          * wait on when trying to clear up gtt space).
1961          */
1962         seqno = i915_add_request(dev, flush_domains);
1963         BUG_ON(seqno == 0);
1964         i915_file_priv->mm.last_gem_seqno = seqno;
1965         for (i = 0; i < args->buffer_count; i++) {
1966                 struct drm_gem_object *obj = object_list[i];
1967                 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1968
1969                 i915_gem_object_move_to_active(obj);
1970                 obj_priv->last_rendering_seqno = seqno;
1971 #if WATCH_LRU
1972                 DRM_INFO("%s: move to exec list %p\n", __func__, obj);
1973 #endif
1974         }
1975 #if WATCH_LRU
1976         i915_dump_lru(dev, __func__);
1977 #endif
1978
1979         i915_verify_inactive(dev, __FILE__, __LINE__);
1980
1981         /* Copy the new buffer offsets back to the user's exec list. */
1982         ret = copy_to_user((struct drm_i915_relocation_entry __user *)
1983                            (uintptr_t) args->buffers_ptr,
1984                            exec_list,
1985                            sizeof(*exec_list) * args->buffer_count);
1986         if (ret)
1987                 DRM_ERROR("failed to copy %d exec entries "
1988                           "back to user (%d)\n",
1989                            args->buffer_count, ret);
1990 err:
1991         if (object_list != NULL) {
1992                 for (i = 0; i < pinned; i++)
1993                         i915_gem_object_unpin(object_list[i]);
1994
1995                 for (i = 0; i < args->buffer_count; i++)
1996                         drm_gem_object_unreference(object_list[i]);
1997         }
1998         mutex_unlock(&dev->struct_mutex);
1999
2000 pre_mutex_err:
2001         drm_free(object_list, sizeof(*object_list) * args->buffer_count,
2002                  DRM_MEM_DRIVER);
2003         drm_free(exec_list, sizeof(*exec_list) * args->buffer_count,
2004                  DRM_MEM_DRIVER);
2005
2006         return ret;
2007 }
2008
2009 int
2010 i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
2011 {
2012         struct drm_device *dev = obj->dev;
2013         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2014         int ret;
2015
2016         i915_verify_inactive(dev, __FILE__, __LINE__);
2017         if (obj_priv->gtt_space == NULL) {
2018                 ret = i915_gem_object_bind_to_gtt(obj, alignment);
2019                 if (ret != 0) {
2020                         DRM_ERROR("Failure to bind: %d", ret);
2021                         return ret;
2022                 }
2023         }
2024         obj_priv->pin_count++;
2025
2026         /* If the object is not active and not pending a flush,
2027          * remove it from the inactive list
2028          */
2029         if (obj_priv->pin_count == 1) {
2030                 atomic_inc(&dev->pin_count);
2031                 atomic_add(obj->size, &dev->pin_memory);
2032                 if (!obj_priv->active &&
2033                     (obj->write_domain & ~(I915_GEM_DOMAIN_CPU |
2034                                            I915_GEM_DOMAIN_GTT)) == 0 &&
2035                     !list_empty(&obj_priv->list))
2036                         list_del_init(&obj_priv->list);
2037         }
2038         i915_verify_inactive(dev, __FILE__, __LINE__);
2039
2040         return 0;
2041 }
2042
2043 void
2044 i915_gem_object_unpin(struct drm_gem_object *obj)
2045 {
2046         struct drm_device *dev = obj->dev;
2047         drm_i915_private_t *dev_priv = dev->dev_private;
2048         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2049
2050         i915_verify_inactive(dev, __FILE__, __LINE__);
2051         obj_priv->pin_count--;
2052         BUG_ON(obj_priv->pin_count < 0);
2053         BUG_ON(obj_priv->gtt_space == NULL);
2054
2055         /* If the object is no longer pinned, and is
2056          * neither active nor being flushed, then stick it on
2057          * the inactive list
2058          */
2059         if (obj_priv->pin_count == 0) {
2060                 if (!obj_priv->active &&
2061                     (obj->write_domain & ~(I915_GEM_DOMAIN_CPU |
2062                                            I915_GEM_DOMAIN_GTT)) == 0)
2063                         list_move_tail(&obj_priv->list,
2064                                        &dev_priv->mm.inactive_list);
2065                 atomic_dec(&dev->pin_count);
2066                 atomic_sub(obj->size, &dev->pin_memory);
2067         }
2068         i915_verify_inactive(dev, __FILE__, __LINE__);
2069 }
2070
2071 int
2072 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
2073                    struct drm_file *file_priv)
2074 {
2075         struct drm_i915_gem_pin *args = data;
2076         struct drm_gem_object *obj;
2077         struct drm_i915_gem_object *obj_priv;
2078         int ret;
2079
2080         mutex_lock(&dev->struct_mutex);
2081
2082         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
2083         if (obj == NULL) {
2084                 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
2085                           args->handle);
2086                 mutex_unlock(&dev->struct_mutex);
2087                 return -EBADF;
2088         }
2089         obj_priv = obj->driver_private;
2090
2091         ret = i915_gem_object_pin(obj, args->alignment);
2092         if (ret != 0) {
2093                 drm_gem_object_unreference(obj);
2094                 mutex_unlock(&dev->struct_mutex);
2095                 return ret;
2096         }
2097
2098         /* XXX - flush the CPU caches for pinned objects
2099          * as the X server doesn't manage domains yet
2100          */
2101         if (obj->write_domain & I915_GEM_DOMAIN_CPU) {
2102                 i915_gem_clflush_object(obj);
2103                 drm_agp_chipset_flush(dev);
2104                 obj->write_domain = 0;
2105         }
2106         args->offset = obj_priv->gtt_offset;
2107         drm_gem_object_unreference(obj);
2108         mutex_unlock(&dev->struct_mutex);
2109
2110         return 0;
2111 }
2112
2113 int
2114 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
2115                      struct drm_file *file_priv)
2116 {
2117         struct drm_i915_gem_pin *args = data;
2118         struct drm_gem_object *obj;
2119
2120         mutex_lock(&dev->struct_mutex);
2121
2122         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
2123         if (obj == NULL) {
2124                 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
2125                           args->handle);
2126                 mutex_unlock(&dev->struct_mutex);
2127                 return -EBADF;
2128         }
2129
2130         i915_gem_object_unpin(obj);
2131
2132         drm_gem_object_unreference(obj);
2133         mutex_unlock(&dev->struct_mutex);
2134         return 0;
2135 }
2136
2137 int
2138 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2139                     struct drm_file *file_priv)
2140 {
2141         struct drm_i915_gem_busy *args = data;
2142         struct drm_gem_object *obj;
2143         struct drm_i915_gem_object *obj_priv;
2144
2145         mutex_lock(&dev->struct_mutex);
2146         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
2147         if (obj == NULL) {
2148                 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
2149                           args->handle);
2150                 mutex_unlock(&dev->struct_mutex);
2151                 return -EBADF;
2152         }
2153
2154         obj_priv = obj->driver_private;
2155         args->busy = obj_priv->active;
2156
2157         drm_gem_object_unreference(obj);
2158         mutex_unlock(&dev->struct_mutex);
2159         return 0;
2160 }
2161
2162 int
2163 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2164                         struct drm_file *file_priv)
2165 {
2166     return i915_gem_ring_throttle(dev, file_priv);
2167 }
2168
2169 int i915_gem_init_object(struct drm_gem_object *obj)
2170 {
2171         struct drm_i915_gem_object *obj_priv;
2172
2173         obj_priv = drm_calloc(1, sizeof(*obj_priv), DRM_MEM_DRIVER);
2174         if (obj_priv == NULL)
2175                 return -ENOMEM;
2176
2177         /*
2178          * We've just allocated pages from the kernel,
2179          * so they've just been written by the CPU with
2180          * zeros. They'll need to be clflushed before we
2181          * use them with the GPU.
2182          */
2183         obj->write_domain = I915_GEM_DOMAIN_CPU;
2184         obj->read_domains = I915_GEM_DOMAIN_CPU;
2185
2186         obj_priv->agp_type = AGP_USER_MEMORY;
2187
2188         obj->driver_private = obj_priv;
2189         obj_priv->obj = obj;
2190         INIT_LIST_HEAD(&obj_priv->list);
2191         return 0;
2192 }
2193
2194 void i915_gem_free_object(struct drm_gem_object *obj)
2195 {
2196         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2197
2198         while (obj_priv->pin_count > 0)
2199                 i915_gem_object_unpin(obj);
2200
2201         i915_gem_object_unbind(obj);
2202
2203         drm_free(obj_priv->page_cpu_valid, 1, DRM_MEM_DRIVER);
2204         drm_free(obj->driver_private, 1, DRM_MEM_DRIVER);
2205 }
2206
2207 static int
2208 i915_gem_set_domain(struct drm_gem_object *obj,
2209                     struct drm_file *file_priv,
2210                     uint32_t read_domains,
2211                     uint32_t write_domain)
2212 {
2213         struct drm_device *dev = obj->dev;
2214         int ret;
2215         uint32_t flush_domains;
2216
2217         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
2218
2219         ret = i915_gem_object_set_domain(obj, read_domains, write_domain);
2220         if (ret)
2221                 return ret;
2222         flush_domains = i915_gem_dev_set_domain(obj->dev);
2223
2224         if (flush_domains & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT))
2225                 (void) i915_add_request(dev, flush_domains);
2226
2227         return 0;
2228 }
2229
2230 /** Unbinds all objects that are on the given buffer list. */
2231 static int
2232 i915_gem_evict_from_list(struct drm_device *dev, struct list_head *head)
2233 {
2234         struct drm_gem_object *obj;
2235         struct drm_i915_gem_object *obj_priv;
2236         int ret;
2237
2238         while (!list_empty(head)) {
2239                 obj_priv = list_first_entry(head,
2240                                             struct drm_i915_gem_object,
2241                                             list);
2242                 obj = obj_priv->obj;
2243
2244                 if (obj_priv->pin_count != 0) {
2245                         DRM_ERROR("Pinned object in unbind list\n");
2246                         mutex_unlock(&dev->struct_mutex);
2247                         return -EINVAL;
2248                 }
2249
2250                 ret = i915_gem_object_unbind(obj);
2251                 if (ret != 0) {
2252                         DRM_ERROR("Error unbinding object in LeaveVT: %d\n",
2253                                   ret);
2254                         mutex_unlock(&dev->struct_mutex);
2255                         return ret;
2256                 }
2257         }
2258
2259
2260         return 0;
2261 }
2262
2263 static int
2264 i915_gem_idle(struct drm_device *dev)
2265 {
2266         drm_i915_private_t *dev_priv = dev->dev_private;
2267         uint32_t seqno, cur_seqno, last_seqno;
2268         int stuck, ret;
2269
2270         mutex_lock(&dev->struct_mutex);
2271
2272         if (dev_priv->mm.suspended || dev_priv->ring.ring_obj == NULL) {
2273                 mutex_unlock(&dev->struct_mutex);
2274                 return 0;
2275         }
2276
2277         /* Hack!  Don't let anybody do execbuf while we don't control the chip.
2278          * We need to replace this with a semaphore, or something.
2279          */
2280         dev_priv->mm.suspended = 1;
2281
2282         /* Cancel the retire work handler, wait for it to finish if running
2283          */
2284         mutex_unlock(&dev->struct_mutex);
2285         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
2286         mutex_lock(&dev->struct_mutex);
2287
2288         i915_kernel_lost_context(dev);
2289
2290         /* Flush the GPU along with all non-CPU write domains
2291          */
2292         i915_gem_flush(dev, ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT),
2293                        ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT));
2294         seqno = i915_add_request(dev, ~(I915_GEM_DOMAIN_CPU |
2295                                         I915_GEM_DOMAIN_GTT));
2296
2297         if (seqno == 0) {
2298                 mutex_unlock(&dev->struct_mutex);
2299                 return -ENOMEM;
2300         }
2301
2302         dev_priv->mm.waiting_gem_seqno = seqno;
2303         last_seqno = 0;
2304         stuck = 0;
2305         for (;;) {
2306                 cur_seqno = i915_get_gem_seqno(dev);
2307                 if (i915_seqno_passed(cur_seqno, seqno))
2308                         break;
2309                 if (last_seqno == cur_seqno) {
2310                         if (stuck++ > 100) {
2311                                 DRM_ERROR("hardware wedged\n");
2312                                 dev_priv->mm.wedged = 1;
2313                                 DRM_WAKEUP(&dev_priv->irq_queue);
2314                                 break;
2315                         }
2316                 }
2317                 msleep(10);
2318                 last_seqno = cur_seqno;
2319         }
2320         dev_priv->mm.waiting_gem_seqno = 0;
2321
2322         i915_gem_retire_requests(dev);
2323
2324         /* Active and flushing should now be empty as we've
2325          * waited for a sequence higher than any pending execbuffer
2326          */
2327         BUG_ON(!list_empty(&dev_priv->mm.active_list));
2328         BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
2329
2330         /* Request should now be empty as we've also waited
2331          * for the last request in the list
2332          */
2333         BUG_ON(!list_empty(&dev_priv->mm.request_list));
2334
2335         /* Move all buffers out of the GTT. */
2336         ret = i915_gem_evict_from_list(dev, &dev_priv->mm.inactive_list);
2337         if (ret) {
2338                 mutex_unlock(&dev->struct_mutex);
2339                 return ret;
2340         }
2341
2342         BUG_ON(!list_empty(&dev_priv->mm.active_list));
2343         BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
2344         BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
2345         BUG_ON(!list_empty(&dev_priv->mm.request_list));
2346
2347         i915_gem_cleanup_ringbuffer(dev);
2348         mutex_unlock(&dev->struct_mutex);
2349
2350         return 0;
2351 }
2352
2353 static int
2354 i915_gem_init_hws(struct drm_device *dev)
2355 {
2356         drm_i915_private_t *dev_priv = dev->dev_private;
2357         struct drm_gem_object *obj;
2358         struct drm_i915_gem_object *obj_priv;
2359         int ret;
2360
2361         /* If we need a physical address for the status page, it's already
2362          * initialized at driver load time.
2363          */
2364         if (!I915_NEED_GFX_HWS(dev))
2365                 return 0;
2366
2367         obj = drm_gem_object_alloc(dev, 4096);
2368         if (obj == NULL) {
2369                 DRM_ERROR("Failed to allocate status page\n");
2370                 return -ENOMEM;
2371         }
2372         obj_priv = obj->driver_private;
2373         obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
2374
2375         ret = i915_gem_object_pin(obj, 4096);
2376         if (ret != 0) {
2377                 drm_gem_object_unreference(obj);
2378                 return ret;
2379         }
2380
2381         dev_priv->status_gfx_addr = obj_priv->gtt_offset;
2382
2383         dev_priv->hw_status_page = kmap(obj_priv->page_list[0]);
2384         if (dev_priv->hw_status_page == NULL) {
2385                 DRM_ERROR("Failed to map status page.\n");
2386                 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
2387                 drm_gem_object_unreference(obj);
2388                 return -EINVAL;
2389         }
2390         dev_priv->hws_obj = obj;
2391         memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
2392         I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
2393         I915_READ(HWS_PGA); /* posting read */
2394         DRM_DEBUG("hws offset: 0x%08x\n", dev_priv->status_gfx_addr);
2395
2396         return 0;
2397 }
2398
2399 static int
2400 i915_gem_init_ringbuffer(struct drm_device *dev)
2401 {
2402         drm_i915_private_t *dev_priv = dev->dev_private;
2403         struct drm_gem_object *obj;
2404         struct drm_i915_gem_object *obj_priv;
2405         int ret;
2406         u32 head;
2407
2408         ret = i915_gem_init_hws(dev);
2409         if (ret != 0)
2410                 return ret;
2411
2412         obj = drm_gem_object_alloc(dev, 128 * 1024);
2413         if (obj == NULL) {
2414                 DRM_ERROR("Failed to allocate ringbuffer\n");
2415                 return -ENOMEM;
2416         }
2417         obj_priv = obj->driver_private;
2418
2419         ret = i915_gem_object_pin(obj, 4096);
2420         if (ret != 0) {
2421                 drm_gem_object_unreference(obj);
2422                 return ret;
2423         }
2424
2425         /* Set up the kernel mapping for the ring. */
2426         dev_priv->ring.Size = obj->size;
2427         dev_priv->ring.tail_mask = obj->size - 1;
2428
2429         dev_priv->ring.map.offset = dev->agp->base + obj_priv->gtt_offset;
2430         dev_priv->ring.map.size = obj->size;
2431         dev_priv->ring.map.type = 0;
2432         dev_priv->ring.map.flags = 0;
2433         dev_priv->ring.map.mtrr = 0;
2434
2435         drm_core_ioremap_wc(&dev_priv->ring.map, dev);
2436         if (dev_priv->ring.map.handle == NULL) {
2437                 DRM_ERROR("Failed to map ringbuffer.\n");
2438                 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
2439                 drm_gem_object_unreference(obj);
2440                 return -EINVAL;
2441         }
2442         dev_priv->ring.ring_obj = obj;
2443         dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
2444
2445         /* Stop the ring if it's running. */
2446         I915_WRITE(PRB0_CTL, 0);
2447         I915_WRITE(PRB0_TAIL, 0);
2448         I915_WRITE(PRB0_HEAD, 0);
2449
2450         /* Initialize the ring. */
2451         I915_WRITE(PRB0_START, obj_priv->gtt_offset);
2452         head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
2453
2454         /* G45 ring initialization fails to reset head to zero */
2455         if (head != 0) {
2456                 DRM_ERROR("Ring head not reset to zero "
2457                           "ctl %08x head %08x tail %08x start %08x\n",
2458                           I915_READ(PRB0_CTL),
2459                           I915_READ(PRB0_HEAD),
2460                           I915_READ(PRB0_TAIL),
2461                           I915_READ(PRB0_START));
2462                 I915_WRITE(PRB0_HEAD, 0);
2463
2464                 DRM_ERROR("Ring head forced to zero "
2465                           "ctl %08x head %08x tail %08x start %08x\n",
2466                           I915_READ(PRB0_CTL),
2467                           I915_READ(PRB0_HEAD),
2468                           I915_READ(PRB0_TAIL),
2469                           I915_READ(PRB0_START));
2470         }
2471
2472         I915_WRITE(PRB0_CTL,
2473                    ((obj->size - 4096) & RING_NR_PAGES) |
2474                    RING_NO_REPORT |
2475                    RING_VALID);
2476
2477         head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
2478
2479         /* If the head is still not zero, the ring is dead */
2480         if (head != 0) {
2481                 DRM_ERROR("Ring initialization failed "
2482                           "ctl %08x head %08x tail %08x start %08x\n",
2483                           I915_READ(PRB0_CTL),
2484                           I915_READ(PRB0_HEAD),
2485                           I915_READ(PRB0_TAIL),
2486                           I915_READ(PRB0_START));
2487                 return -EIO;
2488         }
2489
2490         /* Update our cache of the ring state */
2491         i915_kernel_lost_context(dev);
2492
2493         return 0;
2494 }
2495
2496 static void
2497 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
2498 {
2499         drm_i915_private_t *dev_priv = dev->dev_private;
2500
2501         if (dev_priv->ring.ring_obj == NULL)
2502                 return;
2503
2504         drm_core_ioremapfree(&dev_priv->ring.map, dev);
2505
2506         i915_gem_object_unpin(dev_priv->ring.ring_obj);
2507         drm_gem_object_unreference(dev_priv->ring.ring_obj);
2508         dev_priv->ring.ring_obj = NULL;
2509         memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
2510
2511         if (dev_priv->hws_obj != NULL) {
2512                 struct drm_gem_object *obj = dev_priv->hws_obj;
2513                 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2514
2515                 kunmap(obj_priv->page_list[0]);
2516                 i915_gem_object_unpin(obj);
2517                 drm_gem_object_unreference(obj);
2518                 dev_priv->hws_obj = NULL;
2519                 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
2520                 dev_priv->hw_status_page = NULL;
2521
2522                 /* Write high address into HWS_PGA when disabling. */
2523                 I915_WRITE(HWS_PGA, 0x1ffff000);
2524         }
2525 }
2526
2527 int
2528 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
2529                        struct drm_file *file_priv)
2530 {
2531         drm_i915_private_t *dev_priv = dev->dev_private;
2532         int ret;
2533
2534         if (dev_priv->mm.wedged) {
2535                 DRM_ERROR("Reenabling wedged hardware, good luck\n");
2536                 dev_priv->mm.wedged = 0;
2537         }
2538
2539         ret = i915_gem_init_ringbuffer(dev);
2540         if (ret != 0)
2541                 return ret;
2542
2543         mutex_lock(&dev->struct_mutex);
2544         BUG_ON(!list_empty(&dev_priv->mm.active_list));
2545         BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
2546         BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
2547         BUG_ON(!list_empty(&dev_priv->mm.request_list));
2548         dev_priv->mm.suspended = 0;
2549         mutex_unlock(&dev->struct_mutex);
2550
2551         drm_irq_install(dev);
2552
2553         return 0;
2554 }
2555
2556 int
2557 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
2558                        struct drm_file *file_priv)
2559 {
2560         int ret;
2561
2562         ret = i915_gem_idle(dev);
2563         drm_irq_uninstall(dev);
2564
2565         return ret;
2566 }
2567
2568 void
2569 i915_gem_lastclose(struct drm_device *dev)
2570 {
2571         int ret;
2572
2573         ret = i915_gem_idle(dev);
2574         if (ret)
2575                 DRM_ERROR("failed to idle hardware: %d\n", ret);
2576 }
2577
2578 void
2579 i915_gem_load(struct drm_device *dev)
2580 {
2581         drm_i915_private_t *dev_priv = dev->dev_private;
2582
2583         INIT_LIST_HEAD(&dev_priv->mm.active_list);
2584         INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
2585         INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
2586         INIT_LIST_HEAD(&dev_priv->mm.request_list);
2587         INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
2588                           i915_gem_retire_work_handler);
2589         dev_priv->mm.next_gem_seqno = 1;
2590
2591         i915_gem_detect_bit_6_swizzle(dev);
2592 }