drivers/gpu/drm/i915/i915_gem.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include "drmP.h"
  29 #include "drm.h"
  30 #include "i915_drm.h"
  31 #include "i915_drv.h"
  32 #include <linux/swap.h>
  33
  34 #define I915_GEM_GPU_DOMAINS    (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
  35
  36 static int
  37 i915_gem_object_set_domain(struct drm_gem_object *obj,
  38                             uint32_t read_domains,
  39                             uint32_t write_domain);
  40 static int
  41 i915_gem_object_set_domain_range(struct drm_gem_object *obj,
  42                                  uint64_t offset,
  43                                  uint64_t size,
  44                                  uint32_t read_domains,
  45                                  uint32_t write_domain);
  46 static int
  47 i915_gem_set_domain(struct drm_gem_object *obj,
  48                     struct drm_file *file_priv,
  49                     uint32_t read_domains,
  50                     uint32_t write_domain);
  51 static int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj,
  52                                              int write);
  53 static int i915_gem_object_get_page_list(struct drm_gem_object *obj);
  54 static void i915_gem_object_free_page_list(struct drm_gem_object *obj);
  55 static int i915_gem_object_wait_rendering(struct drm_gem_object *obj);
  56
  57 static void
  58 i915_gem_cleanup_ringbuffer(struct drm_device *dev);
  59
  60 int
  61 i915_gem_init_ioctl(struct drm_device *dev, void *data,
  62                     struct drm_file *file_priv)
  63 {
  64         drm_i915_private_t *dev_priv = dev->dev_private;
  65         struct drm_i915_gem_init *args = data;
  66
  67         mutex_lock(&dev->struct_mutex);
  68
  69         if (args->gtt_start >= args->gtt_end ||
  70             (args->gtt_start & (PAGE_SIZE - 1)) != 0 ||
  71             (args->gtt_end & (PAGE_SIZE - 1)) != 0) {
  72                 mutex_unlock(&dev->struct_mutex);
  73                 return -EINVAL;
  74         }
  75
  76         drm_mm_init(&dev_priv->mm.gtt_space, args->gtt_start,
  77             args->gtt_end - args->gtt_start);
  78
  79         dev->gtt_total = (uint32_t) (args->gtt_end - args->gtt_start);
  80
  81         mutex_unlock(&dev->struct_mutex);
  82
  83         return 0;
  84 }
  85
  86 int
  87 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
  88                             struct drm_file *file_priv)
  89 {
  90         struct drm_i915_gem_get_aperture *args = data;
  91
  92         if (!(dev->driver->driver_features & DRIVER_GEM))
  93                 return -ENODEV;
  94
  95         args->aper_size = dev->gtt_total;
  96         args->aper_available_size = (args->aper_size -
  97                                      atomic_read(&dev->pin_memory));
  98
  99         return 0;
 100 }
 101
 102
 103 /**
 104  * Creates a new mm object and returns a handle to it.
 105  */
 106 int
 107 i915_gem_create_ioctl(struct drm_device *dev, void *data,
 108                       struct drm_file *file_priv)
 109 {
 110         struct drm_i915_gem_create *args = data;
 111         struct drm_gem_object *obj;
 112         int handle, ret;
 113
 114         args->size = roundup(args->size, PAGE_SIZE);
 115
 116         /* Allocate the new object */
 117         obj = drm_gem_object_alloc(dev, args->size);
 118         if (obj == NULL)
 119                 return -ENOMEM;
 120
 121         ret = drm_gem_handle_create(file_priv, obj, &handle);
 122         mutex_lock(&dev->struct_mutex);
 123         drm_gem_object_handle_unreference(obj);
 124         mutex_unlock(&dev->struct_mutex);
 125
 126         if (ret)
 127                 return ret;
 128
 129         args->handle = handle;
 130
 131         return 0;
 132 }
 133
 134 /**
 135  * Reads data from the object referenced by handle.
 136  *
 137  * On error, the contents of *data are undefined.
 138  */
 139 int
 140 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
 141                      struct drm_file *file_priv)
 142 {
 143         struct drm_i915_gem_pread *args = data;
 144         struct drm_gem_object *obj;
 145         struct drm_i915_gem_object *obj_priv;
 146         ssize_t read;
 147         loff_t offset;
 148         int ret;
 149
 150         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
 151         if (obj == NULL)
 152                 return -EBADF;
 153         obj_priv = obj->driver_private;
 154
 155         /* Bounds check source.
 156          *
 157          * XXX: This could use review for overflow issues...
 158          */
 159         if (args->offset > obj->size || args->size > obj->size ||
 160             args->offset + args->size > obj->size) {
 161                 drm_gem_object_unreference(obj);
 162                 return -EINVAL;
 163         }
 164
 165         mutex_lock(&dev->struct_mutex);
 166
 167         ret = i915_gem_object_set_domain_range(obj, args->offset, args->size,
 168                                                I915_GEM_DOMAIN_CPU, 0);
 169         if (ret != 0) {
 170                 drm_gem_object_unreference(obj);
 171                 mutex_unlock(&dev->struct_mutex);
 172                 return ret;
 173         }
 174
 175         offset = args->offset;
 176
 177         read = vfs_read(obj->filp, (char __user *)(uintptr_t)args->data_ptr,
 178                         args->size, &offset);
 179         if (read != args->size) {
 180                 drm_gem_object_unreference(obj);
 181                 mutex_unlock(&dev->struct_mutex);
 182                 if (read < 0)
 183                         return read;
 184                 else
 185                         return -EINVAL;
 186         }
 187
 188         drm_gem_object_unreference(obj);
 189         mutex_unlock(&dev->struct_mutex);
 190
 191         return 0;
 192 }
 193
 194 /* This is the fast write path which cannot handle
 195  * page faults in the source data
 196  */
 197
 198 static inline int
 199 fast_user_write(struct io_mapping *mapping,
 200                 loff_t page_base, int page_offset,
 201                 char __user *user_data,
 202                 int length)
 203 {
 204         char *vaddr_atomic;
 205         unsigned long unwritten;
 206
 207         vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
 208         unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
 209                                                       user_data, length);
 210         io_mapping_unmap_atomic(vaddr_atomic);
 211         if (unwritten)
 212                 return -EFAULT;
 213         return 0;
 214 }
 215
 216 /* Here's the write path which can sleep for
 217  * page faults
 218  */
 219
 220 static inline int
 221 slow_user_write(struct io_mapping *mapping,
 222                 loff_t page_base, int page_offset,
 223                 char __user *user_data,
 224                 int length)
 225 {
 226         char __iomem *vaddr;
 227         unsigned long unwritten;
 228
 229         vaddr = io_mapping_map_wc(mapping, page_base);
 230         if (vaddr == NULL)
 231                 return -EFAULT;
 232         unwritten = __copy_from_user(vaddr + page_offset,
 233                                      user_data, length);
 234         io_mapping_unmap(vaddr);
 235         if (unwritten)
 236                 return -EFAULT;
 237         return 0;
 238 }
 239
 240 static int
 241 i915_gem_gtt_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
 242                     struct drm_i915_gem_pwrite *args,
 243                     struct drm_file *file_priv)
 244 {
 245         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 246         drm_i915_private_t *dev_priv = dev->dev_private;
 247         ssize_t remain;
 248         loff_t offset, page_base;
 249         char __user *user_data;
 250         int page_offset, page_length;
 251         int ret;
 252
 253         user_data = (char __user *) (uintptr_t) args->data_ptr;
 254         remain = args->size;
 255         if (!access_ok(VERIFY_READ, user_data, remain))
 256                 return -EFAULT;
 257
 258
 259         mutex_lock(&dev->struct_mutex);
 260         ret = i915_gem_object_pin(obj, 0);
 261         if (ret) {
 262                 mutex_unlock(&dev->struct_mutex);
 263                 return ret;
 264         }
 265         ret = i915_gem_object_set_to_gtt_domain(obj, 1);
 266         if (ret)
 267                 goto fail;
 268
 269         obj_priv = obj->driver_private;
 270         offset = obj_priv->gtt_offset + args->offset;
 271         obj_priv->dirty = 1;
 272
 273         while (remain > 0) {
 274                 /* Operation in this page
 275                  *
 276                  * page_base = page offset within aperture
 277                  * page_offset = offset within page
 278                  * page_length = bytes to copy for this page
 279                  */
 280                 page_base = (offset & ~(PAGE_SIZE-1));
 281                 page_offset = offset & (PAGE_SIZE-1);
 282                 page_length = remain;
 283                 if ((page_offset + remain) > PAGE_SIZE)
 284                         page_length = PAGE_SIZE - page_offset;
 285
 286                 ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base,
 287                                        page_offset, user_data, page_length);
 288
 289                 /* If we get a fault while copying data, then (presumably) our
 290                  * source page isn't available. In this case, use the
 291                  * non-atomic function
 292                  */
 293                 if (ret) {
 294                         ret = slow_user_write (dev_priv->mm.gtt_mapping,
 295                                                page_base, page_offset,
 296                                                user_data, page_length);
 297                         if (ret)
 298                                 goto fail;
 299                 }
 300
 301                 remain -= page_length;
 302                 user_data += page_length;
 303                 offset += page_length;
 304         }
 305
 306 fail:
 307         i915_gem_object_unpin(obj);
 308         mutex_unlock(&dev->struct_mutex);
 309
 310         return ret;
 311 }
 312
 313 static int
 314 i915_gem_shmem_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
 315                       struct drm_i915_gem_pwrite *args,
 316                       struct drm_file *file_priv)
 317 {
 318         int ret;
 319         loff_t offset;
 320         ssize_t written;
 321
 322         mutex_lock(&dev->struct_mutex);
 323
 324         ret = i915_gem_set_domain(obj, file_priv,
 325                                   I915_GEM_DOMAIN_CPU, I915_GEM_DOMAIN_CPU);
 326         if (ret) {
 327                 mutex_unlock(&dev->struct_mutex);
 328                 return ret;
 329         }
 330
 331         offset = args->offset;
 332
 333         written = vfs_write(obj->filp,
 334                             (char __user *)(uintptr_t) args->data_ptr,
 335                             args->size, &offset);
 336         if (written != args->size) {
 337                 mutex_unlock(&dev->struct_mutex);
 338                 if (written < 0)
 339                         return written;
 340                 else
 341                         return -EINVAL;
 342         }
 343
 344         mutex_unlock(&dev->struct_mutex);
 345
 346         return 0;
 347 }
 348
 349 /**
 350  * Writes data to the object referenced by handle.
 351  *
 352  * On error, the contents of the buffer that were to be modified are undefined.
 353  */
 354 int
 355 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
 356                       struct drm_file *file_priv)
 357 {
 358         struct drm_i915_gem_pwrite *args = data;
 359         struct drm_gem_object *obj;
 360         struct drm_i915_gem_object *obj_priv;
 361         int ret = 0;
 362
 363         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
 364         if (obj == NULL)
 365                 return -EBADF;
 366         obj_priv = obj->driver_private;
 367
 368         /* Bounds check destination.
 369          *
 370          * XXX: This could use review for overflow issues...
 371          */
 372         if (args->offset > obj->size || args->size > obj->size ||
 373             args->offset + args->size > obj->size) {
 374                 drm_gem_object_unreference(obj);
 375                 return -EINVAL;
 376         }
 377
 378         /* We can only do the GTT pwrite on untiled buffers, as otherwise
 379          * it would end up going through the fenced access, and we'll get
 380          * different detiling behavior between reading and writing.
 381          * pread/pwrite currently are reading and writing from the CPU
 382          * perspective, requiring manual detiling by the client.
 383          */
 384         if (obj_priv->tiling_mode == I915_TILING_NONE &&
 385             dev->gtt_total != 0)
 386                 ret = i915_gem_gtt_pwrite(dev, obj, args, file_priv);
 387         else
 388                 ret = i915_gem_shmem_pwrite(dev, obj, args, file_priv);
 389
 390 #if WATCH_PWRITE
 391         if (ret)
 392                 DRM_INFO("pwrite failed %d\n", ret);
 393 #endif
 394
 395         drm_gem_object_unreference(obj);
 396
 397         return ret;
 398 }
 399
 400 /**
 401  * Called when user space prepares to use an object with the CPU, either
 402  * through the mmap ioctl's mapping or a GTT mapping.
 403  */
 404 int
 405 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
 406                           struct drm_file *file_priv)
 407 {
 408         struct drm_i915_gem_set_domain *args = data;
 409         struct drm_gem_object *obj;
 410         uint32_t read_domains = args->read_domains;
 411         uint32_t write_domain = args->write_domain;
 412         int ret;
 413
 414         if (!(dev->driver->driver_features & DRIVER_GEM))
 415                 return -ENODEV;
 416
 417         /* Only handle setting domains to types used by the CPU. */
 418         if (write_domain & ~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
 419                 return -EINVAL;
 420
 421         if (read_domains & ~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
 422                 return -EINVAL;
 423
 424         /* Having something in the write domain implies it's in the read
 425          * domain, and only that read domain.  Enforce that in the request.
 426          */
 427         if (write_domain != 0 && read_domains != write_domain)
 428                 return -EINVAL;
 429
 430         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
 431         if (obj == NULL)
 432                 return -EBADF;
 433
 434         mutex_lock(&dev->struct_mutex);
 435 #if WATCH_BUF
 436         DRM_INFO("set_domain_ioctl %p(%d), %08x %08x\n",
 437                  obj, obj->size, read_domains, write_domain);
 438 #endif
 439         if (read_domains & I915_GEM_DOMAIN_GTT) {
 440                 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
 441         } else {
 442                 ret = i915_gem_set_domain(obj, file_priv,
 443                                           read_domains, write_domain);
 444         }
 445
 446         drm_gem_object_unreference(obj);
 447         mutex_unlock(&dev->struct_mutex);
 448         return ret;
 449 }
 450
 451 /**
 452  * Called when user space has done writes to this buffer
 453  */
 454 int
 455 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
 456                       struct drm_file *file_priv)
 457 {
 458         struct drm_i915_gem_sw_finish *args = data;
 459         struct drm_gem_object *obj;
 460         struct drm_i915_gem_object *obj_priv;
 461         int ret = 0;
 462
 463         if (!(dev->driver->driver_features & DRIVER_GEM))
 464                 return -ENODEV;
 465
 466         mutex_lock(&dev->struct_mutex);
 467         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
 468         if (obj == NULL) {
 469                 mutex_unlock(&dev->struct_mutex);
 470                 return -EBADF;
 471         }
 472
 473 #if WATCH_BUF
 474         DRM_INFO("%s: sw_finish %d (%p %d)\n",
 475                  __func__, args->handle, obj, obj->size);
 476 #endif
 477         obj_priv = obj->driver_private;
 478
 479         /* Pinned buffers may be scanout, so flush the cache */
 480         if ((obj->write_domain & I915_GEM_DOMAIN_CPU) && obj_priv->pin_count) {
 481                 i915_gem_clflush_object(obj);
 482                 drm_agp_chipset_flush(dev);
 483         }
 484         drm_gem_object_unreference(obj);
 485         mutex_unlock(&dev->struct_mutex);
 486         return ret;
 487 }
 488
 489 /**
 490  * Maps the contents of an object, returning the address it is mapped
 491  * into.
 492  *
 493  * While the mapping holds a reference on the contents of the object, it doesn't
 494  * imply a ref on the object itself.
 495  */
 496 int
 497 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
 498                    struct drm_file *file_priv)
 499 {
 500         struct drm_i915_gem_mmap *args = data;
 501         struct drm_gem_object *obj;
 502         loff_t offset;
 503         unsigned long addr;
 504
 505         if (!(dev->driver->driver_features & DRIVER_GEM))
 506                 return -ENODEV;
 507
 508         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
 509         if (obj == NULL)
 510                 return -EBADF;
 511
 512         offset = args->offset;
 513
 514         down_write(&current->mm->mmap_sem);
 515         addr = do_mmap(obj->filp, 0, args->size,
 516                        PROT_READ | PROT_WRITE, MAP_SHARED,
 517                        args->offset);
 518         up_write(&current->mm->mmap_sem);
 519         mutex_lock(&dev->struct_mutex);
 520         drm_gem_object_unreference(obj);
 521         mutex_unlock(&dev->struct_mutex);
 522         if (IS_ERR((void *)addr))
 523                 return addr;
 524
 525         args->addr_ptr = (uint64_t) addr;
 526
 527         return 0;
 528 }
 529
 530 static void
 531 i915_gem_object_free_page_list(struct drm_gem_object *obj)
 532 {
 533         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 534         int page_count = obj->size / PAGE_SIZE;
 535         int i;
 536
 537         if (obj_priv->page_list == NULL)
 538                 return;
 539
 540
 541         for (i = 0; i < page_count; i++)
 542                 if (obj_priv->page_list[i] != NULL) {
 543                         if (obj_priv->dirty)
 544                                 set_page_dirty(obj_priv->page_list[i]);
 545                         mark_page_accessed(obj_priv->page_list[i]);
 546                         page_cache_release(obj_priv->page_list[i]);
 547                 }
 548         obj_priv->dirty = 0;
 549
 550         drm_free(obj_priv->page_list,
 551                  page_count * sizeof(struct page *),
 552                  DRM_MEM_DRIVER);
 553         obj_priv->page_list = NULL;
 554 }
 555
 556 static void
 557 i915_gem_object_move_to_active(struct drm_gem_object *obj, uint32_t seqno)
 558 {
 559         struct drm_device *dev = obj->dev;
 560         drm_i915_private_t *dev_priv = dev->dev_private;
 561         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 562
 563         /* Add a reference if we're newly entering the active list. */
 564         if (!obj_priv->active) {
 565                 drm_gem_object_reference(obj);
 566                 obj_priv->active = 1;
 567         }
 568         /* Move from whatever list we were on to the tail of execution. */
 569         list_move_tail(&obj_priv->list,
 570                        &dev_priv->mm.active_list);
 571         obj_priv->last_rendering_seqno = seqno;
 572 }
 573
 574 static void
 575 i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
 576 {
 577         struct drm_device *dev = obj->dev;
 578         drm_i915_private_t *dev_priv = dev->dev_private;
 579         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 580
 581         BUG_ON(!obj_priv->active);
 582         list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list);
 583         obj_priv->last_rendering_seqno = 0;
 584 }
 585
 586 static void
 587 i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
 588 {
 589         struct drm_device *dev = obj->dev;
 590         drm_i915_private_t *dev_priv = dev->dev_private;
 591         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 592
 593         i915_verify_inactive(dev, __FILE__, __LINE__);
 594         if (obj_priv->pin_count != 0)
 595                 list_del_init(&obj_priv->list);
 596         else
 597                 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
 598
 599         obj_priv->last_rendering_seqno = 0;
 600         if (obj_priv->active) {
 601                 obj_priv->active = 0;
 602                 drm_gem_object_unreference(obj);
 603         }
 604         i915_verify_inactive(dev, __FILE__, __LINE__);
 605 }
 606
 607 /**
 608  * Creates a new sequence number, emitting a write of it to the status page
 609  * plus an interrupt, which will trigger i915_user_interrupt_handler.
 610  *
 611  * Must be called with struct_lock held.
 612  *
 613  * Returned sequence numbers are nonzero on success.
 614  */
 615 static uint32_t
 616 i915_add_request(struct drm_device *dev, uint32_t flush_domains)
 617 {
 618         drm_i915_private_t *dev_priv = dev->dev_private;
 619         struct drm_i915_gem_request *request;
 620         uint32_t seqno;
 621         int was_empty;
 622         RING_LOCALS;
 623
 624         request = drm_calloc(1, sizeof(*request), DRM_MEM_DRIVER);
 625         if (request == NULL)
 626                 return 0;
 627
 628         /* Grab the seqno we're going to make this request be, and bump the
 629          * next (skipping 0 so it can be the reserved no-seqno value).
 630          */
 631         seqno = dev_priv->mm.next_gem_seqno;
 632         dev_priv->mm.next_gem_seqno++;
 633         if (dev_priv->mm.next_gem_seqno == 0)
 634                 dev_priv->mm.next_gem_seqno++;
 635
 636         BEGIN_LP_RING(4);
 637         OUT_RING(MI_STORE_DWORD_INDEX);
 638         OUT_RING(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 639         OUT_RING(seqno);
 640
 641         OUT_RING(MI_USER_INTERRUPT);
 642         ADVANCE_LP_RING();
 643
 644         DRM_DEBUG("%d\n", seqno);
 645
 646         request->seqno = seqno;
 647         request->emitted_jiffies = jiffies;
 648         was_empty = list_empty(&dev_priv->mm.request_list);
 649         list_add_tail(&request->list, &dev_priv->mm.request_list);
 650
 651         /* Associate any objects on the flushing list matching the write
 652          * domain we're flushing with our flush.
 653          */
 654         if (flush_domains != 0) {
 655                 struct drm_i915_gem_object *obj_priv, *next;
 656
 657                 list_for_each_entry_safe(obj_priv, next,
 658                                          &dev_priv->mm.flushing_list, list) {
 659                         struct drm_gem_object *obj = obj_priv->obj;
 660
 661                         if ((obj->write_domain & flush_domains) ==
 662                             obj->write_domain) {
 663                                 obj->write_domain = 0;
 664                                 i915_gem_object_move_to_active(obj, seqno);
 665                         }
 666                 }
 667
 668         }
 669
 670         if (was_empty && !dev_priv->mm.suspended)
 671                 schedule_delayed_work(&dev_priv->mm.retire_work, HZ);
 672         return seqno;
 673 }
 674
 675 /**
 676  * Command execution barrier
 677  *
 678  * Ensures that all commands in the ring are finished
 679  * before signalling the CPU
 680  */
 681 static uint32_t
 682 i915_retire_commands(struct drm_device *dev)
 683 {
 684         drm_i915_private_t *dev_priv = dev->dev_private;
 685         uint32_t cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
 686         uint32_t flush_domains = 0;
 687         RING_LOCALS;
 688
 689         /* The sampler always gets flushed on i965 (sigh) */
 690         if (IS_I965G(dev))
 691                 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
 692         BEGIN_LP_RING(2);
 693         OUT_RING(cmd);
 694         OUT_RING(0); /* noop */
 695         ADVANCE_LP_RING();
 696         return flush_domains;
 697 }
 698
 699 /**
 700  * Moves buffers associated only with the given active seqno from the active
 701  * to inactive list, potentially freeing them.
 702  */
 703 static void
 704 i915_gem_retire_request(struct drm_device *dev,
 705                         struct drm_i915_gem_request *request)
 706 {
 707         drm_i915_private_t *dev_priv = dev->dev_private;
 708
 709         /* Move any buffers on the active list that are no longer referenced
 710          * by the ringbuffer to the flushing/inactive lists as appropriate.
 711          */
 712         while (!list_empty(&dev_priv->mm.active_list)) {
 713                 struct drm_gem_object *obj;
 714                 struct drm_i915_gem_object *obj_priv;
 715
 716                 obj_priv = list_first_entry(&dev_priv->mm.active_list,
 717                                             struct drm_i915_gem_object,
 718                                             list);
 719                 obj = obj_priv->obj;
 720
 721                 /* If the seqno being retired doesn't match the oldest in the
 722                  * list, then the oldest in the list must still be newer than
 723                  * this seqno.
 724                  */
 725                 if (obj_priv->last_rendering_seqno != request->seqno)
 726                         return;
 727 #if WATCH_LRU
 728                 DRM_INFO("%s: retire %d moves to inactive list %p\n",
 729                          __func__, request->seqno, obj);
 730 #endif
 731
 732                 if (obj->write_domain != 0)
 733                         i915_gem_object_move_to_flushing(obj);
 734                 else
 735                         i915_gem_object_move_to_inactive(obj);
 736         }
 737 }
 738
 739 /**
 740  * Returns true if seq1 is later than seq2.
 741  */
 742 static int
 743 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
 744 {
 745         return (int32_t)(seq1 - seq2) >= 0;
 746 }
 747
 748 uint32_t
 749 i915_get_gem_seqno(struct drm_device *dev)
 750 {
 751         drm_i915_private_t *dev_priv = dev->dev_private;
 752
 753         return READ_HWSP(dev_priv, I915_GEM_HWS_INDEX);
 754 }
 755
 756 /**
 757  * This function clears the request list as sequence numbers are passed.
 758  */
 759 void
 760 i915_gem_retire_requests(struct drm_device *dev)
 761 {
 762         drm_i915_private_t *dev_priv = dev->dev_private;
 763         uint32_t seqno;
 764
 765         seqno = i915_get_gem_seqno(dev);
 766
 767         while (!list_empty(&dev_priv->mm.request_list)) {
 768                 struct drm_i915_gem_request *request;
 769                 uint32_t retiring_seqno;
 770
 771                 request = list_first_entry(&dev_priv->mm.request_list,
 772                                            struct drm_i915_gem_request,
 773                                            list);
 774                 retiring_seqno = request->seqno;
 775
 776                 if (i915_seqno_passed(seqno, retiring_seqno) ||
 777                     dev_priv->mm.wedged) {
 778                         i915_gem_retire_request(dev, request);
 779
 780                         list_del(&request->list);
 781                         drm_free(request, sizeof(*request), DRM_MEM_DRIVER);
 782                 } else
 783                         break;
 784         }
 785 }
 786
 787 void
 788 i915_gem_retire_work_handler(struct work_struct *work)
 789 {
 790         drm_i915_private_t *dev_priv;
 791         struct drm_device *dev;
 792
 793         dev_priv = container_of(work, drm_i915_private_t,
 794                                 mm.retire_work.work);
 795         dev = dev_priv->dev;
 796
 797         mutex_lock(&dev->struct_mutex);
 798         i915_gem_retire_requests(dev);
 799         if (!dev_priv->mm.suspended &&
 800             !list_empty(&dev_priv->mm.request_list))
 801                 schedule_delayed_work(&dev_priv->mm.retire_work, HZ);
 802         mutex_unlock(&dev->struct_mutex);
 803 }
 804
 805 /**
 806  * Waits for a sequence number to be signaled, and cleans up the
 807  * request and object lists appropriately for that event.
 808  */
 809 static int
 810 i915_wait_request(struct drm_device *dev, uint32_t seqno)
 811 {
 812         drm_i915_private_t *dev_priv = dev->dev_private;
 813         int ret = 0;
 814
 815         BUG_ON(seqno == 0);
 816
 817         if (!i915_seqno_passed(i915_get_gem_seqno(dev), seqno)) {
 818                 dev_priv->mm.waiting_gem_seqno = seqno;
 819                 i915_user_irq_get(dev);
 820                 ret = wait_event_interruptible(dev_priv->irq_queue,
 821                                                i915_seqno_passed(i915_get_gem_seqno(dev),
 822                                                                  seqno) ||
 823                                                dev_priv->mm.wedged);
 824                 i915_user_irq_put(dev);
 825                 dev_priv->mm.waiting_gem_seqno = 0;
 826         }
 827         if (dev_priv->mm.wedged)
 828                 ret = -EIO;
 829
 830         if (ret && ret != -ERESTARTSYS)
 831                 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
 832                           __func__, ret, seqno, i915_get_gem_seqno(dev));
 833
 834         /* Directly dispatch request retiring.  While we have the work queue
 835          * to handle this, the waiter on a request often wants an associated
 836          * buffer to have made it to the inactive list, and we would need
 837          * a separate wait queue to handle that.
 838          */
 839         if (ret == 0)
 840                 i915_gem_retire_requests(dev);
 841
 842         return ret;
 843 }
 844
 845 static void
 846 i915_gem_flush(struct drm_device *dev,
 847                uint32_t invalidate_domains,
 848                uint32_t flush_domains)
 849 {
 850         drm_i915_private_t *dev_priv = dev->dev_private;
 851         uint32_t cmd;
 852         RING_LOCALS;
 853
 854 #if WATCH_EXEC
 855         DRM_INFO("%s: invalidate %08x flush %08x\n", __func__,
 856                   invalidate_domains, flush_domains);
 857 #endif
 858
 859         if (flush_domains & I915_GEM_DOMAIN_CPU)
 860                 drm_agp_chipset_flush(dev);
 861
 862         if ((invalidate_domains | flush_domains) & ~(I915_GEM_DOMAIN_CPU |
 863                                                      I915_GEM_DOMAIN_GTT)) {
 864                 /*
 865                  * read/write caches:
 866                  *
 867                  * I915_GEM_DOMAIN_RENDER is always invalidated, but is
 868                  * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
 869                  * also flushed at 2d versus 3d pipeline switches.
 870                  *
 871                  * read-only caches:
 872                  *
 873                  * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
 874                  * MI_READ_FLUSH is set, and is always flushed on 965.
 875                  *
 876                  * I915_GEM_DOMAIN_COMMAND may not exist?
 877                  *
 878                  * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
 879                  * invalidated when MI_EXE_FLUSH is set.
 880                  *
 881                  * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
 882                  * invalidated with every MI_FLUSH.
 883                  *
 884                  * TLBs:
 885                  *
 886                  * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
 887                  * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
 888                  * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
 889                  * are flushed at any MI_FLUSH.
 890                  */
 891
 892                 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
 893                 if ((invalidate_domains|flush_domains) &
 894                     I915_GEM_DOMAIN_RENDER)
 895                         cmd &= ~MI_NO_WRITE_FLUSH;
 896                 if (!IS_I965G(dev)) {
 897                         /*
 898                          * On the 965, the sampler cache always gets flushed
 899                          * and this bit is reserved.
 900                          */
 901                         if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
 902                                 cmd |= MI_READ_FLUSH;
 903                 }
 904                 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
 905                         cmd |= MI_EXE_FLUSH;
 906
 907 #if WATCH_EXEC
 908                 DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd);
 909 #endif
 910                 BEGIN_LP_RING(2);
 911                 OUT_RING(cmd);
 912                 OUT_RING(0); /* noop */
 913                 ADVANCE_LP_RING();
 914         }
 915 }
 916
 917 /**
 918  * Ensures that all rendering to the object has completed and the object is
 919  * safe to unbind from the GTT or access from the CPU.
 920  */
 921 static int
 922 i915_gem_object_wait_rendering(struct drm_gem_object *obj)
 923 {
 924         struct drm_device *dev = obj->dev;
 925         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 926         int ret;
 927
 928         /* If there are writes queued to the buffer, flush and
 929          * create a new seqno to wait for.
 930          */
 931         if (obj->write_domain & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT)) {
 932                 uint32_t seqno, write_domain = obj->write_domain;
 933 #if WATCH_BUF
 934                 DRM_INFO("%s: flushing object %p from write domain %08x\n",
 935                           __func__, obj, write_domain);
 936 #endif
 937                 i915_gem_flush(dev, 0, write_domain);
 938
 939                 seqno = i915_add_request(dev, write_domain);
 940                 i915_gem_object_move_to_active(obj, seqno);
 941 #if WATCH_LRU
 942                 DRM_INFO("%s: flush moves to exec list %p\n", __func__, obj);
 943 #endif
 944         }
 945
 946         /* If there is rendering queued on the buffer being evicted, wait for
 947          * it.
 948          */
 949         if (obj_priv->active) {
 950 #if WATCH_BUF
 951                 DRM_INFO("%s: object %p wait for seqno %08x\n",
 952                           __func__, obj, obj_priv->last_rendering_seqno);
 953 #endif
 954                 ret = i915_wait_request(dev, obj_priv->last_rendering_seqno);
 955                 if (ret != 0)
 956                         return ret;
 957         }
 958
 959         return 0;
 960 }
 961
 962 /**
 963  * Unbinds an object from the GTT aperture.
 964  */
 965 static int
 966 i915_gem_object_unbind(struct drm_gem_object *obj)
 967 {
 968         struct drm_device *dev = obj->dev;
 969         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 970         int ret = 0;
 971
 972 #if WATCH_BUF
 973         DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj);
 974         DRM_INFO("gtt_space %p\n", obj_priv->gtt_space);
 975 #endif
 976         if (obj_priv->gtt_space == NULL)
 977                 return 0;
 978
 979         if (obj_priv->pin_count != 0) {
 980                 DRM_ERROR("Attempting to unbind pinned buffer\n");
 981                 return -EINVAL;
 982         }
 983
 984         /* Wait for any rendering to complete
 985          */
 986         ret = i915_gem_object_wait_rendering(obj);
 987         if (ret) {
 988                 DRM_ERROR("wait_rendering failed: %d\n", ret);
 989                 return ret;
 990         }
 991
 992         /* Move the object to the CPU domain to ensure that
 993          * any possible CPU writes while it's not in the GTT
 994          * are flushed when we go to remap it. This will
 995          * also ensure that all pending GPU writes are finished
 996          * before we unbind.
 997          */
 998         ret = i915_gem_object_set_domain(obj, I915_GEM_DOMAIN_CPU,
 999                                          I915_GEM_DOMAIN_CPU);
1000         if (ret) {
1001                 DRM_ERROR("set_domain failed: %d\n", ret);
1002                 return ret;
1003         }
1004
1005         if (obj_priv->agp_mem != NULL) {
1006                 drm_unbind_agp(obj_priv->agp_mem);
1007                 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
1008                 obj_priv->agp_mem = NULL;
1009         }
1010
1011         BUG_ON(obj_priv->active);
1012
1013         i915_gem_object_free_page_list(obj);
1014
1015         if (obj_priv->gtt_space) {
1016                 atomic_dec(&dev->gtt_count);
1017                 atomic_sub(obj->size, &dev->gtt_memory);
1018
1019                 drm_mm_put_block(obj_priv->gtt_space);
1020                 obj_priv->gtt_space = NULL;
1021         }
1022
1023         /* Remove ourselves from the LRU list if present. */
1024         if (!list_empty(&obj_priv->list))
1025                 list_del_init(&obj_priv->list);
1026
1027         return 0;
1028 }
1029
1030 static int
1031 i915_gem_evict_something(struct drm_device *dev)
1032 {
1033         drm_i915_private_t *dev_priv = dev->dev_private;
1034         struct drm_gem_object *obj;
1035         struct drm_i915_gem_object *obj_priv;
1036         int ret = 0;
1037
1038         for (;;) {
1039                 /* If there's an inactive buffer available now, grab it
1040                  * and be done.
1041                  */
1042                 if (!list_empty(&dev_priv->mm.inactive_list)) {
1043                         obj_priv = list_first_entry(&dev_priv->mm.inactive_list,
1044                                                     struct drm_i915_gem_object,
1045                                                     list);
1046                         obj = obj_priv->obj;
1047                         BUG_ON(obj_priv->pin_count != 0);
1048 #if WATCH_LRU
1049                         DRM_INFO("%s: evicting %p\n", __func__, obj);
1050 #endif
1051                         BUG_ON(obj_priv->active);
1052
1053                         /* Wait on the rendering and unbind the buffer. */
1054                         ret = i915_gem_object_unbind(obj);
1055                         break;
1056                 }
1057
1058                 /* If we didn't get anything, but the ring is still processing
1059                  * things, wait for one of those things to finish and hopefully
1060                  * leave us a buffer to evict.
1061                  */
1062                 if (!list_empty(&dev_priv->mm.request_list)) {
1063                         struct drm_i915_gem_request *request;
1064
1065                         request = list_first_entry(&dev_priv->mm.request_list,
1066                                                    struct drm_i915_gem_request,
1067                                                    list);
1068
1069                         ret = i915_wait_request(dev, request->seqno);
1070                         if (ret)
1071                                 break;
1072
1073                         /* if waiting caused an object to become inactive,
1074                          * then loop around and wait for it. Otherwise, we
1075                          * assume that waiting freed and unbound something,
1076                          * so there should now be some space in the GTT
1077                          */
1078                         if (!list_empty(&dev_priv->mm.inactive_list))
1079                                 continue;
1080                         break;
1081                 }
1082
1083                 /* If we didn't have anything on the request list but there
1084                  * are buffers awaiting a flush, emit one and try again.
1085                  * When we wait on it, those buffers waiting for that flush
1086                  * will get moved to inactive.
1087                  */
1088                 if (!list_empty(&dev_priv->mm.flushing_list)) {
1089                         obj_priv = list_first_entry(&dev_priv->mm.flushing_list,
1090                                                     struct drm_i915_gem_object,
1091                                                     list);
1092                         obj = obj_priv->obj;
1093
1094                         i915_gem_flush(dev,
1095                                        obj->write_domain,
1096                                        obj->write_domain);
1097                         i915_add_request(dev, obj->write_domain);
1098
1099                         obj = NULL;
1100                         continue;
1101                 }
1102
1103                 DRM_ERROR("inactive empty %d request empty %d "
1104                           "flushing empty %d\n",
1105                           list_empty(&dev_priv->mm.inactive_list),
1106                           list_empty(&dev_priv->mm.request_list),
1107                           list_empty(&dev_priv->mm.flushing_list));
1108                 /* If we didn't do any of the above, there's nothing to be done
1109                  * and we just can't fit it in.
1110                  */
1111                 return -ENOMEM;
1112         }
1113         return ret;
1114 }
1115
1116 static int
1117 i915_gem_object_get_page_list(struct drm_gem_object *obj)
1118 {
1119         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1120         int page_count, i;
1121         struct address_space *mapping;
1122         struct inode *inode;
1123         struct page *page;
1124         int ret;
1125
1126         if (obj_priv->page_list)
1127                 return 0;
1128
1129         /* Get the list of pages out of our struct file.  They'll be pinned
1130          * at this point until we release them.
1131          */
1132         page_count = obj->size / PAGE_SIZE;
1133         BUG_ON(obj_priv->page_list != NULL);
1134         obj_priv->page_list = drm_calloc(page_count, sizeof(struct page *),
1135                                          DRM_MEM_DRIVER);
1136         if (obj_priv->page_list == NULL) {
1137                 DRM_ERROR("Faled to allocate page list\n");
1138                 return -ENOMEM;
1139         }
1140
1141         inode = obj->filp->f_path.dentry->d_inode;
1142         mapping = inode->i_mapping;
1143         for (i = 0; i < page_count; i++) {
1144                 page = read_mapping_page(mapping, i, NULL);
1145                 if (IS_ERR(page)) {
1146                         ret = PTR_ERR(page);
1147                         DRM_ERROR("read_mapping_page failed: %d\n", ret);
1148                         i915_gem_object_free_page_list(obj);
1149                         return ret;
1150                 }
1151                 obj_priv->page_list[i] = page;
1152         }
1153         return 0;
1154 }
1155
1156 /**
1157  * Finds free space in the GTT aperture and binds the object there.
1158  */
1159 static int
1160 i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
1161 {
1162         struct drm_device *dev = obj->dev;
1163         drm_i915_private_t *dev_priv = dev->dev_private;
1164         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1165         struct drm_mm_node *free_space;
1166         int page_count, ret;
1167
1168         if (alignment == 0)
1169                 alignment = PAGE_SIZE;
1170         if (alignment & (PAGE_SIZE - 1)) {
1171                 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
1172                 return -EINVAL;
1173         }
1174
1175  search_free:
1176         free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
1177                                         obj->size, alignment, 0);
1178         if (free_space != NULL) {
1179                 obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
1180                                                        alignment);
1181                 if (obj_priv->gtt_space != NULL) {
1182                         obj_priv->gtt_space->private = obj;
1183                         obj_priv->gtt_offset = obj_priv->gtt_space->start;
1184                 }
1185         }
1186         if (obj_priv->gtt_space == NULL) {
1187                 /* If the gtt is empty and we're still having trouble
1188                  * fitting our object in, we're out of memory.
1189                  */
1190 #if WATCH_LRU
1191                 DRM_INFO("%s: GTT full, evicting something\n", __func__);
1192 #endif
1193                 if (list_empty(&dev_priv->mm.inactive_list) &&
1194                     list_empty(&dev_priv->mm.flushing_list) &&
1195                     list_empty(&dev_priv->mm.active_list)) {
1196                         DRM_ERROR("GTT full, but LRU list empty\n");
1197                         return -ENOMEM;
1198                 }
1199
1200                 ret = i915_gem_evict_something(dev);
1201                 if (ret != 0) {
1202                         DRM_ERROR("Failed to evict a buffer %d\n", ret);
1203                         return ret;
1204                 }
1205                 goto search_free;
1206         }
1207
1208 #if WATCH_BUF
1209         DRM_INFO("Binding object of size %d at 0x%08x\n",
1210                  obj->size, obj_priv->gtt_offset);
1211 #endif
1212         ret = i915_gem_object_get_page_list(obj);
1213         if (ret) {
1214                 drm_mm_put_block(obj_priv->gtt_space);
1215                 obj_priv->gtt_space = NULL;
1216                 return ret;
1217         }
1218
1219         page_count = obj->size / PAGE_SIZE;
1220         /* Create an AGP memory structure pointing at our pages, and bind it
1221          * into the GTT.
1222          */
1223         obj_priv->agp_mem = drm_agp_bind_pages(dev,
1224                                                obj_priv->page_list,
1225                                                page_count,
1226                                                obj_priv->gtt_offset,
1227                                                obj_priv->agp_type);
1228         if (obj_priv->agp_mem == NULL) {
1229                 i915_gem_object_free_page_list(obj);
1230                 drm_mm_put_block(obj_priv->gtt_space);
1231                 obj_priv->gtt_space = NULL;
1232                 return -ENOMEM;
1233         }
1234         atomic_inc(&dev->gtt_count);
1235         atomic_add(obj->size, &dev->gtt_memory);
1236
1237         /* Assert that the object is not currently in any GPU domain. As it
1238          * wasn't in the GTT, there shouldn't be any way it could have been in
1239          * a GPU cache
1240          */
1241         BUG_ON(obj->read_domains & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT));
1242         BUG_ON(obj->write_domain & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT));
1243
1244         return 0;
1245 }
1246
1247 void
1248 i915_gem_clflush_object(struct drm_gem_object *obj)
1249 {
1250         struct drm_i915_gem_object      *obj_priv = obj->driver_private;
1251
1252         /* If we don't have a page list set up, then we're not pinned
1253          * to GPU, and we can ignore the cache flush because it'll happen
1254          * again at bind time.
1255          */
1256         if (obj_priv->page_list == NULL)
1257                 return;
1258
1259         drm_clflush_pages(obj_priv->page_list, obj->size / PAGE_SIZE);
1260 }
1261
1262 /**
1263  * Moves a single object to the GTT read, and possibly write domain.
1264  *
1265  * This function returns when the move is complete, including waiting on
1266  * flushes to occur.
1267  */
1268 static int
1269 i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
1270 {
1271         struct drm_device *dev = obj->dev;
1272         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1273         uint32_t flush_domains;
1274
1275         /* Figure out what GPU domains we need to flush or invalidate for
1276          * moving to GTT.
1277          */
1278         flush_domains = obj->write_domain & I915_GEM_GPU_DOMAINS;
1279
1280         /* Queue the GPU write cache flushing we need. */
1281         if (flush_domains != 0) {
1282                 uint32_t seqno;
1283
1284                 obj->write_domain &= ~I915_GEM_GPU_DOMAINS;
1285                 i915_gem_flush(dev, 0, flush_domains);
1286                 seqno = i915_add_request(dev, flush_domains);
1287                 i915_gem_object_move_to_active(obj, seqno);
1288         }
1289
1290         /* Wait on any GPU rendering and flushing to occur. */
1291         if (obj_priv->active) {
1292                 int ret;
1293
1294                 ret = i915_wait_request(dev, obj_priv->last_rendering_seqno);
1295                 if (ret != 0)
1296                         return ret;
1297         }
1298
1299         /* If we're writing through the GTT domain, then CPU and GPU caches
1300          * will need to be invalidated at next use.
1301          */
1302         if (write)
1303                 obj->read_domains &= ~(I915_GEM_GPU_DOMAINS |
1304                                             I915_GEM_DOMAIN_CPU);
1305
1306         /* Flush the CPU domain if it's dirty. */
1307         if (obj->write_domain & I915_GEM_DOMAIN_CPU) {
1308                 i915_gem_clflush_object(obj);
1309                 drm_agp_chipset_flush(dev);
1310
1311                 obj->write_domain &= ~I915_GEM_DOMAIN_CPU;
1312         }
1313
1314         /* It should now be out of any other write domains, and we can update
1315          * the domain values for our changes.
1316          */
1317         BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
1318         obj->read_domains |= I915_GEM_DOMAIN_GTT;
1319         if (write)
1320                 obj->write_domain = I915_GEM_DOMAIN_GTT;
1321
1322         return 0;
1323 }
1324
1325 /*
1326  * Set the next domain for the specified object. This
1327  * may not actually perform the necessary flushing/invaliding though,
1328  * as that may want to be batched with other set_domain operations
1329  *
1330  * This is (we hope) the only really tricky part of gem. The goal
1331  * is fairly simple -- track which caches hold bits of the object
1332  * and make sure they remain coherent. A few concrete examples may
1333  * help to explain how it works. For shorthand, we use the notation
1334  * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
1335  * a pair of read and write domain masks.
1336  *
1337  * Case 1: the batch buffer
1338  *
1339  *      1. Allocated
1340  *      2. Written by CPU
1341  *      3. Mapped to GTT
1342  *      4. Read by GPU
1343  *      5. Unmapped from GTT
1344  *      6. Freed
1345  *
1346  *      Let's take these a step at a time
1347  *
1348  *      1. Allocated
1349  *              Pages allocated from the kernel may still have
1350  *              cache contents, so we set them to (CPU, CPU) always.
1351  *      2. Written by CPU (using pwrite)
1352  *              The pwrite function calls set_domain (CPU, CPU) and
1353  *              this function does nothing (as nothing changes)
1354  *      3. Mapped by GTT
1355  *              This function asserts that the object is not
1356  *              currently in any GPU-based read or write domains
1357  *      4. Read by GPU
1358  *              i915_gem_execbuffer calls set_domain (COMMAND, 0).
1359  *              As write_domain is zero, this function adds in the
1360  *              current read domains (CPU+COMMAND, 0).
1361  *              flush_domains is set to CPU.
1362  *              invalidate_domains is set to COMMAND
1363  *              clflush is run to get data out of the CPU caches
1364  *              then i915_dev_set_domain calls i915_gem_flush to
1365  *              emit an MI_FLUSH and drm_agp_chipset_flush
1366  *      5. Unmapped from GTT
1367  *              i915_gem_object_unbind calls set_domain (CPU, CPU)
1368  *              flush_domains and invalidate_domains end up both zero
1369  *              so no flushing/invalidating happens
1370  *      6. Freed
1371  *              yay, done
1372  *
1373  * Case 2: The shared render buffer
1374  *
1375  *      1. Allocated
1376  *      2. Mapped to GTT
1377  *      3. Read/written by GPU
1378  *      4. set_domain to (CPU,CPU)
1379  *      5. Read/written by CPU
1380  *      6. Read/written by GPU
1381  *
1382  *      1. Allocated
1383  *              Same as last example, (CPU, CPU)
1384  *      2. Mapped to GTT
1385  *              Nothing changes (assertions find that it is not in the GPU)
1386  *      3. Read/written by GPU
1387  *              execbuffer calls set_domain (RENDER, RENDER)
1388  *              flush_domains gets CPU
1389  *              invalidate_domains gets GPU
1390  *              clflush (obj)
1391  *              MI_FLUSH and drm_agp_chipset_flush
1392  *      4. set_domain (CPU, CPU)
1393  *              flush_domains gets GPU
1394  *              invalidate_domains gets CPU
1395  *              wait_rendering (obj) to make sure all drawing is complete.
1396  *              This will include an MI_FLUSH to get the data from GPU
1397  *              to memory
1398  *              clflush (obj) to invalidate the CPU cache
1399  *              Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
1400  *      5. Read/written by CPU
1401  *              cache lines are loaded and dirtied
1402  *      6. Read written by GPU
1403  *              Same as last GPU access
1404  *
1405  * Case 3: The constant buffer
1406  *
1407  *      1. Allocated
1408  *      2. Written by CPU
1409  *      3. Read by GPU
1410  *      4. Updated (written) by CPU again
1411  *      5. Read by GPU
1412  *
1413  *      1. Allocated
1414  *              (CPU, CPU)
1415  *      2. Written by CPU
1416  *              (CPU, CPU)
1417  *      3. Read by GPU
1418  *              (CPU+RENDER, 0)
1419  *              flush_domains = CPU
1420  *              invalidate_domains = RENDER
1421  *              clflush (obj)
1422  *              MI_FLUSH
1423  *              drm_agp_chipset_flush
1424  *      4. Updated (written) by CPU again
1425  *              (CPU, CPU)
1426  *              flush_domains = 0 (no previous write domain)
1427  *              invalidate_domains = 0 (no new read domains)
1428  *      5. Read by GPU
1429  *              (CPU+RENDER, 0)
1430  *              flush_domains = CPU
1431  *              invalidate_domains = RENDER
1432  *              clflush (obj)
1433  *              MI_FLUSH
1434  *              drm_agp_chipset_flush
1435  */
1436 static int
1437 i915_gem_object_set_domain(struct drm_gem_object *obj,
1438                             uint32_t read_domains,
1439                             uint32_t write_domain)
1440 {
1441         struct drm_device               *dev = obj->dev;
1442         struct drm_i915_gem_object      *obj_priv = obj->driver_private;
1443         uint32_t                        invalidate_domains = 0;
1444         uint32_t                        flush_domains = 0;
1445         int                             ret;
1446
1447 #if WATCH_BUF
1448         DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
1449                  __func__, obj,
1450                  obj->read_domains, read_domains,
1451                  obj->write_domain, write_domain);
1452 #endif
1453         /*
1454          * If the object isn't moving to a new write domain,
1455          * let the object stay in multiple read domains
1456          */
1457         if (write_domain == 0)
1458                 read_domains |= obj->read_domains;
1459         else
1460                 obj_priv->dirty = 1;
1461
1462         /*
1463          * Flush the current write domain if
1464          * the new read domains don't match. Invalidate
1465          * any read domains which differ from the old
1466          * write domain
1467          */
1468         if (obj->write_domain && obj->write_domain != read_domains) {
1469                 flush_domains |= obj->write_domain;
1470                 invalidate_domains |= read_domains & ~obj->write_domain;
1471         }
1472         /*
1473          * Invalidate any read caches which may have
1474          * stale data. That is, any new read domains.
1475          */
1476         invalidate_domains |= read_domains & ~obj->read_domains;
1477         if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) {
1478 #if WATCH_BUF
1479                 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
1480                          __func__, flush_domains, invalidate_domains);
1481 #endif
1482                 /*
1483                  * If we're invaliding the CPU cache and flushing a GPU cache,
1484                  * then pause for rendering so that the GPU caches will be
1485                  * flushed before the cpu cache is invalidated
1486                  */
1487                 if ((invalidate_domains & I915_GEM_DOMAIN_CPU) &&
1488                     (flush_domains & ~(I915_GEM_DOMAIN_CPU |
1489                                        I915_GEM_DOMAIN_GTT))) {
1490                         ret = i915_gem_object_wait_rendering(obj);
1491                         if (ret)
1492                                 return ret;
1493                 }
1494                 i915_gem_clflush_object(obj);
1495         }
1496
1497         if ((write_domain | flush_domains) != 0)
1498                 obj->write_domain = write_domain;
1499
1500         /* If we're invalidating the CPU domain, clear the per-page CPU
1501          * domain list as well.
1502          */
1503         if (obj_priv->page_cpu_valid != NULL &&
1504             (write_domain != 0 ||
1505              read_domains & I915_GEM_DOMAIN_CPU)) {
1506                 drm_free(obj_priv->page_cpu_valid, obj->size / PAGE_SIZE,
1507                          DRM_MEM_DRIVER);
1508                 obj_priv->page_cpu_valid = NULL;
1509         }
1510         obj->read_domains = read_domains;
1511
1512         dev->invalidate_domains |= invalidate_domains;
1513         dev->flush_domains |= flush_domains;
1514 #if WATCH_BUF
1515         DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
1516                  __func__,
1517                  obj->read_domains, obj->write_domain,
1518                  dev->invalidate_domains, dev->flush_domains);
1519 #endif
1520         return 0;
1521 }
1522
1523 /**
1524  * Set the read/write domain on a range of the object.
1525  *
1526  * Currently only implemented for CPU reads, otherwise drops to normal
1527  * i915_gem_object_set_domain().
1528  */
1529 static int
1530 i915_gem_object_set_domain_range(struct drm_gem_object *obj,
1531                                  uint64_t offset,
1532                                  uint64_t size,
1533                                  uint32_t read_domains,
1534                                  uint32_t write_domain)
1535 {
1536         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1537         int ret, i;
1538
1539         if (obj->read_domains & I915_GEM_DOMAIN_CPU)
1540                 return 0;
1541
1542         if (read_domains != I915_GEM_DOMAIN_CPU ||
1543             write_domain != 0)
1544                 return i915_gem_object_set_domain(obj,
1545                                                   read_domains, write_domain);
1546
1547         /* Wait on any GPU rendering to the object to be flushed. */
1548         ret = i915_gem_object_wait_rendering(obj);
1549         if (ret)
1550                 return ret;
1551
1552         if (obj_priv->page_cpu_valid == NULL) {
1553                 obj_priv->page_cpu_valid = drm_calloc(1, obj->size / PAGE_SIZE,
1554                                                       DRM_MEM_DRIVER);
1555         }
1556
1557         /* Flush the cache on any pages that are still invalid from the CPU's
1558          * perspective.
1559          */
1560         for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE; i++) {
1561                 if (obj_priv->page_cpu_valid[i])
1562                         continue;
1563
1564                 drm_clflush_pages(obj_priv->page_list + i, 1);
1565
1566                 obj_priv->page_cpu_valid[i] = 1;
1567         }
1568
1569         return 0;
1570 }
1571
1572 /**
1573  * Once all of the objects have been set in the proper domain,
1574  * perform the necessary flush and invalidate operations.
1575  *
1576  * Returns the write domains flushed, for use in flush tracking.
1577  */
1578 static uint32_t
1579 i915_gem_dev_set_domain(struct drm_device *dev)
1580 {
1581         uint32_t flush_domains = dev->flush_domains;
1582
1583         /*
1584          * Now that all the buffers are synced to the proper domains,
1585          * flush and invalidate the collected domains
1586          */
1587         if (dev->invalidate_domains | dev->flush_domains) {
1588 #if WATCH_EXEC
1589                 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
1590                           __func__,
1591                          dev->invalidate_domains,
1592                          dev->flush_domains);
1593 #endif
1594                 i915_gem_flush(dev,
1595                                dev->invalidate_domains,
1596                                dev->flush_domains);
1597                 dev->invalidate_domains = 0;
1598                 dev->flush_domains = 0;
1599         }
1600
1601         return flush_domains;
1602 }
1603
1604 /**
1605  * Pin an object to the GTT and evaluate the relocations landing in it.
1606  */
1607 static int
1608 i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
1609                                  struct drm_file *file_priv,
1610                                  struct drm_i915_gem_exec_object *entry)
1611 {
1612         struct drm_device *dev = obj->dev;
1613         drm_i915_private_t *dev_priv = dev->dev_private;
1614         struct drm_i915_gem_relocation_entry reloc;
1615         struct drm_i915_gem_relocation_entry __user *relocs;
1616         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1617         int i, ret;
1618         void __iomem *reloc_page;
1619
1620         /* Choose the GTT offset for our buffer and put it there. */
1621         ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
1622         if (ret)
1623                 return ret;
1624
1625         entry->offset = obj_priv->gtt_offset;
1626
1627         relocs = (struct drm_i915_gem_relocation_entry __user *)
1628                  (uintptr_t) entry->relocs_ptr;
1629         /* Apply the relocations, using the GTT aperture to avoid cache
1630          * flushing requirements.
1631          */
1632         for (i = 0; i < entry->relocation_count; i++) {
1633                 struct drm_gem_object *target_obj;
1634                 struct drm_i915_gem_object *target_obj_priv;
1635                 uint32_t reloc_val, reloc_offset;
1636                 uint32_t __iomem *reloc_entry;
1637
1638                 ret = copy_from_user(&reloc, relocs + i, sizeof(reloc));
1639                 if (ret != 0) {
1640                         i915_gem_object_unpin(obj);
1641                         return ret;
1642                 }
1643
1644                 target_obj = drm_gem_object_lookup(obj->dev, file_priv,
1645                                                    reloc.target_handle);
1646                 if (target_obj == NULL) {
1647                         i915_gem_object_unpin(obj);
1648                         return -EBADF;
1649                 }
1650                 target_obj_priv = target_obj->driver_private;
1651
1652                 /* The target buffer should have appeared before us in the
1653                  * exec_object list, so it should have a GTT space bound by now.
1654                  */
1655                 if (target_obj_priv->gtt_space == NULL) {
1656                         DRM_ERROR("No GTT space found for object %d\n",
1657                                   reloc.target_handle);
1658                         drm_gem_object_unreference(target_obj);
1659                         i915_gem_object_unpin(obj);
1660                         return -EINVAL;
1661                 }
1662
1663                 if (reloc.offset > obj->size - 4) {
1664                         DRM_ERROR("Relocation beyond object bounds: "
1665                                   "obj %p target %d offset %d size %d.\n",
1666                                   obj, reloc.target_handle,
1667                                   (int) reloc.offset, (int) obj->size);
1668                         drm_gem_object_unreference(target_obj);
1669                         i915_gem_object_unpin(obj);
1670                         return -EINVAL;
1671                 }
1672                 if (reloc.offset & 3) {
1673                         DRM_ERROR("Relocation not 4-byte aligned: "
1674                                   "obj %p target %d offset %d.\n",
1675                                   obj, reloc.target_handle,
1676                                   (int) reloc.offset);
1677                         drm_gem_object_unreference(target_obj);
1678                         i915_gem_object_unpin(obj);
1679                         return -EINVAL;
1680                 }
1681
1682                 if (reloc.write_domain && target_obj->pending_write_domain &&
1683                     reloc.write_domain != target_obj->pending_write_domain) {
1684                         DRM_ERROR("Write domain conflict: "
1685                                   "obj %p target %d offset %d "
1686                                   "new %08x old %08x\n",
1687                                   obj, reloc.target_handle,
1688                                   (int) reloc.offset,
1689                                   reloc.write_domain,
1690                                   target_obj->pending_write_domain);
1691                         drm_gem_object_unreference(target_obj);
1692                         i915_gem_object_unpin(obj);
1693                         return -EINVAL;
1694                 }
1695
1696 #if WATCH_RELOC
1697                 DRM_INFO("%s: obj %p offset %08x target %d "
1698                          "read %08x write %08x gtt %08x "
1699                          "presumed %08x delta %08x\n",
1700                          __func__,
1701                          obj,
1702                          (int) reloc.offset,
1703                          (int) reloc.target_handle,
1704                          (int) reloc.read_domains,
1705                          (int) reloc.write_domain,
1706                          (int) target_obj_priv->gtt_offset,
1707                          (int) reloc.presumed_offset,
1708                          reloc.delta);
1709 #endif
1710
1711                 target_obj->pending_read_domains |= reloc.read_domains;
1712                 target_obj->pending_write_domain |= reloc.write_domain;
1713
1714                 /* If the relocation already has the right value in it, no
1715                  * more work needs to be done.
1716                  */
1717                 if (target_obj_priv->gtt_offset == reloc.presumed_offset) {
1718                         drm_gem_object_unreference(target_obj);
1719                         continue;
1720                 }
1721
1722                 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
1723                 if (ret != 0) {
1724                         drm_gem_object_unreference(target_obj);
1725                         i915_gem_object_unpin(obj);
1726                         return -EINVAL;
1727                 }
1728
1729                 /* Map the page containing the relocation we're going to
1730                  * perform.
1731                  */
1732                 reloc_offset = obj_priv->gtt_offset + reloc.offset;
1733                 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
1734                                                       (reloc_offset &
1735                                                        ~(PAGE_SIZE - 1)));
1736                 reloc_entry = (uint32_t __iomem *)(reloc_page +
1737                                                    (reloc_offset & (PAGE_SIZE - 1)));
1738                 reloc_val = target_obj_priv->gtt_offset + reloc.delta;
1739
1740 #if WATCH_BUF
1741                 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
1742                           obj, (unsigned int) reloc.offset,
1743                           readl(reloc_entry), reloc_val);
1744 #endif
1745                 writel(reloc_val, reloc_entry);
1746                 io_mapping_unmap_atomic(reloc_page);
1747
1748                 /* Write the updated presumed offset for this entry back out
1749                  * to the user.
1750                  */
1751                 reloc.presumed_offset = target_obj_priv->gtt_offset;
1752                 ret = copy_to_user(relocs + i, &reloc, sizeof(reloc));
1753                 if (ret != 0) {
1754                         drm_gem_object_unreference(target_obj);
1755                         i915_gem_object_unpin(obj);
1756                         return ret;
1757                 }
1758
1759                 drm_gem_object_unreference(target_obj);
1760         }
1761
1762 #if WATCH_BUF
1763         if (0)
1764                 i915_gem_dump_object(obj, 128, __func__, ~0);
1765 #endif
1766         return 0;
1767 }
1768
1769 /** Dispatch a batchbuffer to the ring
1770  */
1771 static int
1772 i915_dispatch_gem_execbuffer(struct drm_device *dev,
1773                               struct drm_i915_gem_execbuffer *exec,
1774                               uint64_t exec_offset)
1775 {
1776         drm_i915_private_t *dev_priv = dev->dev_private;
1777         struct drm_clip_rect __user *boxes = (struct drm_clip_rect __user *)
1778                                              (uintptr_t) exec->cliprects_ptr;
1779         int nbox = exec->num_cliprects;
1780         int i = 0, count;
1781         uint32_t        exec_start, exec_len;
1782         RING_LOCALS;
1783
1784         exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
1785         exec_len = (uint32_t) exec->batch_len;
1786
1787         if ((exec_start | exec_len) & 0x7) {
1788                 DRM_ERROR("alignment\n");
1789                 return -EINVAL;
1790         }
1791
1792         if (!exec_start)
1793                 return -EINVAL;
1794
1795         count = nbox ? nbox : 1;
1796
1797         for (i = 0; i < count; i++) {
1798                 if (i < nbox) {
1799                         int ret = i915_emit_box(dev, boxes, i,
1800                                                 exec->DR1, exec->DR4);
1801                         if (ret)
1802                                 return ret;
1803                 }
1804
1805                 if (IS_I830(dev) || IS_845G(dev)) {
1806                         BEGIN_LP_RING(4);
1807                         OUT_RING(MI_BATCH_BUFFER);
1808                         OUT_RING(exec_start | MI_BATCH_NON_SECURE);
1809                         OUT_RING(exec_start + exec_len - 4);
1810                         OUT_RING(0);
1811                         ADVANCE_LP_RING();
1812                 } else {
1813                         BEGIN_LP_RING(2);
1814                         if (IS_I965G(dev)) {
1815                                 OUT_RING(MI_BATCH_BUFFER_START |
1816                                          (2 << 6) |
1817                                          MI_BATCH_NON_SECURE_I965);
1818                                 OUT_RING(exec_start);
1819                         } else {
1820                                 OUT_RING(MI_BATCH_BUFFER_START |
1821                                          (2 << 6));
1822                                 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
1823                         }
1824                         ADVANCE_LP_RING();
1825                 }
1826         }
1827
1828         /* XXX breadcrumb */
1829         return 0;
1830 }
1831
1832 /* Throttle our rendering by waiting until the ring has completed our requests
1833  * emitted over 20 msec ago.
1834  *
1835  * This should get us reasonable parallelism between CPU and GPU but also
1836  * relatively low latency when blocking on a particular request to finish.
1837  */
1838 static int
1839 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
1840 {
1841         struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
1842         int ret = 0;
1843         uint32_t seqno;
1844
1845         mutex_lock(&dev->struct_mutex);
1846         seqno = i915_file_priv->mm.last_gem_throttle_seqno;
1847         i915_file_priv->mm.last_gem_throttle_seqno =
1848                 i915_file_priv->mm.last_gem_seqno;
1849         if (seqno)
1850                 ret = i915_wait_request(dev, seqno);
1851         mutex_unlock(&dev->struct_mutex);
1852         return ret;
1853 }
1854
1855 int
1856 i915_gem_execbuffer(struct drm_device *dev, void *data,
1857                     struct drm_file *file_priv)
1858 {
1859         drm_i915_private_t *dev_priv = dev->dev_private;
1860         struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
1861         struct drm_i915_gem_execbuffer *args = data;
1862         struct drm_i915_gem_exec_object *exec_list = NULL;
1863         struct drm_gem_object **object_list = NULL;
1864         struct drm_gem_object *batch_obj;
1865         int ret, i, pinned = 0;
1866         uint64_t exec_offset;
1867         uint32_t seqno, flush_domains;
1868
1869 #if WATCH_EXEC
1870         DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
1871                   (int) args->buffers_ptr, args->buffer_count, args->batch_len);
1872 #endif
1873
1874         if (args->buffer_count < 1) {
1875                 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
1876                 return -EINVAL;
1877         }
1878         /* Copy in the exec list from userland */
1879         exec_list = drm_calloc(sizeof(*exec_list), args->buffer_count,
1880                                DRM_MEM_DRIVER);
1881         object_list = drm_calloc(sizeof(*object_list), args->buffer_count,
1882                                  DRM_MEM_DRIVER);
1883         if (exec_list == NULL || object_list == NULL) {
1884                 DRM_ERROR("Failed to allocate exec or object list "
1885                           "for %d buffers\n",
1886                           args->buffer_count);
1887                 ret = -ENOMEM;
1888                 goto pre_mutex_err;
1889         }
1890         ret = copy_from_user(exec_list,
1891                              (struct drm_i915_relocation_entry __user *)
1892                              (uintptr_t) args->buffers_ptr,
1893                              sizeof(*exec_list) * args->buffer_count);
1894         if (ret != 0) {
1895                 DRM_ERROR("copy %d exec entries failed %d\n",
1896                           args->buffer_count, ret);
1897                 goto pre_mutex_err;
1898         }
1899
1900         mutex_lock(&dev->struct_mutex);
1901
1902         i915_verify_inactive(dev, __FILE__, __LINE__);
1903
1904         if (dev_priv->mm.wedged) {
1905                 DRM_ERROR("Execbuf while wedged\n");
1906                 mutex_unlock(&dev->struct_mutex);
1907                 return -EIO;
1908         }
1909
1910         if (dev_priv->mm.suspended) {
1911                 DRM_ERROR("Execbuf while VT-switched.\n");
1912                 mutex_unlock(&dev->struct_mutex);
1913                 return -EBUSY;
1914         }
1915
1916         /* Zero the gloabl flush/invalidate flags. These
1917          * will be modified as each object is bound to the
1918          * gtt
1919          */
1920         dev->invalidate_domains = 0;
1921         dev->flush_domains = 0;
1922
1923         /* Look up object handles and perform the relocations */
1924         for (i = 0; i < args->buffer_count; i++) {
1925                 object_list[i] = drm_gem_object_lookup(dev, file_priv,
1926                                                        exec_list[i].handle);
1927                 if (object_list[i] == NULL) {
1928                         DRM_ERROR("Invalid object handle %d at index %d\n",
1929                                    exec_list[i].handle, i);
1930                         ret = -EBADF;
1931                         goto err;
1932                 }
1933
1934                 object_list[i]->pending_read_domains = 0;
1935                 object_list[i]->pending_write_domain = 0;
1936                 ret = i915_gem_object_pin_and_relocate(object_list[i],
1937                                                        file_priv,
1938                                                        &exec_list[i]);
1939                 if (ret) {
1940                         DRM_ERROR("object bind and relocate failed %d\n", ret);
1941                         goto err;
1942                 }
1943                 pinned = i + 1;
1944         }
1945
1946         /* Set the pending read domains for the batch buffer to COMMAND */
1947         batch_obj = object_list[args->buffer_count-1];
1948         batch_obj->pending_read_domains = I915_GEM_DOMAIN_COMMAND;
1949         batch_obj->pending_write_domain = 0;
1950
1951         i915_verify_inactive(dev, __FILE__, __LINE__);
1952
1953         for (i = 0; i < args->buffer_count; i++) {
1954                 struct drm_gem_object *obj = object_list[i];
1955
1956                 /* make sure all previous memory operations have passed */
1957                 ret = i915_gem_object_set_domain(obj,
1958                                                  obj->pending_read_domains,
1959                                                  obj->pending_write_domain);
1960                 if (ret) {
1961                         /* As we've partially updated domains on our buffers,
1962                          * we have to emit the flush we've accumulated
1963                          * before exiting, or we'll have broken the
1964                          * active/flushing/inactive invariants.
1965                          *
1966                          * We'll potentially have some things marked as
1967                          * being in write domains that they actually aren't,
1968                          * but that should be merely a minor performance loss.
1969                          */
1970                         flush_domains = i915_gem_dev_set_domain(dev);
1971                         (void)i915_add_request(dev, flush_domains);
1972                         goto err;
1973                 }
1974         }
1975
1976         i915_verify_inactive(dev, __FILE__, __LINE__);
1977
1978         /* Flush/invalidate caches and chipset buffer */
1979         flush_domains = i915_gem_dev_set_domain(dev);
1980
1981         i915_verify_inactive(dev, __FILE__, __LINE__);
1982
1983 #if WATCH_COHERENCY
1984         for (i = 0; i < args->buffer_count; i++) {
1985                 i915_gem_object_check_coherency(object_list[i],
1986                                                 exec_list[i].handle);
1987         }
1988 #endif
1989
1990         exec_offset = exec_list[args->buffer_count - 1].offset;
1991
1992 #if WATCH_EXEC
1993         i915_gem_dump_object(object_list[args->buffer_count - 1],
1994                               args->batch_len,
1995                               __func__,
1996                               ~0);
1997 #endif
1998
1999         (void)i915_add_request(dev, flush_domains);
2000
2001         /* Exec the batchbuffer */
2002         ret = i915_dispatch_gem_execbuffer(dev, args, exec_offset);
2003         if (ret) {
2004                 DRM_ERROR("dispatch failed %d\n", ret);
2005                 goto err;
2006         }
2007
2008         /*
2009          * Ensure that the commands in the batch buffer are
2010          * finished before the interrupt fires
2011          */
2012         flush_domains = i915_retire_commands(dev);
2013
2014         i915_verify_inactive(dev, __FILE__, __LINE__);
2015
2016         /*
2017          * Get a seqno representing the execution of the current buffer,
2018          * which we can wait on.  We would like to mitigate these interrupts,
2019          * likely by only creating seqnos occasionally (so that we have
2020          * *some* interrupts representing completion of buffers that we can
2021          * wait on when trying to clear up gtt space).
2022          */
2023         seqno = i915_add_request(dev, flush_domains);
2024         BUG_ON(seqno == 0);
2025         i915_file_priv->mm.last_gem_seqno = seqno;
2026         for (i = 0; i < args->buffer_count; i++) {
2027                 struct drm_gem_object *obj = object_list[i];
2028
2029                 i915_gem_object_move_to_active(obj, seqno);
2030 #if WATCH_LRU
2031                 DRM_INFO("%s: move to exec list %p\n", __func__, obj);
2032 #endif
2033         }
2034 #if WATCH_LRU
2035         i915_dump_lru(dev, __func__);
2036 #endif
2037
2038         i915_verify_inactive(dev, __FILE__, __LINE__);
2039
2040         /* Copy the new buffer offsets back to the user's exec list. */
2041         ret = copy_to_user((struct drm_i915_relocation_entry __user *)
2042                            (uintptr_t) args->buffers_ptr,
2043                            exec_list,
2044                            sizeof(*exec_list) * args->buffer_count);
2045         if (ret)
2046                 DRM_ERROR("failed to copy %d exec entries "
2047                           "back to user (%d)\n",
2048                            args->buffer_count, ret);
2049 err:
2050         if (object_list != NULL) {
2051                 for (i = 0; i < pinned; i++)
2052                         i915_gem_object_unpin(object_list[i]);
2053
2054                 for (i = 0; i < args->buffer_count; i++)
2055                         drm_gem_object_unreference(object_list[i]);
2056         }
2057         mutex_unlock(&dev->struct_mutex);
2058
2059 pre_mutex_err:
2060         drm_free(object_list, sizeof(*object_list) * args->buffer_count,
2061                  DRM_MEM_DRIVER);
2062         drm_free(exec_list, sizeof(*exec_list) * args->buffer_count,
2063                  DRM_MEM_DRIVER);
2064
2065         return ret;
2066 }
2067
2068 int
2069 i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
2070 {
2071         struct drm_device *dev = obj->dev;
2072         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2073         int ret;
2074
2075         i915_verify_inactive(dev, __FILE__, __LINE__);
2076         if (obj_priv->gtt_space == NULL) {
2077                 ret = i915_gem_object_bind_to_gtt(obj, alignment);
2078                 if (ret != 0) {
2079                         DRM_ERROR("Failure to bind: %d", ret);
2080                         return ret;
2081                 }
2082         }
2083         obj_priv->pin_count++;
2084
2085         /* If the object is not active and not pending a flush,
2086          * remove it from the inactive list
2087          */
2088         if (obj_priv->pin_count == 1) {
2089                 atomic_inc(&dev->pin_count);
2090                 atomic_add(obj->size, &dev->pin_memory);
2091                 if (!obj_priv->active &&
2092                     (obj->write_domain & ~(I915_GEM_DOMAIN_CPU |
2093                                            I915_GEM_DOMAIN_GTT)) == 0 &&
2094                     !list_empty(&obj_priv->list))
2095                         list_del_init(&obj_priv->list);
2096         }
2097         i915_verify_inactive(dev, __FILE__, __LINE__);
2098
2099         return 0;
2100 }
2101
2102 void
2103 i915_gem_object_unpin(struct drm_gem_object *obj)
2104 {
2105         struct drm_device *dev = obj->dev;
2106         drm_i915_private_t *dev_priv = dev->dev_private;
2107         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2108
2109         i915_verify_inactive(dev, __FILE__, __LINE__);
2110         obj_priv->pin_count--;
2111         BUG_ON(obj_priv->pin_count < 0);
2112         BUG_ON(obj_priv->gtt_space == NULL);
2113
2114         /* If the object is no longer pinned, and is
2115          * neither active nor being flushed, then stick it on
2116          * the inactive list
2117          */
2118         if (obj_priv->pin_count == 0) {
2119                 if (!obj_priv->active &&
2120                     (obj->write_domain & ~(I915_GEM_DOMAIN_CPU |
2121                                            I915_GEM_DOMAIN_GTT)) == 0)
2122                         list_move_tail(&obj_priv->list,
2123                                        &dev_priv->mm.inactive_list);
2124                 atomic_dec(&dev->pin_count);
2125                 atomic_sub(obj->size, &dev->pin_memory);
2126         }
2127         i915_verify_inactive(dev, __FILE__, __LINE__);
2128 }
2129
2130 int
2131 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
2132                    struct drm_file *file_priv)
2133 {
2134         struct drm_i915_gem_pin *args = data;
2135         struct drm_gem_object *obj;
2136         struct drm_i915_gem_object *obj_priv;
2137         int ret;
2138
2139         mutex_lock(&dev->struct_mutex);
2140
2141         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
2142         if (obj == NULL) {
2143                 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
2144                           args->handle);
2145                 mutex_unlock(&dev->struct_mutex);
2146                 return -EBADF;
2147         }
2148         obj_priv = obj->driver_private;
2149
2150         ret = i915_gem_object_pin(obj, args->alignment);
2151         if (ret != 0) {
2152                 drm_gem_object_unreference(obj);
2153                 mutex_unlock(&dev->struct_mutex);
2154                 return ret;
2155         }
2156
2157         /* XXX - flush the CPU caches for pinned objects
2158          * as the X server doesn't manage domains yet
2159          */
2160         if (obj->write_domain & I915_GEM_DOMAIN_CPU) {
2161                 i915_gem_clflush_object(obj);
2162                 drm_agp_chipset_flush(dev);
2163                 obj->write_domain = 0;
2164         }
2165         args->offset = obj_priv->gtt_offset;
2166         drm_gem_object_unreference(obj);
2167         mutex_unlock(&dev->struct_mutex);
2168
2169         return 0;
2170 }
2171
2172 int
2173 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
2174                      struct drm_file *file_priv)
2175 {
2176         struct drm_i915_gem_pin *args = data;
2177         struct drm_gem_object *obj;
2178
2179         mutex_lock(&dev->struct_mutex);
2180
2181         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
2182         if (obj == NULL) {
2183                 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
2184                           args->handle);
2185                 mutex_unlock(&dev->struct_mutex);
2186                 return -EBADF;
2187         }
2188
2189         i915_gem_object_unpin(obj);
2190
2191         drm_gem_object_unreference(obj);
2192         mutex_unlock(&dev->struct_mutex);
2193         return 0;
2194 }
2195
2196 int
2197 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2198                     struct drm_file *file_priv)
2199 {
2200         struct drm_i915_gem_busy *args = data;
2201         struct drm_gem_object *obj;
2202         struct drm_i915_gem_object *obj_priv;
2203
2204         mutex_lock(&dev->struct_mutex);
2205         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
2206         if (obj == NULL) {
2207                 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
2208                           args->handle);
2209                 mutex_unlock(&dev->struct_mutex);
2210                 return -EBADF;
2211         }
2212
2213         obj_priv = obj->driver_private;
2214         args->busy = obj_priv->active;
2215
2216         drm_gem_object_unreference(obj);
2217         mutex_unlock(&dev->struct_mutex);
2218         return 0;
2219 }
2220
2221 int
2222 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2223                         struct drm_file *file_priv)
2224 {
2225     return i915_gem_ring_throttle(dev, file_priv);
2226 }
2227
2228 int i915_gem_init_object(struct drm_gem_object *obj)
2229 {
2230         struct drm_i915_gem_object *obj_priv;
2231
2232         obj_priv = drm_calloc(1, sizeof(*obj_priv), DRM_MEM_DRIVER);
2233         if (obj_priv == NULL)
2234                 return -ENOMEM;
2235
2236         /*
2237          * We've just allocated pages from the kernel,
2238          * so they've just been written by the CPU with
2239          * zeros. They'll need to be clflushed before we
2240          * use them with the GPU.
2241          */
2242         obj->write_domain = I915_GEM_DOMAIN_CPU;
2243         obj->read_domains = I915_GEM_DOMAIN_CPU;
2244
2245         obj_priv->agp_type = AGP_USER_MEMORY;
2246
2247         obj->driver_private = obj_priv;
2248         obj_priv->obj = obj;
2249         INIT_LIST_HEAD(&obj_priv->list);
2250         return 0;
2251 }
2252
2253 void i915_gem_free_object(struct drm_gem_object *obj)
2254 {
2255         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2256
2257         while (obj_priv->pin_count > 0)
2258                 i915_gem_object_unpin(obj);
2259
2260         i915_gem_object_unbind(obj);
2261
2262         drm_free(obj_priv->page_cpu_valid, 1, DRM_MEM_DRIVER);
2263         drm_free(obj->driver_private, 1, DRM_MEM_DRIVER);
2264 }
2265
2266 static int
2267 i915_gem_set_domain(struct drm_gem_object *obj,
2268                     struct drm_file *file_priv,
2269                     uint32_t read_domains,
2270                     uint32_t write_domain)
2271 {
2272         struct drm_device *dev = obj->dev;
2273         int ret;
2274         uint32_t flush_domains;
2275
2276         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
2277
2278         ret = i915_gem_object_set_domain(obj, read_domains, write_domain);
2279         if (ret)
2280                 return ret;
2281         flush_domains = i915_gem_dev_set_domain(obj->dev);
2282
2283         if (flush_domains & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT))
2284                 (void) i915_add_request(dev, flush_domains);
2285
2286         return 0;
2287 }
2288
2289 /** Unbinds all objects that are on the given buffer list. */
2290 static int
2291 i915_gem_evict_from_list(struct drm_device *dev, struct list_head *head)
2292 {
2293         struct drm_gem_object *obj;
2294         struct drm_i915_gem_object *obj_priv;
2295         int ret;
2296
2297         while (!list_empty(head)) {
2298                 obj_priv = list_first_entry(head,
2299                                             struct drm_i915_gem_object,
2300                                             list);
2301                 obj = obj_priv->obj;
2302
2303                 if (obj_priv->pin_count != 0) {
2304                         DRM_ERROR("Pinned object in unbind list\n");
2305                         mutex_unlock(&dev->struct_mutex);
2306                         return -EINVAL;
2307                 }
2308
2309                 ret = i915_gem_object_unbind(obj);
2310                 if (ret != 0) {
2311                         DRM_ERROR("Error unbinding object in LeaveVT: %d\n",
2312                                   ret);
2313                         mutex_unlock(&dev->struct_mutex);
2314                         return ret;
2315                 }
2316         }
2317
2318
2319         return 0;
2320 }
2321
2322 static int
2323 i915_gem_idle(struct drm_device *dev)
2324 {
2325         drm_i915_private_t *dev_priv = dev->dev_private;
2326         uint32_t seqno, cur_seqno, last_seqno;
2327         int stuck, ret;
2328
2329         mutex_lock(&dev->struct_mutex);
2330
2331         if (dev_priv->mm.suspended || dev_priv->ring.ring_obj == NULL) {
2332                 mutex_unlock(&dev->struct_mutex);
2333                 return 0;
2334         }
2335
2336         /* Hack!  Don't let anybody do execbuf while we don't control the chip.
2337          * We need to replace this with a semaphore, or something.
2338          */
2339         dev_priv->mm.suspended = 1;
2340
2341         /* Cancel the retire work handler, wait for it to finish if running
2342          */
2343         mutex_unlock(&dev->struct_mutex);
2344         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
2345         mutex_lock(&dev->struct_mutex);
2346
2347         i915_kernel_lost_context(dev);
2348
2349         /* Flush the GPU along with all non-CPU write domains
2350          */
2351         i915_gem_flush(dev, ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT),
2352                        ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT));
2353         seqno = i915_add_request(dev, ~(I915_GEM_DOMAIN_CPU |
2354                                         I915_GEM_DOMAIN_GTT));
2355
2356         if (seqno == 0) {
2357                 mutex_unlock(&dev->struct_mutex);
2358                 return -ENOMEM;
2359         }
2360
2361         dev_priv->mm.waiting_gem_seqno = seqno;
2362         last_seqno = 0;
2363         stuck = 0;
2364         for (;;) {
2365                 cur_seqno = i915_get_gem_seqno(dev);
2366                 if (i915_seqno_passed(cur_seqno, seqno))
2367                         break;
2368                 if (last_seqno == cur_seqno) {
2369                         if (stuck++ > 100) {
2370                                 DRM_ERROR("hardware wedged\n");
2371                                 dev_priv->mm.wedged = 1;
2372                                 DRM_WAKEUP(&dev_priv->irq_queue);
2373                                 break;
2374                         }
2375                 }
2376                 msleep(10);
2377                 last_seqno = cur_seqno;
2378         }
2379         dev_priv->mm.waiting_gem_seqno = 0;
2380
2381         i915_gem_retire_requests(dev);
2382
2383         if (!dev_priv->mm.wedged) {
2384                 /* Active and flushing should now be empty as we've
2385                  * waited for a sequence higher than any pending execbuffer
2386                  */
2387                 WARN_ON(!list_empty(&dev_priv->mm.active_list));
2388                 WARN_ON(!list_empty(&dev_priv->mm.flushing_list));
2389                 /* Request should now be empty as we've also waited
2390                  * for the last request in the list
2391                  */
2392                 WARN_ON(!list_empty(&dev_priv->mm.request_list));
2393         }
2394
2395         /* Empty the active and flushing lists to inactive.  If there's
2396          * anything left at this point, it means that we're wedged and
2397          * nothing good's going to happen by leaving them there.  So strip
2398          * the GPU domains and just stuff them onto inactive.
2399          */
2400         while (!list_empty(&dev_priv->mm.active_list)) {
2401                 struct drm_i915_gem_object *obj_priv;
2402
2403                 obj_priv = list_first_entry(&dev_priv->mm.active_list,
2404                                             struct drm_i915_gem_object,
2405                                             list);
2406                 obj_priv->obj->write_domain &= ~I915_GEM_GPU_DOMAINS;
2407                 i915_gem_object_move_to_inactive(obj_priv->obj);
2408         }
2409
2410         while (!list_empty(&dev_priv->mm.flushing_list)) {
2411                 struct drm_i915_gem_object *obj_priv;
2412
2413                 obj_priv = list_first_entry(&dev_priv->mm.flushing_list,
2414                                             struct drm_i915_gem_object,
2415                                             list);
2416                 obj_priv->obj->write_domain &= ~I915_GEM_GPU_DOMAINS;
2417                 i915_gem_object_move_to_inactive(obj_priv->obj);
2418         }
2419
2420
2421         /* Move all inactive buffers out of the GTT. */
2422         ret = i915_gem_evict_from_list(dev, &dev_priv->mm.inactive_list);
2423         WARN_ON(!list_empty(&dev_priv->mm.inactive_list));
2424         if (ret) {
2425                 mutex_unlock(&dev->struct_mutex);
2426                 return ret;
2427         }
2428
2429         i915_gem_cleanup_ringbuffer(dev);
2430         mutex_unlock(&dev->struct_mutex);
2431
2432         return 0;
2433 }
2434
2435 static int
2436 i915_gem_init_hws(struct drm_device *dev)
2437 {
2438         drm_i915_private_t *dev_priv = dev->dev_private;
2439         struct drm_gem_object *obj;
2440         struct drm_i915_gem_object *obj_priv;
2441         int ret;
2442
2443         /* If we need a physical address for the status page, it's already
2444          * initialized at driver load time.
2445          */
2446         if (!I915_NEED_GFX_HWS(dev))
2447                 return 0;
2448
2449         obj = drm_gem_object_alloc(dev, 4096);
2450         if (obj == NULL) {
2451                 DRM_ERROR("Failed to allocate status page\n");
2452                 return -ENOMEM;
2453         }
2454         obj_priv = obj->driver_private;
2455         obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
2456
2457         ret = i915_gem_object_pin(obj, 4096);
2458         if (ret != 0) {
2459                 drm_gem_object_unreference(obj);
2460                 return ret;
2461         }
2462
2463         dev_priv->status_gfx_addr = obj_priv->gtt_offset;
2464
2465         dev_priv->hw_status_page = kmap(obj_priv->page_list[0]);
2466         if (dev_priv->hw_status_page == NULL) {
2467                 DRM_ERROR("Failed to map status page.\n");
2468                 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
2469                 drm_gem_object_unreference(obj);
2470                 return -EINVAL;
2471         }
2472         dev_priv->hws_obj = obj;
2473         memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
2474         I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
2475         I915_READ(HWS_PGA); /* posting read */
2476         DRM_DEBUG("hws offset: 0x%08x\n", dev_priv->status_gfx_addr);
2477
2478         return 0;
2479 }
2480
2481 static int
2482 i915_gem_init_ringbuffer(struct drm_device *dev)
2483 {
2484         drm_i915_private_t *dev_priv = dev->dev_private;
2485         struct drm_gem_object *obj;
2486         struct drm_i915_gem_object *obj_priv;
2487         int ret;
2488         u32 head;
2489
2490         ret = i915_gem_init_hws(dev);
2491         if (ret != 0)
2492                 return ret;
2493
2494         obj = drm_gem_object_alloc(dev, 128 * 1024);
2495         if (obj == NULL) {
2496                 DRM_ERROR("Failed to allocate ringbuffer\n");
2497                 return -ENOMEM;
2498         }
2499         obj_priv = obj->driver_private;
2500
2501         ret = i915_gem_object_pin(obj, 4096);
2502         if (ret != 0) {
2503                 drm_gem_object_unreference(obj);
2504                 return ret;
2505         }
2506
2507         /* Set up the kernel mapping for the ring. */
2508         dev_priv->ring.Size = obj->size;
2509         dev_priv->ring.tail_mask = obj->size - 1;
2510
2511         dev_priv->ring.map.offset = dev->agp->base + obj_priv->gtt_offset;
2512         dev_priv->ring.map.size = obj->size;
2513         dev_priv->ring.map.type = 0;
2514         dev_priv->ring.map.flags = 0;
2515         dev_priv->ring.map.mtrr = 0;
2516
2517         drm_core_ioremap_wc(&dev_priv->ring.map, dev);
2518         if (dev_priv->ring.map.handle == NULL) {
2519                 DRM_ERROR("Failed to map ringbuffer.\n");
2520                 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
2521                 drm_gem_object_unreference(obj);
2522                 return -EINVAL;
2523         }
2524         dev_priv->ring.ring_obj = obj;
2525         dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
2526
2527         /* Stop the ring if it's running. */
2528         I915_WRITE(PRB0_CTL, 0);
2529         I915_WRITE(PRB0_TAIL, 0);
2530         I915_WRITE(PRB0_HEAD, 0);
2531
2532         /* Initialize the ring. */
2533         I915_WRITE(PRB0_START, obj_priv->gtt_offset);
2534         head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
2535
2536         /* G45 ring initialization fails to reset head to zero */
2537         if (head != 0) {
2538                 DRM_ERROR("Ring head not reset to zero "
2539                           "ctl %08x head %08x tail %08x start %08x\n",
2540                           I915_READ(PRB0_CTL),
2541                           I915_READ(PRB0_HEAD),
2542                           I915_READ(PRB0_TAIL),
2543                           I915_READ(PRB0_START));
2544                 I915_WRITE(PRB0_HEAD, 0);
2545
2546                 DRM_ERROR("Ring head forced to zero "
2547                           "ctl %08x head %08x tail %08x start %08x\n",
2548                           I915_READ(PRB0_CTL),
2549                           I915_READ(PRB0_HEAD),
2550                           I915_READ(PRB0_TAIL),
2551                           I915_READ(PRB0_START));
2552         }
2553
2554         I915_WRITE(PRB0_CTL,
2555                    ((obj->size - 4096) & RING_NR_PAGES) |
2556                    RING_NO_REPORT |
2557                    RING_VALID);
2558
2559         head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
2560
2561         /* If the head is still not zero, the ring is dead */
2562         if (head != 0) {
2563                 DRM_ERROR("Ring initialization failed "
2564                           "ctl %08x head %08x tail %08x start %08x\n",
2565                           I915_READ(PRB0_CTL),
2566                           I915_READ(PRB0_HEAD),
2567                           I915_READ(PRB0_TAIL),
2568                           I915_READ(PRB0_START));
2569                 return -EIO;
2570         }
2571
2572         /* Update our cache of the ring state */
2573         i915_kernel_lost_context(dev);
2574
2575         return 0;
2576 }
2577
2578 static void
2579 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
2580 {
2581         drm_i915_private_t *dev_priv = dev->dev_private;
2582
2583         if (dev_priv->ring.ring_obj == NULL)
2584                 return;
2585
2586         drm_core_ioremapfree(&dev_priv->ring.map, dev);
2587
2588         i915_gem_object_unpin(dev_priv->ring.ring_obj);
2589         drm_gem_object_unreference(dev_priv->ring.ring_obj);
2590         dev_priv->ring.ring_obj = NULL;
2591         memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
2592
2593         if (dev_priv->hws_obj != NULL) {
2594                 struct drm_gem_object *obj = dev_priv->hws_obj;
2595                 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2596
2597                 kunmap(obj_priv->page_list[0]);
2598                 i915_gem_object_unpin(obj);
2599                 drm_gem_object_unreference(obj);
2600                 dev_priv->hws_obj = NULL;
2601                 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
2602                 dev_priv->hw_status_page = NULL;
2603
2604                 /* Write high address into HWS_PGA when disabling. */
2605                 I915_WRITE(HWS_PGA, 0x1ffff000);
2606         }
2607 }
2608
2609 int
2610 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
2611                        struct drm_file *file_priv)
2612 {
2613         drm_i915_private_t *dev_priv = dev->dev_private;
2614         int ret;
2615
2616         if (dev_priv->mm.wedged) {
2617                 DRM_ERROR("Reenabling wedged hardware, good luck\n");
2618                 dev_priv->mm.wedged = 0;
2619         }
2620
2621         ret = i915_gem_init_ringbuffer(dev);
2622         if (ret != 0)
2623                 return ret;
2624
2625         dev_priv->mm.gtt_mapping = io_mapping_create_wc(dev->agp->base,
2626                                                         dev->agp->agp_info.aper_size
2627                                                         * 1024 * 1024);
2628
2629         mutex_lock(&dev->struct_mutex);
2630         BUG_ON(!list_empty(&dev_priv->mm.active_list));
2631         BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
2632         BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
2633         BUG_ON(!list_empty(&dev_priv->mm.request_list));
2634         dev_priv->mm.suspended = 0;
2635         mutex_unlock(&dev->struct_mutex);
2636
2637         drm_irq_install(dev);
2638
2639         return 0;
2640 }
2641
2642 int
2643 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
2644                        struct drm_file *file_priv)
2645 {
2646         drm_i915_private_t *dev_priv = dev->dev_private;
2647         int ret;
2648
2649         ret = i915_gem_idle(dev);
2650         drm_irq_uninstall(dev);
2651
2652         io_mapping_free(dev_priv->mm.gtt_mapping);
2653         return ret;
2654 }
2655
2656 void
2657 i915_gem_lastclose(struct drm_device *dev)
2658 {
2659         int ret;
2660
2661         ret = i915_gem_idle(dev);
2662         if (ret)
2663                 DRM_ERROR("failed to idle hardware: %d\n", ret);
2664 }
2665
2666 void
2667 i915_gem_load(struct drm_device *dev)
2668 {
2669         drm_i915_private_t *dev_priv = dev->dev_private;
2670
2671         INIT_LIST_HEAD(&dev_priv->mm.active_list);
2672         INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
2673         INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
2674         INIT_LIST_HEAD(&dev_priv->mm.request_list);
2675         INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
2676                           i915_gem_retire_work_handler);
2677         dev_priv->mm.next_gem_seqno = 1;
2678
2679         i915_gem_detect_bit_6_swizzle(dev);
2680 }