drivers/gpu/drm/i915/i915_gem_gtt.c

   1 /*
   2  * Copyright © 2010 Daniel Vetter
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include <drm/drmP.h>
  26 #include <drm/i915_drm.h>
  27 #include "i915_drv.h"
  28 #include "i915_trace.h"
  29 #include "intel_drv.h"
  30
  31 typedef uint32_t gen6_gtt_pte_t;
  32
  33 /* PPGTT stuff */
  34 #define GEN6_GTT_ADDR_ENCODE(addr)      ((addr) | (((addr) >> 28) & 0xff0))
  35
  36 #define GEN6_PDE_VALID                  (1 << 0)
  37 /* gen6+ has bit 11-4 for physical addr bit 39-32 */
  38 #define GEN6_PDE_ADDR_ENCODE(addr)      GEN6_GTT_ADDR_ENCODE(addr)
  39
  40 #define GEN6_PTE_VALID                  (1 << 0)
  41 #define GEN6_PTE_UNCACHED               (1 << 1)
  42 #define HSW_PTE_UNCACHED                (0)
  43 #define GEN6_PTE_CACHE_LLC              (2 << 1)
  44 #define GEN6_PTE_CACHE_LLC_MLC          (3 << 1)
  45 #define GEN6_PTE_ADDR_ENCODE(addr)      GEN6_GTT_ADDR_ENCODE(addr)
  46
  47 static inline gen6_gtt_pte_t gen6_pte_encode(struct drm_device *dev,
  48                                              dma_addr_t addr,
  49                                              enum i915_cache_level level)
  50 {
  51         gen6_gtt_pte_t pte = GEN6_PTE_VALID;
  52         pte |= GEN6_PTE_ADDR_ENCODE(addr);
  53
  54         switch (level) {
  55         case I915_CACHE_LLC_MLC:
  56                 /* Haswell doesn't set L3 this way */
  57                 if (IS_HASWELL(dev))
  58                         pte |= GEN6_PTE_CACHE_LLC;
  59                 else
  60                         pte |= GEN6_PTE_CACHE_LLC_MLC;
  61                 break;
  62         case I915_CACHE_LLC:
  63                 pte |= GEN6_PTE_CACHE_LLC;
  64                 break;
  65         case I915_CACHE_NONE:
  66                 if (IS_HASWELL(dev))
  67                         pte |= HSW_PTE_UNCACHED;
  68                 else
  69                         pte |= GEN6_PTE_UNCACHED;
  70                 break;
  71         default:
  72                 BUG();
  73         }
  74
  75         return pte;
  76 }
  77
  78 static int gen6_ppgtt_enable(struct drm_device *dev)
  79 {
  80         drm_i915_private_t *dev_priv = dev->dev_private;
  81         uint32_t pd_offset;
  82         struct intel_ring_buffer *ring;
  83         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
  84         gen6_gtt_pte_t __iomem *pd_addr;
  85         uint32_t pd_entry;
  86         int i;
  87
  88         pd_addr = (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm +
  89                 ppgtt->pd_offset / sizeof(gen6_gtt_pte_t);
  90         for (i = 0; i < ppgtt->num_pd_entries; i++) {
  91                 dma_addr_t pt_addr;
  92
  93                 pt_addr = ppgtt->pt_dma_addr[i];
  94                 pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);
  95                 pd_entry |= GEN6_PDE_VALID;
  96
  97                 writel(pd_entry, pd_addr + i);
  98         }
  99         readl(pd_addr);
 100
 101         pd_offset = ppgtt->pd_offset;
 102         pd_offset /= 64; /* in cachelines, */
 103         pd_offset <<= 16;
 104
 105         if (INTEL_INFO(dev)->gen == 6) {
 106                 uint32_t ecochk, gab_ctl, ecobits;
 107
 108                 ecobits = I915_READ(GAC_ECO_BITS);
 109                 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
 110                                          ECOBITS_PPGTT_CACHE64B);
 111
 112                 gab_ctl = I915_READ(GAB_CTL);
 113                 I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
 114
 115                 ecochk = I915_READ(GAM_ECOCHK);
 116                 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT |
 117                                        ECOCHK_PPGTT_CACHE64B);
 118                 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
 119         } else if (INTEL_INFO(dev)->gen >= 7) {
 120                 uint32_t ecochk, ecobits;
 121
 122                 ecobits = I915_READ(GAC_ECO_BITS);
 123                 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
 124
 125                 ecochk = I915_READ(GAM_ECOCHK);
 126                 if (IS_HASWELL(dev)) {
 127                         ecochk |= ECOCHK_PPGTT_WB_HSW;
 128                 } else {
 129                         ecochk |= ECOCHK_PPGTT_LLC_IVB;
 130                         ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
 131                 }
 132                 I915_WRITE(GAM_ECOCHK, ecochk);
 133                 /* GFX_MODE is per-ring on gen7+ */
 134         }
 135
 136         for_each_ring(ring, dev_priv, i) {
 137                 if (INTEL_INFO(dev)->gen >= 7)
 138                         I915_WRITE(RING_MODE_GEN7(ring),
 139                                    _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
 140
 141                 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
 142                 I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset);
 143         }
 144         return 0;
 145 }
 146
 147 /* PPGTT support for Sandybdrige/Gen6 and later */
 148 static void gen6_ppgtt_clear_range(struct i915_hw_ppgtt *ppgtt,
 149                                    unsigned first_entry,
 150                                    unsigned num_entries)
 151 {
 152         gen6_gtt_pte_t *pt_vaddr, scratch_pte;
 153         unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
 154         unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES;
 155         unsigned last_pte, i;
 156
 157         scratch_pte = gen6_pte_encode(ppgtt->dev,
 158                                       ppgtt->scratch_page_dma_addr,
 159                                       I915_CACHE_LLC);
 160
 161         while (num_entries) {
 162                 last_pte = first_pte + num_entries;
 163                 if (last_pte > I915_PPGTT_PT_ENTRIES)
 164                         last_pte = I915_PPGTT_PT_ENTRIES;
 165
 166                 pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
 167
 168                 for (i = first_pte; i < last_pte; i++)
 169                         pt_vaddr[i] = scratch_pte;
 170
 171                 kunmap_atomic(pt_vaddr);
 172
 173                 num_entries -= last_pte - first_pte;
 174                 first_pte = 0;
 175                 act_pt++;
 176         }
 177 }
 178
 179 static void gen6_ppgtt_insert_entries(struct i915_hw_ppgtt *ppgtt,
 180                                       struct sg_table *pages,
 181                                       unsigned first_entry,
 182                                       enum i915_cache_level cache_level)
 183 {
 184         gen6_gtt_pte_t *pt_vaddr;
 185         unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
 186         unsigned act_pte = first_entry % I915_PPGTT_PT_ENTRIES;
 187         struct sg_page_iter sg_iter;
 188
 189         pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
 190         for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
 191                 dma_addr_t page_addr;
 192
 193                 page_addr = sg_page_iter_dma_address(&sg_iter);
 194                 pt_vaddr[act_pte] = gen6_pte_encode(ppgtt->dev, page_addr,
 195                                                     cache_level);
 196                 if (++act_pte == I915_PPGTT_PT_ENTRIES) {
 197                         kunmap_atomic(pt_vaddr);
 198                         act_pt++;
 199                         pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
 200                         act_pte = 0;
 201
 202                 }
 203         }
 204         kunmap_atomic(pt_vaddr);
 205 }
 206
 207 static void gen6_ppgtt_cleanup(struct i915_hw_ppgtt *ppgtt)
 208 {
 209         int i;
 210
 211         if (ppgtt->pt_dma_addr) {
 212                 for (i = 0; i < ppgtt->num_pd_entries; i++)
 213                         pci_unmap_page(ppgtt->dev->pdev,
 214                                        ppgtt->pt_dma_addr[i],
 215                                        4096, PCI_DMA_BIDIRECTIONAL);
 216         }
 217
 218         kfree(ppgtt->pt_dma_addr);
 219         for (i = 0; i < ppgtt->num_pd_entries; i++)
 220                 __free_page(ppgtt->pt_pages[i]);
 221         kfree(ppgtt->pt_pages);
 222         kfree(ppgtt);
 223 }
 224
 225 static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
 226 {
 227         struct drm_device *dev = ppgtt->dev;
 228         struct drm_i915_private *dev_priv = dev->dev_private;
 229         unsigned first_pd_entry_in_global_pt;
 230         int i;
 231         int ret = -ENOMEM;
 232
 233         /* ppgtt PDEs reside in the global gtt pagetable, which has 512*1024
 234          * entries. For aliasing ppgtt support we just steal them at the end for
 235          * now. */
 236        first_pd_entry_in_global_pt = gtt_total_entries(dev_priv->gtt);
 237
 238         ppgtt->num_pd_entries = I915_PPGTT_PD_ENTRIES;
 239         ppgtt->enable = gen6_ppgtt_enable;
 240         ppgtt->clear_range = gen6_ppgtt_clear_range;
 241         ppgtt->insert_entries = gen6_ppgtt_insert_entries;
 242         ppgtt->cleanup = gen6_ppgtt_cleanup;
 243         ppgtt->pt_pages = kzalloc(sizeof(struct page *)*ppgtt->num_pd_entries,
 244                                   GFP_KERNEL);
 245         if (!ppgtt->pt_pages)
 246                 return -ENOMEM;
 247
 248         for (i = 0; i < ppgtt->num_pd_entries; i++) {
 249                 ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL);
 250                 if (!ppgtt->pt_pages[i])
 251                         goto err_pt_alloc;
 252         }
 253
 254         ppgtt->pt_dma_addr = kzalloc(sizeof(dma_addr_t) *ppgtt->num_pd_entries,
 255                                      GFP_KERNEL);
 256         if (!ppgtt->pt_dma_addr)
 257                 goto err_pt_alloc;
 258
 259         for (i = 0; i < ppgtt->num_pd_entries; i++) {
 260                 dma_addr_t pt_addr;
 261
 262                 pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], 0, 4096,
 263                                        PCI_DMA_BIDIRECTIONAL);
 264
 265                 if (pci_dma_mapping_error(dev->pdev, pt_addr)) {
 266                         ret = -EIO;
 267                         goto err_pd_pin;
 268
 269                 }
 270                 ppgtt->pt_dma_addr[i] = pt_addr;
 271         }
 272
 273         ppgtt->clear_range(ppgtt, 0,
 274                            ppgtt->num_pd_entries*I915_PPGTT_PT_ENTRIES);
 275
 276         ppgtt->pd_offset = first_pd_entry_in_global_pt * sizeof(gen6_gtt_pte_t);
 277
 278         return 0;
 279
 280 err_pd_pin:
 281         if (ppgtt->pt_dma_addr) {
 282                 for (i--; i >= 0; i--)
 283                         pci_unmap_page(dev->pdev, ppgtt->pt_dma_addr[i],
 284                                        4096, PCI_DMA_BIDIRECTIONAL);
 285         }
 286 err_pt_alloc:
 287         kfree(ppgtt->pt_dma_addr);
 288         for (i = 0; i < ppgtt->num_pd_entries; i++) {
 289                 if (ppgtt->pt_pages[i])
 290                         __free_page(ppgtt->pt_pages[i]);
 291         }
 292         kfree(ppgtt->pt_pages);
 293
 294         return ret;
 295 }
 296
 297 static int i915_gem_init_aliasing_ppgtt(struct drm_device *dev)
 298 {
 299         struct drm_i915_private *dev_priv = dev->dev_private;
 300         struct i915_hw_ppgtt *ppgtt;
 301         int ret;
 302
 303         ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
 304         if (!ppgtt)
 305                 return -ENOMEM;
 306
 307         ppgtt->dev = dev;
 308         ppgtt->scratch_page_dma_addr = dev_priv->gtt.scratch_page_dma;
 309
 310         if (INTEL_INFO(dev)->gen < 8)
 311                 ret = gen6_ppgtt_init(ppgtt);
 312         else
 313                 BUG();
 314
 315         if (ret)
 316                 kfree(ppgtt);
 317         else
 318                 dev_priv->mm.aliasing_ppgtt = ppgtt;
 319
 320         return ret;
 321 }
 322
 323 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev)
 324 {
 325         struct drm_i915_private *dev_priv = dev->dev_private;
 326         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
 327
 328         if (!ppgtt)
 329                 return;
 330
 331         ppgtt->cleanup(ppgtt);
 332         dev_priv->mm.aliasing_ppgtt = NULL;
 333 }
 334
 335 void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
 336                             struct drm_i915_gem_object *obj,
 337                             enum i915_cache_level cache_level)
 338 {
 339         ppgtt->insert_entries(ppgtt, obj->pages,
 340                               obj->gtt_space->start >> PAGE_SHIFT,
 341                               cache_level);
 342 }
 343
 344 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
 345                               struct drm_i915_gem_object *obj)
 346 {
 347         ppgtt->clear_range(ppgtt,
 348                            obj->gtt_space->start >> PAGE_SHIFT,
 349                            obj->base.size >> PAGE_SHIFT);
 350 }
 351
 352 extern int intel_iommu_gfx_mapped;
 353 /* Certain Gen5 chipsets require require idling the GPU before
 354  * unmapping anything from the GTT when VT-d is enabled.
 355  */
 356 static inline bool needs_idle_maps(struct drm_device *dev)
 357 {
 358 #ifdef CONFIG_INTEL_IOMMU
 359         /* Query intel_iommu to see if we need the workaround. Presumably that
 360          * was loaded first.
 361          */
 362         if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped)
 363                 return true;
 364 #endif
 365         return false;
 366 }
 367
 368 static bool do_idling(struct drm_i915_private *dev_priv)
 369 {
 370         bool ret = dev_priv->mm.interruptible;
 371
 372         if (unlikely(dev_priv->gtt.do_idle_maps)) {
 373                 dev_priv->mm.interruptible = false;
 374                 if (i915_gpu_idle(dev_priv->dev)) {
 375                         DRM_ERROR("Couldn't idle GPU\n");
 376                         /* Wait a bit, in hopes it avoids the hang */
 377                         udelay(10);
 378                 }
 379         }
 380
 381         return ret;
 382 }
 383
 384 static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
 385 {
 386         if (unlikely(dev_priv->gtt.do_idle_maps))
 387                 dev_priv->mm.interruptible = interruptible;
 388 }
 389
 390 void i915_gem_restore_gtt_mappings(struct drm_device *dev)
 391 {
 392         struct drm_i915_private *dev_priv = dev->dev_private;
 393         struct drm_i915_gem_object *obj;
 394
 395         /* First fill our portion of the GTT with scratch pages */
 396         dev_priv->gtt.gtt_clear_range(dev, dev_priv->gtt.start / PAGE_SIZE,
 397                                       dev_priv->gtt.total / PAGE_SIZE);
 398
 399         list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) {
 400                 i915_gem_clflush_object(obj);
 401                 i915_gem_gtt_bind_object(obj, obj->cache_level);
 402         }
 403
 404         i915_gem_chipset_flush(dev);
 405 }
 406
 407 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
 408 {
 409         if (obj->has_dma_mapping)
 410                 return 0;
 411
 412         if (!dma_map_sg(&obj->base.dev->pdev->dev,
 413                         obj->pages->sgl, obj->pages->nents,
 414                         PCI_DMA_BIDIRECTIONAL))
 415                 return -ENOSPC;
 416
 417         return 0;
 418 }
 419
 420 /*
 421  * Binds an object into the global gtt with the specified cache level. The object
 422  * will be accessible to the GPU via commands whose operands reference offsets
 423  * within the global GTT as well as accessible by the GPU through the GMADR
 424  * mapped BAR (dev_priv->mm.gtt->gtt).
 425  */
 426 static void gen6_ggtt_insert_entries(struct drm_device *dev,
 427                                      struct sg_table *st,
 428                                      unsigned int first_entry,
 429                                      enum i915_cache_level level)
 430 {
 431         struct drm_i915_private *dev_priv = dev->dev_private;
 432         gen6_gtt_pte_t __iomem *gtt_entries =
 433                 (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
 434         int i = 0;
 435         struct sg_page_iter sg_iter;
 436         dma_addr_t addr;
 437
 438         for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
 439                 addr = sg_page_iter_dma_address(&sg_iter);
 440                 iowrite32(gen6_pte_encode(dev, addr, level), &gtt_entries[i]);
 441                 i++;
 442         }
 443
 444         /* XXX: This serves as a posting read to make sure that the PTE has
 445          * actually been updated. There is some concern that even though
 446          * registers and PTEs are within the same BAR that they are potentially
 447          * of NUMA access patterns. Therefore, even with the way we assume
 448          * hardware should work, we must keep this posting read for paranoia.
 449          */
 450         if (i != 0)
 451                 WARN_ON(readl(&gtt_entries[i-1])
 452                         != gen6_pte_encode(dev, addr, level));
 453
 454         /* This next bit makes the above posting read even more important. We
 455          * want to flush the TLBs only after we're certain all the PTE updates
 456          * have finished.
 457          */
 458         I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
 459         POSTING_READ(GFX_FLSH_CNTL_GEN6);
 460 }
 461
 462 static void gen6_ggtt_clear_range(struct drm_device *dev,
 463                                   unsigned int first_entry,
 464                                   unsigned int num_entries)
 465 {
 466         struct drm_i915_private *dev_priv = dev->dev_private;
 467         gen6_gtt_pte_t scratch_pte, __iomem *gtt_base =
 468                 (gen6_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
 469         const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
 470         int i;
 471
 472         if (WARN(num_entries > max_entries,
 473                  "First entry = %d; Num entries = %d (max=%d)\n",
 474                  first_entry, num_entries, max_entries))
 475                 num_entries = max_entries;
 476
 477         scratch_pte = gen6_pte_encode(dev, dev_priv->gtt.scratch_page_dma,
 478                                       I915_CACHE_LLC);
 479         for (i = 0; i < num_entries; i++)
 480                 iowrite32(scratch_pte, &gtt_base[i]);
 481         readl(gtt_base);
 482 }
 483
 484
 485 static void i915_ggtt_insert_entries(struct drm_device *dev,
 486                                      struct sg_table *st,
 487                                      unsigned int pg_start,
 488                                      enum i915_cache_level cache_level)
 489 {
 490         unsigned int flags = (cache_level == I915_CACHE_NONE) ?
 491                 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
 492
 493         intel_gtt_insert_sg_entries(st, pg_start, flags);
 494
 495 }
 496
 497 static void i915_ggtt_clear_range(struct drm_device *dev,
 498                                   unsigned int first_entry,
 499                                   unsigned int num_entries)
 500 {
 501         intel_gtt_clear_range(first_entry, num_entries);
 502 }
 503
 504
 505 void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
 506                               enum i915_cache_level cache_level)
 507 {
 508         struct drm_device *dev = obj->base.dev;
 509         struct drm_i915_private *dev_priv = dev->dev_private;
 510
 511         dev_priv->gtt.gtt_insert_entries(dev, obj->pages,
 512                                          obj->gtt_space->start >> PAGE_SHIFT,
 513                                          cache_level);
 514
 515         obj->has_global_gtt_mapping = 1;
 516 }
 517
 518 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj)
 519 {
 520         struct drm_device *dev = obj->base.dev;
 521         struct drm_i915_private *dev_priv = dev->dev_private;
 522
 523         dev_priv->gtt.gtt_clear_range(obj->base.dev,
 524                                       obj->gtt_space->start >> PAGE_SHIFT,
 525                                       obj->base.size >> PAGE_SHIFT);
 526
 527         obj->has_global_gtt_mapping = 0;
 528 }
 529
 530 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
 531 {
 532         struct drm_device *dev = obj->base.dev;
 533         struct drm_i915_private *dev_priv = dev->dev_private;
 534         bool interruptible;
 535
 536         interruptible = do_idling(dev_priv);
 537
 538         if (!obj->has_dma_mapping)
 539                 dma_unmap_sg(&dev->pdev->dev,
 540                              obj->pages->sgl, obj->pages->nents,
 541                              PCI_DMA_BIDIRECTIONAL);
 542
 543         undo_idling(dev_priv, interruptible);
 544 }
 545
 546 static void i915_gtt_color_adjust(struct drm_mm_node *node,
 547                                   unsigned long color,
 548                                   unsigned long *start,
 549                                   unsigned long *end)
 550 {
 551         if (node->color != color)
 552                 *start += 4096;
 553
 554         if (!list_empty(&node->node_list)) {
 555                 node = list_entry(node->node_list.next,
 556                                   struct drm_mm_node,
 557                                   node_list);
 558                 if (node->allocated && node->color != color)
 559                         *end -= 4096;
 560         }
 561 }
 562 void i915_gem_setup_global_gtt(struct drm_device *dev,
 563                                unsigned long start,
 564                                unsigned long mappable_end,
 565                                unsigned long end)
 566 {
 567         /* Let GEM Manage all of the aperture.
 568          *
 569          * However, leave one page at the end still bound to the scratch page.
 570          * There are a number of places where the hardware apparently prefetches
 571          * past the end of the object, and we've seen multiple hangs with the
 572          * GPU head pointer stuck in a batchbuffer bound at the last page of the
 573          * aperture.  One page should be enough to keep any prefetching inside
 574          * of the aperture.
 575          */
 576         drm_i915_private_t *dev_priv = dev->dev_private;
 577         struct drm_mm_node *entry;
 578         struct drm_i915_gem_object *obj;
 579         unsigned long hole_start, hole_end;
 580
 581         BUG_ON(mappable_end > end);
 582
 583         /* Subtract the guard page ... */
 584         drm_mm_init(&dev_priv->mm.gtt_space, start, end - start - PAGE_SIZE);
 585         if (!HAS_LLC(dev))
 586                 dev_priv->mm.gtt_space.color_adjust = i915_gtt_color_adjust;
 587
 588         /* Mark any preallocated objects as occupied */
 589         list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) {
 590                 DRM_DEBUG_KMS("reserving preallocated space: %x + %zx\n",
 591                               obj->gtt_offset, obj->base.size);
 592
 593                 BUG_ON(obj->gtt_space != I915_GTT_RESERVED);
 594                 obj->gtt_space = drm_mm_create_block(&dev_priv->mm.gtt_space,
 595                                                      obj->gtt_offset,
 596                                                      obj->base.size,
 597                                                      false);
 598                 obj->has_global_gtt_mapping = 1;
 599         }
 600
 601         dev_priv->gtt.start = start;
 602         dev_priv->gtt.total = end - start;
 603
 604         /* Clear any non-preallocated blocks */
 605         drm_mm_for_each_hole(entry, &dev_priv->mm.gtt_space,
 606                              hole_start, hole_end) {
 607                 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
 608                               hole_start, hole_end);
 609                 dev_priv->gtt.gtt_clear_range(dev, hole_start / PAGE_SIZE,
 610                                               (hole_end-hole_start) / PAGE_SIZE);
 611         }
 612
 613         /* And finally clear the reserved guard page */
 614         dev_priv->gtt.gtt_clear_range(dev, end / PAGE_SIZE - 1, 1);
 615 }
 616
 617 static bool
 618 intel_enable_ppgtt(struct drm_device *dev)
 619 {
 620         if (i915_enable_ppgtt >= 0)
 621                 return i915_enable_ppgtt;
 622
 623 #ifdef CONFIG_INTEL_IOMMU
 624         /* Disable ppgtt on SNB if VT-d is on. */
 625         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
 626                 return false;
 627 #endif
 628
 629         return true;
 630 }
 631
 632 void i915_gem_init_global_gtt(struct drm_device *dev)
 633 {
 634         struct drm_i915_private *dev_priv = dev->dev_private;
 635         unsigned long gtt_size, mappable_size;
 636
 637         gtt_size = dev_priv->gtt.total;
 638         mappable_size = dev_priv->gtt.mappable_end;
 639
 640         if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) {
 641                 int ret;
 642
 643                 if (INTEL_INFO(dev)->gen <= 7) {
 644                         /* PPGTT pdes are stolen from global gtt ptes, so shrink the
 645                          * aperture accordingly when using aliasing ppgtt. */
 646                         gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE;
 647                 }
 648
 649                 i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
 650
 651                 ret = i915_gem_init_aliasing_ppgtt(dev);
 652                 if (!ret)
 653                         return;
 654
 655                 DRM_ERROR("Aliased PPGTT setup failed %d\n", ret);
 656                 drm_mm_takedown(&dev_priv->mm.gtt_space);
 657                 gtt_size += I915_PPGTT_PD_ENTRIES*PAGE_SIZE;
 658         }
 659         i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
 660 }
 661
 662 static int setup_scratch_page(struct drm_device *dev)
 663 {
 664         struct drm_i915_private *dev_priv = dev->dev_private;
 665         struct page *page;
 666         dma_addr_t dma_addr;
 667
 668         page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
 669         if (page == NULL)
 670                 return -ENOMEM;
 671         get_page(page);
 672         set_pages_uc(page, 1);
 673
 674 #ifdef CONFIG_INTEL_IOMMU
 675         dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE,
 676                                 PCI_DMA_BIDIRECTIONAL);
 677         if (pci_dma_mapping_error(dev->pdev, dma_addr))
 678                 return -EINVAL;
 679 #else
 680         dma_addr = page_to_phys(page);
 681 #endif
 682         dev_priv->gtt.scratch_page = page;
 683         dev_priv->gtt.scratch_page_dma = dma_addr;
 684
 685         return 0;
 686 }
 687
 688 static void teardown_scratch_page(struct drm_device *dev)
 689 {
 690         struct drm_i915_private *dev_priv = dev->dev_private;
 691         set_pages_wb(dev_priv->gtt.scratch_page, 1);
 692         pci_unmap_page(dev->pdev, dev_priv->gtt.scratch_page_dma,
 693                        PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 694         put_page(dev_priv->gtt.scratch_page);
 695         __free_page(dev_priv->gtt.scratch_page);
 696 }
 697
 698 static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
 699 {
 700         snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
 701         snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
 702         return snb_gmch_ctl << 20;
 703 }
 704
 705 static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
 706 {
 707         snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
 708         snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
 709         return snb_gmch_ctl << 25; /* 32 MB units */
 710 }
 711
 712 static inline size_t gen7_get_stolen_size(u16 snb_gmch_ctl)
 713 {
 714         static const int stolen_decoder[] = {
 715                 0, 0, 0, 0, 0, 32, 48, 64, 128, 256, 96, 160, 224, 352};
 716         snb_gmch_ctl >>= IVB_GMCH_GMS_SHIFT;
 717         snb_gmch_ctl &= IVB_GMCH_GMS_MASK;
 718         return stolen_decoder[snb_gmch_ctl] << 20;
 719 }
 720
 721 static int gen6_gmch_probe(struct drm_device *dev,
 722                            size_t *gtt_total,
 723                            size_t *stolen,
 724                            phys_addr_t *mappable_base,
 725                            unsigned long *mappable_end)
 726 {
 727         struct drm_i915_private *dev_priv = dev->dev_private;
 728         phys_addr_t gtt_bus_addr;
 729         unsigned int gtt_size;
 730         u16 snb_gmch_ctl;
 731         int ret;
 732
 733         *mappable_base = pci_resource_start(dev->pdev, 2);
 734         *mappable_end = pci_resource_len(dev->pdev, 2);
 735
 736         /* 64/512MB is the current min/max we actually know of, but this is just
 737          * a coarse sanity check.
 738          */
 739         if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) {
 740                 DRM_ERROR("Unknown GMADR size (%lx)\n",
 741                           dev_priv->gtt.mappable_end);
 742                 return -ENXIO;
 743         }
 744
 745         if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
 746                 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
 747         pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
 748         gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl);
 749
 750         if (IS_GEN7(dev) && !IS_VALLEYVIEW(dev))
 751                 *stolen = gen7_get_stolen_size(snb_gmch_ctl);
 752         else
 753                 *stolen = gen6_get_stolen_size(snb_gmch_ctl);
 754
 755         *gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT;
 756
 757         /* For Modern GENs the PTEs and register space are split in the BAR */
 758         gtt_bus_addr = pci_resource_start(dev->pdev, 0) +
 759                 (pci_resource_len(dev->pdev, 0) / 2);
 760
 761         dev_priv->gtt.gsm = ioremap_wc(gtt_bus_addr, gtt_size);
 762         if (!dev_priv->gtt.gsm) {
 763                 DRM_ERROR("Failed to map the gtt page table\n");
 764                 return -ENOMEM;
 765         }
 766
 767         ret = setup_scratch_page(dev);
 768         if (ret)
 769                 DRM_ERROR("Scratch setup failed\n");
 770
 771         dev_priv->gtt.gtt_clear_range = gen6_ggtt_clear_range;
 772         dev_priv->gtt.gtt_insert_entries = gen6_ggtt_insert_entries;
 773
 774         return ret;
 775 }
 776
 777 static void gen6_gmch_remove(struct drm_device *dev)
 778 {
 779         struct drm_i915_private *dev_priv = dev->dev_private;
 780         iounmap(dev_priv->gtt.gsm);
 781         teardown_scratch_page(dev_priv->dev);
 782 }
 783
 784 static int i915_gmch_probe(struct drm_device *dev,
 785                            size_t *gtt_total,
 786                            size_t *stolen,
 787                            phys_addr_t *mappable_base,
 788                            unsigned long *mappable_end)
 789 {
 790         struct drm_i915_private *dev_priv = dev->dev_private;
 791         int ret;
 792
 793         ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL);
 794         if (!ret) {
 795                 DRM_ERROR("failed to set up gmch\n");
 796                 return -EIO;
 797         }
 798
 799         intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end);
 800
 801         dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev);
 802         dev_priv->gtt.gtt_clear_range = i915_ggtt_clear_range;
 803         dev_priv->gtt.gtt_insert_entries = i915_ggtt_insert_entries;
 804
 805         return 0;
 806 }
 807
 808 static void i915_gmch_remove(struct drm_device *dev)
 809 {
 810         intel_gmch_remove();
 811 }
 812
 813 int i915_gem_gtt_init(struct drm_device *dev)
 814 {
 815         struct drm_i915_private *dev_priv = dev->dev_private;
 816         struct i915_gtt *gtt = &dev_priv->gtt;
 817         int ret;
 818
 819         if (INTEL_INFO(dev)->gen <= 5) {
 820                 dev_priv->gtt.gtt_probe = i915_gmch_probe;
 821                 dev_priv->gtt.gtt_remove = i915_gmch_remove;
 822         } else {
 823                 dev_priv->gtt.gtt_probe = gen6_gmch_probe;
 824                 dev_priv->gtt.gtt_remove = gen6_gmch_remove;
 825         }
 826
 827         ret = dev_priv->gtt.gtt_probe(dev, &dev_priv->gtt.total,
 828                                      &dev_priv->gtt.stolen_size,
 829                                      &gtt->mappable_base,
 830                                      &gtt->mappable_end);
 831         if (ret)
 832                 return ret;
 833
 834         /* GMADR is the PCI mmio aperture into the global GTT. */
 835         DRM_INFO("Memory usable by graphics device = %zdM\n",
 836                  dev_priv->gtt.total >> 20);
 837         DRM_DEBUG_DRIVER("GMADR size = %ldM\n",
 838                          dev_priv->gtt.mappable_end >> 20);
 839         DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n",
 840                          dev_priv->gtt.stolen_size >> 20);
 841
 842         return 0;
 843 }