drivers/gpu/drm/i915/i915_oa_hsw.c

   1 /*
   2  * Autogenerated file by GPU Top : https://github.com/rib/gputop
   3  * DO NOT EDIT manually!
   4  *
   5  *
   6  * Copyright (c) 2015 Intel Corporation
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  25  * IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include <linux/sysfs.h>
  30
  31 #include "i915_drv.h"
  32 #include "i915_oa_hsw.h"
  33
  34 enum metric_set_id {
  35         METRIC_SET_ID_RENDER_BASIC = 1,
  36         METRIC_SET_ID_COMPUTE_BASIC,
  37         METRIC_SET_ID_COMPUTE_EXTENDED,
  38         METRIC_SET_ID_MEMORY_READS,
  39         METRIC_SET_ID_MEMORY_WRITES,
  40         METRIC_SET_ID_SAMPLER_BALANCE,
  41 };
  42
  43 int i915_oa_n_builtin_metric_sets_hsw = 6;
  44
  45 static const struct i915_oa_reg b_counter_config_render_basic[] = {
  46         { _MMIO(0x2724), 0x00800000 },
  47         { _MMIO(0x2720), 0x00000000 },
  48         { _MMIO(0x2714), 0x00800000 },
  49         { _MMIO(0x2710), 0x00000000 },
  50 };
  51
  52 static const struct i915_oa_reg flex_eu_config_render_basic[] = {
  53 };
  54
  55 static const struct i915_oa_reg mux_config_render_basic[] = {
  56         { _MMIO(0x253a4), 0x01600000 },
  57         { _MMIO(0x25440), 0x00100000 },
  58         { _MMIO(0x25128), 0x00000000 },
  59         { _MMIO(0x2691c), 0x00000800 },
  60         { _MMIO(0x26aa0), 0x01500000 },
  61         { _MMIO(0x26b9c), 0x00006000 },
  62         { _MMIO(0x2791c), 0x00000800 },
  63         { _MMIO(0x27aa0), 0x01500000 },
  64         { _MMIO(0x27b9c), 0x00006000 },
  65         { _MMIO(0x2641c), 0x00000400 },
  66         { _MMIO(0x25380), 0x00000010 },
  67         { _MMIO(0x2538c), 0x00000000 },
  68         { _MMIO(0x25384), 0x0800aaaa },
  69         { _MMIO(0x25400), 0x00000004 },
  70         { _MMIO(0x2540c), 0x06029000 },
  71         { _MMIO(0x25410), 0x00000002 },
  72         { _MMIO(0x25404), 0x5c30ffff },
  73         { _MMIO(0x25100), 0x00000016 },
  74         { _MMIO(0x25110), 0x00000400 },
  75         { _MMIO(0x25104), 0x00000000 },
  76         { _MMIO(0x26804), 0x00001211 },
  77         { _MMIO(0x26884), 0x00000100 },
  78         { _MMIO(0x26900), 0x00000002 },
  79         { _MMIO(0x26908), 0x00700000 },
  80         { _MMIO(0x26904), 0x00000000 },
  81         { _MMIO(0x26984), 0x00001022 },
  82         { _MMIO(0x26a04), 0x00000011 },
  83         { _MMIO(0x26a80), 0x00000006 },
  84         { _MMIO(0x26a88), 0x00000c02 },
  85         { _MMIO(0x26a84), 0x00000000 },
  86         { _MMIO(0x26b04), 0x00001000 },
  87         { _MMIO(0x26b80), 0x00000002 },
  88         { _MMIO(0x26b8c), 0x00000007 },
  89         { _MMIO(0x26b84), 0x00000000 },
  90         { _MMIO(0x27804), 0x00004844 },
  91         { _MMIO(0x27884), 0x00000400 },
  92         { _MMIO(0x27900), 0x00000002 },
  93         { _MMIO(0x27908), 0x0e000000 },
  94         { _MMIO(0x27904), 0x00000000 },
  95         { _MMIO(0x27984), 0x00004088 },
  96         { _MMIO(0x27a04), 0x00000044 },
  97         { _MMIO(0x27a80), 0x00000006 },
  98         { _MMIO(0x27a88), 0x00018040 },
  99         { _MMIO(0x27a84), 0x00000000 },
 100         { _MMIO(0x27b04), 0x00004000 },
 101         { _MMIO(0x27b80), 0x00000002 },
 102         { _MMIO(0x27b8c), 0x000000e0 },
 103         { _MMIO(0x27b84), 0x00000000 },
 104         { _MMIO(0x26104), 0x00002222 },
 105         { _MMIO(0x26184), 0x0c006666 },
 106         { _MMIO(0x26284), 0x04000000 },
 107         { _MMIO(0x26304), 0x04000000 },
 108         { _MMIO(0x26400), 0x00000002 },
 109         { _MMIO(0x26410), 0x000000a0 },
 110         { _MMIO(0x26404), 0x00000000 },
 111         { _MMIO(0x25420), 0x04108020 },
 112         { _MMIO(0x25424), 0x1284a420 },
 113         { _MMIO(0x2541c), 0x00000000 },
 114         { _MMIO(0x25428), 0x00042049 },
 115 };
 116
 117 static int
 118 get_render_basic_mux_config(struct drm_i915_private *dev_priv,
 119                             const struct i915_oa_reg **regs,
 120                             int *lens)
 121 {
 122         int n = 0;
 123
 124         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
 125         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
 126
 127         regs[n] = mux_config_render_basic;
 128         lens[n] = ARRAY_SIZE(mux_config_render_basic);
 129         n++;
 130
 131         return n;
 132 }
 133
 134 static const struct i915_oa_reg b_counter_config_compute_basic[] = {
 135         { _MMIO(0x2710), 0x00000000 },
 136         { _MMIO(0x2714), 0x00800000 },
 137         { _MMIO(0x2718), 0xaaaaaaaa },
 138         { _MMIO(0x271c), 0xaaaaaaaa },
 139         { _MMIO(0x2720), 0x00000000 },
 140         { _MMIO(0x2724), 0x00800000 },
 141         { _MMIO(0x2728), 0xaaaaaaaa },
 142         { _MMIO(0x272c), 0xaaaaaaaa },
 143         { _MMIO(0x2740), 0x00000000 },
 144         { _MMIO(0x2744), 0x00000000 },
 145         { _MMIO(0x2748), 0x00000000 },
 146         { _MMIO(0x274c), 0x00000000 },
 147         { _MMIO(0x2750), 0x00000000 },
 148         { _MMIO(0x2754), 0x00000000 },
 149         { _MMIO(0x2758), 0x00000000 },
 150         { _MMIO(0x275c), 0x00000000 },
 151         { _MMIO(0x236c), 0x00000000 },
 152 };
 153
 154 static const struct i915_oa_reg flex_eu_config_compute_basic[] = {
 155 };
 156
 157 static const struct i915_oa_reg mux_config_compute_basic[] = {
 158         { _MMIO(0x253a4), 0x00000000 },
 159         { _MMIO(0x2681c), 0x01f00800 },
 160         { _MMIO(0x26820), 0x00001000 },
 161         { _MMIO(0x2781c), 0x01f00800 },
 162         { _MMIO(0x26520), 0x00000007 },
 163         { _MMIO(0x265a0), 0x00000007 },
 164         { _MMIO(0x25380), 0x00000010 },
 165         { _MMIO(0x2538c), 0x00300000 },
 166         { _MMIO(0x25384), 0xaa8aaaaa },
 167         { _MMIO(0x25404), 0xffffffff },
 168         { _MMIO(0x26800), 0x00004202 },
 169         { _MMIO(0x26808), 0x00605817 },
 170         { _MMIO(0x2680c), 0x10001005 },
 171         { _MMIO(0x26804), 0x00000000 },
 172         { _MMIO(0x27800), 0x00000102 },
 173         { _MMIO(0x27808), 0x0c0701e0 },
 174         { _MMIO(0x2780c), 0x000200a0 },
 175         { _MMIO(0x27804), 0x00000000 },
 176         { _MMIO(0x26484), 0x44000000 },
 177         { _MMIO(0x26704), 0x44000000 },
 178         { _MMIO(0x26500), 0x00000006 },
 179         { _MMIO(0x26510), 0x00000001 },
 180         { _MMIO(0x26504), 0x88000000 },
 181         { _MMIO(0x26580), 0x00000006 },
 182         { _MMIO(0x26590), 0x00000020 },
 183         { _MMIO(0x26584), 0x00000000 },
 184         { _MMIO(0x26104), 0x55822222 },
 185         { _MMIO(0x26184), 0xaa866666 },
 186         { _MMIO(0x25420), 0x08320c83 },
 187         { _MMIO(0x25424), 0x06820c83 },
 188         { _MMIO(0x2541c), 0x00000000 },
 189         { _MMIO(0x25428), 0x00000c03 },
 190 };
 191
 192 static int
 193 get_compute_basic_mux_config(struct drm_i915_private *dev_priv,
 194                              const struct i915_oa_reg **regs,
 195                              int *lens)
 196 {
 197         int n = 0;
 198
 199         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
 200         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
 201
 202         regs[n] = mux_config_compute_basic;
 203         lens[n] = ARRAY_SIZE(mux_config_compute_basic);
 204         n++;
 205
 206         return n;
 207 }
 208
 209 static const struct i915_oa_reg b_counter_config_compute_extended[] = {
 210         { _MMIO(0x2724), 0xf0800000 },
 211         { _MMIO(0x2720), 0x00000000 },
 212         { _MMIO(0x2714), 0xf0800000 },
 213         { _MMIO(0x2710), 0x00000000 },
 214         { _MMIO(0x2770), 0x0007fe2a },
 215         { _MMIO(0x2774), 0x0000ff00 },
 216         { _MMIO(0x2778), 0x0007fe6a },
 217         { _MMIO(0x277c), 0x0000ff00 },
 218         { _MMIO(0x2780), 0x0007fe92 },
 219         { _MMIO(0x2784), 0x0000ff00 },
 220         { _MMIO(0x2788), 0x0007fea2 },
 221         { _MMIO(0x278c), 0x0000ff00 },
 222         { _MMIO(0x2790), 0x0007fe32 },
 223         { _MMIO(0x2794), 0x0000ff00 },
 224         { _MMIO(0x2798), 0x0007fe9a },
 225         { _MMIO(0x279c), 0x0000ff00 },
 226         { _MMIO(0x27a0), 0x0007ff23 },
 227         { _MMIO(0x27a4), 0x0000ff00 },
 228         { _MMIO(0x27a8), 0x0007fff3 },
 229         { _MMIO(0x27ac), 0x0000fffe },
 230 };
 231
 232 static const struct i915_oa_reg flex_eu_config_compute_extended[] = {
 233 };
 234
 235 static const struct i915_oa_reg mux_config_compute_extended[] = {
 236         { _MMIO(0x2681c), 0x3eb00800 },
 237         { _MMIO(0x26820), 0x00900000 },
 238         { _MMIO(0x25384), 0x02aaaaaa },
 239         { _MMIO(0x25404), 0x03ffffff },
 240         { _MMIO(0x26800), 0x00142284 },
 241         { _MMIO(0x26808), 0x0e629062 },
 242         { _MMIO(0x2680c), 0x3f6f55cb },
 243         { _MMIO(0x26810), 0x00000014 },
 244         { _MMIO(0x26804), 0x00000000 },
 245         { _MMIO(0x26104), 0x02aaaaaa },
 246         { _MMIO(0x26184), 0x02aaaaaa },
 247         { _MMIO(0x25420), 0x00000000 },
 248         { _MMIO(0x25424), 0x00000000 },
 249         { _MMIO(0x2541c), 0x00000000 },
 250         { _MMIO(0x25428), 0x00000000 },
 251 };
 252
 253 static int
 254 get_compute_extended_mux_config(struct drm_i915_private *dev_priv,
 255                                 const struct i915_oa_reg **regs,
 256                                 int *lens)
 257 {
 258         int n = 0;
 259
 260         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
 261         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
 262
 263         regs[n] = mux_config_compute_extended;
 264         lens[n] = ARRAY_SIZE(mux_config_compute_extended);
 265         n++;
 266
 267         return n;
 268 }
 269
 270 static const struct i915_oa_reg b_counter_config_memory_reads[] = {
 271         { _MMIO(0x2724), 0xf0800000 },
 272         { _MMIO(0x2720), 0x00000000 },
 273         { _MMIO(0x2714), 0xf0800000 },
 274         { _MMIO(0x2710), 0x00000000 },
 275         { _MMIO(0x274c), 0x76543298 },
 276         { _MMIO(0x2748), 0x98989898 },
 277         { _MMIO(0x2744), 0x000000e4 },
 278         { _MMIO(0x2740), 0x00000000 },
 279         { _MMIO(0x275c), 0x98a98a98 },
 280         { _MMIO(0x2758), 0x88888888 },
 281         { _MMIO(0x2754), 0x000c5500 },
 282         { _MMIO(0x2750), 0x00000000 },
 283         { _MMIO(0x2770), 0x0007f81a },
 284         { _MMIO(0x2774), 0x0000fc00 },
 285         { _MMIO(0x2778), 0x0007f82a },
 286         { _MMIO(0x277c), 0x0000fc00 },
 287         { _MMIO(0x2780), 0x0007f872 },
 288         { _MMIO(0x2784), 0x0000fc00 },
 289         { _MMIO(0x2788), 0x0007f8ba },
 290         { _MMIO(0x278c), 0x0000fc00 },
 291         { _MMIO(0x2790), 0x0007f87a },
 292         { _MMIO(0x2794), 0x0000fc00 },
 293         { _MMIO(0x2798), 0x0007f8ea },
 294         { _MMIO(0x279c), 0x0000fc00 },
 295         { _MMIO(0x27a0), 0x0007f8e2 },
 296         { _MMIO(0x27a4), 0x0000fc00 },
 297         { _MMIO(0x27a8), 0x0007f8f2 },
 298         { _MMIO(0x27ac), 0x0000fc00 },
 299 };
 300
 301 static const struct i915_oa_reg flex_eu_config_memory_reads[] = {
 302 };
 303
 304 static const struct i915_oa_reg mux_config_memory_reads[] = {
 305         { _MMIO(0x253a4), 0x34300000 },
 306         { _MMIO(0x25440), 0x2d800000 },
 307         { _MMIO(0x25444), 0x00000008 },
 308         { _MMIO(0x25128), 0x0e600000 },
 309         { _MMIO(0x25380), 0x00000450 },
 310         { _MMIO(0x25390), 0x00052c43 },
 311         { _MMIO(0x25384), 0x00000000 },
 312         { _MMIO(0x25400), 0x00006144 },
 313         { _MMIO(0x25408), 0x0a418820 },
 314         { _MMIO(0x2540c), 0x000820e6 },
 315         { _MMIO(0x25404), 0xff500000 },
 316         { _MMIO(0x25100), 0x000005d6 },
 317         { _MMIO(0x2510c), 0x0ef00000 },
 318         { _MMIO(0x25104), 0x00000000 },
 319         { _MMIO(0x25420), 0x02108421 },
 320         { _MMIO(0x25424), 0x00008421 },
 321         { _MMIO(0x2541c), 0x00000000 },
 322         { _MMIO(0x25428), 0x00000000 },
 323 };
 324
 325 static int
 326 get_memory_reads_mux_config(struct drm_i915_private *dev_priv,
 327                             const struct i915_oa_reg **regs,
 328                             int *lens)
 329 {
 330         int n = 0;
 331
 332         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
 333         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
 334
 335         regs[n] = mux_config_memory_reads;
 336         lens[n] = ARRAY_SIZE(mux_config_memory_reads);
 337         n++;
 338
 339         return n;
 340 }
 341
 342 static const struct i915_oa_reg b_counter_config_memory_writes[] = {
 343         { _MMIO(0x2724), 0xf0800000 },
 344         { _MMIO(0x2720), 0x00000000 },
 345         { _MMIO(0x2714), 0xf0800000 },
 346         { _MMIO(0x2710), 0x00000000 },
 347         { _MMIO(0x274c), 0x76543298 },
 348         { _MMIO(0x2748), 0x98989898 },
 349         { _MMIO(0x2744), 0x000000e4 },
 350         { _MMIO(0x2740), 0x00000000 },
 351         { _MMIO(0x275c), 0xbabababa },
 352         { _MMIO(0x2758), 0x88888888 },
 353         { _MMIO(0x2754), 0x000c5500 },
 354         { _MMIO(0x2750), 0x00000000 },
 355         { _MMIO(0x2770), 0x0007f81a },
 356         { _MMIO(0x2774), 0x0000fc00 },
 357         { _MMIO(0x2778), 0x0007f82a },
 358         { _MMIO(0x277c), 0x0000fc00 },
 359         { _MMIO(0x2780), 0x0007f822 },
 360         { _MMIO(0x2784), 0x0000fc00 },
 361         { _MMIO(0x2788), 0x0007f8ba },
 362         { _MMIO(0x278c), 0x0000fc00 },
 363         { _MMIO(0x2790), 0x0007f87a },
 364         { _MMIO(0x2794), 0x0000fc00 },
 365         { _MMIO(0x2798), 0x0007f8ea },
 366         { _MMIO(0x279c), 0x0000fc00 },
 367         { _MMIO(0x27a0), 0x0007f8e2 },
 368         { _MMIO(0x27a4), 0x0000fc00 },
 369         { _MMIO(0x27a8), 0x0007f8f2 },
 370         { _MMIO(0x27ac), 0x0000fc00 },
 371 };
 372
 373 static const struct i915_oa_reg flex_eu_config_memory_writes[] = {
 374 };
 375
 376 static const struct i915_oa_reg mux_config_memory_writes[] = {
 377         { _MMIO(0x253a4), 0x34300000 },
 378         { _MMIO(0x25440), 0x01500000 },
 379         { _MMIO(0x25444), 0x00000120 },
 380         { _MMIO(0x25128), 0x0c200000 },
 381         { _MMIO(0x25380), 0x00000450 },
 382         { _MMIO(0x25390), 0x00052c43 },
 383         { _MMIO(0x25384), 0x00000000 },
 384         { _MMIO(0x25400), 0x00007184 },
 385         { _MMIO(0x25408), 0x0a418820 },
 386         { _MMIO(0x2540c), 0x000820e6 },
 387         { _MMIO(0x25404), 0xff500000 },
 388         { _MMIO(0x25100), 0x000005d6 },
 389         { _MMIO(0x2510c), 0x1e700000 },
 390         { _MMIO(0x25104), 0x00000000 },
 391         { _MMIO(0x25420), 0x02108421 },
 392         { _MMIO(0x25424), 0x00008421 },
 393         { _MMIO(0x2541c), 0x00000000 },
 394         { _MMIO(0x25428), 0x00000000 },
 395 };
 396
 397 static int
 398 get_memory_writes_mux_config(struct drm_i915_private *dev_priv,
 399                              const struct i915_oa_reg **regs,
 400                              int *lens)
 401 {
 402         int n = 0;
 403
 404         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
 405         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
 406
 407         regs[n] = mux_config_memory_writes;
 408         lens[n] = ARRAY_SIZE(mux_config_memory_writes);
 409         n++;
 410
 411         return n;
 412 }
 413
 414 static const struct i915_oa_reg b_counter_config_sampler_balance[] = {
 415         { _MMIO(0x2740), 0x00000000 },
 416         { _MMIO(0x2744), 0x00800000 },
 417         { _MMIO(0x2710), 0x00000000 },
 418         { _MMIO(0x2714), 0x00800000 },
 419         { _MMIO(0x2720), 0x00000000 },
 420         { _MMIO(0x2724), 0x00800000 },
 421 };
 422
 423 static const struct i915_oa_reg flex_eu_config_sampler_balance[] = {
 424 };
 425
 426 static const struct i915_oa_reg mux_config_sampler_balance[] = {
 427         { _MMIO(0x2eb9c), 0x01906400 },
 428         { _MMIO(0x2fb9c), 0x01906400 },
 429         { _MMIO(0x253a4), 0x00000000 },
 430         { _MMIO(0x26b9c), 0x01906400 },
 431         { _MMIO(0x27b9c), 0x01906400 },
 432         { _MMIO(0x27104), 0x00a00000 },
 433         { _MMIO(0x27184), 0x00a50000 },
 434         { _MMIO(0x2e804), 0x00500000 },
 435         { _MMIO(0x2e984), 0x00500000 },
 436         { _MMIO(0x2eb04), 0x00500000 },
 437         { _MMIO(0x2eb80), 0x00000084 },
 438         { _MMIO(0x2eb8c), 0x14200000 },
 439         { _MMIO(0x2eb84), 0x00000000 },
 440         { _MMIO(0x2f804), 0x00050000 },
 441         { _MMIO(0x2f984), 0x00050000 },
 442         { _MMIO(0x2fb04), 0x00050000 },
 443         { _MMIO(0x2fb80), 0x00000084 },
 444         { _MMIO(0x2fb8c), 0x00050800 },
 445         { _MMIO(0x2fb84), 0x00000000 },
 446         { _MMIO(0x25380), 0x00000010 },
 447         { _MMIO(0x2538c), 0x000000c0 },
 448         { _MMIO(0x25384), 0xaa550000 },
 449         { _MMIO(0x25404), 0xffffc000 },
 450         { _MMIO(0x26804), 0x50000000 },
 451         { _MMIO(0x26984), 0x50000000 },
 452         { _MMIO(0x26b04), 0x50000000 },
 453         { _MMIO(0x26b80), 0x00000084 },
 454         { _MMIO(0x26b90), 0x00050800 },
 455         { _MMIO(0x26b84), 0x00000000 },
 456         { _MMIO(0x27804), 0x05000000 },
 457         { _MMIO(0x27984), 0x05000000 },
 458         { _MMIO(0x27b04), 0x05000000 },
 459         { _MMIO(0x27b80), 0x00000084 },
 460         { _MMIO(0x27b90), 0x00000142 },
 461         { _MMIO(0x27b84), 0x00000000 },
 462         { _MMIO(0x26104), 0xa0000000 },
 463         { _MMIO(0x26184), 0xa5000000 },
 464         { _MMIO(0x25424), 0x00008620 },
 465         { _MMIO(0x2541c), 0x00000000 },
 466         { _MMIO(0x25428), 0x0004a54a },
 467 };
 468
 469 static int
 470 get_sampler_balance_mux_config(struct drm_i915_private *dev_priv,
 471                                const struct i915_oa_reg **regs,
 472                                int *lens)
 473 {
 474         int n = 0;
 475
 476         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
 477         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
 478
 479         regs[n] = mux_config_sampler_balance;
 480         lens[n] = ARRAY_SIZE(mux_config_sampler_balance);
 481         n++;
 482
 483         return n;
 484 }
 485
 486 int i915_oa_select_metric_set_hsw(struct drm_i915_private *dev_priv)
 487 {
 488         dev_priv->perf.oa.n_mux_configs = 0;
 489         dev_priv->perf.oa.b_counter_regs = NULL;
 490         dev_priv->perf.oa.b_counter_regs_len = 0;
 491
 492         switch (dev_priv->perf.oa.metrics_set) {
 493         case METRIC_SET_ID_RENDER_BASIC:
 494                 dev_priv->perf.oa.n_mux_configs =
 495                         get_render_basic_mux_config(dev_priv,
 496                                                     dev_priv->perf.oa.mux_regs,
 497                                                     dev_priv->perf.oa.mux_regs_lens);
 498                 if (dev_priv->perf.oa.n_mux_configs == 0) {
 499                         DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_BASIC\" metric set\n");
 500
 501                         /* EINVAL because *_register_sysfs already checked this
 502                          * and so it wouldn't have been advertised to userspace and
 503                          * so shouldn't have been requested
 504                          */
 505                         return -EINVAL;
 506                 }
 507
 508                 dev_priv->perf.oa.b_counter_regs =
 509                         b_counter_config_render_basic;
 510                 dev_priv->perf.oa.b_counter_regs_len =
 511                         ARRAY_SIZE(b_counter_config_render_basic);
 512
 513                 dev_priv->perf.oa.flex_regs =
 514                         flex_eu_config_render_basic;
 515                 dev_priv->perf.oa.flex_regs_len =
 516                         ARRAY_SIZE(flex_eu_config_render_basic);
 517
 518                 return 0;
 519         case METRIC_SET_ID_COMPUTE_BASIC:
 520                 dev_priv->perf.oa.n_mux_configs =
 521                         get_compute_basic_mux_config(dev_priv,
 522                                                      dev_priv->perf.oa.mux_regs,
 523                                                      dev_priv->perf.oa.mux_regs_lens);
 524                 if (dev_priv->perf.oa.n_mux_configs == 0) {
 525                         DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_BASIC\" metric set\n");
 526
 527                         /* EINVAL because *_register_sysfs already checked this
 528                          * and so it wouldn't have been advertised to userspace and
 529                          * so shouldn't have been requested
 530                          */
 531                         return -EINVAL;
 532                 }
 533
 534                 dev_priv->perf.oa.b_counter_regs =
 535                         b_counter_config_compute_basic;
 536                 dev_priv->perf.oa.b_counter_regs_len =
 537                         ARRAY_SIZE(b_counter_config_compute_basic);
 538
 539                 dev_priv->perf.oa.flex_regs =
 540                         flex_eu_config_compute_basic;
 541                 dev_priv->perf.oa.flex_regs_len =
 542                         ARRAY_SIZE(flex_eu_config_compute_basic);
 543
 544                 return 0;
 545         case METRIC_SET_ID_COMPUTE_EXTENDED:
 546                 dev_priv->perf.oa.n_mux_configs =
 547                         get_compute_extended_mux_config(dev_priv,
 548                                                         dev_priv->perf.oa.mux_regs,
 549                                                         dev_priv->perf.oa.mux_regs_lens);
 550                 if (dev_priv->perf.oa.n_mux_configs == 0) {
 551                         DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTENDED\" metric set\n");
 552
 553                         /* EINVAL because *_register_sysfs already checked this
 554                          * and so it wouldn't have been advertised to userspace and
 555                          * so shouldn't have been requested
 556                          */
 557                         return -EINVAL;
 558                 }
 559
 560                 dev_priv->perf.oa.b_counter_regs =
 561                         b_counter_config_compute_extended;
 562                 dev_priv->perf.oa.b_counter_regs_len =
 563                         ARRAY_SIZE(b_counter_config_compute_extended);
 564
 565                 dev_priv->perf.oa.flex_regs =
 566                         flex_eu_config_compute_extended;
 567                 dev_priv->perf.oa.flex_regs_len =
 568                         ARRAY_SIZE(flex_eu_config_compute_extended);
 569
 570                 return 0;
 571         case METRIC_SET_ID_MEMORY_READS:
 572                 dev_priv->perf.oa.n_mux_configs =
 573                         get_memory_reads_mux_config(dev_priv,
 574                                                     dev_priv->perf.oa.mux_regs,
 575                                                     dev_priv->perf.oa.mux_regs_lens);
 576                 if (dev_priv->perf.oa.n_mux_configs == 0) {
 577                         DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_READS\" metric set\n");
 578
 579                         /* EINVAL because *_register_sysfs already checked this
 580                          * and so it wouldn't have been advertised to userspace and
 581                          * so shouldn't have been requested
 582                          */
 583                         return -EINVAL;
 584                 }
 585
 586                 dev_priv->perf.oa.b_counter_regs =
 587                         b_counter_config_memory_reads;
 588                 dev_priv->perf.oa.b_counter_regs_len =
 589                         ARRAY_SIZE(b_counter_config_memory_reads);
 590
 591                 dev_priv->perf.oa.flex_regs =
 592                         flex_eu_config_memory_reads;
 593                 dev_priv->perf.oa.flex_regs_len =
 594                         ARRAY_SIZE(flex_eu_config_memory_reads);
 595
 596                 return 0;
 597         case METRIC_SET_ID_MEMORY_WRITES:
 598                 dev_priv->perf.oa.n_mux_configs =
 599                         get_memory_writes_mux_config(dev_priv,
 600                                                      dev_priv->perf.oa.mux_regs,
 601                                                      dev_priv->perf.oa.mux_regs_lens);
 602                 if (dev_priv->perf.oa.n_mux_configs == 0) {
 603                         DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_WRITES\" metric set\n");
 604
 605                         /* EINVAL because *_register_sysfs already checked this
 606                          * and so it wouldn't have been advertised to userspace and
 607                          * so shouldn't have been requested
 608                          */
 609                         return -EINVAL;
 610                 }
 611
 612                 dev_priv->perf.oa.b_counter_regs =
 613                         b_counter_config_memory_writes;
 614                 dev_priv->perf.oa.b_counter_regs_len =
 615                         ARRAY_SIZE(b_counter_config_memory_writes);
 616
 617                 dev_priv->perf.oa.flex_regs =
 618                         flex_eu_config_memory_writes;
 619                 dev_priv->perf.oa.flex_regs_len =
 620                         ARRAY_SIZE(flex_eu_config_memory_writes);
 621
 622                 return 0;
 623         case METRIC_SET_ID_SAMPLER_BALANCE:
 624                 dev_priv->perf.oa.n_mux_configs =
 625                         get_sampler_balance_mux_config(dev_priv,
 626                                                        dev_priv->perf.oa.mux_regs,
 627                                                        dev_priv->perf.oa.mux_regs_lens);
 628                 if (dev_priv->perf.oa.n_mux_configs == 0) {
 629                         DRM_DEBUG_DRIVER("No suitable MUX config for \"SAMPLER_BALANCE\" metric set\n");
 630
 631                         /* EINVAL because *_register_sysfs already checked this
 632                          * and so it wouldn't have been advertised to userspace and
 633                          * so shouldn't have been requested
 634                          */
 635                         return -EINVAL;
 636                 }
 637
 638                 dev_priv->perf.oa.b_counter_regs =
 639                         b_counter_config_sampler_balance;
 640                 dev_priv->perf.oa.b_counter_regs_len =
 641                         ARRAY_SIZE(b_counter_config_sampler_balance);
 642
 643                 dev_priv->perf.oa.flex_regs =
 644                         flex_eu_config_sampler_balance;
 645                 dev_priv->perf.oa.flex_regs_len =
 646                         ARRAY_SIZE(flex_eu_config_sampler_balance);
 647
 648                 return 0;
 649         default:
 650                 return -ENODEV;
 651         }
 652 }
 653
 654 static ssize_t
 655 show_render_basic_id(struct device *kdev, struct device_attribute *attr, char *buf)
 656 {
 657         return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_BASIC);
 658 }
 659
 660 static struct device_attribute dev_attr_render_basic_id = {
 661         .attr = { .name = "id", .mode = 0444 },
 662         .show = show_render_basic_id,
 663         .store = NULL,
 664 };
 665
 666 static struct attribute *attrs_render_basic[] = {
 667         &dev_attr_render_basic_id.attr,
 668         NULL,
 669 };
 670
 671 static struct attribute_group group_render_basic = {
 672         .name = "403d8832-1a27-4aa6-a64e-f5389ce7b212",
 673         .attrs =  attrs_render_basic,
 674 };
 675
 676 static ssize_t
 677 show_compute_basic_id(struct device *kdev, struct device_attribute *attr, char *buf)
 678 {
 679         return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_BASIC);
 680 }
 681
 682 static struct device_attribute dev_attr_compute_basic_id = {
 683         .attr = { .name = "id", .mode = 0444 },
 684         .show = show_compute_basic_id,
 685         .store = NULL,
 686 };
 687
 688 static struct attribute *attrs_compute_basic[] = {
 689         &dev_attr_compute_basic_id.attr,
 690         NULL,
 691 };
 692
 693 static struct attribute_group group_compute_basic = {
 694         .name = "39ad14bc-2380-45c4-91eb-fbcb3aa7ae7b",
 695         .attrs =  attrs_compute_basic,
 696 };
 697
 698 static ssize_t
 699 show_compute_extended_id(struct device *kdev, struct device_attribute *attr, char *buf)
 700 {
 701         return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTENDED);
 702 }
 703
 704 static struct device_attribute dev_attr_compute_extended_id = {
 705         .attr = { .name = "id", .mode = 0444 },
 706         .show = show_compute_extended_id,
 707         .store = NULL,
 708 };
 709
 710 static struct attribute *attrs_compute_extended[] = {
 711         &dev_attr_compute_extended_id.attr,
 712         NULL,
 713 };
 714
 715 static struct attribute_group group_compute_extended = {
 716         .name = "3865be28-6982-49fe-9494-e4d1b4795413",
 717         .attrs =  attrs_compute_extended,
 718 };
 719
 720 static ssize_t
 721 show_memory_reads_id(struct device *kdev, struct device_attribute *attr, char *buf)
 722 {
 723         return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_READS);
 724 }
 725
 726 static struct device_attribute dev_attr_memory_reads_id = {
 727         .attr = { .name = "id", .mode = 0444 },
 728         .show = show_memory_reads_id,
 729         .store = NULL,
 730 };
 731
 732 static struct attribute *attrs_memory_reads[] = {
 733         &dev_attr_memory_reads_id.attr,
 734         NULL,
 735 };
 736
 737 static struct attribute_group group_memory_reads = {
 738         .name = "bb5ed49b-2497-4095-94f6-26ba294db88a",
 739         .attrs =  attrs_memory_reads,
 740 };
 741
 742 static ssize_t
 743 show_memory_writes_id(struct device *kdev, struct device_attribute *attr, char *buf)
 744 {
 745         return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_WRITES);
 746 }
 747
 748 static struct device_attribute dev_attr_memory_writes_id = {
 749         .attr = { .name = "id", .mode = 0444 },
 750         .show = show_memory_writes_id,
 751         .store = NULL,
 752 };
 753
 754 static struct attribute *attrs_memory_writes[] = {
 755         &dev_attr_memory_writes_id.attr,
 756         NULL,
 757 };
 758
 759 static struct attribute_group group_memory_writes = {
 760         .name = "3358d639-9b5f-45ab-976d-9b08cbfc6240",
 761         .attrs =  attrs_memory_writes,
 762 };
 763
 764 static ssize_t
 765 show_sampler_balance_id(struct device *kdev, struct device_attribute *attr, char *buf)
 766 {
 767         return sprintf(buf, "%d\n", METRIC_SET_ID_SAMPLER_BALANCE);
 768 }
 769
 770 static struct device_attribute dev_attr_sampler_balance_id = {
 771         .attr = { .name = "id", .mode = 0444 },
 772         .show = show_sampler_balance_id,
 773         .store = NULL,
 774 };
 775
 776 static struct attribute *attrs_sampler_balance[] = {
 777         &dev_attr_sampler_balance_id.attr,
 778         NULL,
 779 };
 780
 781 static struct attribute_group group_sampler_balance = {
 782         .name = "bc274488-b4b6-40c7-90da-b77d7ad16189",
 783         .attrs =  attrs_sampler_balance,
 784 };
 785
 786 int
 787 i915_perf_register_sysfs_hsw(struct drm_i915_private *dev_priv)
 788 {
 789         const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)];
 790         int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)];
 791         int ret = 0;
 792
 793         if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) {
 794                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_basic);
 795                 if (ret)
 796                         goto error_render_basic;
 797         }
 798         if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) {
 799                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_basic);
 800                 if (ret)
 801                         goto error_compute_basic;
 802         }
 803         if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) {
 804                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extended);
 805                 if (ret)
 806                         goto error_compute_extended;
 807         }
 808         if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) {
 809                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_reads);
 810                 if (ret)
 811                         goto error_memory_reads;
 812         }
 813         if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) {
 814                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_writes);
 815                 if (ret)
 816                         goto error_memory_writes;
 817         }
 818         if (get_sampler_balance_mux_config(dev_priv, mux_regs, mux_lens)) {
 819                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_sampler_balance);
 820                 if (ret)
 821                         goto error_sampler_balance;
 822         }
 823
 824         return 0;
 825
 826 error_sampler_balance:
 827         if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens))
 828                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes);
 829 error_memory_writes:
 830         if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens))
 831                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads);
 832 error_memory_reads:
 833         if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens))
 834                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended);
 835 error_compute_extended:
 836         if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens))
 837                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic);
 838 error_compute_basic:
 839         if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens))
 840                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic);
 841 error_render_basic:
 842         return ret;
 843 }
 844
 845 void
 846 i915_perf_unregister_sysfs_hsw(struct drm_i915_private *dev_priv)
 847 {
 848         const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)];
 849         int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)];
 850
 851         if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens))
 852                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic);
 853         if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens))
 854                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic);
 855         if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens))
 856                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended);
 857         if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens))
 858                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads);
 859         if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens))
 860                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes);
 861         if (get_sampler_balance_mux_config(dev_priv, mux_regs, mux_lens))
 862                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler_balance);
 863 }