drivers/gpu/drm/i915/intel_cdclk.c

   1 /*
   2  * Copyright © 2006-2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "intel_drv.h"
  25
  26 /**
  27  * DOC: CDCLK / RAWCLK
  28  *
  29  * The display engine uses several different clocks to do its work. There
  30  * are two main clocks involved that aren't directly related to the actual
  31  * pixel clock or any symbol/bit clock of the actual output port. These
  32  * are the core display clock (CDCLK) and RAWCLK.
  33  *
  34  * CDCLK clocks most of the display pipe logic, and thus its frequency
  35  * must be high enough to support the rate at which pixels are flowing
  36  * through the pipes. Downscaling must also be accounted as that increases
  37  * the effective pixel rate.
  38  *
  39  * On several platforms the CDCLK frequency can be changed dynamically
  40  * to minimize power consumption for a given display configuration.
  41  * Typically changes to the CDCLK frequency require all the display pipes
  42  * to be shut down while the frequency is being changed.
  43  *
  44  * On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit.
  45  * DMC will not change the active CDCLK frequency however, so that part
  46  * will still be performed by the driver directly.
  47  *
  48  * RAWCLK is a fixed frequency clock, often used by various auxiliary
  49  * blocks such as AUX CH or backlight PWM. Hence the only thing we
  50  * really need to know about RAWCLK is its frequency so that various
  51  * dividers can be programmed correctly.
  52  */
  53
  54 static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv,
  55                                    struct intel_cdclk_state *cdclk_state)
  56 {
  57         cdclk_state->cdclk = 133333;
  58 }
  59
  60 static void fixed_200mhz_get_cdclk(struct drm_i915_private *dev_priv,
  61                                    struct intel_cdclk_state *cdclk_state)
  62 {
  63         cdclk_state->cdclk = 200000;
  64 }
  65
  66 static void fixed_266mhz_get_cdclk(struct drm_i915_private *dev_priv,
  67                                    struct intel_cdclk_state *cdclk_state)
  68 {
  69         cdclk_state->cdclk = 266667;
  70 }
  71
  72 static void fixed_333mhz_get_cdclk(struct drm_i915_private *dev_priv,
  73                                    struct intel_cdclk_state *cdclk_state)
  74 {
  75         cdclk_state->cdclk = 333333;
  76 }
  77
  78 static void fixed_400mhz_get_cdclk(struct drm_i915_private *dev_priv,
  79                                    struct intel_cdclk_state *cdclk_state)
  80 {
  81         cdclk_state->cdclk = 400000;
  82 }
  83
  84 static void fixed_450mhz_get_cdclk(struct drm_i915_private *dev_priv,
  85                                    struct intel_cdclk_state *cdclk_state)
  86 {
  87         cdclk_state->cdclk = 450000;
  88 }
  89
  90 static void i85x_get_cdclk(struct drm_i915_private *dev_priv,
  91                            struct intel_cdclk_state *cdclk_state)
  92 {
  93         struct pci_dev *pdev = dev_priv->drm.pdev;
  94         u16 hpllcc = 0;
  95
  96         /*
  97          * 852GM/852GMV only supports 133 MHz and the HPLLCC
  98          * encoding is different :(
  99          * FIXME is this the right way to detect 852GM/852GMV?
 100          */
 101         if (pdev->revision == 0x1) {
 102                 cdclk_state->cdclk = 133333;
 103                 return;
 104         }
 105
 106         pci_bus_read_config_word(pdev->bus,
 107                                  PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
 108
 109         /* Assume that the hardware is in the high speed state.  This
 110          * should be the default.
 111          */
 112         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
 113         case GC_CLOCK_133_200:
 114         case GC_CLOCK_133_200_2:
 115         case GC_CLOCK_100_200:
 116                 cdclk_state->cdclk = 200000;
 117                 break;
 118         case GC_CLOCK_166_250:
 119                 cdclk_state->cdclk = 250000;
 120                 break;
 121         case GC_CLOCK_100_133:
 122                 cdclk_state->cdclk = 133333;
 123                 break;
 124         case GC_CLOCK_133_266:
 125         case GC_CLOCK_133_266_2:
 126         case GC_CLOCK_166_266:
 127                 cdclk_state->cdclk = 266667;
 128                 break;
 129         }
 130 }
 131
 132 static void i915gm_get_cdclk(struct drm_i915_private *dev_priv,
 133                              struct intel_cdclk_state *cdclk_state)
 134 {
 135         struct pci_dev *pdev = dev_priv->drm.pdev;
 136         u16 gcfgc = 0;
 137
 138         pci_read_config_word(pdev, GCFGC, &gcfgc);
 139
 140         if (gcfgc & GC_LOW_FREQUENCY_ENABLE) {
 141                 cdclk_state->cdclk = 133333;
 142                 return;
 143         }
 144
 145         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
 146         case GC_DISPLAY_CLOCK_333_320_MHZ:
 147                 cdclk_state->cdclk = 333333;
 148                 break;
 149         default:
 150         case GC_DISPLAY_CLOCK_190_200_MHZ:
 151                 cdclk_state->cdclk = 190000;
 152                 break;
 153         }
 154 }
 155
 156 static void i945gm_get_cdclk(struct drm_i915_private *dev_priv,
 157                              struct intel_cdclk_state *cdclk_state)
 158 {
 159         struct pci_dev *pdev = dev_priv->drm.pdev;
 160         u16 gcfgc = 0;
 161
 162         pci_read_config_word(pdev, GCFGC, &gcfgc);
 163
 164         if (gcfgc & GC_LOW_FREQUENCY_ENABLE) {
 165                 cdclk_state->cdclk = 133333;
 166                 return;
 167         }
 168
 169         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
 170         case GC_DISPLAY_CLOCK_333_320_MHZ:
 171                 cdclk_state->cdclk = 320000;
 172                 break;
 173         default:
 174         case GC_DISPLAY_CLOCK_190_200_MHZ:
 175                 cdclk_state->cdclk = 200000;
 176                 break;
 177         }
 178 }
 179
 180 static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv)
 181 {
 182         static const unsigned int blb_vco[8] = {
 183                 [0] = 3200000,
 184                 [1] = 4000000,
 185                 [2] = 5333333,
 186                 [3] = 4800000,
 187                 [4] = 6400000,
 188         };
 189         static const unsigned int pnv_vco[8] = {
 190                 [0] = 3200000,
 191                 [1] = 4000000,
 192                 [2] = 5333333,
 193                 [3] = 4800000,
 194                 [4] = 2666667,
 195         };
 196         static const unsigned int cl_vco[8] = {
 197                 [0] = 3200000,
 198                 [1] = 4000000,
 199                 [2] = 5333333,
 200                 [3] = 6400000,
 201                 [4] = 3333333,
 202                 [5] = 3566667,
 203                 [6] = 4266667,
 204         };
 205         static const unsigned int elk_vco[8] = {
 206                 [0] = 3200000,
 207                 [1] = 4000000,
 208                 [2] = 5333333,
 209                 [3] = 4800000,
 210         };
 211         static const unsigned int ctg_vco[8] = {
 212                 [0] = 3200000,
 213                 [1] = 4000000,
 214                 [2] = 5333333,
 215                 [3] = 6400000,
 216                 [4] = 2666667,
 217                 [5] = 4266667,
 218         };
 219         const unsigned int *vco_table;
 220         unsigned int vco;
 221         uint8_t tmp = 0;
 222
 223         /* FIXME other chipsets? */
 224         if (IS_GM45(dev_priv))
 225                 vco_table = ctg_vco;
 226         else if (IS_G45(dev_priv))
 227                 vco_table = elk_vco;
 228         else if (IS_I965GM(dev_priv))
 229                 vco_table = cl_vco;
 230         else if (IS_PINEVIEW(dev_priv))
 231                 vco_table = pnv_vco;
 232         else if (IS_G33(dev_priv))
 233                 vco_table = blb_vco;
 234         else
 235                 return 0;
 236
 237         tmp = I915_READ(IS_MOBILE(dev_priv) ? HPLLVCO_MOBILE : HPLLVCO);
 238
 239         vco = vco_table[tmp & 0x7];
 240         if (vco == 0)
 241                 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
 242         else
 243                 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
 244
 245         return vco;
 246 }
 247
 248 static void g33_get_cdclk(struct drm_i915_private *dev_priv,
 249                           struct intel_cdclk_state *cdclk_state)
 250 {
 251         struct pci_dev *pdev = dev_priv->drm.pdev;
 252         static const uint8_t div_3200[] = { 12, 10,  8,  7, 5, 16 };
 253         static const uint8_t div_4000[] = { 14, 12, 10,  8, 6, 20 };
 254         static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
 255         static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
 256         const uint8_t *div_table;
 257         unsigned int cdclk_sel;
 258         uint16_t tmp = 0;
 259
 260         cdclk_state->vco = intel_hpll_vco(dev_priv);
 261
 262         pci_read_config_word(pdev, GCFGC, &tmp);
 263
 264         cdclk_sel = (tmp >> 4) & 0x7;
 265
 266         if (cdclk_sel >= ARRAY_SIZE(div_3200))
 267                 goto fail;
 268
 269         switch (cdclk_state->vco) {
 270         case 3200000:
 271                 div_table = div_3200;
 272                 break;
 273         case 4000000:
 274                 div_table = div_4000;
 275                 break;
 276         case 4800000:
 277                 div_table = div_4800;
 278                 break;
 279         case 5333333:
 280                 div_table = div_5333;
 281                 break;
 282         default:
 283                 goto fail;
 284         }
 285
 286         cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco,
 287                                                div_table[cdclk_sel]);
 288         return;
 289
 290 fail:
 291         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n",
 292                   cdclk_state->vco, tmp);
 293         cdclk_state->cdclk = 190476;
 294 }
 295
 296 static void pnv_get_cdclk(struct drm_i915_private *dev_priv,
 297                           struct intel_cdclk_state *cdclk_state)
 298 {
 299         struct pci_dev *pdev = dev_priv->drm.pdev;
 300         u16 gcfgc = 0;
 301
 302         pci_read_config_word(pdev, GCFGC, &gcfgc);
 303
 304         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
 305         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
 306                 cdclk_state->cdclk = 266667;
 307                 break;
 308         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
 309                 cdclk_state->cdclk = 333333;
 310                 break;
 311         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
 312                 cdclk_state->cdclk = 444444;
 313                 break;
 314         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
 315                 cdclk_state->cdclk = 200000;
 316                 break;
 317         default:
 318                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
 319         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
 320                 cdclk_state->cdclk = 133333;
 321                 break;
 322         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
 323                 cdclk_state->cdclk = 166667;
 324                 break;
 325         }
 326 }
 327
 328 static void i965gm_get_cdclk(struct drm_i915_private *dev_priv,
 329                              struct intel_cdclk_state *cdclk_state)
 330 {
 331         struct pci_dev *pdev = dev_priv->drm.pdev;
 332         static const uint8_t div_3200[] = { 16, 10,  8 };
 333         static const uint8_t div_4000[] = { 20, 12, 10 };
 334         static const uint8_t div_5333[] = { 24, 16, 14 };
 335         const uint8_t *div_table;
 336         unsigned int cdclk_sel;
 337         uint16_t tmp = 0;
 338
 339         cdclk_state->vco = intel_hpll_vco(dev_priv);
 340
 341         pci_read_config_word(pdev, GCFGC, &tmp);
 342
 343         cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
 344
 345         if (cdclk_sel >= ARRAY_SIZE(div_3200))
 346                 goto fail;
 347
 348         switch (cdclk_state->vco) {
 349         case 3200000:
 350                 div_table = div_3200;
 351                 break;
 352         case 4000000:
 353                 div_table = div_4000;
 354                 break;
 355         case 5333333:
 356                 div_table = div_5333;
 357                 break;
 358         default:
 359                 goto fail;
 360         }
 361
 362         cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco,
 363                                                div_table[cdclk_sel]);
 364         return;
 365
 366 fail:
 367         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n",
 368                   cdclk_state->vco, tmp);
 369         cdclk_state->cdclk = 200000;
 370 }
 371
 372 static void gm45_get_cdclk(struct drm_i915_private *dev_priv,
 373                            struct intel_cdclk_state *cdclk_state)
 374 {
 375         struct pci_dev *pdev = dev_priv->drm.pdev;
 376         unsigned int cdclk_sel;
 377         uint16_t tmp = 0;
 378
 379         cdclk_state->vco = intel_hpll_vco(dev_priv);
 380
 381         pci_read_config_word(pdev, GCFGC, &tmp);
 382
 383         cdclk_sel = (tmp >> 12) & 0x1;
 384
 385         switch (cdclk_state->vco) {
 386         case 2666667:
 387         case 4000000:
 388         case 5333333:
 389                 cdclk_state->cdclk = cdclk_sel ? 333333 : 222222;
 390                 break;
 391         case 3200000:
 392                 cdclk_state->cdclk = cdclk_sel ? 320000 : 228571;
 393                 break;
 394         default:
 395                 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n",
 396                           cdclk_state->vco, tmp);
 397                 cdclk_state->cdclk = 222222;
 398                 break;
 399         }
 400 }
 401
 402 static void hsw_get_cdclk(struct drm_i915_private *dev_priv,
 403                           struct intel_cdclk_state *cdclk_state)
 404 {
 405         uint32_t lcpll = I915_READ(LCPLL_CTL);
 406         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
 407
 408         if (lcpll & LCPLL_CD_SOURCE_FCLK)
 409                 cdclk_state->cdclk = 800000;
 410         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
 411                 cdclk_state->cdclk = 450000;
 412         else if (freq == LCPLL_CLK_FREQ_450)
 413                 cdclk_state->cdclk = 450000;
 414         else if (IS_HSW_ULT(dev_priv))
 415                 cdclk_state->cdclk = 337500;
 416         else
 417                 cdclk_state->cdclk = 540000;
 418 }
 419
 420 static int vlv_calc_cdclk(struct drm_i915_private *dev_priv,
 421                           int max_pixclk)
 422 {
 423         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ?
 424                 333333 : 320000;
 425         int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
 426
 427         /*
 428          * We seem to get an unstable or solid color picture at 200MHz.
 429          * Not sure what's wrong. For now use 200MHz only when all pipes
 430          * are off.
 431          */
 432         if (!IS_CHERRYVIEW(dev_priv) &&
 433             max_pixclk > freq_320*limit/100)
 434                 return 400000;
 435         else if (max_pixclk > 266667*limit/100)
 436                 return freq_320;
 437         else if (max_pixclk > 0)
 438                 return 266667;
 439         else
 440                 return 200000;
 441 }
 442
 443 static void vlv_get_cdclk(struct drm_i915_private *dev_priv,
 444                           struct intel_cdclk_state *cdclk_state)
 445 {
 446         cdclk_state->vco = vlv_get_hpll_vco(dev_priv);
 447         cdclk_state->cdclk = vlv_get_cck_clock(dev_priv, "cdclk",
 448                                                CCK_DISPLAY_CLOCK_CONTROL,
 449                                                cdclk_state->vco);
 450 }
 451
 452 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
 453 {
 454         unsigned int credits, default_credits;
 455
 456         if (IS_CHERRYVIEW(dev_priv))
 457                 default_credits = PFI_CREDIT(12);
 458         else
 459                 default_credits = PFI_CREDIT(8);
 460
 461         if (dev_priv->cdclk.hw.cdclk >= dev_priv->czclk_freq) {
 462                 /* CHV suggested value is 31 or 63 */
 463                 if (IS_CHERRYVIEW(dev_priv))
 464                         credits = PFI_CREDIT_63;
 465                 else
 466                         credits = PFI_CREDIT(15);
 467         } else {
 468                 credits = default_credits;
 469         }
 470
 471         /*
 472          * WA - write default credits before re-programming
 473          * FIXME: should we also set the resend bit here?
 474          */
 475         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
 476                    default_credits);
 477
 478         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
 479                    credits | PFI_CREDIT_RESEND);
 480
 481         /*
 482          * FIXME is this guaranteed to clear
 483          * immediately or should we poll for it?
 484          */
 485         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
 486 }
 487
 488 static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
 489                           const struct intel_cdclk_state *cdclk_state)
 490 {
 491         int cdclk = cdclk_state->cdclk;
 492         u32 val, cmd;
 493
 494         /* There are cases where we can end up here with power domains
 495          * off and a CDCLK frequency other than the minimum, like when
 496          * issuing a modeset without actually changing any display after
 497          * a system suspend.  So grab the PIPE-A domain, which covers
 498          * the HW blocks needed for the following programming.
 499          */
 500         intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
 501
 502         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
 503                 cmd = 2;
 504         else if (cdclk == 266667)
 505                 cmd = 1;
 506         else
 507                 cmd = 0;
 508
 509         mutex_lock(&dev_priv->rps.hw_lock);
 510         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
 511         val &= ~DSPFREQGUAR_MASK;
 512         val |= (cmd << DSPFREQGUAR_SHIFT);
 513         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
 514         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
 515                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
 516                      50)) {
 517                 DRM_ERROR("timed out waiting for CDclk change\n");
 518         }
 519         mutex_unlock(&dev_priv->rps.hw_lock);
 520
 521         mutex_lock(&dev_priv->sb_lock);
 522
 523         if (cdclk == 400000) {
 524                 u32 divider;
 525
 526                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1,
 527                                             cdclk) - 1;
 528
 529                 /* adjust cdclk divider */
 530                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
 531                 val &= ~CCK_FREQUENCY_VALUES;
 532                 val |= divider;
 533                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
 534
 535                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
 536                               CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
 537                              50))
 538                         DRM_ERROR("timed out waiting for CDclk change\n");
 539         }
 540
 541         /* adjust self-refresh exit latency value */
 542         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
 543         val &= ~0x7f;
 544
 545         /*
 546          * For high bandwidth configs, we set a higher latency in the bunit
 547          * so that the core display fetch happens in time to avoid underruns.
 548          */
 549         if (cdclk == 400000)
 550                 val |= 4500 / 250; /* 4.5 usec */
 551         else
 552                 val |= 3000 / 250; /* 3.0 usec */
 553         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
 554
 555         mutex_unlock(&dev_priv->sb_lock);
 556
 557         intel_update_cdclk(dev_priv);
 558
 559         vlv_program_pfi_credits(dev_priv);
 560
 561         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
 562 }
 563
 564 static void chv_set_cdclk(struct drm_i915_private *dev_priv,
 565                           const struct intel_cdclk_state *cdclk_state)
 566 {
 567         int cdclk = cdclk_state->cdclk;
 568         u32 val, cmd;
 569
 570         switch (cdclk) {
 571         case 333333:
 572         case 320000:
 573         case 266667:
 574         case 200000:
 575                 break;
 576         default:
 577                 MISSING_CASE(cdclk);
 578                 return;
 579         }
 580
 581         /* There are cases where we can end up here with power domains
 582          * off and a CDCLK frequency other than the minimum, like when
 583          * issuing a modeset without actually changing any display after
 584          * a system suspend.  So grab the PIPE-A domain, which covers
 585          * the HW blocks needed for the following programming.
 586          */
 587         intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
 588
 589         /*
 590          * Specs are full of misinformation, but testing on actual
 591          * hardware has shown that we just need to write the desired
 592          * CCK divider into the Punit register.
 593          */
 594         cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
 595
 596         mutex_lock(&dev_priv->rps.hw_lock);
 597         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
 598         val &= ~DSPFREQGUAR_MASK_CHV;
 599         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
 600         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
 601         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
 602                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
 603                      50)) {
 604                 DRM_ERROR("timed out waiting for CDclk change\n");
 605         }
 606         mutex_unlock(&dev_priv->rps.hw_lock);
 607
 608         intel_update_cdclk(dev_priv);
 609
 610         vlv_program_pfi_credits(dev_priv);
 611
 612         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
 613 }
 614
 615 static int bdw_calc_cdclk(int max_pixclk)
 616 {
 617         if (max_pixclk > 540000)
 618                 return 675000;
 619         else if (max_pixclk > 450000)
 620                 return 540000;
 621         else if (max_pixclk > 337500)
 622                 return 450000;
 623         else
 624                 return 337500;
 625 }
 626
 627 static void bdw_get_cdclk(struct drm_i915_private *dev_priv,
 628                           struct intel_cdclk_state *cdclk_state)
 629 {
 630         uint32_t lcpll = I915_READ(LCPLL_CTL);
 631         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
 632
 633         if (lcpll & LCPLL_CD_SOURCE_FCLK)
 634                 cdclk_state->cdclk = 800000;
 635         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
 636                 cdclk_state->cdclk = 450000;
 637         else if (freq == LCPLL_CLK_FREQ_450)
 638                 cdclk_state->cdclk = 450000;
 639         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
 640                 cdclk_state->cdclk = 540000;
 641         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
 642                 cdclk_state->cdclk = 337500;
 643         else
 644                 cdclk_state->cdclk = 675000;
 645 }
 646
 647 static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
 648                           const struct intel_cdclk_state *cdclk_state)
 649 {
 650         int cdclk = cdclk_state->cdclk;
 651         uint32_t val, data;
 652         int ret;
 653
 654         if (WARN((I915_READ(LCPLL_CTL) &
 655                   (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
 656                    LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
 657                    LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
 658                    LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
 659                  "trying to change cdclk frequency with cdclk not enabled\n"))
 660                 return;
 661
 662         mutex_lock(&dev_priv->rps.hw_lock);
 663         ret = sandybridge_pcode_write(dev_priv,
 664                                       BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
 665         mutex_unlock(&dev_priv->rps.hw_lock);
 666         if (ret) {
 667                 DRM_ERROR("failed to inform pcode about cdclk change\n");
 668                 return;
 669         }
 670
 671         val = I915_READ(LCPLL_CTL);
 672         val |= LCPLL_CD_SOURCE_FCLK;
 673         I915_WRITE(LCPLL_CTL, val);
 674
 675         if (wait_for_us(I915_READ(LCPLL_CTL) &
 676                         LCPLL_CD_SOURCE_FCLK_DONE, 1))
 677                 DRM_ERROR("Switching to FCLK failed\n");
 678
 679         val = I915_READ(LCPLL_CTL);
 680         val &= ~LCPLL_CLK_FREQ_MASK;
 681
 682         switch (cdclk) {
 683         case 450000:
 684                 val |= LCPLL_CLK_FREQ_450;
 685                 data = 0;
 686                 break;
 687         case 540000:
 688                 val |= LCPLL_CLK_FREQ_54O_BDW;
 689                 data = 1;
 690                 break;
 691         case 337500:
 692                 val |= LCPLL_CLK_FREQ_337_5_BDW;
 693                 data = 2;
 694                 break;
 695         case 675000:
 696                 val |= LCPLL_CLK_FREQ_675_BDW;
 697                 data = 3;
 698                 break;
 699         default:
 700                 WARN(1, "invalid cdclk frequency\n");
 701                 return;
 702         }
 703
 704         I915_WRITE(LCPLL_CTL, val);
 705
 706         val = I915_READ(LCPLL_CTL);
 707         val &= ~LCPLL_CD_SOURCE_FCLK;
 708         I915_WRITE(LCPLL_CTL, val);
 709
 710         if (wait_for_us((I915_READ(LCPLL_CTL) &
 711                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
 712                 DRM_ERROR("Switching back to LCPLL failed\n");
 713
 714         mutex_lock(&dev_priv->rps.hw_lock);
 715         sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
 716         mutex_unlock(&dev_priv->rps.hw_lock);
 717
 718         I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
 719
 720         intel_update_cdclk(dev_priv);
 721
 722         WARN(cdclk != dev_priv->cdclk.hw.cdclk,
 723              "cdclk requested %d kHz but got %d kHz\n",
 724              cdclk, dev_priv->cdclk.hw.cdclk);
 725 }
 726
 727 static int skl_calc_cdclk(int max_pixclk, int vco)
 728 {
 729         if (vco == 8640000) {
 730                 if (max_pixclk > 540000)
 731                         return 617143;
 732                 else if (max_pixclk > 432000)
 733                         return 540000;
 734                 else if (max_pixclk > 308571)
 735                         return 432000;
 736                 else
 737                         return 308571;
 738         } else {
 739                 if (max_pixclk > 540000)
 740                         return 675000;
 741                 else if (max_pixclk > 450000)
 742                         return 540000;
 743                 else if (max_pixclk > 337500)
 744                         return 450000;
 745                 else
 746                         return 337500;
 747         }
 748 }
 749
 750 static void skl_dpll0_update(struct drm_i915_private *dev_priv,
 751                              struct intel_cdclk_state *cdclk_state)
 752 {
 753         u32 val;
 754
 755         cdclk_state->ref = 24000;
 756         cdclk_state->vco = 0;
 757
 758         val = I915_READ(LCPLL1_CTL);
 759         if ((val & LCPLL_PLL_ENABLE) == 0)
 760                 return;
 761
 762         if (WARN_ON((val & LCPLL_PLL_LOCK) == 0))
 763                 return;
 764
 765         val = I915_READ(DPLL_CTRL1);
 766
 767         if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
 768                             DPLL_CTRL1_SSC(SKL_DPLL0) |
 769                             DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
 770                     DPLL_CTRL1_OVERRIDE(SKL_DPLL0)))
 771                 return;
 772
 773         switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
 774         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
 775         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
 776         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
 777         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
 778                 cdclk_state->vco = 8100000;
 779                 break;
 780         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
 781         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
 782                 cdclk_state->vco = 8640000;
 783                 break;
 784         default:
 785                 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
 786                 break;
 787         }
 788 }
 789
 790 static void skl_get_cdclk(struct drm_i915_private *dev_priv,
 791                           struct intel_cdclk_state *cdclk_state)
 792 {
 793         u32 cdctl;
 794
 795         skl_dpll0_update(dev_priv, cdclk_state);
 796
 797         cdclk_state->cdclk = cdclk_state->ref;
 798
 799         if (cdclk_state->vco == 0)
 800                 return;
 801
 802         cdctl = I915_READ(CDCLK_CTL);
 803
 804         if (cdclk_state->vco == 8640000) {
 805                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
 806                 case CDCLK_FREQ_450_432:
 807                         cdclk_state->cdclk = 432000;
 808                         break;
 809                 case CDCLK_FREQ_337_308:
 810                         cdclk_state->cdclk = 308571;
 811                         break;
 812                 case CDCLK_FREQ_540:
 813                         cdclk_state->cdclk = 540000;
 814                         break;
 815                 case CDCLK_FREQ_675_617:
 816                         cdclk_state->cdclk = 617143;
 817                         break;
 818                 default:
 819                         MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
 820                         break;
 821                 }
 822         } else {
 823                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
 824                 case CDCLK_FREQ_450_432:
 825                         cdclk_state->cdclk = 450000;
 826                         break;
 827                 case CDCLK_FREQ_337_308:
 828                         cdclk_state->cdclk = 337500;
 829                         break;
 830                 case CDCLK_FREQ_540:
 831                         cdclk_state->cdclk = 540000;
 832                         break;
 833                 case CDCLK_FREQ_675_617:
 834                         cdclk_state->cdclk = 675000;
 835                         break;
 836                 default:
 837                         MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
 838                         break;
 839                 }
 840         }
 841 }
 842
 843 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
 844 static int skl_cdclk_decimal(int cdclk)
 845 {
 846         return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
 847 }
 848
 849 static void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv,
 850                                         int vco)
 851 {
 852         bool changed = dev_priv->skl_preferred_vco_freq != vco;
 853
 854         dev_priv->skl_preferred_vco_freq = vco;
 855
 856         if (changed)
 857                 intel_update_max_cdclk(dev_priv);
 858 }
 859
 860 static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
 861 {
 862         int min_cdclk = skl_calc_cdclk(0, vco);
 863         u32 val;
 864
 865         WARN_ON(vco != 8100000 && vco != 8640000);
 866
 867         /* select the minimum CDCLK before enabling DPLL 0 */
 868         val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk);
 869         I915_WRITE(CDCLK_CTL, val);
 870         POSTING_READ(CDCLK_CTL);
 871
 872         /*
 873          * We always enable DPLL0 with the lowest link rate possible, but still
 874          * taking into account the VCO required to operate the eDP panel at the
 875          * desired frequency. The usual DP link rates operate with a VCO of
 876          * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
 877          * The modeset code is responsible for the selection of the exact link
 878          * rate later on, with the constraint of choosing a frequency that
 879          * works with vco.
 880          */
 881         val = I915_READ(DPLL_CTRL1);
 882
 883         val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
 884                  DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
 885         val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
 886         if (vco == 8640000)
 887                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
 888                                             SKL_DPLL0);
 889         else
 890                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
 891                                             SKL_DPLL0);
 892
 893         I915_WRITE(DPLL_CTRL1, val);
 894         POSTING_READ(DPLL_CTRL1);
 895
 896         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
 897
 898         if (intel_wait_for_register(dev_priv,
 899                                     LCPLL1_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
 900                                     5))
 901                 DRM_ERROR("DPLL0 not locked\n");
 902
 903         dev_priv->cdclk.hw.vco = vco;
 904
 905         /* We'll want to keep using the current vco from now on. */
 906         skl_set_preferred_cdclk_vco(dev_priv, vco);
 907 }
 908
 909 static void skl_dpll0_disable(struct drm_i915_private *dev_priv)
 910 {
 911         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
 912         if (intel_wait_for_register(dev_priv,
 913                                    LCPLL1_CTL, LCPLL_PLL_LOCK, 0,
 914                                    1))
 915                 DRM_ERROR("Couldn't disable DPLL0\n");
 916
 917         dev_priv->cdclk.hw.vco = 0;
 918 }
 919
 920 static void skl_set_cdclk(struct drm_i915_private *dev_priv,
 921                           const struct intel_cdclk_state *cdclk_state)
 922 {
 923         int cdclk = cdclk_state->cdclk;
 924         int vco = cdclk_state->vco;
 925         u32 freq_select, pcu_ack;
 926         int ret;
 927
 928         WARN_ON((cdclk == 24000) != (vco == 0));
 929
 930         mutex_lock(&dev_priv->rps.hw_lock);
 931         ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
 932                                 SKL_CDCLK_PREPARE_FOR_CHANGE,
 933                                 SKL_CDCLK_READY_FOR_CHANGE,
 934                                 SKL_CDCLK_READY_FOR_CHANGE, 3);
 935         mutex_unlock(&dev_priv->rps.hw_lock);
 936         if (ret) {
 937                 DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
 938                           ret);
 939                 return;
 940         }
 941
 942         /* set CDCLK_CTL */
 943         switch (cdclk) {
 944         case 450000:
 945         case 432000:
 946                 freq_select = CDCLK_FREQ_450_432;
 947                 pcu_ack = 1;
 948                 break;
 949         case 540000:
 950                 freq_select = CDCLK_FREQ_540;
 951                 pcu_ack = 2;
 952                 break;
 953         case 308571:
 954         case 337500:
 955         default:
 956                 freq_select = CDCLK_FREQ_337_308;
 957                 pcu_ack = 0;
 958                 break;
 959         case 617143:
 960         case 675000:
 961                 freq_select = CDCLK_FREQ_675_617;
 962                 pcu_ack = 3;
 963                 break;
 964         }
 965
 966         if (dev_priv->cdclk.hw.vco != 0 &&
 967             dev_priv->cdclk.hw.vco != vco)
 968                 skl_dpll0_disable(dev_priv);
 969
 970         if (dev_priv->cdclk.hw.vco != vco)
 971                 skl_dpll0_enable(dev_priv, vco);
 972
 973         I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk));
 974         POSTING_READ(CDCLK_CTL);
 975
 976         /* inform PCU of the change */
 977         mutex_lock(&dev_priv->rps.hw_lock);
 978         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
 979         mutex_unlock(&dev_priv->rps.hw_lock);
 980
 981         intel_update_cdclk(dev_priv);
 982 }
 983
 984 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
 985 {
 986         uint32_t cdctl, expected;
 987
 988         /*
 989          * check if the pre-os initialized the display
 990          * There is SWF18 scratchpad register defined which is set by the
 991          * pre-os which can be used by the OS drivers to check the status
 992          */
 993         if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
 994                 goto sanitize;
 995
 996         intel_update_cdclk(dev_priv);
 997         /* Is PLL enabled and locked ? */
 998         if (dev_priv->cdclk.hw.vco == 0 ||
 999             dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.ref)
1000                 goto sanitize;
1001
1002         /* DPLL okay; verify the cdclock
1003          *
1004          * Noticed in some instances that the freq selection is correct but
1005          * decimal part is programmed wrong from BIOS where pre-os does not
1006          * enable display. Verify the same as well.
1007          */
1008         cdctl = I915_READ(CDCLK_CTL);
1009         expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
1010                 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
1011         if (cdctl == expected)
1012                 /* All well; nothing to sanitize */
1013                 return;
1014
1015 sanitize:
1016         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
1017
1018         /* force cdclk programming */
1019         dev_priv->cdclk.hw.cdclk = 0;
1020         /* force full PLL disable + enable */
1021         dev_priv->cdclk.hw.vco = -1;
1022 }
1023
1024 /**
1025  * skl_init_cdclk - Initialize CDCLK on SKL
1026  * @dev_priv: i915 device
1027  *
1028  * Initialize CDCLK for SKL and derivatives. This is generally
1029  * done only during the display core initialization sequence,
1030  * after which the DMC will take care of turning CDCLK off/on
1031  * as needed.
1032  */
1033 void skl_init_cdclk(struct drm_i915_private *dev_priv)
1034 {
1035         struct intel_cdclk_state cdclk_state;
1036
1037         skl_sanitize_cdclk(dev_priv);
1038
1039         if (dev_priv->cdclk.hw.cdclk != 0 &&
1040             dev_priv->cdclk.hw.vco != 0) {
1041                 /*
1042                  * Use the current vco as our initial
1043                  * guess as to what the preferred vco is.
1044                  */
1045                 if (dev_priv->skl_preferred_vco_freq == 0)
1046                         skl_set_preferred_cdclk_vco(dev_priv,
1047                                                     dev_priv->cdclk.hw.vco);
1048                 return;
1049         }
1050
1051         cdclk_state = dev_priv->cdclk.hw;
1052
1053         cdclk_state.vco = dev_priv->skl_preferred_vco_freq;
1054         if (cdclk_state.vco == 0)
1055                 cdclk_state.vco = 8100000;
1056         cdclk_state.cdclk = skl_calc_cdclk(0, cdclk_state.vco);
1057
1058         skl_set_cdclk(dev_priv, &cdclk_state);
1059 }
1060
1061 /**
1062  * skl_uninit_cdclk - Uninitialize CDCLK on SKL
1063  * @dev_priv: i915 device
1064  *
1065  * Uninitialize CDCLK for SKL and derivatives. This is done only
1066  * during the display core uninitialization sequence.
1067  */
1068 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
1069 {
1070         struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
1071
1072         cdclk_state.cdclk = cdclk_state.ref;
1073         cdclk_state.vco = 0;
1074
1075         skl_set_cdclk(dev_priv, &cdclk_state);
1076 }
1077
1078 static int bxt_calc_cdclk(int max_pixclk)
1079 {
1080         if (max_pixclk > 576000)
1081                 return 624000;
1082         else if (max_pixclk > 384000)
1083                 return 576000;
1084         else if (max_pixclk > 288000)
1085                 return 384000;
1086         else if (max_pixclk > 144000)
1087                 return 288000;
1088         else
1089                 return 144000;
1090 }
1091
1092 static int glk_calc_cdclk(int max_pixclk)
1093 {
1094         /*
1095          * FIXME: Avoid using a pixel clock that is more than 99% of the cdclk
1096          * as a temporary workaround. Use a higher cdclk instead. (Note that
1097          * intel_compute_max_dotclk() limits the max pixel clock to 99% of max
1098          * cdclk.)
1099          */
1100         if (max_pixclk > DIV_ROUND_UP(2 * 158400 * 99, 100))
1101                 return 316800;
1102         else if (max_pixclk > DIV_ROUND_UP(2 * 79200 * 99, 100))
1103                 return 158400;
1104         else
1105                 return 79200;
1106 }
1107
1108 static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
1109 {
1110         int ratio;
1111
1112         if (cdclk == dev_priv->cdclk.hw.ref)
1113                 return 0;
1114
1115         switch (cdclk) {
1116         default:
1117                 MISSING_CASE(cdclk);
1118         case 144000:
1119         case 288000:
1120         case 384000:
1121         case 576000:
1122                 ratio = 60;
1123                 break;
1124         case 624000:
1125                 ratio = 65;
1126                 break;
1127         }
1128
1129         return dev_priv->cdclk.hw.ref * ratio;
1130 }
1131
1132 static int glk_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
1133 {
1134         int ratio;
1135
1136         if (cdclk == dev_priv->cdclk.hw.ref)
1137                 return 0;
1138
1139         switch (cdclk) {
1140         default:
1141                 MISSING_CASE(cdclk);
1142         case  79200:
1143         case 158400:
1144         case 316800:
1145                 ratio = 33;
1146                 break;
1147         }
1148
1149         return dev_priv->cdclk.hw.ref * ratio;
1150 }
1151
1152 static void bxt_de_pll_update(struct drm_i915_private *dev_priv,
1153                               struct intel_cdclk_state *cdclk_state)
1154 {
1155         u32 val;
1156
1157         cdclk_state->ref = 19200;
1158         cdclk_state->vco = 0;
1159
1160         val = I915_READ(BXT_DE_PLL_ENABLE);
1161         if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
1162                 return;
1163
1164         if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
1165                 return;
1166
1167         val = I915_READ(BXT_DE_PLL_CTL);
1168         cdclk_state->vco = (val & BXT_DE_PLL_RATIO_MASK) * cdclk_state->ref;
1169 }
1170
1171 static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
1172                           struct intel_cdclk_state *cdclk_state)
1173 {
1174         u32 divider;
1175         int div;
1176
1177         bxt_de_pll_update(dev_priv, cdclk_state);
1178
1179         cdclk_state->cdclk = cdclk_state->ref;
1180
1181         if (cdclk_state->vco == 0)
1182                 return;
1183
1184         divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
1185
1186         switch (divider) {
1187         case BXT_CDCLK_CD2X_DIV_SEL_1:
1188                 div = 2;
1189                 break;
1190         case BXT_CDCLK_CD2X_DIV_SEL_1_5:
1191                 WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n");
1192                 div = 3;
1193                 break;
1194         case BXT_CDCLK_CD2X_DIV_SEL_2:
1195                 div = 4;
1196                 break;
1197         case BXT_CDCLK_CD2X_DIV_SEL_4:
1198                 div = 8;
1199                 break;
1200         default:
1201                 MISSING_CASE(divider);
1202                 return;
1203         }
1204
1205         cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div);
1206 }
1207
1208 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
1209 {
1210         I915_WRITE(BXT_DE_PLL_ENABLE, 0);
1211
1212         /* Timeout 200us */
1213         if (intel_wait_for_register(dev_priv,
1214                                     BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 0,
1215                                     1))
1216                 DRM_ERROR("timeout waiting for DE PLL unlock\n");
1217
1218         dev_priv->cdclk.hw.vco = 0;
1219 }
1220
1221 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
1222 {
1223         int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
1224         u32 val;
1225
1226         val = I915_READ(BXT_DE_PLL_CTL);
1227         val &= ~BXT_DE_PLL_RATIO_MASK;
1228         val |= BXT_DE_PLL_RATIO(ratio);
1229         I915_WRITE(BXT_DE_PLL_CTL, val);
1230
1231         I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
1232
1233         /* Timeout 200us */
1234         if (intel_wait_for_register(dev_priv,
1235                                     BXT_DE_PLL_ENABLE,
1236                                     BXT_DE_PLL_LOCK,
1237                                     BXT_DE_PLL_LOCK,
1238                                     1))
1239                 DRM_ERROR("timeout waiting for DE PLL lock\n");
1240
1241         dev_priv->cdclk.hw.vco = vco;
1242 }
1243
1244 static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
1245                           const struct intel_cdclk_state *cdclk_state)
1246 {
1247         int cdclk = cdclk_state->cdclk;
1248         int vco = cdclk_state->vco;
1249         u32 val, divider;
1250         int ret;
1251
1252         /* cdclk = vco / 2 / div{1,1.5,2,4} */
1253         switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
1254         case 8:
1255                 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
1256                 break;
1257         case 4:
1258                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
1259                 break;
1260         case 3:
1261                 WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n");
1262                 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
1263                 break;
1264         case 2:
1265                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
1266                 break;
1267         default:
1268                 WARN_ON(cdclk != dev_priv->cdclk.hw.ref);
1269                 WARN_ON(vco != 0);
1270
1271                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
1272                 break;
1273         }
1274
1275         /* Inform power controller of upcoming frequency change */
1276         mutex_lock(&dev_priv->rps.hw_lock);
1277         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
1278                                       0x80000000);
1279         mutex_unlock(&dev_priv->rps.hw_lock);
1280
1281         if (ret) {
1282                 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
1283                           ret, cdclk);
1284                 return;
1285         }
1286
1287         if (dev_priv->cdclk.hw.vco != 0 &&
1288             dev_priv->cdclk.hw.vco != vco)
1289                 bxt_de_pll_disable(dev_priv);
1290
1291         if (dev_priv->cdclk.hw.vco != vco)
1292                 bxt_de_pll_enable(dev_priv, vco);
1293
1294         val = divider | skl_cdclk_decimal(cdclk);
1295         /*
1296          * FIXME if only the cd2x divider needs changing, it could be done
1297          * without shutting off the pipe (if only one pipe is active).
1298          */
1299         val |= BXT_CDCLK_CD2X_PIPE_NONE;
1300         /*
1301          * Disable SSA Precharge when CD clock frequency < 500 MHz,
1302          * enable otherwise.
1303          */
1304         if (cdclk >= 500000)
1305                 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
1306         I915_WRITE(CDCLK_CTL, val);
1307
1308         mutex_lock(&dev_priv->rps.hw_lock);
1309         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
1310                                       DIV_ROUND_UP(cdclk, 25000));
1311         mutex_unlock(&dev_priv->rps.hw_lock);
1312
1313         if (ret) {
1314                 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
1315                           ret, cdclk);
1316                 return;
1317         }
1318
1319         intel_update_cdclk(dev_priv);
1320 }
1321
1322 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
1323 {
1324         u32 cdctl, expected;
1325
1326         intel_update_cdclk(dev_priv);
1327
1328         if (dev_priv->cdclk.hw.vco == 0 ||
1329             dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.ref)
1330                 goto sanitize;
1331
1332         /* DPLL okay; verify the cdclock
1333          *
1334          * Some BIOS versions leave an incorrect decimal frequency value and
1335          * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
1336          * so sanitize this register.
1337          */
1338         cdctl = I915_READ(CDCLK_CTL);
1339         /*
1340          * Let's ignore the pipe field, since BIOS could have configured the
1341          * dividers both synching to an active pipe, or asynchronously
1342          * (PIPE_NONE).
1343          */
1344         cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
1345
1346         expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
1347                 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
1348         /*
1349          * Disable SSA Precharge when CD clock frequency < 500 MHz,
1350          * enable otherwise.
1351          */
1352         if (dev_priv->cdclk.hw.cdclk >= 500000)
1353                 expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
1354
1355         if (cdctl == expected)
1356                 /* All well; nothing to sanitize */
1357                 return;
1358
1359 sanitize:
1360         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
1361
1362         /* force cdclk programming */
1363         dev_priv->cdclk.hw.cdclk = 0;
1364
1365         /* force full PLL disable + enable */
1366         dev_priv->cdclk.hw.vco = -1;
1367 }
1368
1369 /**
1370  * bxt_init_cdclk - Initialize CDCLK on BXT
1371  * @dev_priv: i915 device
1372  *
1373  * Initialize CDCLK for BXT and derivatives. This is generally
1374  * done only during the display core initialization sequence,
1375  * after which the DMC will take care of turning CDCLK off/on
1376  * as needed.
1377  */
1378 void bxt_init_cdclk(struct drm_i915_private *dev_priv)
1379 {
1380         struct intel_cdclk_state cdclk_state;
1381
1382         bxt_sanitize_cdclk(dev_priv);
1383
1384         if (dev_priv->cdclk.hw.cdclk != 0 &&
1385             dev_priv->cdclk.hw.vco != 0)
1386                 return;
1387
1388         cdclk_state = dev_priv->cdclk.hw;
1389
1390         /*
1391          * FIXME:
1392          * - The initial CDCLK needs to be read from VBT.
1393          *   Need to make this change after VBT has changes for BXT.
1394          */
1395         if (IS_GEMINILAKE(dev_priv)) {
1396                 cdclk_state.cdclk = glk_calc_cdclk(0);
1397                 cdclk_state.vco = glk_de_pll_vco(dev_priv, cdclk_state.cdclk);
1398         } else {
1399                 cdclk_state.cdclk = bxt_calc_cdclk(0);
1400                 cdclk_state.vco = bxt_de_pll_vco(dev_priv, cdclk_state.cdclk);
1401         }
1402
1403         bxt_set_cdclk(dev_priv, &cdclk_state);
1404 }
1405
1406 /**
1407  * bxt_uninit_cdclk - Uninitialize CDCLK on BXT
1408  * @dev_priv: i915 device
1409  *
1410  * Uninitialize CDCLK for BXT and derivatives. This is done only
1411  * during the display core uninitialization sequence.
1412  */
1413 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
1414 {
1415         struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
1416
1417         cdclk_state.cdclk = cdclk_state.ref;
1418         cdclk_state.vco = 0;
1419
1420         bxt_set_cdclk(dev_priv, &cdclk_state);
1421 }
1422
1423 static int cnl_calc_cdclk(int max_pixclk)
1424 {
1425         if (max_pixclk > 336000)
1426                 return 528000;
1427         else if (max_pixclk > 168000)
1428                 return 336000;
1429         else
1430                 return 168000;
1431 }
1432
1433 static void cnl_cdclk_pll_update(struct drm_i915_private *dev_priv,
1434                                  struct intel_cdclk_state *cdclk_state)
1435 {
1436         u32 val;
1437
1438         if (I915_READ(SKL_DSSM) & CNL_DSSM_CDCLK_PLL_REFCLK_24MHz)
1439                 cdclk_state->ref = 24000;
1440         else
1441                 cdclk_state->ref = 19200;
1442
1443         cdclk_state->vco = 0;
1444
1445         val = I915_READ(BXT_DE_PLL_ENABLE);
1446         if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
1447                 return;
1448
1449         if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
1450                 return;
1451
1452         cdclk_state->vco = (val & CNL_CDCLK_PLL_RATIO_MASK) * cdclk_state->ref;
1453 }
1454
1455 static void cnl_get_cdclk(struct drm_i915_private *dev_priv,
1456                          struct intel_cdclk_state *cdclk_state)
1457 {
1458         u32 divider;
1459         int div;
1460
1461         cnl_cdclk_pll_update(dev_priv, cdclk_state);
1462
1463         cdclk_state->cdclk = cdclk_state->ref;
1464
1465         if (cdclk_state->vco == 0)
1466                 return;
1467
1468         divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
1469
1470         switch (divider) {
1471         case BXT_CDCLK_CD2X_DIV_SEL_1:
1472                 div = 2;
1473                 break;
1474         case BXT_CDCLK_CD2X_DIV_SEL_2:
1475                 div = 4;
1476                 break;
1477         default:
1478                 MISSING_CASE(divider);
1479                 return;
1480         }
1481
1482         cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div);
1483 }
1484
1485 static void cnl_cdclk_pll_disable(struct drm_i915_private *dev_priv)
1486 {
1487         u32 val;
1488
1489         val = I915_READ(BXT_DE_PLL_ENABLE);
1490         val &= ~BXT_DE_PLL_PLL_ENABLE;
1491         I915_WRITE(BXT_DE_PLL_ENABLE, val);
1492
1493         /* Timeout 200us */
1494         if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) == 0, 1))
1495                 DRM_ERROR("timout waiting for CDCLK PLL unlock\n");
1496
1497         dev_priv->cdclk.hw.vco = 0;
1498 }
1499
1500 static void cnl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco)
1501 {
1502         int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
1503         u32 val;
1504
1505         val = CNL_CDCLK_PLL_RATIO(ratio);
1506         I915_WRITE(BXT_DE_PLL_ENABLE, val);
1507
1508         val |= BXT_DE_PLL_PLL_ENABLE;
1509         I915_WRITE(BXT_DE_PLL_ENABLE, val);
1510
1511         /* Timeout 200us */
1512         if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) != 0, 1))
1513                 DRM_ERROR("timout waiting for CDCLK PLL lock\n");
1514
1515         dev_priv->cdclk.hw.vco = vco;
1516 }
1517
1518 static void cnl_set_cdclk(struct drm_i915_private *dev_priv,
1519                           const struct intel_cdclk_state *cdclk_state)
1520 {
1521         int cdclk = cdclk_state->cdclk;
1522         int vco = cdclk_state->vco;
1523         u32 val, divider, pcu_ack;
1524         int ret;
1525
1526         mutex_lock(&dev_priv->rps.hw_lock);
1527         ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1528                                 SKL_CDCLK_PREPARE_FOR_CHANGE,
1529                                 SKL_CDCLK_READY_FOR_CHANGE,
1530                                 SKL_CDCLK_READY_FOR_CHANGE, 3);
1531         mutex_unlock(&dev_priv->rps.hw_lock);
1532         if (ret) {
1533                 DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
1534                           ret);
1535                 return;
1536         }
1537
1538         /* cdclk = vco / 2 / div{1,2} */
1539         switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
1540         case 4:
1541                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
1542                 break;
1543         case 2:
1544                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
1545                 break;
1546         default:
1547                 WARN_ON(cdclk != dev_priv->cdclk.hw.ref);
1548                 WARN_ON(vco != 0);
1549
1550                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
1551                 break;
1552         }
1553
1554         switch (cdclk) {
1555         case 528000:
1556                 pcu_ack = 2;
1557                 break;
1558         case 336000:
1559                 pcu_ack = 1;
1560                 break;
1561         case 168000:
1562         default:
1563                 pcu_ack = 0;
1564                 break;
1565         }
1566
1567         if (dev_priv->cdclk.hw.vco != 0 &&
1568             dev_priv->cdclk.hw.vco != vco)
1569                 cnl_cdclk_pll_disable(dev_priv);
1570
1571         if (dev_priv->cdclk.hw.vco != vco)
1572                 cnl_cdclk_pll_enable(dev_priv, vco);
1573
1574         val = divider | skl_cdclk_decimal(cdclk);
1575         /*
1576          * FIXME if only the cd2x divider needs changing, it could be done
1577          * without shutting off the pipe (if only one pipe is active).
1578          */
1579         val |= BXT_CDCLK_CD2X_PIPE_NONE;
1580         I915_WRITE(CDCLK_CTL, val);
1581
1582         /* inform PCU of the change */
1583         mutex_lock(&dev_priv->rps.hw_lock);
1584         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
1585         mutex_unlock(&dev_priv->rps.hw_lock);
1586
1587         intel_update_cdclk(dev_priv);
1588 }
1589
1590 static int cnl_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
1591 {
1592         int ratio;
1593
1594         if (cdclk == dev_priv->cdclk.hw.ref)
1595                 return 0;
1596
1597         switch (cdclk) {
1598         default:
1599                 MISSING_CASE(cdclk);
1600         case 168000:
1601         case 336000:
1602                 ratio = dev_priv->cdclk.hw.ref == 19200 ? 35 : 28;
1603                 break;
1604         case 528000:
1605                 ratio = dev_priv->cdclk.hw.ref == 19200 ? 55 : 44;
1606                 break;
1607         }
1608
1609         return dev_priv->cdclk.hw.ref * ratio;
1610 }
1611
1612 static void cnl_sanitize_cdclk(struct drm_i915_private *dev_priv)
1613 {
1614         u32 cdctl, expected;
1615
1616         intel_update_cdclk(dev_priv);
1617
1618         if (dev_priv->cdclk.hw.vco == 0 ||
1619             dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.ref)
1620                 goto sanitize;
1621
1622         /* DPLL okay; verify the cdclock
1623          *
1624          * Some BIOS versions leave an incorrect decimal frequency value and
1625          * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
1626          * so sanitize this register.
1627          */
1628         cdctl = I915_READ(CDCLK_CTL);
1629         /*
1630          * Let's ignore the pipe field, since BIOS could have configured the
1631          * dividers both synching to an active pipe, or asynchronously
1632          * (PIPE_NONE).
1633          */
1634         cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
1635
1636         expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
1637                    skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
1638
1639         if (cdctl == expected)
1640                 /* All well; nothing to sanitize */
1641                 return;
1642
1643 sanitize:
1644         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
1645
1646         /* force cdclk programming */
1647         dev_priv->cdclk.hw.cdclk = 0;
1648
1649         /* force full PLL disable + enable */
1650         dev_priv->cdclk.hw.vco = -1;
1651 }
1652
1653 /**
1654  * cnl_init_cdclk - Initialize CDCLK on CNL
1655  * @dev_priv: i915 device
1656  *
1657  * Initialize CDCLK for CNL. This is generally
1658  * done only during the display core initialization sequence,
1659  * after which the DMC will take care of turning CDCLK off/on
1660  * as needed.
1661  */
1662 void cnl_init_cdclk(struct drm_i915_private *dev_priv)
1663 {
1664         struct intel_cdclk_state cdclk_state;
1665
1666         cnl_sanitize_cdclk(dev_priv);
1667
1668         if (dev_priv->cdclk.hw.cdclk != 0 &&
1669             dev_priv->cdclk.hw.vco != 0)
1670                 return;
1671
1672         cdclk_state = dev_priv->cdclk.hw;
1673
1674         cdclk_state.cdclk = cnl_calc_cdclk(0);
1675         cdclk_state.vco = cnl_cdclk_pll_vco(dev_priv, cdclk_state.cdclk);
1676
1677         cnl_set_cdclk(dev_priv, &cdclk_state);
1678 }
1679
1680 /**
1681  * cnl_uninit_cdclk - Uninitialize CDCLK on CNL
1682  * @dev_priv: i915 device
1683  *
1684  * Uninitialize CDCLK for CNL. This is done only
1685  * during the display core uninitialization sequence.
1686  */
1687 void cnl_uninit_cdclk(struct drm_i915_private *dev_priv)
1688 {
1689         struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
1690
1691         cdclk_state.cdclk = cdclk_state.ref;
1692         cdclk_state.vco = 0;
1693
1694         cnl_set_cdclk(dev_priv, &cdclk_state);
1695 }
1696
1697 /**
1698  * intel_cdclk_state_compare - Determine if two CDCLK states differ
1699  * @a: first CDCLK state
1700  * @b: second CDCLK state
1701  *
1702  * Returns:
1703  * True if the CDCLK states are identical, false if they differ.
1704  */
1705 bool intel_cdclk_state_compare(const struct intel_cdclk_state *a,
1706                                const struct intel_cdclk_state *b)
1707 {
1708         return memcmp(a, b, sizeof(*a)) == 0;
1709 }
1710
1711 /**
1712  * intel_set_cdclk - Push the CDCLK state to the hardware
1713  * @dev_priv: i915 device
1714  * @cdclk_state: new CDCLK state
1715  *
1716  * Program the hardware based on the passed in CDCLK state,
1717  * if necessary.
1718  */
1719 void intel_set_cdclk(struct drm_i915_private *dev_priv,
1720                      const struct intel_cdclk_state *cdclk_state)
1721 {
1722         if (intel_cdclk_state_compare(&dev_priv->cdclk.hw, cdclk_state))
1723                 return;
1724
1725         if (WARN_ON_ONCE(!dev_priv->display.set_cdclk))
1726                 return;
1727
1728         DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz, VCO %d kHz, ref %d kHz\n",
1729                          cdclk_state->cdclk, cdclk_state->vco,
1730                          cdclk_state->ref);
1731
1732         dev_priv->display.set_cdclk(dev_priv, cdclk_state);
1733 }
1734
1735 static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state,
1736                                           int pixel_rate)
1737 {
1738         struct drm_i915_private *dev_priv =
1739                 to_i915(crtc_state->base.crtc->dev);
1740
1741         /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
1742         if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
1743                 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
1744
1745         /* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz,
1746          * audio enabled, port width x4, and link rate HBR2 (5.4 GHz), or else
1747          * there may be audio corruption or screen corruption." This cdclk
1748          * restriction for GLK is 316.8 MHz and since GLK can output two
1749          * pixels per clock, the pixel rate becomes 2 * 316.8 MHz.
1750          */
1751         if (intel_crtc_has_dp_encoder(crtc_state) &&
1752             crtc_state->has_audio &&
1753             crtc_state->port_clock >= 540000 &&
1754             crtc_state->lane_count == 4) {
1755                 if (IS_CANNONLAKE(dev_priv))
1756                         pixel_rate = max(316800, pixel_rate);
1757                 else if (IS_GEMINILAKE(dev_priv))
1758                         pixel_rate = max(2 * 316800, pixel_rate);
1759                 else
1760                         pixel_rate = max(432000, pixel_rate);
1761         }
1762
1763         /* According to BSpec, "The CD clock frequency must be at least twice
1764          * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
1765          * The check for GLK has to be adjusted as the platform can output
1766          * two pixels per clock.
1767          */
1768         if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9) {
1769                 if (IS_GEMINILAKE(dev_priv))
1770                         pixel_rate = max(2 * 2 * 96000, pixel_rate);
1771                 else
1772                         pixel_rate = max(2 * 96000, pixel_rate);
1773         }
1774
1775         return pixel_rate;
1776 }
1777
1778 /* compute the max rate for new configuration */
1779 static int intel_max_pixel_rate(struct drm_atomic_state *state)
1780 {
1781         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
1782         struct drm_i915_private *dev_priv = to_i915(state->dev);
1783         struct drm_crtc *crtc;
1784         struct drm_crtc_state *cstate;
1785         struct intel_crtc_state *crtc_state;
1786         unsigned int max_pixel_rate = 0, i;
1787         enum pipe pipe;
1788
1789         memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
1790                sizeof(intel_state->min_pixclk));
1791
1792         for_each_new_crtc_in_state(state, crtc, cstate, i) {
1793                 int pixel_rate;
1794
1795                 crtc_state = to_intel_crtc_state(cstate);
1796                 if (!crtc_state->base.enable) {
1797                         intel_state->min_pixclk[i] = 0;
1798                         continue;
1799                 }
1800
1801                 pixel_rate = crtc_state->pixel_rate;
1802
1803                 if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9)
1804                         pixel_rate =
1805                                 bdw_adjust_min_pipe_pixel_rate(crtc_state,
1806                                                                pixel_rate);
1807
1808                 intel_state->min_pixclk[i] = pixel_rate;
1809         }
1810
1811         for_each_pipe(dev_priv, pipe)
1812                 max_pixel_rate = max(intel_state->min_pixclk[pipe],
1813                                      max_pixel_rate);
1814
1815         return max_pixel_rate;
1816 }
1817
1818 static int vlv_modeset_calc_cdclk(struct drm_atomic_state *state)
1819 {
1820         struct drm_i915_private *dev_priv = to_i915(state->dev);
1821         int max_pixclk = intel_max_pixel_rate(state);
1822         struct intel_atomic_state *intel_state =
1823                 to_intel_atomic_state(state);
1824         int cdclk;
1825
1826         cdclk = vlv_calc_cdclk(dev_priv, max_pixclk);
1827
1828         if (cdclk > dev_priv->max_cdclk_freq) {
1829                 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
1830                               cdclk, dev_priv->max_cdclk_freq);
1831                 return -EINVAL;
1832         }
1833
1834         intel_state->cdclk.logical.cdclk = cdclk;
1835
1836         if (!intel_state->active_crtcs) {
1837                 cdclk = vlv_calc_cdclk(dev_priv, 0);
1838
1839                 intel_state->cdclk.actual.cdclk = cdclk;
1840         } else {
1841                 intel_state->cdclk.actual =
1842                         intel_state->cdclk.logical;
1843         }
1844
1845         return 0;
1846 }
1847
1848 static int bdw_modeset_calc_cdclk(struct drm_atomic_state *state)
1849 {
1850         struct drm_i915_private *dev_priv = to_i915(state->dev);
1851         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
1852         int max_pixclk = intel_max_pixel_rate(state);
1853         int cdclk;
1854
1855         /*
1856          * FIXME should also account for plane ratio
1857          * once 64bpp pixel formats are supported.
1858          */
1859         cdclk = bdw_calc_cdclk(max_pixclk);
1860
1861         if (cdclk > dev_priv->max_cdclk_freq) {
1862                 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
1863                               cdclk, dev_priv->max_cdclk_freq);
1864                 return -EINVAL;
1865         }
1866
1867         intel_state->cdclk.logical.cdclk = cdclk;
1868
1869         if (!intel_state->active_crtcs) {
1870                 cdclk = bdw_calc_cdclk(0);
1871
1872                 intel_state->cdclk.actual.cdclk = cdclk;
1873         } else {
1874                 intel_state->cdclk.actual =
1875                         intel_state->cdclk.logical;
1876         }
1877
1878         return 0;
1879 }
1880
1881 static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
1882 {
1883         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
1884         struct drm_i915_private *dev_priv = to_i915(state->dev);
1885         const int max_pixclk = intel_max_pixel_rate(state);
1886         int cdclk, vco;
1887
1888         vco = intel_state->cdclk.logical.vco;
1889         if (!vco)
1890                 vco = dev_priv->skl_preferred_vco_freq;
1891
1892         /*
1893          * FIXME should also account for plane ratio
1894          * once 64bpp pixel formats are supported.
1895          */
1896         cdclk = skl_calc_cdclk(max_pixclk, vco);
1897
1898         if (cdclk > dev_priv->max_cdclk_freq) {
1899                 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
1900                               cdclk, dev_priv->max_cdclk_freq);
1901                 return -EINVAL;
1902         }
1903
1904         intel_state->cdclk.logical.vco = vco;
1905         intel_state->cdclk.logical.cdclk = cdclk;
1906
1907         if (!intel_state->active_crtcs) {
1908                 cdclk = skl_calc_cdclk(0, vco);
1909
1910                 intel_state->cdclk.actual.vco = vco;
1911                 intel_state->cdclk.actual.cdclk = cdclk;
1912         } else {
1913                 intel_state->cdclk.actual =
1914                         intel_state->cdclk.logical;
1915         }
1916
1917         return 0;
1918 }
1919
1920 static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
1921 {
1922         struct drm_i915_private *dev_priv = to_i915(state->dev);
1923         int max_pixclk = intel_max_pixel_rate(state);
1924         struct intel_atomic_state *intel_state =
1925                 to_intel_atomic_state(state);
1926         int cdclk, vco;
1927
1928         if (IS_GEMINILAKE(dev_priv)) {
1929                 cdclk = glk_calc_cdclk(max_pixclk);
1930                 vco = glk_de_pll_vco(dev_priv, cdclk);
1931         } else {
1932                 cdclk = bxt_calc_cdclk(max_pixclk);
1933                 vco = bxt_de_pll_vco(dev_priv, cdclk);
1934         }
1935
1936         if (cdclk > dev_priv->max_cdclk_freq) {
1937                 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
1938                               cdclk, dev_priv->max_cdclk_freq);
1939                 return -EINVAL;
1940         }
1941
1942         intel_state->cdclk.logical.vco = vco;
1943         intel_state->cdclk.logical.cdclk = cdclk;
1944
1945         if (!intel_state->active_crtcs) {
1946                 if (IS_GEMINILAKE(dev_priv)) {
1947                         cdclk = glk_calc_cdclk(0);
1948                         vco = glk_de_pll_vco(dev_priv, cdclk);
1949                 } else {
1950                         cdclk = bxt_calc_cdclk(0);
1951                         vco = bxt_de_pll_vco(dev_priv, cdclk);
1952                 }
1953
1954                 intel_state->cdclk.actual.vco = vco;
1955                 intel_state->cdclk.actual.cdclk = cdclk;
1956         } else {
1957                 intel_state->cdclk.actual =
1958                         intel_state->cdclk.logical;
1959         }
1960
1961         return 0;
1962 }
1963
1964 static int cnl_modeset_calc_cdclk(struct drm_atomic_state *state)
1965 {
1966         struct drm_i915_private *dev_priv = to_i915(state->dev);
1967         struct intel_atomic_state *intel_state =
1968                 to_intel_atomic_state(state);
1969         int max_pixclk = intel_max_pixel_rate(state);
1970         int cdclk, vco;
1971
1972         cdclk = cnl_calc_cdclk(max_pixclk);
1973         vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
1974
1975         if (cdclk > dev_priv->max_cdclk_freq) {
1976                 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
1977                               cdclk, dev_priv->max_cdclk_freq);
1978                 return -EINVAL;
1979         }
1980
1981         intel_state->cdclk.logical.vco = vco;
1982         intel_state->cdclk.logical.cdclk = cdclk;
1983
1984         if (!intel_state->active_crtcs) {
1985                 cdclk = cnl_calc_cdclk(0);
1986                 vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
1987
1988                 intel_state->cdclk.actual.vco = vco;
1989                 intel_state->cdclk.actual.cdclk = cdclk;
1990         } else {
1991                 intel_state->cdclk.actual =
1992                         intel_state->cdclk.logical;
1993         }
1994
1995         return 0;
1996 }
1997
1998 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
1999 {
2000         int max_cdclk_freq = dev_priv->max_cdclk_freq;
2001
2002         if (IS_GEMINILAKE(dev_priv))
2003                 /*
2004                  * FIXME: Limiting to 99% as a temporary workaround. See
2005                  * glk_calc_cdclk() for details.
2006                  */
2007                 return 2 * max_cdclk_freq * 99 / 100;
2008         else if (INTEL_INFO(dev_priv)->gen >= 9 ||
2009                  IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
2010                 return max_cdclk_freq;
2011         else if (IS_CHERRYVIEW(dev_priv))
2012                 return max_cdclk_freq*95/100;
2013         else if (INTEL_INFO(dev_priv)->gen < 4)
2014                 return 2*max_cdclk_freq*90/100;
2015         else
2016                 return max_cdclk_freq*90/100;
2017 }
2018
2019 /**
2020  * intel_update_max_cdclk - Determine the maximum support CDCLK frequency
2021  * @dev_priv: i915 device
2022  *
2023  * Determine the maximum CDCLK frequency the platform supports, and also
2024  * derive the maximum dot clock frequency the maximum CDCLK frequency
2025  * allows.
2026  */
2027 void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
2028 {
2029         if (IS_CANNONLAKE(dev_priv)) {
2030                 dev_priv->max_cdclk_freq = 528000;
2031         } else if (IS_GEN9_BC(dev_priv)) {
2032                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
2033                 int max_cdclk, vco;
2034
2035                 vco = dev_priv->skl_preferred_vco_freq;
2036                 WARN_ON(vco != 8100000 && vco != 8640000);
2037
2038                 /*
2039                  * Use the lower (vco 8640) cdclk values as a
2040                  * first guess. skl_calc_cdclk() will correct it
2041                  * if the preferred vco is 8100 instead.
2042                  */
2043                 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
2044                         max_cdclk = 617143;
2045                 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
2046                         max_cdclk = 540000;
2047                 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
2048                         max_cdclk = 432000;
2049                 else
2050                         max_cdclk = 308571;
2051
2052                 dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
2053         } else if (IS_GEMINILAKE(dev_priv)) {
2054                 dev_priv->max_cdclk_freq = 316800;
2055         } else if (IS_BROXTON(dev_priv)) {
2056                 dev_priv->max_cdclk_freq = 624000;
2057         } else if (IS_BROADWELL(dev_priv))  {
2058                 /*
2059                  * FIXME with extra cooling we can allow
2060                  * 540 MHz for ULX and 675 Mhz for ULT.
2061                  * How can we know if extra cooling is
2062                  * available? PCI ID, VTB, something else?
2063                  */
2064                 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
2065                         dev_priv->max_cdclk_freq = 450000;
2066                 else if (IS_BDW_ULX(dev_priv))
2067                         dev_priv->max_cdclk_freq = 450000;
2068                 else if (IS_BDW_ULT(dev_priv))
2069                         dev_priv->max_cdclk_freq = 540000;
2070                 else
2071                         dev_priv->max_cdclk_freq = 675000;
2072         } else if (IS_CHERRYVIEW(dev_priv)) {
2073                 dev_priv->max_cdclk_freq = 320000;
2074         } else if (IS_VALLEYVIEW(dev_priv)) {
2075                 dev_priv->max_cdclk_freq = 400000;
2076         } else {
2077                 /* otherwise assume cdclk is fixed */
2078                 dev_priv->max_cdclk_freq = dev_priv->cdclk.hw.cdclk;
2079         }
2080
2081         dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
2082
2083         DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
2084                          dev_priv->max_cdclk_freq);
2085
2086         DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
2087                          dev_priv->max_dotclk_freq);
2088 }
2089
2090 /**
2091  * intel_update_cdclk - Determine the current CDCLK frequency
2092  * @dev_priv: i915 device
2093  *
2094  * Determine the current CDCLK frequency.
2095  */
2096 void intel_update_cdclk(struct drm_i915_private *dev_priv)
2097 {
2098         dev_priv->display.get_cdclk(dev_priv, &dev_priv->cdclk.hw);
2099
2100         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n",
2101                          dev_priv->cdclk.hw.cdclk, dev_priv->cdclk.hw.vco,
2102                          dev_priv->cdclk.hw.ref);
2103
2104         /*
2105          * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
2106          * Programmng [sic] note: bit[9:2] should be programmed to the number
2107          * of cdclk that generates 4MHz reference clock freq which is used to
2108          * generate GMBus clock. This will vary with the cdclk freq.
2109          */
2110         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2111                 I915_WRITE(GMBUSFREQ_VLV,
2112                            DIV_ROUND_UP(dev_priv->cdclk.hw.cdclk, 1000));
2113 }
2114
2115 static int cnp_rawclk(struct drm_i915_private *dev_priv)
2116 {
2117         u32 rawclk;
2118         int divider, fraction;
2119
2120         if (I915_READ(SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) {
2121                 /* 24 MHz */
2122                 divider = 24000;
2123                 fraction = 0;
2124         } else {
2125                 /* 19.2 MHz */
2126                 divider = 19000;
2127                 fraction = 200;
2128         }
2129
2130         rawclk = CNP_RAWCLK_DIV((divider / 1000) - 1);
2131         if (fraction)
2132                 rawclk |= CNP_RAWCLK_FRAC(DIV_ROUND_CLOSEST(1000,
2133                                                             fraction) - 1);
2134
2135         I915_WRITE(PCH_RAWCLK_FREQ, rawclk);
2136         return divider + fraction;
2137 }
2138
2139 static int pch_rawclk(struct drm_i915_private *dev_priv)
2140 {
2141         return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
2142 }
2143
2144 static int vlv_hrawclk(struct drm_i915_private *dev_priv)
2145 {
2146         /* RAWCLK_FREQ_VLV register updated from power well code */
2147         return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
2148                                       CCK_DISPLAY_REF_CLOCK_CONTROL);
2149 }
2150
2151 static int g4x_hrawclk(struct drm_i915_private *dev_priv)
2152 {
2153         uint32_t clkcfg;
2154
2155         /* hrawclock is 1/4 the FSB frequency */
2156         clkcfg = I915_READ(CLKCFG);
2157         switch (clkcfg & CLKCFG_FSB_MASK) {
2158         case CLKCFG_FSB_400:
2159                 return 100000;
2160         case CLKCFG_FSB_533:
2161                 return 133333;
2162         case CLKCFG_FSB_667:
2163                 return 166667;
2164         case CLKCFG_FSB_800:
2165                 return 200000;
2166         case CLKCFG_FSB_1067:
2167         case CLKCFG_FSB_1067_ALT:
2168                 return 266667;
2169         case CLKCFG_FSB_1333:
2170         case CLKCFG_FSB_1333_ALT:
2171                 return 333333;
2172         default:
2173                 return 133333;
2174         }
2175 }
2176
2177 /**
2178  * intel_update_rawclk - Determine the current RAWCLK frequency
2179  * @dev_priv: i915 device
2180  *
2181  * Determine the current RAWCLK frequency. RAWCLK is a fixed
2182  * frequency clock so this needs to done only once.
2183  */
2184 void intel_update_rawclk(struct drm_i915_private *dev_priv)
2185 {
2186
2187         if (HAS_PCH_CNP(dev_priv))
2188                 dev_priv->rawclk_freq = cnp_rawclk(dev_priv);
2189         else if (HAS_PCH_SPLIT(dev_priv))
2190                 dev_priv->rawclk_freq = pch_rawclk(dev_priv);
2191         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2192                 dev_priv->rawclk_freq = vlv_hrawclk(dev_priv);
2193         else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
2194                 dev_priv->rawclk_freq = g4x_hrawclk(dev_priv);
2195         else
2196                 /* no rawclk on other platforms, or no need to know it */
2197                 return;
2198
2199         DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
2200 }
2201
2202 /**
2203  * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks
2204  * @dev_priv: i915 device
2205  */
2206 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
2207 {
2208         if (IS_CHERRYVIEW(dev_priv)) {
2209                 dev_priv->display.set_cdclk = chv_set_cdclk;
2210                 dev_priv->display.modeset_calc_cdclk =
2211                         vlv_modeset_calc_cdclk;
2212         } else if (IS_VALLEYVIEW(dev_priv)) {
2213                 dev_priv->display.set_cdclk = vlv_set_cdclk;
2214                 dev_priv->display.modeset_calc_cdclk =
2215                         vlv_modeset_calc_cdclk;
2216         } else if (IS_BROADWELL(dev_priv)) {
2217                 dev_priv->display.set_cdclk = bdw_set_cdclk;
2218                 dev_priv->display.modeset_calc_cdclk =
2219                         bdw_modeset_calc_cdclk;
2220         } else if (IS_GEN9_LP(dev_priv)) {
2221                 dev_priv->display.set_cdclk = bxt_set_cdclk;
2222                 dev_priv->display.modeset_calc_cdclk =
2223                         bxt_modeset_calc_cdclk;
2224         } else if (IS_GEN9_BC(dev_priv)) {
2225                 dev_priv->display.set_cdclk = skl_set_cdclk;
2226                 dev_priv->display.modeset_calc_cdclk =
2227                         skl_modeset_calc_cdclk;
2228         } else if (IS_CANNONLAKE(dev_priv)) {
2229                 dev_priv->display.set_cdclk = cnl_set_cdclk;
2230                 dev_priv->display.modeset_calc_cdclk =
2231                         cnl_modeset_calc_cdclk;
2232         }
2233
2234         if (IS_CANNONLAKE(dev_priv))
2235                 dev_priv->display.get_cdclk = cnl_get_cdclk;
2236         else if (IS_GEN9_BC(dev_priv))
2237                 dev_priv->display.get_cdclk = skl_get_cdclk;
2238         else if (IS_GEN9_LP(dev_priv))
2239                 dev_priv->display.get_cdclk = bxt_get_cdclk;
2240         else if (IS_BROADWELL(dev_priv))
2241                 dev_priv->display.get_cdclk = bdw_get_cdclk;
2242         else if (IS_HASWELL(dev_priv))
2243                 dev_priv->display.get_cdclk = hsw_get_cdclk;
2244         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2245                 dev_priv->display.get_cdclk = vlv_get_cdclk;
2246         else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
2247                 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
2248         else if (IS_GEN5(dev_priv))
2249                 dev_priv->display.get_cdclk = fixed_450mhz_get_cdclk;
2250         else if (IS_GM45(dev_priv))
2251                 dev_priv->display.get_cdclk = gm45_get_cdclk;
2252         else if (IS_G45(dev_priv))
2253                 dev_priv->display.get_cdclk = g33_get_cdclk;
2254         else if (IS_I965GM(dev_priv))
2255                 dev_priv->display.get_cdclk = i965gm_get_cdclk;
2256         else if (IS_I965G(dev_priv))
2257                 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
2258         else if (IS_PINEVIEW(dev_priv))
2259                 dev_priv->display.get_cdclk = pnv_get_cdclk;
2260         else if (IS_G33(dev_priv))
2261                 dev_priv->display.get_cdclk = g33_get_cdclk;
2262         else if (IS_I945GM(dev_priv))
2263                 dev_priv->display.get_cdclk = i945gm_get_cdclk;
2264         else if (IS_I945G(dev_priv))
2265                 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
2266         else if (IS_I915GM(dev_priv))
2267                 dev_priv->display.get_cdclk = i915gm_get_cdclk;
2268         else if (IS_I915G(dev_priv))
2269                 dev_priv->display.get_cdclk = fixed_333mhz_get_cdclk;
2270         else if (IS_I865G(dev_priv))
2271                 dev_priv->display.get_cdclk = fixed_266mhz_get_cdclk;
2272         else if (IS_I85X(dev_priv))
2273                 dev_priv->display.get_cdclk = i85x_get_cdclk;
2274         else if (IS_I845G(dev_priv))
2275                 dev_priv->display.get_cdclk = fixed_200mhz_get_cdclk;
2276         else { /* 830 */
2277                 WARN(!IS_I830(dev_priv),
2278                      "Unknown platform. Assuming 133 MHz CDCLK\n");
2279                 dev_priv->display.get_cdclk = fixed_133mhz_get_cdclk;
2280         }
2281 }