drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/module.h>
  28 #include <linux/input.h>
  29 #include <linux/i2c.h>
  30 #include <linux/kernel.h>
  31 #include <linux/slab.h>
  32 #include <linux/vgaarb.h>
  33 #include "drmP.h"
  34 #include "intel_drv.h"
  35 #include "i915_drm.h"
  36 #include "i915_drv.h"
  37 #include "i915_trace.h"
  38 #include "drm_dp_helper.h"
  39
  40 #include "drm_crtc_helper.h"
  41
  42 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  43
  44 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  45 static void intel_update_watermarks(struct drm_device *dev);
  46 static void intel_increase_pllclock(struct drm_crtc *crtc);
  47 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  48
  49 typedef struct {
  50     /* given values */
  51     int n;
  52     int m1, m2;
  53     int p1, p2;
  54     /* derived values */
  55     int dot;
  56     int vco;
  57     int m;
  58     int p;
  59 } intel_clock_t;
  60
  61 typedef struct {
  62     int min, max;
  63 } intel_range_t;
  64
  65 typedef struct {
  66     int dot_limit;
  67     int p2_slow, p2_fast;
  68 } intel_p2_t;
  69
  70 #define INTEL_P2_NUM                  2
  71 typedef struct intel_limit intel_limit_t;
  72 struct intel_limit {
  73     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  74     intel_p2_t      p2;
  75     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  76                       int, int, intel_clock_t *);
  77 };
  78
  79 #define I8XX_DOT_MIN              25000
  80 #define I8XX_DOT_MAX             350000
  81 #define I8XX_VCO_MIN             930000
  82 #define I8XX_VCO_MAX            1400000
  83 #define I8XX_N_MIN                    3
  84 #define I8XX_N_MAX                   16
  85 #define I8XX_M_MIN                   96
  86 #define I8XX_M_MAX                  140
  87 #define I8XX_M1_MIN                  18
  88 #define I8XX_M1_MAX                  26
  89 #define I8XX_M2_MIN                   6
  90 #define I8XX_M2_MAX                  16
  91 #define I8XX_P_MIN                    4
  92 #define I8XX_P_MAX                  128
  93 #define I8XX_P1_MIN                   2
  94 #define I8XX_P1_MAX                  33
  95 #define I8XX_P1_LVDS_MIN              1
  96 #define I8XX_P1_LVDS_MAX              6
  97 #define I8XX_P2_SLOW                  4
  98 #define I8XX_P2_FAST                  2
  99 #define I8XX_P2_LVDS_SLOW             14
 100 #define I8XX_P2_LVDS_FAST             7
 101 #define I8XX_P2_SLOW_LIMIT       165000
 102
 103 #define I9XX_DOT_MIN              20000
 104 #define I9XX_DOT_MAX             400000
 105 #define I9XX_VCO_MIN            1400000
 106 #define I9XX_VCO_MAX            2800000
 107 #define PINEVIEW_VCO_MIN                1700000
 108 #define PINEVIEW_VCO_MAX                3500000
 109 #define I9XX_N_MIN                    1
 110 #define I9XX_N_MAX                    6
 111 /* Pineview's Ncounter is a ring counter */
 112 #define PINEVIEW_N_MIN                3
 113 #define PINEVIEW_N_MAX                6
 114 #define I9XX_M_MIN                   70
 115 #define I9XX_M_MAX                  120
 116 #define PINEVIEW_M_MIN                2
 117 #define PINEVIEW_M_MAX              256
 118 #define I9XX_M1_MIN                  10
 119 #define I9XX_M1_MAX                  22
 120 #define I9XX_M2_MIN                   5
 121 #define I9XX_M2_MAX                   9
 122 /* Pineview M1 is reserved, and must be 0 */
 123 #define PINEVIEW_M1_MIN               0
 124 #define PINEVIEW_M1_MAX               0
 125 #define PINEVIEW_M2_MIN               0
 126 #define PINEVIEW_M2_MAX               254
 127 #define I9XX_P_SDVO_DAC_MIN           5
 128 #define I9XX_P_SDVO_DAC_MAX          80
 129 #define I9XX_P_LVDS_MIN               7
 130 #define I9XX_P_LVDS_MAX              98
 131 #define PINEVIEW_P_LVDS_MIN                   7
 132 #define PINEVIEW_P_LVDS_MAX                  112
 133 #define I9XX_P1_MIN                   1
 134 #define I9XX_P1_MAX                   8
 135 #define I9XX_P2_SDVO_DAC_SLOW                10
 136 #define I9XX_P2_SDVO_DAC_FAST                 5
 137 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT      200000
 138 #define I9XX_P2_LVDS_SLOW                    14
 139 #define I9XX_P2_LVDS_FAST                     7
 140 #define I9XX_P2_LVDS_SLOW_LIMIT          112000
 141
 142 /*The parameter is for SDVO on G4x platform*/
 143 #define G4X_DOT_SDVO_MIN           25000
 144 #define G4X_DOT_SDVO_MAX           270000
 145 #define G4X_VCO_MIN                1750000
 146 #define G4X_VCO_MAX                3500000
 147 #define G4X_N_SDVO_MIN             1
 148 #define G4X_N_SDVO_MAX             4
 149 #define G4X_M_SDVO_MIN             104
 150 #define G4X_M_SDVO_MAX             138
 151 #define G4X_M1_SDVO_MIN            17
 152 #define G4X_M1_SDVO_MAX            23
 153 #define G4X_M2_SDVO_MIN            5
 154 #define G4X_M2_SDVO_MAX            11
 155 #define G4X_P_SDVO_MIN             10
 156 #define G4X_P_SDVO_MAX             30
 157 #define G4X_P1_SDVO_MIN            1
 158 #define G4X_P1_SDVO_MAX            3
 159 #define G4X_P2_SDVO_SLOW           10
 160 #define G4X_P2_SDVO_FAST           10
 161 #define G4X_P2_SDVO_LIMIT          270000
 162
 163 /*The parameter is for HDMI_DAC on G4x platform*/
 164 #define G4X_DOT_HDMI_DAC_MIN           22000
 165 #define G4X_DOT_HDMI_DAC_MAX           400000
 166 #define G4X_N_HDMI_DAC_MIN             1
 167 #define G4X_N_HDMI_DAC_MAX             4
 168 #define G4X_M_HDMI_DAC_MIN             104
 169 #define G4X_M_HDMI_DAC_MAX             138
 170 #define G4X_M1_HDMI_DAC_MIN            16
 171 #define G4X_M1_HDMI_DAC_MAX            23
 172 #define G4X_M2_HDMI_DAC_MIN            5
 173 #define G4X_M2_HDMI_DAC_MAX            11
 174 #define G4X_P_HDMI_DAC_MIN             5
 175 #define G4X_P_HDMI_DAC_MAX             80
 176 #define G4X_P1_HDMI_DAC_MIN            1
 177 #define G4X_P1_HDMI_DAC_MAX            8
 178 #define G4X_P2_HDMI_DAC_SLOW           10
 179 #define G4X_P2_HDMI_DAC_FAST           5
 180 #define G4X_P2_HDMI_DAC_LIMIT          165000
 181
 182 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
 183 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN           20000
 184 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX           115000
 185 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN             1
 186 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX             3
 187 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN             104
 188 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX             138
 189 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN            17
 190 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX            23
 191 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN            5
 192 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX            11
 193 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN             28
 194 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX             112
 195 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN            2
 196 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX            8
 197 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW           14
 198 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST           14
 199 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT          0
 200
 201 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
 202 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN           80000
 203 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX           224000
 204 #define G4X_N_DUAL_CHANNEL_LVDS_MIN             1
 205 #define G4X_N_DUAL_CHANNEL_LVDS_MAX             3
 206 #define G4X_M_DUAL_CHANNEL_LVDS_MIN             104
 207 #define G4X_M_DUAL_CHANNEL_LVDS_MAX             138
 208 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN            17
 209 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX            23
 210 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN            5
 211 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX            11
 212 #define G4X_P_DUAL_CHANNEL_LVDS_MIN             14
 213 #define G4X_P_DUAL_CHANNEL_LVDS_MAX             42
 214 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN            2
 215 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX            6
 216 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW           7
 217 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST           7
 218 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT          0
 219
 220 /*The parameter is for DISPLAY PORT on G4x platform*/
 221 #define G4X_DOT_DISPLAY_PORT_MIN           161670
 222 #define G4X_DOT_DISPLAY_PORT_MAX           227000
 223 #define G4X_N_DISPLAY_PORT_MIN             1
 224 #define G4X_N_DISPLAY_PORT_MAX             2
 225 #define G4X_M_DISPLAY_PORT_MIN             97
 226 #define G4X_M_DISPLAY_PORT_MAX             108
 227 #define G4X_M1_DISPLAY_PORT_MIN            0x10
 228 #define G4X_M1_DISPLAY_PORT_MAX            0x12
 229 #define G4X_M2_DISPLAY_PORT_MIN            0x05
 230 #define G4X_M2_DISPLAY_PORT_MAX            0x06
 231 #define G4X_P_DISPLAY_PORT_MIN             10
 232 #define G4X_P_DISPLAY_PORT_MAX             20
 233 #define G4X_P1_DISPLAY_PORT_MIN            1
 234 #define G4X_P1_DISPLAY_PORT_MAX            2
 235 #define G4X_P2_DISPLAY_PORT_SLOW           10
 236 #define G4X_P2_DISPLAY_PORT_FAST           10
 237 #define G4X_P2_DISPLAY_PORT_LIMIT          0
 238
 239 /* Ironlake / Sandybridge */
 240 /* as we calculate clock using (register_value + 2) for
 241    N/M1/M2, so here the range value for them is (actual_value-2).
 242  */
 243 #define IRONLAKE_DOT_MIN         25000
 244 #define IRONLAKE_DOT_MAX         350000
 245 #define IRONLAKE_VCO_MIN         1760000
 246 #define IRONLAKE_VCO_MAX         3510000
 247 #define IRONLAKE_M1_MIN          12
 248 #define IRONLAKE_M1_MAX          22
 249 #define IRONLAKE_M2_MIN          5
 250 #define IRONLAKE_M2_MAX          9
 251 #define IRONLAKE_P2_DOT_LIMIT    225000 /* 225Mhz */
 252
 253 /* We have parameter ranges for different type of outputs. */
 254
 255 /* DAC & HDMI Refclk 120Mhz */
 256 #define IRONLAKE_DAC_N_MIN      1
 257 #define IRONLAKE_DAC_N_MAX      5
 258 #define IRONLAKE_DAC_M_MIN      79
 259 #define IRONLAKE_DAC_M_MAX      127
 260 #define IRONLAKE_DAC_P_MIN      5
 261 #define IRONLAKE_DAC_P_MAX      80
 262 #define IRONLAKE_DAC_P1_MIN     1
 263 #define IRONLAKE_DAC_P1_MAX     8
 264 #define IRONLAKE_DAC_P2_SLOW    10
 265 #define IRONLAKE_DAC_P2_FAST    5
 266
 267 /* LVDS single-channel 120Mhz refclk */
 268 #define IRONLAKE_LVDS_S_N_MIN   1
 269 #define IRONLAKE_LVDS_S_N_MAX   3
 270 #define IRONLAKE_LVDS_S_M_MIN   79
 271 #define IRONLAKE_LVDS_S_M_MAX   118
 272 #define IRONLAKE_LVDS_S_P_MIN   28
 273 #define IRONLAKE_LVDS_S_P_MAX   112
 274 #define IRONLAKE_LVDS_S_P1_MIN  2
 275 #define IRONLAKE_LVDS_S_P1_MAX  8
 276 #define IRONLAKE_LVDS_S_P2_SLOW 14
 277 #define IRONLAKE_LVDS_S_P2_FAST 14
 278
 279 /* LVDS dual-channel 120Mhz refclk */
 280 #define IRONLAKE_LVDS_D_N_MIN   1
 281 #define IRONLAKE_LVDS_D_N_MAX   3
 282 #define IRONLAKE_LVDS_D_M_MIN   79
 283 #define IRONLAKE_LVDS_D_M_MAX   127
 284 #define IRONLAKE_LVDS_D_P_MIN   14
 285 #define IRONLAKE_LVDS_D_P_MAX   56
 286 #define IRONLAKE_LVDS_D_P1_MIN  2
 287 #define IRONLAKE_LVDS_D_P1_MAX  8
 288 #define IRONLAKE_LVDS_D_P2_SLOW 7
 289 #define IRONLAKE_LVDS_D_P2_FAST 7
 290
 291 /* LVDS single-channel 100Mhz refclk */
 292 #define IRONLAKE_LVDS_S_SSC_N_MIN       1
 293 #define IRONLAKE_LVDS_S_SSC_N_MAX       2
 294 #define IRONLAKE_LVDS_S_SSC_M_MIN       79
 295 #define IRONLAKE_LVDS_S_SSC_M_MAX       126
 296 #define IRONLAKE_LVDS_S_SSC_P_MIN       28
 297 #define IRONLAKE_LVDS_S_SSC_P_MAX       112
 298 #define IRONLAKE_LVDS_S_SSC_P1_MIN      2
 299 #define IRONLAKE_LVDS_S_SSC_P1_MAX      8
 300 #define IRONLAKE_LVDS_S_SSC_P2_SLOW     14
 301 #define IRONLAKE_LVDS_S_SSC_P2_FAST     14
 302
 303 /* LVDS dual-channel 100Mhz refclk */
 304 #define IRONLAKE_LVDS_D_SSC_N_MIN       1
 305 #define IRONLAKE_LVDS_D_SSC_N_MAX       3
 306 #define IRONLAKE_LVDS_D_SSC_M_MIN       79
 307 #define IRONLAKE_LVDS_D_SSC_M_MAX       126
 308 #define IRONLAKE_LVDS_D_SSC_P_MIN       14
 309 #define IRONLAKE_LVDS_D_SSC_P_MAX       42
 310 #define IRONLAKE_LVDS_D_SSC_P1_MIN      2
 311 #define IRONLAKE_LVDS_D_SSC_P1_MAX      6
 312 #define IRONLAKE_LVDS_D_SSC_P2_SLOW     7
 313 #define IRONLAKE_LVDS_D_SSC_P2_FAST     7
 314
 315 /* DisplayPort */
 316 #define IRONLAKE_DP_N_MIN               1
 317 #define IRONLAKE_DP_N_MAX               2
 318 #define IRONLAKE_DP_M_MIN               81
 319 #define IRONLAKE_DP_M_MAX               90
 320 #define IRONLAKE_DP_P_MIN               10
 321 #define IRONLAKE_DP_P_MAX               20
 322 #define IRONLAKE_DP_P2_FAST             10
 323 #define IRONLAKE_DP_P2_SLOW             10
 324 #define IRONLAKE_DP_P2_LIMIT            0
 325 #define IRONLAKE_DP_P1_MIN              1
 326 #define IRONLAKE_DP_P1_MAX              2
 327
 328 /* FDI */
 329 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
 330
 331 static bool
 332 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 333                     int target, int refclk, intel_clock_t *best_clock);
 334 static bool
 335 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 336                         int target, int refclk, intel_clock_t *best_clock);
 337
 338 static bool
 339 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 340                       int target, int refclk, intel_clock_t *best_clock);
 341 static bool
 342 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 343                            int target, int refclk, intel_clock_t *best_clock);
 344
 345 static inline u32 /* units of 100MHz */
 346 intel_fdi_link_freq(struct drm_device *dev)
 347 {
 348         if (IS_GEN5(dev)) {
 349                 struct drm_i915_private *dev_priv = dev->dev_private;
 350                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 351         } else
 352                 return 27;
 353 }
 354
 355 static const intel_limit_t intel_limits_i8xx_dvo = {
 356         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 357         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 358         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 359         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 360         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 361         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 362         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 363         .p1  = { .min = I8XX_P1_MIN,            .max = I8XX_P1_MAX },
 364         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 365                  .p2_slow = I8XX_P2_SLOW,       .p2_fast = I8XX_P2_FAST },
 366         .find_pll = intel_find_best_PLL,
 367 };
 368
 369 static const intel_limit_t intel_limits_i8xx_lvds = {
 370         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 371         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 372         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 373         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 374         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 375         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 376         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 377         .p1  = { .min = I8XX_P1_LVDS_MIN,       .max = I8XX_P1_LVDS_MAX },
 378         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 379                  .p2_slow = I8XX_P2_LVDS_SLOW,  .p2_fast = I8XX_P2_LVDS_FAST },
 380         .find_pll = intel_find_best_PLL,
 381 };
 382
 383 static const intel_limit_t intel_limits_i9xx_sdvo = {
 384         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 385         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 386         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 387         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 388         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 389         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 390         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 391         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 392         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 393                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 394         .find_pll = intel_find_best_PLL,
 395 };
 396
 397 static const intel_limit_t intel_limits_i9xx_lvds = {
 398         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 399         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 400         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 401         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 402         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 403         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 404         .p   = { .min = I9XX_P_LVDS_MIN,        .max = I9XX_P_LVDS_MAX },
 405         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 406         /* The single-channel range is 25-112Mhz, and dual-channel
 407          * is 80-224Mhz.  Prefer single channel as much as possible.
 408          */
 409         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 410                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_FAST },
 411         .find_pll = intel_find_best_PLL,
 412 };
 413
 414     /* below parameter and function is for G4X Chipset Family*/
 415 static const intel_limit_t intel_limits_g4x_sdvo = {
 416         .dot = { .min = G4X_DOT_SDVO_MIN,       .max = G4X_DOT_SDVO_MAX },
 417         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 418         .n   = { .min = G4X_N_SDVO_MIN,         .max = G4X_N_SDVO_MAX },
 419         .m   = { .min = G4X_M_SDVO_MIN,         .max = G4X_M_SDVO_MAX },
 420         .m1  = { .min = G4X_M1_SDVO_MIN,        .max = G4X_M1_SDVO_MAX },
 421         .m2  = { .min = G4X_M2_SDVO_MIN,        .max = G4X_M2_SDVO_MAX },
 422         .p   = { .min = G4X_P_SDVO_MIN,         .max = G4X_P_SDVO_MAX },
 423         .p1  = { .min = G4X_P1_SDVO_MIN,        .max = G4X_P1_SDVO_MAX},
 424         .p2  = { .dot_limit = G4X_P2_SDVO_LIMIT,
 425                  .p2_slow = G4X_P2_SDVO_SLOW,
 426                  .p2_fast = G4X_P2_SDVO_FAST
 427         },
 428         .find_pll = intel_g4x_find_best_PLL,
 429 };
 430
 431 static const intel_limit_t intel_limits_g4x_hdmi = {
 432         .dot = { .min = G4X_DOT_HDMI_DAC_MIN,   .max = G4X_DOT_HDMI_DAC_MAX },
 433         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 434         .n   = { .min = G4X_N_HDMI_DAC_MIN,     .max = G4X_N_HDMI_DAC_MAX },
 435         .m   = { .min = G4X_M_HDMI_DAC_MIN,     .max = G4X_M_HDMI_DAC_MAX },
 436         .m1  = { .min = G4X_M1_HDMI_DAC_MIN,    .max = G4X_M1_HDMI_DAC_MAX },
 437         .m2  = { .min = G4X_M2_HDMI_DAC_MIN,    .max = G4X_M2_HDMI_DAC_MAX },
 438         .p   = { .min = G4X_P_HDMI_DAC_MIN,     .max = G4X_P_HDMI_DAC_MAX },
 439         .p1  = { .min = G4X_P1_HDMI_DAC_MIN,    .max = G4X_P1_HDMI_DAC_MAX},
 440         .p2  = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
 441                  .p2_slow = G4X_P2_HDMI_DAC_SLOW,
 442                  .p2_fast = G4X_P2_HDMI_DAC_FAST
 443         },
 444         .find_pll = intel_g4x_find_best_PLL,
 445 };
 446
 447 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 448         .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
 449                  .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
 450         .vco = { .min = G4X_VCO_MIN,
 451                  .max = G4X_VCO_MAX },
 452         .n   = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
 453                  .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
 454         .m   = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
 455                  .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
 456         .m1  = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
 457                  .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
 458         .m2  = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
 459                  .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
 460         .p   = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
 461                  .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
 462         .p1  = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
 463                  .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
 464         .p2  = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
 465                  .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
 466                  .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
 467         },
 468         .find_pll = intel_g4x_find_best_PLL,
 469 };
 470
 471 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 472         .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
 473                  .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
 474         .vco = { .min = G4X_VCO_MIN,
 475                  .max = G4X_VCO_MAX },
 476         .n   = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
 477                  .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
 478         .m   = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
 479                  .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
 480         .m1  = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
 481                  .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
 482         .m2  = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
 483                  .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
 484         .p   = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
 485                  .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
 486         .p1  = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
 487                  .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
 488         .p2  = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
 489                  .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
 490                  .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
 491         },
 492         .find_pll = intel_g4x_find_best_PLL,
 493 };
 494
 495 static const intel_limit_t intel_limits_g4x_display_port = {
 496         .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
 497                  .max = G4X_DOT_DISPLAY_PORT_MAX },
 498         .vco = { .min = G4X_VCO_MIN,
 499                  .max = G4X_VCO_MAX},
 500         .n   = { .min = G4X_N_DISPLAY_PORT_MIN,
 501                  .max = G4X_N_DISPLAY_PORT_MAX },
 502         .m   = { .min = G4X_M_DISPLAY_PORT_MIN,
 503                  .max = G4X_M_DISPLAY_PORT_MAX },
 504         .m1  = { .min = G4X_M1_DISPLAY_PORT_MIN,
 505                  .max = G4X_M1_DISPLAY_PORT_MAX },
 506         .m2  = { .min = G4X_M2_DISPLAY_PORT_MIN,
 507                  .max = G4X_M2_DISPLAY_PORT_MAX },
 508         .p   = { .min = G4X_P_DISPLAY_PORT_MIN,
 509                  .max = G4X_P_DISPLAY_PORT_MAX },
 510         .p1  = { .min = G4X_P1_DISPLAY_PORT_MIN,
 511                  .max = G4X_P1_DISPLAY_PORT_MAX},
 512         .p2  = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
 513                  .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
 514                  .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
 515         .find_pll = intel_find_pll_g4x_dp,
 516 };
 517
 518 static const intel_limit_t intel_limits_pineview_sdvo = {
 519         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX},
 520         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 521         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 522         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 523         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 524         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 525         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 526         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 527         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 528                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 529         .find_pll = intel_find_best_PLL,
 530 };
 531
 532 static const intel_limit_t intel_limits_pineview_lvds = {
 533         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 534         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 535         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 536         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 537         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 538         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 539         .p   = { .min = PINEVIEW_P_LVDS_MIN,    .max = PINEVIEW_P_LVDS_MAX },
 540         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 541         /* Pineview only supports single-channel mode. */
 542         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 543                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_SLOW },
 544         .find_pll = intel_find_best_PLL,
 545 };
 546
 547 static const intel_limit_t intel_limits_ironlake_dac = {
 548         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 549         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 550         .n   = { .min = IRONLAKE_DAC_N_MIN,        .max = IRONLAKE_DAC_N_MAX },
 551         .m   = { .min = IRONLAKE_DAC_M_MIN,        .max = IRONLAKE_DAC_M_MAX },
 552         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 553         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 554         .p   = { .min = IRONLAKE_DAC_P_MIN,        .max = IRONLAKE_DAC_P_MAX },
 555         .p1  = { .min = IRONLAKE_DAC_P1_MIN,       .max = IRONLAKE_DAC_P1_MAX },
 556         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 557                  .p2_slow = IRONLAKE_DAC_P2_SLOW,
 558                  .p2_fast = IRONLAKE_DAC_P2_FAST },
 559         .find_pll = intel_g4x_find_best_PLL,
 560 };
 561
 562 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 563         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 564         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 565         .n   = { .min = IRONLAKE_LVDS_S_N_MIN,     .max = IRONLAKE_LVDS_S_N_MAX },
 566         .m   = { .min = IRONLAKE_LVDS_S_M_MIN,     .max = IRONLAKE_LVDS_S_M_MAX },
 567         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 568         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 569         .p   = { .min = IRONLAKE_LVDS_S_P_MIN,     .max = IRONLAKE_LVDS_S_P_MAX },
 570         .p1  = { .min = IRONLAKE_LVDS_S_P1_MIN,    .max = IRONLAKE_LVDS_S_P1_MAX },
 571         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 572                  .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
 573                  .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
 574         .find_pll = intel_g4x_find_best_PLL,
 575 };
 576
 577 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 578         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 579         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 580         .n   = { .min = IRONLAKE_LVDS_D_N_MIN,     .max = IRONLAKE_LVDS_D_N_MAX },
 581         .m   = { .min = IRONLAKE_LVDS_D_M_MIN,     .max = IRONLAKE_LVDS_D_M_MAX },
 582         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 583         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 584         .p   = { .min = IRONLAKE_LVDS_D_P_MIN,     .max = IRONLAKE_LVDS_D_P_MAX },
 585         .p1  = { .min = IRONLAKE_LVDS_D_P1_MIN,    .max = IRONLAKE_LVDS_D_P1_MAX },
 586         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 587                  .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
 588                  .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
 589         .find_pll = intel_g4x_find_best_PLL,
 590 };
 591
 592 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 593         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 594         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 595         .n   = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
 596         .m   = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
 597         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 598         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 599         .p   = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
 600         .p1  = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
 601         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 602                  .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
 603                  .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
 604         .find_pll = intel_g4x_find_best_PLL,
 605 };
 606
 607 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 608         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 609         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 610         .n   = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
 611         .m   = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
 612         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 613         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 614         .p   = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
 615         .p1  = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
 616         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 617                  .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
 618                  .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
 619         .find_pll = intel_g4x_find_best_PLL,
 620 };
 621
 622 static const intel_limit_t intel_limits_ironlake_display_port = {
 623         .dot = { .min = IRONLAKE_DOT_MIN,
 624                  .max = IRONLAKE_DOT_MAX },
 625         .vco = { .min = IRONLAKE_VCO_MIN,
 626                  .max = IRONLAKE_VCO_MAX},
 627         .n   = { .min = IRONLAKE_DP_N_MIN,
 628                  .max = IRONLAKE_DP_N_MAX },
 629         .m   = { .min = IRONLAKE_DP_M_MIN,
 630                  .max = IRONLAKE_DP_M_MAX },
 631         .m1  = { .min = IRONLAKE_M1_MIN,
 632                  .max = IRONLAKE_M1_MAX },
 633         .m2  = { .min = IRONLAKE_M2_MIN,
 634                  .max = IRONLAKE_M2_MAX },
 635         .p   = { .min = IRONLAKE_DP_P_MIN,
 636                  .max = IRONLAKE_DP_P_MAX },
 637         .p1  = { .min = IRONLAKE_DP_P1_MIN,
 638                  .max = IRONLAKE_DP_P1_MAX},
 639         .p2  = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
 640                  .p2_slow = IRONLAKE_DP_P2_SLOW,
 641                  .p2_fast = IRONLAKE_DP_P2_FAST },
 642         .find_pll = intel_find_pll_ironlake_dp,
 643 };
 644
 645 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 646                                                 int refclk)
 647 {
 648         struct drm_device *dev = crtc->dev;
 649         struct drm_i915_private *dev_priv = dev->dev_private;
 650         const intel_limit_t *limit;
 651
 652         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 653                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
 654                     LVDS_CLKB_POWER_UP) {
 655                         /* LVDS dual channel */
 656                         if (refclk == 100000)
 657                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 658                         else
 659                                 limit = &intel_limits_ironlake_dual_lvds;
 660                 } else {
 661                         if (refclk == 100000)
 662                                 limit = &intel_limits_ironlake_single_lvds_100m;
 663                         else
 664                                 limit = &intel_limits_ironlake_single_lvds;
 665                 }
 666         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 667                         HAS_eDP)
 668                 limit = &intel_limits_ironlake_display_port;
 669         else
 670                 limit = &intel_limits_ironlake_dac;
 671
 672         return limit;
 673 }
 674
 675 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 676 {
 677         struct drm_device *dev = crtc->dev;
 678         struct drm_i915_private *dev_priv = dev->dev_private;
 679         const intel_limit_t *limit;
 680
 681         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 682                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 683                     LVDS_CLKB_POWER_UP)
 684                         /* LVDS with dual channel */
 685                         limit = &intel_limits_g4x_dual_channel_lvds;
 686                 else
 687                         /* LVDS with dual channel */
 688                         limit = &intel_limits_g4x_single_channel_lvds;
 689         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 690                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 691                 limit = &intel_limits_g4x_hdmi;
 692         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 693                 limit = &intel_limits_g4x_sdvo;
 694         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 695                 limit = &intel_limits_g4x_display_port;
 696         } else /* The option is for other outputs */
 697                 limit = &intel_limits_i9xx_sdvo;
 698
 699         return limit;
 700 }
 701
 702 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 703 {
 704         struct drm_device *dev = crtc->dev;
 705         const intel_limit_t *limit;
 706
 707         if (HAS_PCH_SPLIT(dev))
 708                 limit = intel_ironlake_limit(crtc, refclk);
 709         else if (IS_G4X(dev)) {
 710                 limit = intel_g4x_limit(crtc);
 711         } else if (IS_PINEVIEW(dev)) {
 712                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 713                         limit = &intel_limits_pineview_lvds;
 714                 else
 715                         limit = &intel_limits_pineview_sdvo;
 716         } else if (!IS_GEN2(dev)) {
 717                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 718                         limit = &intel_limits_i9xx_lvds;
 719                 else
 720                         limit = &intel_limits_i9xx_sdvo;
 721         } else {
 722                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 723                         limit = &intel_limits_i8xx_lvds;
 724                 else
 725                         limit = &intel_limits_i8xx_dvo;
 726         }
 727         return limit;
 728 }
 729
 730 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 731 static void pineview_clock(int refclk, intel_clock_t *clock)
 732 {
 733         clock->m = clock->m2 + 2;
 734         clock->p = clock->p1 * clock->p2;
 735         clock->vco = refclk * clock->m / clock->n;
 736         clock->dot = clock->vco / clock->p;
 737 }
 738
 739 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 740 {
 741         if (IS_PINEVIEW(dev)) {
 742                 pineview_clock(refclk, clock);
 743                 return;
 744         }
 745         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 746         clock->p = clock->p1 * clock->p2;
 747         clock->vco = refclk * clock->m / (clock->n + 2);
 748         clock->dot = clock->vco / clock->p;
 749 }
 750
 751 /**
 752  * Returns whether any output on the specified pipe is of the specified type
 753  */
 754 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 755 {
 756         struct drm_device *dev = crtc->dev;
 757         struct drm_mode_config *mode_config = &dev->mode_config;
 758         struct intel_encoder *encoder;
 759
 760         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 761                 if (encoder->base.crtc == crtc && encoder->type == type)
 762                         return true;
 763
 764         return false;
 765 }
 766
 767 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 768 /**
 769  * Returns whether the given set of divisors are valid for a given refclk with
 770  * the given connectors.
 771  */
 772
 773 static bool intel_PLL_is_valid(struct drm_device *dev,
 774                                const intel_limit_t *limit,
 775                                const intel_clock_t *clock)
 776 {
 777         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 778                 INTELPllInvalid ("p1 out of range\n");
 779         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 780                 INTELPllInvalid ("p out of range\n");
 781         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 782                 INTELPllInvalid ("m2 out of range\n");
 783         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 784                 INTELPllInvalid ("m1 out of range\n");
 785         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 786                 INTELPllInvalid ("m1 <= m2\n");
 787         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 788                 INTELPllInvalid ("m out of range\n");
 789         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 790                 INTELPllInvalid ("n out of range\n");
 791         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 792                 INTELPllInvalid ("vco out of range\n");
 793         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 794          * connector, etc., rather than just a single range.
 795          */
 796         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 797                 INTELPllInvalid ("dot out of range\n");
 798
 799         return true;
 800 }
 801
 802 static bool
 803 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 804                     int target, int refclk, intel_clock_t *best_clock)
 805
 806 {
 807         struct drm_device *dev = crtc->dev;
 808         struct drm_i915_private *dev_priv = dev->dev_private;
 809         intel_clock_t clock;
 810         int err = target;
 811
 812         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 813             (I915_READ(LVDS)) != 0) {
 814                 /*
 815                  * For LVDS, if the panel is on, just rely on its current
 816                  * settings for dual-channel.  We haven't figured out how to
 817                  * reliably set up different single/dual channel state, if we
 818                  * even can.
 819                  */
 820                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 821                     LVDS_CLKB_POWER_UP)
 822                         clock.p2 = limit->p2.p2_fast;
 823                 else
 824                         clock.p2 = limit->p2.p2_slow;
 825         } else {
 826                 if (target < limit->p2.dot_limit)
 827                         clock.p2 = limit->p2.p2_slow;
 828                 else
 829                         clock.p2 = limit->p2.p2_fast;
 830         }
 831
 832         memset (best_clock, 0, sizeof (*best_clock));
 833
 834         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 835              clock.m1++) {
 836                 for (clock.m2 = limit->m2.min;
 837                      clock.m2 <= limit->m2.max; clock.m2++) {
 838                         /* m1 is always 0 in Pineview */
 839                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 840                                 break;
 841                         for (clock.n = limit->n.min;
 842                              clock.n <= limit->n.max; clock.n++) {
 843                                 for (clock.p1 = limit->p1.min;
 844                                         clock.p1 <= limit->p1.max; clock.p1++) {
 845                                         int this_err;
 846
 847                                         intel_clock(dev, refclk, &clock);
 848                                         if (!intel_PLL_is_valid(dev, limit,
 849                                                                 &clock))
 850                                                 continue;
 851
 852                                         this_err = abs(clock.dot - target);
 853                                         if (this_err < err) {
 854                                                 *best_clock = clock;
 855                                                 err = this_err;
 856                                         }
 857                                 }
 858                         }
 859                 }
 860         }
 861
 862         return (err != target);
 863 }
 864
 865 static bool
 866 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 867                         int target, int refclk, intel_clock_t *best_clock)
 868 {
 869         struct drm_device *dev = crtc->dev;
 870         struct drm_i915_private *dev_priv = dev->dev_private;
 871         intel_clock_t clock;
 872         int max_n;
 873         bool found;
 874         /* approximately equals target * 0.00585 */
 875         int err_most = (target >> 8) + (target >> 9);
 876         found = false;
 877
 878         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 879                 int lvds_reg;
 880
 881                 if (HAS_PCH_SPLIT(dev))
 882                         lvds_reg = PCH_LVDS;
 883                 else
 884                         lvds_reg = LVDS;
 885                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 886                     LVDS_CLKB_POWER_UP)
 887                         clock.p2 = limit->p2.p2_fast;
 888                 else
 889                         clock.p2 = limit->p2.p2_slow;
 890         } else {
 891                 if (target < limit->p2.dot_limit)
 892                         clock.p2 = limit->p2.p2_slow;
 893                 else
 894                         clock.p2 = limit->p2.p2_fast;
 895         }
 896
 897         memset(best_clock, 0, sizeof(*best_clock));
 898         max_n = limit->n.max;
 899         /* based on hardware requirement, prefer smaller n to precision */
 900         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 901                 /* based on hardware requirement, prefere larger m1,m2 */
 902                 for (clock.m1 = limit->m1.max;
 903                      clock.m1 >= limit->m1.min; clock.m1--) {
 904                         for (clock.m2 = limit->m2.max;
 905                              clock.m2 >= limit->m2.min; clock.m2--) {
 906                                 for (clock.p1 = limit->p1.max;
 907                                      clock.p1 >= limit->p1.min; clock.p1--) {
 908                                         int this_err;
 909
 910                                         intel_clock(dev, refclk, &clock);
 911                                         if (!intel_PLL_is_valid(dev, limit,
 912                                                                 &clock))
 913                                                 continue;
 914
 915                                         this_err = abs(clock.dot - target);
 916                                         if (this_err < err_most) {
 917                                                 *best_clock = clock;
 918                                                 err_most = this_err;
 919                                                 max_n = clock.n;
 920                                                 found = true;
 921                                         }
 922                                 }
 923                         }
 924                 }
 925         }
 926         return found;
 927 }
 928
 929 static bool
 930 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 931                            int target, int refclk, intel_clock_t *best_clock)
 932 {
 933         struct drm_device *dev = crtc->dev;
 934         intel_clock_t clock;
 935
 936         if (target < 200000) {
 937                 clock.n = 1;
 938                 clock.p1 = 2;
 939                 clock.p2 = 10;
 940                 clock.m1 = 12;
 941                 clock.m2 = 9;
 942         } else {
 943                 clock.n = 2;
 944                 clock.p1 = 1;
 945                 clock.p2 = 10;
 946                 clock.m1 = 14;
 947                 clock.m2 = 8;
 948         }
 949         intel_clock(dev, refclk, &clock);
 950         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 951         return true;
 952 }
 953
 954 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 955 static bool
 956 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 957                       int target, int refclk, intel_clock_t *best_clock)
 958 {
 959         intel_clock_t clock;
 960         if (target < 200000) {
 961                 clock.p1 = 2;
 962                 clock.p2 = 10;
 963                 clock.n = 2;
 964                 clock.m1 = 23;
 965                 clock.m2 = 8;
 966         } else {
 967                 clock.p1 = 1;
 968                 clock.p2 = 10;
 969                 clock.n = 1;
 970                 clock.m1 = 14;
 971                 clock.m2 = 2;
 972         }
 973         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 974         clock.p = (clock.p1 * clock.p2);
 975         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 976         clock.vco = 0;
 977         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 978         return true;
 979 }
 980
 981 /**
 982  * intel_wait_for_vblank - wait for vblank on a given pipe
 983  * @dev: drm device
 984  * @pipe: pipe to wait for
 985  *
 986  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 987  * mode setting code.
 988  */
 989 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 990 {
 991         struct drm_i915_private *dev_priv = dev->dev_private;
 992         int pipestat_reg = (pipe == 0 ? PIPEASTAT : PIPEBSTAT);
 993
 994         /* Clear existing vblank status. Note this will clear any other
 995          * sticky status fields as well.
 996          *
 997          * This races with i915_driver_irq_handler() with the result
 998          * that either function could miss a vblank event.  Here it is not
 999          * fatal, as we will either wait upon the next vblank interrupt or
1000          * timeout.  Generally speaking intel_wait_for_vblank() is only
1001          * called during modeset at which time the GPU should be idle and
1002          * should *not* be performing page flips and thus not waiting on
1003          * vblanks...
1004          * Currently, the result of us stealing a vblank from the irq
1005          * handler is that a single frame will be skipped during swapbuffers.
1006          */
1007         I915_WRITE(pipestat_reg,
1008                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
1009
1010         /* Wait for vblank interrupt bit to set */
1011         if (wait_for(I915_READ(pipestat_reg) &
1012                      PIPE_VBLANK_INTERRUPT_STATUS,
1013                      50))
1014                 DRM_DEBUG_KMS("vblank wait timed out\n");
1015 }
1016
1017 /*
1018  * intel_wait_for_pipe_off - wait for pipe to turn off
1019  * @dev: drm device
1020  * @pipe: pipe to wait for
1021  *
1022  * After disabling a pipe, we can't wait for vblank in the usual way,
1023  * spinning on the vblank interrupt status bit, since we won't actually
1024  * see an interrupt when the pipe is disabled.
1025  *
1026  * On Gen4 and above:
1027  *   wait for the pipe register state bit to turn off
1028  *
1029  * Otherwise:
1030  *   wait for the display line value to settle (it usually
1031  *   ends up stopping at the start of the next frame).
1032  *
1033  */
1034 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1035 {
1036         struct drm_i915_private *dev_priv = dev->dev_private;
1037
1038         if (INTEL_INFO(dev)->gen >= 4) {
1039                 int reg = PIPECONF(pipe);
1040
1041                 /* Wait for the Pipe State to go off */
1042                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1043                              100))
1044                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
1045         } else {
1046                 u32 last_line;
1047                 int reg = PIPEDSL(pipe);
1048                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1049
1050                 /* Wait for the display line to settle */
1051                 do {
1052                         last_line = I915_READ(reg) & DSL_LINEMASK;
1053                         mdelay(5);
1054                 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
1055                          time_after(timeout, jiffies));
1056                 if (time_after(jiffies, timeout))
1057                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
1058         }
1059 }
1060
1061 static const char *state_string(bool enabled)
1062 {
1063         return enabled ? "on" : "off";
1064 }
1065
1066 /* Only for pre-ILK configs */
1067 static void assert_pll(struct drm_i915_private *dev_priv,
1068                        enum pipe pipe, bool state)
1069 {
1070         int reg;
1071         u32 val;
1072         bool cur_state;
1073
1074         reg = DPLL(pipe);
1075         val = I915_READ(reg);
1076         cur_state = !!(val & DPLL_VCO_ENABLE);
1077         WARN(cur_state != state,
1078              "PLL state assertion failure (expected %s, current %s)\n",
1079              state_string(state), state_string(cur_state));
1080 }
1081 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1082 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1083
1084 /* For ILK+ */
1085 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1086                            enum pipe pipe, bool state)
1087 {
1088         int reg;
1089         u32 val;
1090         bool cur_state;
1091
1092         reg = PCH_DPLL(pipe);
1093         val = I915_READ(reg);
1094         cur_state = !!(val & DPLL_VCO_ENABLE);
1095         WARN(cur_state != state,
1096              "PCH PLL state assertion failure (expected %s, current %s)\n",
1097              state_string(state), state_string(cur_state));
1098 }
1099 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
1100 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
1101
1102 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1103                           enum pipe pipe, bool state)
1104 {
1105         int reg;
1106         u32 val;
1107         bool cur_state;
1108
1109         reg = FDI_TX_CTL(pipe);
1110         val = I915_READ(reg);
1111         cur_state = !!(val & FDI_TX_ENABLE);
1112         WARN(cur_state != state,
1113              "FDI TX state assertion failure (expected %s, current %s)\n",
1114              state_string(state), state_string(cur_state));
1115 }
1116 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1117 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1118
1119 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1120                           enum pipe pipe, bool state)
1121 {
1122         int reg;
1123         u32 val;
1124         bool cur_state;
1125
1126         reg = FDI_RX_CTL(pipe);
1127         val = I915_READ(reg);
1128         cur_state = !!(val & FDI_RX_ENABLE);
1129         WARN(cur_state != state,
1130              "FDI RX state assertion failure (expected %s, current %s)\n",
1131              state_string(state), state_string(cur_state));
1132 }
1133 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1134 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1135
1136 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1137                                       enum pipe pipe)
1138 {
1139         int reg;
1140         u32 val;
1141
1142         /* ILK FDI PLL is always enabled */
1143         if (dev_priv->info->gen == 5)
1144                 return;
1145
1146         reg = FDI_TX_CTL(pipe);
1147         val = I915_READ(reg);
1148         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1149 }
1150
1151 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1152                                       enum pipe pipe)
1153 {
1154         int reg;
1155         u32 val;
1156
1157         reg = FDI_RX_CTL(pipe);
1158         val = I915_READ(reg);
1159         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1160 }
1161
1162 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1163                                   enum pipe pipe)
1164 {
1165         int pp_reg, lvds_reg;
1166         u32 val;
1167         enum pipe panel_pipe = PIPE_A;
1168         bool locked = locked;
1169
1170         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1171                 pp_reg = PCH_PP_CONTROL;
1172                 lvds_reg = PCH_LVDS;
1173         } else {
1174                 pp_reg = PP_CONTROL;
1175                 lvds_reg = LVDS;
1176         }
1177
1178         val = I915_READ(pp_reg);
1179         if (!(val & PANEL_POWER_ON) ||
1180             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1181                 locked = false;
1182
1183         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1184                 panel_pipe = PIPE_B;
1185
1186         WARN(panel_pipe == pipe && locked,
1187              "panel assertion failure, pipe %c regs locked\n",
1188              pipe ? 'B' : 'A');
1189 }
1190
1191 static void assert_pipe(struct drm_i915_private *dev_priv,
1192                         enum pipe pipe, bool state)
1193 {
1194         int reg;
1195         u32 val;
1196         bool cur_state;
1197
1198         reg = PIPECONF(pipe);
1199         val = I915_READ(reg);
1200         cur_state = !!(val & PIPECONF_ENABLE);
1201         WARN(cur_state != state,
1202              "pipe %c assertion failure (expected %s, current %s)\n",
1203              pipe ? 'B' : 'A', state_string(state), state_string(cur_state));
1204 }
1205 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1206 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1207
1208 static void assert_plane_enabled(struct drm_i915_private *dev_priv,
1209                                  enum plane plane)
1210 {
1211         int reg;
1212         u32 val;
1213
1214         reg = DSPCNTR(plane);
1215         val = I915_READ(reg);
1216         WARN(!(val & DISPLAY_PLANE_ENABLE),
1217              "plane %c assertion failure, should be active but is disabled\n",
1218              plane ? 'B' : 'A');
1219 }
1220
1221 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1222                                    enum pipe pipe)
1223 {
1224         int reg, i;
1225         u32 val;
1226         int cur_pipe;
1227
1228         /* Need to check both planes against the pipe */
1229         for (i = 0; i < 2; i++) {
1230                 reg = DSPCNTR(i);
1231                 val = I915_READ(reg);
1232                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1233                         DISPPLANE_SEL_PIPE_SHIFT;
1234                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1235                      "plane %d assertion failure, should be off on pipe %c but is still active\n",
1236                      i, pipe ? 'B' : 'A');
1237         }
1238 }
1239
1240 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1241 {
1242         u32 val;
1243         bool enabled;
1244
1245         val = I915_READ(PCH_DREF_CONTROL);
1246         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1247                             DREF_SUPERSPREAD_SOURCE_MASK));
1248         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1249 }
1250
1251 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1252                                        enum pipe pipe)
1253 {
1254         int reg;
1255         u32 val;
1256         bool enabled;
1257
1258         reg = TRANSCONF(pipe);
1259         val = I915_READ(reg);
1260         enabled = !!(val & TRANS_ENABLE);
1261         WARN(enabled, "transcoder assertion failed, should be off on pipe %c but is still active\n", pipe ? 'B' :'A');
1262 }
1263
1264 /**
1265  * intel_enable_pll - enable a PLL
1266  * @dev_priv: i915 private structure
1267  * @pipe: pipe PLL to enable
1268  *
1269  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1270  * make sure the PLL reg is writable first though, since the panel write
1271  * protect mechanism may be enabled.
1272  *
1273  * Note!  This is for pre-ILK only.
1274  */
1275 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1276 {
1277         int reg;
1278         u32 val;
1279
1280         /* No really, not for ILK+ */
1281         BUG_ON(dev_priv->info->gen >= 5);
1282
1283         /* PLL is protected by panel, make sure we can write it */
1284         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1285                 assert_panel_unlocked(dev_priv, pipe);
1286
1287         reg = DPLL(pipe);
1288         val = I915_READ(reg);
1289         val |= DPLL_VCO_ENABLE;
1290
1291         /* We do this three times for luck */
1292         I915_WRITE(reg, val);
1293         POSTING_READ(reg);
1294         udelay(150); /* wait for warmup */
1295         I915_WRITE(reg, val);
1296         POSTING_READ(reg);
1297         udelay(150); /* wait for warmup */
1298         I915_WRITE(reg, val);
1299         POSTING_READ(reg);
1300         udelay(150); /* wait for warmup */
1301 }
1302
1303 /**
1304  * intel_disable_pll - disable a PLL
1305  * @dev_priv: i915 private structure
1306  * @pipe: pipe PLL to disable
1307  *
1308  * Disable the PLL for @pipe, making sure the pipe is off first.
1309  *
1310  * Note!  This is for pre-ILK only.
1311  */
1312 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1313 {
1314         int reg;
1315         u32 val;
1316
1317         /* Don't disable pipe A or pipe A PLLs if needed */
1318         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1319                 return;
1320
1321         /* Make sure the pipe isn't still relying on us */
1322         assert_pipe_disabled(dev_priv, pipe);
1323
1324         reg = DPLL(pipe);
1325         val = I915_READ(reg);
1326         val &= ~DPLL_VCO_ENABLE;
1327         I915_WRITE(reg, val);
1328         POSTING_READ(reg);
1329 }
1330
1331 /**
1332  * intel_enable_pch_pll - enable PCH PLL
1333  * @dev_priv: i915 private structure
1334  * @pipe: pipe PLL to enable
1335  *
1336  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1337  * drives the transcoder clock.
1338  */
1339 static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1340                                  enum pipe pipe)
1341 {
1342         int reg;
1343         u32 val;
1344
1345         /* PCH only available on ILK+ */
1346         BUG_ON(dev_priv->info->gen < 5);
1347
1348         /* PCH refclock must be enabled first */
1349         assert_pch_refclk_enabled(dev_priv);
1350
1351         reg = PCH_DPLL(pipe);
1352         val = I915_READ(reg);
1353         val |= DPLL_VCO_ENABLE;
1354         I915_WRITE(reg, val);
1355         POSTING_READ(reg);
1356         udelay(200);
1357 }
1358
1359 static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1360                                   enum pipe pipe)
1361 {
1362         int reg;
1363         u32 val;
1364
1365         /* PCH only available on ILK+ */
1366         BUG_ON(dev_priv->info->gen < 5);
1367
1368         /* Make sure transcoder isn't still depending on us */
1369         assert_transcoder_disabled(dev_priv, pipe);
1370
1371         reg = PCH_DPLL(pipe);
1372         val = I915_READ(reg);
1373         val &= ~DPLL_VCO_ENABLE;
1374         I915_WRITE(reg, val);
1375         POSTING_READ(reg);
1376         udelay(200);
1377 }
1378
1379 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1380                                     enum pipe pipe)
1381 {
1382         int reg;
1383         u32 val;
1384
1385         /* PCH only available on ILK+ */
1386         BUG_ON(dev_priv->info->gen < 5);
1387
1388         /* Make sure PCH DPLL is enabled */
1389         assert_pch_pll_enabled(dev_priv, pipe);
1390
1391         /* FDI must be feeding us bits for PCH ports */
1392         assert_fdi_tx_enabled(dev_priv, pipe);
1393         assert_fdi_rx_enabled(dev_priv, pipe);
1394
1395         reg = TRANSCONF(pipe);
1396         val = I915_READ(reg);
1397         /*
1398          * make the BPC in transcoder be consistent with
1399          * that in pipeconf reg.
1400          */
1401         val &= ~PIPE_BPC_MASK;
1402         val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
1403         I915_WRITE(reg, val | TRANS_ENABLE);
1404         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1405                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1406 }
1407
1408 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1409                                      enum pipe pipe)
1410 {
1411         int reg;
1412         u32 val;
1413
1414         /* FDI relies on the transcoder */
1415         assert_fdi_tx_disabled(dev_priv, pipe);
1416         assert_fdi_rx_disabled(dev_priv, pipe);
1417
1418         reg = TRANSCONF(pipe);
1419         val = I915_READ(reg);
1420         val &= ~TRANS_ENABLE;
1421         I915_WRITE(reg, val);
1422         /* wait for PCH transcoder off, transcoder state */
1423         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1424                 DRM_ERROR("failed to disable transcoder\n");
1425 }
1426
1427 /**
1428  * intel_enable_pipe - enable a pipe, assertiing requirements
1429  * @dev_priv: i915 private structure
1430  * @pipe: pipe to enable
1431  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1432  *
1433  * Enable @pipe, making sure that various hardware specific requirements
1434  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1435  *
1436  * @pipe should be %PIPE_A or %PIPE_B.
1437  *
1438  * Will wait until the pipe is actually running (i.e. first vblank) before
1439  * returning.
1440  */
1441 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1442                               bool pch_port)
1443 {
1444         int reg;
1445         u32 val;
1446
1447         /*
1448          * A pipe without a PLL won't actually be able to drive bits from
1449          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1450          * need the check.
1451          */
1452         if (!HAS_PCH_SPLIT(dev_priv->dev))
1453                 assert_pll_enabled(dev_priv, pipe);
1454         else {
1455                 if (pch_port) {
1456                         /* if driving the PCH, we need FDI enabled */
1457                         assert_fdi_rx_pll_enabled(dev_priv, pipe);
1458                         assert_fdi_tx_pll_enabled(dev_priv, pipe);
1459                 }
1460                 /* FIXME: assert CPU port conditions for SNB+ */
1461         }
1462
1463         reg = PIPECONF(pipe);
1464         val = I915_READ(reg);
1465         val |= PIPECONF_ENABLE;
1466         I915_WRITE(reg, val);
1467         POSTING_READ(reg);
1468         intel_wait_for_vblank(dev_priv->dev, pipe);
1469 }
1470
1471 /**
1472  * intel_disable_pipe - disable a pipe, assertiing requirements
1473  * @dev_priv: i915 private structure
1474  * @pipe: pipe to disable
1475  *
1476  * Disable @pipe, making sure that various hardware specific requirements
1477  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1478  *
1479  * @pipe should be %PIPE_A or %PIPE_B.
1480  *
1481  * Will wait until the pipe has shut down before returning.
1482  */
1483 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1484                                enum pipe pipe)
1485 {
1486         int reg;
1487         u32 val;
1488
1489         /*
1490          * Make sure planes won't keep trying to pump pixels to us,
1491          * or we might hang the display.
1492          */
1493         assert_planes_disabled(dev_priv, pipe);
1494
1495         /* Don't disable pipe A or pipe A PLLs if needed */
1496         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1497                 return;
1498
1499         reg = PIPECONF(pipe);
1500         val = I915_READ(reg);
1501         val &= ~PIPECONF_ENABLE;
1502         I915_WRITE(reg, val);
1503         POSTING_READ(reg);
1504         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1505 }
1506
1507 /**
1508  * intel_enable_plane - enable a display plane on a given pipe
1509  * @dev_priv: i915 private structure
1510  * @plane: plane to enable
1511  * @pipe: pipe being fed
1512  *
1513  * Enable @plane on @pipe, making sure that @pipe is running first.
1514  */
1515 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1516                                enum plane plane, enum pipe pipe)
1517 {
1518         int reg;
1519         u32 val;
1520
1521         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1522         assert_pipe_enabled(dev_priv, pipe);
1523
1524         reg = DSPCNTR(plane);
1525         val = I915_READ(reg);
1526         val |= DISPLAY_PLANE_ENABLE;
1527         I915_WRITE(reg, val);
1528         POSTING_READ(reg);
1529         intel_wait_for_vblank(dev_priv->dev, pipe);
1530 }
1531
1532 /*
1533  * Plane regs are double buffered, going from enabled->disabled needs a
1534  * trigger in order to latch.  The display address reg provides this.
1535  */
1536 static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1537                                       enum plane plane)
1538 {
1539         u32 reg = DSPADDR(plane);
1540         I915_WRITE(reg, I915_READ(reg));
1541 }
1542
1543 /**
1544  * intel_disable_plane - disable a display plane
1545  * @dev_priv: i915 private structure
1546  * @plane: plane to disable
1547  * @pipe: pipe consuming the data
1548  *
1549  * Disable @plane; should be an independent operation.
1550  */
1551 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1552                                 enum plane plane, enum pipe pipe)
1553 {
1554         int reg;
1555         u32 val;
1556
1557         reg = DSPCNTR(plane);
1558         val = I915_READ(reg);
1559         val &= ~DISPLAY_PLANE_ENABLE;
1560         I915_WRITE(reg, val);
1561         POSTING_READ(reg);
1562         intel_flush_display_plane(dev_priv, plane);
1563         intel_wait_for_vblank(dev_priv->dev, pipe);
1564 }
1565
1566 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1567 {
1568         struct drm_device *dev = crtc->dev;
1569         struct drm_i915_private *dev_priv = dev->dev_private;
1570         struct drm_framebuffer *fb = crtc->fb;
1571         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1572         struct drm_i915_gem_object *obj = intel_fb->obj;
1573         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1574         int plane, i;
1575         u32 fbc_ctl, fbc_ctl2;
1576
1577         if (fb->pitch == dev_priv->cfb_pitch &&
1578             obj->fence_reg == dev_priv->cfb_fence &&
1579             intel_crtc->plane == dev_priv->cfb_plane &&
1580             I915_READ(FBC_CONTROL) & FBC_CTL_EN)
1581                 return;
1582
1583         i8xx_disable_fbc(dev);
1584
1585         dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1586
1587         if (fb->pitch < dev_priv->cfb_pitch)
1588                 dev_priv->cfb_pitch = fb->pitch;
1589
1590         /* FBC_CTL wants 64B units */
1591         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1592         dev_priv->cfb_fence = obj->fence_reg;
1593         dev_priv->cfb_plane = intel_crtc->plane;
1594         plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1595
1596         /* Clear old tags */
1597         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1598                 I915_WRITE(FBC_TAG + (i * 4), 0);
1599
1600         /* Set it up... */
1601         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1602         if (obj->tiling_mode != I915_TILING_NONE)
1603                 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1604         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1605         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1606
1607         /* enable it... */
1608         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1609         if (IS_I945GM(dev))
1610                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1611         fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1612         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1613         if (obj->tiling_mode != I915_TILING_NONE)
1614                 fbc_ctl |= dev_priv->cfb_fence;
1615         I915_WRITE(FBC_CONTROL, fbc_ctl);
1616
1617         DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1618                       dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1619 }
1620
1621 void i8xx_disable_fbc(struct drm_device *dev)
1622 {
1623         struct drm_i915_private *dev_priv = dev->dev_private;
1624         u32 fbc_ctl;
1625
1626         /* Disable compression */
1627         fbc_ctl = I915_READ(FBC_CONTROL);
1628         if ((fbc_ctl & FBC_CTL_EN) == 0)
1629                 return;
1630
1631         fbc_ctl &= ~FBC_CTL_EN;
1632         I915_WRITE(FBC_CONTROL, fbc_ctl);
1633
1634         /* Wait for compressing bit to clear */
1635         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1636                 DRM_DEBUG_KMS("FBC idle timed out\n");
1637                 return;
1638         }
1639
1640         DRM_DEBUG_KMS("disabled FBC\n");
1641 }
1642
1643 static bool i8xx_fbc_enabled(struct drm_device *dev)
1644 {
1645         struct drm_i915_private *dev_priv = dev->dev_private;
1646
1647         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1648 }
1649
1650 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1651 {
1652         struct drm_device *dev = crtc->dev;
1653         struct drm_i915_private *dev_priv = dev->dev_private;
1654         struct drm_framebuffer *fb = crtc->fb;
1655         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1656         struct drm_i915_gem_object *obj = intel_fb->obj;
1657         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1658         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1659         unsigned long stall_watermark = 200;
1660         u32 dpfc_ctl;
1661
1662         dpfc_ctl = I915_READ(DPFC_CONTROL);
1663         if (dpfc_ctl & DPFC_CTL_EN) {
1664                 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
1665                     dev_priv->cfb_fence == obj->fence_reg &&
1666                     dev_priv->cfb_plane == intel_crtc->plane &&
1667                     dev_priv->cfb_y == crtc->y)
1668                         return;
1669
1670                 I915_WRITE(DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1671                 POSTING_READ(DPFC_CONTROL);
1672                 intel_wait_for_vblank(dev, intel_crtc->pipe);
1673         }
1674
1675         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1676         dev_priv->cfb_fence = obj->fence_reg;
1677         dev_priv->cfb_plane = intel_crtc->plane;
1678         dev_priv->cfb_y = crtc->y;
1679
1680         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1681         if (obj->tiling_mode != I915_TILING_NONE) {
1682                 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1683                 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1684         } else {
1685                 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1686         }
1687
1688         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1689                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1690                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1691         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1692
1693         /* enable it... */
1694         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1695
1696         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1697 }
1698
1699 void g4x_disable_fbc(struct drm_device *dev)
1700 {
1701         struct drm_i915_private *dev_priv = dev->dev_private;
1702         u32 dpfc_ctl;
1703
1704         /* Disable compression */
1705         dpfc_ctl = I915_READ(DPFC_CONTROL);
1706         if (dpfc_ctl & DPFC_CTL_EN) {
1707                 dpfc_ctl &= ~DPFC_CTL_EN;
1708                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1709
1710                 DRM_DEBUG_KMS("disabled FBC\n");
1711         }
1712 }
1713
1714 static bool g4x_fbc_enabled(struct drm_device *dev)
1715 {
1716         struct drm_i915_private *dev_priv = dev->dev_private;
1717
1718         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1719 }
1720
1721 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1722 {
1723         struct drm_device *dev = crtc->dev;
1724         struct drm_i915_private *dev_priv = dev->dev_private;
1725         struct drm_framebuffer *fb = crtc->fb;
1726         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1727         struct drm_i915_gem_object *obj = intel_fb->obj;
1728         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1729         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1730         unsigned long stall_watermark = 200;
1731         u32 dpfc_ctl;
1732
1733         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1734         if (dpfc_ctl & DPFC_CTL_EN) {
1735                 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
1736                     dev_priv->cfb_fence == obj->fence_reg &&
1737                     dev_priv->cfb_plane == intel_crtc->plane &&
1738                     dev_priv->cfb_offset == obj->gtt_offset &&
1739                     dev_priv->cfb_y == crtc->y)
1740                         return;
1741
1742                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1743                 POSTING_READ(ILK_DPFC_CONTROL);
1744                 intel_wait_for_vblank(dev, intel_crtc->pipe);
1745         }
1746
1747         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1748         dev_priv->cfb_fence = obj->fence_reg;
1749         dev_priv->cfb_plane = intel_crtc->plane;
1750         dev_priv->cfb_offset = obj->gtt_offset;
1751         dev_priv->cfb_y = crtc->y;
1752
1753         dpfc_ctl &= DPFC_RESERVED;
1754         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1755         if (obj->tiling_mode != I915_TILING_NONE) {
1756                 dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
1757                 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1758         } else {
1759                 I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1760         }
1761
1762         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1763                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1764                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1765         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1766         I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
1767         /* enable it... */
1768         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1769
1770         if (IS_GEN6(dev)) {
1771                 I915_WRITE(SNB_DPFC_CTL_SA,
1772                            SNB_CPU_FENCE_ENABLE | dev_priv->cfb_fence);
1773                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
1774         }
1775
1776         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1777 }
1778
1779 void ironlake_disable_fbc(struct drm_device *dev)
1780 {
1781         struct drm_i915_private *dev_priv = dev->dev_private;
1782         u32 dpfc_ctl;
1783
1784         /* Disable compression */
1785         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1786         if (dpfc_ctl & DPFC_CTL_EN) {
1787                 dpfc_ctl &= ~DPFC_CTL_EN;
1788                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1789
1790                 DRM_DEBUG_KMS("disabled FBC\n");
1791         }
1792 }
1793
1794 static bool ironlake_fbc_enabled(struct drm_device *dev)
1795 {
1796         struct drm_i915_private *dev_priv = dev->dev_private;
1797
1798         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1799 }
1800
1801 bool intel_fbc_enabled(struct drm_device *dev)
1802 {
1803         struct drm_i915_private *dev_priv = dev->dev_private;
1804
1805         if (!dev_priv->display.fbc_enabled)
1806                 return false;
1807
1808         return dev_priv->display.fbc_enabled(dev);
1809 }
1810
1811 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1812 {
1813         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1814
1815         if (!dev_priv->display.enable_fbc)
1816                 return;
1817
1818         dev_priv->display.enable_fbc(crtc, interval);
1819 }
1820
1821 void intel_disable_fbc(struct drm_device *dev)
1822 {
1823         struct drm_i915_private *dev_priv = dev->dev_private;
1824
1825         if (!dev_priv->display.disable_fbc)
1826                 return;
1827
1828         dev_priv->display.disable_fbc(dev);
1829 }
1830
1831 /**
1832  * intel_update_fbc - enable/disable FBC as needed
1833  * @dev: the drm_device
1834  *
1835  * Set up the framebuffer compression hardware at mode set time.  We
1836  * enable it if possible:
1837  *   - plane A only (on pre-965)
1838  *   - no pixel mulitply/line duplication
1839  *   - no alpha buffer discard
1840  *   - no dual wide
1841  *   - framebuffer <= 2048 in width, 1536 in height
1842  *
1843  * We can't assume that any compression will take place (worst case),
1844  * so the compressed buffer has to be the same size as the uncompressed
1845  * one.  It also must reside (along with the line length buffer) in
1846  * stolen memory.
1847  *
1848  * We need to enable/disable FBC on a global basis.
1849  */
1850 static void intel_update_fbc(struct drm_device *dev)
1851 {
1852         struct drm_i915_private *dev_priv = dev->dev_private;
1853         struct drm_crtc *crtc = NULL, *tmp_crtc;
1854         struct intel_crtc *intel_crtc;
1855         struct drm_framebuffer *fb;
1856         struct intel_framebuffer *intel_fb;
1857         struct drm_i915_gem_object *obj;
1858
1859         DRM_DEBUG_KMS("\n");
1860
1861         if (!i915_powersave)
1862                 return;
1863
1864         if (!I915_HAS_FBC(dev))
1865                 return;
1866
1867         /*
1868          * If FBC is already on, we just have to verify that we can
1869          * keep it that way...
1870          * Need to disable if:
1871          *   - more than one pipe is active
1872          *   - changing FBC params (stride, fence, mode)
1873          *   - new fb is too large to fit in compressed buffer
1874          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1875          */
1876         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1877                 if (tmp_crtc->enabled) {
1878                         if (crtc) {
1879                                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1880                                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1881                                 goto out_disable;
1882                         }
1883                         crtc = tmp_crtc;
1884                 }
1885         }
1886
1887         if (!crtc || crtc->fb == NULL) {
1888                 DRM_DEBUG_KMS("no output, disabling\n");
1889                 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1890                 goto out_disable;
1891         }
1892
1893         intel_crtc = to_intel_crtc(crtc);
1894         fb = crtc->fb;
1895         intel_fb = to_intel_framebuffer(fb);
1896         obj = intel_fb->obj;
1897
1898         if (intel_fb->obj->base.size > dev_priv->cfb_size) {
1899                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1900                               "compression\n");
1901                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1902                 goto out_disable;
1903         }
1904         if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1905             (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1906                 DRM_DEBUG_KMS("mode incompatible with compression, "
1907                               "disabling\n");
1908                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1909                 goto out_disable;
1910         }
1911         if ((crtc->mode.hdisplay > 2048) ||
1912             (crtc->mode.vdisplay > 1536)) {
1913                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1914                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1915                 goto out_disable;
1916         }
1917         if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1918                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1919                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1920                 goto out_disable;
1921         }
1922         if (obj->tiling_mode != I915_TILING_X) {
1923                 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1924                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1925                 goto out_disable;
1926         }
1927
1928         /* If the kernel debugger is active, always disable compression */
1929         if (in_dbg_master())
1930                 goto out_disable;
1931
1932         intel_enable_fbc(crtc, 500);
1933         return;
1934
1935 out_disable:
1936         /* Multiple disables should be harmless */
1937         if (intel_fbc_enabled(dev)) {
1938                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1939                 intel_disable_fbc(dev);
1940         }
1941 }
1942
1943 int
1944 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1945                            struct drm_i915_gem_object *obj,
1946                            struct intel_ring_buffer *pipelined)
1947 {
1948         u32 alignment;
1949         int ret;
1950
1951         switch (obj->tiling_mode) {
1952         case I915_TILING_NONE:
1953                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1954                         alignment = 128 * 1024;
1955                 else if (INTEL_INFO(dev)->gen >= 4)
1956                         alignment = 4 * 1024;
1957                 else
1958                         alignment = 64 * 1024;
1959                 break;
1960         case I915_TILING_X:
1961                 /* pin() will align the object as required by fence */
1962                 alignment = 0;
1963                 break;
1964         case I915_TILING_Y:
1965                 /* FIXME: Is this true? */
1966                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1967                 return -EINVAL;
1968         default:
1969                 BUG();
1970         }
1971
1972         ret = i915_gem_object_pin(obj, alignment, true);
1973         if (ret)
1974                 return ret;
1975
1976         ret = i915_gem_object_set_to_display_plane(obj, pipelined);
1977         if (ret)
1978                 goto err_unpin;
1979
1980         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1981          * fence, whereas 965+ only requires a fence if using
1982          * framebuffer compression.  For simplicity, we always install
1983          * a fence as the cost is not that onerous.
1984          */
1985         if (obj->tiling_mode != I915_TILING_NONE) {
1986                 ret = i915_gem_object_get_fence(obj, pipelined, false);
1987                 if (ret)
1988                         goto err_unpin;
1989         }
1990
1991         return 0;
1992
1993 err_unpin:
1994         i915_gem_object_unpin(obj);
1995         return ret;
1996 }
1997
1998 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1999 static int
2000 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2001                            int x, int y, enum mode_set_atomic state)
2002 {
2003         struct drm_device *dev = crtc->dev;
2004         struct drm_i915_private *dev_priv = dev->dev_private;
2005         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2006         struct intel_framebuffer *intel_fb;
2007         struct drm_i915_gem_object *obj;
2008         int plane = intel_crtc->plane;
2009         unsigned long Start, Offset;
2010         u32 dspcntr;
2011         u32 reg;
2012
2013         switch (plane) {
2014         case 0:
2015         case 1:
2016                 break;
2017         default:
2018                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2019                 return -EINVAL;
2020         }
2021
2022         intel_fb = to_intel_framebuffer(fb);
2023         obj = intel_fb->obj;
2024
2025         reg = DSPCNTR(plane);
2026         dspcntr = I915_READ(reg);
2027         /* Mask out pixel format bits in case we change it */
2028         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2029         switch (fb->bits_per_pixel) {
2030         case 8:
2031                 dspcntr |= DISPPLANE_8BPP;
2032                 break;
2033         case 16:
2034                 if (fb->depth == 15)
2035                         dspcntr |= DISPPLANE_15_16BPP;
2036                 else
2037                         dspcntr |= DISPPLANE_16BPP;
2038                 break;
2039         case 24:
2040         case 32:
2041                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2042                 break;
2043         default:
2044                 DRM_ERROR("Unknown color depth\n");
2045                 return -EINVAL;
2046         }
2047         if (INTEL_INFO(dev)->gen >= 4) {
2048                 if (obj->tiling_mode != I915_TILING_NONE)
2049                         dspcntr |= DISPPLANE_TILED;
2050                 else
2051                         dspcntr &= ~DISPPLANE_TILED;
2052         }
2053
2054         if (HAS_PCH_SPLIT(dev))
2055                 /* must disable */
2056                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2057
2058         I915_WRITE(reg, dspcntr);
2059
2060         Start = obj->gtt_offset;
2061         Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
2062
2063         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2064                       Start, Offset, x, y, fb->pitch);
2065         I915_WRITE(DSPSTRIDE(plane), fb->pitch);
2066         if (INTEL_INFO(dev)->gen >= 4) {
2067                 I915_WRITE(DSPSURF(plane), Start);
2068                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2069                 I915_WRITE(DSPADDR(plane), Offset);
2070         } else
2071                 I915_WRITE(DSPADDR(plane), Start + Offset);
2072         POSTING_READ(reg);
2073
2074         intel_update_fbc(dev);
2075         intel_increase_pllclock(crtc);
2076
2077         return 0;
2078 }
2079
2080 static int
2081 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2082                     struct drm_framebuffer *old_fb)
2083 {
2084         struct drm_device *dev = crtc->dev;
2085         struct drm_i915_master_private *master_priv;
2086         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2087         int ret;
2088
2089         /* no fb bound */
2090         if (!crtc->fb) {
2091                 DRM_DEBUG_KMS("No FB bound\n");
2092                 return 0;
2093         }
2094
2095         switch (intel_crtc->plane) {
2096         case 0:
2097         case 1:
2098                 break;
2099         default:
2100                 return -EINVAL;
2101         }
2102
2103         mutex_lock(&dev->struct_mutex);
2104         ret = intel_pin_and_fence_fb_obj(dev,
2105                                          to_intel_framebuffer(crtc->fb)->obj,
2106                                          NULL);
2107         if (ret != 0) {
2108                 mutex_unlock(&dev->struct_mutex);
2109                 return ret;
2110         }
2111
2112         if (old_fb) {
2113                 struct drm_i915_private *dev_priv = dev->dev_private;
2114                 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2115
2116                 wait_event(dev_priv->pending_flip_queue,
2117                            atomic_read(&obj->pending_flip) == 0);
2118
2119                 /* Big Hammer, we also need to ensure that any pending
2120                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2121                  * current scanout is retired before unpinning the old
2122                  * framebuffer.
2123                  */
2124                 ret = i915_gem_object_flush_gpu(obj, false);
2125                 if (ret) {
2126                         i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
2127                         mutex_unlock(&dev->struct_mutex);
2128                         return ret;
2129                 }
2130         }
2131
2132         ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2133                                          LEAVE_ATOMIC_MODE_SET);
2134         if (ret) {
2135                 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
2136                 mutex_unlock(&dev->struct_mutex);
2137                 return ret;
2138         }
2139
2140         if (old_fb) {
2141                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2142                 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
2143         }
2144
2145         mutex_unlock(&dev->struct_mutex);
2146
2147         if (!dev->primary->master)
2148                 return 0;
2149
2150         master_priv = dev->primary->master->driver_priv;
2151         if (!master_priv->sarea_priv)
2152                 return 0;
2153
2154         if (intel_crtc->pipe) {
2155                 master_priv->sarea_priv->pipeB_x = x;
2156                 master_priv->sarea_priv->pipeB_y = y;
2157         } else {
2158                 master_priv->sarea_priv->pipeA_x = x;
2159                 master_priv->sarea_priv->pipeA_y = y;
2160         }
2161
2162         return 0;
2163 }
2164
2165 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2166 {
2167         struct drm_device *dev = crtc->dev;
2168         struct drm_i915_private *dev_priv = dev->dev_private;
2169         u32 dpa_ctl;
2170
2171         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2172         dpa_ctl = I915_READ(DP_A);
2173         dpa_ctl &= ~DP_PLL_FREQ_MASK;
2174
2175         if (clock < 200000) {
2176                 u32 temp;
2177                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2178                 /* workaround for 160Mhz:
2179                    1) program 0x4600c bits 15:0 = 0x8124
2180                    2) program 0x46010 bit 0 = 1
2181                    3) program 0x46034 bit 24 = 1
2182                    4) program 0x64000 bit 14 = 1
2183                    */
2184                 temp = I915_READ(0x4600c);
2185                 temp &= 0xffff0000;
2186                 I915_WRITE(0x4600c, temp | 0x8124);
2187
2188                 temp = I915_READ(0x46010);
2189                 I915_WRITE(0x46010, temp | 1);
2190
2191                 temp = I915_READ(0x46034);
2192                 I915_WRITE(0x46034, temp | (1 << 24));
2193         } else {
2194                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2195         }
2196         I915_WRITE(DP_A, dpa_ctl);
2197
2198         POSTING_READ(DP_A);
2199         udelay(500);
2200 }
2201
2202 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2203 {
2204         struct drm_device *dev = crtc->dev;
2205         struct drm_i915_private *dev_priv = dev->dev_private;
2206         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2207         int pipe = intel_crtc->pipe;
2208         u32 reg, temp;
2209
2210         /* enable normal train */
2211         reg = FDI_TX_CTL(pipe);
2212         temp = I915_READ(reg);
2213         temp &= ~FDI_LINK_TRAIN_NONE;
2214         temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2215         I915_WRITE(reg, temp);
2216
2217         reg = FDI_RX_CTL(pipe);
2218         temp = I915_READ(reg);
2219         if (HAS_PCH_CPT(dev)) {
2220                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2221                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2222         } else {
2223                 temp &= ~FDI_LINK_TRAIN_NONE;
2224                 temp |= FDI_LINK_TRAIN_NONE;
2225         }
2226         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2227
2228         /* wait one idle pattern time */
2229         POSTING_READ(reg);
2230         udelay(1000);
2231 }
2232
2233 /* The FDI link training functions for ILK/Ibexpeak. */
2234 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2235 {
2236         struct drm_device *dev = crtc->dev;
2237         struct drm_i915_private *dev_priv = dev->dev_private;
2238         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2239         int pipe = intel_crtc->pipe;
2240         u32 reg, temp, tries;
2241
2242         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2243            for train result */
2244         reg = FDI_RX_IMR(pipe);
2245         temp = I915_READ(reg);
2246         temp &= ~FDI_RX_SYMBOL_LOCK;
2247         temp &= ~FDI_RX_BIT_LOCK;
2248         I915_WRITE(reg, temp);
2249         I915_READ(reg);
2250         udelay(150);
2251
2252         /* enable CPU FDI TX and PCH FDI RX */
2253         reg = FDI_TX_CTL(pipe);
2254         temp = I915_READ(reg);
2255         temp &= ~(7 << 19);
2256         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2257         temp &= ~FDI_LINK_TRAIN_NONE;
2258         temp |= FDI_LINK_TRAIN_PATTERN_1;
2259         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2260
2261         reg = FDI_RX_CTL(pipe);
2262         temp = I915_READ(reg);
2263         temp &= ~FDI_LINK_TRAIN_NONE;
2264         temp |= FDI_LINK_TRAIN_PATTERN_1;
2265         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2266
2267         POSTING_READ(reg);
2268         udelay(150);
2269
2270         /* Ironlake workaround, enable clock pointer after FDI enable*/
2271         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_ENABLE);
2272
2273         reg = FDI_RX_IIR(pipe);
2274         for (tries = 0; tries < 5; tries++) {
2275                 temp = I915_READ(reg);
2276                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2277
2278                 if ((temp & FDI_RX_BIT_LOCK)) {
2279                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2280                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2281                         break;
2282                 }
2283         }
2284         if (tries == 5)
2285                 DRM_ERROR("FDI train 1 fail!\n");
2286
2287         /* Train 2 */
2288         reg = FDI_TX_CTL(pipe);
2289         temp = I915_READ(reg);
2290         temp &= ~FDI_LINK_TRAIN_NONE;
2291         temp |= FDI_LINK_TRAIN_PATTERN_2;
2292         I915_WRITE(reg, temp);
2293
2294         reg = FDI_RX_CTL(pipe);
2295         temp = I915_READ(reg);
2296         temp &= ~FDI_LINK_TRAIN_NONE;
2297         temp |= FDI_LINK_TRAIN_PATTERN_2;
2298         I915_WRITE(reg, temp);
2299
2300         POSTING_READ(reg);
2301         udelay(150);
2302
2303         reg = FDI_RX_IIR(pipe);
2304         for (tries = 0; tries < 5; tries++) {
2305                 temp = I915_READ(reg);
2306                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2307
2308                 if (temp & FDI_RX_SYMBOL_LOCK) {
2309                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2310                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2311                         break;
2312                 }
2313         }
2314         if (tries == 5)
2315                 DRM_ERROR("FDI train 2 fail!\n");
2316
2317         DRM_DEBUG_KMS("FDI train done\n");
2318
2319 }
2320
2321 static const int const snb_b_fdi_train_param [] = {
2322         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2323         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2324         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2325         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2326 };
2327
2328 /* The FDI link training functions for SNB/Cougarpoint. */
2329 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2330 {
2331         struct drm_device *dev = crtc->dev;
2332         struct drm_i915_private *dev_priv = dev->dev_private;
2333         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2334         int pipe = intel_crtc->pipe;
2335         u32 reg, temp, i;
2336
2337         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2338            for train result */
2339         reg = FDI_RX_IMR(pipe);
2340         temp = I915_READ(reg);
2341         temp &= ~FDI_RX_SYMBOL_LOCK;
2342         temp &= ~FDI_RX_BIT_LOCK;
2343         I915_WRITE(reg, temp);
2344
2345         POSTING_READ(reg);
2346         udelay(150);
2347
2348         /* enable CPU FDI TX and PCH FDI RX */
2349         reg = FDI_TX_CTL(pipe);
2350         temp = I915_READ(reg);
2351         temp &= ~(7 << 19);
2352         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2353         temp &= ~FDI_LINK_TRAIN_NONE;
2354         temp |= FDI_LINK_TRAIN_PATTERN_1;
2355         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2356         /* SNB-B */
2357         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2358         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2359
2360         reg = FDI_RX_CTL(pipe);
2361         temp = I915_READ(reg);
2362         if (HAS_PCH_CPT(dev)) {
2363                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2364                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2365         } else {
2366                 temp &= ~FDI_LINK_TRAIN_NONE;
2367                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2368         }
2369         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2370
2371         POSTING_READ(reg);
2372         udelay(150);
2373
2374         for (i = 0; i < 4; i++ ) {
2375                 reg = FDI_TX_CTL(pipe);
2376                 temp = I915_READ(reg);
2377                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2378                 temp |= snb_b_fdi_train_param[i];
2379                 I915_WRITE(reg, temp);
2380
2381                 POSTING_READ(reg);
2382                 udelay(500);
2383
2384                 reg = FDI_RX_IIR(pipe);
2385                 temp = I915_READ(reg);
2386                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2387
2388                 if (temp & FDI_RX_BIT_LOCK) {
2389                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2390                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2391                         break;
2392                 }
2393         }
2394         if (i == 4)
2395                 DRM_ERROR("FDI train 1 fail!\n");
2396
2397         /* Train 2 */
2398         reg = FDI_TX_CTL(pipe);
2399         temp = I915_READ(reg);
2400         temp &= ~FDI_LINK_TRAIN_NONE;
2401         temp |= FDI_LINK_TRAIN_PATTERN_2;
2402         if (IS_GEN6(dev)) {
2403                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2404                 /* SNB-B */
2405                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2406         }
2407         I915_WRITE(reg, temp);
2408
2409         reg = FDI_RX_CTL(pipe);
2410         temp = I915_READ(reg);
2411         if (HAS_PCH_CPT(dev)) {
2412                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2413                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2414         } else {
2415                 temp &= ~FDI_LINK_TRAIN_NONE;
2416                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2417         }
2418         I915_WRITE(reg, temp);
2419
2420         POSTING_READ(reg);
2421         udelay(150);
2422
2423         for (i = 0; i < 4; i++ ) {
2424                 reg = FDI_TX_CTL(pipe);
2425                 temp = I915_READ(reg);
2426                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2427                 temp |= snb_b_fdi_train_param[i];
2428                 I915_WRITE(reg, temp);
2429
2430                 POSTING_READ(reg);
2431                 udelay(500);
2432
2433                 reg = FDI_RX_IIR(pipe);
2434                 temp = I915_READ(reg);
2435                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2436
2437                 if (temp & FDI_RX_SYMBOL_LOCK) {
2438                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2439                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2440                         break;
2441                 }
2442         }
2443         if (i == 4)
2444                 DRM_ERROR("FDI train 2 fail!\n");
2445
2446         DRM_DEBUG_KMS("FDI train done.\n");
2447 }
2448
2449 static void ironlake_fdi_enable(struct drm_crtc *crtc)
2450 {
2451         struct drm_device *dev = crtc->dev;
2452         struct drm_i915_private *dev_priv = dev->dev_private;
2453         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2454         int pipe = intel_crtc->pipe;
2455         u32 reg, temp;
2456
2457         /* Write the TU size bits so error detection works */
2458         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2459                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2460
2461         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2462         reg = FDI_RX_CTL(pipe);
2463         temp = I915_READ(reg);
2464         temp &= ~((0x7 << 19) | (0x7 << 16));
2465         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2466         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2467         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2468
2469         POSTING_READ(reg);
2470         udelay(200);
2471
2472         /* Switch from Rawclk to PCDclk */
2473         temp = I915_READ(reg);
2474         I915_WRITE(reg, temp | FDI_PCDCLK);
2475
2476         POSTING_READ(reg);
2477         udelay(200);
2478
2479         /* Enable CPU FDI TX PLL, always on for Ironlake */
2480         reg = FDI_TX_CTL(pipe);
2481         temp = I915_READ(reg);
2482         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2483                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2484
2485                 POSTING_READ(reg);
2486                 udelay(100);
2487         }
2488 }
2489
2490 /*
2491  * When we disable a pipe, we need to clear any pending scanline wait events
2492  * to avoid hanging the ring, which we assume we are waiting on.
2493  */
2494 static void intel_clear_scanline_wait(struct drm_device *dev)
2495 {
2496         struct drm_i915_private *dev_priv = dev->dev_private;
2497         struct intel_ring_buffer *ring;
2498         u32 tmp;
2499
2500         if (IS_GEN2(dev))
2501                 /* Can't break the hang on i8xx */
2502                 return;
2503
2504         ring = LP_RING(dev_priv);
2505         tmp = I915_READ_CTL(ring);
2506         if (tmp & RING_WAIT)
2507                 I915_WRITE_CTL(ring, tmp);
2508 }
2509
2510 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2511 {
2512         struct drm_i915_gem_object *obj;
2513         struct drm_i915_private *dev_priv;
2514
2515         if (crtc->fb == NULL)
2516                 return;
2517
2518         obj = to_intel_framebuffer(crtc->fb)->obj;
2519         dev_priv = crtc->dev->dev_private;
2520         wait_event(dev_priv->pending_flip_queue,
2521                    atomic_read(&obj->pending_flip) == 0);
2522 }
2523
2524 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2525 {
2526         struct drm_device *dev = crtc->dev;
2527         struct drm_mode_config *mode_config = &dev->mode_config;
2528         struct intel_encoder *encoder;
2529
2530         /*
2531          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2532          * must be driven by its own crtc; no sharing is possible.
2533          */
2534         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2535                 if (encoder->base.crtc != crtc)
2536                         continue;
2537
2538                 switch (encoder->type) {
2539                 case INTEL_OUTPUT_EDP:
2540                         if (!intel_encoder_is_pch_edp(&encoder->base))
2541                                 return false;
2542                         continue;
2543                 }
2544         }
2545
2546         return true;
2547 }
2548
2549 static void ironlake_crtc_enable(struct drm_crtc *crtc)
2550 {
2551         struct drm_device *dev = crtc->dev;
2552         struct drm_i915_private *dev_priv = dev->dev_private;
2553         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2554         int pipe = intel_crtc->pipe;
2555         int plane = intel_crtc->plane;
2556         u32 reg, temp;
2557         bool is_pch_port;
2558
2559         if (intel_crtc->active)
2560                 return;
2561
2562         intel_crtc->active = true;
2563         intel_update_watermarks(dev);
2564
2565         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2566                 temp = I915_READ(PCH_LVDS);
2567                 if ((temp & LVDS_PORT_EN) == 0)
2568                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2569         }
2570
2571         ironlake_fdi_enable(crtc);
2572
2573         /* Enable panel fitting for LVDS */
2574         if (dev_priv->pch_pf_size &&
2575             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2576                 /* Force use of hard-coded filter coefficients
2577                  * as some pre-programmed values are broken,
2578                  * e.g. x201.
2579                  */
2580                 I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1,
2581                            PF_ENABLE | PF_FILTER_MED_3x3);
2582                 I915_WRITE(pipe ? PFB_WIN_POS : PFA_WIN_POS,
2583                            dev_priv->pch_pf_pos);
2584                 I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ,
2585                            dev_priv->pch_pf_size);
2586         }
2587
2588         is_pch_port = intel_crtc_driving_pch(crtc);
2589
2590         intel_enable_pipe(dev_priv, pipe, is_pch_port);
2591         intel_enable_plane(dev_priv, plane, pipe);
2592
2593         /* For PCH output, training FDI link */
2594         if (IS_GEN6(dev))
2595                 gen6_fdi_link_train(crtc);
2596         else
2597                 ironlake_fdi_link_train(crtc);
2598
2599         intel_enable_pch_pll(dev_priv, pipe);
2600
2601         if (HAS_PCH_CPT(dev)) {
2602                 /* Be sure PCH DPLL SEL is set */
2603                 temp = I915_READ(PCH_DPLL_SEL);
2604                 if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
2605                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2606                 else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
2607                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2608                 I915_WRITE(PCH_DPLL_SEL, temp);
2609         }
2610
2611         /* set transcoder timing, panel must allow it */
2612         assert_panel_unlocked(dev_priv, pipe);
2613         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2614         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2615         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
2616
2617         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2618         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2619         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
2620
2621         intel_fdi_normal_train(crtc);
2622
2623         /* For PCH DP, enable TRANS_DP_CTL */
2624         if (HAS_PCH_CPT(dev) &&
2625             intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2626                 reg = TRANS_DP_CTL(pipe);
2627                 temp = I915_READ(reg);
2628                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2629                           TRANS_DP_SYNC_MASK |
2630                           TRANS_DP_BPC_MASK);
2631                 temp |= (TRANS_DP_OUTPUT_ENABLE |
2632                          TRANS_DP_ENH_FRAMING);
2633                 temp |= TRANS_DP_8BPC;
2634
2635                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2636                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2637                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2638                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2639
2640                 switch (intel_trans_dp_port_sel(crtc)) {
2641                 case PCH_DP_B:
2642                         temp |= TRANS_DP_PORT_SEL_B;
2643                         break;
2644                 case PCH_DP_C:
2645                         temp |= TRANS_DP_PORT_SEL_C;
2646                         break;
2647                 case PCH_DP_D:
2648                         temp |= TRANS_DP_PORT_SEL_D;
2649                         break;
2650                 default:
2651                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2652                         temp |= TRANS_DP_PORT_SEL_B;
2653                         break;
2654                 }
2655
2656                 I915_WRITE(reg, temp);
2657         }
2658
2659         intel_enable_transcoder(dev_priv, pipe);
2660
2661         intel_crtc_load_lut(crtc);
2662         intel_update_fbc(dev);
2663         intel_crtc_update_cursor(crtc, true);
2664 }
2665
2666 static void ironlake_crtc_disable(struct drm_crtc *crtc)
2667 {
2668         struct drm_device *dev = crtc->dev;
2669         struct drm_i915_private *dev_priv = dev->dev_private;
2670         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2671         int pipe = intel_crtc->pipe;
2672         int plane = intel_crtc->plane;
2673         u32 reg, temp;
2674
2675         if (!intel_crtc->active)
2676                 return;
2677
2678         intel_crtc_wait_for_pending_flips(crtc);
2679         drm_vblank_off(dev, pipe);
2680         intel_crtc_update_cursor(crtc, false);
2681
2682         intel_disable_plane(dev_priv, plane, pipe);
2683
2684         if (dev_priv->cfb_plane == plane &&
2685             dev_priv->display.disable_fbc)
2686                 dev_priv->display.disable_fbc(dev);
2687
2688         intel_disable_pipe(dev_priv, pipe);
2689
2690         /* Disable PF */
2691         I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1, 0);
2692         I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ, 0);
2693
2694         /* disable CPU FDI tx and PCH FDI rx */
2695         reg = FDI_TX_CTL(pipe);
2696         temp = I915_READ(reg);
2697         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2698         POSTING_READ(reg);
2699
2700         reg = FDI_RX_CTL(pipe);
2701         temp = I915_READ(reg);
2702         temp &= ~(0x7 << 16);
2703         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2704         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2705
2706         POSTING_READ(reg);
2707         udelay(100);
2708
2709         /* Ironlake workaround, disable clock pointer after downing FDI */
2710         if (HAS_PCH_IBX(dev))
2711                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2712                            I915_READ(FDI_RX_CHICKEN(pipe) &
2713                                      ~FDI_RX_PHASE_SYNC_POINTER_ENABLE));
2714
2715         /* still set train pattern 1 */
2716         reg = FDI_TX_CTL(pipe);
2717         temp = I915_READ(reg);
2718         temp &= ~FDI_LINK_TRAIN_NONE;
2719         temp |= FDI_LINK_TRAIN_PATTERN_1;
2720         I915_WRITE(reg, temp);
2721
2722         reg = FDI_RX_CTL(pipe);
2723         temp = I915_READ(reg);
2724         if (HAS_PCH_CPT(dev)) {
2725                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2726                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2727         } else {
2728                 temp &= ~FDI_LINK_TRAIN_NONE;
2729                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2730         }
2731         /* BPC in FDI rx is consistent with that in PIPECONF */
2732         temp &= ~(0x07 << 16);
2733         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2734         I915_WRITE(reg, temp);
2735
2736         POSTING_READ(reg);
2737         udelay(100);
2738
2739         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2740                 temp = I915_READ(PCH_LVDS);
2741                 if (temp & LVDS_PORT_EN) {
2742                         I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
2743                         POSTING_READ(PCH_LVDS);
2744                         udelay(100);
2745                 }
2746         }
2747
2748         intel_disable_transcoder(dev_priv, pipe);
2749
2750         if (HAS_PCH_CPT(dev)) {
2751                 /* disable TRANS_DP_CTL */
2752                 reg = TRANS_DP_CTL(pipe);
2753                 temp = I915_READ(reg);
2754                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2755                 I915_WRITE(reg, temp);
2756
2757                 /* disable DPLL_SEL */
2758                 temp = I915_READ(PCH_DPLL_SEL);
2759                 if (pipe == 0)
2760                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2761                 else
2762                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2763                 I915_WRITE(PCH_DPLL_SEL, temp);
2764         }
2765
2766         /* disable PCH DPLL */
2767         intel_disable_pch_pll(dev_priv, pipe);
2768
2769         /* Switch from PCDclk to Rawclk */
2770         reg = FDI_RX_CTL(pipe);
2771         temp = I915_READ(reg);
2772         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2773
2774         /* Disable CPU FDI TX PLL */
2775         reg = FDI_TX_CTL(pipe);
2776         temp = I915_READ(reg);
2777         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2778
2779         POSTING_READ(reg);
2780         udelay(100);
2781
2782         reg = FDI_RX_CTL(pipe);
2783         temp = I915_READ(reg);
2784         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2785
2786         /* Wait for the clocks to turn off. */
2787         POSTING_READ(reg);
2788         udelay(100);
2789
2790         intel_crtc->active = false;
2791         intel_update_watermarks(dev);
2792         intel_update_fbc(dev);
2793         intel_clear_scanline_wait(dev);
2794 }
2795
2796 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2797 {
2798         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2799         int pipe = intel_crtc->pipe;
2800         int plane = intel_crtc->plane;
2801
2802         /* XXX: When our outputs are all unaware of DPMS modes other than off
2803          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2804          */
2805         switch (mode) {
2806         case DRM_MODE_DPMS_ON:
2807         case DRM_MODE_DPMS_STANDBY:
2808         case DRM_MODE_DPMS_SUSPEND:
2809                 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
2810                 ironlake_crtc_enable(crtc);
2811                 break;
2812
2813         case DRM_MODE_DPMS_OFF:
2814                 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2815                 ironlake_crtc_disable(crtc);
2816                 break;
2817         }
2818 }
2819
2820 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2821 {
2822         if (!enable && intel_crtc->overlay) {
2823                 struct drm_device *dev = intel_crtc->base.dev;
2824
2825                 mutex_lock(&dev->struct_mutex);
2826                 (void) intel_overlay_switch_off(intel_crtc->overlay, false);
2827                 mutex_unlock(&dev->struct_mutex);
2828         }
2829
2830         /* Let userspace switch the overlay on again. In most cases userspace
2831          * has to recompute where to put it anyway.
2832          */
2833 }
2834
2835 static void i9xx_crtc_enable(struct drm_crtc *crtc)
2836 {
2837         struct drm_device *dev = crtc->dev;
2838         struct drm_i915_private *dev_priv = dev->dev_private;
2839         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2840         int pipe = intel_crtc->pipe;
2841         int plane = intel_crtc->plane;
2842
2843         if (intel_crtc->active)
2844                 return;
2845
2846         intel_crtc->active = true;
2847         intel_update_watermarks(dev);
2848
2849         intel_enable_pll(dev_priv, pipe);
2850         intel_enable_pipe(dev_priv, pipe, false);
2851         intel_enable_plane(dev_priv, plane, pipe);
2852
2853         intel_crtc_load_lut(crtc);
2854         intel_update_fbc(dev);
2855
2856         /* Give the overlay scaler a chance to enable if it's on this pipe */
2857         intel_crtc_dpms_overlay(intel_crtc, true);
2858         intel_crtc_update_cursor(crtc, true);
2859 }
2860
2861 static void i9xx_crtc_disable(struct drm_crtc *crtc)
2862 {
2863         struct drm_device *dev = crtc->dev;
2864         struct drm_i915_private *dev_priv = dev->dev_private;
2865         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2866         int pipe = intel_crtc->pipe;
2867         int plane = intel_crtc->plane;
2868
2869         if (!intel_crtc->active)
2870                 return;
2871
2872         /* Give the overlay scaler a chance to disable if it's on this pipe */
2873         intel_crtc_wait_for_pending_flips(crtc);
2874         drm_vblank_off(dev, pipe);
2875         intel_crtc_dpms_overlay(intel_crtc, false);
2876         intel_crtc_update_cursor(crtc, false);
2877
2878         if (dev_priv->cfb_plane == plane &&
2879             dev_priv->display.disable_fbc)
2880                 dev_priv->display.disable_fbc(dev);
2881
2882         intel_disable_plane(dev_priv, plane, pipe);
2883         intel_disable_pipe(dev_priv, pipe);
2884         intel_disable_pll(dev_priv, pipe);
2885
2886         intel_crtc->active = false;
2887         intel_update_fbc(dev);
2888         intel_update_watermarks(dev);
2889         intel_clear_scanline_wait(dev);
2890 }
2891
2892 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2893 {
2894         /* XXX: When our outputs are all unaware of DPMS modes other than off
2895          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2896          */
2897         switch (mode) {
2898         case DRM_MODE_DPMS_ON:
2899         case DRM_MODE_DPMS_STANDBY:
2900         case DRM_MODE_DPMS_SUSPEND:
2901                 i9xx_crtc_enable(crtc);
2902                 break;
2903         case DRM_MODE_DPMS_OFF:
2904                 i9xx_crtc_disable(crtc);
2905                 break;
2906         }
2907 }
2908
2909 /**
2910  * Sets the power management mode of the pipe and plane.
2911  */
2912 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2913 {
2914         struct drm_device *dev = crtc->dev;
2915         struct drm_i915_private *dev_priv = dev->dev_private;
2916         struct drm_i915_master_private *master_priv;
2917         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2918         int pipe = intel_crtc->pipe;
2919         bool enabled;
2920
2921         if (intel_crtc->dpms_mode == mode)
2922                 return;
2923
2924         intel_crtc->dpms_mode = mode;
2925
2926         dev_priv->display.dpms(crtc, mode);
2927
2928         if (!dev->primary->master)
2929                 return;
2930
2931         master_priv = dev->primary->master->driver_priv;
2932         if (!master_priv->sarea_priv)
2933                 return;
2934
2935         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2936
2937         switch (pipe) {
2938         case 0:
2939                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2940                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2941                 break;
2942         case 1:
2943                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2944                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2945                 break;
2946         default:
2947                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2948                 break;
2949         }
2950 }
2951
2952 static void intel_crtc_disable(struct drm_crtc *crtc)
2953 {
2954         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2955         struct drm_device *dev = crtc->dev;
2956
2957         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2958
2959         if (crtc->fb) {
2960                 mutex_lock(&dev->struct_mutex);
2961                 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
2962                 mutex_unlock(&dev->struct_mutex);
2963         }
2964 }
2965
2966 /* Prepare for a mode set.
2967  *
2968  * Note we could be a lot smarter here.  We need to figure out which outputs
2969  * will be enabled, which disabled (in short, how the config will changes)
2970  * and perform the minimum necessary steps to accomplish that, e.g. updating
2971  * watermarks, FBC configuration, making sure PLLs are programmed correctly,
2972  * panel fitting is in the proper state, etc.
2973  */
2974 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
2975 {
2976         i9xx_crtc_disable(crtc);
2977 }
2978
2979 static void i9xx_crtc_commit(struct drm_crtc *crtc)
2980 {
2981         i9xx_crtc_enable(crtc);
2982 }
2983
2984 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
2985 {
2986         ironlake_crtc_disable(crtc);
2987 }
2988
2989 static void ironlake_crtc_commit(struct drm_crtc *crtc)
2990 {
2991         ironlake_crtc_enable(crtc);
2992 }
2993
2994 void intel_encoder_prepare (struct drm_encoder *encoder)
2995 {
2996         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2997         /* lvds has its own version of prepare see intel_lvds_prepare */
2998         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2999 }
3000
3001 void intel_encoder_commit (struct drm_encoder *encoder)
3002 {
3003         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3004         /* lvds has its own version of commit see intel_lvds_commit */
3005         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3006 }
3007
3008 void intel_encoder_destroy(struct drm_encoder *encoder)
3009 {
3010         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3011
3012         drm_encoder_cleanup(encoder);
3013         kfree(intel_encoder);
3014 }
3015
3016 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3017                                   struct drm_display_mode *mode,
3018                                   struct drm_display_mode *adjusted_mode)
3019 {
3020         struct drm_device *dev = crtc->dev;
3021
3022         if (HAS_PCH_SPLIT(dev)) {
3023                 /* FDI link clock is fixed at 2.7G */
3024                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3025                         return false;
3026         }
3027
3028         /* XXX some encoders set the crtcinfo, others don't.
3029          * Obviously we need some form of conflict resolution here...
3030          */
3031         if (adjusted_mode->crtc_htotal == 0)
3032                 drm_mode_set_crtcinfo(adjusted_mode, 0);
3033
3034         return true;
3035 }
3036
3037 static int i945_get_display_clock_speed(struct drm_device *dev)
3038 {
3039         return 400000;
3040 }
3041
3042 static int i915_get_display_clock_speed(struct drm_device *dev)
3043 {
3044         return 333000;
3045 }
3046
3047 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3048 {
3049         return 200000;
3050 }
3051
3052 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3053 {
3054         u16 gcfgc = 0;
3055
3056         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3057
3058         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3059                 return 133000;
3060         else {
3061                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3062                 case GC_DISPLAY_CLOCK_333_MHZ:
3063                         return 333000;
3064                 default:
3065                 case GC_DISPLAY_CLOCK_190_200_MHZ:
3066                         return 190000;
3067                 }
3068         }
3069 }
3070
3071 static int i865_get_display_clock_speed(struct drm_device *dev)
3072 {
3073         return 266000;
3074 }
3075
3076 static int i855_get_display_clock_speed(struct drm_device *dev)
3077 {
3078         u16 hpllcc = 0;
3079         /* Assume that the hardware is in the high speed state.  This
3080          * should be the default.
3081          */
3082         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3083         case GC_CLOCK_133_200:
3084         case GC_CLOCK_100_200:
3085                 return 200000;
3086         case GC_CLOCK_166_250:
3087                 return 250000;
3088         case GC_CLOCK_100_133:
3089                 return 133000;
3090         }
3091
3092         /* Shouldn't happen */
3093         return 0;
3094 }
3095
3096 static int i830_get_display_clock_speed(struct drm_device *dev)
3097 {
3098         return 133000;
3099 }
3100
3101 struct fdi_m_n {
3102         u32        tu;
3103         u32        gmch_m;
3104         u32        gmch_n;
3105         u32        link_m;
3106         u32        link_n;
3107 };
3108
3109 static void
3110 fdi_reduce_ratio(u32 *num, u32 *den)
3111 {
3112         while (*num > 0xffffff || *den > 0xffffff) {
3113                 *num >>= 1;
3114                 *den >>= 1;
3115         }
3116 }
3117
3118 static void
3119 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3120                      int link_clock, struct fdi_m_n *m_n)
3121 {
3122         m_n->tu = 64; /* default size */
3123
3124         /* BUG_ON(pixel_clock > INT_MAX / 36); */
3125         m_n->gmch_m = bits_per_pixel * pixel_clock;
3126         m_n->gmch_n = link_clock * nlanes * 8;
3127         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3128
3129         m_n->link_m = pixel_clock;
3130         m_n->link_n = link_clock;
3131         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3132 }
3133
3134
3135 struct intel_watermark_params {
3136         unsigned long fifo_size;
3137         unsigned long max_wm;
3138         unsigned long default_wm;
3139         unsigned long guard_size;
3140         unsigned long cacheline_size;
3141 };
3142
3143 /* Pineview has different values for various configs */
3144 static struct intel_watermark_params pineview_display_wm = {
3145         PINEVIEW_DISPLAY_FIFO,
3146         PINEVIEW_MAX_WM,
3147         PINEVIEW_DFT_WM,
3148         PINEVIEW_GUARD_WM,
3149         PINEVIEW_FIFO_LINE_SIZE
3150 };
3151 static struct intel_watermark_params pineview_display_hplloff_wm = {
3152         PINEVIEW_DISPLAY_FIFO,
3153         PINEVIEW_MAX_WM,
3154         PINEVIEW_DFT_HPLLOFF_WM,
3155         PINEVIEW_GUARD_WM,
3156         PINEVIEW_FIFO_LINE_SIZE
3157 };
3158 static struct intel_watermark_params pineview_cursor_wm = {
3159         PINEVIEW_CURSOR_FIFO,
3160         PINEVIEW_CURSOR_MAX_WM,
3161         PINEVIEW_CURSOR_DFT_WM,
3162         PINEVIEW_CURSOR_GUARD_WM,
3163         PINEVIEW_FIFO_LINE_SIZE,
3164 };
3165 static struct intel_watermark_params pineview_cursor_hplloff_wm = {
3166         PINEVIEW_CURSOR_FIFO,
3167         PINEVIEW_CURSOR_MAX_WM,
3168         PINEVIEW_CURSOR_DFT_WM,
3169         PINEVIEW_CURSOR_GUARD_WM,
3170         PINEVIEW_FIFO_LINE_SIZE
3171 };
3172 static struct intel_watermark_params g4x_wm_info = {
3173         G4X_FIFO_SIZE,
3174         G4X_MAX_WM,
3175         G4X_MAX_WM,
3176         2,
3177         G4X_FIFO_LINE_SIZE,
3178 };
3179 static struct intel_watermark_params g4x_cursor_wm_info = {
3180         I965_CURSOR_FIFO,
3181         I965_CURSOR_MAX_WM,
3182         I965_CURSOR_DFT_WM,
3183         2,
3184         G4X_FIFO_LINE_SIZE,
3185 };
3186 static struct intel_watermark_params i965_cursor_wm_info = {
3187         I965_CURSOR_FIFO,
3188         I965_CURSOR_MAX_WM,
3189         I965_CURSOR_DFT_WM,
3190         2,
3191         I915_FIFO_LINE_SIZE,
3192 };
3193 static struct intel_watermark_params i945_wm_info = {
3194         I945_FIFO_SIZE,
3195         I915_MAX_WM,
3196         1,
3197         2,
3198         I915_FIFO_LINE_SIZE
3199 };
3200 static struct intel_watermark_params i915_wm_info = {
3201         I915_FIFO_SIZE,
3202         I915_MAX_WM,
3203         1,
3204         2,
3205         I915_FIFO_LINE_SIZE
3206 };
3207 static struct intel_watermark_params i855_wm_info = {
3208         I855GM_FIFO_SIZE,
3209         I915_MAX_WM,
3210         1,
3211         2,
3212         I830_FIFO_LINE_SIZE
3213 };
3214 static struct intel_watermark_params i830_wm_info = {
3215         I830_FIFO_SIZE,
3216         I915_MAX_WM,
3217         1,
3218         2,
3219         I830_FIFO_LINE_SIZE
3220 };
3221
3222 static struct intel_watermark_params ironlake_display_wm_info = {
3223         ILK_DISPLAY_FIFO,
3224         ILK_DISPLAY_MAXWM,
3225         ILK_DISPLAY_DFTWM,
3226         2,
3227         ILK_FIFO_LINE_SIZE
3228 };
3229
3230 static struct intel_watermark_params ironlake_cursor_wm_info = {
3231         ILK_CURSOR_FIFO,
3232         ILK_CURSOR_MAXWM,
3233         ILK_CURSOR_DFTWM,
3234         2,
3235         ILK_FIFO_LINE_SIZE
3236 };
3237
3238 static struct intel_watermark_params ironlake_display_srwm_info = {
3239         ILK_DISPLAY_SR_FIFO,
3240         ILK_DISPLAY_MAX_SRWM,
3241         ILK_DISPLAY_DFT_SRWM,
3242         2,
3243         ILK_FIFO_LINE_SIZE
3244 };
3245
3246 static struct intel_watermark_params ironlake_cursor_srwm_info = {
3247         ILK_CURSOR_SR_FIFO,
3248         ILK_CURSOR_MAX_SRWM,
3249         ILK_CURSOR_DFT_SRWM,
3250         2,
3251         ILK_FIFO_LINE_SIZE
3252 };
3253
3254 static struct intel_watermark_params sandybridge_display_wm_info = {
3255         SNB_DISPLAY_FIFO,
3256         SNB_DISPLAY_MAXWM,
3257         SNB_DISPLAY_DFTWM,
3258         2,
3259         SNB_FIFO_LINE_SIZE
3260 };
3261
3262 static struct intel_watermark_params sandybridge_cursor_wm_info = {
3263         SNB_CURSOR_FIFO,
3264         SNB_CURSOR_MAXWM,
3265         SNB_CURSOR_DFTWM,
3266         2,
3267         SNB_FIFO_LINE_SIZE
3268 };
3269
3270 static struct intel_watermark_params sandybridge_display_srwm_info = {
3271         SNB_DISPLAY_SR_FIFO,
3272         SNB_DISPLAY_MAX_SRWM,
3273         SNB_DISPLAY_DFT_SRWM,
3274         2,
3275         SNB_FIFO_LINE_SIZE
3276 };
3277
3278 static struct intel_watermark_params sandybridge_cursor_srwm_info = {
3279         SNB_CURSOR_SR_FIFO,
3280         SNB_CURSOR_MAX_SRWM,
3281         SNB_CURSOR_DFT_SRWM,
3282         2,
3283         SNB_FIFO_LINE_SIZE
3284 };
3285
3286
3287 /**
3288  * intel_calculate_wm - calculate watermark level
3289  * @clock_in_khz: pixel clock
3290  * @wm: chip FIFO params
3291  * @pixel_size: display pixel size
3292  * @latency_ns: memory latency for the platform
3293  *
3294  * Calculate the watermark level (the level at which the display plane will
3295  * start fetching from memory again).  Each chip has a different display
3296  * FIFO size and allocation, so the caller needs to figure that out and pass
3297  * in the correct intel_watermark_params structure.
3298  *
3299  * As the pixel clock runs, the FIFO will be drained at a rate that depends
3300  * on the pixel size.  When it reaches the watermark level, it'll start
3301  * fetching FIFO line sized based chunks from memory until the FIFO fills
3302  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
3303  * will occur, and a display engine hang could result.
3304  */
3305 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
3306                                         struct intel_watermark_params *wm,
3307                                         int pixel_size,
3308                                         unsigned long latency_ns)
3309 {
3310         long entries_required, wm_size;
3311
3312         /*
3313          * Note: we need to make sure we don't overflow for various clock &
3314          * latency values.
3315          * clocks go from a few thousand to several hundred thousand.
3316          * latency is usually a few thousand
3317          */
3318         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3319                 1000;
3320         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
3321
3322         DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
3323
3324         wm_size = wm->fifo_size - (entries_required + wm->guard_size);
3325
3326         DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
3327
3328         /* Don't promote wm_size to unsigned... */
3329         if (wm_size > (long)wm->max_wm)
3330                 wm_size = wm->max_wm;
3331         if (wm_size <= 0)
3332                 wm_size = wm->default_wm;
3333         return wm_size;
3334 }
3335
3336 struct cxsr_latency {
3337         int is_desktop;
3338         int is_ddr3;
3339         unsigned long fsb_freq;
3340         unsigned long mem_freq;
3341         unsigned long display_sr;
3342         unsigned long display_hpll_disable;
3343         unsigned long cursor_sr;
3344         unsigned long cursor_hpll_disable;
3345 };
3346
3347 static const struct cxsr_latency cxsr_latency_table[] = {
3348         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
3349         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
3350         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
3351         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
3352         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
3353
3354         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
3355         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
3356         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
3357         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
3358         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
3359
3360         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
3361         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
3362         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
3363         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
3364         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
3365
3366         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
3367         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
3368         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
3369         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
3370         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
3371
3372         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
3373         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
3374         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
3375         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
3376         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
3377
3378         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
3379         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
3380         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
3381         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
3382         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
3383 };
3384
3385 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3386                                                          int is_ddr3,
3387                                                          int fsb,
3388                                                          int mem)
3389 {
3390         const struct cxsr_latency *latency;
3391         int i;
3392
3393         if (fsb == 0 || mem == 0)
3394                 return NULL;
3395
3396         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3397                 latency = &cxsr_latency_table[i];
3398                 if (is_desktop == latency->is_desktop &&
3399                     is_ddr3 == latency->is_ddr3 &&
3400                     fsb == latency->fsb_freq && mem == latency->mem_freq)
3401                         return latency;
3402         }
3403
3404         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3405
3406         return NULL;
3407 }
3408
3409 static void pineview_disable_cxsr(struct drm_device *dev)
3410 {
3411         struct drm_i915_private *dev_priv = dev->dev_private;
3412
3413         /* deactivate cxsr */
3414         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
3415 }
3416
3417 /*
3418  * Latency for FIFO fetches is dependent on several factors:
3419  *   - memory configuration (speed, channels)
3420  *   - chipset
3421  *   - current MCH state
3422  * It can be fairly high in some situations, so here we assume a fairly
3423  * pessimal value.  It's a tradeoff between extra memory fetches (if we
3424  * set this value too high, the FIFO will fetch frequently to stay full)
3425  * and power consumption (set it too low to save power and we might see
3426  * FIFO underruns and display "flicker").
3427  *
3428  * A value of 5us seems to be a good balance; safe for very low end
3429  * platforms but not overly aggressive on lower latency configs.
3430  */
3431 static const int latency_ns = 5000;
3432
3433 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
3434 {
3435         struct drm_i915_private *dev_priv = dev->dev_private;
3436         uint32_t dsparb = I915_READ(DSPARB);
3437         int size;
3438
3439         size = dsparb & 0x7f;
3440         if (plane)
3441                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
3442
3443         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3444                       plane ? "B" : "A", size);
3445
3446         return size;
3447 }
3448
3449 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3450 {
3451         struct drm_i915_private *dev_priv = dev->dev_private;
3452         uint32_t dsparb = I915_READ(DSPARB);
3453         int size;
3454
3455         size = dsparb & 0x1ff;
3456         if (plane)
3457                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
3458         size >>= 1; /* Convert to cachelines */
3459
3460         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3461                       plane ? "B" : "A", size);
3462
3463         return size;
3464 }
3465
3466 static int i845_get_fifo_size(struct drm_device *dev, int plane)
3467 {
3468         struct drm_i915_private *dev_priv = dev->dev_private;
3469         uint32_t dsparb = I915_READ(DSPARB);
3470         int size;
3471
3472         size = dsparb & 0x7f;
3473         size >>= 2; /* Convert to cachelines */
3474
3475         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3476                       plane ? "B" : "A",
3477                       size);
3478
3479         return size;
3480 }
3481
3482 static int i830_get_fifo_size(struct drm_device *dev, int plane)
3483 {
3484         struct drm_i915_private *dev_priv = dev->dev_private;
3485         uint32_t dsparb = I915_READ(DSPARB);
3486         int size;
3487
3488         size = dsparb & 0x7f;
3489         size >>= 1; /* Convert to cachelines */
3490
3491         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3492                       plane ? "B" : "A", size);
3493
3494         return size;
3495 }
3496
3497 static void pineview_update_wm(struct drm_device *dev,  int planea_clock,
3498                                int planeb_clock, int sr_hdisplay, int unused,
3499                                int pixel_size)
3500 {
3501         struct drm_i915_private *dev_priv = dev->dev_private;
3502         const struct cxsr_latency *latency;
3503         u32 reg;
3504         unsigned long wm;
3505         int sr_clock;
3506
3507         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3508                                          dev_priv->fsb_freq, dev_priv->mem_freq);
3509         if (!latency) {
3510                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3511                 pineview_disable_cxsr(dev);
3512                 return;
3513         }
3514
3515         if (!planea_clock || !planeb_clock) {
3516                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3517
3518                 /* Display SR */
3519                 wm = intel_calculate_wm(sr_clock, &pineview_display_wm,
3520                                         pixel_size, latency->display_sr);
3521                 reg = I915_READ(DSPFW1);
3522                 reg &= ~DSPFW_SR_MASK;
3523                 reg |= wm << DSPFW_SR_SHIFT;
3524                 I915_WRITE(DSPFW1, reg);
3525                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3526
3527                 /* cursor SR */
3528                 wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm,
3529                                         pixel_size, latency->cursor_sr);
3530                 reg = I915_READ(DSPFW3);
3531                 reg &= ~DSPFW_CURSOR_SR_MASK;
3532                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3533                 I915_WRITE(DSPFW3, reg);
3534
3535                 /* Display HPLL off SR */
3536                 wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm,
3537                                         pixel_size, latency->display_hpll_disable);
3538                 reg = I915_READ(DSPFW3);
3539                 reg &= ~DSPFW_HPLL_SR_MASK;
3540                 reg |= wm & DSPFW_HPLL_SR_MASK;
3541                 I915_WRITE(DSPFW3, reg);
3542
3543                 /* cursor HPLL off SR */
3544                 wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm,
3545                                         pixel_size, latency->cursor_hpll_disable);
3546                 reg = I915_READ(DSPFW3);
3547                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3548                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3549                 I915_WRITE(DSPFW3, reg);
3550                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3551
3552                 /* activate cxsr */
3553                 I915_WRITE(DSPFW3,
3554                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3555                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3556         } else {
3557                 pineview_disable_cxsr(dev);
3558                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3559         }
3560 }
3561
3562 static void g4x_update_wm(struct drm_device *dev,  int planea_clock,
3563                           int planeb_clock, int sr_hdisplay, int sr_htotal,
3564                           int pixel_size)
3565 {
3566         struct drm_i915_private *dev_priv = dev->dev_private;
3567         int total_size, cacheline_size;
3568         int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
3569         struct intel_watermark_params planea_params, planeb_params;
3570         unsigned long line_time_us;
3571         int sr_clock, sr_entries = 0, entries_required;
3572
3573         /* Create copies of the base settings for each pipe */
3574         planea_params = planeb_params = g4x_wm_info;
3575
3576         /* Grab a couple of global values before we overwrite them */
3577         total_size = planea_params.fifo_size;
3578         cacheline_size = planea_params.cacheline_size;
3579
3580         /*
3581          * Note: we need to make sure we don't overflow for various clock &
3582          * latency values.
3583          * clocks go from a few thousand to several hundred thousand.
3584          * latency is usually a few thousand
3585          */
3586         entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
3587                 1000;
3588         entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3589         planea_wm = entries_required + planea_params.guard_size;
3590
3591         entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
3592                 1000;
3593         entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3594         planeb_wm = entries_required + planeb_params.guard_size;
3595
3596         cursora_wm = cursorb_wm = 16;
3597         cursor_sr = 32;
3598
3599         DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3600
3601         /* Calc sr entries for one plane configs */
3602         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3603                 /* self-refresh has much higher latency */
3604                 static const int sr_latency_ns = 12000;
3605
3606                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3607                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3608
3609                 /* Use ns/us then divide to preserve precision */
3610                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3611                         pixel_size * sr_hdisplay;
3612                 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3613
3614                 entries_required = (((sr_latency_ns / line_time_us) +
3615                                      1000) / 1000) * pixel_size * 64;
3616                 entries_required = DIV_ROUND_UP(entries_required,
3617                                                 g4x_cursor_wm_info.cacheline_size);
3618                 cursor_sr = entries_required + g4x_cursor_wm_info.guard_size;
3619
3620                 if (cursor_sr > g4x_cursor_wm_info.max_wm)
3621                         cursor_sr = g4x_cursor_wm_info.max_wm;
3622                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3623                               "cursor %d\n", sr_entries, cursor_sr);
3624
3625                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3626         } else {
3627                 /* Turn off self refresh if both pipes are enabled */
3628                 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3629                            & ~FW_BLC_SELF_EN);
3630         }
3631
3632         DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
3633                   planea_wm, planeb_wm, sr_entries);
3634
3635         planea_wm &= 0x3f;
3636         planeb_wm &= 0x3f;
3637
3638         I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
3639                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
3640                    (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
3641         I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
3642                    (cursora_wm << DSPFW_CURSORA_SHIFT));
3643         /* HPLL off in SR has some issues on G4x... disable it */
3644         I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
3645                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3646 }
3647
3648 static void i965_update_wm(struct drm_device *dev, int planea_clock,
3649                            int planeb_clock, int sr_hdisplay, int sr_htotal,
3650                            int pixel_size)
3651 {
3652         struct drm_i915_private *dev_priv = dev->dev_private;
3653         unsigned long line_time_us;
3654         int sr_clock, sr_entries, srwm = 1;
3655         int cursor_sr = 16;
3656
3657         /* Calc sr entries for one plane configs */
3658         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3659                 /* self-refresh has much higher latency */
3660                 static const int sr_latency_ns = 12000;
3661
3662                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3663                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3664
3665                 /* Use ns/us then divide to preserve precision */
3666                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3667                         pixel_size * sr_hdisplay;
3668                 sr_entries = DIV_ROUND_UP(sr_entries, I915_FIFO_LINE_SIZE);
3669                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
3670                 srwm = I965_FIFO_SIZE - sr_entries;
3671                 if (srwm < 0)
3672                         srwm = 1;
3673                 srwm &= 0x1ff;
3674
3675                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3676                         pixel_size * 64;
3677                 sr_entries = DIV_ROUND_UP(sr_entries,
3678                                           i965_cursor_wm_info.cacheline_size);
3679                 cursor_sr = i965_cursor_wm_info.fifo_size -
3680                         (sr_entries + i965_cursor_wm_info.guard_size);
3681
3682                 if (cursor_sr > i965_cursor_wm_info.max_wm)
3683                         cursor_sr = i965_cursor_wm_info.max_wm;
3684
3685                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3686                               "cursor %d\n", srwm, cursor_sr);
3687
3688                 if (IS_CRESTLINE(dev))
3689                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3690         } else {
3691                 /* Turn off self refresh if both pipes are enabled */
3692                 if (IS_CRESTLINE(dev))
3693                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3694                                    & ~FW_BLC_SELF_EN);
3695         }
3696
3697         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3698                       srwm);
3699
3700         /* 965 has limitations... */
3701         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
3702                    (8 << 0));
3703         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
3704         /* update cursor SR watermark */
3705         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3706 }
3707
3708 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
3709                            int planeb_clock, int sr_hdisplay, int sr_htotal,
3710                            int pixel_size)
3711 {
3712         struct drm_i915_private *dev_priv = dev->dev_private;
3713         uint32_t fwater_lo;
3714         uint32_t fwater_hi;
3715         int total_size, cacheline_size, cwm, srwm = 1;
3716         int planea_wm, planeb_wm;
3717         struct intel_watermark_params planea_params, planeb_params;
3718         unsigned long line_time_us;
3719         int sr_clock, sr_entries = 0;
3720
3721         /* Create copies of the base settings for each pipe */
3722         if (IS_CRESTLINE(dev) || IS_I945GM(dev))
3723                 planea_params = planeb_params = i945_wm_info;
3724         else if (!IS_GEN2(dev))
3725                 planea_params = planeb_params = i915_wm_info;
3726         else
3727                 planea_params = planeb_params = i855_wm_info;
3728
3729         /* Grab a couple of global values before we overwrite them */
3730         total_size = planea_params.fifo_size;
3731         cacheline_size = planea_params.cacheline_size;
3732
3733         /* Update per-plane FIFO sizes */
3734         planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3735         planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
3736
3737         planea_wm = intel_calculate_wm(planea_clock, &planea_params,
3738                                        pixel_size, latency_ns);
3739         planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
3740                                        pixel_size, latency_ns);
3741         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3742
3743         /*
3744          * Overlay gets an aggressive default since video jitter is bad.
3745          */
3746         cwm = 2;
3747
3748         /* Calc sr entries for one plane configs */
3749         if (HAS_FW_BLC(dev) && sr_hdisplay &&
3750             (!planea_clock || !planeb_clock)) {
3751                 /* self-refresh has much higher latency */
3752                 static const int sr_latency_ns = 6000;
3753
3754                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3755                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3756
3757                 /* Use ns/us then divide to preserve precision */
3758                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3759                         pixel_size * sr_hdisplay;
3760                 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3761                 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
3762                 srwm = total_size - sr_entries;
3763                 if (srwm < 0)
3764                         srwm = 1;
3765
3766                 if (IS_I945G(dev) || IS_I945GM(dev))
3767                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3768                 else if (IS_I915GM(dev)) {
3769                         /* 915M has a smaller SRWM field */
3770                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
3771                         I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3772                 }
3773         } else {
3774                 /* Turn off self refresh if both pipes are enabled */
3775                 if (IS_I945G(dev) || IS_I945GM(dev)) {
3776                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3777                                    & ~FW_BLC_SELF_EN);
3778                 } else if (IS_I915GM(dev)) {
3779                         I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3780                 }
3781         }
3782
3783         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
3784                       planea_wm, planeb_wm, cwm, srwm);
3785
3786         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3787         fwater_hi = (cwm & 0x1f);
3788
3789         /* Set request length to 8 cachelines per fetch */
3790         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3791         fwater_hi = fwater_hi | (1 << 8);
3792
3793         I915_WRITE(FW_BLC, fwater_lo);
3794         I915_WRITE(FW_BLC2, fwater_hi);
3795 }
3796
3797 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
3798                            int unused2, int unused3, int pixel_size)
3799 {
3800         struct drm_i915_private *dev_priv = dev->dev_private;
3801         uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
3802         int planea_wm;
3803
3804         i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3805
3806         planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
3807                                        pixel_size, latency_ns);
3808         fwater_lo |= (3<<8) | planea_wm;
3809
3810         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
3811
3812         I915_WRITE(FW_BLC, fwater_lo);
3813 }
3814
3815 #define ILK_LP0_PLANE_LATENCY           700
3816 #define ILK_LP0_CURSOR_LATENCY          1300
3817
3818 static bool ironlake_compute_wm0(struct drm_device *dev,
3819                                  int pipe,
3820                                  const struct intel_watermark_params *display,
3821                                  int display_latency_ns,
3822                                  const struct intel_watermark_params *cursor,
3823                                  int cursor_latency_ns,
3824                                  int *plane_wm,
3825                                  int *cursor_wm)
3826 {
3827         struct drm_crtc *crtc;
3828         int htotal, hdisplay, clock, pixel_size;
3829         int line_time_us, line_count;
3830         int entries, tlb_miss;
3831
3832         crtc = intel_get_crtc_for_pipe(dev, pipe);
3833         if (crtc->fb == NULL || !crtc->enabled)
3834                 return false;
3835
3836         htotal = crtc->mode.htotal;
3837         hdisplay = crtc->mode.hdisplay;
3838         clock = crtc->mode.clock;
3839         pixel_size = crtc->fb->bits_per_pixel / 8;
3840
3841         /* Use the small buffer method to calculate plane watermark */
3842         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
3843         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
3844         if (tlb_miss > 0)
3845                 entries += tlb_miss;
3846         entries = DIV_ROUND_UP(entries, display->cacheline_size);
3847         *plane_wm = entries + display->guard_size;
3848         if (*plane_wm > (int)display->max_wm)
3849                 *plane_wm = display->max_wm;
3850
3851         /* Use the large buffer method to calculate cursor watermark */
3852         line_time_us = ((htotal * 1000) / clock);
3853         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3854         entries = line_count * 64 * pixel_size;
3855         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
3856         if (tlb_miss > 0)
3857                 entries += tlb_miss;
3858         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3859         *cursor_wm = entries + cursor->guard_size;
3860         if (*cursor_wm > (int)cursor->max_wm)
3861                 *cursor_wm = (int)cursor->max_wm;
3862
3863         return true;
3864 }
3865
3866 /*
3867  * Check the wm result.
3868  *
3869  * If any calculated watermark values is larger than the maximum value that
3870  * can be programmed into the associated watermark register, that watermark
3871  * must be disabled.
3872  */
3873 static bool ironlake_check_srwm(struct drm_device *dev, int level,
3874                                 int fbc_wm, int display_wm, int cursor_wm,
3875                                 const struct intel_watermark_params *display,
3876                                 const struct intel_watermark_params *cursor)
3877 {
3878         struct drm_i915_private *dev_priv = dev->dev_private;
3879
3880         DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
3881                       " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
3882
3883         if (fbc_wm > SNB_FBC_MAX_SRWM) {
3884                 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
3885                               fbc_wm, SNB_FBC_MAX_SRWM, level);
3886
3887                 /* fbc has it's own way to disable FBC WM */
3888                 I915_WRITE(DISP_ARB_CTL,
3889                            I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
3890                 return false;
3891         }
3892
3893         if (display_wm > display->max_wm) {
3894                 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
3895                               display_wm, SNB_DISPLAY_MAX_SRWM, level);
3896                 return false;
3897         }
3898
3899         if (cursor_wm > cursor->max_wm) {
3900                 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
3901                               cursor_wm, SNB_CURSOR_MAX_SRWM, level);
3902                 return false;
3903         }
3904
3905         if (!(fbc_wm || display_wm || cursor_wm)) {
3906                 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
3907                 return false;
3908         }
3909
3910         return true;
3911 }
3912
3913 /*
3914  * Compute watermark values of WM[1-3],
3915  */
3916 static bool ironlake_compute_srwm(struct drm_device *dev, int level,
3917                                   int hdisplay, int htotal,
3918                                   int pixel_size, int clock, int latency_ns,
3919                                   const struct intel_watermark_params *display,
3920                                   const struct intel_watermark_params *cursor,
3921                                   int *fbc_wm, int *display_wm, int *cursor_wm)
3922 {
3923
3924         unsigned long line_time_us;
3925         int line_count, line_size;
3926         int small, large;
3927         int entries;
3928
3929         if (!latency_ns) {
3930                 *fbc_wm = *display_wm = *cursor_wm = 0;
3931                 return false;
3932         }
3933
3934         line_time_us = (htotal * 1000) / clock;
3935         line_count = (latency_ns / line_time_us + 1000) / 1000;
3936         line_size = hdisplay * pixel_size;
3937
3938         /* Use the minimum of the small and large buffer method for primary */
3939         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
3940         large = line_count * line_size;
3941
3942         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
3943         *display_wm = entries + display->guard_size;
3944
3945         /*
3946          * Spec says:
3947          * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
3948          */
3949         *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
3950
3951         /* calculate the self-refresh watermark for display cursor */
3952         entries = line_count * pixel_size * 64;
3953         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3954         *cursor_wm = entries + cursor->guard_size;
3955
3956         return ironlake_check_srwm(dev, level,
3957                                    *fbc_wm, *display_wm, *cursor_wm,
3958                                    display, cursor);
3959 }
3960
3961 static void ironlake_update_wm(struct drm_device *dev,
3962                                int planea_clock, int planeb_clock,
3963                                int hdisplay, int htotal,
3964                                int pixel_size)
3965 {
3966         struct drm_i915_private *dev_priv = dev->dev_private;
3967         int fbc_wm, plane_wm, cursor_wm, enabled;
3968         int clock;
3969
3970         enabled = 0;
3971         if (ironlake_compute_wm0(dev, 0,
3972                                  &ironlake_display_wm_info,
3973                                  ILK_LP0_PLANE_LATENCY,
3974                                  &ironlake_cursor_wm_info,
3975                                  ILK_LP0_CURSOR_LATENCY,
3976                                  &plane_wm, &cursor_wm)) {
3977                 I915_WRITE(WM0_PIPEA_ILK,
3978                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
3979                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
3980                               " plane %d, " "cursor: %d\n",
3981                               plane_wm, cursor_wm);
3982                 enabled++;
3983         }
3984
3985         if (ironlake_compute_wm0(dev, 1,
3986                                  &ironlake_display_wm_info,
3987                                  ILK_LP0_PLANE_LATENCY,
3988                                  &ironlake_cursor_wm_info,
3989                                  ILK_LP0_CURSOR_LATENCY,
3990                                  &plane_wm, &cursor_wm)) {
3991                 I915_WRITE(WM0_PIPEB_ILK,
3992                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
3993                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
3994                               " plane %d, cursor: %d\n",
3995                               plane_wm, cursor_wm);
3996                 enabled++;
3997         }
3998
3999         /*
4000          * Calculate and update the self-refresh watermark only when one
4001          * display plane is used.
4002          */
4003         I915_WRITE(WM3_LP_ILK, 0);
4004         I915_WRITE(WM2_LP_ILK, 0);
4005         I915_WRITE(WM1_LP_ILK, 0);
4006
4007         if (enabled != 1)
4008                 return;
4009
4010         clock = planea_clock ? planea_clock : planeb_clock;
4011
4012         /* WM1 */
4013         if (!ironlake_compute_srwm(dev, 1, hdisplay, htotal, pixel_size,
4014                                    clock, ILK_READ_WM1_LATENCY() * 500,
4015                                    &ironlake_display_srwm_info,
4016                                    &ironlake_cursor_srwm_info,
4017                                    &fbc_wm, &plane_wm, &cursor_wm))
4018                 return;
4019
4020         I915_WRITE(WM1_LP_ILK,
4021                    WM1_LP_SR_EN |
4022                    (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4023                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4024                    (plane_wm << WM1_LP_SR_SHIFT) |
4025                    cursor_wm);
4026
4027         /* WM2 */
4028         if (!ironlake_compute_srwm(dev, 2, hdisplay, htotal, pixel_size,
4029                                    clock, ILK_READ_WM2_LATENCY() * 500,
4030                                    &ironlake_display_srwm_info,
4031                                    &ironlake_cursor_srwm_info,
4032                                    &fbc_wm, &plane_wm, &cursor_wm))
4033                 return;
4034
4035         I915_WRITE(WM2_LP_ILK,
4036                    WM2_LP_EN |
4037                    (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4038                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4039                    (plane_wm << WM1_LP_SR_SHIFT) |
4040                    cursor_wm);
4041
4042         /*
4043          * WM3 is unsupported on ILK, probably because we don't have latency
4044          * data for that power state
4045          */
4046 }
4047
4048 static void sandybridge_update_wm(struct drm_device *dev,
4049                                int planea_clock, int planeb_clock,
4050                                int hdisplay, int htotal,
4051                                int pixel_size)
4052 {
4053         struct drm_i915_private *dev_priv = dev->dev_private;
4054         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
4055         int fbc_wm, plane_wm, cursor_wm, enabled;
4056         int clock;
4057
4058         enabled = 0;
4059         if (ironlake_compute_wm0(dev, 0,
4060                                  &sandybridge_display_wm_info, latency,
4061                                  &sandybridge_cursor_wm_info, latency,
4062                                  &plane_wm, &cursor_wm)) {
4063                 I915_WRITE(WM0_PIPEA_ILK,
4064                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4065                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4066                               " plane %d, " "cursor: %d\n",
4067                               plane_wm, cursor_wm);
4068                 enabled++;
4069         }
4070
4071         if (ironlake_compute_wm0(dev, 1,
4072                                  &sandybridge_display_wm_info, latency,
4073                                  &sandybridge_cursor_wm_info, latency,
4074                                  &plane_wm, &cursor_wm)) {
4075                 I915_WRITE(WM0_PIPEB_ILK,
4076                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4077                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4078                               " plane %d, cursor: %d\n",
4079                               plane_wm, cursor_wm);
4080                 enabled++;
4081         }
4082
4083         /*
4084          * Calculate and update the self-refresh watermark only when one
4085          * display plane is used.
4086          *
4087          * SNB support 3 levels of watermark.
4088          *
4089          * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4090          * and disabled in the descending order
4091          *
4092          */
4093         I915_WRITE(WM3_LP_ILK, 0);
4094         I915_WRITE(WM2_LP_ILK, 0);
4095         I915_WRITE(WM1_LP_ILK, 0);
4096
4097         if (enabled != 1)
4098                 return;
4099
4100         clock = planea_clock ? planea_clock : planeb_clock;
4101
4102         /* WM1 */
4103         if (!ironlake_compute_srwm(dev, 1, hdisplay, htotal, pixel_size,
4104                                    clock, SNB_READ_WM1_LATENCY() * 500,
4105                                    &sandybridge_display_srwm_info,
4106                                    &sandybridge_cursor_srwm_info,
4107                                    &fbc_wm, &plane_wm, &cursor_wm))
4108                 return;
4109
4110         I915_WRITE(WM1_LP_ILK,
4111                    WM1_LP_SR_EN |
4112                    (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4113                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4114                    (plane_wm << WM1_LP_SR_SHIFT) |
4115                    cursor_wm);
4116
4117         /* WM2 */
4118         if (!ironlake_compute_srwm(dev, 2,
4119                                    hdisplay, htotal, pixel_size,
4120                                    clock, SNB_READ_WM2_LATENCY() * 500,
4121                                    &sandybridge_display_srwm_info,
4122                                    &sandybridge_cursor_srwm_info,
4123                                    &fbc_wm, &plane_wm, &cursor_wm))
4124                 return;
4125
4126         I915_WRITE(WM2_LP_ILK,
4127                    WM2_LP_EN |
4128                    (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4129                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4130                    (plane_wm << WM1_LP_SR_SHIFT) |
4131                    cursor_wm);
4132
4133         /* WM3 */
4134         if (!ironlake_compute_srwm(dev, 3,
4135                                    hdisplay, htotal, pixel_size,
4136                                    clock, SNB_READ_WM3_LATENCY() * 500,
4137                                    &sandybridge_display_srwm_info,
4138                                    &sandybridge_cursor_srwm_info,
4139                                    &fbc_wm, &plane_wm, &cursor_wm))
4140                 return;
4141
4142         I915_WRITE(WM3_LP_ILK,
4143                    WM3_LP_EN |
4144                    (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4145                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4146                    (plane_wm << WM1_LP_SR_SHIFT) |
4147                    cursor_wm);
4148 }
4149
4150 /**
4151  * intel_update_watermarks - update FIFO watermark values based on current modes
4152  *
4153  * Calculate watermark values for the various WM regs based on current mode
4154  * and plane configuration.
4155  *
4156  * There are several cases to deal with here:
4157  *   - normal (i.e. non-self-refresh)
4158  *   - self-refresh (SR) mode
4159  *   - lines are large relative to FIFO size (buffer can hold up to 2)
4160  *   - lines are small relative to FIFO size (buffer can hold more than 2
4161  *     lines), so need to account for TLB latency
4162  *
4163  *   The normal calculation is:
4164  *     watermark = dotclock * bytes per pixel * latency
4165  *   where latency is platform & configuration dependent (we assume pessimal
4166  *   values here).
4167  *
4168  *   The SR calculation is:
4169  *     watermark = (trunc(latency/line time)+1) * surface width *
4170  *       bytes per pixel
4171  *   where
4172  *     line time = htotal / dotclock
4173  *     surface width = hdisplay for normal plane and 64 for cursor
4174  *   and latency is assumed to be high, as above.
4175  *
4176  * The final value programmed to the register should always be rounded up,
4177  * and include an extra 2 entries to account for clock crossings.
4178  *
4179  * We don't use the sprite, so we can ignore that.  And on Crestline we have
4180  * to set the non-SR watermarks to 8.
4181  */
4182 static void intel_update_watermarks(struct drm_device *dev)
4183 {
4184         struct drm_i915_private *dev_priv = dev->dev_private;
4185         struct drm_crtc *crtc;
4186         int sr_hdisplay = 0;
4187         unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
4188         int enabled = 0, pixel_size = 0;
4189         int sr_htotal = 0;
4190
4191         if (!dev_priv->display.update_wm)
4192                 return;
4193
4194         /* Get the clock config from both planes */
4195         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4196                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4197                 if (intel_crtc->active) {
4198                         enabled++;
4199                         if (intel_crtc->plane == 0) {
4200                                 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
4201                                               intel_crtc->pipe, crtc->mode.clock);
4202                                 planea_clock = crtc->mode.clock;
4203                         } else {
4204                                 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
4205                                               intel_crtc->pipe, crtc->mode.clock);
4206                                 planeb_clock = crtc->mode.clock;
4207                         }
4208                         sr_hdisplay = crtc->mode.hdisplay;
4209                         sr_clock = crtc->mode.clock;
4210                         sr_htotal = crtc->mode.htotal;
4211                         if (crtc->fb)
4212                                 pixel_size = crtc->fb->bits_per_pixel / 8;
4213                         else
4214                                 pixel_size = 4; /* by default */
4215                 }
4216         }
4217
4218         if (enabled <= 0)
4219                 return;
4220
4221         dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
4222                                     sr_hdisplay, sr_htotal, pixel_size);
4223 }
4224
4225 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4226 {
4227         return dev_priv->lvds_use_ssc && i915_panel_use_ssc;
4228 }
4229
4230 static int intel_crtc_mode_set(struct drm_crtc *crtc,
4231                                struct drm_display_mode *mode,
4232                                struct drm_display_mode *adjusted_mode,
4233                                int x, int y,
4234                                struct drm_framebuffer *old_fb)
4235 {
4236         struct drm_device *dev = crtc->dev;
4237         struct drm_i915_private *dev_priv = dev->dev_private;
4238         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4239         int pipe = intel_crtc->pipe;
4240         int plane = intel_crtc->plane;
4241         u32 fp_reg, dpll_reg;
4242         int refclk, num_connectors = 0;
4243         intel_clock_t clock, reduced_clock;
4244         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
4245         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
4246         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4247         struct intel_encoder *has_edp_encoder = NULL;
4248         struct drm_mode_config *mode_config = &dev->mode_config;
4249         struct intel_encoder *encoder;
4250         const intel_limit_t *limit;
4251         int ret;
4252         struct fdi_m_n m_n = {0};
4253         u32 reg, temp;
4254         int target_clock;
4255
4256         drm_vblank_pre_modeset(dev, pipe);
4257
4258         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4259                 if (encoder->base.crtc != crtc)
4260                         continue;
4261
4262                 switch (encoder->type) {
4263                 case INTEL_OUTPUT_LVDS:
4264                         is_lvds = true;
4265                         break;
4266                 case INTEL_OUTPUT_SDVO:
4267                 case INTEL_OUTPUT_HDMI:
4268                         is_sdvo = true;
4269                         if (encoder->needs_tv_clock)
4270                                 is_tv = true;
4271                         break;
4272                 case INTEL_OUTPUT_DVO:
4273                         is_dvo = true;
4274                         break;
4275                 case INTEL_OUTPUT_TVOUT:
4276                         is_tv = true;
4277                         break;
4278                 case INTEL_OUTPUT_ANALOG:
4279                         is_crt = true;
4280                         break;
4281                 case INTEL_OUTPUT_DISPLAYPORT:
4282                         is_dp = true;
4283                         break;
4284                 case INTEL_OUTPUT_EDP:
4285                         has_edp_encoder = encoder;
4286                         break;
4287                 }
4288
4289                 num_connectors++;
4290         }
4291
4292         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4293                 refclk = dev_priv->lvds_ssc_freq * 1000;
4294                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4295                               refclk / 1000);
4296         } else if (!IS_GEN2(dev)) {
4297                 refclk = 96000;
4298                 if (HAS_PCH_SPLIT(dev) &&
4299                     (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)))
4300                         refclk = 120000; /* 120Mhz refclk */
4301         } else {
4302                 refclk = 48000;
4303         }
4304
4305         /*
4306          * Returns a set of divisors for the desired target clock with the given
4307          * refclk, or FALSE.  The returned values represent the clock equation:
4308          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4309          */
4310         limit = intel_limit(crtc, refclk);
4311         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
4312         if (!ok) {
4313                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4314                 drm_vblank_post_modeset(dev, pipe);
4315                 return -EINVAL;
4316         }
4317
4318         /* Ensure that the cursor is valid for the new mode before changing... */
4319         intel_crtc_update_cursor(crtc, true);
4320
4321         if (is_lvds && dev_priv->lvds_downclock_avail) {
4322                 has_reduced_clock = limit->find_pll(limit, crtc,
4323                                                     dev_priv->lvds_downclock,
4324                                                     refclk,
4325                                                     &reduced_clock);
4326                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
4327                         /*
4328                          * If the different P is found, it means that we can't
4329                          * switch the display clock by using the FP0/FP1.
4330                          * In such case we will disable the LVDS downclock
4331                          * feature.
4332                          */
4333                         DRM_DEBUG_KMS("Different P is found for "
4334                                       "LVDS clock/downclock\n");
4335                         has_reduced_clock = 0;
4336                 }
4337         }
4338         /* SDVO TV has fixed PLL values depend on its clock range,
4339            this mirrors vbios setting. */
4340         if (is_sdvo && is_tv) {
4341                 if (adjusted_mode->clock >= 100000
4342                     && adjusted_mode->clock < 140500) {
4343                         clock.p1 = 2;
4344                         clock.p2 = 10;
4345                         clock.n = 3;
4346                         clock.m1 = 16;
4347                         clock.m2 = 8;
4348                 } else if (adjusted_mode->clock >= 140500
4349                            && adjusted_mode->clock <= 200000) {
4350                         clock.p1 = 1;
4351                         clock.p2 = 10;
4352                         clock.n = 6;
4353                         clock.m1 = 12;
4354                         clock.m2 = 8;
4355                 }
4356         }
4357
4358         /* FDI link */
4359         if (HAS_PCH_SPLIT(dev)) {
4360                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4361                 int lane = 0, link_bw, bpp;
4362                 /* CPU eDP doesn't require FDI link, so just set DP M/N
4363                    according to current link config */
4364                 if (has_edp_encoder && !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4365                         target_clock = mode->clock;
4366                         intel_edp_link_config(has_edp_encoder,
4367                                               &lane, &link_bw);
4368                 } else {
4369                         /* [e]DP over FDI requires target mode clock
4370                            instead of link clock */
4371                         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
4372                                 target_clock = mode->clock;
4373                         else
4374                                 target_clock = adjusted_mode->clock;
4375
4376                         /* FDI is a binary signal running at ~2.7GHz, encoding
4377                          * each output octet as 10 bits. The actual frequency
4378                          * is stored as a divider into a 100MHz clock, and the
4379                          * mode pixel clock is stored in units of 1KHz.
4380                          * Hence the bw of each lane in terms of the mode signal
4381                          * is:
4382                          */
4383                         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4384                 }
4385
4386                 /* determine panel color depth */
4387                 temp = I915_READ(PIPECONF(pipe));
4388                 temp &= ~PIPE_BPC_MASK;
4389                 if (is_lvds) {
4390                         /* the BPC will be 6 if it is 18-bit LVDS panel */
4391                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
4392                                 temp |= PIPE_8BPC;
4393                         else
4394                                 temp |= PIPE_6BPC;
4395                 } else if (has_edp_encoder) {
4396                         switch (dev_priv->edp.bpp/3) {
4397                         case 8:
4398                                 temp |= PIPE_8BPC;
4399                                 break;
4400                         case 10:
4401                                 temp |= PIPE_10BPC;
4402                                 break;
4403                         case 6:
4404                                 temp |= PIPE_6BPC;
4405                                 break;
4406                         case 12:
4407                                 temp |= PIPE_12BPC;
4408                                 break;
4409                         }
4410                 } else
4411                         temp |= PIPE_8BPC;
4412                 I915_WRITE(PIPECONF(pipe), temp);
4413
4414                 switch (temp & PIPE_BPC_MASK) {
4415                 case PIPE_8BPC:
4416                         bpp = 24;
4417                         break;
4418                 case PIPE_10BPC:
4419                         bpp = 30;
4420                         break;
4421                 case PIPE_6BPC:
4422                         bpp = 18;
4423                         break;
4424                 case PIPE_12BPC:
4425                         bpp = 36;
4426                         break;
4427                 default:
4428                         DRM_ERROR("unknown pipe bpc value\n");
4429                         bpp = 24;
4430                 }
4431
4432                 if (!lane) {
4433                         /*
4434                          * Account for spread spectrum to avoid
4435                          * oversubscribing the link. Max center spread
4436                          * is 2.5%; use 5% for safety's sake.
4437                          */
4438                         u32 bps = target_clock * bpp * 21 / 20;
4439                         lane = bps / (link_bw * 8) + 1;
4440                 }
4441
4442                 intel_crtc->fdi_lanes = lane;
4443
4444                 if (pixel_multiplier > 1)
4445                         link_bw *= pixel_multiplier;
4446                 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
4447         }
4448
4449         /* Ironlake: try to setup display ref clock before DPLL
4450          * enabling. This is only under driver's control after
4451          * PCH B stepping, previous chipset stepping should be
4452          * ignoring this setting.
4453          */
4454         if (HAS_PCH_SPLIT(dev)) {
4455                 temp = I915_READ(PCH_DREF_CONTROL);
4456                 /* Always enable nonspread source */
4457                 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4458                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4459                 temp &= ~DREF_SSC_SOURCE_MASK;
4460                 temp |= DREF_SSC_SOURCE_ENABLE;
4461                 I915_WRITE(PCH_DREF_CONTROL, temp);
4462
4463                 POSTING_READ(PCH_DREF_CONTROL);
4464                 udelay(200);
4465
4466                 if (has_edp_encoder) {
4467                         if (intel_panel_use_ssc(dev_priv)) {
4468                                 temp |= DREF_SSC1_ENABLE;
4469                                 I915_WRITE(PCH_DREF_CONTROL, temp);
4470
4471                                 POSTING_READ(PCH_DREF_CONTROL);
4472                                 udelay(200);
4473                         }
4474                         temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4475
4476                         /* Enable CPU source on CPU attached eDP */
4477                         if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4478                                 if (intel_panel_use_ssc(dev_priv))
4479                                         temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4480                                 else
4481                                         temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4482                         } else {
4483                                 /* Enable SSC on PCH eDP if needed */
4484                                 if (intel_panel_use_ssc(dev_priv)) {
4485                                         DRM_ERROR("enabling SSC on PCH\n");
4486                                         temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
4487                                 }
4488                         }
4489                         I915_WRITE(PCH_DREF_CONTROL, temp);
4490                         POSTING_READ(PCH_DREF_CONTROL);
4491                         udelay(200);
4492                 }
4493         }
4494
4495         if (IS_PINEVIEW(dev)) {
4496                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
4497                 if (has_reduced_clock)
4498                         fp2 = (1 << reduced_clock.n) << 16 |
4499                                 reduced_clock.m1 << 8 | reduced_clock.m2;
4500         } else {
4501                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4502                 if (has_reduced_clock)
4503                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4504                                 reduced_clock.m2;
4505         }
4506
4507         /* Enable autotuning of the PLL clock (if permissible) */
4508         if (HAS_PCH_SPLIT(dev)) {
4509                 int factor = 21;
4510
4511                 if (is_lvds) {
4512                         if ((intel_panel_use_ssc(dev_priv) &&
4513                              dev_priv->lvds_ssc_freq == 100) ||
4514                             (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4515                                 factor = 25;
4516                 } else if (is_sdvo && is_tv)
4517                         factor = 20;
4518
4519                 if (clock.m1 < factor * clock.n)
4520                         fp |= FP_CB_TUNE;
4521         }
4522
4523         dpll = 0;
4524         if (!HAS_PCH_SPLIT(dev))
4525                 dpll = DPLL_VGA_MODE_DIS;
4526
4527         if (!IS_GEN2(dev)) {
4528                 if (is_lvds)
4529                         dpll |= DPLLB_MODE_LVDS;
4530                 else
4531                         dpll |= DPLLB_MODE_DAC_SERIAL;
4532                 if (is_sdvo) {
4533                         int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4534                         if (pixel_multiplier > 1) {
4535                                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4536                                         dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4537                                 else if (HAS_PCH_SPLIT(dev))
4538                                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
4539                         }
4540                         dpll |= DPLL_DVO_HIGH_SPEED;
4541                 }
4542                 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
4543                         dpll |= DPLL_DVO_HIGH_SPEED;
4544
4545                 /* compute bitmask from p1 value */
4546                 if (IS_PINEVIEW(dev))
4547                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4548                 else {
4549                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4550                         /* also FPA1 */
4551                         if (HAS_PCH_SPLIT(dev))
4552                                 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4553                         if (IS_G4X(dev) && has_reduced_clock)
4554                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4555                 }
4556                 switch (clock.p2) {
4557                 case 5:
4558                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4559                         break;
4560                 case 7:
4561                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4562                         break;
4563                 case 10:
4564                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4565                         break;
4566                 case 14:
4567                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4568                         break;
4569                 }
4570                 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
4571                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4572         } else {
4573                 if (is_lvds) {
4574                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4575                 } else {
4576                         if (clock.p1 == 2)
4577                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
4578                         else
4579                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4580                         if (clock.p2 == 4)
4581                                 dpll |= PLL_P2_DIVIDE_BY_4;
4582                 }
4583         }
4584
4585         if (is_sdvo && is_tv)
4586                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4587         else if (is_tv)
4588                 /* XXX: just matching BIOS for now */
4589                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4590                 dpll |= 3;
4591         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4592                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4593         else
4594                 dpll |= PLL_REF_INPUT_DREFCLK;
4595
4596         /* setup pipeconf */
4597         pipeconf = I915_READ(PIPECONF(pipe));
4598
4599         /* Set up the display plane register */
4600         dspcntr = DISPPLANE_GAMMA_ENABLE;
4601
4602         /* Ironlake's plane is forced to pipe, bit 24 is to
4603            enable color space conversion */
4604         if (!HAS_PCH_SPLIT(dev)) {
4605                 if (pipe == 0)
4606                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4607                 else
4608                         dspcntr |= DISPPLANE_SEL_PIPE_B;
4609         }
4610
4611         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4612                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4613                  * core speed.
4614                  *
4615                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4616                  * pipe == 0 check?
4617                  */
4618                 if (mode->clock >
4619                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4620                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4621                 else
4622                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4623         }
4624
4625         if (!HAS_PCH_SPLIT(dev))
4626                 dpll |= DPLL_VCO_ENABLE;
4627
4628         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4629         drm_mode_debug_printmodeline(mode);
4630
4631         /* assign to Ironlake registers */
4632         if (HAS_PCH_SPLIT(dev)) {
4633                 fp_reg = PCH_FP0(pipe);
4634                 dpll_reg = PCH_DPLL(pipe);
4635         } else {
4636                 fp_reg = FP0(pipe);
4637                 dpll_reg = DPLL(pipe);
4638         }
4639
4640         /* PCH eDP needs FDI, but CPU eDP does not */
4641         if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4642                 I915_WRITE(fp_reg, fp);
4643                 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
4644
4645                 POSTING_READ(dpll_reg);
4646                 udelay(150);
4647         }
4648
4649         /* enable transcoder DPLL */
4650         if (HAS_PCH_CPT(dev)) {
4651                 temp = I915_READ(PCH_DPLL_SEL);
4652                 if (pipe == 0)
4653                         temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL;
4654                 else
4655                         temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
4656                 I915_WRITE(PCH_DPLL_SEL, temp);
4657
4658                 POSTING_READ(PCH_DPLL_SEL);
4659                 udelay(150);
4660         }
4661
4662         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4663          * This is an exception to the general rule that mode_set doesn't turn
4664          * things on.
4665          */
4666         if (is_lvds) {
4667                 reg = LVDS;
4668                 if (HAS_PCH_SPLIT(dev))
4669                         reg = PCH_LVDS;
4670
4671                 temp = I915_READ(reg);
4672                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4673                 if (pipe == 1) {
4674                         if (HAS_PCH_CPT(dev))
4675                                 temp |= PORT_TRANS_B_SEL_CPT;
4676                         else
4677                                 temp |= LVDS_PIPEB_SELECT;
4678                 } else {
4679                         if (HAS_PCH_CPT(dev))
4680                                 temp &= ~PORT_TRANS_SEL_MASK;
4681                         else
4682                                 temp &= ~LVDS_PIPEB_SELECT;
4683                 }
4684                 /* set the corresponsding LVDS_BORDER bit */
4685                 temp |= dev_priv->lvds_border_bits;
4686                 /* Set the B0-B3 data pairs corresponding to whether we're going to
4687                  * set the DPLLs for dual-channel mode or not.
4688                  */
4689                 if (clock.p2 == 7)
4690                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4691                 else
4692                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4693
4694                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4695                  * appropriately here, but we need to look more thoroughly into how
4696                  * panels behave in the two modes.
4697                  */
4698                 /* set the dithering flag on non-PCH LVDS as needed */
4699                 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
4700                         if (dev_priv->lvds_dither)
4701                                 temp |= LVDS_ENABLE_DITHER;
4702                         else
4703                                 temp &= ~LVDS_ENABLE_DITHER;
4704                 }
4705                 I915_WRITE(reg, temp);
4706         }
4707
4708         /* set the dithering flag and clear for anything other than a panel. */
4709         if (HAS_PCH_SPLIT(dev)) {
4710                 pipeconf &= ~PIPECONF_DITHER_EN;
4711                 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
4712                 if (dev_priv->lvds_dither && (is_lvds || has_edp_encoder)) {
4713                         pipeconf |= PIPECONF_DITHER_EN;
4714                         pipeconf |= PIPECONF_DITHER_TYPE_ST1;
4715                 }
4716         }
4717
4718         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4719                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4720         } else if (HAS_PCH_SPLIT(dev)) {
4721                 /* For non-DP output, clear any trans DP clock recovery setting.*/
4722                 if (pipe == 0) {
4723                         I915_WRITE(TRANSA_DATA_M1, 0);
4724                         I915_WRITE(TRANSA_DATA_N1, 0);
4725                         I915_WRITE(TRANSA_DP_LINK_M1, 0);
4726                         I915_WRITE(TRANSA_DP_LINK_N1, 0);
4727                 } else {
4728                         I915_WRITE(TRANSB_DATA_M1, 0);
4729                         I915_WRITE(TRANSB_DATA_N1, 0);
4730                         I915_WRITE(TRANSB_DP_LINK_M1, 0);
4731                         I915_WRITE(TRANSB_DP_LINK_N1, 0);
4732                 }
4733         }
4734
4735         if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4736                 I915_WRITE(dpll_reg, dpll);
4737
4738                 /* Wait for the clocks to stabilize. */
4739                 POSTING_READ(dpll_reg);
4740                 udelay(150);
4741
4742                 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
4743                         temp = 0;
4744                         if (is_sdvo) {
4745                                 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4746                                 if (temp > 1)
4747                                         temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4748                                 else
4749                                         temp = 0;
4750                         }
4751                         I915_WRITE(DPLL_MD(pipe), temp);
4752                 } else {
4753                         /* The pixel multiplier can only be updated once the
4754                          * DPLL is enabled and the clocks are stable.
4755                          *
4756                          * So write it again.
4757                          */
4758                         I915_WRITE(dpll_reg, dpll);
4759                 }
4760         }
4761
4762         intel_crtc->lowfreq_avail = false;
4763         if (is_lvds && has_reduced_clock && i915_powersave) {
4764                 I915_WRITE(fp_reg + 4, fp2);
4765                 intel_crtc->lowfreq_avail = true;
4766                 if (HAS_PIPE_CXSR(dev)) {
4767                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4768                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4769                 }
4770         } else {
4771                 I915_WRITE(fp_reg + 4, fp);
4772                 if (HAS_PIPE_CXSR(dev)) {
4773                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4774                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4775                 }
4776         }
4777
4778         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4779                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4780                 /* the chip adds 2 halflines automatically */
4781                 adjusted_mode->crtc_vdisplay -= 1;
4782                 adjusted_mode->crtc_vtotal -= 1;
4783                 adjusted_mode->crtc_vblank_start -= 1;
4784                 adjusted_mode->crtc_vblank_end -= 1;
4785                 adjusted_mode->crtc_vsync_end -= 1;
4786                 adjusted_mode->crtc_vsync_start -= 1;
4787         } else
4788                 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
4789
4790         I915_WRITE(HTOTAL(pipe),
4791                    (adjusted_mode->crtc_hdisplay - 1) |
4792                    ((adjusted_mode->crtc_htotal - 1) << 16));
4793         I915_WRITE(HBLANK(pipe),
4794                    (adjusted_mode->crtc_hblank_start - 1) |
4795                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4796         I915_WRITE(HSYNC(pipe),
4797                    (adjusted_mode->crtc_hsync_start - 1) |
4798                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4799
4800         I915_WRITE(VTOTAL(pipe),
4801                    (adjusted_mode->crtc_vdisplay - 1) |
4802                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4803         I915_WRITE(VBLANK(pipe),
4804                    (adjusted_mode->crtc_vblank_start - 1) |
4805                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4806         I915_WRITE(VSYNC(pipe),
4807                    (adjusted_mode->crtc_vsync_start - 1) |
4808                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4809
4810         /* pipesrc and dspsize control the size that is scaled from,
4811          * which should always be the user's requested size.
4812          */
4813         if (!HAS_PCH_SPLIT(dev)) {
4814                 I915_WRITE(DSPSIZE(plane),
4815                            ((mode->vdisplay - 1) << 16) |
4816                            (mode->hdisplay - 1));
4817                 I915_WRITE(DSPPOS(plane), 0);
4818         }
4819         I915_WRITE(PIPESRC(pipe),
4820                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4821
4822         if (HAS_PCH_SPLIT(dev)) {
4823                 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4824                 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4825                 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4826                 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
4827
4828                 if (has_edp_encoder && !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4829                         ironlake_set_pll_edp(crtc, adjusted_mode->clock);
4830                 }
4831         }
4832
4833         I915_WRITE(PIPECONF(pipe), pipeconf);
4834         POSTING_READ(PIPECONF(pipe));
4835         if (!HAS_PCH_SPLIT(dev))
4836                 intel_enable_pipe(dev_priv, pipe, false);
4837
4838         intel_wait_for_vblank(dev, pipe);
4839
4840         if (IS_GEN5(dev)) {
4841                 /* enable address swizzle for tiling buffer */
4842                 temp = I915_READ(DISP_ARB_CTL);
4843                 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
4844         }
4845
4846         I915_WRITE(DSPCNTR(plane), dspcntr);
4847         POSTING_READ(DSPCNTR(plane));
4848         if (!HAS_PCH_SPLIT(dev))
4849                 intel_enable_plane(dev_priv, plane, pipe);
4850
4851         ret = intel_pipe_set_base(crtc, x, y, old_fb);
4852
4853         intel_update_watermarks(dev);
4854
4855         drm_vblank_post_modeset(dev, pipe);
4856
4857         return ret;
4858 }
4859
4860 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4861 void intel_crtc_load_lut(struct drm_crtc *crtc)
4862 {
4863         struct drm_device *dev = crtc->dev;
4864         struct drm_i915_private *dev_priv = dev->dev_private;
4865         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4866         int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
4867         int i;
4868
4869         /* The clocks have to be on to load the palette. */
4870         if (!crtc->enabled)
4871                 return;
4872
4873         /* use legacy palette for Ironlake */
4874         if (HAS_PCH_SPLIT(dev))
4875                 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
4876                                                    LGC_PALETTE_B;
4877
4878         for (i = 0; i < 256; i++) {
4879                 I915_WRITE(palreg + 4 * i,
4880                            (intel_crtc->lut_r[i] << 16) |
4881                            (intel_crtc->lut_g[i] << 8) |
4882                            intel_crtc->lut_b[i]);
4883         }
4884 }
4885
4886 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
4887 {
4888         struct drm_device *dev = crtc->dev;
4889         struct drm_i915_private *dev_priv = dev->dev_private;
4890         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4891         bool visible = base != 0;
4892         u32 cntl;
4893
4894         if (intel_crtc->cursor_visible == visible)
4895                 return;
4896
4897         cntl = I915_READ(CURACNTR);
4898         if (visible) {
4899                 /* On these chipsets we can only modify the base whilst
4900                  * the cursor is disabled.
4901                  */
4902                 I915_WRITE(CURABASE, base);
4903
4904                 cntl &= ~(CURSOR_FORMAT_MASK);
4905                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
4906                 cntl |= CURSOR_ENABLE |
4907                         CURSOR_GAMMA_ENABLE |
4908                         CURSOR_FORMAT_ARGB;
4909         } else
4910                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
4911         I915_WRITE(CURACNTR, cntl);
4912
4913         intel_crtc->cursor_visible = visible;
4914 }
4915
4916 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
4917 {
4918         struct drm_device *dev = crtc->dev;
4919         struct drm_i915_private *dev_priv = dev->dev_private;
4920         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4921         int pipe = intel_crtc->pipe;
4922         bool visible = base != 0;
4923
4924         if (intel_crtc->cursor_visible != visible) {
4925                 uint32_t cntl = I915_READ(pipe == 0 ? CURACNTR : CURBCNTR);
4926                 if (base) {
4927                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4928                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4929                         cntl |= pipe << 28; /* Connect to correct pipe */
4930                 } else {
4931                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4932                         cntl |= CURSOR_MODE_DISABLE;
4933                 }
4934                 I915_WRITE(pipe == 0 ? CURACNTR : CURBCNTR, cntl);
4935
4936                 intel_crtc->cursor_visible = visible;
4937         }
4938         /* and commit changes on next vblank */
4939         I915_WRITE(pipe == 0 ? CURABASE : CURBBASE, base);
4940 }
4941
4942 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
4943 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
4944                                      bool on)
4945 {
4946         struct drm_device *dev = crtc->dev;
4947         struct drm_i915_private *dev_priv = dev->dev_private;
4948         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4949         int pipe = intel_crtc->pipe;
4950         int x = intel_crtc->cursor_x;
4951         int y = intel_crtc->cursor_y;
4952         u32 base, pos;
4953         bool visible;
4954
4955         pos = 0;
4956
4957         if (on && crtc->enabled && crtc->fb) {
4958                 base = intel_crtc->cursor_addr;
4959                 if (x > (int) crtc->fb->width)
4960                         base = 0;
4961
4962                 if (y > (int) crtc->fb->height)
4963                         base = 0;
4964         } else
4965                 base = 0;
4966
4967         if (x < 0) {
4968                 if (x + intel_crtc->cursor_width < 0)
4969                         base = 0;
4970
4971                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
4972                 x = -x;
4973         }
4974         pos |= x << CURSOR_X_SHIFT;
4975
4976         if (y < 0) {
4977                 if (y + intel_crtc->cursor_height < 0)
4978                         base = 0;
4979
4980                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
4981                 y = -y;
4982         }
4983         pos |= y << CURSOR_Y_SHIFT;
4984
4985         visible = base != 0;
4986         if (!visible && !intel_crtc->cursor_visible)
4987                 return;
4988
4989         I915_WRITE(pipe == 0 ? CURAPOS : CURBPOS, pos);
4990         if (IS_845G(dev) || IS_I865G(dev))
4991                 i845_update_cursor(crtc, base);
4992         else
4993                 i9xx_update_cursor(crtc, base);
4994
4995         if (visible)
4996                 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
4997 }
4998
4999 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
5000                                  struct drm_file *file,
5001                                  uint32_t handle,
5002                                  uint32_t width, uint32_t height)
5003 {
5004         struct drm_device *dev = crtc->dev;
5005         struct drm_i915_private *dev_priv = dev->dev_private;
5006         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5007         struct drm_i915_gem_object *obj;
5008         uint32_t addr;
5009         int ret;
5010
5011         DRM_DEBUG_KMS("\n");
5012
5013         /* if we want to turn off the cursor ignore width and height */
5014         if (!handle) {
5015                 DRM_DEBUG_KMS("cursor off\n");
5016                 addr = 0;
5017                 obj = NULL;
5018                 mutex_lock(&dev->struct_mutex);
5019                 goto finish;
5020         }
5021
5022         /* Currently we only support 64x64 cursors */
5023         if (width != 64 || height != 64) {
5024                 DRM_ERROR("we currently only support 64x64 cursors\n");
5025                 return -EINVAL;
5026         }
5027
5028         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
5029         if (!obj)
5030                 return -ENOENT;
5031
5032         if (obj->base.size < width * height * 4) {
5033                 DRM_ERROR("buffer is to small\n");
5034                 ret = -ENOMEM;
5035                 goto fail;
5036         }
5037
5038         /* we only need to pin inside GTT if cursor is non-phy */
5039         mutex_lock(&dev->struct_mutex);
5040         if (!dev_priv->info->cursor_needs_physical) {
5041                 if (obj->tiling_mode) {
5042                         DRM_ERROR("cursor cannot be tiled\n");
5043                         ret = -EINVAL;
5044                         goto fail_locked;
5045                 }
5046
5047                 ret = i915_gem_object_pin(obj, PAGE_SIZE, true);
5048                 if (ret) {
5049                         DRM_ERROR("failed to pin cursor bo\n");
5050                         goto fail_locked;
5051                 }
5052
5053                 ret = i915_gem_object_set_to_gtt_domain(obj, 0);
5054                 if (ret) {
5055                         DRM_ERROR("failed to move cursor bo into the GTT\n");
5056                         goto fail_unpin;
5057                 }
5058
5059                 ret = i915_gem_object_put_fence(obj);
5060                 if (ret) {
5061                         DRM_ERROR("failed to move cursor bo into the GTT\n");
5062                         goto fail_unpin;
5063                 }
5064
5065                 addr = obj->gtt_offset;
5066         } else {
5067                 int align = IS_I830(dev) ? 16 * 1024 : 256;
5068                 ret = i915_gem_attach_phys_object(dev, obj,
5069                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5070                                                   align);
5071                 if (ret) {
5072                         DRM_ERROR("failed to attach phys object\n");
5073                         goto fail_locked;
5074                 }
5075                 addr = obj->phys_obj->handle->busaddr;
5076         }
5077
5078         if (IS_GEN2(dev))
5079                 I915_WRITE(CURSIZE, (height << 12) | width);
5080
5081  finish:
5082         if (intel_crtc->cursor_bo) {
5083                 if (dev_priv->info->cursor_needs_physical) {
5084                         if (intel_crtc->cursor_bo != obj)
5085                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5086                 } else
5087                         i915_gem_object_unpin(intel_crtc->cursor_bo);
5088                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
5089         }
5090
5091         mutex_unlock(&dev->struct_mutex);
5092
5093         intel_crtc->cursor_addr = addr;
5094         intel_crtc->cursor_bo = obj;
5095         intel_crtc->cursor_width = width;
5096         intel_crtc->cursor_height = height;
5097
5098         intel_crtc_update_cursor(crtc, true);
5099
5100         return 0;
5101 fail_unpin:
5102         i915_gem_object_unpin(obj);
5103 fail_locked:
5104         mutex_unlock(&dev->struct_mutex);
5105 fail:
5106         drm_gem_object_unreference_unlocked(&obj->base);
5107         return ret;
5108 }
5109
5110 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5111 {
5112         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5113
5114         intel_crtc->cursor_x = x;
5115         intel_crtc->cursor_y = y;
5116
5117         intel_crtc_update_cursor(crtc, true);
5118
5119         return 0;
5120 }
5121
5122 /** Sets the color ramps on behalf of RandR */
5123 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5124                                  u16 blue, int regno)
5125 {
5126         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5127
5128         intel_crtc->lut_r[regno] = red >> 8;
5129         intel_crtc->lut_g[regno] = green >> 8;
5130         intel_crtc->lut_b[regno] = blue >> 8;
5131 }
5132
5133 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5134                              u16 *blue, int regno)
5135 {
5136         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5137
5138         *red = intel_crtc->lut_r[regno] << 8;
5139         *green = intel_crtc->lut_g[regno] << 8;
5140         *blue = intel_crtc->lut_b[regno] << 8;
5141 }
5142
5143 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
5144                                  u16 *blue, uint32_t start, uint32_t size)
5145 {
5146         int end = (start + size > 256) ? 256 : start + size, i;
5147         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5148
5149         for (i = start; i < end; i++) {
5150                 intel_crtc->lut_r[i] = red[i] >> 8;
5151                 intel_crtc->lut_g[i] = green[i] >> 8;
5152                 intel_crtc->lut_b[i] = blue[i] >> 8;
5153         }
5154
5155         intel_crtc_load_lut(crtc);
5156 }
5157
5158 /**
5159  * Get a pipe with a simple mode set on it for doing load-based monitor
5160  * detection.
5161  *
5162  * It will be up to the load-detect code to adjust the pipe as appropriate for
5163  * its requirements.  The pipe will be connected to no other encoders.
5164  *
5165  * Currently this code will only succeed if there is a pipe with no encoders
5166  * configured for it.  In the future, it could choose to temporarily disable
5167  * some outputs to free up a pipe for its use.
5168  *
5169  * \return crtc, or NULL if no pipes are available.
5170  */
5171
5172 /* VESA 640x480x72Hz mode to set on the pipe */
5173 static struct drm_display_mode load_detect_mode = {
5174         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5175                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5176 };
5177
5178 struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
5179                                             struct drm_connector *connector,
5180                                             struct drm_display_mode *mode,
5181                                             int *dpms_mode)
5182 {
5183         struct intel_crtc *intel_crtc;
5184         struct drm_crtc *possible_crtc;
5185         struct drm_crtc *supported_crtc =NULL;
5186         struct drm_encoder *encoder = &intel_encoder->base;
5187         struct drm_crtc *crtc = NULL;
5188         struct drm_device *dev = encoder->dev;
5189         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
5190         struct drm_crtc_helper_funcs *crtc_funcs;
5191         int i = -1;
5192
5193         /*
5194          * Algorithm gets a little messy:
5195          *   - if the connector already has an assigned crtc, use it (but make
5196          *     sure it's on first)
5197          *   - try to find the first unused crtc that can drive this connector,
5198          *     and use that if we find one
5199          *   - if there are no unused crtcs available, try to use the first
5200          *     one we found that supports the connector
5201          */
5202
5203         /* See if we already have a CRTC for this connector */
5204         if (encoder->crtc) {
5205                 crtc = encoder->crtc;
5206                 /* Make sure the crtc and connector are running */
5207                 intel_crtc = to_intel_crtc(crtc);
5208                 *dpms_mode = intel_crtc->dpms_mode;
5209                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
5210                         crtc_funcs = crtc->helper_private;
5211                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
5212                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
5213                 }
5214                 return crtc;
5215         }
5216
5217         /* Find an unused one (if possible) */
5218         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5219                 i++;
5220                 if (!(encoder->possible_crtcs & (1 << i)))
5221                         continue;
5222                 if (!possible_crtc->enabled) {
5223                         crtc = possible_crtc;
5224                         break;
5225                 }
5226                 if (!supported_crtc)
5227                         supported_crtc = possible_crtc;
5228         }
5229
5230         /*
5231          * If we didn't find an unused CRTC, don't use any.
5232          */
5233         if (!crtc) {
5234                 return NULL;
5235         }
5236
5237         encoder->crtc = crtc;
5238         connector->encoder = encoder;
5239         intel_encoder->load_detect_temp = true;
5240
5241         intel_crtc = to_intel_crtc(crtc);
5242         *dpms_mode = intel_crtc->dpms_mode;
5243
5244         if (!crtc->enabled) {
5245                 if (!mode)
5246                         mode = &load_detect_mode;
5247                 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
5248         } else {
5249                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
5250                         crtc_funcs = crtc->helper_private;
5251                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
5252                 }
5253
5254                 /* Add this connector to the crtc */
5255                 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
5256                 encoder_funcs->commit(encoder);
5257         }
5258         /* let the connector get through one full cycle before testing */
5259         intel_wait_for_vblank(dev, intel_crtc->pipe);
5260
5261         return crtc;
5262 }
5263
5264 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
5265                                     struct drm_connector *connector, int dpms_mode)
5266 {
5267         struct drm_encoder *encoder = &intel_encoder->base;
5268         struct drm_device *dev = encoder->dev;
5269         struct drm_crtc *crtc = encoder->crtc;
5270         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
5271         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
5272
5273         if (intel_encoder->load_detect_temp) {
5274                 encoder->crtc = NULL;
5275                 connector->encoder = NULL;
5276                 intel_encoder->load_detect_temp = false;
5277                 crtc->enabled = drm_helper_crtc_in_use(crtc);
5278                 drm_helper_disable_unused_functions(dev);
5279         }
5280
5281         /* Switch crtc and encoder back off if necessary */
5282         if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
5283                 if (encoder->crtc == crtc)
5284                         encoder_funcs->dpms(encoder, dpms_mode);
5285                 crtc_funcs->dpms(crtc, dpms_mode);
5286         }
5287 }
5288
5289 /* Returns the clock of the currently programmed mode of the given pipe. */
5290 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5291 {
5292         struct drm_i915_private *dev_priv = dev->dev_private;
5293         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5294         int pipe = intel_crtc->pipe;
5295         u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
5296         u32 fp;
5297         intel_clock_t clock;
5298
5299         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
5300                 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
5301         else
5302                 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
5303
5304         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
5305         if (IS_PINEVIEW(dev)) {
5306                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5307                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
5308         } else {
5309                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5310                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5311         }
5312
5313         if (!IS_GEN2(dev)) {
5314                 if (IS_PINEVIEW(dev))
5315                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5316                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
5317                 else
5318                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
5319                                DPLL_FPA01_P1_POST_DIV_SHIFT);
5320
5321                 switch (dpll & DPLL_MODE_MASK) {
5322                 case DPLLB_MODE_DAC_SERIAL:
5323                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5324                                 5 : 10;
5325                         break;
5326                 case DPLLB_MODE_LVDS:
5327                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5328                                 7 : 14;
5329                         break;
5330                 default:
5331                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
5332                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
5333                         return 0;
5334                 }
5335
5336                 /* XXX: Handle the 100Mhz refclk */
5337                 intel_clock(dev, 96000, &clock);
5338         } else {
5339                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5340
5341                 if (is_lvds) {
5342                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5343                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
5344                         clock.p2 = 14;
5345
5346                         if ((dpll & PLL_REF_INPUT_MASK) ==
5347                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5348                                 /* XXX: might not be 66MHz */
5349                                 intel_clock(dev, 66000, &clock);
5350                         } else
5351                                 intel_clock(dev, 48000, &clock);
5352                 } else {
5353                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
5354                                 clock.p1 = 2;
5355                         else {
5356                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5357                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5358                         }
5359                         if (dpll & PLL_P2_DIVIDE_BY_4)
5360                                 clock.p2 = 4;
5361                         else
5362                                 clock.p2 = 2;
5363
5364                         intel_clock(dev, 48000, &clock);
5365                 }
5366         }
5367
5368         /* XXX: It would be nice to validate the clocks, but we can't reuse
5369          * i830PllIsValid() because it relies on the xf86_config connector
5370          * configuration being accurate, which it isn't necessarily.
5371          */
5372
5373         return clock.dot;
5374 }
5375
5376 /** Returns the currently programmed mode of the given pipe. */
5377 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5378                                              struct drm_crtc *crtc)
5379 {
5380         struct drm_i915_private *dev_priv = dev->dev_private;
5381         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5382         int pipe = intel_crtc->pipe;
5383         struct drm_display_mode *mode;
5384         int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
5385         int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
5386         int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
5387         int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
5388
5389         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
5390         if (!mode)
5391                 return NULL;
5392
5393         mode->clock = intel_crtc_clock_get(dev, crtc);
5394         mode->hdisplay = (htot & 0xffff) + 1;
5395         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
5396         mode->hsync_start = (hsync & 0xffff) + 1;
5397         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
5398         mode->vdisplay = (vtot & 0xffff) + 1;
5399         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
5400         mode->vsync_start = (vsync & 0xffff) + 1;
5401         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
5402
5403         drm_mode_set_name(mode);
5404         drm_mode_set_crtcinfo(mode, 0);
5405
5406         return mode;
5407 }
5408
5409 #define GPU_IDLE_TIMEOUT 500 /* ms */
5410
5411 /* When this timer fires, we've been idle for awhile */
5412 static void intel_gpu_idle_timer(unsigned long arg)
5413 {
5414         struct drm_device *dev = (struct drm_device *)arg;
5415         drm_i915_private_t *dev_priv = dev->dev_private;
5416
5417         if (!list_empty(&dev_priv->mm.active_list)) {
5418                 /* Still processing requests, so just re-arm the timer. */
5419                 mod_timer(&dev_priv->idle_timer, jiffies +
5420                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5421                 return;
5422         }
5423
5424         dev_priv->busy = false;
5425         queue_work(dev_priv->wq, &dev_priv->idle_work);
5426 }
5427
5428 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
5429
5430 static void intel_crtc_idle_timer(unsigned long arg)
5431 {
5432         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
5433         struct drm_crtc *crtc = &intel_crtc->base;
5434         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
5435         struct intel_framebuffer *intel_fb;
5436
5437         intel_fb = to_intel_framebuffer(crtc->fb);
5438         if (intel_fb && intel_fb->obj->active) {
5439                 /* The framebuffer is still being accessed by the GPU. */
5440                 mod_timer(&intel_crtc->idle_timer, jiffies +
5441                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5442                 return;
5443         }
5444
5445         intel_crtc->busy = false;
5446         queue_work(dev_priv->wq, &dev_priv->idle_work);
5447 }
5448
5449 static void intel_increase_pllclock(struct drm_crtc *crtc)
5450 {
5451         struct drm_device *dev = crtc->dev;
5452         drm_i915_private_t *dev_priv = dev->dev_private;
5453         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5454         int pipe = intel_crtc->pipe;
5455         int dpll_reg = DPLL(pipe);
5456         int dpll;
5457
5458         if (HAS_PCH_SPLIT(dev))
5459                 return;
5460
5461         if (!dev_priv->lvds_downclock_avail)
5462                 return;
5463
5464         dpll = I915_READ(dpll_reg);
5465         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
5466                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
5467
5468                 /* Unlock panel regs */
5469                 I915_WRITE(PP_CONTROL,
5470                            I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
5471
5472                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
5473                 I915_WRITE(dpll_reg, dpll);
5474                 POSTING_READ(dpll_reg);
5475                 intel_wait_for_vblank(dev, pipe);
5476
5477                 dpll = I915_READ(dpll_reg);
5478                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
5479                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
5480
5481                 /* ...and lock them again */
5482                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
5483         }
5484
5485         /* Schedule downclock */
5486         mod_timer(&intel_crtc->idle_timer, jiffies +
5487                   msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5488 }
5489
5490 static void intel_decrease_pllclock(struct drm_crtc *crtc)
5491 {
5492         struct drm_device *dev = crtc->dev;
5493         drm_i915_private_t *dev_priv = dev->dev_private;
5494         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5495         int pipe = intel_crtc->pipe;
5496         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
5497         int dpll = I915_READ(dpll_reg);
5498
5499         if (HAS_PCH_SPLIT(dev))
5500                 return;
5501
5502         if (!dev_priv->lvds_downclock_avail)
5503                 return;
5504
5505         /*
5506          * Since this is called by a timer, we should never get here in
5507          * the manual case.
5508          */
5509         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
5510                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
5511
5512                 /* Unlock panel regs */
5513                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
5514                            PANEL_UNLOCK_REGS);
5515
5516                 dpll |= DISPLAY_RATE_SELECT_FPA1;
5517                 I915_WRITE(dpll_reg, dpll);
5518                 dpll = I915_READ(dpll_reg);
5519                 intel_wait_for_vblank(dev, pipe);
5520                 dpll = I915_READ(dpll_reg);
5521                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
5522                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
5523
5524                 /* ...and lock them again */
5525                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
5526         }
5527
5528 }
5529
5530 /**
5531  * intel_idle_update - adjust clocks for idleness
5532  * @work: work struct
5533  *
5534  * Either the GPU or display (or both) went idle.  Check the busy status
5535  * here and adjust the CRTC and GPU clocks as necessary.
5536  */
5537 static void intel_idle_update(struct work_struct *work)
5538 {
5539         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
5540                                                     idle_work);
5541         struct drm_device *dev = dev_priv->dev;
5542         struct drm_crtc *crtc;
5543         struct intel_crtc *intel_crtc;
5544         int enabled = 0;
5545
5546         if (!i915_powersave)
5547                 return;
5548
5549         mutex_lock(&dev->struct_mutex);
5550
5551         i915_update_gfx_val(dev_priv);
5552
5553         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5554                 /* Skip inactive CRTCs */
5555                 if (!crtc->fb)
5556                         continue;
5557
5558                 enabled++;
5559                 intel_crtc = to_intel_crtc(crtc);
5560                 if (!intel_crtc->busy)
5561                         intel_decrease_pllclock(crtc);
5562         }
5563
5564         if ((enabled == 1) && (IS_I945G(dev) || IS_I945GM(dev))) {
5565                 DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
5566                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
5567         }
5568
5569         mutex_unlock(&dev->struct_mutex);
5570 }
5571
5572 /**
5573  * intel_mark_busy - mark the GPU and possibly the display busy
5574  * @dev: drm device
5575  * @obj: object we're operating on
5576  *
5577  * Callers can use this function to indicate that the GPU is busy processing
5578  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
5579  * buffer), we'll also mark the display as busy, so we know to increase its
5580  * clock frequency.
5581  */
5582 void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
5583 {
5584         drm_i915_private_t *dev_priv = dev->dev_private;
5585         struct drm_crtc *crtc = NULL;
5586         struct intel_framebuffer *intel_fb;
5587         struct intel_crtc *intel_crtc;
5588
5589         if (!drm_core_check_feature(dev, DRIVER_MODESET))
5590                 return;
5591
5592         if (!dev_priv->busy) {
5593                 if (IS_I945G(dev) || IS_I945GM(dev)) {
5594                         u32 fw_blc_self;
5595
5596                         DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
5597                         fw_blc_self = I915_READ(FW_BLC_SELF);
5598                         fw_blc_self &= ~FW_BLC_SELF_EN;
5599                         I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
5600                 }
5601                 dev_priv->busy = true;
5602         } else
5603                 mod_timer(&dev_priv->idle_timer, jiffies +
5604                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5605
5606         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5607                 if (!crtc->fb)
5608                         continue;
5609
5610                 intel_crtc = to_intel_crtc(crtc);
5611                 intel_fb = to_intel_framebuffer(crtc->fb);
5612                 if (intel_fb->obj == obj) {
5613                         if (!intel_crtc->busy) {
5614                                 if (IS_I945G(dev) || IS_I945GM(dev)) {
5615                                         u32 fw_blc_self;
5616
5617                                         DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
5618                                         fw_blc_self = I915_READ(FW_BLC_SELF);
5619                                         fw_blc_self &= ~FW_BLC_SELF_EN;
5620                                         I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
5621                                 }
5622                                 /* Non-busy -> busy, upclock */
5623                                 intel_increase_pllclock(crtc);
5624                                 intel_crtc->busy = true;
5625                         } else {
5626                                 /* Busy -> busy, put off timer */
5627                                 mod_timer(&intel_crtc->idle_timer, jiffies +
5628                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5629                         }
5630                 }
5631         }
5632 }
5633
5634 static void intel_crtc_destroy(struct drm_crtc *crtc)
5635 {
5636         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5637         struct drm_device *dev = crtc->dev;
5638         struct intel_unpin_work *work;
5639         unsigned long flags;
5640
5641         spin_lock_irqsave(&dev->event_lock, flags);
5642         work = intel_crtc->unpin_work;
5643         intel_crtc->unpin_work = NULL;
5644         spin_unlock_irqrestore(&dev->event_lock, flags);
5645
5646         if (work) {
5647                 cancel_work_sync(&work->work);
5648                 kfree(work);
5649         }
5650
5651         drm_crtc_cleanup(crtc);
5652
5653         kfree(intel_crtc);
5654 }
5655
5656 static void intel_unpin_work_fn(struct work_struct *__work)
5657 {
5658         struct intel_unpin_work *work =
5659                 container_of(__work, struct intel_unpin_work, work);
5660
5661         mutex_lock(&work->dev->struct_mutex);
5662         i915_gem_object_unpin(work->old_fb_obj);
5663         drm_gem_object_unreference(&work->pending_flip_obj->base);
5664         drm_gem_object_unreference(&work->old_fb_obj->base);
5665
5666         mutex_unlock(&work->dev->struct_mutex);
5667         kfree(work);
5668 }
5669
5670 static void do_intel_finish_page_flip(struct drm_device *dev,
5671                                       struct drm_crtc *crtc)
5672 {
5673         drm_i915_private_t *dev_priv = dev->dev_private;
5674         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5675         struct intel_unpin_work *work;
5676         struct drm_i915_gem_object *obj;
5677         struct drm_pending_vblank_event *e;
5678         struct timeval tnow, tvbl;
5679         unsigned long flags;
5680
5681         /* Ignore early vblank irqs */
5682         if (intel_crtc == NULL)
5683                 return;
5684
5685         do_gettimeofday(&tnow);
5686
5687         spin_lock_irqsave(&dev->event_lock, flags);
5688         work = intel_crtc->unpin_work;
5689         if (work == NULL || !work->pending) {
5690                 spin_unlock_irqrestore(&dev->event_lock, flags);
5691                 return;
5692         }
5693
5694         intel_crtc->unpin_work = NULL;
5695
5696         if (work->event) {
5697                 e = work->event;
5698                 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
5699
5700                 /* Called before vblank count and timestamps have
5701                  * been updated for the vblank interval of flip
5702                  * completion? Need to increment vblank count and
5703                  * add one videorefresh duration to returned timestamp
5704                  * to account for this. We assume this happened if we
5705                  * get called over 0.9 frame durations after the last
5706                  * timestamped vblank.
5707                  *
5708                  * This calculation can not be used with vrefresh rates
5709                  * below 5Hz (10Hz to be on the safe side) without
5710                  * promoting to 64 integers.
5711                  */
5712                 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
5713                     9 * crtc->framedur_ns) {
5714                         e->event.sequence++;
5715                         tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
5716                                              crtc->framedur_ns);
5717                 }
5718
5719                 e->event.tv_sec = tvbl.tv_sec;
5720                 e->event.tv_usec = tvbl.tv_usec;
5721
5722                 list_add_tail(&e->base.link,
5723                               &e->base.file_priv->event_list);
5724                 wake_up_interruptible(&e->base.file_priv->event_wait);
5725         }
5726
5727         drm_vblank_put(dev, intel_crtc->pipe);
5728
5729         spin_unlock_irqrestore(&dev->event_lock, flags);
5730
5731         obj = work->old_fb_obj;
5732
5733         atomic_clear_mask(1 << intel_crtc->plane,
5734                           &obj->pending_flip.counter);
5735         if (atomic_read(&obj->pending_flip) == 0)
5736                 wake_up(&dev_priv->pending_flip_queue);
5737
5738         schedule_work(&work->work);
5739
5740         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
5741 }
5742
5743 void intel_finish_page_flip(struct drm_device *dev, int pipe)
5744 {
5745         drm_i915_private_t *dev_priv = dev->dev_private;
5746         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
5747
5748         do_intel_finish_page_flip(dev, crtc);
5749 }
5750
5751 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
5752 {
5753         drm_i915_private_t *dev_priv = dev->dev_private;
5754         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
5755
5756         do_intel_finish_page_flip(dev, crtc);
5757 }
5758
5759 void intel_prepare_page_flip(struct drm_device *dev, int plane)
5760 {
5761         drm_i915_private_t *dev_priv = dev->dev_private;
5762         struct intel_crtc *intel_crtc =
5763                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
5764         unsigned long flags;
5765
5766         spin_lock_irqsave(&dev->event_lock, flags);
5767         if (intel_crtc->unpin_work) {
5768                 if ((++intel_crtc->unpin_work->pending) > 1)
5769                         DRM_ERROR("Prepared flip multiple times\n");
5770         } else {
5771                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
5772         }
5773         spin_unlock_irqrestore(&dev->event_lock, flags);
5774 }
5775
5776 static int intel_crtc_page_flip(struct drm_crtc *crtc,
5777                                 struct drm_framebuffer *fb,
5778                                 struct drm_pending_vblank_event *event)
5779 {
5780         struct drm_device *dev = crtc->dev;
5781         struct drm_i915_private *dev_priv = dev->dev_private;
5782         struct intel_framebuffer *intel_fb;
5783         struct drm_i915_gem_object *obj;
5784         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5785         struct intel_unpin_work *work;
5786         unsigned long flags, offset;
5787         int pipe = intel_crtc->pipe;
5788         u32 pf, pipesrc;
5789         int ret;
5790
5791         work = kzalloc(sizeof *work, GFP_KERNEL);
5792         if (work == NULL)
5793                 return -ENOMEM;
5794
5795         work->event = event;
5796         work->dev = crtc->dev;
5797         intel_fb = to_intel_framebuffer(crtc->fb);
5798         work->old_fb_obj = intel_fb->obj;
5799         INIT_WORK(&work->work, intel_unpin_work_fn);
5800
5801         /* We borrow the event spin lock for protecting unpin_work */
5802         spin_lock_irqsave(&dev->event_lock, flags);
5803         if (intel_crtc->unpin_work) {
5804                 spin_unlock_irqrestore(&dev->event_lock, flags);
5805                 kfree(work);
5806
5807                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5808                 return -EBUSY;
5809         }
5810         intel_crtc->unpin_work = work;
5811         spin_unlock_irqrestore(&dev->event_lock, flags);
5812
5813         intel_fb = to_intel_framebuffer(fb);
5814         obj = intel_fb->obj;
5815
5816         mutex_lock(&dev->struct_mutex);
5817         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
5818         if (ret)
5819                 goto cleanup_work;
5820
5821         /* Reference the objects for the scheduled work. */
5822         drm_gem_object_reference(&work->old_fb_obj->base);
5823         drm_gem_object_reference(&obj->base);
5824
5825         crtc->fb = fb;
5826
5827         ret = drm_vblank_get(dev, intel_crtc->pipe);
5828         if (ret)
5829                 goto cleanup_objs;
5830
5831         if (IS_GEN3(dev) || IS_GEN2(dev)) {
5832                 u32 flip_mask;
5833
5834                 /* Can't queue multiple flips, so wait for the previous
5835                  * one to finish before executing the next.
5836                  */
5837                 ret = BEGIN_LP_RING(2);
5838                 if (ret)
5839                         goto cleanup_objs;
5840
5841                 if (intel_crtc->plane)
5842                         flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5843                 else
5844                         flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
5845                 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
5846                 OUT_RING(MI_NOOP);
5847                 ADVANCE_LP_RING();
5848         }
5849
5850         work->pending_flip_obj = obj;
5851
5852         work->enable_stall_check = true;
5853
5854         /* Offset into the new buffer for cases of shared fbs between CRTCs */
5855         offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
5856
5857         ret = BEGIN_LP_RING(4);
5858         if (ret)
5859                 goto cleanup_objs;
5860
5861         /* Block clients from rendering to the new back buffer until
5862          * the flip occurs and the object is no longer visible.
5863          */
5864         atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
5865
5866         switch (INTEL_INFO(dev)->gen) {
5867         case 2:
5868                 OUT_RING(MI_DISPLAY_FLIP |
5869                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5870                 OUT_RING(fb->pitch);
5871                 OUT_RING(obj->gtt_offset + offset);
5872                 OUT_RING(MI_NOOP);
5873                 break;
5874
5875         case 3:
5876                 OUT_RING(MI_DISPLAY_FLIP_I915 |
5877                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5878                 OUT_RING(fb->pitch);
5879                 OUT_RING(obj->gtt_offset + offset);
5880                 OUT_RING(MI_NOOP);
5881                 break;
5882
5883         case 4:
5884         case 5:
5885                 /* i965+ uses the linear or tiled offsets from the
5886                  * Display Registers (which do not change across a page-flip)
5887                  * so we need only reprogram the base address.
5888                  */
5889                 OUT_RING(MI_DISPLAY_FLIP |
5890                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5891                 OUT_RING(fb->pitch);
5892                 OUT_RING(obj->gtt_offset | obj->tiling_mode);
5893
5894                 /* XXX Enabling the panel-fitter across page-flip is so far
5895                  * untested on non-native modes, so ignore it for now.
5896                  * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5897                  */
5898                 pf = 0;
5899                 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
5900                 OUT_RING(pf | pipesrc);
5901                 break;
5902
5903         case 6:
5904                 OUT_RING(MI_DISPLAY_FLIP |
5905                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5906                 OUT_RING(fb->pitch | obj->tiling_mode);
5907                 OUT_RING(obj->gtt_offset);
5908
5909                 pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5910                 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
5911                 OUT_RING(pf | pipesrc);
5912                 break;
5913         }
5914         ADVANCE_LP_RING();
5915
5916         mutex_unlock(&dev->struct_mutex);
5917
5918         trace_i915_flip_request(intel_crtc->plane, obj);
5919
5920         return 0;
5921
5922 cleanup_objs:
5923         drm_gem_object_unreference(&work->old_fb_obj->base);
5924         drm_gem_object_unreference(&obj->base);
5925 cleanup_work:
5926         mutex_unlock(&dev->struct_mutex);
5927
5928         spin_lock_irqsave(&dev->event_lock, flags);
5929         intel_crtc->unpin_work = NULL;
5930         spin_unlock_irqrestore(&dev->event_lock, flags);
5931
5932         kfree(work);
5933
5934         return ret;
5935 }
5936
5937 static struct drm_crtc_helper_funcs intel_helper_funcs = {
5938         .dpms = intel_crtc_dpms,
5939         .mode_fixup = intel_crtc_mode_fixup,
5940         .mode_set = intel_crtc_mode_set,
5941         .mode_set_base = intel_pipe_set_base,
5942         .mode_set_base_atomic = intel_pipe_set_base_atomic,
5943         .load_lut = intel_crtc_load_lut,
5944         .disable = intel_crtc_disable,
5945 };
5946
5947 static const struct drm_crtc_funcs intel_crtc_funcs = {
5948         .cursor_set = intel_crtc_cursor_set,
5949         .cursor_move = intel_crtc_cursor_move,
5950         .gamma_set = intel_crtc_gamma_set,
5951         .set_config = drm_crtc_helper_set_config,
5952         .destroy = intel_crtc_destroy,
5953         .page_flip = intel_crtc_page_flip,
5954 };
5955
5956 static void intel_sanitize_modesetting(struct drm_device *dev,
5957                                        int pipe, int plane)
5958 {
5959         struct drm_i915_private *dev_priv = dev->dev_private;
5960         u32 reg, val;
5961
5962         if (HAS_PCH_SPLIT(dev))
5963                 return;
5964
5965         /* Who knows what state these registers were left in by the BIOS or
5966          * grub?
5967          *
5968          * If we leave the registers in a conflicting state (e.g. with the
5969          * display plane reading from the other pipe than the one we intend
5970          * to use) then when we attempt to teardown the active mode, we will
5971          * not disable the pipes and planes in the correct order -- leaving
5972          * a plane reading from a disabled pipe and possibly leading to
5973          * undefined behaviour.
5974          */
5975
5976         reg = DSPCNTR(plane);
5977         val = I915_READ(reg);
5978
5979         if ((val & DISPLAY_PLANE_ENABLE) == 0)
5980                 return;
5981         if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
5982                 return;
5983
5984         /* This display plane is active and attached to the other CPU pipe. */
5985         pipe = !pipe;
5986
5987         /* Disable the plane and wait for it to stop reading from the pipe. */
5988         intel_disable_plane(dev_priv, plane, pipe);
5989         intel_disable_pipe(dev_priv, pipe);
5990 }
5991
5992 static void intel_crtc_init(struct drm_device *dev, int pipe)
5993 {
5994         drm_i915_private_t *dev_priv = dev->dev_private;
5995         struct intel_crtc *intel_crtc;
5996         int i;
5997
5998         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
5999         if (intel_crtc == NULL)
6000                 return;
6001
6002         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
6003
6004         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
6005         for (i = 0; i < 256; i++) {
6006                 intel_crtc->lut_r[i] = i;
6007                 intel_crtc->lut_g[i] = i;
6008                 intel_crtc->lut_b[i] = i;
6009         }
6010
6011         /* Swap pipes & planes for FBC on pre-965 */
6012         intel_crtc->pipe = pipe;
6013         intel_crtc->plane = pipe;
6014         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
6015                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
6016                 intel_crtc->plane = !pipe;
6017         }
6018
6019         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
6020                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
6021         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
6022         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
6023
6024         intel_crtc->cursor_addr = 0;
6025         intel_crtc->dpms_mode = -1;
6026         intel_crtc->active = true; /* force the pipe off on setup_init_config */
6027
6028         if (HAS_PCH_SPLIT(dev)) {
6029                 intel_helper_funcs.prepare = ironlake_crtc_prepare;
6030                 intel_helper_funcs.commit = ironlake_crtc_commit;
6031         } else {
6032                 intel_helper_funcs.prepare = i9xx_crtc_prepare;
6033                 intel_helper_funcs.commit = i9xx_crtc_commit;
6034         }
6035
6036         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
6037
6038         intel_crtc->busy = false;
6039
6040         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
6041                     (unsigned long)intel_crtc);
6042
6043         intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
6044 }
6045
6046 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
6047                                 struct drm_file *file)
6048 {
6049         drm_i915_private_t *dev_priv = dev->dev_private;
6050         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
6051         struct drm_mode_object *drmmode_obj;
6052         struct intel_crtc *crtc;
6053
6054         if (!dev_priv) {
6055                 DRM_ERROR("called with no initialization\n");
6056                 return -EINVAL;
6057         }
6058
6059         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
6060                         DRM_MODE_OBJECT_CRTC);
6061
6062         if (!drmmode_obj) {
6063                 DRM_ERROR("no such CRTC id\n");
6064                 return -EINVAL;
6065         }
6066
6067         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
6068         pipe_from_crtc_id->pipe = crtc->pipe;
6069
6070         return 0;
6071 }
6072
6073 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
6074 {
6075         struct intel_encoder *encoder;
6076         int index_mask = 0;
6077         int entry = 0;
6078
6079         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6080                 if (type_mask & encoder->clone_mask)
6081                         index_mask |= (1 << entry);
6082                 entry++;
6083         }
6084
6085         return index_mask;
6086 }
6087
6088 static bool has_edp_a(struct drm_device *dev)
6089 {
6090         struct drm_i915_private *dev_priv = dev->dev_private;
6091
6092         if (!IS_MOBILE(dev))
6093                 return false;
6094
6095         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
6096                 return false;
6097
6098         if (IS_GEN5(dev) &&
6099             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
6100                 return false;
6101
6102         return true;
6103 }
6104
6105 static void intel_setup_outputs(struct drm_device *dev)
6106 {
6107         struct drm_i915_private *dev_priv = dev->dev_private;
6108         struct intel_encoder *encoder;
6109         bool dpd_is_edp = false;
6110         bool has_lvds = false;
6111
6112         if (IS_MOBILE(dev) && !IS_I830(dev))
6113                 has_lvds = intel_lvds_init(dev);
6114         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
6115                 /* disable the panel fitter on everything but LVDS */
6116                 I915_WRITE(PFIT_CONTROL, 0);
6117         }
6118
6119         if (HAS_PCH_SPLIT(dev)) {
6120                 dpd_is_edp = intel_dpd_is_edp(dev);
6121
6122                 if (has_edp_a(dev))
6123                         intel_dp_init(dev, DP_A);
6124
6125                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6126                         intel_dp_init(dev, PCH_DP_D);
6127         }
6128
6129         intel_crt_init(dev);
6130
6131         if (HAS_PCH_SPLIT(dev)) {
6132                 int found;
6133
6134                 if (I915_READ(HDMIB) & PORT_DETECTED) {
6135                         /* PCH SDVOB multiplex with HDMIB */
6136                         found = intel_sdvo_init(dev, PCH_SDVOB);
6137                         if (!found)
6138                                 intel_hdmi_init(dev, HDMIB);
6139                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
6140                                 intel_dp_init(dev, PCH_DP_B);
6141                 }
6142
6143                 if (I915_READ(HDMIC) & PORT_DETECTED)
6144                         intel_hdmi_init(dev, HDMIC);
6145
6146                 if (I915_READ(HDMID) & PORT_DETECTED)
6147                         intel_hdmi_init(dev, HDMID);
6148
6149                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
6150                         intel_dp_init(dev, PCH_DP_C);
6151
6152                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6153                         intel_dp_init(dev, PCH_DP_D);
6154
6155         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
6156                 bool found = false;
6157
6158                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6159                         DRM_DEBUG_KMS("probing SDVOB\n");
6160                         found = intel_sdvo_init(dev, SDVOB);
6161                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
6162                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
6163                                 intel_hdmi_init(dev, SDVOB);
6164                         }
6165
6166                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
6167                                 DRM_DEBUG_KMS("probing DP_B\n");
6168                                 intel_dp_init(dev, DP_B);
6169                         }
6170                 }
6171
6172                 /* Before G4X SDVOC doesn't have its own detect register */
6173
6174                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6175                         DRM_DEBUG_KMS("probing SDVOC\n");
6176                         found = intel_sdvo_init(dev, SDVOC);
6177                 }
6178
6179                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
6180
6181                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
6182                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
6183                                 intel_hdmi_init(dev, SDVOC);
6184                         }
6185                         if (SUPPORTS_INTEGRATED_DP(dev)) {
6186                                 DRM_DEBUG_KMS("probing DP_C\n");
6187                                 intel_dp_init(dev, DP_C);
6188                         }
6189                 }
6190
6191                 if (SUPPORTS_INTEGRATED_DP(dev) &&
6192                     (I915_READ(DP_D) & DP_DETECTED)) {
6193                         DRM_DEBUG_KMS("probing DP_D\n");
6194                         intel_dp_init(dev, DP_D);
6195                 }
6196         } else if (IS_GEN2(dev))
6197                 intel_dvo_init(dev);
6198
6199         if (SUPPORTS_TV(dev))
6200                 intel_tv_init(dev);
6201
6202         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6203                 encoder->base.possible_crtcs = encoder->crtc_mask;
6204                 encoder->base.possible_clones =
6205                         intel_encoder_clones(dev, encoder->clone_mask);
6206         }
6207
6208         intel_panel_setup_backlight(dev);
6209 }
6210
6211 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
6212 {
6213         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
6214
6215         drm_framebuffer_cleanup(fb);
6216         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
6217
6218         kfree(intel_fb);
6219 }
6220
6221 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
6222                                                 struct drm_file *file,
6223                                                 unsigned int *handle)
6224 {
6225         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
6226         struct drm_i915_gem_object *obj = intel_fb->obj;
6227
6228         return drm_gem_handle_create(file, &obj->base, handle);
6229 }
6230
6231 static const struct drm_framebuffer_funcs intel_fb_funcs = {
6232         .destroy = intel_user_framebuffer_destroy,
6233         .create_handle = intel_user_framebuffer_create_handle,
6234 };
6235
6236 int intel_framebuffer_init(struct drm_device *dev,
6237                            struct intel_framebuffer *intel_fb,
6238                            struct drm_mode_fb_cmd *mode_cmd,
6239                            struct drm_i915_gem_object *obj)
6240 {
6241         int ret;
6242
6243         if (obj->tiling_mode == I915_TILING_Y)
6244                 return -EINVAL;
6245
6246         if (mode_cmd->pitch & 63)
6247                 return -EINVAL;
6248
6249         switch (mode_cmd->bpp) {
6250         case 8:
6251         case 16:
6252         case 24:
6253         case 32:
6254                 break;
6255         default:
6256                 return -EINVAL;
6257         }
6258
6259         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
6260         if (ret) {
6261                 DRM_ERROR("framebuffer init failed %d\n", ret);
6262                 return ret;
6263         }
6264
6265         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
6266         intel_fb->obj = obj;
6267         return 0;
6268 }
6269
6270 static struct drm_framebuffer *
6271 intel_user_framebuffer_create(struct drm_device *dev,
6272                               struct drm_file *filp,
6273                               struct drm_mode_fb_cmd *mode_cmd)
6274 {
6275         struct drm_i915_gem_object *obj;
6276         struct intel_framebuffer *intel_fb;
6277         int ret;
6278
6279         obj = to_intel_bo(drm_gem_object_lookup(dev, filp, mode_cmd->handle));
6280         if (!obj)
6281                 return ERR_PTR(-ENOENT);
6282
6283         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6284         if (!intel_fb)
6285                 return ERR_PTR(-ENOMEM);
6286
6287         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6288         if (ret) {
6289                 drm_gem_object_unreference_unlocked(&obj->base);
6290                 kfree(intel_fb);
6291                 return ERR_PTR(ret);
6292         }
6293
6294         return &intel_fb->base;
6295 }
6296
6297 static const struct drm_mode_config_funcs intel_mode_funcs = {
6298         .fb_create = intel_user_framebuffer_create,
6299         .output_poll_changed = intel_fb_output_poll_changed,
6300 };
6301
6302 static struct drm_i915_gem_object *
6303 intel_alloc_context_page(struct drm_device *dev)
6304 {
6305         struct drm_i915_gem_object *ctx;
6306         int ret;
6307
6308         ctx = i915_gem_alloc_object(dev, 4096);
6309         if (!ctx) {
6310                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
6311                 return NULL;
6312         }
6313
6314         mutex_lock(&dev->struct_mutex);
6315         ret = i915_gem_object_pin(ctx, 4096, true);
6316         if (ret) {
6317                 DRM_ERROR("failed to pin power context: %d\n", ret);
6318                 goto err_unref;
6319         }
6320
6321         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
6322         if (ret) {
6323                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
6324                 goto err_unpin;
6325         }
6326         mutex_unlock(&dev->struct_mutex);
6327
6328         return ctx;
6329
6330 err_unpin:
6331         i915_gem_object_unpin(ctx);
6332 err_unref:
6333         drm_gem_object_unreference(&ctx->base);
6334         mutex_unlock(&dev->struct_mutex);
6335         return NULL;
6336 }
6337
6338 bool ironlake_set_drps(struct drm_device *dev, u8 val)
6339 {
6340         struct drm_i915_private *dev_priv = dev->dev_private;
6341         u16 rgvswctl;
6342
6343         rgvswctl = I915_READ16(MEMSWCTL);
6344         if (rgvswctl & MEMCTL_CMD_STS) {
6345                 DRM_DEBUG("gpu busy, RCS change rejected\n");
6346                 return false; /* still busy with another command */
6347         }
6348
6349         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
6350                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
6351         I915_WRITE16(MEMSWCTL, rgvswctl);
6352         POSTING_READ16(MEMSWCTL);
6353
6354         rgvswctl |= MEMCTL_CMD_STS;
6355         I915_WRITE16(MEMSWCTL, rgvswctl);
6356
6357         return true;
6358 }
6359
6360 void ironlake_enable_drps(struct drm_device *dev)
6361 {
6362         struct drm_i915_private *dev_priv = dev->dev_private;
6363         u32 rgvmodectl = I915_READ(MEMMODECTL);
6364         u8 fmax, fmin, fstart, vstart;
6365
6366         /* Enable temp reporting */
6367         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
6368         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
6369
6370         /* 100ms RC evaluation intervals */
6371         I915_WRITE(RCUPEI, 100000);
6372         I915_WRITE(RCDNEI, 100000);
6373
6374         /* Set max/min thresholds to 90ms and 80ms respectively */
6375         I915_WRITE(RCBMAXAVG, 90000);
6376         I915_WRITE(RCBMINAVG, 80000);
6377
6378         I915_WRITE(MEMIHYST, 1);
6379
6380         /* Set up min, max, and cur for interrupt handling */
6381         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
6382         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
6383         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
6384                 MEMMODE_FSTART_SHIFT;
6385
6386         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
6387                 PXVFREQ_PX_SHIFT;
6388
6389         dev_priv->fmax = fmax; /* IPS callback will increase this */
6390         dev_priv->fstart = fstart;
6391
6392         dev_priv->max_delay = fstart;
6393         dev_priv->min_delay = fmin;
6394         dev_priv->cur_delay = fstart;
6395
6396         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
6397                          fmax, fmin, fstart);
6398
6399         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
6400
6401         /*
6402          * Interrupts will be enabled in ironlake_irq_postinstall
6403          */
6404
6405         I915_WRITE(VIDSTART, vstart);
6406         POSTING_READ(VIDSTART);
6407
6408         rgvmodectl |= MEMMODE_SWMODE_EN;
6409         I915_WRITE(MEMMODECTL, rgvmodectl);
6410
6411         if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
6412                 DRM_ERROR("stuck trying to change perf mode\n");
6413         msleep(1);
6414
6415         ironlake_set_drps(dev, fstart);
6416
6417         dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
6418                 I915_READ(0x112e0);
6419         dev_priv->last_time1 = jiffies_to_msecs(jiffies);
6420         dev_priv->last_count2 = I915_READ(0x112f4);
6421         getrawmonotonic(&dev_priv->last_time2);
6422 }
6423
6424 void ironlake_disable_drps(struct drm_device *dev)
6425 {
6426         struct drm_i915_private *dev_priv = dev->dev_private;
6427         u16 rgvswctl = I915_READ16(MEMSWCTL);
6428
6429         /* Ack interrupts, disable EFC interrupt */
6430         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
6431         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
6432         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
6433         I915_WRITE(DEIIR, DE_PCU_EVENT);
6434         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
6435
6436         /* Go back to the starting frequency */
6437         ironlake_set_drps(dev, dev_priv->fstart);
6438         msleep(1);
6439         rgvswctl |= MEMCTL_CMD_STS;
6440         I915_WRITE(MEMSWCTL, rgvswctl);
6441         msleep(1);
6442
6443 }
6444
6445 void gen6_set_rps(struct drm_device *dev, u8 val)
6446 {
6447         struct drm_i915_private *dev_priv = dev->dev_private;
6448         u32 swreq;
6449
6450         swreq = (val & 0x3ff) << 25;
6451         I915_WRITE(GEN6_RPNSWREQ, swreq);
6452 }
6453
6454 void gen6_disable_rps(struct drm_device *dev)
6455 {
6456         struct drm_i915_private *dev_priv = dev->dev_private;
6457
6458         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
6459         I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
6460         I915_WRITE(GEN6_PMIER, 0);
6461         I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
6462 }
6463
6464 static unsigned long intel_pxfreq(u32 vidfreq)
6465 {
6466         unsigned long freq;
6467         int div = (vidfreq & 0x3f0000) >> 16;
6468         int post = (vidfreq & 0x3000) >> 12;
6469         int pre = (vidfreq & 0x7);
6470
6471         if (!pre)
6472                 return 0;
6473
6474         freq = ((div * 133333) / ((1<<post) * pre));
6475
6476         return freq;
6477 }
6478
6479 void intel_init_emon(struct drm_device *dev)
6480 {
6481         struct drm_i915_private *dev_priv = dev->dev_private;
6482         u32 lcfuse;
6483         u8 pxw[16];
6484         int i;
6485
6486         /* Disable to program */
6487         I915_WRITE(ECR, 0);
6488         POSTING_READ(ECR);
6489
6490         /* Program energy weights for various events */
6491         I915_WRITE(SDEW, 0x15040d00);
6492         I915_WRITE(CSIEW0, 0x007f0000);
6493         I915_WRITE(CSIEW1, 0x1e220004);
6494         I915_WRITE(CSIEW2, 0x04000004);
6495
6496         for (i = 0; i < 5; i++)
6497                 I915_WRITE(PEW + (i * 4), 0);
6498         for (i = 0; i < 3; i++)
6499                 I915_WRITE(DEW + (i * 4), 0);
6500
6501         /* Program P-state weights to account for frequency power adjustment */
6502         for (i = 0; i < 16; i++) {
6503                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
6504                 unsigned long freq = intel_pxfreq(pxvidfreq);
6505                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6506                         PXVFREQ_PX_SHIFT;
6507                 unsigned long val;
6508
6509                 val = vid * vid;
6510                 val *= (freq / 1000);
6511                 val *= 255;
6512                 val /= (127*127*900);
6513                 if (val > 0xff)
6514                         DRM_ERROR("bad pxval: %ld\n", val);
6515                 pxw[i] = val;
6516         }
6517         /* Render standby states get 0 weight */
6518         pxw[14] = 0;
6519         pxw[15] = 0;
6520
6521         for (i = 0; i < 4; i++) {
6522                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6523                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
6524                 I915_WRITE(PXW + (i * 4), val);
6525         }
6526
6527         /* Adjust magic regs to magic values (more experimental results) */
6528         I915_WRITE(OGW0, 0);
6529         I915_WRITE(OGW1, 0);
6530         I915_WRITE(EG0, 0x00007f00);
6531         I915_WRITE(EG1, 0x0000000e);
6532         I915_WRITE(EG2, 0x000e0000);
6533         I915_WRITE(EG3, 0x68000300);
6534         I915_WRITE(EG4, 0x42000000);
6535         I915_WRITE(EG5, 0x00140031);
6536         I915_WRITE(EG6, 0);
6537         I915_WRITE(EG7, 0);
6538
6539         for (i = 0; i < 8; i++)
6540                 I915_WRITE(PXWL + (i * 4), 0);
6541
6542         /* Enable PMON + select events */
6543         I915_WRITE(ECR, 0x80000019);
6544
6545         lcfuse = I915_READ(LCFUSE02);
6546
6547         dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
6548 }
6549
6550 void gen6_enable_rps(struct drm_i915_private *dev_priv)
6551 {
6552         u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
6553         u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
6554         u32 pcu_mbox;
6555         int cur_freq, min_freq, max_freq;
6556         int i;
6557
6558         /* Here begins a magic sequence of register writes to enable
6559          * auto-downclocking.
6560          *
6561          * Perhaps there might be some value in exposing these to
6562          * userspace...
6563          */
6564         I915_WRITE(GEN6_RC_STATE, 0);
6565         __gen6_force_wake_get(dev_priv);
6566
6567         /* disable the counters and set deterministic thresholds */
6568         I915_WRITE(GEN6_RC_CONTROL, 0);
6569
6570         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
6571         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
6572         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
6573         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
6574         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
6575
6576         for (i = 0; i < I915_NUM_RINGS; i++)
6577                 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
6578
6579         I915_WRITE(GEN6_RC_SLEEP, 0);
6580         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
6581         I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
6582         I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
6583         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
6584
6585         I915_WRITE(GEN6_RC_CONTROL,
6586                    GEN6_RC_CTL_RC6p_ENABLE |
6587                    GEN6_RC_CTL_RC6_ENABLE |
6588                    GEN6_RC_CTL_EI_MODE(1) |
6589                    GEN6_RC_CTL_HW_ENABLE);
6590
6591         I915_WRITE(GEN6_RPNSWREQ,
6592                    GEN6_FREQUENCY(10) |
6593                    GEN6_OFFSET(0) |
6594                    GEN6_AGGRESSIVE_TURBO);
6595         I915_WRITE(GEN6_RC_VIDEO_FREQ,
6596                    GEN6_FREQUENCY(12));
6597
6598         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
6599         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
6600                    18 << 24 |
6601                    6 << 16);
6602         I915_WRITE(GEN6_RP_UP_THRESHOLD, 90000);
6603         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 100000);
6604         I915_WRITE(GEN6_RP_UP_EI, 100000);
6605         I915_WRITE(GEN6_RP_DOWN_EI, 300000);
6606         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6607         I915_WRITE(GEN6_RP_CONTROL,
6608                    GEN6_RP_MEDIA_TURBO |
6609                    GEN6_RP_USE_NORMAL_FREQ |
6610                    GEN6_RP_MEDIA_IS_GFX |
6611                    GEN6_RP_ENABLE |
6612                    GEN6_RP_UP_BUSY_MAX |
6613                    GEN6_RP_DOWN_BUSY_MIN);
6614
6615         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6616                      500))
6617                 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
6618
6619         I915_WRITE(GEN6_PCODE_DATA, 0);
6620         I915_WRITE(GEN6_PCODE_MAILBOX,
6621                    GEN6_PCODE_READY |
6622                    GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
6623         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6624                      500))
6625                 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
6626
6627         min_freq = (rp_state_cap & 0xff0000) >> 16;
6628         max_freq = rp_state_cap & 0xff;
6629         cur_freq = (gt_perf_status & 0xff00) >> 8;
6630
6631         /* Check for overclock support */
6632         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6633                      500))
6634                 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
6635         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
6636         pcu_mbox = I915_READ(GEN6_PCODE_DATA);
6637         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6638                      500))
6639                 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
6640         if (pcu_mbox & (1<<31)) { /* OC supported */
6641                 max_freq = pcu_mbox & 0xff;
6642                 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 100);
6643         }
6644
6645         /* In units of 100MHz */
6646         dev_priv->max_delay = max_freq;
6647         dev_priv->min_delay = min_freq;
6648         dev_priv->cur_delay = cur_freq;
6649
6650         /* requires MSI enabled */
6651         I915_WRITE(GEN6_PMIER,
6652                    GEN6_PM_MBOX_EVENT |
6653                    GEN6_PM_THERMAL_EVENT |
6654                    GEN6_PM_RP_DOWN_TIMEOUT |
6655                    GEN6_PM_RP_UP_THRESHOLD |
6656                    GEN6_PM_RP_DOWN_THRESHOLD |
6657                    GEN6_PM_RP_UP_EI_EXPIRED |
6658                    GEN6_PM_RP_DOWN_EI_EXPIRED);
6659         I915_WRITE(GEN6_PMIMR, 0);
6660         /* enable all PM interrupts */
6661         I915_WRITE(GEN6_PMINTRMSK, 0);
6662
6663         __gen6_force_wake_put(dev_priv);
6664 }
6665
6666 void intel_enable_clock_gating(struct drm_device *dev)
6667 {
6668         struct drm_i915_private *dev_priv = dev->dev_private;
6669
6670         /*
6671          * Disable clock gating reported to work incorrectly according to the
6672          * specs, but enable as much else as we can.
6673          */
6674         if (HAS_PCH_SPLIT(dev)) {
6675                 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
6676
6677                 if (IS_GEN5(dev)) {
6678                         /* Required for FBC */
6679                         dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE;
6680                         /* Required for CxSR */
6681                         dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
6682
6683                         I915_WRITE(PCH_3DCGDIS0,
6684                                    MARIUNIT_CLOCK_GATE_DISABLE |
6685                                    SVSMUNIT_CLOCK_GATE_DISABLE);
6686                         I915_WRITE(PCH_3DCGDIS1,
6687                                    VFMUNIT_CLOCK_GATE_DISABLE);
6688                 }
6689
6690                 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
6691
6692                 /*
6693                  * On Ibex Peak and Cougar Point, we need to disable clock
6694                  * gating for the panel power sequencer or it will fail to
6695                  * start up when no ports are active.
6696                  */
6697                 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6698
6699                 /*
6700                  * According to the spec the following bits should be set in
6701                  * order to enable memory self-refresh
6702                  * The bit 22/21 of 0x42004
6703                  * The bit 5 of 0x42020
6704                  * The bit 15 of 0x45000
6705                  */
6706                 if (IS_GEN5(dev)) {
6707                         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6708                                         (I915_READ(ILK_DISPLAY_CHICKEN2) |
6709                                         ILK_DPARB_GATE | ILK_VSDPFD_FULL));
6710                         I915_WRITE(ILK_DSPCLK_GATE,
6711                                         (I915_READ(ILK_DSPCLK_GATE) |
6712                                                 ILK_DPARB_CLK_GATE));
6713                         I915_WRITE(DISP_ARB_CTL,
6714                                         (I915_READ(DISP_ARB_CTL) |
6715                                                 DISP_FBC_WM_DIS));
6716                         I915_WRITE(WM3_LP_ILK, 0);
6717                         I915_WRITE(WM2_LP_ILK, 0);
6718                         I915_WRITE(WM1_LP_ILK, 0);
6719                 }
6720                 /*
6721                  * Based on the document from hardware guys the following bits
6722                  * should be set unconditionally in order to enable FBC.
6723                  * The bit 22 of 0x42000
6724                  * The bit 22 of 0x42004
6725                  * The bit 7,8,9 of 0x42020.
6726                  */
6727                 if (IS_IRONLAKE_M(dev)) {
6728                         I915_WRITE(ILK_DISPLAY_CHICKEN1,
6729                                    I915_READ(ILK_DISPLAY_CHICKEN1) |
6730                                    ILK_FBCQ_DIS);
6731                         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6732                                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6733                                    ILK_DPARB_GATE);
6734                         I915_WRITE(ILK_DSPCLK_GATE,
6735                                    I915_READ(ILK_DSPCLK_GATE) |
6736                                    ILK_DPFC_DIS1 |
6737                                    ILK_DPFC_DIS2 |
6738                                    ILK_CLK_FBC);
6739                 }
6740
6741                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6742                            I915_READ(ILK_DISPLAY_CHICKEN2) |
6743                            ILK_ELPIN_409_SELECT);
6744
6745                 if (IS_GEN5(dev)) {
6746                         I915_WRITE(_3D_CHICKEN2,
6747                                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6748                                    _3D_CHICKEN2_WM_READ_PIPELINED);
6749                 }
6750
6751                 if (IS_GEN6(dev)) {
6752                         I915_WRITE(WM3_LP_ILK, 0);
6753                         I915_WRITE(WM2_LP_ILK, 0);
6754                         I915_WRITE(WM1_LP_ILK, 0);
6755
6756                         /*
6757                          * According to the spec the following bits should be
6758                          * set in order to enable memory self-refresh and fbc:
6759                          * The bit21 and bit22 of 0x42000
6760                          * The bit21 and bit22 of 0x42004
6761                          * The bit5 and bit7 of 0x42020
6762                          * The bit14 of 0x70180
6763                          * The bit14 of 0x71180
6764                          */
6765                         I915_WRITE(ILK_DISPLAY_CHICKEN1,
6766                                    I915_READ(ILK_DISPLAY_CHICKEN1) |
6767                                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6768                         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6769                                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6770                                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
6771                         I915_WRITE(ILK_DSPCLK_GATE,
6772                                    I915_READ(ILK_DSPCLK_GATE) |
6773                                    ILK_DPARB_CLK_GATE  |
6774                                    ILK_DPFD_CLK_GATE);
6775
6776                         I915_WRITE(DSPACNTR,
6777                                    I915_READ(DSPACNTR) |
6778                                    DISPPLANE_TRICKLE_FEED_DISABLE);
6779                         I915_WRITE(DSPBCNTR,
6780                                    I915_READ(DSPBCNTR) |
6781                                    DISPPLANE_TRICKLE_FEED_DISABLE);
6782                 }
6783         } else if (IS_G4X(dev)) {
6784                 uint32_t dspclk_gate;
6785                 I915_WRITE(RENCLK_GATE_D1, 0);
6786                 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
6787                        GS_UNIT_CLOCK_GATE_DISABLE |
6788                        CL_UNIT_CLOCK_GATE_DISABLE);
6789                 I915_WRITE(RAMCLK_GATE_D, 0);
6790                 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
6791                         OVRUNIT_CLOCK_GATE_DISABLE |
6792                         OVCUNIT_CLOCK_GATE_DISABLE;
6793                 if (IS_GM45(dev))
6794                         dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
6795                 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
6796         } else if (IS_CRESTLINE(dev)) {
6797                 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
6798                 I915_WRITE(RENCLK_GATE_D2, 0);
6799                 I915_WRITE(DSPCLK_GATE_D, 0);
6800                 I915_WRITE(RAMCLK_GATE_D, 0);
6801                 I915_WRITE16(DEUC, 0);
6802         } else if (IS_BROADWATER(dev)) {
6803                 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
6804                        I965_RCC_CLOCK_GATE_DISABLE |
6805                        I965_RCPB_CLOCK_GATE_DISABLE |
6806                        I965_ISC_CLOCK_GATE_DISABLE |
6807                        I965_FBC_CLOCK_GATE_DISABLE);
6808                 I915_WRITE(RENCLK_GATE_D2, 0);
6809         } else if (IS_GEN3(dev)) {
6810                 u32 dstate = I915_READ(D_STATE);
6811
6812                 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
6813                         DSTATE_DOT_CLOCK_GATING;
6814                 I915_WRITE(D_STATE, dstate);
6815         } else if (IS_I85X(dev) || IS_I865G(dev)) {
6816                 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
6817         } else if (IS_I830(dev)) {
6818                 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
6819         }
6820 }
6821
6822 void intel_disable_clock_gating(struct drm_device *dev)
6823 {
6824         struct drm_i915_private *dev_priv = dev->dev_private;
6825
6826         if (dev_priv->renderctx) {
6827                 struct drm_i915_gem_object *obj = dev_priv->renderctx;
6828
6829                 I915_WRITE(CCID, 0);
6830                 POSTING_READ(CCID);
6831
6832                 i915_gem_object_unpin(obj);
6833                 drm_gem_object_unreference(&obj->base);
6834                 dev_priv->renderctx = NULL;
6835         }
6836
6837         if (dev_priv->pwrctx) {
6838                 struct drm_i915_gem_object *obj = dev_priv->pwrctx;
6839
6840                 I915_WRITE(PWRCTXA, 0);
6841                 POSTING_READ(PWRCTXA);
6842
6843                 i915_gem_object_unpin(obj);
6844                 drm_gem_object_unreference(&obj->base);
6845                 dev_priv->pwrctx = NULL;
6846         }
6847 }
6848
6849 static void ironlake_disable_rc6(struct drm_device *dev)
6850 {
6851         struct drm_i915_private *dev_priv = dev->dev_private;
6852
6853         /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
6854         I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
6855         wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
6856                  10);
6857         POSTING_READ(CCID);
6858         I915_WRITE(PWRCTXA, 0);
6859         POSTING_READ(PWRCTXA);
6860         I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
6861         POSTING_READ(RSTDBYCTL);
6862         i915_gem_object_unpin(dev_priv->renderctx);
6863         drm_gem_object_unreference(&dev_priv->renderctx->base);
6864         dev_priv->renderctx = NULL;
6865         i915_gem_object_unpin(dev_priv->pwrctx);
6866         drm_gem_object_unreference(&dev_priv->pwrctx->base);
6867         dev_priv->pwrctx = NULL;
6868 }
6869
6870 void ironlake_enable_rc6(struct drm_device *dev)
6871 {
6872         struct drm_i915_private *dev_priv = dev->dev_private;
6873         int ret;
6874
6875         /*
6876          * GPU can automatically power down the render unit if given a page
6877          * to save state.
6878          */
6879         ret = BEGIN_LP_RING(6);
6880         if (ret) {
6881                 ironlake_disable_rc6(dev);
6882                 return;
6883         }
6884         OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
6885         OUT_RING(MI_SET_CONTEXT);
6886         OUT_RING(dev_priv->renderctx->gtt_offset |
6887                  MI_MM_SPACE_GTT |
6888                  MI_SAVE_EXT_STATE_EN |
6889                  MI_RESTORE_EXT_STATE_EN |
6890                  MI_RESTORE_INHIBIT);
6891         OUT_RING(MI_SUSPEND_FLUSH);
6892         OUT_RING(MI_NOOP);
6893         OUT_RING(MI_FLUSH);
6894         ADVANCE_LP_RING();
6895
6896         I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
6897         I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
6898 }
6899
6900 /* Set up chip specific display functions */
6901 static void intel_init_display(struct drm_device *dev)
6902 {
6903         struct drm_i915_private *dev_priv = dev->dev_private;
6904
6905         /* We always want a DPMS function */
6906         if (HAS_PCH_SPLIT(dev))
6907                 dev_priv->display.dpms = ironlake_crtc_dpms;
6908         else
6909                 dev_priv->display.dpms = i9xx_crtc_dpms;
6910
6911         if (I915_HAS_FBC(dev)) {
6912                 if (HAS_PCH_SPLIT(dev)) {
6913                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
6914                         dev_priv->display.enable_fbc = ironlake_enable_fbc;
6915                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
6916                 } else if (IS_GM45(dev)) {
6917                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
6918                         dev_priv->display.enable_fbc = g4x_enable_fbc;
6919                         dev_priv->display.disable_fbc = g4x_disable_fbc;
6920                 } else if (IS_CRESTLINE(dev)) {
6921                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
6922                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
6923                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
6924                 }
6925                 /* 855GM needs testing */
6926         }
6927
6928         /* Returns the core display clock speed */
6929         if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
6930                 dev_priv->display.get_display_clock_speed =
6931                         i945_get_display_clock_speed;
6932         else if (IS_I915G(dev))
6933                 dev_priv->display.get_display_clock_speed =
6934                         i915_get_display_clock_speed;
6935         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
6936                 dev_priv->display.get_display_clock_speed =
6937                         i9xx_misc_get_display_clock_speed;
6938         else if (IS_I915GM(dev))
6939                 dev_priv->display.get_display_clock_speed =
6940                         i915gm_get_display_clock_speed;
6941         else if (IS_I865G(dev))
6942                 dev_priv->display.get_display_clock_speed =
6943                         i865_get_display_clock_speed;
6944         else if (IS_I85X(dev))
6945                 dev_priv->display.get_display_clock_speed =
6946                         i855_get_display_clock_speed;
6947         else /* 852, 830 */
6948                 dev_priv->display.get_display_clock_speed =
6949                         i830_get_display_clock_speed;
6950
6951         /* For FIFO watermark updates */
6952         if (HAS_PCH_SPLIT(dev)) {
6953                 if (IS_GEN5(dev)) {
6954                         if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
6955                                 dev_priv->display.update_wm = ironlake_update_wm;
6956                         else {
6957                                 DRM_DEBUG_KMS("Failed to get proper latency. "
6958                                               "Disable CxSR\n");
6959                                 dev_priv->display.update_wm = NULL;
6960                         }
6961                 } else if (IS_GEN6(dev)) {
6962                         if (SNB_READ_WM0_LATENCY()) {
6963                                 dev_priv->display.update_wm = sandybridge_update_wm;
6964                         } else {
6965                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
6966                                               "Disable CxSR\n");
6967                                 dev_priv->display.update_wm = NULL;
6968                         }
6969                 } else
6970                         dev_priv->display.update_wm = NULL;
6971         } else if (IS_PINEVIEW(dev)) {
6972                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
6973                                             dev_priv->is_ddr3,
6974                                             dev_priv->fsb_freq,
6975                                             dev_priv->mem_freq)) {
6976                         DRM_INFO("failed to find known CxSR latency "
6977                                  "(found ddr%s fsb freq %d, mem freq %d), "
6978                                  "disabling CxSR\n",
6979                                  (dev_priv->is_ddr3 == 1) ? "3": "2",
6980                                  dev_priv->fsb_freq, dev_priv->mem_freq);
6981                         /* Disable CxSR and never update its watermark again */
6982                         pineview_disable_cxsr(dev);
6983                         dev_priv->display.update_wm = NULL;
6984                 } else
6985                         dev_priv->display.update_wm = pineview_update_wm;
6986         } else if (IS_G4X(dev))
6987                 dev_priv->display.update_wm = g4x_update_wm;
6988         else if (IS_GEN4(dev))
6989                 dev_priv->display.update_wm = i965_update_wm;
6990         else if (IS_GEN3(dev)) {
6991                 dev_priv->display.update_wm = i9xx_update_wm;
6992                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6993         } else if (IS_I85X(dev)) {
6994                 dev_priv->display.update_wm = i9xx_update_wm;
6995                 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
6996         } else {
6997                 dev_priv->display.update_wm = i830_update_wm;
6998                 if (IS_845G(dev))
6999                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
7000                 else
7001                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
7002         }
7003 }
7004
7005 /*
7006  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
7007  * resume, or other times.  This quirk makes sure that's the case for
7008  * affected systems.
7009  */
7010 static void quirk_pipea_force (struct drm_device *dev)
7011 {
7012         struct drm_i915_private *dev_priv = dev->dev_private;
7013
7014         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
7015         DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
7016 }
7017
7018 struct intel_quirk {
7019         int device;
7020         int subsystem_vendor;
7021         int subsystem_device;
7022         void (*hook)(struct drm_device *dev);
7023 };
7024
7025 struct intel_quirk intel_quirks[] = {
7026         /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
7027         { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
7028         /* HP Mini needs pipe A force quirk (LP: #322104) */
7029         { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
7030
7031         /* Thinkpad R31 needs pipe A force quirk */
7032         { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
7033         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
7034         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
7035
7036         /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
7037         { 0x3577,  0x1014, 0x0513, quirk_pipea_force },
7038         /* ThinkPad X40 needs pipe A force quirk */
7039
7040         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
7041         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
7042
7043         /* 855 & before need to leave pipe A & dpll A up */
7044         { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7045         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7046 };
7047
7048 static void intel_init_quirks(struct drm_device *dev)
7049 {
7050         struct pci_dev *d = dev->pdev;
7051         int i;
7052
7053         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
7054                 struct intel_quirk *q = &intel_quirks[i];
7055
7056                 if (d->device == q->device &&
7057                     (d->subsystem_vendor == q->subsystem_vendor ||
7058                      q->subsystem_vendor == PCI_ANY_ID) &&
7059                     (d->subsystem_device == q->subsystem_device ||
7060                      q->subsystem_device == PCI_ANY_ID))
7061                         q->hook(dev);
7062         }
7063 }
7064
7065 /* Disable the VGA plane that we never use */
7066 static void i915_disable_vga(struct drm_device *dev)
7067 {
7068         struct drm_i915_private *dev_priv = dev->dev_private;
7069         u8 sr1;
7070         u32 vga_reg;
7071
7072         if (HAS_PCH_SPLIT(dev))
7073                 vga_reg = CPU_VGACNTRL;
7074         else
7075                 vga_reg = VGACNTRL;
7076
7077         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
7078         outb(1, VGA_SR_INDEX);
7079         sr1 = inb(VGA_SR_DATA);
7080         outb(sr1 | 1<<5, VGA_SR_DATA);
7081         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
7082         udelay(300);
7083
7084         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
7085         POSTING_READ(vga_reg);
7086 }
7087
7088 void intel_modeset_init(struct drm_device *dev)
7089 {
7090         struct drm_i915_private *dev_priv = dev->dev_private;
7091         int i;
7092
7093         drm_mode_config_init(dev);
7094
7095         dev->mode_config.min_width = 0;
7096         dev->mode_config.min_height = 0;
7097
7098         dev->mode_config.funcs = (void *)&intel_mode_funcs;
7099
7100         intel_init_quirks(dev);
7101
7102         intel_init_display(dev);
7103
7104         if (IS_GEN2(dev)) {
7105                 dev->mode_config.max_width = 2048;
7106                 dev->mode_config.max_height = 2048;
7107         } else if (IS_GEN3(dev)) {
7108                 dev->mode_config.max_width = 4096;
7109                 dev->mode_config.max_height = 4096;
7110         } else {
7111                 dev->mode_config.max_width = 8192;
7112                 dev->mode_config.max_height = 8192;
7113         }
7114         dev->mode_config.fb_base = dev->agp->base;
7115
7116         if (IS_MOBILE(dev) || !IS_GEN2(dev))
7117                 dev_priv->num_pipe = 2;
7118         else
7119                 dev_priv->num_pipe = 1;
7120         DRM_DEBUG_KMS("%d display pipe%s available.\n",
7121                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
7122
7123         for (i = 0; i < dev_priv->num_pipe; i++) {
7124                 intel_crtc_init(dev, i);
7125         }
7126
7127         intel_setup_outputs(dev);
7128
7129         intel_enable_clock_gating(dev);
7130
7131         /* Just disable it once at startup */
7132         i915_disable_vga(dev);
7133
7134         if (IS_IRONLAKE_M(dev)) {
7135                 ironlake_enable_drps(dev);
7136                 intel_init_emon(dev);
7137         }
7138
7139         if (IS_GEN6(dev))
7140                 gen6_enable_rps(dev_priv);
7141
7142         if (IS_IRONLAKE_M(dev)) {
7143                 dev_priv->renderctx = intel_alloc_context_page(dev);
7144                 if (!dev_priv->renderctx)
7145                         goto skip_rc6;
7146                 dev_priv->pwrctx = intel_alloc_context_page(dev);
7147                 if (!dev_priv->pwrctx) {
7148                         i915_gem_object_unpin(dev_priv->renderctx);
7149                         drm_gem_object_unreference(&dev_priv->renderctx->base);
7150                         dev_priv->renderctx = NULL;
7151                         goto skip_rc6;
7152                 }
7153                 ironlake_enable_rc6(dev);
7154         }
7155
7156 skip_rc6:
7157         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
7158         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
7159                     (unsigned long)dev);
7160
7161         intel_setup_overlay(dev);
7162 }
7163
7164 void intel_modeset_cleanup(struct drm_device *dev)
7165 {
7166         struct drm_i915_private *dev_priv = dev->dev_private;
7167         struct drm_crtc *crtc;
7168         struct intel_crtc *intel_crtc;
7169
7170         drm_kms_helper_poll_fini(dev);
7171         mutex_lock(&dev->struct_mutex);
7172
7173         intel_unregister_dsm_handler();
7174
7175
7176         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7177                 /* Skip inactive CRTCs */
7178                 if (!crtc->fb)
7179                         continue;
7180
7181                 intel_crtc = to_intel_crtc(crtc);
7182                 intel_increase_pllclock(crtc);
7183         }
7184
7185         if (dev_priv->display.disable_fbc)
7186                 dev_priv->display.disable_fbc(dev);
7187
7188         if (IS_IRONLAKE_M(dev))
7189                 ironlake_disable_drps(dev);
7190         if (IS_GEN6(dev))
7191                 gen6_disable_rps(dev);
7192
7193         if (IS_IRONLAKE_M(dev))
7194                 ironlake_disable_rc6(dev);
7195
7196         mutex_unlock(&dev->struct_mutex);
7197
7198         /* Disable the irq before mode object teardown, for the irq might
7199          * enqueue unpin/hotplug work. */
7200         drm_irq_uninstall(dev);
7201         cancel_work_sync(&dev_priv->hotplug_work);
7202
7203         /* Shut off idle work before the crtcs get freed. */
7204         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7205                 intel_crtc = to_intel_crtc(crtc);
7206                 del_timer_sync(&intel_crtc->idle_timer);
7207         }
7208         del_timer_sync(&dev_priv->idle_timer);
7209         cancel_work_sync(&dev_priv->idle_work);
7210
7211         drm_mode_config_cleanup(dev);
7212 }
7213
7214 /*
7215  * Return which encoder is currently attached for connector.
7216  */
7217 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
7218 {
7219         return &intel_attached_encoder(connector)->base;
7220 }
7221
7222 void intel_connector_attach_encoder(struct intel_connector *connector,
7223                                     struct intel_encoder *encoder)
7224 {
7225         connector->encoder = encoder;
7226         drm_mode_connector_attach_encoder(&connector->base,
7227                                           &encoder->base);
7228 }
7229
7230 /*
7231  * set vga decode state - true == enable VGA decode
7232  */
7233 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
7234 {
7235         struct drm_i915_private *dev_priv = dev->dev_private;
7236         u16 gmch_ctrl;
7237
7238         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
7239         if (state)
7240                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
7241         else
7242                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
7243         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
7244         return 0;
7245 }
7246
7247 #ifdef CONFIG_DEBUG_FS
7248 #include <linux/seq_file.h>
7249
7250 struct intel_display_error_state {
7251         struct intel_cursor_error_state {
7252                 u32 control;
7253                 u32 position;
7254                 u32 base;
7255                 u32 size;
7256         } cursor[2];
7257
7258         struct intel_pipe_error_state {
7259                 u32 conf;
7260                 u32 source;
7261
7262                 u32 htotal;
7263                 u32 hblank;
7264                 u32 hsync;
7265                 u32 vtotal;
7266                 u32 vblank;
7267                 u32 vsync;
7268         } pipe[2];
7269
7270         struct intel_plane_error_state {
7271                 u32 control;
7272                 u32 stride;
7273                 u32 size;
7274                 u32 pos;
7275                 u32 addr;
7276                 u32 surface;
7277                 u32 tile_offset;
7278         } plane[2];
7279 };
7280
7281 struct intel_display_error_state *
7282 intel_display_capture_error_state(struct drm_device *dev)
7283 {
7284         drm_i915_private_t *dev_priv = dev->dev_private;
7285         struct intel_display_error_state *error;
7286         int i;
7287
7288         error = kmalloc(sizeof(*error), GFP_ATOMIC);
7289         if (error == NULL)
7290                 return NULL;
7291
7292         for (i = 0; i < 2; i++) {
7293                 error->cursor[i].control = I915_READ(CURCNTR(i));
7294                 error->cursor[i].position = I915_READ(CURPOS(i));
7295                 error->cursor[i].base = I915_READ(CURBASE(i));
7296
7297                 error->plane[i].control = I915_READ(DSPCNTR(i));
7298                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
7299                 error->plane[i].size = I915_READ(DSPSIZE(i));
7300                 error->plane[i].pos= I915_READ(DSPPOS(i));
7301                 error->plane[i].addr = I915_READ(DSPADDR(i));
7302                 if (INTEL_INFO(dev)->gen >= 4) {
7303                         error->plane[i].surface = I915_READ(DSPSURF(i));
7304                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
7305                 }
7306
7307                 error->pipe[i].conf = I915_READ(PIPECONF(i));
7308                 error->pipe[i].source = I915_READ(PIPESRC(i));
7309                 error->pipe[i].htotal = I915_READ(HTOTAL(i));
7310                 error->pipe[i].hblank = I915_READ(HBLANK(i));
7311                 error->pipe[i].hsync = I915_READ(HSYNC(i));
7312                 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
7313                 error->pipe[i].vblank = I915_READ(VBLANK(i));
7314                 error->pipe[i].vsync = I915_READ(VSYNC(i));
7315         }
7316
7317         return error;
7318 }
7319
7320 void
7321 intel_display_print_error_state(struct seq_file *m,
7322                                 struct drm_device *dev,
7323                                 struct intel_display_error_state *error)
7324 {
7325         int i;
7326
7327         for (i = 0; i < 2; i++) {
7328                 seq_printf(m, "Pipe [%d]:\n", i);
7329                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
7330                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
7331                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
7332                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
7333                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
7334                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
7335                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
7336                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
7337
7338                 seq_printf(m, "Plane [%d]:\n", i);
7339                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
7340                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
7341                 seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
7342                 seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
7343                 seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
7344                 if (INTEL_INFO(dev)->gen >= 4) {
7345                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
7346                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
7347                 }
7348
7349                 seq_printf(m, "Cursor [%d]:\n", i);
7350                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
7351                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
7352                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
7353         }
7354 }
7355 #endif