drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include "intel_frontbuffer.h"
  38 #include <drm/i915_drm.h>
  39 #include "i915_drv.h"
  40 #include "intel_dsi.h"
  41 #include "i915_trace.h"
  42 #include <drm/drm_atomic.h>
  43 #include <drm/drm_atomic_helper.h>
  44 #include <drm/drm_dp_helper.h>
  45 #include <drm/drm_crtc_helper.h>
  46 #include <drm/drm_plane_helper.h>
  47 #include <drm/drm_rect.h>
  48 #include <linux/dma_remapping.h>
  49 #include <linux/reservation.h>
  50
  51 static bool is_mmio_work(struct intel_flip_work *work)
  52 {
  53         return work->mmio_work.func;
  54 }
  55
  56 /* Primary plane formats for gen <= 3 */
  57 static const uint32_t i8xx_primary_formats[] = {
  58         DRM_FORMAT_C8,
  59         DRM_FORMAT_RGB565,
  60         DRM_FORMAT_XRGB1555,
  61         DRM_FORMAT_XRGB8888,
  62 };
  63
  64 /* Primary plane formats for gen >= 4 */
  65 static const uint32_t i965_primary_formats[] = {
  66         DRM_FORMAT_C8,
  67         DRM_FORMAT_RGB565,
  68         DRM_FORMAT_XRGB8888,
  69         DRM_FORMAT_XBGR8888,
  70         DRM_FORMAT_XRGB2101010,
  71         DRM_FORMAT_XBGR2101010,
  72 };
  73
  74 static const uint32_t skl_primary_formats[] = {
  75         DRM_FORMAT_C8,
  76         DRM_FORMAT_RGB565,
  77         DRM_FORMAT_XRGB8888,
  78         DRM_FORMAT_XBGR8888,
  79         DRM_FORMAT_ARGB8888,
  80         DRM_FORMAT_ABGR8888,
  81         DRM_FORMAT_XRGB2101010,
  82         DRM_FORMAT_XBGR2101010,
  83         DRM_FORMAT_YUYV,
  84         DRM_FORMAT_YVYU,
  85         DRM_FORMAT_UYVY,
  86         DRM_FORMAT_VYUY,
  87 };
  88
  89 /* Cursor formats */
  90 static const uint32_t intel_cursor_formats[] = {
  91         DRM_FORMAT_ARGB8888,
  92 };
  93
  94 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  95                                 struct intel_crtc_state *pipe_config);
  96 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  97                                    struct intel_crtc_state *pipe_config);
  98
  99 static int intel_framebuffer_init(struct drm_device *dev,
 100                                   struct intel_framebuffer *ifb,
 101                                   struct drm_mode_fb_cmd2 *mode_cmd,
 102                                   struct drm_i915_gem_object *obj);
 103 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
 104 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
 105 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
 106 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
 107                                          struct intel_link_m_n *m_n,
 108                                          struct intel_link_m_n *m2_n2);
 109 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 110 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 111 static void haswell_set_pipemisc(struct drm_crtc *crtc);
 112 static void vlv_prepare_pll(struct intel_crtc *crtc,
 113                             const struct intel_crtc_state *pipe_config);
 114 static void chv_prepare_pll(struct intel_crtc *crtc,
 115                             const struct intel_crtc_state *pipe_config);
 116 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 117 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 118 static void skl_init_scalers(struct drm_i915_private *dev_priv,
 119                              struct intel_crtc *crtc,
 120                              struct intel_crtc_state *crtc_state);
 121 static void skylake_pfit_enable(struct intel_crtc *crtc);
 122 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
 123 static void ironlake_pfit_enable(struct intel_crtc *crtc);
 124 static void intel_modeset_setup_hw_state(struct drm_device *dev);
 125 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
 126 static int ilk_max_pixel_rate(struct drm_atomic_state *state);
 127 static int bxt_calc_cdclk(int max_pixclk);
 128
 129 struct intel_limit {
 130         struct {
 131                 int min, max;
 132         } dot, vco, n, m, m1, m2, p, p1;
 133
 134         struct {
 135                 int dot_limit;
 136                 int p2_slow, p2_fast;
 137         } p2;
 138 };
 139
 140 /* returns HPLL frequency in kHz */
 141 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
 142 {
 143         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 144
 145         /* Obtain SKU information */
 146         mutex_lock(&dev_priv->sb_lock);
 147         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 148                 CCK_FUSE_HPLL_FREQ_MASK;
 149         mutex_unlock(&dev_priv->sb_lock);
 150
 151         return vco_freq[hpll_freq] * 1000;
 152 }
 153
 154 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
 155                       const char *name, u32 reg, int ref_freq)
 156 {
 157         u32 val;
 158         int divider;
 159
 160         mutex_lock(&dev_priv->sb_lock);
 161         val = vlv_cck_read(dev_priv, reg);
 162         mutex_unlock(&dev_priv->sb_lock);
 163
 164         divider = val & CCK_FREQUENCY_VALUES;
 165
 166         WARN((val & CCK_FREQUENCY_STATUS) !=
 167              (divider << CCK_FREQUENCY_STATUS_SHIFT),
 168              "%s change in progress\n", name);
 169
 170         return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
 171 }
 172
 173 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 174                                   const char *name, u32 reg)
 175 {
 176         if (dev_priv->hpll_freq == 0)
 177                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
 178
 179         return vlv_get_cck_clock(dev_priv, name, reg,
 180                                  dev_priv->hpll_freq);
 181 }
 182
 183 static int
 184 intel_pch_rawclk(struct drm_i915_private *dev_priv)
 185 {
 186         return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
 187 }
 188
 189 static int
 190 intel_vlv_hrawclk(struct drm_i915_private *dev_priv)
 191 {
 192         /* RAWCLK_FREQ_VLV register updated from power well code */
 193         return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
 194                                       CCK_DISPLAY_REF_CLOCK_CONTROL);
 195 }
 196
 197 static int
 198 intel_g4x_hrawclk(struct drm_i915_private *dev_priv)
 199 {
 200         uint32_t clkcfg;
 201
 202         /* hrawclock is 1/4 the FSB frequency */
 203         clkcfg = I915_READ(CLKCFG);
 204         switch (clkcfg & CLKCFG_FSB_MASK) {
 205         case CLKCFG_FSB_400:
 206                 return 100000;
 207         case CLKCFG_FSB_533:
 208                 return 133333;
 209         case CLKCFG_FSB_667:
 210                 return 166667;
 211         case CLKCFG_FSB_800:
 212                 return 200000;
 213         case CLKCFG_FSB_1067:
 214                 return 266667;
 215         case CLKCFG_FSB_1333:
 216                 return 333333;
 217         /* these two are just a guess; one of them might be right */
 218         case CLKCFG_FSB_1600:
 219         case CLKCFG_FSB_1600_ALT:
 220                 return 400000;
 221         default:
 222                 return 133333;
 223         }
 224 }
 225
 226 void intel_update_rawclk(struct drm_i915_private *dev_priv)
 227 {
 228         if (HAS_PCH_SPLIT(dev_priv))
 229                 dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv);
 230         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 231                 dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv);
 232         else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
 233                 dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv);
 234         else
 235                 return; /* no rawclk on other platforms, or no need to know it */
 236
 237         DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
 238 }
 239
 240 static void intel_update_czclk(struct drm_i915_private *dev_priv)
 241 {
 242         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
 243                 return;
 244
 245         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 246                                                       CCK_CZ_CLOCK_CONTROL);
 247
 248         DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
 249 }
 250
 251 static inline u32 /* units of 100MHz */
 252 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
 253                     const struct intel_crtc_state *pipe_config)
 254 {
 255         if (HAS_DDI(dev_priv))
 256                 return pipe_config->port_clock; /* SPLL */
 257         else if (IS_GEN5(dev_priv))
 258                 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
 259         else
 260                 return 270000;
 261 }
 262
 263 static const struct intel_limit intel_limits_i8xx_dac = {
 264         .dot = { .min = 25000, .max = 350000 },
 265         .vco = { .min = 908000, .max = 1512000 },
 266         .n = { .min = 2, .max = 16 },
 267         .m = { .min = 96, .max = 140 },
 268         .m1 = { .min = 18, .max = 26 },
 269         .m2 = { .min = 6, .max = 16 },
 270         .p = { .min = 4, .max = 128 },
 271         .p1 = { .min = 2, .max = 33 },
 272         .p2 = { .dot_limit = 165000,
 273                 .p2_slow = 4, .p2_fast = 2 },
 274 };
 275
 276 static const struct intel_limit intel_limits_i8xx_dvo = {
 277         .dot = { .min = 25000, .max = 350000 },
 278         .vco = { .min = 908000, .max = 1512000 },
 279         .n = { .min = 2, .max = 16 },
 280         .m = { .min = 96, .max = 140 },
 281         .m1 = { .min = 18, .max = 26 },
 282         .m2 = { .min = 6, .max = 16 },
 283         .p = { .min = 4, .max = 128 },
 284         .p1 = { .min = 2, .max = 33 },
 285         .p2 = { .dot_limit = 165000,
 286                 .p2_slow = 4, .p2_fast = 4 },
 287 };
 288
 289 static const struct intel_limit intel_limits_i8xx_lvds = {
 290         .dot = { .min = 25000, .max = 350000 },
 291         .vco = { .min = 908000, .max = 1512000 },
 292         .n = { .min = 2, .max = 16 },
 293         .m = { .min = 96, .max = 140 },
 294         .m1 = { .min = 18, .max = 26 },
 295         .m2 = { .min = 6, .max = 16 },
 296         .p = { .min = 4, .max = 128 },
 297         .p1 = { .min = 1, .max = 6 },
 298         .p2 = { .dot_limit = 165000,
 299                 .p2_slow = 14, .p2_fast = 7 },
 300 };
 301
 302 static const struct intel_limit intel_limits_i9xx_sdvo = {
 303         .dot = { .min = 20000, .max = 400000 },
 304         .vco = { .min = 1400000, .max = 2800000 },
 305         .n = { .min = 1, .max = 6 },
 306         .m = { .min = 70, .max = 120 },
 307         .m1 = { .min = 8, .max = 18 },
 308         .m2 = { .min = 3, .max = 7 },
 309         .p = { .min = 5, .max = 80 },
 310         .p1 = { .min = 1, .max = 8 },
 311         .p2 = { .dot_limit = 200000,
 312                 .p2_slow = 10, .p2_fast = 5 },
 313 };
 314
 315 static const struct intel_limit intel_limits_i9xx_lvds = {
 316         .dot = { .min = 20000, .max = 400000 },
 317         .vco = { .min = 1400000, .max = 2800000 },
 318         .n = { .min = 1, .max = 6 },
 319         .m = { .min = 70, .max = 120 },
 320         .m1 = { .min = 8, .max = 18 },
 321         .m2 = { .min = 3, .max = 7 },
 322         .p = { .min = 7, .max = 98 },
 323         .p1 = { .min = 1, .max = 8 },
 324         .p2 = { .dot_limit = 112000,
 325                 .p2_slow = 14, .p2_fast = 7 },
 326 };
 327
 328
 329 static const struct intel_limit intel_limits_g4x_sdvo = {
 330         .dot = { .min = 25000, .max = 270000 },
 331         .vco = { .min = 1750000, .max = 3500000},
 332         .n = { .min = 1, .max = 4 },
 333         .m = { .min = 104, .max = 138 },
 334         .m1 = { .min = 17, .max = 23 },
 335         .m2 = { .min = 5, .max = 11 },
 336         .p = { .min = 10, .max = 30 },
 337         .p1 = { .min = 1, .max = 3},
 338         .p2 = { .dot_limit = 270000,
 339                 .p2_slow = 10,
 340                 .p2_fast = 10
 341         },
 342 };
 343
 344 static const struct intel_limit intel_limits_g4x_hdmi = {
 345         .dot = { .min = 22000, .max = 400000 },
 346         .vco = { .min = 1750000, .max = 3500000},
 347         .n = { .min = 1, .max = 4 },
 348         .m = { .min = 104, .max = 138 },
 349         .m1 = { .min = 16, .max = 23 },
 350         .m2 = { .min = 5, .max = 11 },
 351         .p = { .min = 5, .max = 80 },
 352         .p1 = { .min = 1, .max = 8},
 353         .p2 = { .dot_limit = 165000,
 354                 .p2_slow = 10, .p2_fast = 5 },
 355 };
 356
 357 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
 358         .dot = { .min = 20000, .max = 115000 },
 359         .vco = { .min = 1750000, .max = 3500000 },
 360         .n = { .min = 1, .max = 3 },
 361         .m = { .min = 104, .max = 138 },
 362         .m1 = { .min = 17, .max = 23 },
 363         .m2 = { .min = 5, .max = 11 },
 364         .p = { .min = 28, .max = 112 },
 365         .p1 = { .min = 2, .max = 8 },
 366         .p2 = { .dot_limit = 0,
 367                 .p2_slow = 14, .p2_fast = 14
 368         },
 369 };
 370
 371 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
 372         .dot = { .min = 80000, .max = 224000 },
 373         .vco = { .min = 1750000, .max = 3500000 },
 374         .n = { .min = 1, .max = 3 },
 375         .m = { .min = 104, .max = 138 },
 376         .m1 = { .min = 17, .max = 23 },
 377         .m2 = { .min = 5, .max = 11 },
 378         .p = { .min = 14, .max = 42 },
 379         .p1 = { .min = 2, .max = 6 },
 380         .p2 = { .dot_limit = 0,
 381                 .p2_slow = 7, .p2_fast = 7
 382         },
 383 };
 384
 385 static const struct intel_limit intel_limits_pineview_sdvo = {
 386         .dot = { .min = 20000, .max = 400000},
 387         .vco = { .min = 1700000, .max = 3500000 },
 388         /* Pineview's Ncounter is a ring counter */
 389         .n = { .min = 3, .max = 6 },
 390         .m = { .min = 2, .max = 256 },
 391         /* Pineview only has one combined m divider, which we treat as m2. */
 392         .m1 = { .min = 0, .max = 0 },
 393         .m2 = { .min = 0, .max = 254 },
 394         .p = { .min = 5, .max = 80 },
 395         .p1 = { .min = 1, .max = 8 },
 396         .p2 = { .dot_limit = 200000,
 397                 .p2_slow = 10, .p2_fast = 5 },
 398 };
 399
 400 static const struct intel_limit intel_limits_pineview_lvds = {
 401         .dot = { .min = 20000, .max = 400000 },
 402         .vco = { .min = 1700000, .max = 3500000 },
 403         .n = { .min = 3, .max = 6 },
 404         .m = { .min = 2, .max = 256 },
 405         .m1 = { .min = 0, .max = 0 },
 406         .m2 = { .min = 0, .max = 254 },
 407         .p = { .min = 7, .max = 112 },
 408         .p1 = { .min = 1, .max = 8 },
 409         .p2 = { .dot_limit = 112000,
 410                 .p2_slow = 14, .p2_fast = 14 },
 411 };
 412
 413 /* Ironlake / Sandybridge
 414  *
 415  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 416  * the range value for them is (actual_value - 2).
 417  */
 418 static const struct intel_limit intel_limits_ironlake_dac = {
 419         .dot = { .min = 25000, .max = 350000 },
 420         .vco = { .min = 1760000, .max = 3510000 },
 421         .n = { .min = 1, .max = 5 },
 422         .m = { .min = 79, .max = 127 },
 423         .m1 = { .min = 12, .max = 22 },
 424         .m2 = { .min = 5, .max = 9 },
 425         .p = { .min = 5, .max = 80 },
 426         .p1 = { .min = 1, .max = 8 },
 427         .p2 = { .dot_limit = 225000,
 428                 .p2_slow = 10, .p2_fast = 5 },
 429 };
 430
 431 static const struct intel_limit intel_limits_ironlake_single_lvds = {
 432         .dot = { .min = 25000, .max = 350000 },
 433         .vco = { .min = 1760000, .max = 3510000 },
 434         .n = { .min = 1, .max = 3 },
 435         .m = { .min = 79, .max = 118 },
 436         .m1 = { .min = 12, .max = 22 },
 437         .m2 = { .min = 5, .max = 9 },
 438         .p = { .min = 28, .max = 112 },
 439         .p1 = { .min = 2, .max = 8 },
 440         .p2 = { .dot_limit = 225000,
 441                 .p2_slow = 14, .p2_fast = 14 },
 442 };
 443
 444 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
 445         .dot = { .min = 25000, .max = 350000 },
 446         .vco = { .min = 1760000, .max = 3510000 },
 447         .n = { .min = 1, .max = 3 },
 448         .m = { .min = 79, .max = 127 },
 449         .m1 = { .min = 12, .max = 22 },
 450         .m2 = { .min = 5, .max = 9 },
 451         .p = { .min = 14, .max = 56 },
 452         .p1 = { .min = 2, .max = 8 },
 453         .p2 = { .dot_limit = 225000,
 454                 .p2_slow = 7, .p2_fast = 7 },
 455 };
 456
 457 /* LVDS 100mhz refclk limits. */
 458 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
 459         .dot = { .min = 25000, .max = 350000 },
 460         .vco = { .min = 1760000, .max = 3510000 },
 461         .n = { .min = 1, .max = 2 },
 462         .m = { .min = 79, .max = 126 },
 463         .m1 = { .min = 12, .max = 22 },
 464         .m2 = { .min = 5, .max = 9 },
 465         .p = { .min = 28, .max = 112 },
 466         .p1 = { .min = 2, .max = 8 },
 467         .p2 = { .dot_limit = 225000,
 468                 .p2_slow = 14, .p2_fast = 14 },
 469 };
 470
 471 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
 472         .dot = { .min = 25000, .max = 350000 },
 473         .vco = { .min = 1760000, .max = 3510000 },
 474         .n = { .min = 1, .max = 3 },
 475         .m = { .min = 79, .max = 126 },
 476         .m1 = { .min = 12, .max = 22 },
 477         .m2 = { .min = 5, .max = 9 },
 478         .p = { .min = 14, .max = 42 },
 479         .p1 = { .min = 2, .max = 6 },
 480         .p2 = { .dot_limit = 225000,
 481                 .p2_slow = 7, .p2_fast = 7 },
 482 };
 483
 484 static const struct intel_limit intel_limits_vlv = {
 485          /*
 486           * These are the data rate limits (measured in fast clocks)
 487           * since those are the strictest limits we have. The fast
 488           * clock and actual rate limits are more relaxed, so checking
 489           * them would make no difference.
 490           */
 491         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 492         .vco = { .min = 4000000, .max = 6000000 },
 493         .n = { .min = 1, .max = 7 },
 494         .m1 = { .min = 2, .max = 3 },
 495         .m2 = { .min = 11, .max = 156 },
 496         .p1 = { .min = 2, .max = 3 },
 497         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 498 };
 499
 500 static const struct intel_limit intel_limits_chv = {
 501         /*
 502          * These are the data rate limits (measured in fast clocks)
 503          * since those are the strictest limits we have.  The fast
 504          * clock and actual rate limits are more relaxed, so checking
 505          * them would make no difference.
 506          */
 507         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 508         .vco = { .min = 4800000, .max = 6480000 },
 509         .n = { .min = 1, .max = 1 },
 510         .m1 = { .min = 2, .max = 2 },
 511         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 512         .p1 = { .min = 2, .max = 4 },
 513         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 514 };
 515
 516 static const struct intel_limit intel_limits_bxt = {
 517         /* FIXME: find real dot limits */
 518         .dot = { .min = 0, .max = INT_MAX },
 519         .vco = { .min = 4800000, .max = 6700000 },
 520         .n = { .min = 1, .max = 1 },
 521         .m1 = { .min = 2, .max = 2 },
 522         /* FIXME: find real m2 limits */
 523         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 524         .p1 = { .min = 2, .max = 4 },
 525         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 526 };
 527
 528 static bool
 529 needs_modeset(struct drm_crtc_state *state)
 530 {
 531         return drm_atomic_crtc_needs_modeset(state);
 532 }
 533
 534 /*
 535  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 536  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 537  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 538  * The helpers' return value is the rate of the clock that is fed to the
 539  * display engine's pipe which can be the above fast dot clock rate or a
 540  * divided-down version of it.
 541  */
 542 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 543 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
 544 {
 545         clock->m = clock->m2 + 2;
 546         clock->p = clock->p1 * clock->p2;
 547         if (WARN_ON(clock->n == 0 || clock->p == 0))
 548                 return 0;
 549         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 550         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 551
 552         return clock->dot;
 553 }
 554
 555 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 556 {
 557         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 558 }
 559
 560 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
 561 {
 562         clock->m = i9xx_dpll_compute_m(clock);
 563         clock->p = clock->p1 * clock->p2;
 564         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 565                 return 0;
 566         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 567         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 568
 569         return clock->dot;
 570 }
 571
 572 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
 573 {
 574         clock->m = clock->m1 * clock->m2;
 575         clock->p = clock->p1 * clock->p2;
 576         if (WARN_ON(clock->n == 0 || clock->p == 0))
 577                 return 0;
 578         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 579         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 580
 581         return clock->dot / 5;
 582 }
 583
 584 int chv_calc_dpll_params(int refclk, struct dpll *clock)
 585 {
 586         clock->m = clock->m1 * clock->m2;
 587         clock->p = clock->p1 * clock->p2;
 588         if (WARN_ON(clock->n == 0 || clock->p == 0))
 589                 return 0;
 590         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 591                         clock->n << 22);
 592         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 593
 594         return clock->dot / 5;
 595 }
 596
 597 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 598 /**
 599  * Returns whether the given set of divisors are valid for a given refclk with
 600  * the given connectors.
 601  */
 602
 603 static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
 604                                const struct intel_limit *limit,
 605                                const struct dpll *clock)
 606 {
 607         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 608                 INTELPllInvalid("n out of range\n");
 609         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 610                 INTELPllInvalid("p1 out of range\n");
 611         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 612                 INTELPllInvalid("m2 out of range\n");
 613         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 614                 INTELPllInvalid("m1 out of range\n");
 615
 616         if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
 617             !IS_CHERRYVIEW(dev_priv) && !IS_BROXTON(dev_priv))
 618                 if (clock->m1 <= clock->m2)
 619                         INTELPllInvalid("m1 <= m2\n");
 620
 621         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
 622             !IS_BROXTON(dev_priv)) {
 623                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 624                         INTELPllInvalid("p out of range\n");
 625                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 626                         INTELPllInvalid("m out of range\n");
 627         }
 628
 629         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 630                 INTELPllInvalid("vco out of range\n");
 631         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 632          * connector, etc., rather than just a single range.
 633          */
 634         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 635                 INTELPllInvalid("dot out of range\n");
 636
 637         return true;
 638 }
 639
 640 static int
 641 i9xx_select_p2_div(const struct intel_limit *limit,
 642                    const struct intel_crtc_state *crtc_state,
 643                    int target)
 644 {
 645         struct drm_device *dev = crtc_state->base.crtc->dev;
 646
 647         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 648                 /*
 649                  * For LVDS just rely on its current settings for dual-channel.
 650                  * We haven't figured out how to reliably set up different
 651                  * single/dual channel state, if we even can.
 652                  */
 653                 if (intel_is_dual_link_lvds(dev))
 654                         return limit->p2.p2_fast;
 655                 else
 656                         return limit->p2.p2_slow;
 657         } else {
 658                 if (target < limit->p2.dot_limit)
 659                         return limit->p2.p2_slow;
 660                 else
 661                         return limit->p2.p2_fast;
 662         }
 663 }
 664
 665 /*
 666  * Returns a set of divisors for the desired target clock with the given
 667  * refclk, or FALSE.  The returned values represent the clock equation:
 668  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 669  *
 670  * Target and reference clocks are specified in kHz.
 671  *
 672  * If match_clock is provided, then best_clock P divider must match the P
 673  * divider from @match_clock used for LVDS downclocking.
 674  */
 675 static bool
 676 i9xx_find_best_dpll(const struct intel_limit *limit,
 677                     struct intel_crtc_state *crtc_state,
 678                     int target, int refclk, struct dpll *match_clock,
 679                     struct dpll *best_clock)
 680 {
 681         struct drm_device *dev = crtc_state->base.crtc->dev;
 682         struct dpll clock;
 683         int err = target;
 684
 685         memset(best_clock, 0, sizeof(*best_clock));
 686
 687         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 688
 689         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 690              clock.m1++) {
 691                 for (clock.m2 = limit->m2.min;
 692                      clock.m2 <= limit->m2.max; clock.m2++) {
 693                         if (clock.m2 >= clock.m1)
 694                                 break;
 695                         for (clock.n = limit->n.min;
 696                              clock.n <= limit->n.max; clock.n++) {
 697                                 for (clock.p1 = limit->p1.min;
 698                                         clock.p1 <= limit->p1.max; clock.p1++) {
 699                                         int this_err;
 700
 701                                         i9xx_calc_dpll_params(refclk, &clock);
 702                                         if (!intel_PLL_is_valid(to_i915(dev),
 703                                                                 limit,
 704                                                                 &clock))
 705                                                 continue;
 706                                         if (match_clock &&
 707                                             clock.p != match_clock->p)
 708                                                 continue;
 709
 710                                         this_err = abs(clock.dot - target);
 711                                         if (this_err < err) {
 712                                                 *best_clock = clock;
 713                                                 err = this_err;
 714                                         }
 715                                 }
 716                         }
 717                 }
 718         }
 719
 720         return (err != target);
 721 }
 722
 723 /*
 724  * Returns a set of divisors for the desired target clock with the given
 725  * refclk, or FALSE.  The returned values represent the clock equation:
 726  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 727  *
 728  * Target and reference clocks are specified in kHz.
 729  *
 730  * If match_clock is provided, then best_clock P divider must match the P
 731  * divider from @match_clock used for LVDS downclocking.
 732  */
 733 static bool
 734 pnv_find_best_dpll(const struct intel_limit *limit,
 735                    struct intel_crtc_state *crtc_state,
 736                    int target, int refclk, struct dpll *match_clock,
 737                    struct dpll *best_clock)
 738 {
 739         struct drm_device *dev = crtc_state->base.crtc->dev;
 740         struct dpll clock;
 741         int err = target;
 742
 743         memset(best_clock, 0, sizeof(*best_clock));
 744
 745         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 746
 747         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 748              clock.m1++) {
 749                 for (clock.m2 = limit->m2.min;
 750                      clock.m2 <= limit->m2.max; clock.m2++) {
 751                         for (clock.n = limit->n.min;
 752                              clock.n <= limit->n.max; clock.n++) {
 753                                 for (clock.p1 = limit->p1.min;
 754                                         clock.p1 <= limit->p1.max; clock.p1++) {
 755                                         int this_err;
 756
 757                                         pnv_calc_dpll_params(refclk, &clock);
 758                                         if (!intel_PLL_is_valid(to_i915(dev),
 759                                                                 limit,
 760                                                                 &clock))
 761                                                 continue;
 762                                         if (match_clock &&
 763                                             clock.p != match_clock->p)
 764                                                 continue;
 765
 766                                         this_err = abs(clock.dot - target);
 767                                         if (this_err < err) {
 768                                                 *best_clock = clock;
 769                                                 err = this_err;
 770                                         }
 771                                 }
 772                         }
 773                 }
 774         }
 775
 776         return (err != target);
 777 }
 778
 779 /*
 780  * Returns a set of divisors for the desired target clock with the given
 781  * refclk, or FALSE.  The returned values represent the clock equation:
 782  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 783  *
 784  * Target and reference clocks are specified in kHz.
 785  *
 786  * If match_clock is provided, then best_clock P divider must match the P
 787  * divider from @match_clock used for LVDS downclocking.
 788  */
 789 static bool
 790 g4x_find_best_dpll(const struct intel_limit *limit,
 791                    struct intel_crtc_state *crtc_state,
 792                    int target, int refclk, struct dpll *match_clock,
 793                    struct dpll *best_clock)
 794 {
 795         struct drm_device *dev = crtc_state->base.crtc->dev;
 796         struct dpll clock;
 797         int max_n;
 798         bool found = false;
 799         /* approximately equals target * 0.00585 */
 800         int err_most = (target >> 8) + (target >> 9);
 801
 802         memset(best_clock, 0, sizeof(*best_clock));
 803
 804         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 805
 806         max_n = limit->n.max;
 807         /* based on hardware requirement, prefer smaller n to precision */
 808         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 809                 /* based on hardware requirement, prefere larger m1,m2 */
 810                 for (clock.m1 = limit->m1.max;
 811                      clock.m1 >= limit->m1.min; clock.m1--) {
 812                         for (clock.m2 = limit->m2.max;
 813                              clock.m2 >= limit->m2.min; clock.m2--) {
 814                                 for (clock.p1 = limit->p1.max;
 815                                      clock.p1 >= limit->p1.min; clock.p1--) {
 816                                         int this_err;
 817
 818                                         i9xx_calc_dpll_params(refclk, &clock);
 819                                         if (!intel_PLL_is_valid(to_i915(dev),
 820                                                                 limit,
 821                                                                 &clock))
 822                                                 continue;
 823
 824                                         this_err = abs(clock.dot - target);
 825                                         if (this_err < err_most) {
 826                                                 *best_clock = clock;
 827                                                 err_most = this_err;
 828                                                 max_n = clock.n;
 829                                                 found = true;
 830                                         }
 831                                 }
 832                         }
 833                 }
 834         }
 835         return found;
 836 }
 837
 838 /*
 839  * Check if the calculated PLL configuration is more optimal compared to the
 840  * best configuration and error found so far. Return the calculated error.
 841  */
 842 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 843                                const struct dpll *calculated_clock,
 844                                const struct dpll *best_clock,
 845                                unsigned int best_error_ppm,
 846                                unsigned int *error_ppm)
 847 {
 848         /*
 849          * For CHV ignore the error and consider only the P value.
 850          * Prefer a bigger P value based on HW requirements.
 851          */
 852         if (IS_CHERRYVIEW(to_i915(dev))) {
 853                 *error_ppm = 0;
 854
 855                 return calculated_clock->p > best_clock->p;
 856         }
 857
 858         if (WARN_ON_ONCE(!target_freq))
 859                 return false;
 860
 861         *error_ppm = div_u64(1000000ULL *
 862                                 abs(target_freq - calculated_clock->dot),
 863                              target_freq);
 864         /*
 865          * Prefer a better P value over a better (smaller) error if the error
 866          * is small. Ensure this preference for future configurations too by
 867          * setting the error to 0.
 868          */
 869         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 870                 *error_ppm = 0;
 871
 872                 return true;
 873         }
 874
 875         return *error_ppm + 10 < best_error_ppm;
 876 }
 877
 878 /*
 879  * Returns a set of divisors for the desired target clock with the given
 880  * refclk, or FALSE.  The returned values represent the clock equation:
 881  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 882  */
 883 static bool
 884 vlv_find_best_dpll(const struct intel_limit *limit,
 885                    struct intel_crtc_state *crtc_state,
 886                    int target, int refclk, struct dpll *match_clock,
 887                    struct dpll *best_clock)
 888 {
 889         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 890         struct drm_device *dev = crtc->base.dev;
 891         struct dpll clock;
 892         unsigned int bestppm = 1000000;
 893         /* min update 19.2 MHz */
 894         int max_n = min(limit->n.max, refclk / 19200);
 895         bool found = false;
 896
 897         target *= 5; /* fast clock */
 898
 899         memset(best_clock, 0, sizeof(*best_clock));
 900
 901         /* based on hardware requirement, prefer smaller n to precision */
 902         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 903                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 904                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 905                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 906                                 clock.p = clock.p1 * clock.p2;
 907                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 908                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 909                                         unsigned int ppm;
 910
 911                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 912                                                                      refclk * clock.m1);
 913
 914                                         vlv_calc_dpll_params(refclk, &clock);
 915
 916                                         if (!intel_PLL_is_valid(to_i915(dev),
 917                                                                 limit,
 918                                                                 &clock))
 919                                                 continue;
 920
 921                                         if (!vlv_PLL_is_optimal(dev, target,
 922                                                                 &clock,
 923                                                                 best_clock,
 924                                                                 bestppm, &ppm))
 925                                                 continue;
 926
 927                                         *best_clock = clock;
 928                                         bestppm = ppm;
 929                                         found = true;
 930                                 }
 931                         }
 932                 }
 933         }
 934
 935         return found;
 936 }
 937
 938 /*
 939  * Returns a set of divisors for the desired target clock with the given
 940  * refclk, or FALSE.  The returned values represent the clock equation:
 941  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 942  */
 943 static bool
 944 chv_find_best_dpll(const struct intel_limit *limit,
 945                    struct intel_crtc_state *crtc_state,
 946                    int target, int refclk, struct dpll *match_clock,
 947                    struct dpll *best_clock)
 948 {
 949         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 950         struct drm_device *dev = crtc->base.dev;
 951         unsigned int best_error_ppm;
 952         struct dpll clock;
 953         uint64_t m2;
 954         int found = false;
 955
 956         memset(best_clock, 0, sizeof(*best_clock));
 957         best_error_ppm = 1000000;
 958
 959         /*
 960          * Based on hardware doc, the n always set to 1, and m1 always
 961          * set to 2.  If requires to support 200Mhz refclk, we need to
 962          * revisit this because n may not 1 anymore.
 963          */
 964         clock.n = 1, clock.m1 = 2;
 965         target *= 5;    /* fast clock */
 966
 967         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 968                 for (clock.p2 = limit->p2.p2_fast;
 969                                 clock.p2 >= limit->p2.p2_slow;
 970                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 971                         unsigned int error_ppm;
 972
 973                         clock.p = clock.p1 * clock.p2;
 974
 975                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 976                                         clock.n) << 22, refclk * clock.m1);
 977
 978                         if (m2 > INT_MAX/clock.m1)
 979                                 continue;
 980
 981                         clock.m2 = m2;
 982
 983                         chv_calc_dpll_params(refclk, &clock);
 984
 985                         if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))
 986                                 continue;
 987
 988                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
 989                                                 best_error_ppm, &error_ppm))
 990                                 continue;
 991
 992                         *best_clock = clock;
 993                         best_error_ppm = error_ppm;
 994                         found = true;
 995                 }
 996         }
 997
 998         return found;
 999 }
1000
1001 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1002                         struct dpll *best_clock)
1003 {
1004         int refclk = 100000;
1005         const struct intel_limit *limit = &intel_limits_bxt;
1006
1007         return chv_find_best_dpll(limit, crtc_state,
1008                                   target_clock, refclk, NULL, best_clock);
1009 }
1010
1011 bool intel_crtc_active(struct intel_crtc *crtc)
1012 {
1013         /* Be paranoid as we can arrive here with only partial
1014          * state retrieved from the hardware during setup.
1015          *
1016          * We can ditch the adjusted_mode.crtc_clock check as soon
1017          * as Haswell has gained clock readout/fastboot support.
1018          *
1019          * We can ditch the crtc->primary->fb check as soon as we can
1020          * properly reconstruct framebuffers.
1021          *
1022          * FIXME: The intel_crtc->active here should be switched to
1023          * crtc->state->active once we have proper CRTC states wired up
1024          * for atomic.
1025          */
1026         return crtc->active && crtc->base.primary->state->fb &&
1027                 crtc->config->base.adjusted_mode.crtc_clock;
1028 }
1029
1030 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1031                                              enum pipe pipe)
1032 {
1033         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1034
1035         return crtc->config->cpu_transcoder;
1036 }
1037
1038 static bool pipe_dsl_stopped(struct drm_i915_private *dev_priv, enum pipe pipe)
1039 {
1040         i915_reg_t reg = PIPEDSL(pipe);
1041         u32 line1, line2;
1042         u32 line_mask;
1043
1044         if (IS_GEN2(dev_priv))
1045                 line_mask = DSL_LINEMASK_GEN2;
1046         else
1047                 line_mask = DSL_LINEMASK_GEN3;
1048
1049         line1 = I915_READ(reg) & line_mask;
1050         msleep(5);
1051         line2 = I915_READ(reg) & line_mask;
1052
1053         return line1 == line2;
1054 }
1055
1056 /*
1057  * intel_wait_for_pipe_off - wait for pipe to turn off
1058  * @crtc: crtc whose pipe to wait for
1059  *
1060  * After disabling a pipe, we can't wait for vblank in the usual way,
1061  * spinning on the vblank interrupt status bit, since we won't actually
1062  * see an interrupt when the pipe is disabled.
1063  *
1064  * On Gen4 and above:
1065  *   wait for the pipe register state bit to turn off
1066  *
1067  * Otherwise:
1068  *   wait for the display line value to settle (it usually
1069  *   ends up stopping at the start of the next frame).
1070  *
1071  */
1072 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1073 {
1074         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1075         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1076         enum pipe pipe = crtc->pipe;
1077
1078         if (INTEL_GEN(dev_priv) >= 4) {
1079                 i915_reg_t reg = PIPECONF(cpu_transcoder);
1080
1081                 /* Wait for the Pipe State to go off */
1082                 if (intel_wait_for_register(dev_priv,
1083                                             reg, I965_PIPECONF_ACTIVE, 0,
1084                                             100))
1085                         WARN(1, "pipe_off wait timed out\n");
1086         } else {
1087                 /* Wait for the display line to settle */
1088                 if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100))
1089                         WARN(1, "pipe_off wait timed out\n");
1090         }
1091 }
1092
1093 /* Only for pre-ILK configs */
1094 void assert_pll(struct drm_i915_private *dev_priv,
1095                 enum pipe pipe, bool state)
1096 {
1097         u32 val;
1098         bool cur_state;
1099
1100         val = I915_READ(DPLL(pipe));
1101         cur_state = !!(val & DPLL_VCO_ENABLE);
1102         I915_STATE_WARN(cur_state != state,
1103              "PLL state assertion failure (expected %s, current %s)\n",
1104                         onoff(state), onoff(cur_state));
1105 }
1106
1107 /* XXX: the dsi pll is shared between MIPI DSI ports */
1108 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1109 {
1110         u32 val;
1111         bool cur_state;
1112
1113         mutex_lock(&dev_priv->sb_lock);
1114         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1115         mutex_unlock(&dev_priv->sb_lock);
1116
1117         cur_state = val & DSI_PLL_VCO_EN;
1118         I915_STATE_WARN(cur_state != state,
1119              "DSI PLL state assertion failure (expected %s, current %s)\n",
1120                         onoff(state), onoff(cur_state));
1121 }
1122
1123 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1124                           enum pipe pipe, bool state)
1125 {
1126         bool cur_state;
1127         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1128                                                                       pipe);
1129
1130         if (HAS_DDI(dev_priv)) {
1131                 /* DDI does not have a specific FDI_TX register */
1132                 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1133                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1134         } else {
1135                 u32 val = I915_READ(FDI_TX_CTL(pipe));
1136                 cur_state = !!(val & FDI_TX_ENABLE);
1137         }
1138         I915_STATE_WARN(cur_state != state,
1139              "FDI TX state assertion failure (expected %s, current %s)\n",
1140                         onoff(state), onoff(cur_state));
1141 }
1142 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1143 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1144
1145 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1146                           enum pipe pipe, bool state)
1147 {
1148         u32 val;
1149         bool cur_state;
1150
1151         val = I915_READ(FDI_RX_CTL(pipe));
1152         cur_state = !!(val & FDI_RX_ENABLE);
1153         I915_STATE_WARN(cur_state != state,
1154              "FDI RX state assertion failure (expected %s, current %s)\n",
1155                         onoff(state), onoff(cur_state));
1156 }
1157 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1158 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1159
1160 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1161                                       enum pipe pipe)
1162 {
1163         u32 val;
1164
1165         /* ILK FDI PLL is always enabled */
1166         if (IS_GEN5(dev_priv))
1167                 return;
1168
1169         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1170         if (HAS_DDI(dev_priv))
1171                 return;
1172
1173         val = I915_READ(FDI_TX_CTL(pipe));
1174         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1175 }
1176
1177 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1178                        enum pipe pipe, bool state)
1179 {
1180         u32 val;
1181         bool cur_state;
1182
1183         val = I915_READ(FDI_RX_CTL(pipe));
1184         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1185         I915_STATE_WARN(cur_state != state,
1186              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1187                         onoff(state), onoff(cur_state));
1188 }
1189
1190 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1191 {
1192         i915_reg_t pp_reg;
1193         u32 val;
1194         enum pipe panel_pipe = PIPE_A;
1195         bool locked = true;
1196
1197         if (WARN_ON(HAS_DDI(dev_priv)))
1198                 return;
1199
1200         if (HAS_PCH_SPLIT(dev_priv)) {
1201                 u32 port_sel;
1202
1203                 pp_reg = PP_CONTROL(0);
1204                 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1205
1206                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1207                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1208                         panel_pipe = PIPE_B;
1209                 /* XXX: else fix for eDP */
1210         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1211                 /* presumably write lock depends on pipe, not port select */
1212                 pp_reg = PP_CONTROL(pipe);
1213                 panel_pipe = pipe;
1214         } else {
1215                 pp_reg = PP_CONTROL(0);
1216                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1217                         panel_pipe = PIPE_B;
1218         }
1219
1220         val = I915_READ(pp_reg);
1221         if (!(val & PANEL_POWER_ON) ||
1222             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1223                 locked = false;
1224
1225         I915_STATE_WARN(panel_pipe == pipe && locked,
1226              "panel assertion failure, pipe %c regs locked\n",
1227              pipe_name(pipe));
1228 }
1229
1230 static void assert_cursor(struct drm_i915_private *dev_priv,
1231                           enum pipe pipe, bool state)
1232 {
1233         bool cur_state;
1234
1235         if (IS_845G(dev_priv) || IS_I865G(dev_priv))
1236                 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1237         else
1238                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1239
1240         I915_STATE_WARN(cur_state != state,
1241              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1242                         pipe_name(pipe), onoff(state), onoff(cur_state));
1243 }
1244 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1245 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1246
1247 void assert_pipe(struct drm_i915_private *dev_priv,
1248                  enum pipe pipe, bool state)
1249 {
1250         bool cur_state;
1251         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1252                                                                       pipe);
1253         enum intel_display_power_domain power_domain;
1254
1255         /* if we need the pipe quirk it must be always on */
1256         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1257             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1258                 state = true;
1259
1260         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1261         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1262                 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1263                 cur_state = !!(val & PIPECONF_ENABLE);
1264
1265                 intel_display_power_put(dev_priv, power_domain);
1266         } else {
1267                 cur_state = false;
1268         }
1269
1270         I915_STATE_WARN(cur_state != state,
1271              "pipe %c assertion failure (expected %s, current %s)\n",
1272                         pipe_name(pipe), onoff(state), onoff(cur_state));
1273 }
1274
1275 static void assert_plane(struct drm_i915_private *dev_priv,
1276                          enum plane plane, bool state)
1277 {
1278         u32 val;
1279         bool cur_state;
1280
1281         val = I915_READ(DSPCNTR(plane));
1282         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1283         I915_STATE_WARN(cur_state != state,
1284              "plane %c assertion failure (expected %s, current %s)\n",
1285                         plane_name(plane), onoff(state), onoff(cur_state));
1286 }
1287
1288 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1289 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1290
1291 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1292                                    enum pipe pipe)
1293 {
1294         int i;
1295
1296         /* Primary planes are fixed to pipes on gen4+ */
1297         if (INTEL_GEN(dev_priv) >= 4) {
1298                 u32 val = I915_READ(DSPCNTR(pipe));
1299                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1300                      "plane %c assertion failure, should be disabled but not\n",
1301                      plane_name(pipe));
1302                 return;
1303         }
1304
1305         /* Need to check both planes against the pipe */
1306         for_each_pipe(dev_priv, i) {
1307                 u32 val = I915_READ(DSPCNTR(i));
1308                 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1309                         DISPPLANE_SEL_PIPE_SHIFT;
1310                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1311                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1312                      plane_name(i), pipe_name(pipe));
1313         }
1314 }
1315
1316 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1317                                     enum pipe pipe)
1318 {
1319         int sprite;
1320
1321         if (INTEL_GEN(dev_priv) >= 9) {
1322                 for_each_sprite(dev_priv, pipe, sprite) {
1323                         u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1324                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1325                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1326                              sprite, pipe_name(pipe));
1327                 }
1328         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1329                 for_each_sprite(dev_priv, pipe, sprite) {
1330                         u32 val = I915_READ(SPCNTR(pipe, sprite));
1331                         I915_STATE_WARN(val & SP_ENABLE,
1332                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1333                              sprite_name(pipe, sprite), pipe_name(pipe));
1334                 }
1335         } else if (INTEL_GEN(dev_priv) >= 7) {
1336                 u32 val = I915_READ(SPRCTL(pipe));
1337                 I915_STATE_WARN(val & SPRITE_ENABLE,
1338                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1339                      plane_name(pipe), pipe_name(pipe));
1340         } else if (INTEL_GEN(dev_priv) >= 5) {
1341                 u32 val = I915_READ(DVSCNTR(pipe));
1342                 I915_STATE_WARN(val & DVS_ENABLE,
1343                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1344                      plane_name(pipe), pipe_name(pipe));
1345         }
1346 }
1347
1348 static void assert_vblank_disabled(struct drm_crtc *crtc)
1349 {
1350         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1351                 drm_crtc_vblank_put(crtc);
1352 }
1353
1354 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1355                                     enum pipe pipe)
1356 {
1357         u32 val;
1358         bool enabled;
1359
1360         val = I915_READ(PCH_TRANSCONF(pipe));
1361         enabled = !!(val & TRANS_ENABLE);
1362         I915_STATE_WARN(enabled,
1363              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1364              pipe_name(pipe));
1365 }
1366
1367 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1368                             enum pipe pipe, u32 port_sel, u32 val)
1369 {
1370         if ((val & DP_PORT_EN) == 0)
1371                 return false;
1372
1373         if (HAS_PCH_CPT(dev_priv)) {
1374                 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1375                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1376                         return false;
1377         } else if (IS_CHERRYVIEW(dev_priv)) {
1378                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1379                         return false;
1380         } else {
1381                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1382                         return false;
1383         }
1384         return true;
1385 }
1386
1387 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1388                               enum pipe pipe, u32 val)
1389 {
1390         if ((val & SDVO_ENABLE) == 0)
1391                 return false;
1392
1393         if (HAS_PCH_CPT(dev_priv)) {
1394                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1395                         return false;
1396         } else if (IS_CHERRYVIEW(dev_priv)) {
1397                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1398                         return false;
1399         } else {
1400                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1401                         return false;
1402         }
1403         return true;
1404 }
1405
1406 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1407                               enum pipe pipe, u32 val)
1408 {
1409         if ((val & LVDS_PORT_EN) == 0)
1410                 return false;
1411
1412         if (HAS_PCH_CPT(dev_priv)) {
1413                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1414                         return false;
1415         } else {
1416                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1417                         return false;
1418         }
1419         return true;
1420 }
1421
1422 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1423                               enum pipe pipe, u32 val)
1424 {
1425         if ((val & ADPA_DAC_ENABLE) == 0)
1426                 return false;
1427         if (HAS_PCH_CPT(dev_priv)) {
1428                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1429                         return false;
1430         } else {
1431                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1432                         return false;
1433         }
1434         return true;
1435 }
1436
1437 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1438                                    enum pipe pipe, i915_reg_t reg,
1439                                    u32 port_sel)
1440 {
1441         u32 val = I915_READ(reg);
1442         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1443              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1444              i915_mmio_reg_offset(reg), pipe_name(pipe));
1445
1446         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1447              && (val & DP_PIPEB_SELECT),
1448              "IBX PCH dp port still using transcoder B\n");
1449 }
1450
1451 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1452                                      enum pipe pipe, i915_reg_t reg)
1453 {
1454         u32 val = I915_READ(reg);
1455         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1456              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1457              i915_mmio_reg_offset(reg), pipe_name(pipe));
1458
1459         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1460              && (val & SDVO_PIPE_B_SELECT),
1461              "IBX PCH hdmi port still using transcoder B\n");
1462 }
1463
1464 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1465                                       enum pipe pipe)
1466 {
1467         u32 val;
1468
1469         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1470         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1471         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1472
1473         val = I915_READ(PCH_ADPA);
1474         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1475              "PCH VGA enabled on transcoder %c, should be disabled\n",
1476              pipe_name(pipe));
1477
1478         val = I915_READ(PCH_LVDS);
1479         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1480              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1481              pipe_name(pipe));
1482
1483         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1484         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1485         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1486 }
1487
1488 static void _vlv_enable_pll(struct intel_crtc *crtc,
1489                             const struct intel_crtc_state *pipe_config)
1490 {
1491         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1492         enum pipe pipe = crtc->pipe;
1493
1494         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1495         POSTING_READ(DPLL(pipe));
1496         udelay(150);
1497
1498         if (intel_wait_for_register(dev_priv,
1499                                     DPLL(pipe),
1500                                     DPLL_LOCK_VLV,
1501                                     DPLL_LOCK_VLV,
1502                                     1))
1503                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1504 }
1505
1506 static void vlv_enable_pll(struct intel_crtc *crtc,
1507                            const struct intel_crtc_state *pipe_config)
1508 {
1509         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1510         enum pipe pipe = crtc->pipe;
1511
1512         assert_pipe_disabled(dev_priv, pipe);
1513
1514         /* PLL is protected by panel, make sure we can write it */
1515         assert_panel_unlocked(dev_priv, pipe);
1516
1517         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1518                 _vlv_enable_pll(crtc, pipe_config);
1519
1520         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1521         POSTING_READ(DPLL_MD(pipe));
1522 }
1523
1524
1525 static void _chv_enable_pll(struct intel_crtc *crtc,
1526                             const struct intel_crtc_state *pipe_config)
1527 {
1528         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1529         enum pipe pipe = crtc->pipe;
1530         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1531         u32 tmp;
1532
1533         mutex_lock(&dev_priv->sb_lock);
1534
1535         /* Enable back the 10bit clock to display controller */
1536         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1537         tmp |= DPIO_DCLKP_EN;
1538         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1539
1540         mutex_unlock(&dev_priv->sb_lock);
1541
1542         /*
1543          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1544          */
1545         udelay(1);
1546
1547         /* Enable PLL */
1548         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1549
1550         /* Check PLL is locked */
1551         if (intel_wait_for_register(dev_priv,
1552                                     DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1553                                     1))
1554                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1555 }
1556
1557 static void chv_enable_pll(struct intel_crtc *crtc,
1558                            const struct intel_crtc_state *pipe_config)
1559 {
1560         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1561         enum pipe pipe = crtc->pipe;
1562
1563         assert_pipe_disabled(dev_priv, pipe);
1564
1565         /* PLL is protected by panel, make sure we can write it */
1566         assert_panel_unlocked(dev_priv, pipe);
1567
1568         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1569                 _chv_enable_pll(crtc, pipe_config);
1570
1571         if (pipe != PIPE_A) {
1572                 /*
1573                  * WaPixelRepeatModeFixForC0:chv
1574                  *
1575                  * DPLLCMD is AWOL. Use chicken bits to propagate
1576                  * the value from DPLLBMD to either pipe B or C.
1577                  */
1578                 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1579                 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1580                 I915_WRITE(CBR4_VLV, 0);
1581                 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1582
1583                 /*
1584                  * DPLLB VGA mode also seems to cause problems.
1585                  * We should always have it disabled.
1586                  */
1587                 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1588         } else {
1589                 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1590                 POSTING_READ(DPLL_MD(pipe));
1591         }
1592 }
1593
1594 static int intel_num_dvo_pipes(struct drm_i915_private *dev_priv)
1595 {
1596         struct intel_crtc *crtc;
1597         int count = 0;
1598
1599         for_each_intel_crtc(&dev_priv->drm, crtc) {
1600                 count += crtc->base.state->active &&
1601                         intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO);
1602         }
1603
1604         return count;
1605 }
1606
1607 static void i9xx_enable_pll(struct intel_crtc *crtc)
1608 {
1609         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1610         i915_reg_t reg = DPLL(crtc->pipe);
1611         u32 dpll = crtc->config->dpll_hw_state.dpll;
1612
1613         assert_pipe_disabled(dev_priv, crtc->pipe);
1614
1615         /* PLL is protected by panel, make sure we can write it */
1616         if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
1617                 assert_panel_unlocked(dev_priv, crtc->pipe);
1618
1619         /* Enable DVO 2x clock on both PLLs if necessary */
1620         if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev_priv) > 0) {
1621                 /*
1622                  * It appears to be important that we don't enable this
1623                  * for the current pipe before otherwise configuring the
1624                  * PLL. No idea how this should be handled if multiple
1625                  * DVO outputs are enabled simultaneosly.
1626                  */
1627                 dpll |= DPLL_DVO_2X_MODE;
1628                 I915_WRITE(DPLL(!crtc->pipe),
1629                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1630         }
1631
1632         /*
1633          * Apparently we need to have VGA mode enabled prior to changing
1634          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1635          * dividers, even though the register value does change.
1636          */
1637         I915_WRITE(reg, 0);
1638
1639         I915_WRITE(reg, dpll);
1640
1641         /* Wait for the clocks to stabilize. */
1642         POSTING_READ(reg);
1643         udelay(150);
1644
1645         if (INTEL_GEN(dev_priv) >= 4) {
1646                 I915_WRITE(DPLL_MD(crtc->pipe),
1647                            crtc->config->dpll_hw_state.dpll_md);
1648         } else {
1649                 /* The pixel multiplier can only be updated once the
1650                  * DPLL is enabled and the clocks are stable.
1651                  *
1652                  * So write it again.
1653                  */
1654                 I915_WRITE(reg, dpll);
1655         }
1656
1657         /* We do this three times for luck */
1658         I915_WRITE(reg, dpll);
1659         POSTING_READ(reg);
1660         udelay(150); /* wait for warmup */
1661         I915_WRITE(reg, dpll);
1662         POSTING_READ(reg);
1663         udelay(150); /* wait for warmup */
1664         I915_WRITE(reg, dpll);
1665         POSTING_READ(reg);
1666         udelay(150); /* wait for warmup */
1667 }
1668
1669 /**
1670  * i9xx_disable_pll - disable a PLL
1671  * @dev_priv: i915 private structure
1672  * @pipe: pipe PLL to disable
1673  *
1674  * Disable the PLL for @pipe, making sure the pipe is off first.
1675  *
1676  * Note!  This is for pre-ILK only.
1677  */
1678 static void i9xx_disable_pll(struct intel_crtc *crtc)
1679 {
1680         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1681         enum pipe pipe = crtc->pipe;
1682
1683         /* Disable DVO 2x clock on both PLLs if necessary */
1684         if (IS_I830(dev_priv) &&
1685             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
1686             !intel_num_dvo_pipes(dev_priv)) {
1687                 I915_WRITE(DPLL(PIPE_B),
1688                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1689                 I915_WRITE(DPLL(PIPE_A),
1690                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1691         }
1692
1693         /* Don't disable pipe or pipe PLLs if needed */
1694         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1695             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1696                 return;
1697
1698         /* Make sure the pipe isn't still relying on us */
1699         assert_pipe_disabled(dev_priv, pipe);
1700
1701         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1702         POSTING_READ(DPLL(pipe));
1703 }
1704
1705 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1706 {
1707         u32 val;
1708
1709         /* Make sure the pipe isn't still relying on us */
1710         assert_pipe_disabled(dev_priv, pipe);
1711
1712         val = DPLL_INTEGRATED_REF_CLK_VLV |
1713                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1714         if (pipe != PIPE_A)
1715                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1716
1717         I915_WRITE(DPLL(pipe), val);
1718         POSTING_READ(DPLL(pipe));
1719 }
1720
1721 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1722 {
1723         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1724         u32 val;
1725
1726         /* Make sure the pipe isn't still relying on us */
1727         assert_pipe_disabled(dev_priv, pipe);
1728
1729         val = DPLL_SSC_REF_CLK_CHV |
1730                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1731         if (pipe != PIPE_A)
1732                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1733
1734         I915_WRITE(DPLL(pipe), val);
1735         POSTING_READ(DPLL(pipe));
1736
1737         mutex_lock(&dev_priv->sb_lock);
1738
1739         /* Disable 10bit clock to display controller */
1740         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1741         val &= ~DPIO_DCLKP_EN;
1742         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1743
1744         mutex_unlock(&dev_priv->sb_lock);
1745 }
1746
1747 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1748                          struct intel_digital_port *dport,
1749                          unsigned int expected_mask)
1750 {
1751         u32 port_mask;
1752         i915_reg_t dpll_reg;
1753
1754         switch (dport->port) {
1755         case PORT_B:
1756                 port_mask = DPLL_PORTB_READY_MASK;
1757                 dpll_reg = DPLL(0);
1758                 break;
1759         case PORT_C:
1760                 port_mask = DPLL_PORTC_READY_MASK;
1761                 dpll_reg = DPLL(0);
1762                 expected_mask <<= 4;
1763                 break;
1764         case PORT_D:
1765                 port_mask = DPLL_PORTD_READY_MASK;
1766                 dpll_reg = DPIO_PHY_STATUS;
1767                 break;
1768         default:
1769                 BUG();
1770         }
1771
1772         if (intel_wait_for_register(dev_priv,
1773                                     dpll_reg, port_mask, expected_mask,
1774                                     1000))
1775                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1776                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1777 }
1778
1779 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1780                                            enum pipe pipe)
1781 {
1782         struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
1783                                                                 pipe);
1784         i915_reg_t reg;
1785         uint32_t val, pipeconf_val;
1786
1787         /* Make sure PCH DPLL is enabled */
1788         assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1789
1790         /* FDI must be feeding us bits for PCH ports */
1791         assert_fdi_tx_enabled(dev_priv, pipe);
1792         assert_fdi_rx_enabled(dev_priv, pipe);
1793
1794         if (HAS_PCH_CPT(dev_priv)) {
1795                 /* Workaround: Set the timing override bit before enabling the
1796                  * pch transcoder. */
1797                 reg = TRANS_CHICKEN2(pipe);
1798                 val = I915_READ(reg);
1799                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1800                 I915_WRITE(reg, val);
1801         }
1802
1803         reg = PCH_TRANSCONF(pipe);
1804         val = I915_READ(reg);
1805         pipeconf_val = I915_READ(PIPECONF(pipe));
1806
1807         if (HAS_PCH_IBX(dev_priv)) {
1808                 /*
1809                  * Make the BPC in transcoder be consistent with
1810                  * that in pipeconf reg. For HDMI we must use 8bpc
1811                  * here for both 8bpc and 12bpc.
1812                  */
1813                 val &= ~PIPECONF_BPC_MASK;
1814                 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI))
1815                         val |= PIPECONF_8BPC;
1816                 else
1817                         val |= pipeconf_val & PIPECONF_BPC_MASK;
1818         }
1819
1820         val &= ~TRANS_INTERLACE_MASK;
1821         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1822                 if (HAS_PCH_IBX(dev_priv) &&
1823                     intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
1824                         val |= TRANS_LEGACY_INTERLACED_ILK;
1825                 else
1826                         val |= TRANS_INTERLACED;
1827         else
1828                 val |= TRANS_PROGRESSIVE;
1829
1830         I915_WRITE(reg, val | TRANS_ENABLE);
1831         if (intel_wait_for_register(dev_priv,
1832                                     reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1833                                     100))
1834                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1835 }
1836
1837 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1838                                       enum transcoder cpu_transcoder)
1839 {
1840         u32 val, pipeconf_val;
1841
1842         /* FDI must be feeding us bits for PCH ports */
1843         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1844         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1845
1846         /* Workaround: set timing override bit. */
1847         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1848         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1849         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1850
1851         val = TRANS_ENABLE;
1852         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1853
1854         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1855             PIPECONF_INTERLACED_ILK)
1856                 val |= TRANS_INTERLACED;
1857         else
1858                 val |= TRANS_PROGRESSIVE;
1859
1860         I915_WRITE(LPT_TRANSCONF, val);
1861         if (intel_wait_for_register(dev_priv,
1862                                     LPT_TRANSCONF,
1863                                     TRANS_STATE_ENABLE,
1864                                     TRANS_STATE_ENABLE,
1865                                     100))
1866                 DRM_ERROR("Failed to enable PCH transcoder\n");
1867 }
1868
1869 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1870                                             enum pipe pipe)
1871 {
1872         i915_reg_t reg;
1873         uint32_t val;
1874
1875         /* FDI relies on the transcoder */
1876         assert_fdi_tx_disabled(dev_priv, pipe);
1877         assert_fdi_rx_disabled(dev_priv, pipe);
1878
1879         /* Ports must be off as well */
1880         assert_pch_ports_disabled(dev_priv, pipe);
1881
1882         reg = PCH_TRANSCONF(pipe);
1883         val = I915_READ(reg);
1884         val &= ~TRANS_ENABLE;
1885         I915_WRITE(reg, val);
1886         /* wait for PCH transcoder off, transcoder state */
1887         if (intel_wait_for_register(dev_priv,
1888                                     reg, TRANS_STATE_ENABLE, 0,
1889                                     50))
1890                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1891
1892         if (HAS_PCH_CPT(dev_priv)) {
1893                 /* Workaround: Clear the timing override chicken bit again. */
1894                 reg = TRANS_CHICKEN2(pipe);
1895                 val = I915_READ(reg);
1896                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1897                 I915_WRITE(reg, val);
1898         }
1899 }
1900
1901 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1902 {
1903         u32 val;
1904
1905         val = I915_READ(LPT_TRANSCONF);
1906         val &= ~TRANS_ENABLE;
1907         I915_WRITE(LPT_TRANSCONF, val);
1908         /* wait for PCH transcoder off, transcoder state */
1909         if (intel_wait_for_register(dev_priv,
1910                                     LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1911                                     50))
1912                 DRM_ERROR("Failed to disable PCH transcoder\n");
1913
1914         /* Workaround: clear timing override bit. */
1915         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1916         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1917         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1918 }
1919
1920 enum transcoder intel_crtc_pch_transcoder(struct intel_crtc *crtc)
1921 {
1922         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1923
1924         WARN_ON(!crtc->config->has_pch_encoder);
1925
1926         if (HAS_PCH_LPT(dev_priv))
1927                 return TRANSCODER_A;
1928         else
1929                 return (enum transcoder) crtc->pipe;
1930 }
1931
1932 /**
1933  * intel_enable_pipe - enable a pipe, asserting requirements
1934  * @crtc: crtc responsible for the pipe
1935  *
1936  * Enable @crtc's pipe, making sure that various hardware specific requirements
1937  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1938  */
1939 static void intel_enable_pipe(struct intel_crtc *crtc)
1940 {
1941         struct drm_device *dev = crtc->base.dev;
1942         struct drm_i915_private *dev_priv = to_i915(dev);
1943         enum pipe pipe = crtc->pipe;
1944         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1945         i915_reg_t reg;
1946         u32 val;
1947
1948         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1949
1950         assert_planes_disabled(dev_priv, pipe);
1951         assert_cursor_disabled(dev_priv, pipe);
1952         assert_sprites_disabled(dev_priv, pipe);
1953
1954         /*
1955          * A pipe without a PLL won't actually be able to drive bits from
1956          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1957          * need the check.
1958          */
1959         if (HAS_GMCH_DISPLAY(dev_priv)) {
1960                 if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI))
1961                         assert_dsi_pll_enabled(dev_priv);
1962                 else
1963                         assert_pll_enabled(dev_priv, pipe);
1964         } else {
1965                 if (crtc->config->has_pch_encoder) {
1966                         /* if driving the PCH, we need FDI enabled */
1967                         assert_fdi_rx_pll_enabled(dev_priv,
1968                                                   (enum pipe) intel_crtc_pch_transcoder(crtc));
1969                         assert_fdi_tx_pll_enabled(dev_priv,
1970                                                   (enum pipe) cpu_transcoder);
1971                 }
1972                 /* FIXME: assert CPU port conditions for SNB+ */
1973         }
1974
1975         reg = PIPECONF(cpu_transcoder);
1976         val = I915_READ(reg);
1977         if (val & PIPECONF_ENABLE) {
1978                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1979                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
1980                 return;
1981         }
1982
1983         I915_WRITE(reg, val | PIPECONF_ENABLE);
1984         POSTING_READ(reg);
1985
1986         /*
1987          * Until the pipe starts DSL will read as 0, which would cause
1988          * an apparent vblank timestamp jump, which messes up also the
1989          * frame count when it's derived from the timestamps. So let's
1990          * wait for the pipe to start properly before we call
1991          * drm_crtc_vblank_on()
1992          */
1993         if (dev->max_vblank_count == 0 &&
1994             wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
1995                 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
1996 }
1997
1998 /**
1999  * intel_disable_pipe - disable a pipe, asserting requirements
2000  * @crtc: crtc whose pipes is to be disabled
2001  *
2002  * Disable the pipe of @crtc, making sure that various hardware
2003  * specific requirements are met, if applicable, e.g. plane
2004  * disabled, panel fitter off, etc.
2005  *
2006  * Will wait until the pipe has shut down before returning.
2007  */
2008 static void intel_disable_pipe(struct intel_crtc *crtc)
2009 {
2010         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2011         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2012         enum pipe pipe = crtc->pipe;
2013         i915_reg_t reg;
2014         u32 val;
2015
2016         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2017
2018         /*
2019          * Make sure planes won't keep trying to pump pixels to us,
2020          * or we might hang the display.
2021          */
2022         assert_planes_disabled(dev_priv, pipe);
2023         assert_cursor_disabled(dev_priv, pipe);
2024         assert_sprites_disabled(dev_priv, pipe);
2025
2026         reg = PIPECONF(cpu_transcoder);
2027         val = I915_READ(reg);
2028         if ((val & PIPECONF_ENABLE) == 0)
2029                 return;
2030
2031         /*
2032          * Double wide has implications for planes
2033          * so best keep it disabled when not needed.
2034          */
2035         if (crtc->config->double_wide)
2036                 val &= ~PIPECONF_DOUBLE_WIDE;
2037
2038         /* Don't disable pipe or pipe PLLs if needed */
2039         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2040             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2041                 val &= ~PIPECONF_ENABLE;
2042
2043         I915_WRITE(reg, val);
2044         if ((val & PIPECONF_ENABLE) == 0)
2045                 intel_wait_for_pipe_off(crtc);
2046 }
2047
2048 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
2049 {
2050         return IS_GEN2(dev_priv) ? 2048 : 4096;
2051 }
2052
2053 static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv,
2054                                            uint64_t fb_modifier, unsigned int cpp)
2055 {
2056         switch (fb_modifier) {
2057         case DRM_FORMAT_MOD_NONE:
2058                 return cpp;
2059         case I915_FORMAT_MOD_X_TILED:
2060                 if (IS_GEN2(dev_priv))
2061                         return 128;
2062                 else
2063                         return 512;
2064         case I915_FORMAT_MOD_Y_TILED:
2065                 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2066                         return 128;
2067                 else
2068                         return 512;
2069         case I915_FORMAT_MOD_Yf_TILED:
2070                 switch (cpp) {
2071                 case 1:
2072                         return 64;
2073                 case 2:
2074                 case 4:
2075                         return 128;
2076                 case 8:
2077                 case 16:
2078                         return 256;
2079                 default:
2080                         MISSING_CASE(cpp);
2081                         return cpp;
2082                 }
2083                 break;
2084         default:
2085                 MISSING_CASE(fb_modifier);
2086                 return cpp;
2087         }
2088 }
2089
2090 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
2091                                uint64_t fb_modifier, unsigned int cpp)
2092 {
2093         if (fb_modifier == DRM_FORMAT_MOD_NONE)
2094                 return 1;
2095         else
2096                 return intel_tile_size(dev_priv) /
2097                         intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2098 }
2099
2100 /* Return the tile dimensions in pixel units */
2101 static void intel_tile_dims(const struct drm_i915_private *dev_priv,
2102                             unsigned int *tile_width,
2103                             unsigned int *tile_height,
2104                             uint64_t fb_modifier,
2105                             unsigned int cpp)
2106 {
2107         unsigned int tile_width_bytes =
2108                 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2109
2110         *tile_width = tile_width_bytes / cpp;
2111         *tile_height = intel_tile_size(dev_priv) / tile_width_bytes;
2112 }
2113
2114 unsigned int
2115 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2116                       uint32_t pixel_format, uint64_t fb_modifier)
2117 {
2118         unsigned int cpp = drm_format_plane_cpp(pixel_format, 0);
2119         unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp);
2120
2121         return ALIGN(height, tile_height);
2122 }
2123
2124 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2125 {
2126         unsigned int size = 0;
2127         int i;
2128
2129         for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2130                 size += rot_info->plane[i].width * rot_info->plane[i].height;
2131
2132         return size;
2133 }
2134
2135 static void
2136 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2137                         const struct drm_framebuffer *fb,
2138                         unsigned int rotation)
2139 {
2140         if (drm_rotation_90_or_270(rotation)) {
2141                 *view = i915_ggtt_view_rotated;
2142                 view->params.rotated = to_intel_framebuffer(fb)->rot_info;
2143         } else {
2144                 *view = i915_ggtt_view_normal;
2145         }
2146 }
2147
2148 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2149 {
2150         if (INTEL_INFO(dev_priv)->gen >= 9)
2151                 return 256 * 1024;
2152         else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2153                  IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2154                 return 128 * 1024;
2155         else if (INTEL_INFO(dev_priv)->gen >= 4)
2156                 return 4 * 1024;
2157         else
2158                 return 0;
2159 }
2160
2161 static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv,
2162                                          uint64_t fb_modifier)
2163 {
2164         switch (fb_modifier) {
2165         case DRM_FORMAT_MOD_NONE:
2166                 return intel_linear_alignment(dev_priv);
2167         case I915_FORMAT_MOD_X_TILED:
2168                 if (INTEL_INFO(dev_priv)->gen >= 9)
2169                         return 256 * 1024;
2170                 return 0;
2171         case I915_FORMAT_MOD_Y_TILED:
2172         case I915_FORMAT_MOD_Yf_TILED:
2173                 return 1 * 1024 * 1024;
2174         default:
2175                 MISSING_CASE(fb_modifier);
2176                 return 0;
2177         }
2178 }
2179
2180 struct i915_vma *
2181 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2182 {
2183         struct drm_device *dev = fb->dev;
2184         struct drm_i915_private *dev_priv = to_i915(dev);
2185         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2186         struct i915_ggtt_view view;
2187         struct i915_vma *vma;
2188         u32 alignment;
2189
2190         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2191
2192         alignment = intel_surf_alignment(dev_priv, fb->modifier);
2193
2194         intel_fill_fb_ggtt_view(&view, fb, rotation);
2195
2196         /* Note that the w/a also requires 64 PTE of padding following the
2197          * bo. We currently fill all unused PTE with the shadow page and so
2198          * we should always have valid PTE following the scanout preventing
2199          * the VT-d warning.
2200          */
2201         if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2202                 alignment = 256 * 1024;
2203
2204         /*
2205          * Global gtt pte registers are special registers which actually forward
2206          * writes to a chunk of system memory. Which means that there is no risk
2207          * that the register values disappear as soon as we call
2208          * intel_runtime_pm_put(), so it is correct to wrap only the
2209          * pin/unpin/fence and not more.
2210          */
2211         intel_runtime_pm_get(dev_priv);
2212
2213         vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view);
2214         if (IS_ERR(vma))
2215                 goto err;
2216
2217         if (i915_vma_is_map_and_fenceable(vma)) {
2218                 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2219                  * fence, whereas 965+ only requires a fence if using
2220                  * framebuffer compression.  For simplicity, we always, when
2221                  * possible, install a fence as the cost is not that onerous.
2222                  *
2223                  * If we fail to fence the tiled scanout, then either the
2224                  * modeset will reject the change (which is highly unlikely as
2225                  * the affected systems, all but one, do not have unmappable
2226                  * space) or we will not be able to enable full powersaving
2227                  * techniques (also likely not to apply due to various limits
2228                  * FBC and the like impose on the size of the buffer, which
2229                  * presumably we violated anyway with this unmappable buffer).
2230                  * Anyway, it is presumably better to stumble onwards with
2231                  * something and try to run the system in a "less than optimal"
2232                  * mode that matches the user configuration.
2233                  */
2234                 if (i915_vma_get_fence(vma) == 0)
2235                         i915_vma_pin_fence(vma);
2236         }
2237
2238 err:
2239         intel_runtime_pm_put(dev_priv);
2240         return vma;
2241 }
2242
2243 void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2244 {
2245         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2246         struct i915_ggtt_view view;
2247         struct i915_vma *vma;
2248
2249         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2250
2251         intel_fill_fb_ggtt_view(&view, fb, rotation);
2252         vma = i915_gem_object_to_ggtt(obj, &view);
2253
2254         i915_vma_unpin_fence(vma);
2255         i915_gem_object_unpin_from_display_plane(vma);
2256 }
2257
2258 static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane,
2259                           unsigned int rotation)
2260 {
2261         if (drm_rotation_90_or_270(rotation))
2262                 return to_intel_framebuffer(fb)->rotated[plane].pitch;
2263         else
2264                 return fb->pitches[plane];
2265 }
2266
2267 /*
2268  * Convert the x/y offsets into a linear offset.
2269  * Only valid with 0/180 degree rotation, which is fine since linear
2270  * offset is only used with linear buffers on pre-hsw and tiled buffers
2271  * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2272  */
2273 u32 intel_fb_xy_to_linear(int x, int y,
2274                           const struct intel_plane_state *state,
2275                           int plane)
2276 {
2277         const struct drm_framebuffer *fb = state->base.fb;
2278         unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2279         unsigned int pitch = fb->pitches[plane];
2280
2281         return y * pitch + x * cpp;
2282 }
2283
2284 /*
2285  * Add the x/y offsets derived from fb->offsets[] to the user
2286  * specified plane src x/y offsets. The resulting x/y offsets
2287  * specify the start of scanout from the beginning of the gtt mapping.
2288  */
2289 void intel_add_fb_offsets(int *x, int *y,
2290                           const struct intel_plane_state *state,
2291                           int plane)
2292
2293 {
2294         const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
2295         unsigned int rotation = state->base.rotation;
2296
2297         if (drm_rotation_90_or_270(rotation)) {
2298                 *x += intel_fb->rotated[plane].x;
2299                 *y += intel_fb->rotated[plane].y;
2300         } else {
2301                 *x += intel_fb->normal[plane].x;
2302                 *y += intel_fb->normal[plane].y;
2303         }
2304 }
2305
2306 /*
2307  * Input tile dimensions and pitch must already be
2308  * rotated to match x and y, and in pixel units.
2309  */
2310 static u32 _intel_adjust_tile_offset(int *x, int *y,
2311                                      unsigned int tile_width,
2312                                      unsigned int tile_height,
2313                                      unsigned int tile_size,
2314                                      unsigned int pitch_tiles,
2315                                      u32 old_offset,
2316                                      u32 new_offset)
2317 {
2318         unsigned int pitch_pixels = pitch_tiles * tile_width;
2319         unsigned int tiles;
2320
2321         WARN_ON(old_offset & (tile_size - 1));
2322         WARN_ON(new_offset & (tile_size - 1));
2323         WARN_ON(new_offset > old_offset);
2324
2325         tiles = (old_offset - new_offset) / tile_size;
2326
2327         *y += tiles / pitch_tiles * tile_height;
2328         *x += tiles % pitch_tiles * tile_width;
2329
2330         /* minimize x in case it got needlessly big */
2331         *y += *x / pitch_pixels * tile_height;
2332         *x %= pitch_pixels;
2333
2334         return new_offset;
2335 }
2336
2337 /*
2338  * Adjust the tile offset by moving the difference into
2339  * the x/y offsets.
2340  */
2341 static u32 intel_adjust_tile_offset(int *x, int *y,
2342                                     const struct intel_plane_state *state, int plane,
2343                                     u32 old_offset, u32 new_offset)
2344 {
2345         const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2346         const struct drm_framebuffer *fb = state->base.fb;
2347         unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2348         unsigned int rotation = state->base.rotation;
2349         unsigned int pitch = intel_fb_pitch(fb, plane, rotation);
2350
2351         WARN_ON(new_offset > old_offset);
2352
2353         if (fb->modifier != DRM_FORMAT_MOD_NONE) {
2354                 unsigned int tile_size, tile_width, tile_height;
2355                 unsigned int pitch_tiles;
2356
2357                 tile_size = intel_tile_size(dev_priv);
2358                 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2359                                 fb->modifier, cpp);
2360
2361                 if (drm_rotation_90_or_270(rotation)) {
2362                         pitch_tiles = pitch / tile_height;
2363                         swap(tile_width, tile_height);
2364                 } else {
2365                         pitch_tiles = pitch / (tile_width * cpp);
2366                 }
2367
2368                 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2369                                           tile_size, pitch_tiles,
2370                                           old_offset, new_offset);
2371         } else {
2372                 old_offset += *y * pitch + *x * cpp;
2373
2374                 *y = (old_offset - new_offset) / pitch;
2375                 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2376         }
2377
2378         return new_offset;
2379 }
2380
2381 /*
2382  * Computes the linear offset to the base tile and adjusts
2383  * x, y. bytes per pixel is assumed to be a power-of-two.
2384  *
2385  * In the 90/270 rotated case, x and y are assumed
2386  * to be already rotated to match the rotated GTT view, and
2387  * pitch is the tile_height aligned framebuffer height.
2388  *
2389  * This function is used when computing the derived information
2390  * under intel_framebuffer, so using any of that information
2391  * here is not allowed. Anything under drm_framebuffer can be
2392  * used. This is why the user has to pass in the pitch since it
2393  * is specified in the rotated orientation.
2394  */
2395 static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv,
2396                                       int *x, int *y,
2397                                       const struct drm_framebuffer *fb, int plane,
2398                                       unsigned int pitch,
2399                                       unsigned int rotation,
2400                                       u32 alignment)
2401 {
2402         uint64_t fb_modifier = fb->modifier;
2403         unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2404         u32 offset, offset_aligned;
2405
2406         if (alignment)
2407                 alignment--;
2408
2409         if (fb_modifier != DRM_FORMAT_MOD_NONE) {
2410                 unsigned int tile_size, tile_width, tile_height;
2411                 unsigned int tile_rows, tiles, pitch_tiles;
2412
2413                 tile_size = intel_tile_size(dev_priv);
2414                 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2415                                 fb_modifier, cpp);
2416
2417                 if (drm_rotation_90_or_270(rotation)) {
2418                         pitch_tiles = pitch / tile_height;
2419                         swap(tile_width, tile_height);
2420                 } else {
2421                         pitch_tiles = pitch / (tile_width * cpp);
2422                 }
2423
2424                 tile_rows = *y / tile_height;
2425                 *y %= tile_height;
2426
2427                 tiles = *x / tile_width;
2428                 *x %= tile_width;
2429
2430                 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2431                 offset_aligned = offset & ~alignment;
2432
2433                 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2434                                           tile_size, pitch_tiles,
2435                                           offset, offset_aligned);
2436         } else {
2437                 offset = *y * pitch + *x * cpp;
2438                 offset_aligned = offset & ~alignment;
2439
2440                 *y = (offset & alignment) / pitch;
2441                 *x = ((offset & alignment) - *y * pitch) / cpp;
2442         }
2443
2444         return offset_aligned;
2445 }
2446
2447 u32 intel_compute_tile_offset(int *x, int *y,
2448                               const struct intel_plane_state *state,
2449                               int plane)
2450 {
2451         const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2452         const struct drm_framebuffer *fb = state->base.fb;
2453         unsigned int rotation = state->base.rotation;
2454         int pitch = intel_fb_pitch(fb, plane, rotation);
2455         u32 alignment;
2456
2457         /* AUX_DIST needs only 4K alignment */
2458         if (fb->pixel_format == DRM_FORMAT_NV12 && plane == 1)
2459                 alignment = 4096;
2460         else
2461                 alignment = intel_surf_alignment(dev_priv, fb->modifier);
2462
2463         return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch,
2464                                           rotation, alignment);
2465 }
2466
2467 /* Convert the fb->offset[] linear offset into x/y offsets */
2468 static void intel_fb_offset_to_xy(int *x, int *y,
2469                                   const struct drm_framebuffer *fb, int plane)
2470 {
2471         unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2472         unsigned int pitch = fb->pitches[plane];
2473         u32 linear_offset = fb->offsets[plane];
2474
2475         *y = linear_offset / pitch;
2476         *x = linear_offset % pitch / cpp;
2477 }
2478
2479 static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier)
2480 {
2481         switch (fb_modifier) {
2482         case I915_FORMAT_MOD_X_TILED:
2483                 return I915_TILING_X;
2484         case I915_FORMAT_MOD_Y_TILED:
2485                 return I915_TILING_Y;
2486         default:
2487                 return I915_TILING_NONE;
2488         }
2489 }
2490
2491 static int
2492 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2493                    struct drm_framebuffer *fb)
2494 {
2495         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2496         struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2497         u32 gtt_offset_rotated = 0;
2498         unsigned int max_size = 0;
2499         uint32_t format = fb->pixel_format;
2500         int i, num_planes = drm_format_num_planes(format);
2501         unsigned int tile_size = intel_tile_size(dev_priv);
2502
2503         for (i = 0; i < num_planes; i++) {
2504                 unsigned int width, height;
2505                 unsigned int cpp, size;
2506                 u32 offset;
2507                 int x, y;
2508
2509                 cpp = drm_format_plane_cpp(format, i);
2510                 width = drm_format_plane_width(fb->width, format, i);
2511                 height = drm_format_plane_height(fb->height, format, i);
2512
2513                 intel_fb_offset_to_xy(&x, &y, fb, i);
2514
2515                 /*
2516                  * The fence (if used) is aligned to the start of the object
2517                  * so having the framebuffer wrap around across the edge of the
2518                  * fenced region doesn't really work. We have no API to configure
2519                  * the fence start offset within the object (nor could we probably
2520                  * on gen2/3). So it's just easier if we just require that the
2521                  * fb layout agrees with the fence layout. We already check that the
2522                  * fb stride matches the fence stride elsewhere.
2523                  */
2524                 if (i915_gem_object_is_tiled(intel_fb->obj) &&
2525                     (x + width) * cpp > fb->pitches[i]) {
2526                         DRM_DEBUG("bad fb plane %d offset: 0x%x\n",
2527                                   i, fb->offsets[i]);
2528                         return -EINVAL;
2529                 }
2530
2531                 /*
2532                  * First pixel of the framebuffer from
2533                  * the start of the normal gtt mapping.
2534                  */
2535                 intel_fb->normal[i].x = x;
2536                 intel_fb->normal[i].y = y;
2537
2538                 offset = _intel_compute_tile_offset(dev_priv, &x, &y,
2539                                                     fb, 0, fb->pitches[i],
2540                                                     DRM_ROTATE_0, tile_size);
2541                 offset /= tile_size;
2542
2543                 if (fb->modifier != DRM_FORMAT_MOD_NONE) {
2544                         unsigned int tile_width, tile_height;
2545                         unsigned int pitch_tiles;
2546                         struct drm_rect r;
2547
2548                         intel_tile_dims(dev_priv, &tile_width, &tile_height,
2549                                         fb->modifier, cpp);
2550
2551                         rot_info->plane[i].offset = offset;
2552                         rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2553                         rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2554                         rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2555
2556                         intel_fb->rotated[i].pitch =
2557                                 rot_info->plane[i].height * tile_height;
2558
2559                         /* how many tiles does this plane need */
2560                         size = rot_info->plane[i].stride * rot_info->plane[i].height;
2561                         /*
2562                          * If the plane isn't horizontally tile aligned,
2563                          * we need one more tile.
2564                          */
2565                         if (x != 0)
2566                                 size++;
2567
2568                         /* rotate the x/y offsets to match the GTT view */
2569                         r.x1 = x;
2570                         r.y1 = y;
2571                         r.x2 = x + width;
2572                         r.y2 = y + height;
2573                         drm_rect_rotate(&r,
2574                                         rot_info->plane[i].width * tile_width,
2575                                         rot_info->plane[i].height * tile_height,
2576                                         DRM_ROTATE_270);
2577                         x = r.x1;
2578                         y = r.y1;
2579
2580                         /* rotate the tile dimensions to match the GTT view */
2581                         pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2582                         swap(tile_width, tile_height);
2583
2584                         /*
2585                          * We only keep the x/y offsets, so push all of the
2586                          * gtt offset into the x/y offsets.
2587                          */
2588                         _intel_adjust_tile_offset(&x, &y, tile_size,
2589                                                   tile_width, tile_height, pitch_tiles,
2590                                                   gtt_offset_rotated * tile_size, 0);
2591
2592                         gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2593
2594                         /*
2595                          * First pixel of the framebuffer from
2596                          * the start of the rotated gtt mapping.
2597                          */
2598                         intel_fb->rotated[i].x = x;
2599                         intel_fb->rotated[i].y = y;
2600                 } else {
2601                         size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2602                                             x * cpp, tile_size);
2603                 }
2604
2605                 /* how many tiles in total needed in the bo */
2606                 max_size = max(max_size, offset + size);
2607         }
2608
2609         if (max_size * tile_size > to_intel_framebuffer(fb)->obj->base.size) {
2610                 DRM_DEBUG("fb too big for bo (need %u bytes, have %zu bytes)\n",
2611                           max_size * tile_size, to_intel_framebuffer(fb)->obj->base.size);
2612                 return -EINVAL;
2613         }
2614
2615         return 0;
2616 }
2617
2618 static int i9xx_format_to_fourcc(int format)
2619 {
2620         switch (format) {
2621         case DISPPLANE_8BPP:
2622                 return DRM_FORMAT_C8;
2623         case DISPPLANE_BGRX555:
2624                 return DRM_FORMAT_XRGB1555;
2625         case DISPPLANE_BGRX565:
2626                 return DRM_FORMAT_RGB565;
2627         default:
2628         case DISPPLANE_BGRX888:
2629                 return DRM_FORMAT_XRGB8888;
2630         case DISPPLANE_RGBX888:
2631                 return DRM_FORMAT_XBGR8888;
2632         case DISPPLANE_BGRX101010:
2633                 return DRM_FORMAT_XRGB2101010;
2634         case DISPPLANE_RGBX101010:
2635                 return DRM_FORMAT_XBGR2101010;
2636         }
2637 }
2638
2639 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2640 {
2641         switch (format) {
2642         case PLANE_CTL_FORMAT_RGB_565:
2643                 return DRM_FORMAT_RGB565;
2644         default:
2645         case PLANE_CTL_FORMAT_XRGB_8888:
2646                 if (rgb_order) {
2647                         if (alpha)
2648                                 return DRM_FORMAT_ABGR8888;
2649                         else
2650                                 return DRM_FORMAT_XBGR8888;
2651                 } else {
2652                         if (alpha)
2653                                 return DRM_FORMAT_ARGB8888;
2654                         else
2655                                 return DRM_FORMAT_XRGB8888;
2656                 }
2657         case PLANE_CTL_FORMAT_XRGB_2101010:
2658                 if (rgb_order)
2659                         return DRM_FORMAT_XBGR2101010;
2660                 else
2661                         return DRM_FORMAT_XRGB2101010;
2662         }
2663 }
2664
2665 static bool
2666 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2667                               struct intel_initial_plane_config *plane_config)
2668 {
2669         struct drm_device *dev = crtc->base.dev;
2670         struct drm_i915_private *dev_priv = to_i915(dev);
2671         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2672         struct drm_i915_gem_object *obj = NULL;
2673         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2674         struct drm_framebuffer *fb = &plane_config->fb->base;
2675         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2676         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2677                                     PAGE_SIZE);
2678
2679         size_aligned -= base_aligned;
2680
2681         if (plane_config->size == 0)
2682                 return false;
2683
2684         /* If the FB is too big, just don't use it since fbdev is not very
2685          * important and we should probably use that space with FBC or other
2686          * features. */
2687         if (size_aligned * 2 > ggtt->stolen_usable_size)
2688                 return false;
2689
2690         mutex_lock(&dev->struct_mutex);
2691
2692         obj = i915_gem_object_create_stolen_for_preallocated(dev,
2693                                                              base_aligned,
2694                                                              base_aligned,
2695                                                              size_aligned);
2696         if (!obj) {
2697                 mutex_unlock(&dev->struct_mutex);
2698                 return false;
2699         }
2700
2701         if (plane_config->tiling == I915_TILING_X)
2702                 obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X;
2703
2704         mode_cmd.pixel_format = fb->pixel_format;
2705         mode_cmd.width = fb->width;
2706         mode_cmd.height = fb->height;
2707         mode_cmd.pitches[0] = fb->pitches[0];
2708         mode_cmd.modifier[0] = fb->modifier;
2709         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2710
2711         if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2712                                    &mode_cmd, obj)) {
2713                 DRM_DEBUG_KMS("intel fb init failed\n");
2714                 goto out_unref_obj;
2715         }
2716
2717         mutex_unlock(&dev->struct_mutex);
2718
2719         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2720         return true;
2721
2722 out_unref_obj:
2723         i915_gem_object_put(obj);
2724         mutex_unlock(&dev->struct_mutex);
2725         return false;
2726 }
2727
2728 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2729 static void
2730 update_state_fb(struct drm_plane *plane)
2731 {
2732         if (plane->fb == plane->state->fb)
2733                 return;
2734
2735         if (plane->state->fb)
2736                 drm_framebuffer_unreference(plane->state->fb);
2737         plane->state->fb = plane->fb;
2738         if (plane->state->fb)
2739                 drm_framebuffer_reference(plane->state->fb);
2740 }
2741
2742 static void
2743 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2744                              struct intel_initial_plane_config *plane_config)
2745 {
2746         struct drm_device *dev = intel_crtc->base.dev;
2747         struct drm_i915_private *dev_priv = to_i915(dev);
2748         struct drm_crtc *c;
2749         struct intel_crtc *i;
2750         struct drm_i915_gem_object *obj;
2751         struct drm_plane *primary = intel_crtc->base.primary;
2752         struct drm_plane_state *plane_state = primary->state;
2753         struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2754         struct intel_plane *intel_plane = to_intel_plane(primary);
2755         struct intel_plane_state *intel_state =
2756                 to_intel_plane_state(plane_state);
2757         struct drm_framebuffer *fb;
2758
2759         if (!plane_config->fb)
2760                 return;
2761
2762         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2763                 fb = &plane_config->fb->base;
2764                 goto valid_fb;
2765         }
2766
2767         kfree(plane_config->fb);
2768
2769         /*
2770          * Failed to alloc the obj, check to see if we should share
2771          * an fb with another CRTC instead
2772          */
2773         for_each_crtc(dev, c) {
2774                 i = to_intel_crtc(c);
2775
2776                 if (c == &intel_crtc->base)
2777                         continue;
2778
2779                 if (!i->active)
2780                         continue;
2781
2782                 fb = c->primary->fb;
2783                 if (!fb)
2784                         continue;
2785
2786                 obj = intel_fb_obj(fb);
2787                 if (i915_gem_object_ggtt_offset(obj, NULL) == plane_config->base) {
2788                         drm_framebuffer_reference(fb);
2789                         goto valid_fb;
2790                 }
2791         }
2792
2793         /*
2794          * We've failed to reconstruct the BIOS FB.  Current display state
2795          * indicates that the primary plane is visible, but has a NULL FB,
2796          * which will lead to problems later if we don't fix it up.  The
2797          * simplest solution is to just disable the primary plane now and
2798          * pretend the BIOS never had it enabled.
2799          */
2800         to_intel_plane_state(plane_state)->base.visible = false;
2801         crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
2802         intel_pre_disable_primary_noatomic(&intel_crtc->base);
2803         intel_plane->disable_plane(primary, &intel_crtc->base);
2804
2805         return;
2806
2807 valid_fb:
2808         plane_state->src_x = 0;
2809         plane_state->src_y = 0;
2810         plane_state->src_w = fb->width << 16;
2811         plane_state->src_h = fb->height << 16;
2812
2813         plane_state->crtc_x = 0;
2814         plane_state->crtc_y = 0;
2815         plane_state->crtc_w = fb->width;
2816         plane_state->crtc_h = fb->height;
2817
2818         intel_state->base.src = drm_plane_state_src(plane_state);
2819         intel_state->base.dst = drm_plane_state_dest(plane_state);
2820
2821         obj = intel_fb_obj(fb);
2822         if (i915_gem_object_is_tiled(obj))
2823                 dev_priv->preserve_bios_swizzle = true;
2824
2825         drm_framebuffer_reference(fb);
2826         primary->fb = primary->state->fb = fb;
2827         primary->crtc = primary->state->crtc = &intel_crtc->base;
2828         intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2829         atomic_or(to_intel_plane(primary)->frontbuffer_bit,
2830                   &obj->frontbuffer_bits);
2831 }
2832
2833 static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane,
2834                                unsigned int rotation)
2835 {
2836         int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2837
2838         switch (fb->modifier) {
2839         case DRM_FORMAT_MOD_NONE:
2840         case I915_FORMAT_MOD_X_TILED:
2841                 switch (cpp) {
2842                 case 8:
2843                         return 4096;
2844                 case 4:
2845                 case 2:
2846                 case 1:
2847                         return 8192;
2848                 default:
2849                         MISSING_CASE(cpp);
2850                         break;
2851                 }
2852                 break;
2853         case I915_FORMAT_MOD_Y_TILED:
2854         case I915_FORMAT_MOD_Yf_TILED:
2855                 switch (cpp) {
2856                 case 8:
2857                         return 2048;
2858                 case 4:
2859                         return 4096;
2860                 case 2:
2861                 case 1:
2862                         return 8192;
2863                 default:
2864                         MISSING_CASE(cpp);
2865                         break;
2866                 }
2867                 break;
2868         default:
2869                 MISSING_CASE(fb->modifier);
2870         }
2871
2872         return 2048;
2873 }
2874
2875 static int skl_check_main_surface(struct intel_plane_state *plane_state)
2876 {
2877         const struct drm_i915_private *dev_priv = to_i915(plane_state->base.plane->dev);
2878         const struct drm_framebuffer *fb = plane_state->base.fb;
2879         unsigned int rotation = plane_state->base.rotation;
2880         int x = plane_state->base.src.x1 >> 16;
2881         int y = plane_state->base.src.y1 >> 16;
2882         int w = drm_rect_width(&plane_state->base.src) >> 16;
2883         int h = drm_rect_height(&plane_state->base.src) >> 16;
2884         int max_width = skl_max_plane_width(fb, 0, rotation);
2885         int max_height = 4096;
2886         u32 alignment, offset, aux_offset = plane_state->aux.offset;
2887
2888         if (w > max_width || h > max_height) {
2889                 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
2890                               w, h, max_width, max_height);
2891                 return -EINVAL;
2892         }
2893
2894         intel_add_fb_offsets(&x, &y, plane_state, 0);
2895         offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
2896
2897         alignment = intel_surf_alignment(dev_priv, fb->modifier);
2898
2899         /*
2900          * AUX surface offset is specified as the distance from the
2901          * main surface offset, and it must be non-negative. Make
2902          * sure that is what we will get.
2903          */
2904         if (offset > aux_offset)
2905                 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2906                                                   offset, aux_offset & ~(alignment - 1));
2907
2908         /*
2909          * When using an X-tiled surface, the plane blows up
2910          * if the x offset + width exceed the stride.
2911          *
2912          * TODO: linear and Y-tiled seem fine, Yf untested,
2913          */
2914         if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
2915                 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2916
2917                 while ((x + w) * cpp > fb->pitches[0]) {
2918                         if (offset == 0) {
2919                                 DRM_DEBUG_KMS("Unable to find suitable display surface offset\n");
2920                                 return -EINVAL;
2921                         }
2922
2923                         offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2924                                                           offset, offset - alignment);
2925                 }
2926         }
2927
2928         plane_state->main.offset = offset;
2929         plane_state->main.x = x;
2930         plane_state->main.y = y;
2931
2932         return 0;
2933 }
2934
2935 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
2936 {
2937         const struct drm_framebuffer *fb = plane_state->base.fb;
2938         unsigned int rotation = plane_state->base.rotation;
2939         int max_width = skl_max_plane_width(fb, 1, rotation);
2940         int max_height = 4096;
2941         int x = plane_state->base.src.x1 >> 17;
2942         int y = plane_state->base.src.y1 >> 17;
2943         int w = drm_rect_width(&plane_state->base.src) >> 17;
2944         int h = drm_rect_height(&plane_state->base.src) >> 17;
2945         u32 offset;
2946
2947         intel_add_fb_offsets(&x, &y, plane_state, 1);
2948         offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
2949
2950         /* FIXME not quite sure how/if these apply to the chroma plane */
2951         if (w > max_width || h > max_height) {
2952                 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
2953                               w, h, max_width, max_height);
2954                 return -EINVAL;
2955         }
2956
2957         plane_state->aux.offset = offset;
2958         plane_state->aux.x = x;
2959         plane_state->aux.y = y;
2960
2961         return 0;
2962 }
2963
2964 int skl_check_plane_surface(struct intel_plane_state *plane_state)
2965 {
2966         const struct drm_framebuffer *fb = plane_state->base.fb;
2967         unsigned int rotation = plane_state->base.rotation;
2968         int ret;
2969
2970         if (!plane_state->base.visible)
2971                 return 0;
2972
2973         /* Rotate src coordinates to match rotated GTT view */
2974         if (drm_rotation_90_or_270(rotation))
2975                 drm_rect_rotate(&plane_state->base.src,
2976                                 fb->width << 16, fb->height << 16,
2977                                 DRM_ROTATE_270);
2978
2979         /*
2980          * Handle the AUX surface first since
2981          * the main surface setup depends on it.
2982          */
2983         if (fb->pixel_format == DRM_FORMAT_NV12) {
2984                 ret = skl_check_nv12_aux_surface(plane_state);
2985                 if (ret)
2986                         return ret;
2987         } else {
2988                 plane_state->aux.offset = ~0xfff;
2989                 plane_state->aux.x = 0;
2990                 plane_state->aux.y = 0;
2991         }
2992
2993         ret = skl_check_main_surface(plane_state);
2994         if (ret)
2995                 return ret;
2996
2997         return 0;
2998 }
2999
3000 static void i9xx_update_primary_plane(struct drm_plane *primary,
3001                                       const struct intel_crtc_state *crtc_state,
3002                                       const struct intel_plane_state *plane_state)
3003 {
3004         struct drm_i915_private *dev_priv = to_i915(primary->dev);
3005         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3006         struct drm_framebuffer *fb = plane_state->base.fb;
3007         int plane = intel_crtc->plane;
3008         u32 linear_offset;
3009         u32 dspcntr;
3010         i915_reg_t reg = DSPCNTR(plane);
3011         unsigned int rotation = plane_state->base.rotation;
3012         int x = plane_state->base.src.x1 >> 16;
3013         int y = plane_state->base.src.y1 >> 16;
3014
3015         dspcntr = DISPPLANE_GAMMA_ENABLE;
3016
3017         dspcntr |= DISPLAY_PLANE_ENABLE;
3018
3019         if (INTEL_GEN(dev_priv) < 4) {
3020                 if (intel_crtc->pipe == PIPE_B)
3021                         dspcntr |= DISPPLANE_SEL_PIPE_B;
3022
3023                 /* pipesrc and dspsize control the size that is scaled from,
3024                  * which should always be the user's requested size.
3025                  */
3026                 I915_WRITE(DSPSIZE(plane),
3027                            ((crtc_state->pipe_src_h - 1) << 16) |
3028                            (crtc_state->pipe_src_w - 1));
3029                 I915_WRITE(DSPPOS(plane), 0);
3030         } else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) {
3031                 I915_WRITE(PRIMSIZE(plane),
3032                            ((crtc_state->pipe_src_h - 1) << 16) |
3033                            (crtc_state->pipe_src_w - 1));
3034                 I915_WRITE(PRIMPOS(plane), 0);
3035                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
3036         }
3037
3038         switch (fb->pixel_format) {
3039         case DRM_FORMAT_C8:
3040                 dspcntr |= DISPPLANE_8BPP;
3041                 break;
3042         case DRM_FORMAT_XRGB1555:
3043                 dspcntr |= DISPPLANE_BGRX555;
3044                 break;
3045         case DRM_FORMAT_RGB565:
3046                 dspcntr |= DISPPLANE_BGRX565;
3047                 break;
3048         case DRM_FORMAT_XRGB8888:
3049                 dspcntr |= DISPPLANE_BGRX888;
3050                 break;
3051         case DRM_FORMAT_XBGR8888:
3052                 dspcntr |= DISPPLANE_RGBX888;
3053                 break;
3054         case DRM_FORMAT_XRGB2101010:
3055                 dspcntr |= DISPPLANE_BGRX101010;
3056                 break;
3057         case DRM_FORMAT_XBGR2101010:
3058                 dspcntr |= DISPPLANE_RGBX101010;
3059                 break;
3060         default:
3061                 BUG();
3062         }
3063
3064         if (INTEL_GEN(dev_priv) >= 4 &&
3065             fb->modifier == I915_FORMAT_MOD_X_TILED)
3066                 dspcntr |= DISPPLANE_TILED;
3067
3068         if (rotation & DRM_ROTATE_180)
3069                 dspcntr |= DISPPLANE_ROTATE_180;
3070
3071         if (rotation & DRM_REFLECT_X)
3072                 dspcntr |= DISPPLANE_MIRROR;
3073
3074         if (IS_G4X(dev_priv))
3075                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3076
3077         intel_add_fb_offsets(&x, &y, plane_state, 0);
3078
3079         if (INTEL_GEN(dev_priv) >= 4)
3080                 intel_crtc->dspaddr_offset =
3081                         intel_compute_tile_offset(&x, &y, plane_state, 0);
3082
3083         if (rotation & DRM_ROTATE_180) {
3084                 x += crtc_state->pipe_src_w - 1;
3085                 y += crtc_state->pipe_src_h - 1;
3086         } else if (rotation & DRM_REFLECT_X) {
3087                 x += crtc_state->pipe_src_w - 1;
3088         }
3089
3090         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3091
3092         if (INTEL_GEN(dev_priv) < 4)
3093                 intel_crtc->dspaddr_offset = linear_offset;
3094
3095         intel_crtc->adjusted_x = x;
3096         intel_crtc->adjusted_y = y;
3097
3098         I915_WRITE(reg, dspcntr);
3099
3100         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
3101         if (INTEL_GEN(dev_priv) >= 4) {
3102                 I915_WRITE(DSPSURF(plane),
3103                            intel_fb_gtt_offset(fb, rotation) +
3104                            intel_crtc->dspaddr_offset);
3105                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
3106                 I915_WRITE(DSPLINOFF(plane), linear_offset);
3107         } else {
3108                 I915_WRITE(DSPADDR(plane),
3109                            intel_fb_gtt_offset(fb, rotation) +
3110                            intel_crtc->dspaddr_offset);
3111         }
3112         POSTING_READ(reg);
3113 }
3114
3115 static void i9xx_disable_primary_plane(struct drm_plane *primary,
3116                                        struct drm_crtc *crtc)
3117 {
3118         struct drm_device *dev = crtc->dev;
3119         struct drm_i915_private *dev_priv = to_i915(dev);
3120         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3121         int plane = intel_crtc->plane;
3122
3123         I915_WRITE(DSPCNTR(plane), 0);
3124         if (INTEL_INFO(dev_priv)->gen >= 4)
3125                 I915_WRITE(DSPSURF(plane), 0);
3126         else
3127                 I915_WRITE(DSPADDR(plane), 0);
3128         POSTING_READ(DSPCNTR(plane));
3129 }
3130
3131 static void ironlake_update_primary_plane(struct drm_plane *primary,
3132                                           const struct intel_crtc_state *crtc_state,
3133                                           const struct intel_plane_state *plane_state)
3134 {
3135         struct drm_device *dev = primary->dev;
3136         struct drm_i915_private *dev_priv = to_i915(dev);
3137         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3138         struct drm_framebuffer *fb = plane_state->base.fb;
3139         int plane = intel_crtc->plane;
3140         u32 linear_offset;
3141         u32 dspcntr;
3142         i915_reg_t reg = DSPCNTR(plane);
3143         unsigned int rotation = plane_state->base.rotation;
3144         int x = plane_state->base.src.x1 >> 16;
3145         int y = plane_state->base.src.y1 >> 16;
3146
3147         dspcntr = DISPPLANE_GAMMA_ENABLE;
3148         dspcntr |= DISPLAY_PLANE_ENABLE;
3149
3150         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
3151                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
3152
3153         switch (fb->pixel_format) {
3154         case DRM_FORMAT_C8:
3155                 dspcntr |= DISPPLANE_8BPP;
3156                 break;
3157         case DRM_FORMAT_RGB565:
3158                 dspcntr |= DISPPLANE_BGRX565;
3159                 break;
3160         case DRM_FORMAT_XRGB8888:
3161                 dspcntr |= DISPPLANE_BGRX888;
3162                 break;
3163         case DRM_FORMAT_XBGR8888:
3164                 dspcntr |= DISPPLANE_RGBX888;
3165                 break;
3166         case DRM_FORMAT_XRGB2101010:
3167                 dspcntr |= DISPPLANE_BGRX101010;
3168                 break;
3169         case DRM_FORMAT_XBGR2101010:
3170                 dspcntr |= DISPPLANE_RGBX101010;
3171                 break;
3172         default:
3173                 BUG();
3174         }
3175
3176         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
3177                 dspcntr |= DISPPLANE_TILED;
3178
3179         if (rotation & DRM_ROTATE_180)
3180                 dspcntr |= DISPPLANE_ROTATE_180;
3181
3182         if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv))
3183                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3184
3185         intel_add_fb_offsets(&x, &y, plane_state, 0);
3186
3187         intel_crtc->dspaddr_offset =
3188                 intel_compute_tile_offset(&x, &y, plane_state, 0);
3189
3190         /* HSW+ does this automagically in hardware */
3191         if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv) &&
3192             rotation & DRM_ROTATE_180) {
3193                 x += crtc_state->pipe_src_w - 1;
3194                 y += crtc_state->pipe_src_h - 1;
3195         }
3196
3197         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3198
3199         intel_crtc->adjusted_x = x;
3200         intel_crtc->adjusted_y = y;
3201
3202         I915_WRITE(reg, dspcntr);
3203
3204         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
3205         I915_WRITE(DSPSURF(plane),
3206                    intel_fb_gtt_offset(fb, rotation) +
3207                    intel_crtc->dspaddr_offset);
3208         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3209                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
3210         } else {
3211                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
3212                 I915_WRITE(DSPLINOFF(plane), linear_offset);
3213         }
3214         POSTING_READ(reg);
3215 }
3216
3217 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
3218                               uint64_t fb_modifier, uint32_t pixel_format)
3219 {
3220         if (fb_modifier == DRM_FORMAT_MOD_NONE) {
3221                 return 64;
3222         } else {
3223                 int cpp = drm_format_plane_cpp(pixel_format, 0);
3224
3225                 return intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
3226         }
3227 }
3228
3229 u32 intel_fb_gtt_offset(struct drm_framebuffer *fb,
3230                         unsigned int rotation)
3231 {
3232         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
3233         struct i915_ggtt_view view;
3234         struct i915_vma *vma;
3235
3236         intel_fill_fb_ggtt_view(&view, fb, rotation);
3237
3238         vma = i915_gem_object_to_ggtt(obj, &view);
3239         if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
3240                  view.type))
3241                 return -1;
3242
3243         return i915_ggtt_offset(vma);
3244 }
3245
3246 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
3247 {
3248         struct drm_device *dev = intel_crtc->base.dev;
3249         struct drm_i915_private *dev_priv = to_i915(dev);
3250
3251         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
3252         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
3253         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
3254 }
3255
3256 /*
3257  * This function detaches (aka. unbinds) unused scalers in hardware
3258  */
3259 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
3260 {
3261         struct intel_crtc_scaler_state *scaler_state;
3262         int i;
3263
3264         scaler_state = &intel_crtc->config->scaler_state;
3265
3266         /* loop through and disable scalers that aren't in use */
3267         for (i = 0; i < intel_crtc->num_scalers; i++) {
3268                 if (!scaler_state->scalers[i].in_use)
3269                         skl_detach_scaler(intel_crtc, i);
3270         }
3271 }
3272
3273 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
3274                      unsigned int rotation)
3275 {
3276         const struct drm_i915_private *dev_priv = to_i915(fb->dev);
3277         u32 stride = intel_fb_pitch(fb, plane, rotation);
3278
3279         /*
3280          * The stride is either expressed as a multiple of 64 bytes chunks for
3281          * linear buffers or in number of tiles for tiled buffers.
3282          */
3283         if (drm_rotation_90_or_270(rotation)) {
3284                 int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
3285
3286                 stride /= intel_tile_height(dev_priv, fb->modifier, cpp);
3287         } else {
3288                 stride /= intel_fb_stride_alignment(dev_priv, fb->modifier,
3289                                                     fb->pixel_format);
3290         }
3291
3292         return stride;
3293 }
3294
3295 u32 skl_plane_ctl_format(uint32_t pixel_format)
3296 {
3297         switch (pixel_format) {
3298         case DRM_FORMAT_C8:
3299                 return PLANE_CTL_FORMAT_INDEXED;
3300         case DRM_FORMAT_RGB565:
3301                 return PLANE_CTL_FORMAT_RGB_565;
3302         case DRM_FORMAT_XBGR8888:
3303                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3304         case DRM_FORMAT_XRGB8888:
3305                 return PLANE_CTL_FORMAT_XRGB_8888;
3306         /*
3307          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3308          * to be already pre-multiplied. We need to add a knob (or a different
3309          * DRM_FORMAT) for user-space to configure that.
3310          */
3311         case DRM_FORMAT_ABGR8888:
3312                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3313                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3314         case DRM_FORMAT_ARGB8888:
3315                 return PLANE_CTL_FORMAT_XRGB_8888 |
3316                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3317         case DRM_FORMAT_XRGB2101010:
3318                 return PLANE_CTL_FORMAT_XRGB_2101010;
3319         case DRM_FORMAT_XBGR2101010:
3320                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3321         case DRM_FORMAT_YUYV:
3322                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3323         case DRM_FORMAT_YVYU:
3324                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3325         case DRM_FORMAT_UYVY:
3326                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3327         case DRM_FORMAT_VYUY:
3328                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3329         default:
3330                 MISSING_CASE(pixel_format);
3331         }
3332
3333         return 0;
3334 }
3335
3336 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3337 {
3338         switch (fb_modifier) {
3339         case DRM_FORMAT_MOD_NONE:
3340                 break;
3341         case I915_FORMAT_MOD_X_TILED:
3342                 return PLANE_CTL_TILED_X;
3343         case I915_FORMAT_MOD_Y_TILED:
3344                 return PLANE_CTL_TILED_Y;
3345         case I915_FORMAT_MOD_Yf_TILED:
3346                 return PLANE_CTL_TILED_YF;
3347         default:
3348                 MISSING_CASE(fb_modifier);
3349         }
3350
3351         return 0;
3352 }
3353
3354 u32 skl_plane_ctl_rotation(unsigned int rotation)
3355 {
3356         switch (rotation) {
3357         case DRM_ROTATE_0:
3358                 break;
3359         /*
3360          * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3361          * while i915 HW rotation is clockwise, thats why this swapping.
3362          */
3363         case DRM_ROTATE_90:
3364                 return PLANE_CTL_ROTATE_270;
3365         case DRM_ROTATE_180:
3366                 return PLANE_CTL_ROTATE_180;
3367         case DRM_ROTATE_270:
3368                 return PLANE_CTL_ROTATE_90;
3369         default:
3370                 MISSING_CASE(rotation);
3371         }
3372
3373         return 0;
3374 }
3375
3376 static void skylake_update_primary_plane(struct drm_plane *plane,
3377                                          const struct intel_crtc_state *crtc_state,
3378                                          const struct intel_plane_state *plane_state)
3379 {
3380         struct drm_device *dev = plane->dev;
3381         struct drm_i915_private *dev_priv = to_i915(dev);
3382         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3383         struct drm_framebuffer *fb = plane_state->base.fb;
3384         int pipe = intel_crtc->pipe;
3385         u32 plane_ctl;
3386         unsigned int rotation = plane_state->base.rotation;
3387         u32 stride = skl_plane_stride(fb, 0, rotation);
3388         u32 surf_addr = plane_state->main.offset;
3389         int scaler_id = plane_state->scaler_id;
3390         int src_x = plane_state->main.x;
3391         int src_y = plane_state->main.y;
3392         int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3393         int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3394         int dst_x = plane_state->base.dst.x1;
3395         int dst_y = plane_state->base.dst.y1;
3396         int dst_w = drm_rect_width(&plane_state->base.dst);
3397         int dst_h = drm_rect_height(&plane_state->base.dst);
3398
3399         plane_ctl = PLANE_CTL_ENABLE |
3400                     PLANE_CTL_PIPE_GAMMA_ENABLE |
3401                     PLANE_CTL_PIPE_CSC_ENABLE;
3402
3403         plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3404         plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
3405         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3406         plane_ctl |= skl_plane_ctl_rotation(rotation);
3407
3408         /* Sizes are 0 based */
3409         src_w--;
3410         src_h--;
3411         dst_w--;
3412         dst_h--;
3413
3414         intel_crtc->dspaddr_offset = surf_addr;
3415
3416         intel_crtc->adjusted_x = src_x;
3417         intel_crtc->adjusted_y = src_y;
3418
3419         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3420         I915_WRITE(PLANE_OFFSET(pipe, 0), (src_y << 16) | src_x);
3421         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3422         I915_WRITE(PLANE_SIZE(pipe, 0), (src_h << 16) | src_w);
3423
3424         if (scaler_id >= 0) {
3425                 uint32_t ps_ctrl = 0;
3426
3427                 WARN_ON(!dst_w || !dst_h);
3428                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3429                         crtc_state->scaler_state.scalers[scaler_id].mode;
3430                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3431                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3432                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3433                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3434                 I915_WRITE(PLANE_POS(pipe, 0), 0);
3435         } else {
3436                 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3437         }
3438
3439         I915_WRITE(PLANE_SURF(pipe, 0),
3440                    intel_fb_gtt_offset(fb, rotation) + surf_addr);
3441
3442         POSTING_READ(PLANE_SURF(pipe, 0));
3443 }
3444
3445 static void skylake_disable_primary_plane(struct drm_plane *primary,
3446                                           struct drm_crtc *crtc)
3447 {
3448         struct drm_device *dev = crtc->dev;
3449         struct drm_i915_private *dev_priv = to_i915(dev);
3450         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3451         int pipe = intel_crtc->pipe;
3452
3453         I915_WRITE(PLANE_CTL(pipe, 0), 0);
3454         I915_WRITE(PLANE_SURF(pipe, 0), 0);
3455         POSTING_READ(PLANE_SURF(pipe, 0));
3456 }
3457
3458 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3459 static int
3460 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3461                            int x, int y, enum mode_set_atomic state)
3462 {
3463         /* Support for kgdboc is disabled, this needs a major rework. */
3464         DRM_ERROR("legacy panic handler not supported any more.\n");
3465
3466         return -ENODEV;
3467 }
3468
3469 static void intel_complete_page_flips(struct drm_i915_private *dev_priv)
3470 {
3471         struct intel_crtc *crtc;
3472
3473         for_each_intel_crtc(&dev_priv->drm, crtc)
3474                 intel_finish_page_flip_cs(dev_priv, crtc->pipe);
3475 }
3476
3477 static void intel_update_primary_planes(struct drm_device *dev)
3478 {
3479         struct drm_crtc *crtc;
3480
3481         for_each_crtc(dev, crtc) {
3482                 struct intel_plane *plane = to_intel_plane(crtc->primary);
3483                 struct intel_plane_state *plane_state =
3484                         to_intel_plane_state(plane->base.state);
3485
3486                 if (plane_state->base.visible)
3487                         plane->update_plane(&plane->base,
3488                                             to_intel_crtc_state(crtc->state),
3489                                             plane_state);
3490         }
3491 }
3492
3493 static int
3494 __intel_display_resume(struct drm_device *dev,
3495                        struct drm_atomic_state *state)
3496 {
3497         struct drm_crtc_state *crtc_state;
3498         struct drm_crtc *crtc;
3499         int i, ret;
3500
3501         intel_modeset_setup_hw_state(dev);
3502         i915_redisable_vga(to_i915(dev));
3503
3504         if (!state)
3505                 return 0;
3506
3507         for_each_crtc_in_state(state, crtc, crtc_state, i) {
3508                 /*
3509                  * Force recalculation even if we restore
3510                  * current state. With fast modeset this may not result
3511                  * in a modeset when the state is compatible.
3512                  */
3513                 crtc_state->mode_changed = true;
3514         }
3515
3516         /* ignore any reset values/BIOS leftovers in the WM registers */
3517         to_intel_atomic_state(state)->skip_intermediate_wm = true;
3518
3519         ret = drm_atomic_commit(state);
3520
3521         WARN_ON(ret == -EDEADLK);
3522         return ret;
3523 }
3524
3525 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
3526 {
3527         return intel_has_gpu_reset(dev_priv) &&
3528                 INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv);
3529 }
3530
3531 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3532 {
3533         struct drm_device *dev = &dev_priv->drm;
3534         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3535         struct drm_atomic_state *state;
3536         int ret;
3537
3538         /*
3539          * Need mode_config.mutex so that we don't
3540          * trample ongoing ->detect() and whatnot.
3541          */
3542         mutex_lock(&dev->mode_config.mutex);
3543         drm_modeset_acquire_init(ctx, 0);
3544         while (1) {
3545                 ret = drm_modeset_lock_all_ctx(dev, ctx);
3546                 if (ret != -EDEADLK)
3547                         break;
3548
3549                 drm_modeset_backoff(ctx);
3550         }
3551
3552         /* reset doesn't touch the display, but flips might get nuked anyway, */
3553         if (!i915.force_reset_modeset_test &&
3554             !gpu_reset_clobbers_display(dev_priv))
3555                 return;
3556
3557         /*
3558          * Disabling the crtcs gracefully seems nicer. Also the
3559          * g33 docs say we should at least disable all the planes.
3560          */
3561         state = drm_atomic_helper_duplicate_state(dev, ctx);
3562         if (IS_ERR(state)) {
3563                 ret = PTR_ERR(state);
3564                 state = NULL;
3565                 DRM_ERROR("Duplicating state failed with %i\n", ret);
3566                 goto err;
3567         }
3568
3569         ret = drm_atomic_helper_disable_all(dev, ctx);
3570         if (ret) {
3571                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
3572                 goto err;
3573         }
3574
3575         dev_priv->modeset_restore_state = state;
3576         state->acquire_ctx = ctx;
3577         return;
3578
3579 err:
3580         drm_atomic_state_put(state);
3581 }
3582
3583 void intel_finish_reset(struct drm_i915_private *dev_priv)
3584 {
3585         struct drm_device *dev = &dev_priv->drm;
3586         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3587         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
3588         int ret;
3589
3590         /*
3591          * Flips in the rings will be nuked by the reset,
3592          * so complete all pending flips so that user space
3593          * will get its events and not get stuck.
3594          */
3595         intel_complete_page_flips(dev_priv);
3596
3597         dev_priv->modeset_restore_state = NULL;
3598
3599         /* reset doesn't touch the display */
3600         if (!gpu_reset_clobbers_display(dev_priv)) {
3601                 if (!state) {
3602                         /*
3603                          * Flips in the rings have been nuked by the reset,
3604                          * so update the base address of all primary
3605                          * planes to the the last fb to make sure we're
3606                          * showing the correct fb after a reset.
3607                          *
3608                          * FIXME: Atomic will make this obsolete since we won't schedule
3609                          * CS-based flips (which might get lost in gpu resets) any more.
3610                          */
3611                         intel_update_primary_planes(dev);
3612                 } else {
3613                         ret = __intel_display_resume(dev, state);
3614                         if (ret)
3615                                 DRM_ERROR("Restoring old state failed with %i\n", ret);
3616                 }
3617         } else {
3618                 /*
3619                  * The display has been reset as well,
3620                  * so need a full re-initialization.
3621                  */
3622                 intel_runtime_pm_disable_interrupts(dev_priv);
3623                 intel_runtime_pm_enable_interrupts(dev_priv);
3624
3625                 intel_pps_unlock_regs_wa(dev_priv);
3626                 intel_modeset_init_hw(dev);
3627
3628                 spin_lock_irq(&dev_priv->irq_lock);
3629                 if (dev_priv->display.hpd_irq_setup)
3630                         dev_priv->display.hpd_irq_setup(dev_priv);
3631                 spin_unlock_irq(&dev_priv->irq_lock);
3632
3633                 ret = __intel_display_resume(dev, state);
3634                 if (ret)
3635                         DRM_ERROR("Restoring old state failed with %i\n", ret);
3636
3637                 intel_hpd_init(dev_priv);
3638         }
3639
3640         if (state)
3641                 drm_atomic_state_put(state);
3642         drm_modeset_drop_locks(ctx);
3643         drm_modeset_acquire_fini(ctx);
3644         mutex_unlock(&dev->mode_config.mutex);
3645 }
3646
3647 static bool abort_flip_on_reset(struct intel_crtc *crtc)
3648 {
3649         struct i915_gpu_error *error = &to_i915(crtc->base.dev)->gpu_error;
3650
3651         if (i915_reset_in_progress(error))
3652                 return true;
3653
3654         if (crtc->reset_count != i915_reset_count(error))
3655                 return true;
3656
3657         return false;
3658 }
3659
3660 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3661 {
3662         struct drm_device *dev = crtc->dev;
3663         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3664         bool pending;
3665
3666         if (abort_flip_on_reset(intel_crtc))
3667                 return false;
3668
3669         spin_lock_irq(&dev->event_lock);
3670         pending = to_intel_crtc(crtc)->flip_work != NULL;
3671         spin_unlock_irq(&dev->event_lock);
3672
3673         return pending;
3674 }
3675
3676 static void intel_update_pipe_config(struct intel_crtc *crtc,
3677                                      struct intel_crtc_state *old_crtc_state)
3678 {
3679         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3680         struct intel_crtc_state *pipe_config =
3681                 to_intel_crtc_state(crtc->base.state);
3682
3683         /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3684         crtc->base.mode = crtc->base.state->mode;
3685
3686         DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3687                       old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3688                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3689
3690         /*
3691          * Update pipe size and adjust fitter if needed: the reason for this is
3692          * that in compute_mode_changes we check the native mode (not the pfit
3693          * mode) to see if we can flip rather than do a full mode set. In the
3694          * fastboot case, we'll flip, but if we don't update the pipesrc and
3695          * pfit state, we'll end up with a big fb scanned out into the wrong
3696          * sized surface.
3697          */
3698
3699         I915_WRITE(PIPESRC(crtc->pipe),
3700                    ((pipe_config->pipe_src_w - 1) << 16) |
3701                    (pipe_config->pipe_src_h - 1));
3702
3703         /* on skylake this is done by detaching scalers */
3704         if (INTEL_GEN(dev_priv) >= 9) {
3705                 skl_detach_scalers(crtc);
3706
3707                 if (pipe_config->pch_pfit.enabled)
3708                         skylake_pfit_enable(crtc);
3709         } else if (HAS_PCH_SPLIT(dev_priv)) {
3710                 if (pipe_config->pch_pfit.enabled)
3711                         ironlake_pfit_enable(crtc);
3712                 else if (old_crtc_state->pch_pfit.enabled)
3713                         ironlake_pfit_disable(crtc, true);
3714         }
3715 }
3716
3717 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3718 {
3719         struct drm_device *dev = crtc->dev;
3720         struct drm_i915_private *dev_priv = to_i915(dev);
3721         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3722         int pipe = intel_crtc->pipe;
3723         i915_reg_t reg;
3724         u32 temp;
3725
3726         /* enable normal train */
3727         reg = FDI_TX_CTL(pipe);
3728         temp = I915_READ(reg);
3729         if (IS_IVYBRIDGE(dev_priv)) {
3730                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3731                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3732         } else {
3733                 temp &= ~FDI_LINK_TRAIN_NONE;
3734                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3735         }
3736         I915_WRITE(reg, temp);
3737
3738         reg = FDI_RX_CTL(pipe);
3739         temp = I915_READ(reg);
3740         if (HAS_PCH_CPT(dev_priv)) {
3741                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3742                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3743         } else {
3744                 temp &= ~FDI_LINK_TRAIN_NONE;
3745                 temp |= FDI_LINK_TRAIN_NONE;
3746         }
3747         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3748
3749         /* wait one idle pattern time */
3750         POSTING_READ(reg);
3751         udelay(1000);
3752
3753         /* IVB wants error correction enabled */
3754         if (IS_IVYBRIDGE(dev_priv))
3755                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3756                            FDI_FE_ERRC_ENABLE);
3757 }
3758
3759 /* The FDI link training functions for ILK/Ibexpeak. */
3760 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3761 {
3762         struct drm_device *dev = crtc->dev;
3763         struct drm_i915_private *dev_priv = to_i915(dev);
3764         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3765         int pipe = intel_crtc->pipe;
3766         i915_reg_t reg;
3767         u32 temp, tries;
3768
3769         /* FDI needs bits from pipe first */
3770         assert_pipe_enabled(dev_priv, pipe);
3771
3772         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3773            for train result */
3774         reg = FDI_RX_IMR(pipe);
3775         temp = I915_READ(reg);
3776         temp &= ~FDI_RX_SYMBOL_LOCK;
3777         temp &= ~FDI_RX_BIT_LOCK;
3778         I915_WRITE(reg, temp);
3779         I915_READ(reg);
3780         udelay(150);
3781
3782         /* enable CPU FDI TX and PCH FDI RX */
3783         reg = FDI_TX_CTL(pipe);
3784         temp = I915_READ(reg);
3785         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3786         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3787         temp &= ~FDI_LINK_TRAIN_NONE;
3788         temp |= FDI_LINK_TRAIN_PATTERN_1;
3789         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3790
3791         reg = FDI_RX_CTL(pipe);
3792         temp = I915_READ(reg);
3793         temp &= ~FDI_LINK_TRAIN_NONE;
3794         temp |= FDI_LINK_TRAIN_PATTERN_1;
3795         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3796
3797         POSTING_READ(reg);
3798         udelay(150);
3799
3800         /* Ironlake workaround, enable clock pointer after FDI enable*/
3801         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3802         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3803                    FDI_RX_PHASE_SYNC_POINTER_EN);
3804
3805         reg = FDI_RX_IIR(pipe);
3806         for (tries = 0; tries < 5; tries++) {
3807                 temp = I915_READ(reg);
3808                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3809
3810                 if ((temp & FDI_RX_BIT_LOCK)) {
3811                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3812                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3813                         break;
3814                 }
3815         }
3816         if (tries == 5)
3817                 DRM_ERROR("FDI train 1 fail!\n");
3818
3819         /* Train 2 */
3820         reg = FDI_TX_CTL(pipe);
3821         temp = I915_READ(reg);
3822         temp &= ~FDI_LINK_TRAIN_NONE;
3823         temp |= FDI_LINK_TRAIN_PATTERN_2;
3824         I915_WRITE(reg, temp);
3825
3826         reg = FDI_RX_CTL(pipe);
3827         temp = I915_READ(reg);
3828         temp &= ~FDI_LINK_TRAIN_NONE;
3829         temp |= FDI_LINK_TRAIN_PATTERN_2;
3830         I915_WRITE(reg, temp);
3831
3832         POSTING_READ(reg);
3833         udelay(150);
3834
3835         reg = FDI_RX_IIR(pipe);
3836         for (tries = 0; tries < 5; tries++) {
3837                 temp = I915_READ(reg);
3838                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3839
3840                 if (temp & FDI_RX_SYMBOL_LOCK) {
3841                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3842                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3843                         break;
3844                 }
3845         }
3846         if (tries == 5)
3847                 DRM_ERROR("FDI train 2 fail!\n");
3848
3849         DRM_DEBUG_KMS("FDI train done\n");
3850
3851 }
3852
3853 static const int snb_b_fdi_train_param[] = {
3854         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3855         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3856         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3857         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3858 };
3859
3860 /* The FDI link training functions for SNB/Cougarpoint. */
3861 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3862 {
3863         struct drm_device *dev = crtc->dev;
3864         struct drm_i915_private *dev_priv = to_i915(dev);
3865         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3866         int pipe = intel_crtc->pipe;
3867         i915_reg_t reg;
3868         u32 temp, i, retry;
3869
3870         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3871            for train result */
3872         reg = FDI_RX_IMR(pipe);
3873         temp = I915_READ(reg);
3874         temp &= ~FDI_RX_SYMBOL_LOCK;
3875         temp &= ~FDI_RX_BIT_LOCK;
3876         I915_WRITE(reg, temp);
3877
3878         POSTING_READ(reg);
3879         udelay(150);
3880
3881         /* enable CPU FDI TX and PCH FDI RX */
3882         reg = FDI_TX_CTL(pipe);
3883         temp = I915_READ(reg);
3884         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3885         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3886         temp &= ~FDI_LINK_TRAIN_NONE;
3887         temp |= FDI_LINK_TRAIN_PATTERN_1;
3888         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3889         /* SNB-B */
3890         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3891         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3892
3893         I915_WRITE(FDI_RX_MISC(pipe),
3894                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3895
3896         reg = FDI_RX_CTL(pipe);
3897         temp = I915_READ(reg);
3898         if (HAS_PCH_CPT(dev_priv)) {
3899                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3900                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3901         } else {
3902                 temp &= ~FDI_LINK_TRAIN_NONE;
3903                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3904         }
3905         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3906
3907         POSTING_READ(reg);
3908         udelay(150);
3909
3910         for (i = 0; i < 4; i++) {
3911                 reg = FDI_TX_CTL(pipe);
3912                 temp = I915_READ(reg);
3913                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3914                 temp |= snb_b_fdi_train_param[i];
3915                 I915_WRITE(reg, temp);
3916
3917                 POSTING_READ(reg);
3918                 udelay(500);
3919
3920                 for (retry = 0; retry < 5; retry++) {
3921                         reg = FDI_RX_IIR(pipe);
3922                         temp = I915_READ(reg);
3923                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3924                         if (temp & FDI_RX_BIT_LOCK) {
3925                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3926                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3927                                 break;
3928                         }
3929                         udelay(50);
3930                 }
3931                 if (retry < 5)
3932                         break;
3933         }
3934         if (i == 4)
3935                 DRM_ERROR("FDI train 1 fail!\n");
3936
3937         /* Train 2 */
3938         reg = FDI_TX_CTL(pipe);
3939         temp = I915_READ(reg);
3940         temp &= ~FDI_LINK_TRAIN_NONE;
3941         temp |= FDI_LINK_TRAIN_PATTERN_2;
3942         if (IS_GEN6(dev_priv)) {
3943                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3944                 /* SNB-B */
3945                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3946         }
3947         I915_WRITE(reg, temp);
3948
3949         reg = FDI_RX_CTL(pipe);
3950         temp = I915_READ(reg);
3951         if (HAS_PCH_CPT(dev_priv)) {
3952                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3953                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3954         } else {
3955                 temp &= ~FDI_LINK_TRAIN_NONE;
3956                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3957         }
3958         I915_WRITE(reg, temp);
3959
3960         POSTING_READ(reg);
3961         udelay(150);
3962
3963         for (i = 0; i < 4; i++) {
3964                 reg = FDI_TX_CTL(pipe);
3965                 temp = I915_READ(reg);
3966                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3967                 temp |= snb_b_fdi_train_param[i];
3968                 I915_WRITE(reg, temp);
3969
3970                 POSTING_READ(reg);
3971                 udelay(500);
3972
3973                 for (retry = 0; retry < 5; retry++) {
3974                         reg = FDI_RX_IIR(pipe);
3975                         temp = I915_READ(reg);
3976                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3977                         if (temp & FDI_RX_SYMBOL_LOCK) {
3978                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3979                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3980                                 break;
3981                         }
3982                         udelay(50);
3983                 }
3984                 if (retry < 5)
3985                         break;
3986         }
3987         if (i == 4)
3988                 DRM_ERROR("FDI train 2 fail!\n");
3989
3990         DRM_DEBUG_KMS("FDI train done.\n");
3991 }
3992
3993 /* Manual link training for Ivy Bridge A0 parts */
3994 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3995 {
3996         struct drm_device *dev = crtc->dev;
3997         struct drm_i915_private *dev_priv = to_i915(dev);
3998         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3999         int pipe = intel_crtc->pipe;
4000         i915_reg_t reg;
4001         u32 temp, i, j;
4002
4003         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4004            for train result */
4005         reg = FDI_RX_IMR(pipe);
4006         temp = I915_READ(reg);
4007         temp &= ~FDI_RX_SYMBOL_LOCK;
4008         temp &= ~FDI_RX_BIT_LOCK;
4009         I915_WRITE(reg, temp);
4010
4011         POSTING_READ(reg);
4012         udelay(150);
4013
4014         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
4015                       I915_READ(FDI_RX_IIR(pipe)));
4016
4017         /* Try each vswing and preemphasis setting twice before moving on */
4018         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
4019                 /* disable first in case we need to retry */
4020                 reg = FDI_TX_CTL(pipe);
4021                 temp = I915_READ(reg);
4022                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
4023                 temp &= ~FDI_TX_ENABLE;
4024                 I915_WRITE(reg, temp);
4025
4026                 reg = FDI_RX_CTL(pipe);
4027                 temp = I915_READ(reg);
4028                 temp &= ~FDI_LINK_TRAIN_AUTO;
4029                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4030                 temp &= ~FDI_RX_ENABLE;
4031                 I915_WRITE(reg, temp);
4032
4033                 /* enable CPU FDI TX and PCH FDI RX */
4034                 reg = FDI_TX_CTL(pipe);
4035                 temp = I915_READ(reg);
4036                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
4037                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4038                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
4039                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4040                 temp |= snb_b_fdi_train_param[j/2];
4041                 temp |= FDI_COMPOSITE_SYNC;
4042                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4043
4044                 I915_WRITE(FDI_RX_MISC(pipe),
4045                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4046
4047                 reg = FDI_RX_CTL(pipe);
4048                 temp = I915_READ(reg);
4049                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4050                 temp |= FDI_COMPOSITE_SYNC;
4051                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4052
4053                 POSTING_READ(reg);
4054                 udelay(1); /* should be 0.5us */
4055
4056                 for (i = 0; i < 4; i++) {
4057                         reg = FDI_RX_IIR(pipe);
4058                         temp = I915_READ(reg);
4059                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4060
4061                         if (temp & FDI_RX_BIT_LOCK ||
4062                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
4063                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4064                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4065                                               i);
4066                                 break;
4067                         }
4068                         udelay(1); /* should be 0.5us */
4069                 }
4070                 if (i == 4) {
4071                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
4072                         continue;
4073                 }
4074
4075                 /* Train 2 */
4076                 reg = FDI_TX_CTL(pipe);
4077                 temp = I915_READ(reg);
4078                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4079                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
4080                 I915_WRITE(reg, temp);
4081
4082                 reg = FDI_RX_CTL(pipe);
4083                 temp = I915_READ(reg);
4084                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4085                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4086                 I915_WRITE(reg, temp);
4087
4088                 POSTING_READ(reg);
4089                 udelay(2); /* should be 1.5us */
4090
4091                 for (i = 0; i < 4; i++) {
4092                         reg = FDI_RX_IIR(pipe);
4093                         temp = I915_READ(reg);
4094                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4095
4096                         if (temp & FDI_RX_SYMBOL_LOCK ||
4097                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
4098                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4099                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4100                                               i);
4101                                 goto train_done;
4102                         }
4103                         udelay(2); /* should be 1.5us */
4104                 }
4105                 if (i == 4)
4106                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
4107         }
4108
4109 train_done:
4110         DRM_DEBUG_KMS("FDI train done.\n");
4111 }
4112
4113 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
4114 {
4115         struct drm_device *dev = intel_crtc->base.dev;
4116         struct drm_i915_private *dev_priv = to_i915(dev);
4117         int pipe = intel_crtc->pipe;
4118         i915_reg_t reg;
4119         u32 temp;
4120
4121         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
4122         reg = FDI_RX_CTL(pipe);
4123         temp = I915_READ(reg);
4124         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
4125         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4126         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4127         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4128
4129         POSTING_READ(reg);
4130         udelay(200);
4131
4132         /* Switch from Rawclk to PCDclk */
4133         temp = I915_READ(reg);
4134         I915_WRITE(reg, temp | FDI_PCDCLK);
4135
4136         POSTING_READ(reg);
4137         udelay(200);
4138
4139         /* Enable CPU FDI TX PLL, always on for Ironlake */
4140         reg = FDI_TX_CTL(pipe);
4141         temp = I915_READ(reg);
4142         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
4143                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
4144
4145                 POSTING_READ(reg);
4146                 udelay(100);
4147         }
4148 }
4149
4150 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
4151 {
4152         struct drm_device *dev = intel_crtc->base.dev;
4153         struct drm_i915_private *dev_priv = to_i915(dev);
4154         int pipe = intel_crtc->pipe;
4155         i915_reg_t reg;
4156         u32 temp;
4157
4158         /* Switch from PCDclk to Rawclk */
4159         reg = FDI_RX_CTL(pipe);
4160         temp = I915_READ(reg);
4161         I915_WRITE(reg, temp & ~FDI_PCDCLK);
4162
4163         /* Disable CPU FDI TX PLL */
4164         reg = FDI_TX_CTL(pipe);
4165         temp = I915_READ(reg);
4166         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
4167
4168         POSTING_READ(reg);
4169         udelay(100);
4170
4171         reg = FDI_RX_CTL(pipe);
4172         temp = I915_READ(reg);
4173         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
4174
4175         /* Wait for the clocks to turn off. */
4176         POSTING_READ(reg);
4177         udelay(100);
4178 }
4179
4180 static void ironlake_fdi_disable(struct drm_crtc *crtc)
4181 {
4182         struct drm_device *dev = crtc->dev;
4183         struct drm_i915_private *dev_priv = to_i915(dev);
4184         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4185         int pipe = intel_crtc->pipe;
4186         i915_reg_t reg;
4187         u32 temp;
4188
4189         /* disable CPU FDI tx and PCH FDI rx */
4190         reg = FDI_TX_CTL(pipe);
4191         temp = I915_READ(reg);
4192         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
4193         POSTING_READ(reg);
4194
4195         reg = FDI_RX_CTL(pipe);
4196         temp = I915_READ(reg);
4197         temp &= ~(0x7 << 16);
4198         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4199         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
4200
4201         POSTING_READ(reg);
4202         udelay(100);
4203
4204         /* Ironlake workaround, disable clock pointer after downing FDI */
4205         if (HAS_PCH_IBX(dev_priv))
4206                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4207
4208         /* still set train pattern 1 */
4209         reg = FDI_TX_CTL(pipe);
4210         temp = I915_READ(reg);
4211         temp &= ~FDI_LINK_TRAIN_NONE;
4212         temp |= FDI_LINK_TRAIN_PATTERN_1;
4213         I915_WRITE(reg, temp);
4214
4215         reg = FDI_RX_CTL(pipe);
4216         temp = I915_READ(reg);
4217         if (HAS_PCH_CPT(dev_priv)) {
4218                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4219                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4220         } else {
4221                 temp &= ~FDI_LINK_TRAIN_NONE;
4222                 temp |= FDI_LINK_TRAIN_PATTERN_1;
4223         }
4224         /* BPC in FDI rx is consistent with that in PIPECONF */
4225         temp &= ~(0x07 << 16);
4226         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4227         I915_WRITE(reg, temp);
4228
4229         POSTING_READ(reg);
4230         udelay(100);
4231 }
4232
4233 bool intel_has_pending_fb_unpin(struct drm_device *dev)
4234 {
4235         struct drm_i915_private *dev_priv = to_i915(dev);
4236         struct intel_crtc *crtc;
4237
4238         /* Note that we don't need to be called with mode_config.lock here
4239          * as our list of CRTC objects is static for the lifetime of the
4240          * device and so cannot disappear as we iterate. Similarly, we can
4241          * happily treat the predicates as racy, atomic checks as userspace
4242          * cannot claim and pin a new fb without at least acquring the
4243          * struct_mutex and so serialising with us.
4244          */
4245         for_each_intel_crtc(dev, crtc) {
4246                 if (atomic_read(&crtc->unpin_work_count) == 0)
4247                         continue;
4248
4249                 if (crtc->flip_work)
4250                         intel_wait_for_vblank(dev_priv, crtc->pipe);
4251
4252                 return true;
4253         }
4254
4255         return false;
4256 }
4257
4258 static void page_flip_completed(struct intel_crtc *intel_crtc)
4259 {
4260         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4261         struct intel_flip_work *work = intel_crtc->flip_work;
4262
4263         intel_crtc->flip_work = NULL;
4264
4265         if (work->event)
4266                 drm_crtc_send_vblank_event(&intel_crtc->base, work->event);
4267
4268         drm_crtc_vblank_put(&intel_crtc->base);
4269
4270         wake_up_all(&dev_priv->pending_flip_queue);
4271         queue_work(dev_priv->wq, &work->unpin_work);
4272
4273         trace_i915_flip_complete(intel_crtc->plane,
4274                                  work->pending_flip_obj);
4275 }
4276
4277 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
4278 {
4279         struct drm_device *dev = crtc->dev;
4280         struct drm_i915_private *dev_priv = to_i915(dev);
4281         long ret;
4282
4283         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
4284
4285         ret = wait_event_interruptible_timeout(
4286                                         dev_priv->pending_flip_queue,
4287                                         !intel_crtc_has_pending_flip(crtc),
4288                                         60*HZ);
4289
4290         if (ret < 0)
4291                 return ret;
4292
4293         if (ret == 0) {
4294                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4295                 struct intel_flip_work *work;
4296
4297                 spin_lock_irq(&dev->event_lock);
4298                 work = intel_crtc->flip_work;
4299                 if (work && !is_mmio_work(work)) {
4300                         WARN_ONCE(1, "Removing stuck page flip\n");
4301                         page_flip_completed(intel_crtc);
4302                 }
4303                 spin_unlock_irq(&dev->event_lock);
4304         }
4305
4306         return 0;
4307 }
4308
4309 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
4310 {
4311         u32 temp;
4312
4313         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
4314
4315         mutex_lock(&dev_priv->sb_lock);
4316
4317         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4318         temp |= SBI_SSCCTL_DISABLE;
4319         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4320
4321         mutex_unlock(&dev_priv->sb_lock);
4322 }
4323
4324 /* Program iCLKIP clock to the desired frequency */
4325 static void lpt_program_iclkip(struct drm_crtc *crtc)
4326 {
4327         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
4328         int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
4329         u32 divsel, phaseinc, auxdiv, phasedir = 0;
4330         u32 temp;
4331
4332         lpt_disable_iclkip(dev_priv);
4333
4334         /* The iCLK virtual clock root frequency is in MHz,
4335          * but the adjusted_mode->crtc_clock in in KHz. To get the
4336          * divisors, it is necessary to divide one by another, so we
4337          * convert the virtual clock precision to KHz here for higher
4338          * precision.
4339          */
4340         for (auxdiv = 0; auxdiv < 2; auxdiv++) {
4341                 u32 iclk_virtual_root_freq = 172800 * 1000;
4342                 u32 iclk_pi_range = 64;
4343                 u32 desired_divisor;
4344
4345                 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4346                                                     clock << auxdiv);
4347                 divsel = (desired_divisor / iclk_pi_range) - 2;
4348                 phaseinc = desired_divisor % iclk_pi_range;
4349
4350                 /*
4351                  * Near 20MHz is a corner case which is
4352                  * out of range for the 7-bit divisor
4353                  */
4354                 if (divsel <= 0x7f)
4355                         break;
4356         }
4357
4358         /* This should not happen with any sane values */
4359         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4360                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4361         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4362                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4363
4364         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4365                         clock,
4366                         auxdiv,
4367                         divsel,
4368                         phasedir,
4369                         phaseinc);
4370
4371         mutex_lock(&dev_priv->sb_lock);
4372
4373         /* Program SSCDIVINTPHASE6 */
4374         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4375         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4376         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4377         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4378         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4379         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4380         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4381         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4382
4383         /* Program SSCAUXDIV */
4384         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4385         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4386         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4387         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4388
4389         /* Enable modulator and associated divider */
4390         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4391         temp &= ~SBI_SSCCTL_DISABLE;
4392         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4393
4394         mutex_unlock(&dev_priv->sb_lock);
4395
4396         /* Wait for initialization time */
4397         udelay(24);
4398
4399         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4400 }
4401
4402 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
4403 {
4404         u32 divsel, phaseinc, auxdiv;
4405         u32 iclk_virtual_root_freq = 172800 * 1000;
4406         u32 iclk_pi_range = 64;
4407         u32 desired_divisor;
4408         u32 temp;
4409
4410         if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
4411                 return 0;
4412
4413         mutex_lock(&dev_priv->sb_lock);
4414
4415         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4416         if (temp & SBI_SSCCTL_DISABLE) {
4417                 mutex_unlock(&dev_priv->sb_lock);
4418                 return 0;
4419         }
4420
4421         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4422         divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
4423                 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
4424         phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
4425                 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
4426
4427         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4428         auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4429                 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4430
4431         mutex_unlock(&dev_priv->sb_lock);
4432
4433         desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4434
4435         return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4436                                  desired_divisor << auxdiv);
4437 }
4438
4439 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4440                                                 enum pipe pch_transcoder)
4441 {
4442         struct drm_device *dev = crtc->base.dev;
4443         struct drm_i915_private *dev_priv = to_i915(dev);
4444         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4445
4446         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4447                    I915_READ(HTOTAL(cpu_transcoder)));
4448         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4449                    I915_READ(HBLANK(cpu_transcoder)));
4450         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4451                    I915_READ(HSYNC(cpu_transcoder)));
4452
4453         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4454                    I915_READ(VTOTAL(cpu_transcoder)));
4455         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4456                    I915_READ(VBLANK(cpu_transcoder)));
4457         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4458                    I915_READ(VSYNC(cpu_transcoder)));
4459         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4460                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
4461 }
4462
4463 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4464 {
4465         struct drm_i915_private *dev_priv = to_i915(dev);
4466         uint32_t temp;
4467
4468         temp = I915_READ(SOUTH_CHICKEN1);
4469         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4470                 return;
4471
4472         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4473         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4474
4475         temp &= ~FDI_BC_BIFURCATION_SELECT;
4476         if (enable)
4477                 temp |= FDI_BC_BIFURCATION_SELECT;
4478
4479         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4480         I915_WRITE(SOUTH_CHICKEN1, temp);
4481         POSTING_READ(SOUTH_CHICKEN1);
4482 }
4483
4484 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4485 {
4486         struct drm_device *dev = intel_crtc->base.dev;
4487
4488         switch (intel_crtc->pipe) {
4489         case PIPE_A:
4490                 break;
4491         case PIPE_B:
4492                 if (intel_crtc->config->fdi_lanes > 2)
4493                         cpt_set_fdi_bc_bifurcation(dev, false);
4494                 else
4495                         cpt_set_fdi_bc_bifurcation(dev, true);
4496
4497                 break;
4498         case PIPE_C:
4499                 cpt_set_fdi_bc_bifurcation(dev, true);
4500
4501                 break;
4502         default:
4503                 BUG();
4504         }
4505 }
4506
4507 /* Return which DP Port should be selected for Transcoder DP control */
4508 static enum port
4509 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4510 {
4511         struct drm_device *dev = crtc->dev;
4512         struct intel_encoder *encoder;
4513
4514         for_each_encoder_on_crtc(dev, crtc, encoder) {
4515                 if (encoder->type == INTEL_OUTPUT_DP ||
4516                     encoder->type == INTEL_OUTPUT_EDP)
4517                         return enc_to_dig_port(&encoder->base)->port;
4518         }
4519
4520         return -1;
4521 }
4522
4523 /*
4524  * Enable PCH resources required for PCH ports:
4525  *   - PCH PLLs
4526  *   - FDI training & RX/TX
4527  *   - update transcoder timings
4528  *   - DP transcoding bits
4529  *   - transcoder
4530  */
4531 static void ironlake_pch_enable(struct drm_crtc *crtc)
4532 {
4533         struct drm_device *dev = crtc->dev;
4534         struct drm_i915_private *dev_priv = to_i915(dev);
4535         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4536         int pipe = intel_crtc->pipe;
4537         u32 temp;
4538
4539         assert_pch_transcoder_disabled(dev_priv, pipe);
4540
4541         if (IS_IVYBRIDGE(dev_priv))
4542                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4543
4544         /* Write the TU size bits before fdi link training, so that error
4545          * detection works. */
4546         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4547                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4548
4549         /* For PCH output, training FDI link */
4550         dev_priv->display.fdi_link_train(crtc);
4551
4552         /* We need to program the right clock selection before writing the pixel
4553          * mutliplier into the DPLL. */
4554         if (HAS_PCH_CPT(dev_priv)) {
4555                 u32 sel;
4556
4557                 temp = I915_READ(PCH_DPLL_SEL);
4558                 temp |= TRANS_DPLL_ENABLE(pipe);
4559                 sel = TRANS_DPLLB_SEL(pipe);
4560                 if (intel_crtc->config->shared_dpll ==
4561                     intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4562                         temp |= sel;
4563                 else
4564                         temp &= ~sel;
4565                 I915_WRITE(PCH_DPLL_SEL, temp);
4566         }
4567
4568         /* XXX: pch pll's can be enabled any time before we enable the PCH
4569          * transcoder, and we actually should do this to not upset any PCH
4570          * transcoder that already use the clock when we share it.
4571          *
4572          * Note that enable_shared_dpll tries to do the right thing, but
4573          * get_shared_dpll unconditionally resets the pll - we need that to have
4574          * the right LVDS enable sequence. */
4575         intel_enable_shared_dpll(intel_crtc);
4576
4577         /* set transcoder timing, panel must allow it */
4578         assert_panel_unlocked(dev_priv, pipe);
4579         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4580
4581         intel_fdi_normal_train(crtc);
4582
4583         /* For PCH DP, enable TRANS_DP_CTL */
4584         if (HAS_PCH_CPT(dev_priv) &&
4585             intel_crtc_has_dp_encoder(intel_crtc->config)) {
4586                 const struct drm_display_mode *adjusted_mode =
4587                         &intel_crtc->config->base.adjusted_mode;
4588                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4589                 i915_reg_t reg = TRANS_DP_CTL(pipe);
4590                 temp = I915_READ(reg);
4591                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4592                           TRANS_DP_SYNC_MASK |
4593                           TRANS_DP_BPC_MASK);
4594                 temp |= TRANS_DP_OUTPUT_ENABLE;
4595                 temp |= bpc << 9; /* same format but at 11:9 */
4596
4597                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4598                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4599                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4600                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4601
4602                 switch (intel_trans_dp_port_sel(crtc)) {
4603                 case PORT_B:
4604                         temp |= TRANS_DP_PORT_SEL_B;
4605                         break;
4606                 case PORT_C:
4607                         temp |= TRANS_DP_PORT_SEL_C;
4608                         break;
4609                 case PORT_D:
4610                         temp |= TRANS_DP_PORT_SEL_D;
4611                         break;
4612                 default:
4613                         BUG();
4614                 }
4615
4616                 I915_WRITE(reg, temp);
4617         }
4618
4619         ironlake_enable_pch_transcoder(dev_priv, pipe);
4620 }
4621
4622 static void lpt_pch_enable(struct drm_crtc *crtc)
4623 {
4624         struct drm_device *dev = crtc->dev;
4625         struct drm_i915_private *dev_priv = to_i915(dev);
4626         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4627         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4628
4629         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4630
4631         lpt_program_iclkip(crtc);
4632
4633         /* Set transcoder timing. */
4634         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4635
4636         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4637 }
4638
4639 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4640 {
4641         struct drm_i915_private *dev_priv = to_i915(dev);
4642         i915_reg_t dslreg = PIPEDSL(pipe);
4643         u32 temp;
4644
4645         temp = I915_READ(dslreg);
4646         udelay(500);
4647         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4648                 if (wait_for(I915_READ(dslreg) != temp, 5))
4649                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4650         }
4651 }
4652
4653 static int
4654 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4655                   unsigned scaler_user, int *scaler_id, unsigned int rotation,
4656                   int src_w, int src_h, int dst_w, int dst_h)
4657 {
4658         struct intel_crtc_scaler_state *scaler_state =
4659                 &crtc_state->scaler_state;
4660         struct intel_crtc *intel_crtc =
4661                 to_intel_crtc(crtc_state->base.crtc);
4662         int need_scaling;
4663
4664         need_scaling = drm_rotation_90_or_270(rotation) ?
4665                 (src_h != dst_w || src_w != dst_h):
4666                 (src_w != dst_w || src_h != dst_h);
4667
4668         /*
4669          * if plane is being disabled or scaler is no more required or force detach
4670          *  - free scaler binded to this plane/crtc
4671          *  - in order to do this, update crtc->scaler_usage
4672          *
4673          * Here scaler state in crtc_state is set free so that
4674          * scaler can be assigned to other user. Actual register
4675          * update to free the scaler is done in plane/panel-fit programming.
4676          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4677          */
4678         if (force_detach || !need_scaling) {
4679                 if (*scaler_id >= 0) {
4680                         scaler_state->scaler_users &= ~(1 << scaler_user);
4681                         scaler_state->scalers[*scaler_id].in_use = 0;
4682
4683                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4684                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4685                                 intel_crtc->pipe, scaler_user, *scaler_id,
4686                                 scaler_state->scaler_users);
4687                         *scaler_id = -1;
4688                 }
4689                 return 0;
4690         }
4691
4692         /* range checks */
4693         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4694                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4695
4696                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4697                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4698                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4699                         "size is out of scaler range\n",
4700                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4701                 return -EINVAL;
4702         }
4703
4704         /* mark this plane as a scaler user in crtc_state */
4705         scaler_state->scaler_users |= (1 << scaler_user);
4706         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4707                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4708                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4709                 scaler_state->scaler_users);
4710
4711         return 0;
4712 }
4713
4714 /**
4715  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4716  *
4717  * @state: crtc's scaler state
4718  *
4719  * Return
4720  *     0 - scaler_usage updated successfully
4721  *    error - requested scaling cannot be supported or other error condition
4722  */
4723 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4724 {
4725         const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4726
4727         return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4728                 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4729                 state->pipe_src_w, state->pipe_src_h,
4730                 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4731 }
4732
4733 /**
4734  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4735  *
4736  * @state: crtc's scaler state
4737  * @plane_state: atomic plane state to update
4738  *
4739  * Return
4740  *     0 - scaler_usage updated successfully
4741  *    error - requested scaling cannot be supported or other error condition
4742  */
4743 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4744                                    struct intel_plane_state *plane_state)
4745 {
4746
4747         struct intel_plane *intel_plane =
4748                 to_intel_plane(plane_state->base.plane);
4749         struct drm_framebuffer *fb = plane_state->base.fb;
4750         int ret;
4751
4752         bool force_detach = !fb || !plane_state->base.visible;
4753
4754         ret = skl_update_scaler(crtc_state, force_detach,
4755                                 drm_plane_index(&intel_plane->base),
4756                                 &plane_state->scaler_id,
4757                                 plane_state->base.rotation,
4758                                 drm_rect_width(&plane_state->base.src) >> 16,
4759                                 drm_rect_height(&plane_state->base.src) >> 16,
4760                                 drm_rect_width(&plane_state->base.dst),
4761                                 drm_rect_height(&plane_state->base.dst));
4762
4763         if (ret || plane_state->scaler_id < 0)
4764                 return ret;
4765
4766         /* check colorkey */
4767         if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4768                 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4769                               intel_plane->base.base.id,
4770                               intel_plane->base.name);
4771                 return -EINVAL;
4772         }
4773
4774         /* Check src format */
4775         switch (fb->pixel_format) {
4776         case DRM_FORMAT_RGB565:
4777         case DRM_FORMAT_XBGR8888:
4778         case DRM_FORMAT_XRGB8888:
4779         case DRM_FORMAT_ABGR8888:
4780         case DRM_FORMAT_ARGB8888:
4781         case DRM_FORMAT_XRGB2101010:
4782         case DRM_FORMAT_XBGR2101010:
4783         case DRM_FORMAT_YUYV:
4784         case DRM_FORMAT_YVYU:
4785         case DRM_FORMAT_UYVY:
4786         case DRM_FORMAT_VYUY:
4787                 break;
4788         default:
4789                 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4790                               intel_plane->base.base.id, intel_plane->base.name,
4791                               fb->base.id, fb->pixel_format);
4792                 return -EINVAL;
4793         }
4794
4795         return 0;
4796 }
4797
4798 static void skylake_scaler_disable(struct intel_crtc *crtc)
4799 {
4800         int i;
4801
4802         for (i = 0; i < crtc->num_scalers; i++)
4803                 skl_detach_scaler(crtc, i);
4804 }
4805
4806 static void skylake_pfit_enable(struct intel_crtc *crtc)
4807 {
4808         struct drm_device *dev = crtc->base.dev;
4809         struct drm_i915_private *dev_priv = to_i915(dev);
4810         int pipe = crtc->pipe;
4811         struct intel_crtc_scaler_state *scaler_state =
4812                 &crtc->config->scaler_state;
4813
4814         DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4815
4816         if (crtc->config->pch_pfit.enabled) {
4817                 int id;
4818
4819                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4820                         DRM_ERROR("Requesting pfit without getting a scaler first\n");
4821                         return;
4822                 }
4823
4824                 id = scaler_state->scaler_id;
4825                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4826                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4827                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4828                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4829
4830                 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4831         }
4832 }
4833
4834 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4835 {
4836         struct drm_device *dev = crtc->base.dev;
4837         struct drm_i915_private *dev_priv = to_i915(dev);
4838         int pipe = crtc->pipe;
4839
4840         if (crtc->config->pch_pfit.enabled) {
4841                 /* Force use of hard-coded filter coefficients
4842                  * as some pre-programmed values are broken,
4843                  * e.g. x201.
4844                  */
4845                 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
4846                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4847                                                  PF_PIPE_SEL_IVB(pipe));
4848                 else
4849                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4850                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4851                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4852         }
4853 }
4854
4855 void hsw_enable_ips(struct intel_crtc *crtc)
4856 {
4857         struct drm_device *dev = crtc->base.dev;
4858         struct drm_i915_private *dev_priv = to_i915(dev);
4859
4860         if (!crtc->config->ips_enabled)
4861                 return;
4862
4863         /*
4864          * We can only enable IPS after we enable a plane and wait for a vblank
4865          * This function is called from post_plane_update, which is run after
4866          * a vblank wait.
4867          */
4868
4869         assert_plane_enabled(dev_priv, crtc->plane);
4870         if (IS_BROADWELL(dev_priv)) {
4871                 mutex_lock(&dev_priv->rps.hw_lock);
4872                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4873                 mutex_unlock(&dev_priv->rps.hw_lock);
4874                 /* Quoting Art Runyan: "its not safe to expect any particular
4875                  * value in IPS_CTL bit 31 after enabling IPS through the
4876                  * mailbox." Moreover, the mailbox may return a bogus state,
4877                  * so we need to just enable it and continue on.
4878                  */
4879         } else {
4880                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4881                 /* The bit only becomes 1 in the next vblank, so this wait here
4882                  * is essentially intel_wait_for_vblank. If we don't have this
4883                  * and don't wait for vblanks until the end of crtc_enable, then
4884                  * the HW state readout code will complain that the expected
4885                  * IPS_CTL value is not the one we read. */
4886                 if (intel_wait_for_register(dev_priv,
4887                                             IPS_CTL, IPS_ENABLE, IPS_ENABLE,
4888                                             50))
4889                         DRM_ERROR("Timed out waiting for IPS enable\n");
4890         }
4891 }
4892
4893 void hsw_disable_ips(struct intel_crtc *crtc)
4894 {
4895         struct drm_device *dev = crtc->base.dev;
4896         struct drm_i915_private *dev_priv = to_i915(dev);
4897
4898         if (!crtc->config->ips_enabled)
4899                 return;
4900
4901         assert_plane_enabled(dev_priv, crtc->plane);
4902         if (IS_BROADWELL(dev_priv)) {
4903                 mutex_lock(&dev_priv->rps.hw_lock);
4904                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4905                 mutex_unlock(&dev_priv->rps.hw_lock);
4906                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4907                 if (intel_wait_for_register(dev_priv,
4908                                             IPS_CTL, IPS_ENABLE, 0,
4909                                             42))
4910                         DRM_ERROR("Timed out waiting for IPS disable\n");
4911         } else {
4912                 I915_WRITE(IPS_CTL, 0);
4913                 POSTING_READ(IPS_CTL);
4914         }
4915
4916         /* We need to wait for a vblank before we can disable the plane. */
4917         intel_wait_for_vblank(dev_priv, crtc->pipe);
4918 }
4919
4920 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4921 {
4922         if (intel_crtc->overlay) {
4923                 struct drm_device *dev = intel_crtc->base.dev;
4924                 struct drm_i915_private *dev_priv = to_i915(dev);
4925
4926                 mutex_lock(&dev->struct_mutex);
4927                 dev_priv->mm.interruptible = false;
4928                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4929                 dev_priv->mm.interruptible = true;
4930                 mutex_unlock(&dev->struct_mutex);
4931         }
4932
4933         /* Let userspace switch the overlay on again. In most cases userspace
4934          * has to recompute where to put it anyway.
4935          */
4936 }
4937
4938 /**
4939  * intel_post_enable_primary - Perform operations after enabling primary plane
4940  * @crtc: the CRTC whose primary plane was just enabled
4941  *
4942  * Performs potentially sleeping operations that must be done after the primary
4943  * plane is enabled, such as updating FBC and IPS.  Note that this may be
4944  * called due to an explicit primary plane update, or due to an implicit
4945  * re-enable that is caused when a sprite plane is updated to no longer
4946  * completely hide the primary plane.
4947  */
4948 static void
4949 intel_post_enable_primary(struct drm_crtc *crtc)
4950 {
4951         struct drm_device *dev = crtc->dev;
4952         struct drm_i915_private *dev_priv = to_i915(dev);
4953         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4954         int pipe = intel_crtc->pipe;
4955
4956         /*
4957          * FIXME IPS should be fine as long as one plane is
4958          * enabled, but in practice it seems to have problems
4959          * when going from primary only to sprite only and vice
4960          * versa.
4961          */
4962         hsw_enable_ips(intel_crtc);
4963
4964         /*
4965          * Gen2 reports pipe underruns whenever all planes are disabled.
4966          * So don't enable underrun reporting before at least some planes
4967          * are enabled.
4968          * FIXME: Need to fix the logic to work when we turn off all planes
4969          * but leave the pipe running.
4970          */
4971         if (IS_GEN2(dev_priv))
4972                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4973
4974         /* Underruns don't always raise interrupts, so check manually. */
4975         intel_check_cpu_fifo_underruns(dev_priv);
4976         intel_check_pch_fifo_underruns(dev_priv);
4977 }
4978
4979 /* FIXME move all this to pre_plane_update() with proper state tracking */
4980 static void
4981 intel_pre_disable_primary(struct drm_crtc *crtc)
4982 {
4983         struct drm_device *dev = crtc->dev;
4984         struct drm_i915_private *dev_priv = to_i915(dev);
4985         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4986         int pipe = intel_crtc->pipe;
4987
4988         /*
4989          * Gen2 reports pipe underruns whenever all planes are disabled.
4990          * So diasble underrun reporting before all the planes get disabled.
4991          * FIXME: Need to fix the logic to work when we turn off all planes
4992          * but leave the pipe running.
4993          */
4994         if (IS_GEN2(dev_priv))
4995                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4996
4997         /*
4998          * FIXME IPS should be fine as long as one plane is
4999          * enabled, but in practice it seems to have problems
5000          * when going from primary only to sprite only and vice
5001          * versa.
5002          */
5003         hsw_disable_ips(intel_crtc);
5004 }
5005
5006 /* FIXME get rid of this and use pre_plane_update */
5007 static void
5008 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
5009 {
5010         struct drm_device *dev = crtc->dev;
5011         struct drm_i915_private *dev_priv = to_i915(dev);
5012         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5013         int pipe = intel_crtc->pipe;
5014
5015         intel_pre_disable_primary(crtc);
5016
5017         /*
5018          * Vblank time updates from the shadow to live plane control register
5019          * are blocked if the memory self-refresh mode is active at that
5020          * moment. So to make sure the plane gets truly disabled, disable
5021          * first the self-refresh mode. The self-refresh enable bit in turn
5022          * will be checked/applied by the HW only at the next frame start
5023          * event which is after the vblank start event, so we need to have a
5024          * wait-for-vblank between disabling the plane and the pipe.
5025          */
5026         if (HAS_GMCH_DISPLAY(dev_priv)) {
5027                 intel_set_memory_cxsr(dev_priv, false);
5028                 dev_priv->wm.vlv.cxsr = false;
5029                 intel_wait_for_vblank(dev_priv, pipe);
5030         }
5031 }
5032
5033 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
5034 {
5035         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5036         struct drm_atomic_state *old_state = old_crtc_state->base.state;
5037         struct intel_crtc_state *pipe_config =
5038                 to_intel_crtc_state(crtc->base.state);
5039         struct drm_plane *primary = crtc->base.primary;
5040         struct drm_plane_state *old_pri_state =
5041                 drm_atomic_get_existing_plane_state(old_state, primary);
5042
5043         intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
5044
5045         crtc->wm.cxsr_allowed = true;
5046
5047         if (pipe_config->update_wm_post && pipe_config->base.active)
5048                 intel_update_watermarks(crtc);
5049
5050         if (old_pri_state) {
5051                 struct intel_plane_state *primary_state =
5052                         to_intel_plane_state(primary->state);
5053                 struct intel_plane_state *old_primary_state =
5054                         to_intel_plane_state(old_pri_state);
5055
5056                 intel_fbc_post_update(crtc);
5057
5058                 if (primary_state->base.visible &&
5059                     (needs_modeset(&pipe_config->base) ||
5060                      !old_primary_state->base.visible))
5061                         intel_post_enable_primary(&crtc->base);
5062         }
5063 }
5064
5065 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
5066 {
5067         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5068         struct drm_device *dev = crtc->base.dev;
5069         struct drm_i915_private *dev_priv = to_i915(dev);
5070         struct intel_crtc_state *pipe_config =
5071                 to_intel_crtc_state(crtc->base.state);
5072         struct drm_atomic_state *old_state = old_crtc_state->base.state;
5073         struct drm_plane *primary = crtc->base.primary;
5074         struct drm_plane_state *old_pri_state =
5075                 drm_atomic_get_existing_plane_state(old_state, primary);
5076         bool modeset = needs_modeset(&pipe_config->base);
5077         struct intel_atomic_state *old_intel_state =
5078                 to_intel_atomic_state(old_state);
5079
5080         if (old_pri_state) {
5081                 struct intel_plane_state *primary_state =
5082                         to_intel_plane_state(primary->state);
5083                 struct intel_plane_state *old_primary_state =
5084                         to_intel_plane_state(old_pri_state);
5085
5086                 intel_fbc_pre_update(crtc, pipe_config, primary_state);
5087
5088                 if (old_primary_state->base.visible &&
5089                     (modeset || !primary_state->base.visible))
5090                         intel_pre_disable_primary(&crtc->base);
5091         }
5092
5093         if (pipe_config->disable_cxsr && HAS_GMCH_DISPLAY(dev_priv)) {
5094                 crtc->wm.cxsr_allowed = false;
5095
5096                 /*
5097                  * Vblank time updates from the shadow to live plane control register
5098                  * are blocked if the memory self-refresh mode is active at that
5099                  * moment. So to make sure the plane gets truly disabled, disable
5100                  * first the self-refresh mode. The self-refresh enable bit in turn
5101                  * will be checked/applied by the HW only at the next frame start
5102                  * event which is after the vblank start event, so we need to have a
5103                  * wait-for-vblank between disabling the plane and the pipe.
5104                  */
5105                 if (old_crtc_state->base.active) {
5106                         intel_set_memory_cxsr(dev_priv, false);
5107                         dev_priv->wm.vlv.cxsr = false;
5108                         intel_wait_for_vblank(dev_priv, crtc->pipe);
5109                 }
5110         }
5111
5112         /*
5113          * IVB workaround: must disable low power watermarks for at least
5114          * one frame before enabling scaling.  LP watermarks can be re-enabled
5115          * when scaling is disabled.
5116          *
5117          * WaCxSRDisabledForSpriteScaling:ivb
5118          */
5119         if (pipe_config->disable_lp_wm) {
5120                 ilk_disable_lp_wm(dev);
5121                 intel_wait_for_vblank(dev_priv, crtc->pipe);
5122         }
5123
5124         /*
5125          * If we're doing a modeset, we're done.  No need to do any pre-vblank
5126          * watermark programming here.
5127          */
5128         if (needs_modeset(&pipe_config->base))
5129                 return;
5130
5131         /*
5132          * For platforms that support atomic watermarks, program the
5133          * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
5134          * will be the intermediate values that are safe for both pre- and
5135          * post- vblank; when vblank happens, the 'active' values will be set
5136          * to the final 'target' values and we'll do this again to get the
5137          * optimal watermarks.  For gen9+ platforms, the values we program here
5138          * will be the final target values which will get automatically latched
5139          * at vblank time; no further programming will be necessary.
5140          *
5141          * If a platform hasn't been transitioned to atomic watermarks yet,
5142          * we'll continue to update watermarks the old way, if flags tell
5143          * us to.
5144          */
5145         if (dev_priv->display.initial_watermarks != NULL)
5146                 dev_priv->display.initial_watermarks(old_intel_state,
5147                                                      pipe_config);
5148         else if (pipe_config->update_wm_pre)
5149                 intel_update_watermarks(crtc);
5150 }
5151
5152 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
5153 {
5154         struct drm_device *dev = crtc->dev;
5155         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5156         struct drm_plane *p;
5157         int pipe = intel_crtc->pipe;
5158
5159         intel_crtc_dpms_overlay_disable(intel_crtc);
5160
5161         drm_for_each_plane_mask(p, dev, plane_mask)
5162                 to_intel_plane(p)->disable_plane(p, crtc);
5163
5164         /*
5165          * FIXME: Once we grow proper nuclear flip support out of this we need
5166          * to compute the mask of flip planes precisely. For the time being
5167          * consider this a flip to a NULL plane.
5168          */
5169         intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe));
5170 }
5171
5172 static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc,
5173                                           struct intel_crtc_state *crtc_state,
5174                                           struct drm_atomic_state *old_state)
5175 {
5176         struct drm_connector_state *old_conn_state;
5177         struct drm_connector *conn;
5178         int i;
5179
5180         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5181                 struct drm_connector_state *conn_state = conn->state;
5182                 struct intel_encoder *encoder =
5183                         to_intel_encoder(conn_state->best_encoder);
5184
5185                 if (conn_state->crtc != crtc)
5186                         continue;
5187
5188                 if (encoder->pre_pll_enable)
5189                         encoder->pre_pll_enable(encoder, crtc_state, conn_state);
5190         }
5191 }
5192
5193 static void intel_encoders_pre_enable(struct drm_crtc *crtc,
5194                                       struct intel_crtc_state *crtc_state,
5195                                       struct drm_atomic_state *old_state)
5196 {
5197         struct drm_connector_state *old_conn_state;
5198         struct drm_connector *conn;
5199         int i;
5200
5201         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5202                 struct drm_connector_state *conn_state = conn->state;
5203                 struct intel_encoder *encoder =
5204                         to_intel_encoder(conn_state->best_encoder);
5205
5206                 if (conn_state->crtc != crtc)
5207                         continue;
5208
5209                 if (encoder->pre_enable)
5210                         encoder->pre_enable(encoder, crtc_state, conn_state);
5211         }
5212 }
5213
5214 static void intel_encoders_enable(struct drm_crtc *crtc,
5215                                   struct intel_crtc_state *crtc_state,
5216                                   struct drm_atomic_state *old_state)
5217 {
5218         struct drm_connector_state *old_conn_state;
5219         struct drm_connector *conn;
5220         int i;
5221
5222         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5223                 struct drm_connector_state *conn_state = conn->state;
5224                 struct intel_encoder *encoder =
5225                         to_intel_encoder(conn_state->best_encoder);
5226
5227                 if (conn_state->crtc != crtc)
5228                         continue;
5229
5230                 encoder->enable(encoder, crtc_state, conn_state);
5231                 intel_opregion_notify_encoder(encoder, true);
5232         }
5233 }
5234
5235 static void intel_encoders_disable(struct drm_crtc *crtc,
5236                                    struct intel_crtc_state *old_crtc_state,
5237                                    struct drm_atomic_state *old_state)
5238 {
5239         struct drm_connector_state *old_conn_state;
5240         struct drm_connector *conn;
5241         int i;
5242
5243         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5244                 struct intel_encoder *encoder =
5245                         to_intel_encoder(old_conn_state->best_encoder);
5246
5247                 if (old_conn_state->crtc != crtc)
5248                         continue;
5249
5250                 intel_opregion_notify_encoder(encoder, false);
5251                 encoder->disable(encoder, old_crtc_state, old_conn_state);
5252         }
5253 }
5254
5255 static void intel_encoders_post_disable(struct drm_crtc *crtc,
5256                                         struct intel_crtc_state *old_crtc_state,
5257                                         struct drm_atomic_state *old_state)
5258 {
5259         struct drm_connector_state *old_conn_state;
5260         struct drm_connector *conn;
5261         int i;
5262
5263         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5264                 struct intel_encoder *encoder =
5265                         to_intel_encoder(old_conn_state->best_encoder);
5266
5267                 if (old_conn_state->crtc != crtc)
5268                         continue;
5269
5270                 if (encoder->post_disable)
5271                         encoder->post_disable(encoder, old_crtc_state, old_conn_state);
5272         }
5273 }
5274
5275 static void intel_encoders_post_pll_disable(struct drm_crtc *crtc,
5276                                             struct intel_crtc_state *old_crtc_state,
5277                                             struct drm_atomic_state *old_state)
5278 {
5279         struct drm_connector_state *old_conn_state;
5280         struct drm_connector *conn;
5281         int i;
5282
5283         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5284                 struct intel_encoder *encoder =
5285                         to_intel_encoder(old_conn_state->best_encoder);
5286
5287                 if (old_conn_state->crtc != crtc)
5288                         continue;
5289
5290                 if (encoder->post_pll_disable)
5291                         encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state);
5292         }
5293 }
5294
5295 static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
5296                                  struct drm_atomic_state *old_state)
5297 {
5298         struct drm_crtc *crtc = pipe_config->base.crtc;
5299         struct drm_device *dev = crtc->dev;
5300         struct drm_i915_private *dev_priv = to_i915(dev);
5301         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5302         int pipe = intel_crtc->pipe;
5303         struct intel_atomic_state *old_intel_state =
5304                 to_intel_atomic_state(old_state);
5305
5306         if (WARN_ON(intel_crtc->active))
5307                 return;
5308
5309         /*
5310          * Sometimes spurious CPU pipe underruns happen during FDI
5311          * training, at least with VGA+HDMI cloning. Suppress them.
5312          *
5313          * On ILK we get an occasional spurious CPU pipe underruns
5314          * between eDP port A enable and vdd enable. Also PCH port
5315          * enable seems to result in the occasional CPU pipe underrun.
5316          *
5317          * Spurious PCH underruns also occur during PCH enabling.
5318          */
5319         if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
5320                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5321         if (intel_crtc->config->has_pch_encoder)
5322                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5323
5324         if (intel_crtc->config->has_pch_encoder)
5325                 intel_prepare_shared_dpll(intel_crtc);
5326
5327         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5328                 intel_dp_set_m_n(intel_crtc, M1_N1);
5329
5330         intel_set_pipe_timings(intel_crtc);
5331         intel_set_pipe_src_size(intel_crtc);
5332
5333         if (intel_crtc->config->has_pch_encoder) {
5334                 intel_cpu_transcoder_set_m_n(intel_crtc,
5335                                      &intel_crtc->config->fdi_m_n, NULL);
5336         }
5337
5338         ironlake_set_pipeconf(crtc);
5339
5340         intel_crtc->active = true;
5341
5342         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5343
5344         if (intel_crtc->config->has_pch_encoder) {
5345                 /* Note: FDI PLL enabling _must_ be done before we enable the
5346                  * cpu pipes, hence this is separate from all the other fdi/pch
5347                  * enabling. */
5348                 ironlake_fdi_pll_enable(intel_crtc);
5349         } else {
5350                 assert_fdi_tx_disabled(dev_priv, pipe);
5351                 assert_fdi_rx_disabled(dev_priv, pipe);
5352         }
5353
5354         ironlake_pfit_enable(intel_crtc);
5355
5356         /*
5357          * On ILK+ LUT must be loaded before the pipe is running but with
5358          * clocks enabled
5359          */
5360         intel_color_load_luts(&pipe_config->base);
5361
5362         if (dev_priv->display.initial_watermarks != NULL)
5363                 dev_priv->display.initial_watermarks(old_intel_state, intel_crtc->config);
5364         intel_enable_pipe(intel_crtc);
5365
5366         if (intel_crtc->config->has_pch_encoder)
5367                 ironlake_pch_enable(crtc);
5368
5369         assert_vblank_disabled(crtc);
5370         drm_crtc_vblank_on(crtc);
5371
5372         intel_encoders_enable(crtc, pipe_config, old_state);
5373
5374         if (HAS_PCH_CPT(dev_priv))
5375                 cpt_verify_modeset(dev, intel_crtc->pipe);
5376
5377         /* Must wait for vblank to avoid spurious PCH FIFO underruns */
5378         if (intel_crtc->config->has_pch_encoder)
5379                 intel_wait_for_vblank(dev_priv, pipe);
5380         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5381         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5382 }
5383
5384 /* IPS only exists on ULT machines and is tied to pipe A. */
5385 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
5386 {
5387         return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
5388 }
5389
5390 static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
5391                                 struct drm_atomic_state *old_state)
5392 {
5393         struct drm_crtc *crtc = pipe_config->base.crtc;
5394         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5395         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5396         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
5397         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5398         struct intel_atomic_state *old_intel_state =
5399                 to_intel_atomic_state(old_state);
5400
5401         if (WARN_ON(intel_crtc->active))
5402                 return;
5403
5404         if (intel_crtc->config->has_pch_encoder)
5405                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5406                                                       false);
5407
5408         intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5409
5410         if (intel_crtc->config->shared_dpll)
5411                 intel_enable_shared_dpll(intel_crtc);
5412
5413         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5414                 intel_dp_set_m_n(intel_crtc, M1_N1);
5415
5416         if (!transcoder_is_dsi(cpu_transcoder))
5417                 intel_set_pipe_timings(intel_crtc);
5418
5419         intel_set_pipe_src_size(intel_crtc);
5420
5421         if (cpu_transcoder != TRANSCODER_EDP &&
5422             !transcoder_is_dsi(cpu_transcoder)) {
5423                 I915_WRITE(PIPE_MULT(cpu_transcoder),
5424                            intel_crtc->config->pixel_multiplier - 1);
5425         }
5426
5427         if (intel_crtc->config->has_pch_encoder) {
5428                 intel_cpu_transcoder_set_m_n(intel_crtc,
5429                                      &intel_crtc->config->fdi_m_n, NULL);
5430         }
5431
5432         if (!transcoder_is_dsi(cpu_transcoder))
5433                 haswell_set_pipeconf(crtc);
5434
5435         haswell_set_pipemisc(crtc);
5436
5437         intel_color_set_csc(&pipe_config->base);
5438
5439         intel_crtc->active = true;
5440
5441         if (intel_crtc->config->has_pch_encoder)
5442                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5443         else
5444                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5445
5446         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5447
5448         if (intel_crtc->config->has_pch_encoder)
5449                 dev_priv->display.fdi_link_train(crtc);
5450
5451         if (!transcoder_is_dsi(cpu_transcoder))
5452                 intel_ddi_enable_pipe_clock(intel_crtc);
5453
5454         if (INTEL_GEN(dev_priv) >= 9)
5455                 skylake_pfit_enable(intel_crtc);
5456         else
5457                 ironlake_pfit_enable(intel_crtc);
5458
5459         /*
5460          * On ILK+ LUT must be loaded before the pipe is running but with
5461          * clocks enabled
5462          */
5463         intel_color_load_luts(&pipe_config->base);
5464
5465         intel_ddi_set_pipe_settings(crtc);
5466         if (!transcoder_is_dsi(cpu_transcoder))
5467                 intel_ddi_enable_transcoder_func(crtc);
5468
5469         if (dev_priv->display.initial_watermarks != NULL)
5470                 dev_priv->display.initial_watermarks(old_intel_state,
5471                                                      pipe_config);
5472         else
5473                 intel_update_watermarks(intel_crtc);
5474
5475         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5476         if (!transcoder_is_dsi(cpu_transcoder))
5477                 intel_enable_pipe(intel_crtc);
5478
5479         if (intel_crtc->config->has_pch_encoder)
5480                 lpt_pch_enable(crtc);
5481
5482         if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5483                 intel_ddi_set_vc_payload_alloc(crtc, true);
5484
5485         assert_vblank_disabled(crtc);
5486         drm_crtc_vblank_on(crtc);
5487
5488         intel_encoders_enable(crtc, pipe_config, old_state);
5489
5490         if (intel_crtc->config->has_pch_encoder) {
5491                 intel_wait_for_vblank(dev_priv, pipe);
5492                 intel_wait_for_vblank(dev_priv, pipe);
5493                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5494                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5495                                                       true);
5496         }
5497
5498         /* If we change the relative order between pipe/planes enabling, we need
5499          * to change the workaround. */
5500         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5501         if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
5502                 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5503                 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5504         }
5505 }
5506
5507 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5508 {
5509         struct drm_device *dev = crtc->base.dev;
5510         struct drm_i915_private *dev_priv = to_i915(dev);
5511         int pipe = crtc->pipe;
5512
5513         /* To avoid upsetting the power well on haswell only disable the pfit if
5514          * it's in use. The hw state code will make sure we get this right. */
5515         if (force || crtc->config->pch_pfit.enabled) {
5516                 I915_WRITE(PF_CTL(pipe), 0);
5517                 I915_WRITE(PF_WIN_POS(pipe), 0);
5518                 I915_WRITE(PF_WIN_SZ(pipe), 0);
5519         }
5520 }
5521
5522 static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
5523                                   struct drm_atomic_state *old_state)
5524 {
5525         struct drm_crtc *crtc = old_crtc_state->base.crtc;
5526         struct drm_device *dev = crtc->dev;
5527         struct drm_i915_private *dev_priv = to_i915(dev);
5528         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5529         int pipe = intel_crtc->pipe;
5530
5531         /*
5532          * Sometimes spurious CPU pipe underruns happen when the
5533          * pipe is already disabled, but FDI RX/TX is still enabled.
5534          * Happens at least with VGA+HDMI cloning. Suppress them.
5535          */
5536         if (intel_crtc->config->has_pch_encoder) {
5537                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5538                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5539         }
5540
5541         intel_encoders_disable(crtc, old_crtc_state, old_state);
5542
5543         drm_crtc_vblank_off(crtc);
5544         assert_vblank_disabled(crtc);
5545
5546         intel_disable_pipe(intel_crtc);
5547
5548         ironlake_pfit_disable(intel_crtc, false);
5549
5550         if (intel_crtc->config->has_pch_encoder)
5551                 ironlake_fdi_disable(crtc);
5552
5553         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5554
5555         if (intel_crtc->config->has_pch_encoder) {
5556                 ironlake_disable_pch_transcoder(dev_priv, pipe);
5557
5558                 if (HAS_PCH_CPT(dev_priv)) {
5559                         i915_reg_t reg;
5560                         u32 temp;
5561
5562                         /* disable TRANS_DP_CTL */
5563                         reg = TRANS_DP_CTL(pipe);
5564                         temp = I915_READ(reg);
5565                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5566                                   TRANS_DP_PORT_SEL_MASK);
5567                         temp |= TRANS_DP_PORT_SEL_NONE;
5568                         I915_WRITE(reg, temp);
5569
5570                         /* disable DPLL_SEL */
5571                         temp = I915_READ(PCH_DPLL_SEL);
5572                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5573                         I915_WRITE(PCH_DPLL_SEL, temp);
5574                 }
5575
5576                 ironlake_fdi_pll_disable(intel_crtc);
5577         }
5578
5579         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5580         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5581 }
5582
5583 static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
5584                                  struct drm_atomic_state *old_state)
5585 {
5586         struct drm_crtc *crtc = old_crtc_state->base.crtc;
5587         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5588         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5589         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5590
5591         if (intel_crtc->config->has_pch_encoder)
5592                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5593                                                       false);
5594
5595         intel_encoders_disable(crtc, old_crtc_state, old_state);
5596
5597         drm_crtc_vblank_off(crtc);
5598         assert_vblank_disabled(crtc);
5599
5600         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5601         if (!transcoder_is_dsi(cpu_transcoder))
5602                 intel_disable_pipe(intel_crtc);
5603
5604         if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5605                 intel_ddi_set_vc_payload_alloc(crtc, false);
5606
5607         if (!transcoder_is_dsi(cpu_transcoder))
5608                 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5609
5610         if (INTEL_GEN(dev_priv) >= 9)
5611                 skylake_scaler_disable(intel_crtc);
5612         else
5613                 ironlake_pfit_disable(intel_crtc, false);
5614
5615         if (!transcoder_is_dsi(cpu_transcoder))
5616                 intel_ddi_disable_pipe_clock(intel_crtc);
5617
5618         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5619
5620         if (old_crtc_state->has_pch_encoder)
5621                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5622                                                       true);
5623 }
5624
5625 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5626 {
5627         struct drm_device *dev = crtc->base.dev;
5628         struct drm_i915_private *dev_priv = to_i915(dev);
5629         struct intel_crtc_state *pipe_config = crtc->config;
5630
5631         if (!pipe_config->gmch_pfit.control)
5632                 return;
5633
5634         /*
5635          * The panel fitter should only be adjusted whilst the pipe is disabled,
5636          * according to register description and PRM.
5637          */
5638         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5639         assert_pipe_disabled(dev_priv, crtc->pipe);
5640
5641         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5642         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5643
5644         /* Border color in case we don't scale up to the full screen. Black by
5645          * default, change to something else for debugging. */
5646         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5647 }
5648
5649 static enum intel_display_power_domain port_to_power_domain(enum port port)
5650 {
5651         switch (port) {
5652         case PORT_A:
5653                 return POWER_DOMAIN_PORT_DDI_A_LANES;
5654         case PORT_B:
5655                 return POWER_DOMAIN_PORT_DDI_B_LANES;
5656         case PORT_C:
5657                 return POWER_DOMAIN_PORT_DDI_C_LANES;
5658         case PORT_D:
5659                 return POWER_DOMAIN_PORT_DDI_D_LANES;
5660         case PORT_E:
5661                 return POWER_DOMAIN_PORT_DDI_E_LANES;
5662         default:
5663                 MISSING_CASE(port);
5664                 return POWER_DOMAIN_PORT_OTHER;
5665         }
5666 }
5667
5668 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5669 {
5670         switch (port) {
5671         case PORT_A:
5672                 return POWER_DOMAIN_AUX_A;
5673         case PORT_B:
5674                 return POWER_DOMAIN_AUX_B;
5675         case PORT_C:
5676                 return POWER_DOMAIN_AUX_C;
5677         case PORT_D:
5678                 return POWER_DOMAIN_AUX_D;
5679         case PORT_E:
5680                 /* FIXME: Check VBT for actual wiring of PORT E */
5681                 return POWER_DOMAIN_AUX_D;
5682         default:
5683                 MISSING_CASE(port);
5684                 return POWER_DOMAIN_AUX_A;
5685         }
5686 }
5687
5688 enum intel_display_power_domain
5689 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5690 {
5691         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
5692         struct intel_digital_port *intel_dig_port;
5693
5694         switch (intel_encoder->type) {
5695         case INTEL_OUTPUT_UNKNOWN:
5696                 /* Only DDI platforms should ever use this output type */
5697                 WARN_ON_ONCE(!HAS_DDI(dev_priv));
5698         case INTEL_OUTPUT_DP:
5699         case INTEL_OUTPUT_HDMI:
5700         case INTEL_OUTPUT_EDP:
5701                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5702                 return port_to_power_domain(intel_dig_port->port);
5703         case INTEL_OUTPUT_DP_MST:
5704                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5705                 return port_to_power_domain(intel_dig_port->port);
5706         case INTEL_OUTPUT_ANALOG:
5707                 return POWER_DOMAIN_PORT_CRT;
5708         case INTEL_OUTPUT_DSI:
5709                 return POWER_DOMAIN_PORT_DSI;
5710         default:
5711                 return POWER_DOMAIN_PORT_OTHER;
5712         }
5713 }
5714
5715 enum intel_display_power_domain
5716 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5717 {
5718         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
5719         struct intel_digital_port *intel_dig_port;
5720
5721         switch (intel_encoder->type) {
5722         case INTEL_OUTPUT_UNKNOWN:
5723         case INTEL_OUTPUT_HDMI:
5724                 /*
5725                  * Only DDI platforms should ever use these output types.
5726                  * We can get here after the HDMI detect code has already set
5727                  * the type of the shared encoder. Since we can't be sure
5728                  * what's the status of the given connectors, play safe and
5729                  * run the DP detection too.
5730                  */
5731                 WARN_ON_ONCE(!HAS_DDI(dev_priv));
5732         case INTEL_OUTPUT_DP:
5733         case INTEL_OUTPUT_EDP:
5734                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5735                 return port_to_aux_power_domain(intel_dig_port->port);
5736         case INTEL_OUTPUT_DP_MST:
5737                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5738                 return port_to_aux_power_domain(intel_dig_port->port);
5739         default:
5740                 MISSING_CASE(intel_encoder->type);
5741                 return POWER_DOMAIN_AUX_A;
5742         }
5743 }
5744
5745 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc,
5746                                             struct intel_crtc_state *crtc_state)
5747 {
5748         struct drm_device *dev = crtc->dev;
5749         struct drm_encoder *encoder;
5750         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5751         enum pipe pipe = intel_crtc->pipe;
5752         unsigned long mask;
5753         enum transcoder transcoder = crtc_state->cpu_transcoder;
5754
5755         if (!crtc_state->base.active)
5756                 return 0;
5757
5758         mask = BIT(POWER_DOMAIN_PIPE(pipe));
5759         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5760         if (crtc_state->pch_pfit.enabled ||
5761             crtc_state->pch_pfit.force_thru)
5762                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5763
5764         drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5765                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5766
5767                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5768         }
5769
5770         if (crtc_state->shared_dpll)
5771                 mask |= BIT(POWER_DOMAIN_PLLS);
5772
5773         return mask;
5774 }
5775
5776 static unsigned long
5777 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5778                                struct intel_crtc_state *crtc_state)
5779 {
5780         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5781         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5782         enum intel_display_power_domain domain;
5783         unsigned long domains, new_domains, old_domains;
5784
5785         old_domains = intel_crtc->enabled_power_domains;
5786         intel_crtc->enabled_power_domains = new_domains =
5787                 get_crtc_power_domains(crtc, crtc_state);
5788
5789         domains = new_domains & ~old_domains;
5790
5791         for_each_power_domain(domain, domains)
5792                 intel_display_power_get(dev_priv, domain);
5793
5794         return old_domains & ~new_domains;
5795 }
5796
5797 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5798                                       unsigned long domains)
5799 {
5800         enum intel_display_power_domain domain;
5801
5802         for_each_power_domain(domain, domains)
5803                 intel_display_power_put(dev_priv, domain);
5804 }
5805
5806 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5807 {
5808         int max_cdclk_freq = dev_priv->max_cdclk_freq;
5809
5810         if (INTEL_INFO(dev_priv)->gen >= 9 ||
5811             IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5812                 return max_cdclk_freq;
5813         else if (IS_CHERRYVIEW(dev_priv))
5814                 return max_cdclk_freq*95/100;
5815         else if (INTEL_INFO(dev_priv)->gen < 4)
5816                 return 2*max_cdclk_freq*90/100;
5817         else
5818                 return max_cdclk_freq*90/100;
5819 }
5820
5821 static int skl_calc_cdclk(int max_pixclk, int vco);
5822
5823 static void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
5824 {
5825         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5826                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5827                 int max_cdclk, vco;
5828
5829                 vco = dev_priv->skl_preferred_vco_freq;
5830                 WARN_ON(vco != 8100000 && vco != 8640000);
5831
5832                 /*
5833                  * Use the lower (vco 8640) cdclk values as a
5834                  * first guess. skl_calc_cdclk() will correct it
5835                  * if the preferred vco is 8100 instead.
5836                  */
5837                 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5838                         max_cdclk = 617143;
5839                 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5840                         max_cdclk = 540000;
5841                 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5842                         max_cdclk = 432000;
5843                 else
5844                         max_cdclk = 308571;
5845
5846                 dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
5847         } else if (IS_BROXTON(dev_priv)) {
5848                 dev_priv->max_cdclk_freq = 624000;
5849         } else if (IS_BROADWELL(dev_priv))  {
5850                 /*
5851                  * FIXME with extra cooling we can allow
5852                  * 540 MHz for ULX and 675 Mhz for ULT.
5853                  * How can we know if extra cooling is
5854                  * available? PCI ID, VTB, something else?
5855                  */
5856                 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5857                         dev_priv->max_cdclk_freq = 450000;
5858                 else if (IS_BDW_ULX(dev_priv))
5859                         dev_priv->max_cdclk_freq = 450000;
5860                 else if (IS_BDW_ULT(dev_priv))
5861                         dev_priv->max_cdclk_freq = 540000;
5862                 else
5863                         dev_priv->max_cdclk_freq = 675000;
5864         } else if (IS_CHERRYVIEW(dev_priv)) {
5865                 dev_priv->max_cdclk_freq = 320000;
5866         } else if (IS_VALLEYVIEW(dev_priv)) {
5867                 dev_priv->max_cdclk_freq = 400000;
5868         } else {
5869                 /* otherwise assume cdclk is fixed */
5870                 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5871         }
5872
5873         dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5874
5875         DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5876                          dev_priv->max_cdclk_freq);
5877
5878         DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5879                          dev_priv->max_dotclk_freq);
5880 }
5881
5882 static void intel_update_cdclk(struct drm_i915_private *dev_priv)
5883 {
5884         dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev_priv);
5885
5886         if (INTEL_GEN(dev_priv) >= 9)
5887                 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n",
5888                                  dev_priv->cdclk_freq, dev_priv->cdclk_pll.vco,
5889                                  dev_priv->cdclk_pll.ref);
5890         else
5891                 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5892                                  dev_priv->cdclk_freq);
5893
5894         /*
5895          * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
5896          * Programmng [sic] note: bit[9:2] should be programmed to the number
5897          * of cdclk that generates 4MHz reference clock freq which is used to
5898          * generate GMBus clock. This will vary with the cdclk freq.
5899          */
5900         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5901                 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5902 }
5903
5904 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5905 static int skl_cdclk_decimal(int cdclk)
5906 {
5907         return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
5908 }
5909
5910 static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
5911 {
5912         int ratio;
5913
5914         if (cdclk == dev_priv->cdclk_pll.ref)
5915                 return 0;
5916
5917         switch (cdclk) {
5918         default:
5919                 MISSING_CASE(cdclk);
5920         case 144000:
5921         case 288000:
5922         case 384000:
5923         case 576000:
5924                 ratio = 60;
5925                 break;
5926         case 624000:
5927                 ratio = 65;
5928                 break;
5929         }
5930
5931         return dev_priv->cdclk_pll.ref * ratio;
5932 }
5933
5934 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
5935 {
5936         I915_WRITE(BXT_DE_PLL_ENABLE, 0);
5937
5938         /* Timeout 200us */
5939         if (intel_wait_for_register(dev_priv,
5940                                     BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 0,
5941                                     1))
5942                 DRM_ERROR("timeout waiting for DE PLL unlock\n");
5943
5944         dev_priv->cdclk_pll.vco = 0;
5945 }
5946
5947 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
5948 {
5949         int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk_pll.ref);
5950         u32 val;
5951
5952         val = I915_READ(BXT_DE_PLL_CTL);
5953         val &= ~BXT_DE_PLL_RATIO_MASK;
5954         val |= BXT_DE_PLL_RATIO(ratio);
5955         I915_WRITE(BXT_DE_PLL_CTL, val);
5956
5957         I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5958
5959         /* Timeout 200us */
5960         if (intel_wait_for_register(dev_priv,
5961                                     BXT_DE_PLL_ENABLE,
5962                                     BXT_DE_PLL_LOCK,
5963                                     BXT_DE_PLL_LOCK,
5964                                     1))
5965                 DRM_ERROR("timeout waiting for DE PLL lock\n");
5966
5967         dev_priv->cdclk_pll.vco = vco;
5968 }
5969
5970 static void bxt_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
5971 {
5972         u32 val, divider;
5973         int vco, ret;
5974
5975         vco = bxt_de_pll_vco(dev_priv, cdclk);
5976
5977         DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
5978
5979         /* cdclk = vco / 2 / div{1,1.5,2,4} */
5980         switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
5981         case 8:
5982                 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5983                 break;
5984         case 4:
5985                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5986                 break;
5987         case 3:
5988                 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5989                 break;
5990         case 2:
5991                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5992                 break;
5993         default:
5994                 WARN_ON(cdclk != dev_priv->cdclk_pll.ref);
5995                 WARN_ON(vco != 0);
5996
5997                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5998                 break;
5999         }
6000
6001         /* Inform power controller of upcoming frequency change */
6002         mutex_lock(&dev_priv->rps.hw_lock);
6003         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
6004                                       0x80000000);
6005         mutex_unlock(&dev_priv->rps.hw_lock);
6006
6007         if (ret) {
6008                 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
6009                           ret, cdclk);
6010                 return;
6011         }
6012
6013         if (dev_priv->cdclk_pll.vco != 0 &&
6014             dev_priv->cdclk_pll.vco != vco)
6015                 bxt_de_pll_disable(dev_priv);
6016
6017         if (dev_priv->cdclk_pll.vco != vco)
6018                 bxt_de_pll_enable(dev_priv, vco);
6019
6020         val = divider | skl_cdclk_decimal(cdclk);
6021         /*
6022          * FIXME if only the cd2x divider needs changing, it could be done
6023          * without shutting off the pipe (if only one pipe is active).
6024          */
6025         val |= BXT_CDCLK_CD2X_PIPE_NONE;
6026         /*
6027          * Disable SSA Precharge when CD clock frequency < 500 MHz,
6028          * enable otherwise.
6029          */
6030         if (cdclk >= 500000)
6031                 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
6032         I915_WRITE(CDCLK_CTL, val);
6033
6034         mutex_lock(&dev_priv->rps.hw_lock);
6035         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
6036                                       DIV_ROUND_UP(cdclk, 25000));
6037         mutex_unlock(&dev_priv->rps.hw_lock);
6038
6039         if (ret) {
6040                 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
6041                           ret, cdclk);
6042                 return;
6043         }
6044
6045         intel_update_cdclk(dev_priv);
6046 }
6047
6048 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
6049 {
6050         u32 cdctl, expected;
6051
6052         intel_update_cdclk(dev_priv);
6053
6054         if (dev_priv->cdclk_pll.vco == 0 ||
6055             dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
6056                 goto sanitize;
6057
6058         /* DPLL okay; verify the cdclock
6059          *
6060          * Some BIOS versions leave an incorrect decimal frequency value and
6061          * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
6062          * so sanitize this register.
6063          */
6064         cdctl = I915_READ(CDCLK_CTL);
6065         /*
6066          * Let's ignore the pipe field, since BIOS could have configured the
6067          * dividers both synching to an active pipe, or asynchronously
6068          * (PIPE_NONE).
6069          */
6070         cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
6071
6072         expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
6073                    skl_cdclk_decimal(dev_priv->cdclk_freq);
6074         /*
6075          * Disable SSA Precharge when CD clock frequency < 500 MHz,
6076          * enable otherwise.
6077          */
6078         if (dev_priv->cdclk_freq >= 500000)
6079                 expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
6080
6081         if (cdctl == expected)
6082                 /* All well; nothing to sanitize */
6083                 return;
6084
6085 sanitize:
6086         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
6087
6088         /* force cdclk programming */
6089         dev_priv->cdclk_freq = 0;
6090
6091         /* force full PLL disable + enable */
6092         dev_priv->cdclk_pll.vco = -1;
6093 }
6094
6095 void bxt_init_cdclk(struct drm_i915_private *dev_priv)
6096 {
6097         bxt_sanitize_cdclk(dev_priv);
6098
6099         if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0)
6100                 return;
6101
6102         /*
6103          * FIXME:
6104          * - The initial CDCLK needs to be read from VBT.
6105          *   Need to make this change after VBT has changes for BXT.
6106          */
6107         bxt_set_cdclk(dev_priv, bxt_calc_cdclk(0));
6108 }
6109
6110 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
6111 {
6112         bxt_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref);
6113 }
6114
6115 static int skl_calc_cdclk(int max_pixclk, int vco)
6116 {
6117         if (vco == 8640000) {
6118                 if (max_pixclk > 540000)
6119                         return 617143;
6120                 else if (max_pixclk > 432000)
6121                         return 540000;
6122                 else if (max_pixclk > 308571)
6123                         return 432000;
6124                 else
6125                         return 308571;
6126         } else {
6127                 if (max_pixclk > 540000)
6128                         return 675000;
6129                 else if (max_pixclk > 450000)
6130                         return 540000;
6131                 else if (max_pixclk > 337500)
6132                         return 450000;
6133                 else
6134                         return 337500;
6135         }
6136 }
6137
6138 static void
6139 skl_dpll0_update(struct drm_i915_private *dev_priv)
6140 {
6141         u32 val;
6142
6143         dev_priv->cdclk_pll.ref = 24000;
6144         dev_priv->cdclk_pll.vco = 0;
6145
6146         val = I915_READ(LCPLL1_CTL);
6147         if ((val & LCPLL_PLL_ENABLE) == 0)
6148                 return;
6149
6150         if (WARN_ON((val & LCPLL_PLL_LOCK) == 0))
6151                 return;
6152
6153         val = I915_READ(DPLL_CTRL1);
6154
6155         if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
6156                             DPLL_CTRL1_SSC(SKL_DPLL0) |
6157                             DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
6158                     DPLL_CTRL1_OVERRIDE(SKL_DPLL0)))
6159                 return;
6160
6161         switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
6162         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
6163         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
6164         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
6165         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
6166                 dev_priv->cdclk_pll.vco = 8100000;
6167                 break;
6168         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
6169         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
6170                 dev_priv->cdclk_pll.vco = 8640000;
6171                 break;
6172         default:
6173                 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
6174                 break;
6175         }
6176 }
6177
6178 void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco)
6179 {
6180         bool changed = dev_priv->skl_preferred_vco_freq != vco;
6181
6182         dev_priv->skl_preferred_vco_freq = vco;
6183
6184         if (changed)
6185                 intel_update_max_cdclk(dev_priv);
6186 }
6187
6188 static void
6189 skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
6190 {
6191         int min_cdclk = skl_calc_cdclk(0, vco);
6192         u32 val;
6193
6194         WARN_ON(vco != 8100000 && vco != 8640000);
6195
6196         /* select the minimum CDCLK before enabling DPLL 0 */
6197         val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk);
6198         I915_WRITE(CDCLK_CTL, val);
6199         POSTING_READ(CDCLK_CTL);
6200
6201         /*
6202          * We always enable DPLL0 with the lowest link rate possible, but still
6203          * taking into account the VCO required to operate the eDP panel at the
6204          * desired frequency. The usual DP link rates operate with a VCO of
6205          * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
6206          * The modeset code is responsible for the selection of the exact link
6207          * rate later on, with the constraint of choosing a frequency that
6208          * works with vco.
6209          */
6210         val = I915_READ(DPLL_CTRL1);
6211
6212         val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
6213                  DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
6214         val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
6215         if (vco == 8640000)
6216                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
6217                                             SKL_DPLL0);
6218         else
6219                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
6220                                             SKL_DPLL0);
6221
6222         I915_WRITE(DPLL_CTRL1, val);
6223         POSTING_READ(DPLL_CTRL1);
6224
6225         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
6226
6227         if (intel_wait_for_register(dev_priv,
6228                                     LCPLL1_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
6229                                     5))
6230                 DRM_ERROR("DPLL0 not locked\n");
6231
6232         dev_priv->cdclk_pll.vco = vco;
6233
6234         /* We'll want to keep using the current vco from now on. */
6235         skl_set_preferred_cdclk_vco(dev_priv, vco);
6236 }
6237
6238 static void
6239 skl_dpll0_disable(struct drm_i915_private *dev_priv)
6240 {
6241         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
6242         if (intel_wait_for_register(dev_priv,
6243                                    LCPLL1_CTL, LCPLL_PLL_LOCK, 0,
6244                                    1))
6245                 DRM_ERROR("Couldn't disable DPLL0\n");
6246
6247         dev_priv->cdclk_pll.vco = 0;
6248 }
6249
6250 static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco)
6251 {
6252         u32 freq_select, pcu_ack;
6253         int ret;
6254
6255         WARN_ON((cdclk == 24000) != (vco == 0));
6256
6257         DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
6258
6259         mutex_lock(&dev_priv->rps.hw_lock);
6260         ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
6261                                 SKL_CDCLK_PREPARE_FOR_CHANGE,
6262                                 SKL_CDCLK_READY_FOR_CHANGE,
6263                                 SKL_CDCLK_READY_FOR_CHANGE, 3);
6264         mutex_unlock(&dev_priv->rps.hw_lock);
6265         if (ret) {
6266                 DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
6267                           ret);
6268                 return;
6269         }
6270
6271         /* set CDCLK_CTL */
6272         switch (cdclk) {
6273         case 450000:
6274         case 432000:
6275                 freq_select = CDCLK_FREQ_450_432;
6276                 pcu_ack = 1;
6277                 break;
6278         case 540000:
6279                 freq_select = CDCLK_FREQ_540;
6280                 pcu_ack = 2;
6281                 break;
6282         case 308571:
6283         case 337500:
6284         default:
6285                 freq_select = CDCLK_FREQ_337_308;
6286                 pcu_ack = 0;
6287                 break;
6288         case 617143:
6289         case 675000:
6290                 freq_select = CDCLK_FREQ_675_617;
6291                 pcu_ack = 3;
6292                 break;
6293         }
6294
6295         if (dev_priv->cdclk_pll.vco != 0 &&
6296             dev_priv->cdclk_pll.vco != vco)
6297                 skl_dpll0_disable(dev_priv);
6298
6299         if (dev_priv->cdclk_pll.vco != vco)
6300                 skl_dpll0_enable(dev_priv, vco);
6301
6302         I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk));
6303         POSTING_READ(CDCLK_CTL);
6304
6305         /* inform PCU of the change */
6306         mutex_lock(&dev_priv->rps.hw_lock);
6307         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
6308         mutex_unlock(&dev_priv->rps.hw_lock);
6309
6310         intel_update_cdclk(dev_priv);
6311 }
6312
6313 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
6314
6315 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
6316 {
6317         skl_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref, 0);
6318 }
6319
6320 void skl_init_cdclk(struct drm_i915_private *dev_priv)
6321 {
6322         int cdclk, vco;
6323
6324         skl_sanitize_cdclk(dev_priv);
6325
6326         if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0) {
6327                 /*
6328                  * Use the current vco as our initial
6329                  * guess as to what the preferred vco is.
6330                  */
6331                 if (dev_priv->skl_preferred_vco_freq == 0)
6332                         skl_set_preferred_cdclk_vco(dev_priv,
6333                                                     dev_priv->cdclk_pll.vco);
6334                 return;
6335         }
6336
6337         vco = dev_priv->skl_preferred_vco_freq;
6338         if (vco == 0)
6339                 vco = 8100000;
6340         cdclk = skl_calc_cdclk(0, vco);
6341
6342         skl_set_cdclk(dev_priv, cdclk, vco);
6343 }
6344
6345 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
6346 {
6347         uint32_t cdctl, expected;
6348
6349         /*
6350          * check if the pre-os intialized the display
6351          * There is SWF18 scratchpad register defined which is set by the
6352          * pre-os which can be used by the OS drivers to check the status
6353          */
6354         if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
6355                 goto sanitize;
6356
6357         intel_update_cdclk(dev_priv);
6358         /* Is PLL enabled and locked ? */
6359         if (dev_priv->cdclk_pll.vco == 0 ||
6360             dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
6361                 goto sanitize;
6362
6363         /* DPLL okay; verify the cdclock
6364          *
6365          * Noticed in some instances that the freq selection is correct but
6366          * decimal part is programmed wrong from BIOS where pre-os does not
6367          * enable display. Verify the same as well.
6368          */
6369         cdctl = I915_READ(CDCLK_CTL);
6370         expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
6371                 skl_cdclk_decimal(dev_priv->cdclk_freq);
6372         if (cdctl == expected)
6373                 /* All well; nothing to sanitize */
6374                 return;
6375
6376 sanitize:
6377         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
6378
6379         /* force cdclk programming */
6380         dev_priv->cdclk_freq = 0;
6381         /* force full PLL disable + enable */
6382         dev_priv->cdclk_pll.vco = -1;
6383 }
6384
6385 /* Adjust CDclk dividers to allow high res or save power if possible */
6386 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
6387 {
6388         struct drm_i915_private *dev_priv = to_i915(dev);
6389         u32 val, cmd;
6390
6391         WARN_ON(dev_priv->display.get_display_clock_speed(dev_priv)
6392                                         != dev_priv->cdclk_freq);
6393
6394         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
6395                 cmd = 2;
6396         else if (cdclk == 266667)
6397                 cmd = 1;
6398         else
6399                 cmd = 0;
6400
6401         mutex_lock(&dev_priv->rps.hw_lock);
6402         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
6403         val &= ~DSPFREQGUAR_MASK;
6404         val |= (cmd << DSPFREQGUAR_SHIFT);
6405         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
6406         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
6407                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
6408                      50)) {
6409                 DRM_ERROR("timed out waiting for CDclk change\n");
6410         }
6411         mutex_unlock(&dev_priv->rps.hw_lock);
6412
6413         mutex_lock(&dev_priv->sb_lock);
6414
6415         if (cdclk == 400000) {
6416                 u32 divider;
6417
6418                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
6419
6420                 /* adjust cdclk divider */
6421                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6422                 val &= ~CCK_FREQUENCY_VALUES;
6423                 val |= divider;
6424                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
6425
6426                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
6427                               CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
6428                              50))
6429                         DRM_ERROR("timed out waiting for CDclk change\n");
6430         }
6431
6432         /* adjust self-refresh exit latency value */
6433         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
6434         val &= ~0x7f;
6435
6436         /*
6437          * For high bandwidth configs, we set a higher latency in the bunit
6438          * so that the core display fetch happens in time to avoid underruns.
6439          */
6440         if (cdclk == 400000)
6441                 val |= 4500 / 250; /* 4.5 usec */
6442         else
6443                 val |= 3000 / 250; /* 3.0 usec */
6444         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
6445
6446         mutex_unlock(&dev_priv->sb_lock);
6447
6448         intel_update_cdclk(dev_priv);
6449 }
6450
6451 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
6452 {
6453         struct drm_i915_private *dev_priv = to_i915(dev);
6454         u32 val, cmd;
6455
6456         WARN_ON(dev_priv->display.get_display_clock_speed(dev_priv)
6457                                                 != dev_priv->cdclk_freq);
6458
6459         switch (cdclk) {
6460         case 333333:
6461         case 320000:
6462         case 266667:
6463         case 200000:
6464                 break;
6465         default:
6466                 MISSING_CASE(cdclk);
6467                 return;
6468         }
6469
6470         /*
6471          * Specs are full of misinformation, but testing on actual
6472          * hardware has shown that we just need to write the desired
6473          * CCK divider into the Punit register.
6474          */
6475         cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
6476
6477         mutex_lock(&dev_priv->rps.hw_lock);
6478         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
6479         val &= ~DSPFREQGUAR_MASK_CHV;
6480         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
6481         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
6482         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
6483                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
6484                      50)) {
6485                 DRM_ERROR("timed out waiting for CDclk change\n");
6486         }
6487         mutex_unlock(&dev_priv->rps.hw_lock);
6488
6489         intel_update_cdclk(dev_priv);
6490 }
6491
6492 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
6493                                  int max_pixclk)
6494 {
6495         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
6496         int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
6497
6498         /*
6499          * Really only a few cases to deal with, as only 4 CDclks are supported:
6500          *   200MHz
6501          *   267MHz
6502          *   320/333MHz (depends on HPLL freq)
6503          *   400MHz (VLV only)
6504          * So we check to see whether we're above 90% (VLV) or 95% (CHV)
6505          * of the lower bin and adjust if needed.
6506          *
6507          * We seem to get an unstable or solid color picture at 200MHz.
6508          * Not sure what's wrong. For now use 200MHz only when all pipes
6509          * are off.
6510          */
6511         if (!IS_CHERRYVIEW(dev_priv) &&
6512             max_pixclk > freq_320*limit/100)
6513                 return 400000;
6514         else if (max_pixclk > 266667*limit/100)
6515                 return freq_320;
6516         else if (max_pixclk > 0)
6517                 return 266667;
6518         else
6519                 return 200000;
6520 }
6521
6522 static int bxt_calc_cdclk(int max_pixclk)
6523 {
6524         if (max_pixclk > 576000)
6525                 return 624000;
6526         else if (max_pixclk > 384000)
6527                 return 576000;
6528         else if (max_pixclk > 288000)
6529                 return 384000;
6530         else if (max_pixclk > 144000)
6531                 return 288000;
6532         else
6533                 return 144000;
6534 }
6535
6536 /* Compute the max pixel clock for new configuration. */
6537 static int intel_mode_max_pixclk(struct drm_device *dev,
6538                                  struct drm_atomic_state *state)
6539 {
6540         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
6541         struct drm_i915_private *dev_priv = to_i915(dev);
6542         struct drm_crtc *crtc;
6543         struct drm_crtc_state *crtc_state;
6544         unsigned max_pixclk = 0, i;
6545         enum pipe pipe;
6546
6547         memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
6548                sizeof(intel_state->min_pixclk));
6549
6550         for_each_crtc_in_state(state, crtc, crtc_state, i) {
6551                 int pixclk = 0;
6552
6553                 if (crtc_state->enable)
6554                         pixclk = crtc_state->adjusted_mode.crtc_clock;
6555
6556                 intel_state->min_pixclk[i] = pixclk;
6557         }
6558
6559         for_each_pipe(dev_priv, pipe)
6560                 max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk);
6561
6562         return max_pixclk;
6563 }
6564
6565 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
6566 {
6567         struct drm_device *dev = state->dev;
6568         struct drm_i915_private *dev_priv = to_i915(dev);
6569         int max_pixclk = intel_mode_max_pixclk(dev, state);
6570         struct intel_atomic_state *intel_state =
6571                 to_intel_atomic_state(state);
6572
6573         intel_state->cdclk = intel_state->dev_cdclk =
6574                 valleyview_calc_cdclk(dev_priv, max_pixclk);
6575
6576         if (!intel_state->active_crtcs)
6577                 intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0);
6578
6579         return 0;
6580 }
6581
6582 static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
6583 {
6584         int max_pixclk = ilk_max_pixel_rate(state);
6585         struct intel_atomic_state *intel_state =
6586                 to_intel_atomic_state(state);
6587
6588         intel_state->cdclk = intel_state->dev_cdclk =
6589                 bxt_calc_cdclk(max_pixclk);
6590
6591         if (!intel_state->active_crtcs)
6592                 intel_state->dev_cdclk = bxt_calc_cdclk(0);
6593
6594         return 0;
6595 }
6596
6597 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6598 {
6599         unsigned int credits, default_credits;
6600
6601         if (IS_CHERRYVIEW(dev_priv))
6602                 default_credits = PFI_CREDIT(12);
6603         else
6604                 default_credits = PFI_CREDIT(8);
6605
6606         if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
6607                 /* CHV suggested value is 31 or 63 */
6608                 if (IS_CHERRYVIEW(dev_priv))
6609                         credits = PFI_CREDIT_63;
6610                 else
6611                         credits = PFI_CREDIT(15);
6612         } else {
6613                 credits = default_credits;
6614         }
6615
6616         /*
6617          * WA - write default credits before re-programming
6618          * FIXME: should we also set the resend bit here?
6619          */
6620         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6621                    default_credits);
6622
6623         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6624                    credits | PFI_CREDIT_RESEND);
6625
6626         /*
6627          * FIXME is this guaranteed to clear
6628          * immediately or should we poll for it?
6629          */
6630         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6631 }
6632
6633 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6634 {
6635         struct drm_device *dev = old_state->dev;
6636         struct drm_i915_private *dev_priv = to_i915(dev);
6637         struct intel_atomic_state *old_intel_state =
6638                 to_intel_atomic_state(old_state);
6639         unsigned req_cdclk = old_intel_state->dev_cdclk;
6640
6641         /*
6642          * FIXME: We can end up here with all power domains off, yet
6643          * with a CDCLK frequency other than the minimum. To account
6644          * for this take the PIPE-A power domain, which covers the HW
6645          * blocks needed for the following programming. This can be
6646          * removed once it's guaranteed that we get here either with
6647          * the minimum CDCLK set, or the required power domains
6648          * enabled.
6649          */
6650         intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6651
6652         if (IS_CHERRYVIEW(dev_priv))
6653                 cherryview_set_cdclk(dev, req_cdclk);
6654         else
6655                 valleyview_set_cdclk(dev, req_cdclk);
6656
6657         vlv_program_pfi_credits(dev_priv);
6658
6659         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6660 }
6661
6662 static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
6663                                    struct drm_atomic_state *old_state)
6664 {
6665         struct drm_crtc *crtc = pipe_config->base.crtc;
6666         struct drm_device *dev = crtc->dev;
6667         struct drm_i915_private *dev_priv = to_i915(dev);
6668         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6669         int pipe = intel_crtc->pipe;
6670
6671         if (WARN_ON(intel_crtc->active))
6672                 return;
6673
6674         if (intel_crtc_has_dp_encoder(intel_crtc->config))
6675                 intel_dp_set_m_n(intel_crtc, M1_N1);
6676
6677         intel_set_pipe_timings(intel_crtc);
6678         intel_set_pipe_src_size(intel_crtc);
6679
6680         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
6681                 struct drm_i915_private *dev_priv = to_i915(dev);
6682
6683                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6684                 I915_WRITE(CHV_CANVAS(pipe), 0);
6685         }
6686
6687         i9xx_set_pipeconf(intel_crtc);
6688
6689         intel_crtc->active = true;
6690
6691         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6692
6693         intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
6694
6695         if (IS_CHERRYVIEW(dev_priv)) {
6696                 chv_prepare_pll(intel_crtc, intel_crtc->config);
6697                 chv_enable_pll(intel_crtc, intel_crtc->config);
6698         } else {
6699                 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6700                 vlv_enable_pll(intel_crtc, intel_crtc->config);
6701         }
6702
6703         intel_encoders_pre_enable(crtc, pipe_config, old_state);
6704
6705         i9xx_pfit_enable(intel_crtc);
6706
6707         intel_color_load_luts(&pipe_config->base);
6708
6709         intel_update_watermarks(intel_crtc);
6710         intel_enable_pipe(intel_crtc);
6711
6712         assert_vblank_disabled(crtc);
6713         drm_crtc_vblank_on(crtc);
6714
6715         intel_encoders_enable(crtc, pipe_config, old_state);
6716 }
6717
6718 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6719 {
6720         struct drm_device *dev = crtc->base.dev;
6721         struct drm_i915_private *dev_priv = to_i915(dev);
6722
6723         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6724         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6725 }
6726
6727 static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
6728                              struct drm_atomic_state *old_state)
6729 {
6730         struct drm_crtc *crtc = pipe_config->base.crtc;
6731         struct drm_device *dev = crtc->dev;
6732         struct drm_i915_private *dev_priv = to_i915(dev);
6733         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6734         enum pipe pipe = intel_crtc->pipe;
6735
6736         if (WARN_ON(intel_crtc->active))
6737                 return;
6738
6739         i9xx_set_pll_dividers(intel_crtc);
6740
6741         if (intel_crtc_has_dp_encoder(intel_crtc->config))
6742                 intel_dp_set_m_n(intel_crtc, M1_N1);
6743
6744         intel_set_pipe_timings(intel_crtc);
6745         intel_set_pipe_src_size(intel_crtc);
6746
6747         i9xx_set_pipeconf(intel_crtc);
6748
6749         intel_crtc->active = true;
6750
6751         if (!IS_GEN2(dev_priv))
6752                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6753
6754         intel_encoders_pre_enable(crtc, pipe_config, old_state);
6755
6756         i9xx_enable_pll(intel_crtc);
6757
6758         i9xx_pfit_enable(intel_crtc);
6759
6760         intel_color_load_luts(&pipe_config->base);
6761
6762         intel_update_watermarks(intel_crtc);
6763         intel_enable_pipe(intel_crtc);
6764
6765         assert_vblank_disabled(crtc);
6766         drm_crtc_vblank_on(crtc);
6767
6768         intel_encoders_enable(crtc, pipe_config, old_state);
6769 }
6770
6771 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6772 {
6773         struct drm_device *dev = crtc->base.dev;
6774         struct drm_i915_private *dev_priv = to_i915(dev);
6775
6776         if (!crtc->config->gmch_pfit.control)
6777                 return;
6778
6779         assert_pipe_disabled(dev_priv, crtc->pipe);
6780
6781         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6782                          I915_READ(PFIT_CONTROL));
6783         I915_WRITE(PFIT_CONTROL, 0);
6784 }
6785
6786 static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
6787                               struct drm_atomic_state *old_state)
6788 {
6789         struct drm_crtc *crtc = old_crtc_state->base.crtc;
6790         struct drm_device *dev = crtc->dev;
6791         struct drm_i915_private *dev_priv = to_i915(dev);
6792         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6793         int pipe = intel_crtc->pipe;
6794
6795         /*
6796          * On gen2 planes are double buffered but the pipe isn't, so we must
6797          * wait for planes to fully turn off before disabling the pipe.
6798          */
6799         if (IS_GEN2(dev_priv))
6800                 intel_wait_for_vblank(dev_priv, pipe);
6801
6802         intel_encoders_disable(crtc, old_crtc_state, old_state);
6803
6804         drm_crtc_vblank_off(crtc);
6805         assert_vblank_disabled(crtc);
6806
6807         intel_disable_pipe(intel_crtc);
6808
6809         i9xx_pfit_disable(intel_crtc);
6810
6811         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
6812
6813         if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) {
6814                 if (IS_CHERRYVIEW(dev_priv))
6815                         chv_disable_pll(dev_priv, pipe);
6816                 else if (IS_VALLEYVIEW(dev_priv))
6817                         vlv_disable_pll(dev_priv, pipe);
6818                 else
6819                         i9xx_disable_pll(intel_crtc);
6820         }
6821
6822         intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
6823
6824         if (!IS_GEN2(dev_priv))
6825                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6826 }
6827
6828 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6829 {
6830         struct intel_encoder *encoder;
6831         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6832         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6833         enum intel_display_power_domain domain;
6834         unsigned long domains;
6835         struct drm_atomic_state *state;
6836         struct intel_crtc_state *crtc_state;
6837         int ret;
6838
6839         if (!intel_crtc->active)
6840                 return;
6841
6842         if (to_intel_plane_state(crtc->primary->state)->base.visible) {
6843                 WARN_ON(intel_crtc->flip_work);
6844
6845                 intel_pre_disable_primary_noatomic(crtc);
6846
6847                 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
6848                 to_intel_plane_state(crtc->primary->state)->base.visible = false;
6849         }
6850
6851         state = drm_atomic_state_alloc(crtc->dev);
6852         state->acquire_ctx = crtc->dev->mode_config.acquire_ctx;
6853
6854         /* Everything's already locked, -EDEADLK can't happen. */
6855         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
6856         ret = drm_atomic_add_affected_connectors(state, crtc);
6857
6858         WARN_ON(IS_ERR(crtc_state) || ret);
6859
6860         dev_priv->display.crtc_disable(crtc_state, state);
6861
6862         drm_atomic_state_put(state);
6863
6864         DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
6865                       crtc->base.id, crtc->name);
6866
6867         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
6868         crtc->state->active = false;
6869         intel_crtc->active = false;
6870         crtc->enabled = false;
6871         crtc->state->connector_mask = 0;
6872         crtc->state->encoder_mask = 0;
6873
6874         for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
6875                 encoder->base.crtc = NULL;
6876
6877         intel_fbc_disable(intel_crtc);
6878         intel_update_watermarks(intel_crtc);
6879         intel_disable_shared_dpll(intel_crtc);
6880
6881         domains = intel_crtc->enabled_power_domains;
6882         for_each_power_domain(domain, domains)
6883                 intel_display_power_put(dev_priv, domain);
6884         intel_crtc->enabled_power_domains = 0;
6885
6886         dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6887         dev_priv->min_pixclk[intel_crtc->pipe] = 0;
6888 }
6889
6890 /*
6891  * turn all crtc's off, but do not adjust state
6892  * This has to be paired with a call to intel_modeset_setup_hw_state.
6893  */
6894 int intel_display_suspend(struct drm_device *dev)
6895 {
6896         struct drm_i915_private *dev_priv = to_i915(dev);
6897         struct drm_atomic_state *state;
6898         int ret;
6899
6900         state = drm_atomic_helper_suspend(dev);
6901         ret = PTR_ERR_OR_ZERO(state);
6902         if (ret)
6903                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6904         else
6905                 dev_priv->modeset_restore_state = state;
6906         return ret;
6907 }
6908
6909 void intel_encoder_destroy(struct drm_encoder *encoder)
6910 {
6911         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6912
6913         drm_encoder_cleanup(encoder);
6914         kfree(intel_encoder);
6915 }
6916
6917 /* Cross check the actual hw state with our own modeset state tracking (and it's
6918  * internal consistency). */
6919 static void intel_connector_verify_state(struct intel_connector *connector)
6920 {
6921         struct drm_crtc *crtc = connector->base.state->crtc;
6922
6923         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6924                       connector->base.base.id,
6925                       connector->base.name);
6926
6927         if (connector->get_hw_state(connector)) {
6928                 struct intel_encoder *encoder = connector->encoder;
6929                 struct drm_connector_state *conn_state = connector->base.state;
6930
6931                 I915_STATE_WARN(!crtc,
6932                          "connector enabled without attached crtc\n");
6933
6934                 if (!crtc)
6935                         return;
6936
6937                 I915_STATE_WARN(!crtc->state->active,
6938                       "connector is active, but attached crtc isn't\n");
6939
6940                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6941                         return;
6942
6943                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6944                         "atomic encoder doesn't match attached encoder\n");
6945
6946                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6947                         "attached encoder crtc differs from connector crtc\n");
6948         } else {
6949                 I915_STATE_WARN(crtc && crtc->state->active,
6950                         "attached crtc is active, but connector isn't\n");
6951                 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6952                         "best encoder set without crtc!\n");
6953         }
6954 }
6955
6956 int intel_connector_init(struct intel_connector *connector)
6957 {
6958         drm_atomic_helper_connector_reset(&connector->base);
6959
6960         if (!connector->base.state)
6961                 return -ENOMEM;
6962
6963         return 0;
6964 }
6965
6966 struct intel_connector *intel_connector_alloc(void)
6967 {
6968         struct intel_connector *connector;
6969
6970         connector = kzalloc(sizeof *connector, GFP_KERNEL);
6971         if (!connector)
6972                 return NULL;
6973
6974         if (intel_connector_init(connector) < 0) {
6975                 kfree(connector);
6976                 return NULL;
6977         }
6978
6979         return connector;
6980 }
6981
6982 /* Simple connector->get_hw_state implementation for encoders that support only
6983  * one connector and no cloning and hence the encoder state determines the state
6984  * of the connector. */
6985 bool intel_connector_get_hw_state(struct intel_connector *connector)
6986 {
6987         enum pipe pipe = 0;
6988         struct intel_encoder *encoder = connector->encoder;
6989
6990         return encoder->get_hw_state(encoder, &pipe);
6991 }
6992
6993 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6994 {
6995         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6996                 return crtc_state->fdi_lanes;
6997
6998         return 0;
6999 }
7000
7001 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
7002                                      struct intel_crtc_state *pipe_config)
7003 {
7004         struct drm_i915_private *dev_priv = to_i915(dev);
7005         struct drm_atomic_state *state = pipe_config->base.state;
7006         struct intel_crtc *other_crtc;
7007         struct intel_crtc_state *other_crtc_state;
7008
7009         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
7010                       pipe_name(pipe), pipe_config->fdi_lanes);
7011         if (pipe_config->fdi_lanes > 4) {
7012                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
7013                               pipe_name(pipe), pipe_config->fdi_lanes);
7014                 return -EINVAL;
7015         }
7016
7017         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
7018                 if (pipe_config->fdi_lanes > 2) {
7019                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
7020                                       pipe_config->fdi_lanes);
7021                         return -EINVAL;
7022                 } else {
7023                         return 0;
7024                 }
7025         }
7026
7027         if (INTEL_INFO(dev_priv)->num_pipes == 2)
7028                 return 0;
7029
7030         /* Ivybridge 3 pipe is really complicated */
7031         switch (pipe) {
7032         case PIPE_A:
7033                 return 0;
7034         case PIPE_B:
7035                 if (pipe_config->fdi_lanes <= 2)
7036                         return 0;
7037
7038                 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C);
7039                 other_crtc_state =
7040                         intel_atomic_get_crtc_state(state, other_crtc);
7041                 if (IS_ERR(other_crtc_state))
7042                         return PTR_ERR(other_crtc_state);
7043
7044                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
7045                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
7046                                       pipe_name(pipe), pipe_config->fdi_lanes);
7047                         return -EINVAL;
7048                 }
7049                 return 0;
7050         case PIPE_C:
7051                 if (pipe_config->fdi_lanes > 2) {
7052                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
7053                                       pipe_name(pipe), pipe_config->fdi_lanes);
7054                         return -EINVAL;
7055                 }
7056
7057                 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B);
7058                 other_crtc_state =
7059                         intel_atomic_get_crtc_state(state, other_crtc);
7060                 if (IS_ERR(other_crtc_state))
7061                         return PTR_ERR(other_crtc_state);
7062
7063                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
7064                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
7065                         return -EINVAL;
7066                 }
7067                 return 0;
7068         default:
7069                 BUG();
7070         }
7071 }
7072
7073 #define RETRY 1
7074 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
7075                                        struct intel_crtc_state *pipe_config)
7076 {
7077         struct drm_device *dev = intel_crtc->base.dev;
7078         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
7079         int lane, link_bw, fdi_dotclock, ret;
7080         bool needs_recompute = false;
7081
7082 retry:
7083         /* FDI is a binary signal running at ~2.7GHz, encoding
7084          * each output octet as 10 bits. The actual frequency
7085          * is stored as a divider into a 100MHz clock, and the
7086          * mode pixel clock is stored in units of 1KHz.
7087          * Hence the bw of each lane in terms of the mode signal
7088          * is:
7089          */
7090         link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
7091
7092         fdi_dotclock = adjusted_mode->crtc_clock;
7093
7094         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
7095                                            pipe_config->pipe_bpp);
7096
7097         pipe_config->fdi_lanes = lane;
7098
7099         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
7100                                link_bw, &pipe_config->fdi_m_n);
7101
7102         ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
7103         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
7104                 pipe_config->pipe_bpp -= 2*3;
7105                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
7106                               pipe_config->pipe_bpp);
7107                 needs_recompute = true;
7108                 pipe_config->bw_constrained = true;
7109
7110                 goto retry;
7111         }
7112
7113         if (needs_recompute)
7114                 return RETRY;
7115
7116         return ret;
7117 }
7118
7119 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
7120                                      struct intel_crtc_state *pipe_config)
7121 {
7122         if (pipe_config->pipe_bpp > 24)
7123                 return false;
7124
7125         /* HSW can handle pixel rate up to cdclk? */
7126         if (IS_HASWELL(dev_priv))
7127                 return true;
7128
7129         /*
7130          * We compare against max which means we must take
7131          * the increased cdclk requirement into account when
7132          * calculating the new cdclk.
7133          *
7134          * Should measure whether using a lower cdclk w/o IPS
7135          */
7136         return ilk_pipe_pixel_rate(pipe_config) <=
7137                 dev_priv->max_cdclk_freq * 95 / 100;
7138 }
7139
7140 static void hsw_compute_ips_config(struct intel_crtc *crtc,
7141                                    struct intel_crtc_state *pipe_config)
7142 {
7143         struct drm_device *dev = crtc->base.dev;
7144         struct drm_i915_private *dev_priv = to_i915(dev);
7145
7146         pipe_config->ips_enabled = i915.enable_ips &&
7147                 hsw_crtc_supports_ips(crtc) &&
7148                 pipe_config_supports_ips(dev_priv, pipe_config);
7149 }
7150
7151 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
7152 {
7153         const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7154
7155         /* GDG double wide on either pipe, otherwise pipe A only */
7156         return INTEL_INFO(dev_priv)->gen < 4 &&
7157                 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
7158 }
7159
7160 static int intel_crtc_compute_config(struct intel_crtc *crtc,
7161                                      struct intel_crtc_state *pipe_config)
7162 {
7163         struct drm_device *dev = crtc->base.dev;
7164         struct drm_i915_private *dev_priv = to_i915(dev);
7165         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
7166         int clock_limit = dev_priv->max_dotclk_freq;
7167
7168         if (INTEL_GEN(dev_priv) < 4) {
7169                 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
7170
7171                 /*
7172                  * Enable double wide mode when the dot clock
7173                  * is > 90% of the (display) core speed.
7174                  */
7175                 if (intel_crtc_supports_double_wide(crtc) &&
7176                     adjusted_mode->crtc_clock > clock_limit) {
7177                         clock_limit = dev_priv->max_dotclk_freq;
7178                         pipe_config->double_wide = true;
7179                 }
7180         }
7181
7182         if (adjusted_mode->crtc_clock > clock_limit) {
7183                 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
7184                               adjusted_mode->crtc_clock, clock_limit,
7185                               yesno(pipe_config->double_wide));
7186                 return -EINVAL;
7187         }
7188
7189         /*
7190          * Pipe horizontal size must be even in:
7191          * - DVO ganged mode
7192          * - LVDS dual channel mode
7193          * - Double wide pipe
7194          */
7195         if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
7196              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
7197                 pipe_config->pipe_src_w &= ~1;
7198
7199         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
7200          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
7201          */
7202         if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
7203                 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
7204                 return -EINVAL;
7205
7206         if (HAS_IPS(dev_priv))
7207                 hsw_compute_ips_config(crtc, pipe_config);
7208
7209         if (pipe_config->has_pch_encoder)
7210                 return ironlake_fdi_compute_config(crtc, pipe_config);
7211
7212         return 0;
7213 }
7214
7215 static int skylake_get_display_clock_speed(struct drm_i915_private *dev_priv)
7216 {
7217         u32 cdctl;
7218
7219         skl_dpll0_update(dev_priv);
7220
7221         if (dev_priv->cdclk_pll.vco == 0)
7222                 return dev_priv->cdclk_pll.ref;
7223
7224         cdctl = I915_READ(CDCLK_CTL);
7225
7226         if (dev_priv->cdclk_pll.vco == 8640000) {
7227                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
7228                 case CDCLK_FREQ_450_432:
7229                         return 432000;
7230                 case CDCLK_FREQ_337_308:
7231                         return 308571;
7232                 case CDCLK_FREQ_540:
7233                         return 540000;
7234                 case CDCLK_FREQ_675_617:
7235                         return 617143;
7236                 default:
7237                         MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
7238                 }
7239         } else {
7240                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
7241                 case CDCLK_FREQ_450_432:
7242                         return 450000;
7243                 case CDCLK_FREQ_337_308:
7244                         return 337500;
7245                 case CDCLK_FREQ_540:
7246                         return 540000;
7247                 case CDCLK_FREQ_675_617:
7248                         return 675000;
7249                 default:
7250                         MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
7251                 }
7252         }
7253
7254         return dev_priv->cdclk_pll.ref;
7255 }
7256
7257 static void bxt_de_pll_update(struct drm_i915_private *dev_priv)
7258 {
7259         u32 val;
7260
7261         dev_priv->cdclk_pll.ref = 19200;
7262         dev_priv->cdclk_pll.vco = 0;
7263
7264         val = I915_READ(BXT_DE_PLL_ENABLE);
7265         if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
7266                 return;
7267
7268         if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
7269                 return;
7270
7271         val = I915_READ(BXT_DE_PLL_CTL);
7272         dev_priv->cdclk_pll.vco = (val & BXT_DE_PLL_RATIO_MASK) *
7273                 dev_priv->cdclk_pll.ref;
7274 }
7275
7276 static int broxton_get_display_clock_speed(struct drm_i915_private *dev_priv)
7277 {
7278         u32 divider;
7279         int div, vco;
7280
7281         bxt_de_pll_update(dev_priv);
7282
7283         vco = dev_priv->cdclk_pll.vco;
7284         if (vco == 0)
7285                 return dev_priv->cdclk_pll.ref;
7286
7287         divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
7288
7289         switch (divider) {
7290         case BXT_CDCLK_CD2X_DIV_SEL_1:
7291                 div = 2;
7292                 break;
7293         case BXT_CDCLK_CD2X_DIV_SEL_1_5:
7294                 div = 3;
7295                 break;
7296         case BXT_CDCLK_CD2X_DIV_SEL_2:
7297                 div = 4;
7298                 break;
7299         case BXT_CDCLK_CD2X_DIV_SEL_4:
7300                 div = 8;
7301                 break;
7302         default:
7303                 MISSING_CASE(divider);
7304                 return dev_priv->cdclk_pll.ref;
7305         }
7306
7307         return DIV_ROUND_CLOSEST(vco, div);
7308 }
7309
7310 static int broadwell_get_display_clock_speed(struct drm_i915_private *dev_priv)
7311 {
7312         uint32_t lcpll = I915_READ(LCPLL_CTL);
7313         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
7314
7315         if (lcpll & LCPLL_CD_SOURCE_FCLK)
7316                 return 800000;
7317         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
7318                 return 450000;
7319         else if (freq == LCPLL_CLK_FREQ_450)
7320                 return 450000;
7321         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
7322                 return 540000;
7323         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
7324                 return 337500;
7325         else
7326                 return 675000;
7327 }
7328
7329 static int haswell_get_display_clock_speed(struct drm_i915_private *dev_priv)
7330 {
7331         uint32_t lcpll = I915_READ(LCPLL_CTL);
7332         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
7333
7334         if (lcpll & LCPLL_CD_SOURCE_FCLK)
7335                 return 800000;
7336         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
7337                 return 450000;
7338         else if (freq == LCPLL_CLK_FREQ_450)
7339                 return 450000;
7340         else if (IS_HSW_ULT(dev_priv))
7341                 return 337500;
7342         else
7343                 return 540000;
7344 }
7345
7346 static int valleyview_get_display_clock_speed(struct drm_i915_private *dev_priv)
7347 {
7348         return vlv_get_cck_clock_hpll(dev_priv, "cdclk",
7349                                       CCK_DISPLAY_CLOCK_CONTROL);
7350 }
7351
7352 static int ilk_get_display_clock_speed(struct drm_i915_private *dev_priv)
7353 {
7354         return 450000;
7355 }
7356
7357 static int i945_get_display_clock_speed(struct drm_i915_private *dev_priv)
7358 {
7359         return 400000;
7360 }
7361
7362 static int i915_get_display_clock_speed(struct drm_i915_private *dev_priv)
7363 {
7364         return 333333;
7365 }
7366
7367 static int i9xx_misc_get_display_clock_speed(struct drm_i915_private *dev_priv)
7368 {
7369         return 200000;
7370 }
7371
7372 static int pnv_get_display_clock_speed(struct drm_i915_private *dev_priv)
7373 {
7374         struct pci_dev *pdev = dev_priv->drm.pdev;
7375         u16 gcfgc = 0;
7376
7377         pci_read_config_word(pdev, GCFGC, &gcfgc);
7378
7379         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
7380         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
7381                 return 266667;
7382         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
7383                 return 333333;
7384         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
7385                 return 444444;
7386         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
7387                 return 200000;
7388         default:
7389                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
7390         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
7391                 return 133333;
7392         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
7393                 return 166667;
7394         }
7395 }
7396
7397 static int i915gm_get_display_clock_speed(struct drm_i915_private *dev_priv)
7398 {
7399         struct pci_dev *pdev = dev_priv->drm.pdev;
7400         u16 gcfgc = 0;
7401
7402         pci_read_config_word(pdev, GCFGC, &gcfgc);
7403
7404         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
7405                 return 133333;
7406         else {
7407                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
7408                 case GC_DISPLAY_CLOCK_333_MHZ:
7409                         return 333333;
7410                 default:
7411                 case GC_DISPLAY_CLOCK_190_200_MHZ:
7412                         return 190000;
7413                 }
7414         }
7415 }
7416
7417 static int i865_get_display_clock_speed(struct drm_i915_private *dev_priv)
7418 {
7419         return 266667;
7420 }
7421
7422 static int i85x_get_display_clock_speed(struct drm_i915_private *dev_priv)
7423 {
7424         struct pci_dev *pdev = dev_priv->drm.pdev;
7425         u16 hpllcc = 0;
7426
7427         /*
7428          * 852GM/852GMV only supports 133 MHz and the HPLLCC
7429          * encoding is different :(
7430          * FIXME is this the right way to detect 852GM/852GMV?
7431          */
7432         if (pdev->revision == 0x1)
7433                 return 133333;
7434
7435         pci_bus_read_config_word(pdev->bus,
7436                                  PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
7437
7438         /* Assume that the hardware is in the high speed state.  This
7439          * should be the default.
7440          */
7441         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
7442         case GC_CLOCK_133_200:
7443         case GC_CLOCK_133_200_2:
7444         case GC_CLOCK_100_200:
7445                 return 200000;
7446         case GC_CLOCK_166_250:
7447                 return 250000;
7448         case GC_CLOCK_100_133:
7449                 return 133333;
7450         case GC_CLOCK_133_266:
7451         case GC_CLOCK_133_266_2:
7452         case GC_CLOCK_166_266:
7453                 return 266667;
7454         }
7455
7456         /* Shouldn't happen */
7457         return 0;
7458 }
7459
7460 static int i830_get_display_clock_speed(struct drm_i915_private *dev_priv)
7461 {
7462         return 133333;
7463 }
7464
7465 static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv)
7466 {
7467         static const unsigned int blb_vco[8] = {
7468                 [0] = 3200000,
7469                 [1] = 4000000,
7470                 [2] = 5333333,
7471                 [3] = 4800000,
7472                 [4] = 6400000,
7473         };
7474         static const unsigned int pnv_vco[8] = {
7475                 [0] = 3200000,
7476                 [1] = 4000000,
7477                 [2] = 5333333,
7478                 [3] = 4800000,
7479                 [4] = 2666667,
7480         };
7481         static const unsigned int cl_vco[8] = {
7482                 [0] = 3200000,
7483                 [1] = 4000000,
7484                 [2] = 5333333,
7485                 [3] = 6400000,
7486                 [4] = 3333333,
7487                 [5] = 3566667,
7488                 [6] = 4266667,
7489         };
7490         static const unsigned int elk_vco[8] = {
7491                 [0] = 3200000,
7492                 [1] = 4000000,
7493                 [2] = 5333333,
7494                 [3] = 4800000,
7495         };
7496         static const unsigned int ctg_vco[8] = {
7497                 [0] = 3200000,
7498                 [1] = 4000000,
7499                 [2] = 5333333,
7500                 [3] = 6400000,
7501                 [4] = 2666667,
7502                 [5] = 4266667,
7503         };
7504         const unsigned int *vco_table;
7505         unsigned int vco;
7506         uint8_t tmp = 0;
7507
7508         /* FIXME other chipsets? */
7509         if (IS_GM45(dev_priv))
7510                 vco_table = ctg_vco;
7511         else if (IS_G4X(dev_priv))
7512                 vco_table = elk_vco;
7513         else if (IS_CRESTLINE(dev_priv))
7514                 vco_table = cl_vco;
7515         else if (IS_PINEVIEW(dev_priv))
7516                 vco_table = pnv_vco;
7517         else if (IS_G33(dev_priv))
7518                 vco_table = blb_vco;
7519         else
7520                 return 0;
7521
7522         tmp = I915_READ(IS_MOBILE(dev_priv) ? HPLLVCO_MOBILE : HPLLVCO);
7523
7524         vco = vco_table[tmp & 0x7];
7525         if (vco == 0)
7526                 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
7527         else
7528                 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
7529
7530         return vco;
7531 }
7532
7533 static int gm45_get_display_clock_speed(struct drm_i915_private *dev_priv)
7534 {
7535         struct pci_dev *pdev = dev_priv->drm.pdev;
7536         unsigned int cdclk_sel, vco = intel_hpll_vco(dev_priv);
7537         uint16_t tmp = 0;
7538
7539         pci_read_config_word(pdev, GCFGC, &tmp);
7540
7541         cdclk_sel = (tmp >> 12) & 0x1;
7542
7543         switch (vco) {
7544         case 2666667:
7545         case 4000000:
7546         case 5333333:
7547                 return cdclk_sel ? 333333 : 222222;
7548         case 3200000:
7549                 return cdclk_sel ? 320000 : 228571;
7550         default:
7551                 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
7552                 return 222222;
7553         }
7554 }
7555
7556 static int i965gm_get_display_clock_speed(struct drm_i915_private *dev_priv)
7557 {
7558         struct pci_dev *pdev = dev_priv->drm.pdev;
7559         static const uint8_t div_3200[] = { 16, 10,  8 };
7560         static const uint8_t div_4000[] = { 20, 12, 10 };
7561         static const uint8_t div_5333[] = { 24, 16, 14 };
7562         const uint8_t *div_table;
7563         unsigned int cdclk_sel, vco = intel_hpll_vco(dev_priv);
7564         uint16_t tmp = 0;
7565
7566         pci_read_config_word(pdev, GCFGC, &tmp);
7567
7568         cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
7569
7570         if (cdclk_sel >= ARRAY_SIZE(div_3200))
7571                 goto fail;
7572
7573         switch (vco) {
7574         case 3200000:
7575                 div_table = div_3200;
7576                 break;
7577         case 4000000:
7578                 div_table = div_4000;
7579                 break;
7580         case 5333333:
7581                 div_table = div_5333;
7582                 break;
7583         default:
7584                 goto fail;
7585         }
7586
7587         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7588
7589 fail:
7590         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
7591         return 200000;
7592 }
7593
7594 static int g33_get_display_clock_speed(struct drm_i915_private *dev_priv)
7595 {
7596         struct pci_dev *pdev = dev_priv->drm.pdev;
7597         static const uint8_t div_3200[] = { 12, 10,  8,  7, 5, 16 };
7598         static const uint8_t div_4000[] = { 14, 12, 10,  8, 6, 20 };
7599         static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7600         static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7601         const uint8_t *div_table;
7602         unsigned int cdclk_sel, vco = intel_hpll_vco(dev_priv);
7603         uint16_t tmp = 0;
7604
7605         pci_read_config_word(pdev, GCFGC, &tmp);
7606
7607         cdclk_sel = (tmp >> 4) & 0x7;
7608
7609         if (cdclk_sel >= ARRAY_SIZE(div_3200))
7610                 goto fail;
7611
7612         switch (vco) {
7613         case 3200000:
7614                 div_table = div_3200;
7615                 break;
7616         case 4000000:
7617                 div_table = div_4000;
7618                 break;
7619         case 4800000:
7620                 div_table = div_4800;
7621                 break;
7622         case 5333333:
7623                 div_table = div_5333;
7624                 break;
7625         default:
7626                 goto fail;
7627         }
7628
7629         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7630
7631 fail:
7632         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7633         return 190476;
7634 }
7635
7636 static void
7637 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7638 {
7639         while (*num > DATA_LINK_M_N_MASK ||
7640                *den > DATA_LINK_M_N_MASK) {
7641                 *num >>= 1;
7642                 *den >>= 1;
7643         }
7644 }
7645
7646 static void compute_m_n(unsigned int m, unsigned int n,
7647                         uint32_t *ret_m, uint32_t *ret_n)
7648 {
7649         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7650         *ret_m = div_u64((uint64_t) m * *ret_n, n);
7651         intel_reduce_m_n_ratio(ret_m, ret_n);
7652 }
7653
7654 void
7655 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7656                        int pixel_clock, int link_clock,
7657                        struct intel_link_m_n *m_n)
7658 {
7659         m_n->tu = 64;
7660
7661         compute_m_n(bits_per_pixel * pixel_clock,
7662                     link_clock * nlanes * 8,
7663                     &m_n->gmch_m, &m_n->gmch_n);
7664
7665         compute_m_n(pixel_clock, link_clock,
7666                     &m_n->link_m, &m_n->link_n);
7667 }
7668
7669 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7670 {
7671         if (i915.panel_use_ssc >= 0)
7672                 return i915.panel_use_ssc != 0;
7673         return dev_priv->vbt.lvds_use_ssc
7674                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7675 }
7676
7677 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7678 {
7679         return (1 << dpll->n) << 16 | dpll->m2;
7680 }
7681
7682 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7683 {
7684         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7685 }
7686
7687 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7688                                      struct intel_crtc_state *crtc_state,
7689                                      struct dpll *reduced_clock)
7690 {
7691         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7692         u32 fp, fp2 = 0;
7693
7694         if (IS_PINEVIEW(dev_priv)) {
7695                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7696                 if (reduced_clock)
7697                         fp2 = pnv_dpll_compute_fp(reduced_clock);
7698         } else {
7699                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7700                 if (reduced_clock)
7701                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
7702         }
7703
7704         crtc_state->dpll_hw_state.fp0 = fp;
7705
7706         crtc->lowfreq_avail = false;
7707         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7708             reduced_clock) {
7709                 crtc_state->dpll_hw_state.fp1 = fp2;
7710                 crtc->lowfreq_avail = true;
7711         } else {
7712                 crtc_state->dpll_hw_state.fp1 = fp;
7713         }
7714 }
7715
7716 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7717                 pipe)
7718 {
7719         u32 reg_val;
7720
7721         /*
7722          * PLLB opamp always calibrates to max value of 0x3f, force enable it
7723          * and set it to a reasonable value instead.
7724          */
7725         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7726         reg_val &= 0xffffff00;
7727         reg_val |= 0x00000030;
7728         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7729
7730         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7731         reg_val &= 0x8cffffff;
7732         reg_val = 0x8c000000;
7733         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7734
7735         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7736         reg_val &= 0xffffff00;
7737         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7738
7739         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7740         reg_val &= 0x00ffffff;
7741         reg_val |= 0xb0000000;
7742         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7743 }
7744
7745 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7746                                          struct intel_link_m_n *m_n)
7747 {
7748         struct drm_device *dev = crtc->base.dev;
7749         struct drm_i915_private *dev_priv = to_i915(dev);
7750         int pipe = crtc->pipe;
7751
7752         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7753         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7754         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7755         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7756 }
7757
7758 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7759                                          struct intel_link_m_n *m_n,
7760                                          struct intel_link_m_n *m2_n2)
7761 {
7762         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7763         int pipe = crtc->pipe;
7764         enum transcoder transcoder = crtc->config->cpu_transcoder;
7765
7766         if (INTEL_GEN(dev_priv) >= 5) {
7767                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7768                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7769                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7770                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7771                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7772                  * for gen < 8) and if DRRS is supported (to make sure the
7773                  * registers are not unnecessarily accessed).
7774                  */
7775                 if (m2_n2 && (IS_CHERRYVIEW(dev_priv) ||
7776                     INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) {
7777                         I915_WRITE(PIPE_DATA_M2(transcoder),
7778                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7779                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7780                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7781                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7782                 }
7783         } else {
7784                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7785                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7786                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7787                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7788         }
7789 }
7790
7791 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7792 {
7793         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7794
7795         if (m_n == M1_N1) {
7796                 dp_m_n = &crtc->config->dp_m_n;
7797                 dp_m2_n2 = &crtc->config->dp_m2_n2;
7798         } else if (m_n == M2_N2) {
7799
7800                 /*
7801                  * M2_N2 registers are not supported. Hence m2_n2 divider value
7802                  * needs to be programmed into M1_N1.
7803                  */
7804                 dp_m_n = &crtc->config->dp_m2_n2;
7805         } else {
7806                 DRM_ERROR("Unsupported divider value\n");
7807                 return;
7808         }
7809
7810         if (crtc->config->has_pch_encoder)
7811                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7812         else
7813                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7814 }
7815
7816 static void vlv_compute_dpll(struct intel_crtc *crtc,
7817                              struct intel_crtc_state *pipe_config)
7818 {
7819         pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
7820                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7821         if (crtc->pipe != PIPE_A)
7822                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7823
7824         /* DPLL not used with DSI, but still need the rest set up */
7825         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
7826                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
7827                         DPLL_EXT_BUFFER_ENABLE_VLV;
7828
7829         pipe_config->dpll_hw_state.dpll_md =
7830                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7831 }
7832
7833 static void chv_compute_dpll(struct intel_crtc *crtc,
7834                              struct intel_crtc_state *pipe_config)
7835 {
7836         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7837                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7838         if (crtc->pipe != PIPE_A)
7839                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7840
7841         /* DPLL not used with DSI, but still need the rest set up */
7842         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
7843                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
7844
7845         pipe_config->dpll_hw_state.dpll_md =
7846                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7847 }
7848
7849 static void vlv_prepare_pll(struct intel_crtc *crtc,
7850                             const struct intel_crtc_state *pipe_config)
7851 {
7852         struct drm_device *dev = crtc->base.dev;
7853         struct drm_i915_private *dev_priv = to_i915(dev);
7854         enum pipe pipe = crtc->pipe;
7855         u32 mdiv;
7856         u32 bestn, bestm1, bestm2, bestp1, bestp2;
7857         u32 coreclk, reg_val;
7858
7859         /* Enable Refclk */
7860         I915_WRITE(DPLL(pipe),
7861                    pipe_config->dpll_hw_state.dpll &
7862                    ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
7863
7864         /* No need to actually set up the DPLL with DSI */
7865         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7866                 return;
7867
7868         mutex_lock(&dev_priv->sb_lock);
7869
7870         bestn = pipe_config->dpll.n;
7871         bestm1 = pipe_config->dpll.m1;
7872         bestm2 = pipe_config->dpll.m2;
7873         bestp1 = pipe_config->dpll.p1;
7874         bestp2 = pipe_config->dpll.p2;
7875
7876         /* See eDP HDMI DPIO driver vbios notes doc */
7877
7878         /* PLL B needs special handling */
7879         if (pipe == PIPE_B)
7880                 vlv_pllb_recal_opamp(dev_priv, pipe);
7881
7882         /* Set up Tx target for periodic Rcomp update */
7883         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7884
7885         /* Disable target IRef on PLL */
7886         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7887         reg_val &= 0x00ffffff;
7888         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7889
7890         /* Disable fast lock */
7891         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7892
7893         /* Set idtafcrecal before PLL is enabled */
7894         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7895         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7896         mdiv |= ((bestn << DPIO_N_SHIFT));
7897         mdiv |= (1 << DPIO_K_SHIFT);
7898
7899         /*
7900          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7901          * but we don't support that).
7902          * Note: don't use the DAC post divider as it seems unstable.
7903          */
7904         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7905         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7906
7907         mdiv |= DPIO_ENABLE_CALIBRATION;
7908         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7909
7910         /* Set HBR and RBR LPF coefficients */
7911         if (pipe_config->port_clock == 162000 ||
7912             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) ||
7913             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI))
7914                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7915                                  0x009f0003);
7916         else
7917                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7918                                  0x00d0000f);
7919
7920         if (intel_crtc_has_dp_encoder(pipe_config)) {
7921                 /* Use SSC source */
7922                 if (pipe == PIPE_A)
7923                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7924                                          0x0df40000);
7925                 else
7926                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7927                                          0x0df70000);
7928         } else { /* HDMI or VGA */
7929                 /* Use bend source */
7930                 if (pipe == PIPE_A)
7931                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7932                                          0x0df70000);
7933                 else
7934                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7935                                          0x0df40000);
7936         }
7937
7938         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7939         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7940         if (intel_crtc_has_dp_encoder(crtc->config))
7941                 coreclk |= 0x01000000;
7942         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7943
7944         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7945         mutex_unlock(&dev_priv->sb_lock);
7946 }
7947
7948 static void chv_prepare_pll(struct intel_crtc *crtc,
7949                             const struct intel_crtc_state *pipe_config)
7950 {
7951         struct drm_device *dev = crtc->base.dev;
7952         struct drm_i915_private *dev_priv = to_i915(dev);
7953         enum pipe pipe = crtc->pipe;
7954         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7955         u32 loopfilter, tribuf_calcntr;
7956         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7957         u32 dpio_val;
7958         int vco;
7959
7960         /* Enable Refclk and SSC */
7961         I915_WRITE(DPLL(pipe),
7962                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7963
7964         /* No need to actually set up the DPLL with DSI */
7965         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7966                 return;
7967
7968         bestn = pipe_config->dpll.n;
7969         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7970         bestm1 = pipe_config->dpll.m1;
7971         bestm2 = pipe_config->dpll.m2 >> 22;
7972         bestp1 = pipe_config->dpll.p1;
7973         bestp2 = pipe_config->dpll.p2;
7974         vco = pipe_config->dpll.vco;
7975         dpio_val = 0;
7976         loopfilter = 0;
7977
7978         mutex_lock(&dev_priv->sb_lock);
7979
7980         /* p1 and p2 divider */
7981         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7982                         5 << DPIO_CHV_S1_DIV_SHIFT |
7983                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7984                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7985                         1 << DPIO_CHV_K_DIV_SHIFT);
7986
7987         /* Feedback post-divider - m2 */
7988         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7989
7990         /* Feedback refclk divider - n and m1 */
7991         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7992                         DPIO_CHV_M1_DIV_BY_2 |
7993                         1 << DPIO_CHV_N_DIV_SHIFT);
7994
7995         /* M2 fraction division */
7996         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7997
7998         /* M2 fraction division enable */
7999         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8000         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
8001         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
8002         if (bestm2_frac)
8003                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
8004         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
8005
8006         /* Program digital lock detect threshold */
8007         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
8008         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
8009                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
8010         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
8011         if (!bestm2_frac)
8012                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
8013         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
8014
8015         /* Loop filter */
8016         if (vco == 5400000) {
8017                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
8018                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
8019                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
8020                 tribuf_calcntr = 0x9;
8021         } else if (vco <= 6200000) {
8022                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
8023                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
8024                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8025                 tribuf_calcntr = 0x9;
8026         } else if (vco <= 6480000) {
8027                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
8028                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
8029                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8030                 tribuf_calcntr = 0x8;
8031         } else {
8032                 /* Not supported. Apply the same limits as in the max case */
8033                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
8034                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
8035                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8036                 tribuf_calcntr = 0;
8037         }
8038         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
8039
8040         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
8041         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
8042         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
8043         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
8044
8045         /* AFC Recal */
8046         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
8047                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
8048                         DPIO_AFC_RECAL);
8049
8050         mutex_unlock(&dev_priv->sb_lock);
8051 }
8052
8053 /**
8054  * vlv_force_pll_on - forcibly enable just the PLL
8055  * @dev_priv: i915 private structure
8056  * @pipe: pipe PLL to enable
8057  * @dpll: PLL configuration
8058  *
8059  * Enable the PLL for @pipe using the supplied @dpll config. To be used
8060  * in cases where we need the PLL enabled even when @pipe is not going to
8061  * be enabled.
8062  */
8063 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
8064                      const struct dpll *dpll)
8065 {
8066         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
8067         struct intel_crtc_state *pipe_config;
8068
8069         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8070         if (!pipe_config)
8071                 return -ENOMEM;
8072
8073         pipe_config->base.crtc = &crtc->base;
8074         pipe_config->pixel_multiplier = 1;
8075         pipe_config->dpll = *dpll;
8076
8077         if (IS_CHERRYVIEW(dev_priv)) {
8078                 chv_compute_dpll(crtc, pipe_config);
8079                 chv_prepare_pll(crtc, pipe_config);
8080                 chv_enable_pll(crtc, pipe_config);
8081         } else {
8082                 vlv_compute_dpll(crtc, pipe_config);
8083                 vlv_prepare_pll(crtc, pipe_config);
8084                 vlv_enable_pll(crtc, pipe_config);
8085         }
8086
8087         kfree(pipe_config);
8088
8089         return 0;
8090 }
8091
8092 /**
8093  * vlv_force_pll_off - forcibly disable just the PLL
8094  * @dev_priv: i915 private structure
8095  * @pipe: pipe PLL to disable
8096  *
8097  * Disable the PLL for @pipe. To be used in cases where we need
8098  * the PLL enabled even when @pipe is not going to be enabled.
8099  */
8100 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
8101 {
8102         if (IS_CHERRYVIEW(dev_priv))
8103                 chv_disable_pll(dev_priv, pipe);
8104         else
8105                 vlv_disable_pll(dev_priv, pipe);
8106 }
8107
8108 static void i9xx_compute_dpll(struct intel_crtc *crtc,
8109                               struct intel_crtc_state *crtc_state,
8110                               struct dpll *reduced_clock)
8111 {
8112         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8113         u32 dpll;
8114         struct dpll *clock = &crtc_state->dpll;
8115
8116         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8117
8118         dpll = DPLL_VGA_MODE_DIS;
8119
8120         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8121                 dpll |= DPLLB_MODE_LVDS;
8122         else
8123                 dpll |= DPLLB_MODE_DAC_SERIAL;
8124
8125         if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || IS_G33(dev_priv)) {
8126                 dpll |= (crtc_state->pixel_multiplier - 1)
8127                         << SDVO_MULTIPLIER_SHIFT_HIRES;
8128         }
8129
8130         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8131             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8132                 dpll |= DPLL_SDVO_HIGH_SPEED;
8133
8134         if (intel_crtc_has_dp_encoder(crtc_state))
8135                 dpll |= DPLL_SDVO_HIGH_SPEED;
8136
8137         /* compute bitmask from p1 value */
8138         if (IS_PINEVIEW(dev_priv))
8139                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
8140         else {
8141                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8142                 if (IS_G4X(dev_priv) && reduced_clock)
8143                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8144         }
8145         switch (clock->p2) {
8146         case 5:
8147                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8148                 break;
8149         case 7:
8150                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8151                 break;
8152         case 10:
8153                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8154                 break;
8155         case 14:
8156                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8157                 break;
8158         }
8159         if (INTEL_GEN(dev_priv) >= 4)
8160                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
8161
8162         if (crtc_state->sdvo_tv_clock)
8163                 dpll |= PLL_REF_INPUT_TVCLKINBC;
8164         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8165                  intel_panel_use_ssc(dev_priv))
8166                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8167         else
8168                 dpll |= PLL_REF_INPUT_DREFCLK;
8169
8170         dpll |= DPLL_VCO_ENABLE;
8171         crtc_state->dpll_hw_state.dpll = dpll;
8172
8173         if (INTEL_GEN(dev_priv) >= 4) {
8174                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
8175                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8176                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
8177         }
8178 }
8179
8180 static void i8xx_compute_dpll(struct intel_crtc *crtc,
8181                               struct intel_crtc_state *crtc_state,
8182                               struct dpll *reduced_clock)
8183 {
8184         struct drm_device *dev = crtc->base.dev;
8185         struct drm_i915_private *dev_priv = to_i915(dev);
8186         u32 dpll;
8187         struct dpll *clock = &crtc_state->dpll;
8188
8189         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8190
8191         dpll = DPLL_VGA_MODE_DIS;
8192
8193         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8194                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8195         } else {
8196                 if (clock->p1 == 2)
8197                         dpll |= PLL_P1_DIVIDE_BY_TWO;
8198                 else
8199                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8200                 if (clock->p2 == 4)
8201                         dpll |= PLL_P2_DIVIDE_BY_4;
8202         }
8203
8204         if (!IS_I830(dev_priv) &&
8205             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
8206                 dpll |= DPLL_DVO_2X_MODE;
8207
8208         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8209             intel_panel_use_ssc(dev_priv))
8210                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8211         else
8212                 dpll |= PLL_REF_INPUT_DREFCLK;
8213
8214         dpll |= DPLL_VCO_ENABLE;
8215         crtc_state->dpll_hw_state.dpll = dpll;
8216 }
8217
8218 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
8219 {
8220         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
8221         enum pipe pipe = intel_crtc->pipe;
8222         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8223         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
8224         uint32_t crtc_vtotal, crtc_vblank_end;
8225         int vsyncshift = 0;
8226
8227         /* We need to be careful not to changed the adjusted mode, for otherwise
8228          * the hw state checker will get angry at the mismatch. */
8229         crtc_vtotal = adjusted_mode->crtc_vtotal;
8230         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
8231
8232         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
8233                 /* the chip adds 2 halflines automatically */
8234                 crtc_vtotal -= 1;
8235                 crtc_vblank_end -= 1;
8236
8237                 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
8238                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
8239                 else
8240                         vsyncshift = adjusted_mode->crtc_hsync_start -
8241                                 adjusted_mode->crtc_htotal / 2;
8242                 if (vsyncshift < 0)
8243                         vsyncshift += adjusted_mode->crtc_htotal;
8244         }
8245
8246         if (INTEL_GEN(dev_priv) > 3)
8247                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
8248
8249         I915_WRITE(HTOTAL(cpu_transcoder),
8250                    (adjusted_mode->crtc_hdisplay - 1) |
8251                    ((adjusted_mode->crtc_htotal - 1) << 16));
8252         I915_WRITE(HBLANK(cpu_transcoder),
8253                    (adjusted_mode->crtc_hblank_start - 1) |
8254                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
8255         I915_WRITE(HSYNC(cpu_transcoder),
8256                    (adjusted_mode->crtc_hsync_start - 1) |
8257                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
8258
8259         I915_WRITE(VTOTAL(cpu_transcoder),
8260                    (adjusted_mode->crtc_vdisplay - 1) |
8261                    ((crtc_vtotal - 1) << 16));
8262         I915_WRITE(VBLANK(cpu_transcoder),
8263                    (adjusted_mode->crtc_vblank_start - 1) |
8264                    ((crtc_vblank_end - 1) << 16));
8265         I915_WRITE(VSYNC(cpu_transcoder),
8266                    (adjusted_mode->crtc_vsync_start - 1) |
8267                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
8268
8269         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
8270          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
8271          * documented on the DDI_FUNC_CTL register description, EDP Input Select
8272          * bits. */
8273         if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
8274             (pipe == PIPE_B || pipe == PIPE_C))
8275                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
8276
8277 }
8278
8279 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
8280 {
8281         struct drm_device *dev = intel_crtc->base.dev;
8282         struct drm_i915_private *dev_priv = to_i915(dev);
8283         enum pipe pipe = intel_crtc->pipe;
8284
8285         /* pipesrc controls the size that is scaled from, which should
8286          * always be the user's requested size.
8287          */
8288         I915_WRITE(PIPESRC(pipe),
8289                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
8290                    (intel_crtc->config->pipe_src_h - 1));
8291 }
8292
8293 static void intel_get_pipe_timings(struct intel_crtc *crtc,
8294                                    struct intel_crtc_state *pipe_config)
8295 {
8296         struct drm_device *dev = crtc->base.dev;
8297         struct drm_i915_private *dev_priv = to_i915(dev);
8298         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
8299         uint32_t tmp;
8300
8301         tmp = I915_READ(HTOTAL(cpu_transcoder));
8302         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
8303         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
8304         tmp = I915_READ(HBLANK(cpu_transcoder));
8305         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
8306         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
8307         tmp = I915_READ(HSYNC(cpu_transcoder));
8308         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
8309         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
8310
8311         tmp = I915_READ(VTOTAL(cpu_transcoder));
8312         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
8313         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
8314         tmp = I915_READ(VBLANK(cpu_transcoder));
8315         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
8316         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
8317         tmp = I915_READ(VSYNC(cpu_transcoder));
8318         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
8319         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
8320
8321         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
8322                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
8323                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
8324                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
8325         }
8326 }
8327
8328 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
8329                                     struct intel_crtc_state *pipe_config)
8330 {
8331         struct drm_device *dev = crtc->base.dev;
8332         struct drm_i915_private *dev_priv = to_i915(dev);
8333         u32 tmp;
8334
8335         tmp = I915_READ(PIPESRC(crtc->pipe));
8336         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
8337         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
8338
8339         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
8340         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
8341 }
8342
8343 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
8344                                  struct intel_crtc_state *pipe_config)
8345 {
8346         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
8347         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
8348         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
8349         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
8350
8351         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
8352         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
8353         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
8354         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
8355
8356         mode->flags = pipe_config->base.adjusted_mode.flags;
8357         mode->type = DRM_MODE_TYPE_DRIVER;
8358
8359         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
8360         mode->flags |= pipe_config->base.adjusted_mode.flags;
8361
8362         mode->hsync = drm_mode_hsync(mode);
8363         mode->vrefresh = drm_mode_vrefresh(mode);
8364         drm_mode_set_name(mode);
8365 }
8366
8367 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
8368 {
8369         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
8370         uint32_t pipeconf;
8371
8372         pipeconf = 0;
8373
8374         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
8375             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
8376                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
8377
8378         if (intel_crtc->config->double_wide)
8379                 pipeconf |= PIPECONF_DOUBLE_WIDE;
8380
8381         /* only g4x and later have fancy bpc/dither controls */
8382         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
8383             IS_CHERRYVIEW(dev_priv)) {
8384                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
8385                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
8386                         pipeconf |= PIPECONF_DITHER_EN |
8387                                     PIPECONF_DITHER_TYPE_SP;
8388
8389                 switch (intel_crtc->config->pipe_bpp) {
8390                 case 18:
8391                         pipeconf |= PIPECONF_6BPC;
8392                         break;
8393                 case 24:
8394                         pipeconf |= PIPECONF_8BPC;
8395                         break;
8396                 case 30:
8397                         pipeconf |= PIPECONF_10BPC;
8398                         break;
8399                 default:
8400                         /* Case prevented by intel_choose_pipe_bpp_dither. */
8401                         BUG();
8402                 }
8403         }
8404
8405         if (HAS_PIPE_CXSR(dev_priv)) {
8406                 if (intel_crtc->lowfreq_avail) {
8407                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
8408                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
8409                 } else {
8410                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
8411                 }
8412         }
8413
8414         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
8415                 if (INTEL_GEN(dev_priv) < 4 ||
8416                     intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
8417                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
8418                 else
8419                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
8420         } else
8421                 pipeconf |= PIPECONF_PROGRESSIVE;
8422
8423         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
8424              intel_crtc->config->limited_color_range)
8425                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
8426
8427         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
8428         POSTING_READ(PIPECONF(intel_crtc->pipe));
8429 }
8430
8431 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
8432                                    struct intel_crtc_state *crtc_state)
8433 {
8434         struct drm_device *dev = crtc->base.dev;
8435         struct drm_i915_private *dev_priv = to_i915(dev);
8436         const struct intel_limit *limit;
8437         int refclk = 48000;
8438
8439         memset(&crtc_state->dpll_hw_state, 0,
8440                sizeof(crtc_state->dpll_hw_state));
8441
8442         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8443                 if (intel_panel_use_ssc(dev_priv)) {
8444                         refclk = dev_priv->vbt.lvds_ssc_freq;
8445                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8446                 }
8447
8448                 limit = &intel_limits_i8xx_lvds;
8449         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
8450                 limit = &intel_limits_i8xx_dvo;
8451         } else {
8452                 limit = &intel_limits_i8xx_dac;
8453         }
8454
8455         if (!crtc_state->clock_set &&
8456             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8457                                  refclk, NULL, &crtc_state->dpll)) {
8458                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8459                 return -EINVAL;
8460         }
8461
8462         i8xx_compute_dpll(crtc, crtc_state, NULL);
8463
8464         return 0;
8465 }
8466
8467 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
8468                                   struct intel_crtc_state *crtc_state)
8469 {
8470         struct drm_device *dev = crtc->base.dev;
8471         struct drm_i915_private *dev_priv = to_i915(dev);
8472         const struct intel_limit *limit;
8473         int refclk = 96000;
8474
8475         memset(&crtc_state->dpll_hw_state, 0,
8476                sizeof(crtc_state->dpll_hw_state));
8477
8478         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8479                 if (intel_panel_use_ssc(dev_priv)) {
8480                         refclk = dev_priv->vbt.lvds_ssc_freq;
8481                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8482                 }
8483
8484                 if (intel_is_dual_link_lvds(dev))
8485                         limit = &intel_limits_g4x_dual_channel_lvds;
8486                 else
8487                         limit = &intel_limits_g4x_single_channel_lvds;
8488         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
8489                    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
8490                 limit = &intel_limits_g4x_hdmi;
8491         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
8492                 limit = &intel_limits_g4x_sdvo;
8493         } else {
8494                 /* The option is for other outputs */
8495                 limit = &intel_limits_i9xx_sdvo;
8496         }
8497
8498         if (!crtc_state->clock_set &&
8499             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8500                                 refclk, NULL, &crtc_state->dpll)) {
8501                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8502                 return -EINVAL;
8503         }
8504
8505         i9xx_compute_dpll(crtc, crtc_state, NULL);
8506
8507         return 0;
8508 }
8509
8510 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
8511                                   struct intel_crtc_state *crtc_state)
8512 {
8513         struct drm_device *dev = crtc->base.dev;
8514         struct drm_i915_private *dev_priv = to_i915(dev);
8515         const struct intel_limit *limit;
8516         int refclk = 96000;
8517
8518         memset(&crtc_state->dpll_hw_state, 0,
8519                sizeof(crtc_state->dpll_hw_state));
8520
8521         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8522                 if (intel_panel_use_ssc(dev_priv)) {
8523                         refclk = dev_priv->vbt.lvds_ssc_freq;
8524                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8525                 }
8526
8527                 limit = &intel_limits_pineview_lvds;
8528         } else {
8529                 limit = &intel_limits_pineview_sdvo;
8530         }
8531
8532         if (!crtc_state->clock_set &&
8533             !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8534                                 refclk, NULL, &crtc_state->dpll)) {
8535                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8536                 return -EINVAL;
8537         }
8538
8539         i9xx_compute_dpll(crtc, crtc_state, NULL);
8540
8541         return 0;
8542 }
8543
8544 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
8545                                    struct intel_crtc_state *crtc_state)
8546 {
8547         struct drm_device *dev = crtc->base.dev;
8548         struct drm_i915_private *dev_priv = to_i915(dev);
8549         const struct intel_limit *limit;
8550         int refclk = 96000;
8551
8552         memset(&crtc_state->dpll_hw_state, 0,
8553                sizeof(crtc_state->dpll_hw_state));
8554
8555         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8556                 if (intel_panel_use_ssc(dev_priv)) {
8557                         refclk = dev_priv->vbt.lvds_ssc_freq;
8558                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8559                 }
8560
8561                 limit = &intel_limits_i9xx_lvds;
8562         } else {
8563                 limit = &intel_limits_i9xx_sdvo;
8564         }
8565
8566         if (!crtc_state->clock_set &&
8567             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8568                                  refclk, NULL, &crtc_state->dpll)) {
8569                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8570                 return -EINVAL;
8571         }
8572
8573         i9xx_compute_dpll(crtc, crtc_state, NULL);
8574
8575         return 0;
8576 }
8577
8578 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
8579                                   struct intel_crtc_state *crtc_state)
8580 {
8581         int refclk = 100000;
8582         const struct intel_limit *limit = &intel_limits_chv;
8583
8584         memset(&crtc_state->dpll_hw_state, 0,
8585                sizeof(crtc_state->dpll_hw_state));
8586
8587         if (!crtc_state->clock_set &&
8588             !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8589                                 refclk, NULL, &crtc_state->dpll)) {
8590                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8591                 return -EINVAL;
8592         }
8593
8594         chv_compute_dpll(crtc, crtc_state);
8595
8596         return 0;
8597 }
8598
8599 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
8600                                   struct intel_crtc_state *crtc_state)
8601 {
8602         int refclk = 100000;
8603         const struct intel_limit *limit = &intel_limits_vlv;
8604
8605         memset(&crtc_state->dpll_hw_state, 0,
8606                sizeof(crtc_state->dpll_hw_state));
8607
8608         if (!crtc_state->clock_set &&
8609             !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8610                                 refclk, NULL, &crtc_state->dpll)) {
8611                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8612                 return -EINVAL;
8613         }
8614
8615         vlv_compute_dpll(crtc, crtc_state);
8616
8617         return 0;
8618 }
8619
8620 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
8621                                  struct intel_crtc_state *pipe_config)
8622 {
8623         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8624         uint32_t tmp;
8625
8626         if (INTEL_GEN(dev_priv) <= 3 &&
8627             (IS_I830(dev_priv) || !IS_MOBILE(dev_priv)))
8628                 return;
8629
8630         tmp = I915_READ(PFIT_CONTROL);
8631         if (!(tmp & PFIT_ENABLE))
8632                 return;
8633
8634         /* Check whether the pfit is attached to our pipe. */
8635         if (INTEL_GEN(dev_priv) < 4) {
8636                 if (crtc->pipe != PIPE_B)
8637                         return;
8638         } else {
8639                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
8640                         return;
8641         }
8642
8643         pipe_config->gmch_pfit.control = tmp;
8644         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
8645 }
8646
8647 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8648                                struct intel_crtc_state *pipe_config)
8649 {
8650         struct drm_device *dev = crtc->base.dev;
8651         struct drm_i915_private *dev_priv = to_i915(dev);
8652         int pipe = pipe_config->cpu_transcoder;
8653         struct dpll clock;
8654         u32 mdiv;
8655         int refclk = 100000;
8656
8657         /* In case of DSI, DPLL will not be used */
8658         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8659                 return;
8660
8661         mutex_lock(&dev_priv->sb_lock);
8662         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8663         mutex_unlock(&dev_priv->sb_lock);
8664
8665         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8666         clock.m2 = mdiv & DPIO_M2DIV_MASK;
8667         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8668         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8669         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8670
8671         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8672 }
8673
8674 static void
8675 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8676                               struct intel_initial_plane_config *plane_config)
8677 {
8678         struct drm_device *dev = crtc->base.dev;
8679         struct drm_i915_private *dev_priv = to_i915(dev);
8680         u32 val, base, offset;
8681         int pipe = crtc->pipe, plane = crtc->plane;
8682         int fourcc, pixel_format;
8683         unsigned int aligned_height;
8684         struct drm_framebuffer *fb;
8685         struct intel_framebuffer *intel_fb;
8686
8687         val = I915_READ(DSPCNTR(plane));
8688         if (!(val & DISPLAY_PLANE_ENABLE))
8689                 return;
8690
8691         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8692         if (!intel_fb) {
8693                 DRM_DEBUG_KMS("failed to alloc fb\n");
8694                 return;
8695         }
8696
8697         fb = &intel_fb->base;
8698
8699         if (INTEL_GEN(dev_priv) >= 4) {
8700                 if (val & DISPPLANE_TILED) {
8701                         plane_config->tiling = I915_TILING_X;
8702                         fb->modifier = I915_FORMAT_MOD_X_TILED;
8703                 }
8704         }
8705
8706         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8707         fourcc = i9xx_format_to_fourcc(pixel_format);
8708         fb->pixel_format = fourcc;
8709         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8710
8711         if (INTEL_GEN(dev_priv) >= 4) {
8712                 if (plane_config->tiling)
8713                         offset = I915_READ(DSPTILEOFF(plane));
8714                 else
8715                         offset = I915_READ(DSPLINOFF(plane));
8716                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8717         } else {
8718                 base = I915_READ(DSPADDR(plane));
8719         }
8720         plane_config->base = base;
8721
8722         val = I915_READ(PIPESRC(pipe));
8723         fb->width = ((val >> 16) & 0xfff) + 1;
8724         fb->height = ((val >> 0) & 0xfff) + 1;
8725
8726         val = I915_READ(DSPSTRIDE(pipe));
8727         fb->pitches[0] = val & 0xffffffc0;
8728
8729         aligned_height = intel_fb_align_height(dev, fb->height,
8730                                                fb->pixel_format,
8731                                                fb->modifier);
8732
8733         plane_config->size = fb->pitches[0] * aligned_height;
8734
8735         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8736                       pipe_name(pipe), plane, fb->width, fb->height,
8737                       fb->bits_per_pixel, base, fb->pitches[0],
8738                       plane_config->size);
8739
8740         plane_config->fb = intel_fb;
8741 }
8742
8743 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8744                                struct intel_crtc_state *pipe_config)
8745 {
8746         struct drm_device *dev = crtc->base.dev;
8747         struct drm_i915_private *dev_priv = to_i915(dev);
8748         int pipe = pipe_config->cpu_transcoder;
8749         enum dpio_channel port = vlv_pipe_to_channel(pipe);
8750         struct dpll clock;
8751         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8752         int refclk = 100000;
8753
8754         /* In case of DSI, DPLL will not be used */
8755         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8756                 return;
8757
8758         mutex_lock(&dev_priv->sb_lock);
8759         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8760         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8761         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8762         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8763         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8764         mutex_unlock(&dev_priv->sb_lock);
8765
8766         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8767         clock.m2 = (pll_dw0 & 0xff) << 22;
8768         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8769                 clock.m2 |= pll_dw2 & 0x3fffff;
8770         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8771         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8772         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8773
8774         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8775 }
8776
8777 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8778                                  struct intel_crtc_state *pipe_config)
8779 {
8780         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8781         enum intel_display_power_domain power_domain;
8782         uint32_t tmp;
8783         bool ret;
8784
8785         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8786         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8787                 return false;
8788
8789         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8790         pipe_config->shared_dpll = NULL;
8791
8792         ret = false;
8793
8794         tmp = I915_READ(PIPECONF(crtc->pipe));
8795         if (!(tmp & PIPECONF_ENABLE))
8796                 goto out;
8797
8798         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
8799             IS_CHERRYVIEW(dev_priv)) {
8800                 switch (tmp & PIPECONF_BPC_MASK) {
8801                 case PIPECONF_6BPC:
8802                         pipe_config->pipe_bpp = 18;
8803                         break;
8804                 case PIPECONF_8BPC:
8805                         pipe_config->pipe_bpp = 24;
8806                         break;
8807                 case PIPECONF_10BPC:
8808                         pipe_config->pipe_bpp = 30;
8809                         break;
8810                 default:
8811                         break;
8812                 }
8813         }
8814
8815         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
8816             (tmp & PIPECONF_COLOR_RANGE_SELECT))
8817                 pipe_config->limited_color_range = true;
8818
8819         if (INTEL_GEN(dev_priv) < 4)
8820                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8821
8822         intel_get_pipe_timings(crtc, pipe_config);
8823         intel_get_pipe_src_size(crtc, pipe_config);
8824
8825         i9xx_get_pfit_config(crtc, pipe_config);
8826
8827         if (INTEL_GEN(dev_priv) >= 4) {
8828                 /* No way to read it out on pipes B and C */
8829                 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
8830                         tmp = dev_priv->chv_dpll_md[crtc->pipe];
8831                 else
8832                         tmp = I915_READ(DPLL_MD(crtc->pipe));
8833                 pipe_config->pixel_multiplier =
8834                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8835                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8836                 pipe_config->dpll_hw_state.dpll_md = tmp;
8837         } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
8838                    IS_G33(dev_priv)) {
8839                 tmp = I915_READ(DPLL(crtc->pipe));
8840                 pipe_config->pixel_multiplier =
8841                         ((tmp & SDVO_MULTIPLIER_MASK)
8842                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8843         } else {
8844                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8845                  * port and will be fixed up in the encoder->get_config
8846                  * function. */
8847                 pipe_config->pixel_multiplier = 1;
8848         }
8849         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8850         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
8851                 /*
8852                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8853                  * on 830. Filter it out here so that we don't
8854                  * report errors due to that.
8855                  */
8856                 if (IS_I830(dev_priv))
8857                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8858
8859                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8860                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8861         } else {
8862                 /* Mask out read-only status bits. */
8863                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8864                                                      DPLL_PORTC_READY_MASK |
8865                                                      DPLL_PORTB_READY_MASK);
8866         }
8867
8868         if (IS_CHERRYVIEW(dev_priv))
8869                 chv_crtc_clock_get(crtc, pipe_config);
8870         else if (IS_VALLEYVIEW(dev_priv))
8871                 vlv_crtc_clock_get(crtc, pipe_config);
8872         else
8873                 i9xx_crtc_clock_get(crtc, pipe_config);
8874
8875         /*
8876          * Normally the dotclock is filled in by the encoder .get_config()
8877          * but in case the pipe is enabled w/o any ports we need a sane
8878          * default.
8879          */
8880         pipe_config->base.adjusted_mode.crtc_clock =
8881                 pipe_config->port_clock / pipe_config->pixel_multiplier;
8882
8883         ret = true;
8884
8885 out:
8886         intel_display_power_put(dev_priv, power_domain);
8887
8888         return ret;
8889 }
8890
8891 static void ironlake_init_pch_refclk(struct drm_device *dev)
8892 {
8893         struct drm_i915_private *dev_priv = to_i915(dev);
8894         struct intel_encoder *encoder;
8895         int i;
8896         u32 val, final;
8897         bool has_lvds = false;
8898         bool has_cpu_edp = false;
8899         bool has_panel = false;
8900         bool has_ck505 = false;
8901         bool can_ssc = false;
8902         bool using_ssc_source = false;
8903
8904         /* We need to take the global config into account */
8905         for_each_intel_encoder(dev, encoder) {
8906                 switch (encoder->type) {
8907                 case INTEL_OUTPUT_LVDS:
8908                         has_panel = true;
8909                         has_lvds = true;
8910                         break;
8911                 case INTEL_OUTPUT_EDP:
8912                         has_panel = true;
8913                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8914                                 has_cpu_edp = true;
8915                         break;
8916                 default:
8917                         break;
8918                 }
8919         }
8920
8921         if (HAS_PCH_IBX(dev_priv)) {
8922                 has_ck505 = dev_priv->vbt.display_clock_mode;
8923                 can_ssc = has_ck505;
8924         } else {
8925                 has_ck505 = false;
8926                 can_ssc = true;
8927         }
8928
8929         /* Check if any DPLLs are using the SSC source */
8930         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8931                 u32 temp = I915_READ(PCH_DPLL(i));
8932
8933                 if (!(temp & DPLL_VCO_ENABLE))
8934                         continue;
8935
8936                 if ((temp & PLL_REF_INPUT_MASK) ==
8937                     PLLB_REF_INPUT_SPREADSPECTRUMIN) {
8938                         using_ssc_source = true;
8939                         break;
8940                 }
8941         }
8942
8943         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
8944                       has_panel, has_lvds, has_ck505, using_ssc_source);
8945
8946         /* Ironlake: try to setup display ref clock before DPLL
8947          * enabling. This is only under driver's control after
8948          * PCH B stepping, previous chipset stepping should be
8949          * ignoring this setting.
8950          */
8951         val = I915_READ(PCH_DREF_CONTROL);
8952
8953         /* As we must carefully and slowly disable/enable each source in turn,
8954          * compute the final state we want first and check if we need to
8955          * make any changes at all.
8956          */
8957         final = val;
8958         final &= ~DREF_NONSPREAD_SOURCE_MASK;
8959         if (has_ck505)
8960                 final |= DREF_NONSPREAD_CK505_ENABLE;
8961         else
8962                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8963
8964         final &= ~DREF_SSC_SOURCE_MASK;
8965         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8966         final &= ~DREF_SSC1_ENABLE;
8967
8968         if (has_panel) {
8969                 final |= DREF_SSC_SOURCE_ENABLE;
8970
8971                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8972                         final |= DREF_SSC1_ENABLE;
8973
8974                 if (has_cpu_edp) {
8975                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
8976                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8977                         else
8978                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8979                 } else
8980                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8981         } else if (using_ssc_source) {
8982                 final |= DREF_SSC_SOURCE_ENABLE;
8983                 final |= DREF_SSC1_ENABLE;
8984         }
8985
8986         if (final == val)
8987                 return;
8988
8989         /* Always enable nonspread source */
8990         val &= ~DREF_NONSPREAD_SOURCE_MASK;
8991
8992         if (has_ck505)
8993                 val |= DREF_NONSPREAD_CK505_ENABLE;
8994         else
8995                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8996
8997         if (has_panel) {
8998                 val &= ~DREF_SSC_SOURCE_MASK;
8999                 val |= DREF_SSC_SOURCE_ENABLE;
9000
9001                 /* SSC must be turned on before enabling the CPU output  */
9002                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
9003                         DRM_DEBUG_KMS("Using SSC on panel\n");
9004                         val |= DREF_SSC1_ENABLE;
9005                 } else
9006                         val &= ~DREF_SSC1_ENABLE;
9007
9008                 /* Get SSC going before enabling the outputs */
9009                 I915_WRITE(PCH_DREF_CONTROL, val);
9010                 POSTING_READ(PCH_DREF_CONTROL);
9011                 udelay(200);
9012
9013                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9014
9015                 /* Enable CPU source on CPU attached eDP */
9016                 if (has_cpu_edp) {
9017                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
9018                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
9019                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
9020                         } else
9021                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
9022                 } else
9023                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9024
9025                 I915_WRITE(PCH_DREF_CONTROL, val);
9026                 POSTING_READ(PCH_DREF_CONTROL);
9027                 udelay(200);
9028         } else {
9029                 DRM_DEBUG_KMS("Disabling CPU source output\n");
9030
9031                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9032
9033                 /* Turn off CPU output */
9034                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9035
9036                 I915_WRITE(PCH_DREF_CONTROL, val);
9037                 POSTING_READ(PCH_DREF_CONTROL);
9038                 udelay(200);
9039
9040                 if (!using_ssc_source) {
9041                         DRM_DEBUG_KMS("Disabling SSC source\n");
9042
9043                         /* Turn off the SSC source */
9044                         val &= ~DREF_SSC_SOURCE_MASK;
9045                         val |= DREF_SSC_SOURCE_DISABLE;
9046
9047                         /* Turn off SSC1 */
9048                         val &= ~DREF_SSC1_ENABLE;
9049
9050                         I915_WRITE(PCH_DREF_CONTROL, val);
9051                         POSTING_READ(PCH_DREF_CONTROL);
9052                         udelay(200);
9053                 }
9054         }
9055
9056         BUG_ON(val != final);
9057 }
9058
9059 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
9060 {
9061         uint32_t tmp;
9062
9063         tmp = I915_READ(SOUTH_CHICKEN2);
9064         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
9065         I915_WRITE(SOUTH_CHICKEN2, tmp);
9066
9067         if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
9068                         FDI_MPHY_IOSFSB_RESET_STATUS, 100))
9069                 DRM_ERROR("FDI mPHY reset assert timeout\n");
9070
9071         tmp = I915_READ(SOUTH_CHICKEN2);
9072         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
9073         I915_WRITE(SOUTH_CHICKEN2, tmp);
9074
9075         if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
9076                          FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
9077                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
9078 }
9079
9080 /* WaMPhyProgramming:hsw */
9081 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
9082 {
9083         uint32_t tmp;
9084
9085         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
9086         tmp &= ~(0xFF << 24);
9087         tmp |= (0x12 << 24);
9088         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
9089
9090         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
9091         tmp |= (1 << 11);
9092         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
9093
9094         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
9095         tmp |= (1 << 11);
9096         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
9097
9098         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
9099         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9100         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
9101
9102         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
9103         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9104         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
9105
9106         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
9107         tmp &= ~(7 << 13);
9108         tmp |= (5 << 13);
9109         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
9110
9111         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
9112         tmp &= ~(7 << 13);
9113         tmp |= (5 << 13);
9114         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
9115
9116         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
9117         tmp &= ~0xFF;
9118         tmp |= 0x1C;
9119         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
9120
9121         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
9122         tmp &= ~0xFF;
9123         tmp |= 0x1C;
9124         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
9125
9126         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
9127         tmp &= ~(0xFF << 16);
9128         tmp |= (0x1C << 16);
9129         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
9130
9131         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
9132         tmp &= ~(0xFF << 16);
9133         tmp |= (0x1C << 16);
9134         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
9135
9136         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
9137         tmp |= (1 << 27);
9138         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
9139
9140         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
9141         tmp |= (1 << 27);
9142         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
9143
9144         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
9145         tmp &= ~(0xF << 28);
9146         tmp |= (4 << 28);
9147         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
9148
9149         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
9150         tmp &= ~(0xF << 28);
9151         tmp |= (4 << 28);
9152         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
9153 }
9154
9155 /* Implements 3 different sequences from BSpec chapter "Display iCLK
9156  * Programming" based on the parameters passed:
9157  * - Sequence to enable CLKOUT_DP
9158  * - Sequence to enable CLKOUT_DP without spread
9159  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
9160  */
9161 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
9162                                  bool with_fdi)
9163 {
9164         struct drm_i915_private *dev_priv = to_i915(dev);
9165         uint32_t reg, tmp;
9166
9167         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
9168                 with_spread = true;
9169         if (WARN(HAS_PCH_LPT_LP(dev_priv) &&
9170             with_fdi, "LP PCH doesn't have FDI\n"))
9171                 with_fdi = false;
9172
9173         mutex_lock(&dev_priv->sb_lock);
9174
9175         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9176         tmp &= ~SBI_SSCCTL_DISABLE;
9177         tmp |= SBI_SSCCTL_PATHALT;
9178         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9179
9180         udelay(24);
9181
9182         if (with_spread) {
9183                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9184                 tmp &= ~SBI_SSCCTL_PATHALT;
9185                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9186
9187                 if (with_fdi) {
9188                         lpt_reset_fdi_mphy(dev_priv);
9189                         lpt_program_fdi_mphy(dev_priv);
9190                 }
9191         }
9192
9193         reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
9194         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9195         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9196         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9197
9198         mutex_unlock(&dev_priv->sb_lock);
9199 }
9200
9201 /* Sequence to disable CLKOUT_DP */
9202 static void lpt_disable_clkout_dp(struct drm_device *dev)
9203 {
9204         struct drm_i915_private *dev_priv = to_i915(dev);
9205         uint32_t reg, tmp;
9206
9207         mutex_lock(&dev_priv->sb_lock);
9208
9209         reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
9210         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9211         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9212         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9213
9214         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9215         if (!(tmp & SBI_SSCCTL_DISABLE)) {
9216                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
9217                         tmp |= SBI_SSCCTL_PATHALT;
9218                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9219                         udelay(32);
9220                 }
9221                 tmp |= SBI_SSCCTL_DISABLE;
9222                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9223         }
9224
9225         mutex_unlock(&dev_priv->sb_lock);
9226 }
9227
9228 #define BEND_IDX(steps) ((50 + (steps)) / 5)
9229
9230 static const uint16_t sscdivintphase[] = {
9231         [BEND_IDX( 50)] = 0x3B23,
9232         [BEND_IDX( 45)] = 0x3B23,
9233         [BEND_IDX( 40)] = 0x3C23,
9234         [BEND_IDX( 35)] = 0x3C23,
9235         [BEND_IDX( 30)] = 0x3D23,
9236         [BEND_IDX( 25)] = 0x3D23,
9237         [BEND_IDX( 20)] = 0x3E23,
9238         [BEND_IDX( 15)] = 0x3E23,
9239         [BEND_IDX( 10)] = 0x3F23,
9240         [BEND_IDX(  5)] = 0x3F23,
9241         [BEND_IDX(  0)] = 0x0025,
9242         [BEND_IDX( -5)] = 0x0025,
9243         [BEND_IDX(-10)] = 0x0125,
9244         [BEND_IDX(-15)] = 0x0125,
9245         [BEND_IDX(-20)] = 0x0225,
9246         [BEND_IDX(-25)] = 0x0225,
9247         [BEND_IDX(-30)] = 0x0325,
9248         [BEND_IDX(-35)] = 0x0325,
9249         [BEND_IDX(-40)] = 0x0425,
9250         [BEND_IDX(-45)] = 0x0425,
9251         [BEND_IDX(-50)] = 0x0525,
9252 };
9253
9254 /*
9255  * Bend CLKOUT_DP
9256  * steps -50 to 50 inclusive, in steps of 5
9257  * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
9258  * change in clock period = -(steps / 10) * 5.787 ps
9259  */
9260 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
9261 {
9262         uint32_t tmp;
9263         int idx = BEND_IDX(steps);
9264
9265         if (WARN_ON(steps % 5 != 0))
9266                 return;
9267
9268         if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
9269                 return;
9270
9271         mutex_lock(&dev_priv->sb_lock);
9272
9273         if (steps % 10 != 0)
9274                 tmp = 0xAAAAAAAB;
9275         else
9276                 tmp = 0x00000000;
9277         intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
9278
9279         tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
9280         tmp &= 0xffff0000;
9281         tmp |= sscdivintphase[idx];
9282         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
9283
9284         mutex_unlock(&dev_priv->sb_lock);
9285 }
9286
9287 #undef BEND_IDX
9288
9289 static void lpt_init_pch_refclk(struct drm_device *dev)
9290 {
9291         struct intel_encoder *encoder;
9292         bool has_vga = false;
9293
9294         for_each_intel_encoder(dev, encoder) {
9295                 switch (encoder->type) {
9296                 case INTEL_OUTPUT_ANALOG:
9297                         has_vga = true;
9298                         break;
9299                 default:
9300                         break;
9301                 }
9302         }
9303
9304         if (has_vga) {
9305                 lpt_bend_clkout_dp(to_i915(dev), 0);
9306                 lpt_enable_clkout_dp(dev, true, true);
9307         } else {
9308                 lpt_disable_clkout_dp(dev);
9309         }
9310 }
9311
9312 /*
9313  * Initialize reference clocks when the driver loads
9314  */
9315 void intel_init_pch_refclk(struct drm_device *dev)
9316 {
9317         struct drm_i915_private *dev_priv = to_i915(dev);
9318
9319         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
9320                 ironlake_init_pch_refclk(dev);
9321         else if (HAS_PCH_LPT(dev_priv))
9322                 lpt_init_pch_refclk(dev);
9323 }
9324
9325 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
9326 {
9327         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
9328         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9329         int pipe = intel_crtc->pipe;
9330         uint32_t val;
9331
9332         val = 0;
9333
9334         switch (intel_crtc->config->pipe_bpp) {
9335         case 18:
9336                 val |= PIPECONF_6BPC;
9337                 break;
9338         case 24:
9339                 val |= PIPECONF_8BPC;
9340                 break;
9341         case 30:
9342                 val |= PIPECONF_10BPC;
9343                 break;
9344         case 36:
9345                 val |= PIPECONF_12BPC;
9346                 break;
9347         default:
9348                 /* Case prevented by intel_choose_pipe_bpp_dither. */
9349                 BUG();
9350         }
9351
9352         if (intel_crtc->config->dither)
9353                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
9354
9355         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
9356                 val |= PIPECONF_INTERLACED_ILK;
9357         else
9358                 val |= PIPECONF_PROGRESSIVE;
9359
9360         if (intel_crtc->config->limited_color_range)
9361                 val |= PIPECONF_COLOR_RANGE_SELECT;
9362
9363         I915_WRITE(PIPECONF(pipe), val);
9364         POSTING_READ(PIPECONF(pipe));
9365 }
9366
9367 static void haswell_set_pipeconf(struct drm_crtc *crtc)
9368 {
9369         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
9370         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9371         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
9372         u32 val = 0;
9373
9374         if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
9375                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
9376
9377         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
9378                 val |= PIPECONF_INTERLACED_ILK;
9379         else
9380                 val |= PIPECONF_PROGRESSIVE;
9381
9382         I915_WRITE(PIPECONF(cpu_transcoder), val);
9383         POSTING_READ(PIPECONF(cpu_transcoder));
9384 }
9385
9386 static void haswell_set_pipemisc(struct drm_crtc *crtc)
9387 {
9388         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
9389         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9390
9391         if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
9392                 u32 val = 0;
9393
9394                 switch (intel_crtc->config->pipe_bpp) {
9395                 case 18:
9396                         val |= PIPEMISC_DITHER_6_BPC;
9397                         break;
9398                 case 24:
9399                         val |= PIPEMISC_DITHER_8_BPC;
9400                         break;
9401                 case 30:
9402                         val |= PIPEMISC_DITHER_10_BPC;
9403                         break;
9404                 case 36:
9405                         val |= PIPEMISC_DITHER_12_BPC;
9406                         break;
9407                 default:
9408                         /* Case prevented by pipe_config_set_bpp. */
9409                         BUG();
9410                 }
9411
9412                 if (intel_crtc->config->dither)
9413                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
9414
9415                 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
9416         }
9417 }
9418
9419 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
9420 {
9421         /*
9422          * Account for spread spectrum to avoid
9423          * oversubscribing the link. Max center spread
9424          * is 2.5%; use 5% for safety's sake.
9425          */
9426         u32 bps = target_clock * bpp * 21 / 20;
9427         return DIV_ROUND_UP(bps, link_bw * 8);
9428 }
9429
9430 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
9431 {
9432         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
9433 }
9434
9435 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
9436                                   struct intel_crtc_state *crtc_state,
9437                                   struct dpll *reduced_clock)
9438 {
9439         struct drm_crtc *crtc = &intel_crtc->base;
9440         struct drm_device *dev = crtc->dev;
9441         struct drm_i915_private *dev_priv = to_i915(dev);
9442         u32 dpll, fp, fp2;
9443         int factor;
9444
9445         /* Enable autotuning of the PLL clock (if permissible) */
9446         factor = 21;
9447         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9448                 if ((intel_panel_use_ssc(dev_priv) &&
9449                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
9450                     (HAS_PCH_IBX(dev_priv) && intel_is_dual_link_lvds(dev)))
9451                         factor = 25;
9452         } else if (crtc_state->sdvo_tv_clock)
9453                 factor = 20;
9454
9455         fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
9456
9457         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
9458                 fp |= FP_CB_TUNE;
9459
9460         if (reduced_clock) {
9461                 fp2 = i9xx_dpll_compute_fp(reduced_clock);
9462
9463                 if (reduced_clock->m < factor * reduced_clock->n)
9464                         fp2 |= FP_CB_TUNE;
9465         } else {
9466                 fp2 = fp;
9467         }
9468
9469         dpll = 0;
9470
9471         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
9472                 dpll |= DPLLB_MODE_LVDS;
9473         else
9474                 dpll |= DPLLB_MODE_DAC_SERIAL;
9475
9476         dpll |= (crtc_state->pixel_multiplier - 1)
9477                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
9478
9479         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
9480             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
9481                 dpll |= DPLL_SDVO_HIGH_SPEED;
9482
9483         if (intel_crtc_has_dp_encoder(crtc_state))
9484                 dpll |= DPLL_SDVO_HIGH_SPEED;
9485
9486         /*
9487          * The high speed IO clock is only really required for
9488          * SDVO/HDMI/DP, but we also enable it for CRT to make it
9489          * possible to share the DPLL between CRT and HDMI. Enabling
9490          * the clock needlessly does no real harm, except use up a
9491          * bit of power potentially.
9492          *
9493          * We'll limit this to IVB with 3 pipes, since it has only two
9494          * DPLLs and so DPLL sharing is the only way to get three pipes
9495          * driving PCH ports at the same time. On SNB we could do this,
9496          * and potentially avoid enabling the second DPLL, but it's not
9497          * clear if it''s a win or loss power wise. No point in doing
9498          * this on ILK at all since it has a fixed DPLL<->pipe mapping.
9499          */
9500         if (INTEL_INFO(dev_priv)->num_pipes == 3 &&
9501             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
9502                 dpll |= DPLL_SDVO_HIGH_SPEED;
9503
9504         /* compute bitmask from p1 value */
9505         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
9506         /* also FPA1 */
9507         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
9508
9509         switch (crtc_state->dpll.p2) {
9510         case 5:
9511                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
9512                 break;
9513         case 7:
9514                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
9515                 break;
9516         case 10:
9517                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
9518                 break;
9519         case 14:
9520                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
9521                 break;
9522         }
9523
9524         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
9525             intel_panel_use_ssc(dev_priv))
9526                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
9527         else
9528                 dpll |= PLL_REF_INPUT_DREFCLK;
9529
9530         dpll |= DPLL_VCO_ENABLE;
9531
9532         crtc_state->dpll_hw_state.dpll = dpll;
9533         crtc_state->dpll_hw_state.fp0 = fp;
9534         crtc_state->dpll_hw_state.fp1 = fp2;
9535 }
9536
9537 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
9538                                        struct intel_crtc_state *crtc_state)
9539 {
9540         struct drm_device *dev = crtc->base.dev;
9541         struct drm_i915_private *dev_priv = to_i915(dev);
9542         struct dpll reduced_clock;
9543         bool has_reduced_clock = false;
9544         struct intel_shared_dpll *pll;
9545         const struct intel_limit *limit;
9546         int refclk = 120000;
9547
9548         memset(&crtc_state->dpll_hw_state, 0,
9549                sizeof(crtc_state->dpll_hw_state));
9550
9551         crtc->lowfreq_avail = false;
9552
9553         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
9554         if (!crtc_state->has_pch_encoder)
9555                 return 0;
9556
9557         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9558                 if (intel_panel_use_ssc(dev_priv)) {
9559                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
9560                                       dev_priv->vbt.lvds_ssc_freq);
9561                         refclk = dev_priv->vbt.lvds_ssc_freq;
9562                 }
9563
9564                 if (intel_is_dual_link_lvds(dev)) {
9565                         if (refclk == 100000)
9566                                 limit = &intel_limits_ironlake_dual_lvds_100m;
9567                         else
9568                                 limit = &intel_limits_ironlake_dual_lvds;
9569                 } else {
9570                         if (refclk == 100000)
9571                                 limit = &intel_limits_ironlake_single_lvds_100m;
9572                         else
9573                                 limit = &intel_limits_ironlake_single_lvds;
9574                 }
9575         } else {
9576                 limit = &intel_limits_ironlake_dac;
9577         }
9578
9579         if (!crtc_state->clock_set &&
9580             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9581                                 refclk, NULL, &crtc_state->dpll)) {
9582                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
9583                 return -EINVAL;
9584         }
9585
9586         ironlake_compute_dpll(crtc, crtc_state,
9587                               has_reduced_clock ? &reduced_clock : NULL);
9588
9589         pll = intel_get_shared_dpll(crtc, crtc_state, NULL);
9590         if (pll == NULL) {
9591                 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
9592                                  pipe_name(crtc->pipe));
9593                 return -EINVAL;
9594         }
9595
9596         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
9597             has_reduced_clock)
9598                 crtc->lowfreq_avail = true;
9599
9600         return 0;
9601 }
9602
9603 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
9604                                          struct intel_link_m_n *m_n)
9605 {
9606         struct drm_device *dev = crtc->base.dev;
9607         struct drm_i915_private *dev_priv = to_i915(dev);
9608         enum pipe pipe = crtc->pipe;
9609
9610         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
9611         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
9612         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
9613                 & ~TU_SIZE_MASK;
9614         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
9615         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
9616                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9617 }
9618
9619 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
9620                                          enum transcoder transcoder,
9621                                          struct intel_link_m_n *m_n,
9622                                          struct intel_link_m_n *m2_n2)
9623 {
9624         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9625         enum pipe pipe = crtc->pipe;
9626
9627         if (INTEL_GEN(dev_priv) >= 5) {
9628                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
9629                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
9630                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
9631                         & ~TU_SIZE_MASK;
9632                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9633                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9634                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9635                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
9636                  * gen < 8) and if DRRS is supported (to make sure the
9637                  * registers are not unnecessarily read).
9638                  */
9639                 if (m2_n2 && INTEL_GEN(dev_priv) < 8 &&
9640                         crtc->config->has_drrs) {
9641                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9642                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9643                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9644                                         & ~TU_SIZE_MASK;
9645                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9646                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9647                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9648                 }
9649         } else {
9650                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9651                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9652                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9653                         & ~TU_SIZE_MASK;
9654                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9655                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9656                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9657         }
9658 }
9659
9660 void intel_dp_get_m_n(struct intel_crtc *crtc,
9661                       struct intel_crtc_state *pipe_config)
9662 {
9663         if (pipe_config->has_pch_encoder)
9664                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9665         else
9666                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9667                                              &pipe_config->dp_m_n,
9668                                              &pipe_config->dp_m2_n2);
9669 }
9670
9671 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9672                                         struct intel_crtc_state *pipe_config)
9673 {
9674         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9675                                      &pipe_config->fdi_m_n, NULL);
9676 }
9677
9678 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9679                                     struct intel_crtc_state *pipe_config)
9680 {
9681         struct drm_device *dev = crtc->base.dev;
9682         struct drm_i915_private *dev_priv = to_i915(dev);
9683         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9684         uint32_t ps_ctrl = 0;
9685         int id = -1;
9686         int i;
9687
9688         /* find scaler attached to this pipe */
9689         for (i = 0; i < crtc->num_scalers; i++) {
9690                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9691                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9692                         id = i;
9693                         pipe_config->pch_pfit.enabled = true;
9694                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9695                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9696                         break;
9697                 }
9698         }
9699
9700         scaler_state->scaler_id = id;
9701         if (id >= 0) {
9702                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9703         } else {
9704                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9705         }
9706 }
9707
9708 static void
9709 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9710                                  struct intel_initial_plane_config *plane_config)
9711 {
9712         struct drm_device *dev = crtc->base.dev;
9713         struct drm_i915_private *dev_priv = to_i915(dev);
9714         u32 val, base, offset, stride_mult, tiling;
9715         int pipe = crtc->pipe;
9716         int fourcc, pixel_format;
9717         unsigned int aligned_height;
9718         struct drm_framebuffer *fb;
9719         struct intel_framebuffer *intel_fb;
9720
9721         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9722         if (!intel_fb) {
9723                 DRM_DEBUG_KMS("failed to alloc fb\n");
9724                 return;
9725         }
9726
9727         fb = &intel_fb->base;
9728
9729         val = I915_READ(PLANE_CTL(pipe, 0));
9730         if (!(val & PLANE_CTL_ENABLE))
9731                 goto error;
9732
9733         pixel_format = val & PLANE_CTL_FORMAT_MASK;
9734         fourcc = skl_format_to_fourcc(pixel_format,
9735                                       val & PLANE_CTL_ORDER_RGBX,
9736                                       val & PLANE_CTL_ALPHA_MASK);
9737         fb->pixel_format = fourcc;
9738         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9739
9740         tiling = val & PLANE_CTL_TILED_MASK;
9741         switch (tiling) {
9742         case PLANE_CTL_TILED_LINEAR:
9743                 fb->modifier = DRM_FORMAT_MOD_NONE;
9744                 break;
9745         case PLANE_CTL_TILED_X:
9746                 plane_config->tiling = I915_TILING_X;
9747                 fb->modifier = I915_FORMAT_MOD_X_TILED;
9748                 break;
9749         case PLANE_CTL_TILED_Y:
9750                 fb->modifier = I915_FORMAT_MOD_Y_TILED;
9751                 break;
9752         case PLANE_CTL_TILED_YF:
9753                 fb->modifier = I915_FORMAT_MOD_Yf_TILED;
9754                 break;
9755         default:
9756                 MISSING_CASE(tiling);
9757                 goto error;
9758         }
9759
9760         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9761         plane_config->base = base;
9762
9763         offset = I915_READ(PLANE_OFFSET(pipe, 0));
9764
9765         val = I915_READ(PLANE_SIZE(pipe, 0));
9766         fb->height = ((val >> 16) & 0xfff) + 1;
9767         fb->width = ((val >> 0) & 0x1fff) + 1;
9768
9769         val = I915_READ(PLANE_STRIDE(pipe, 0));
9770         stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier,
9771                                                 fb->pixel_format);
9772         fb->pitches[0] = (val & 0x3ff) * stride_mult;
9773
9774         aligned_height = intel_fb_align_height(dev, fb->height,
9775                                                fb->pixel_format,
9776                                                fb->modifier);
9777
9778         plane_config->size = fb->pitches[0] * aligned_height;
9779
9780         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9781                       pipe_name(pipe), fb->width, fb->height,
9782                       fb->bits_per_pixel, base, fb->pitches[0],
9783                       plane_config->size);
9784
9785         plane_config->fb = intel_fb;
9786         return;
9787
9788 error:
9789         kfree(intel_fb);
9790 }
9791
9792 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9793                                      struct intel_crtc_state *pipe_config)
9794 {
9795         struct drm_device *dev = crtc->base.dev;
9796         struct drm_i915_private *dev_priv = to_i915(dev);
9797         uint32_t tmp;
9798
9799         tmp = I915_READ(PF_CTL(crtc->pipe));
9800
9801         if (tmp & PF_ENABLE) {
9802                 pipe_config->pch_pfit.enabled = true;
9803                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9804                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9805
9806                 /* We currently do not free assignements of panel fitters on
9807                  * ivb/hsw (since we don't use the higher upscaling modes which
9808                  * differentiates them) so just WARN about this case for now. */
9809                 if (IS_GEN7(dev_priv)) {
9810                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9811                                 PF_PIPE_SEL_IVB(crtc->pipe));
9812                 }
9813         }
9814 }
9815
9816 static void
9817 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9818                                   struct intel_initial_plane_config *plane_config)
9819 {
9820         struct drm_device *dev = crtc->base.dev;
9821         struct drm_i915_private *dev_priv = to_i915(dev);
9822         u32 val, base, offset;
9823         int pipe = crtc->pipe;
9824         int fourcc, pixel_format;
9825         unsigned int aligned_height;
9826         struct drm_framebuffer *fb;
9827         struct intel_framebuffer *intel_fb;
9828
9829         val = I915_READ(DSPCNTR(pipe));
9830         if (!(val & DISPLAY_PLANE_ENABLE))
9831                 return;
9832
9833         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9834         if (!intel_fb) {
9835                 DRM_DEBUG_KMS("failed to alloc fb\n");
9836                 return;
9837         }
9838
9839         fb = &intel_fb->base;
9840
9841         if (INTEL_GEN(dev_priv) >= 4) {
9842                 if (val & DISPPLANE_TILED) {
9843                         plane_config->tiling = I915_TILING_X;
9844                         fb->modifier = I915_FORMAT_MOD_X_TILED;
9845                 }
9846         }
9847
9848         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9849         fourcc = i9xx_format_to_fourcc(pixel_format);
9850         fb->pixel_format = fourcc;
9851         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9852
9853         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9854         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
9855                 offset = I915_READ(DSPOFFSET(pipe));
9856         } else {
9857                 if (plane_config->tiling)
9858                         offset = I915_READ(DSPTILEOFF(pipe));
9859                 else
9860                         offset = I915_READ(DSPLINOFF(pipe));
9861         }
9862         plane_config->base = base;
9863
9864         val = I915_READ(PIPESRC(pipe));
9865         fb->width = ((val >> 16) & 0xfff) + 1;
9866         fb->height = ((val >> 0) & 0xfff) + 1;
9867
9868         val = I915_READ(DSPSTRIDE(pipe));
9869         fb->pitches[0] = val & 0xffffffc0;
9870
9871         aligned_height = intel_fb_align_height(dev, fb->height,
9872                                                fb->pixel_format,
9873                                                fb->modifier);
9874
9875         plane_config->size = fb->pitches[0] * aligned_height;
9876
9877         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9878                       pipe_name(pipe), fb->width, fb->height,
9879                       fb->bits_per_pixel, base, fb->pitches[0],
9880                       plane_config->size);
9881
9882         plane_config->fb = intel_fb;
9883 }
9884
9885 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9886                                      struct intel_crtc_state *pipe_config)
9887 {
9888         struct drm_device *dev = crtc->base.dev;
9889         struct drm_i915_private *dev_priv = to_i915(dev);
9890         enum intel_display_power_domain power_domain;
9891         uint32_t tmp;
9892         bool ret;
9893
9894         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9895         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9896                 return false;
9897
9898         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9899         pipe_config->shared_dpll = NULL;
9900
9901         ret = false;
9902         tmp = I915_READ(PIPECONF(crtc->pipe));
9903         if (!(tmp & PIPECONF_ENABLE))
9904                 goto out;
9905
9906         switch (tmp & PIPECONF_BPC_MASK) {
9907         case PIPECONF_6BPC:
9908                 pipe_config->pipe_bpp = 18;
9909                 break;
9910         case PIPECONF_8BPC:
9911                 pipe_config->pipe_bpp = 24;
9912                 break;
9913         case PIPECONF_10BPC:
9914                 pipe_config->pipe_bpp = 30;
9915                 break;
9916         case PIPECONF_12BPC:
9917                 pipe_config->pipe_bpp = 36;
9918                 break;
9919         default:
9920                 break;
9921         }
9922
9923         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9924                 pipe_config->limited_color_range = true;
9925
9926         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9927                 struct intel_shared_dpll *pll;
9928                 enum intel_dpll_id pll_id;
9929
9930                 pipe_config->has_pch_encoder = true;
9931
9932                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9933                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9934                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9935
9936                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9937
9938                 if (HAS_PCH_IBX(dev_priv)) {
9939                         /*
9940                          * The pipe->pch transcoder and pch transcoder->pll
9941                          * mapping is fixed.
9942                          */
9943                         pll_id = (enum intel_dpll_id) crtc->pipe;
9944                 } else {
9945                         tmp = I915_READ(PCH_DPLL_SEL);
9946                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9947                                 pll_id = DPLL_ID_PCH_PLL_B;
9948                         else
9949                                 pll_id= DPLL_ID_PCH_PLL_A;
9950                 }
9951
9952                 pipe_config->shared_dpll =
9953                         intel_get_shared_dpll_by_id(dev_priv, pll_id);
9954                 pll = pipe_config->shared_dpll;
9955
9956                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9957                                                  &pipe_config->dpll_hw_state));
9958
9959                 tmp = pipe_config->dpll_hw_state.dpll;
9960                 pipe_config->pixel_multiplier =
9961                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9962                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9963
9964                 ironlake_pch_clock_get(crtc, pipe_config);
9965         } else {
9966                 pipe_config->pixel_multiplier = 1;
9967         }
9968
9969         intel_get_pipe_timings(crtc, pipe_config);
9970         intel_get_pipe_src_size(crtc, pipe_config);
9971
9972         ironlake_get_pfit_config(crtc, pipe_config);
9973
9974         ret = true;
9975
9976 out:
9977         intel_display_power_put(dev_priv, power_domain);
9978
9979         return ret;
9980 }
9981
9982 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9983 {
9984         struct drm_device *dev = &dev_priv->drm;
9985         struct intel_crtc *crtc;
9986
9987         for_each_intel_crtc(dev, crtc)
9988                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9989                      pipe_name(crtc->pipe));
9990
9991         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9992         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9993         I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9994         I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9995         I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n");
9996         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9997              "CPU PWM1 enabled\n");
9998         if (IS_HASWELL(dev_priv))
9999                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
10000                      "CPU PWM2 enabled\n");
10001         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
10002              "PCH PWM1 enabled\n");
10003         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
10004              "Utility pin enabled\n");
10005         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
10006
10007         /*
10008          * In theory we can still leave IRQs enabled, as long as only the HPD
10009          * interrupts remain enabled. We used to check for that, but since it's
10010          * gen-specific and since we only disable LCPLL after we fully disable
10011          * the interrupts, the check below should be enough.
10012          */
10013         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
10014 }
10015
10016 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
10017 {
10018         if (IS_HASWELL(dev_priv))
10019                 return I915_READ(D_COMP_HSW);
10020         else
10021                 return I915_READ(D_COMP_BDW);
10022 }
10023
10024 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
10025 {
10026         if (IS_HASWELL(dev_priv)) {
10027                 mutex_lock(&dev_priv->rps.hw_lock);
10028                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
10029                                             val))
10030                         DRM_DEBUG_KMS("Failed to write to D_COMP\n");
10031                 mutex_unlock(&dev_priv->rps.hw_lock);
10032         } else {
10033                 I915_WRITE(D_COMP_BDW, val);
10034                 POSTING_READ(D_COMP_BDW);
10035         }
10036 }
10037
10038 /*
10039  * This function implements pieces of two sequences from BSpec:
10040  * - Sequence for display software to disable LCPLL
10041  * - Sequence for display software to allow package C8+
10042  * The steps implemented here are just the steps that actually touch the LCPLL
10043  * register. Callers should take care of disabling all the display engine
10044  * functions, doing the mode unset, fixing interrupts, etc.
10045  */
10046 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
10047                               bool switch_to_fclk, bool allow_power_down)
10048 {
10049         uint32_t val;
10050
10051         assert_can_disable_lcpll(dev_priv);
10052
10053         val = I915_READ(LCPLL_CTL);
10054
10055         if (switch_to_fclk) {
10056                 val |= LCPLL_CD_SOURCE_FCLK;
10057                 I915_WRITE(LCPLL_CTL, val);
10058
10059                 if (wait_for_us(I915_READ(LCPLL_CTL) &
10060                                 LCPLL_CD_SOURCE_FCLK_DONE, 1))
10061                         DRM_ERROR("Switching to FCLK failed\n");
10062
10063                 val = I915_READ(LCPLL_CTL);
10064         }
10065
10066         val |= LCPLL_PLL_DISABLE;
10067         I915_WRITE(LCPLL_CTL, val);
10068         POSTING_READ(LCPLL_CTL);
10069
10070         if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
10071                 DRM_ERROR("LCPLL still locked\n");
10072
10073         val = hsw_read_dcomp(dev_priv);
10074         val |= D_COMP_COMP_DISABLE;
10075         hsw_write_dcomp(dev_priv, val);
10076         ndelay(100);
10077
10078         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
10079                      1))
10080                 DRM_ERROR("D_COMP RCOMP still in progress\n");
10081
10082         if (allow_power_down) {
10083                 val = I915_READ(LCPLL_CTL);
10084                 val |= LCPLL_POWER_DOWN_ALLOW;
10085                 I915_WRITE(LCPLL_CTL, val);
10086                 POSTING_READ(LCPLL_CTL);
10087         }
10088 }
10089
10090 /*
10091  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
10092  * source.
10093  */
10094 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
10095 {
10096         uint32_t val;
10097
10098         val = I915_READ(LCPLL_CTL);
10099
10100         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
10101                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
10102                 return;
10103
10104         /*
10105          * Make sure we're not on PC8 state before disabling PC8, otherwise
10106          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
10107          */
10108         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
10109
10110         if (val & LCPLL_POWER_DOWN_ALLOW) {
10111                 val &= ~LCPLL_POWER_DOWN_ALLOW;
10112                 I915_WRITE(LCPLL_CTL, val);
10113                 POSTING_READ(LCPLL_CTL);
10114         }
10115
10116         val = hsw_read_dcomp(dev_priv);
10117         val |= D_COMP_COMP_FORCE;
10118         val &= ~D_COMP_COMP_DISABLE;
10119         hsw_write_dcomp(dev_priv, val);
10120
10121         val = I915_READ(LCPLL_CTL);
10122         val &= ~LCPLL_PLL_DISABLE;
10123         I915_WRITE(LCPLL_CTL, val);
10124
10125         if (intel_wait_for_register(dev_priv,
10126                                     LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
10127                                     5))
10128                 DRM_ERROR("LCPLL not locked yet\n");
10129
10130         if (val & LCPLL_CD_SOURCE_FCLK) {
10131                 val = I915_READ(LCPLL_CTL);
10132                 val &= ~LCPLL_CD_SOURCE_FCLK;
10133                 I915_WRITE(LCPLL_CTL, val);
10134
10135                 if (wait_for_us((I915_READ(LCPLL_CTL) &
10136                                  LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
10137                         DRM_ERROR("Switching back to LCPLL failed\n");
10138         }
10139
10140         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
10141         intel_update_cdclk(dev_priv);
10142 }
10143
10144 /*
10145  * Package states C8 and deeper are really deep PC states that can only be
10146  * reached when all the devices on the system allow it, so even if the graphics
10147  * device allows PC8+, it doesn't mean the system will actually get to these
10148  * states. Our driver only allows PC8+ when going into runtime PM.
10149  *
10150  * The requirements for PC8+ are that all the outputs are disabled, the power
10151  * well is disabled and most interrupts are disabled, and these are also
10152  * requirements for runtime PM. When these conditions are met, we manually do
10153  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
10154  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
10155  * hang the machine.
10156  *
10157  * When we really reach PC8 or deeper states (not just when we allow it) we lose
10158  * the state of some registers, so when we come back from PC8+ we need to
10159  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
10160  * need to take care of the registers kept by RC6. Notice that this happens even
10161  * if we don't put the device in PCI D3 state (which is what currently happens
10162  * because of the runtime PM support).
10163  *
10164  * For more, read "Display Sequences for Package C8" on the hardware
10165  * documentation.
10166  */
10167 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
10168 {
10169         struct drm_device *dev = &dev_priv->drm;
10170         uint32_t val;
10171
10172         DRM_DEBUG_KMS("Enabling package C8+\n");
10173
10174         if (HAS_PCH_LPT_LP(dev_priv)) {
10175                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
10176                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
10177                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
10178         }
10179
10180         lpt_disable_clkout_dp(dev);
10181         hsw_disable_lcpll(dev_priv, true, true);
10182 }
10183
10184 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
10185 {
10186         struct drm_device *dev = &dev_priv->drm;
10187         uint32_t val;
10188
10189         DRM_DEBUG_KMS("Disabling package C8+\n");
10190
10191         hsw_restore_lcpll(dev_priv);
10192         lpt_init_pch_refclk(dev);
10193
10194         if (HAS_PCH_LPT_LP(dev_priv)) {
10195                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
10196                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
10197                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
10198         }
10199 }
10200
10201 static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state)
10202 {
10203         struct drm_device *dev = old_state->dev;
10204         struct intel_atomic_state *old_intel_state =
10205                 to_intel_atomic_state(old_state);
10206         unsigned int req_cdclk = old_intel_state->dev_cdclk;
10207
10208         bxt_set_cdclk(to_i915(dev), req_cdclk);
10209 }
10210
10211 static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state,
10212                                           int pixel_rate)
10213 {
10214         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
10215
10216         /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
10217         if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
10218                 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
10219
10220         /* BSpec says "Do not use DisplayPort with CDCLK less than
10221          * 432 MHz, audio enabled, port width x4, and link rate
10222          * HBR2 (5.4 GHz), or else there may be audio corruption or
10223          * screen corruption."
10224          */
10225         if (intel_crtc_has_dp_encoder(crtc_state) &&
10226             crtc_state->has_audio &&
10227             crtc_state->port_clock >= 540000 &&
10228             crtc_state->lane_count == 4)
10229                 pixel_rate = max(432000, pixel_rate);
10230
10231         return pixel_rate;
10232 }
10233
10234 /* compute the max rate for new configuration */
10235 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
10236 {
10237         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
10238         struct drm_i915_private *dev_priv = to_i915(state->dev);
10239         struct drm_crtc *crtc;
10240         struct drm_crtc_state *cstate;
10241         struct intel_crtc_state *crtc_state;
10242         unsigned max_pixel_rate = 0, i;
10243         enum pipe pipe;
10244
10245         memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
10246                sizeof(intel_state->min_pixclk));
10247
10248         for_each_crtc_in_state(state, crtc, cstate, i) {
10249                 int pixel_rate;
10250
10251                 crtc_state = to_intel_crtc_state(cstate);
10252                 if (!crtc_state->base.enable) {
10253                         intel_state->min_pixclk[i] = 0;
10254                         continue;
10255                 }
10256
10257                 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
10258
10259                 if (IS_BROADWELL(dev_priv) || IS_GEN9(dev_priv))
10260                         pixel_rate = bdw_adjust_min_pipe_pixel_rate(crtc_state,
10261                                                                     pixel_rate);
10262
10263                 intel_state->min_pixclk[i] = pixel_rate;
10264         }
10265
10266         for_each_pipe(dev_priv, pipe)
10267                 max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate);
10268
10269         return max_pixel_rate;
10270 }
10271
10272 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
10273 {
10274         struct drm_i915_private *dev_priv = to_i915(dev);
10275         uint32_t val, data;
10276         int ret;
10277
10278         if (WARN((I915_READ(LCPLL_CTL) &
10279                   (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
10280                    LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
10281                    LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
10282                    LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
10283                  "trying to change cdclk frequency with cdclk not enabled\n"))
10284                 return;
10285
10286         mutex_lock(&dev_priv->rps.hw_lock);
10287         ret = sandybridge_pcode_write(dev_priv,
10288                                       BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
10289         mutex_unlock(&dev_priv->rps.hw_lock);
10290         if (ret) {
10291                 DRM_ERROR("failed to inform pcode about cdclk change\n");
10292                 return;
10293         }
10294
10295         val = I915_READ(LCPLL_CTL);
10296         val |= LCPLL_CD_SOURCE_FCLK;
10297         I915_WRITE(LCPLL_CTL, val);
10298
10299         if (wait_for_us(I915_READ(LCPLL_CTL) &
10300                         LCPLL_CD_SOURCE_FCLK_DONE, 1))
10301                 DRM_ERROR("Switching to FCLK failed\n");
10302
10303         val = I915_READ(LCPLL_CTL);
10304         val &= ~LCPLL_CLK_FREQ_MASK;
10305
10306         switch (cdclk) {
10307         case 450000:
10308                 val |= LCPLL_CLK_FREQ_450;
10309                 data = 0;
10310                 break;
10311         case 540000:
10312                 val |= LCPLL_CLK_FREQ_54O_BDW;
10313                 data = 1;
10314                 break;
10315         case 337500:
10316                 val |= LCPLL_CLK_FREQ_337_5_BDW;
10317                 data = 2;
10318                 break;
10319         case 675000:
10320                 val |= LCPLL_CLK_FREQ_675_BDW;
10321                 data = 3;
10322                 break;
10323         default:
10324                 WARN(1, "invalid cdclk frequency\n");
10325                 return;
10326         }
10327
10328         I915_WRITE(LCPLL_CTL, val);
10329
10330         val = I915_READ(LCPLL_CTL);
10331         val &= ~LCPLL_CD_SOURCE_FCLK;
10332         I915_WRITE(LCPLL_CTL, val);
10333
10334         if (wait_for_us((I915_READ(LCPLL_CTL) &
10335                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
10336                 DRM_ERROR("Switching back to LCPLL failed\n");
10337
10338         mutex_lock(&dev_priv->rps.hw_lock);
10339         sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
10340         mutex_unlock(&dev_priv->rps.hw_lock);
10341
10342         I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
10343
10344         intel_update_cdclk(dev_priv);
10345
10346         WARN(cdclk != dev_priv->cdclk_freq,
10347              "cdclk requested %d kHz but got %d kHz\n",
10348              cdclk, dev_priv->cdclk_freq);
10349 }
10350
10351 static int broadwell_calc_cdclk(int max_pixclk)
10352 {
10353         if (max_pixclk > 540000)
10354                 return 675000;
10355         else if (max_pixclk > 450000)
10356                 return 540000;
10357         else if (max_pixclk > 337500)
10358                 return 450000;
10359         else
10360                 return 337500;
10361 }
10362
10363 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
10364 {
10365         struct drm_i915_private *dev_priv = to_i915(state->dev);
10366         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
10367         int max_pixclk = ilk_max_pixel_rate(state);
10368         int cdclk;
10369
10370         /*
10371          * FIXME should also account for plane ratio
10372          * once 64bpp pixel formats are supported.
10373          */
10374         cdclk = broadwell_calc_cdclk(max_pixclk);
10375
10376         if (cdclk > dev_priv->max_cdclk_freq) {
10377                 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
10378                               cdclk, dev_priv->max_cdclk_freq);
10379                 return -EINVAL;
10380         }
10381
10382         intel_state->cdclk = intel_state->dev_cdclk = cdclk;
10383         if (!intel_state->active_crtcs)
10384                 intel_state->dev_cdclk = broadwell_calc_cdclk(0);
10385
10386         return 0;
10387 }
10388
10389 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
10390 {
10391         struct drm_device *dev = old_state->dev;
10392         struct intel_atomic_state *old_intel_state =
10393                 to_intel_atomic_state(old_state);
10394         unsigned req_cdclk = old_intel_state->dev_cdclk;
10395
10396         broadwell_set_cdclk(dev, req_cdclk);
10397 }
10398
10399 static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
10400 {
10401         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
10402         struct drm_i915_private *dev_priv = to_i915(state->dev);
10403         const int max_pixclk = ilk_max_pixel_rate(state);
10404         int vco = intel_state->cdclk_pll_vco;
10405         int cdclk;
10406
10407         /*
10408          * FIXME should also account for plane ratio
10409          * once 64bpp pixel formats are supported.
10410          */
10411         cdclk = skl_calc_cdclk(max_pixclk, vco);
10412
10413         /*
10414          * FIXME move the cdclk caclulation to
10415          * compute_config() so we can fail gracegully.
10416          */
10417         if (cdclk > dev_priv->max_cdclk_freq) {
10418                 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
10419                           cdclk, dev_priv->max_cdclk_freq);
10420                 cdclk = dev_priv->max_cdclk_freq;
10421         }
10422
10423         intel_state->cdclk = intel_state->dev_cdclk = cdclk;
10424         if (!intel_state->active_crtcs)
10425                 intel_state->dev_cdclk = skl_calc_cdclk(0, vco);
10426
10427         return 0;
10428 }
10429
10430 static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state)
10431 {
10432         struct drm_i915_private *dev_priv = to_i915(old_state->dev);
10433         struct intel_atomic_state *intel_state = to_intel_atomic_state(old_state);
10434         unsigned int req_cdclk = intel_state->dev_cdclk;
10435         unsigned int req_vco = intel_state->cdclk_pll_vco;
10436
10437         skl_set_cdclk(dev_priv, req_cdclk, req_vco);
10438 }
10439
10440 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
10441                                       struct intel_crtc_state *crtc_state)
10442 {
10443         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
10444                 if (!intel_ddi_pll_select(crtc, crtc_state))
10445                         return -EINVAL;
10446         }
10447
10448         crtc->lowfreq_avail = false;
10449
10450         return 0;
10451 }
10452
10453 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
10454                                 enum port port,
10455                                 struct intel_crtc_state *pipe_config)
10456 {
10457         enum intel_dpll_id id;
10458
10459         switch (port) {
10460         case PORT_A:
10461                 id = DPLL_ID_SKL_DPLL0;
10462                 break;
10463         case PORT_B:
10464                 id = DPLL_ID_SKL_DPLL1;
10465                 break;
10466         case PORT_C:
10467                 id = DPLL_ID_SKL_DPLL2;
10468                 break;
10469         default:
10470                 DRM_ERROR("Incorrect port type\n");
10471                 return;
10472         }
10473
10474         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10475 }
10476
10477 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
10478                                 enum port port,
10479                                 struct intel_crtc_state *pipe_config)
10480 {
10481         enum intel_dpll_id id;
10482         u32 temp;
10483
10484         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
10485         id = temp >> (port * 3 + 1);
10486
10487         if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3))
10488                 return;
10489
10490         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10491 }
10492
10493 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
10494                                 enum port port,
10495                                 struct intel_crtc_state *pipe_config)
10496 {
10497         enum intel_dpll_id id;
10498         uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
10499
10500         switch (ddi_pll_sel) {
10501         case PORT_CLK_SEL_WRPLL1:
10502                 id = DPLL_ID_WRPLL1;
10503                 break;
10504         case PORT_CLK_SEL_WRPLL2:
10505                 id = DPLL_ID_WRPLL2;
10506                 break;
10507         case PORT_CLK_SEL_SPLL:
10508                 id = DPLL_ID_SPLL;
10509                 break;
10510         case PORT_CLK_SEL_LCPLL_810:
10511                 id = DPLL_ID_LCPLL_810;
10512                 break;
10513         case PORT_CLK_SEL_LCPLL_1350:
10514                 id = DPLL_ID_LCPLL_1350;
10515                 break;
10516         case PORT_CLK_SEL_LCPLL_2700:
10517                 id = DPLL_ID_LCPLL_2700;
10518                 break;
10519         default:
10520                 MISSING_CASE(ddi_pll_sel);
10521                 /* fall through */
10522         case PORT_CLK_SEL_NONE:
10523                 return;
10524         }
10525
10526         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10527 }
10528
10529 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
10530                                      struct intel_crtc_state *pipe_config,
10531                                      unsigned long *power_domain_mask)
10532 {
10533         struct drm_device *dev = crtc->base.dev;
10534         struct drm_i915_private *dev_priv = to_i915(dev);
10535         enum intel_display_power_domain power_domain;
10536         u32 tmp;
10537
10538         /*
10539          * The pipe->transcoder mapping is fixed with the exception of the eDP
10540          * transcoder handled below.
10541          */
10542         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
10543
10544         /*
10545          * XXX: Do intel_display_power_get_if_enabled before reading this (for
10546          * consistency and less surprising code; it's in always on power).
10547          */
10548         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
10549         if (tmp & TRANS_DDI_FUNC_ENABLE) {
10550                 enum pipe trans_edp_pipe;
10551                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
10552                 default:
10553                         WARN(1, "unknown pipe linked to edp transcoder\n");
10554                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
10555                 case TRANS_DDI_EDP_INPUT_A_ON:
10556                         trans_edp_pipe = PIPE_A;
10557                         break;
10558                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
10559                         trans_edp_pipe = PIPE_B;
10560                         break;
10561                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
10562                         trans_edp_pipe = PIPE_C;
10563                         break;
10564                 }
10565
10566                 if (trans_edp_pipe == crtc->pipe)
10567                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
10568         }
10569
10570         power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
10571         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10572                 return false;
10573         *power_domain_mask |= BIT(power_domain);
10574
10575         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
10576
10577         return tmp & PIPECONF_ENABLE;
10578 }
10579
10580 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
10581                                          struct intel_crtc_state *pipe_config,
10582                                          unsigned long *power_domain_mask)
10583 {
10584         struct drm_device *dev = crtc->base.dev;
10585         struct drm_i915_private *dev_priv = to_i915(dev);
10586         enum intel_display_power_domain power_domain;
10587         enum port port;
10588         enum transcoder cpu_transcoder;
10589         u32 tmp;
10590
10591         for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
10592                 if (port == PORT_A)
10593                         cpu_transcoder = TRANSCODER_DSI_A;
10594                 else
10595                         cpu_transcoder = TRANSCODER_DSI_C;
10596
10597                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
10598                 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10599                         continue;
10600                 *power_domain_mask |= BIT(power_domain);
10601
10602                 /*
10603                  * The PLL needs to be enabled with a valid divider
10604                  * configuration, otherwise accessing DSI registers will hang
10605                  * the machine. See BSpec North Display Engine
10606                  * registers/MIPI[BXT]. We can break out here early, since we
10607                  * need the same DSI PLL to be enabled for both DSI ports.
10608                  */
10609                 if (!intel_dsi_pll_is_enabled(dev_priv))
10610                         break;
10611
10612                 /* XXX: this works for video mode only */
10613                 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
10614                 if (!(tmp & DPI_ENABLE))
10615                         continue;
10616
10617                 tmp = I915_READ(MIPI_CTRL(port));
10618                 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
10619                         continue;
10620
10621                 pipe_config->cpu_transcoder = cpu_transcoder;
10622                 break;
10623         }
10624
10625         return transcoder_is_dsi(pipe_config->cpu_transcoder);
10626 }
10627
10628 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
10629                                        struct intel_crtc_state *pipe_config)
10630 {
10631         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10632         struct intel_shared_dpll *pll;
10633         enum port port;
10634         uint32_t tmp;
10635
10636         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
10637
10638         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
10639
10640         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
10641                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
10642         else if (IS_BROXTON(dev_priv))
10643                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
10644         else
10645                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
10646
10647         pll = pipe_config->shared_dpll;
10648         if (pll) {
10649                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
10650                                                  &pipe_config->dpll_hw_state));
10651         }
10652
10653         /*
10654          * Haswell has only FDI/PCH transcoder A. It is which is connected to
10655          * DDI E. So just check whether this pipe is wired to DDI E and whether
10656          * the PCH transcoder is on.
10657          */
10658         if (INTEL_GEN(dev_priv) < 9 &&
10659             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
10660                 pipe_config->has_pch_encoder = true;
10661
10662                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
10663                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
10664                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
10665
10666                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
10667         }
10668 }
10669
10670 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
10671                                     struct intel_crtc_state *pipe_config)
10672 {
10673         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10674         enum intel_display_power_domain power_domain;
10675         unsigned long power_domain_mask;
10676         bool active;
10677
10678         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
10679         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10680                 return false;
10681         power_domain_mask = BIT(power_domain);
10682
10683         pipe_config->shared_dpll = NULL;
10684
10685         active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
10686
10687         if (IS_BROXTON(dev_priv) &&
10688             bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) {
10689                 WARN_ON(active);
10690                 active = true;
10691         }
10692
10693         if (!active)
10694                 goto out;
10695
10696         if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10697                 haswell_get_ddi_port_state(crtc, pipe_config);
10698                 intel_get_pipe_timings(crtc, pipe_config);
10699         }
10700
10701         intel_get_pipe_src_size(crtc, pipe_config);
10702
10703         pipe_config->gamma_mode =
10704                 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
10705
10706         if (INTEL_GEN(dev_priv) >= 9) {
10707                 skl_init_scalers(dev_priv, crtc, pipe_config);
10708
10709                 pipe_config->scaler_state.scaler_id = -1;
10710                 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
10711         }
10712
10713         power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
10714         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
10715                 power_domain_mask |= BIT(power_domain);
10716                 if (INTEL_GEN(dev_priv) >= 9)
10717                         skylake_get_pfit_config(crtc, pipe_config);
10718                 else
10719                         ironlake_get_pfit_config(crtc, pipe_config);
10720         }
10721
10722         if (IS_HASWELL(dev_priv))
10723                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
10724                         (I915_READ(IPS_CTL) & IPS_ENABLE);
10725
10726         if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
10727             !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10728                 pipe_config->pixel_multiplier =
10729                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
10730         } else {
10731                 pipe_config->pixel_multiplier = 1;
10732         }
10733
10734 out:
10735         for_each_power_domain(power_domain, power_domain_mask)
10736                 intel_display_power_put(dev_priv, power_domain);
10737
10738         return active;
10739 }
10740
10741 static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
10742                                const struct intel_plane_state *plane_state)
10743 {
10744         struct drm_device *dev = crtc->dev;
10745         struct drm_i915_private *dev_priv = to_i915(dev);
10746         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10747         uint32_t cntl = 0, size = 0;
10748
10749         if (plane_state && plane_state->base.visible) {
10750                 unsigned int width = plane_state->base.crtc_w;
10751                 unsigned int height = plane_state->base.crtc_h;
10752                 unsigned int stride = roundup_pow_of_two(width) * 4;
10753
10754                 switch (stride) {
10755                 default:
10756                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10757                                   width, stride);
10758                         stride = 256;
10759                         /* fallthrough */
10760                 case 256:
10761                 case 512:
10762                 case 1024:
10763                 case 2048:
10764                         break;
10765                 }
10766
10767                 cntl |= CURSOR_ENABLE |
10768                         CURSOR_GAMMA_ENABLE |
10769                         CURSOR_FORMAT_ARGB |
10770                         CURSOR_STRIDE(stride);
10771
10772                 size = (height << 12) | width;
10773         }
10774
10775         if (intel_crtc->cursor_cntl != 0 &&
10776             (intel_crtc->cursor_base != base ||
10777              intel_crtc->cursor_size != size ||
10778              intel_crtc->cursor_cntl != cntl)) {
10779                 /* On these chipsets we can only modify the base/size/stride
10780                  * whilst the cursor is disabled.
10781                  */
10782                 I915_WRITE(CURCNTR(PIPE_A), 0);
10783                 POSTING_READ(CURCNTR(PIPE_A));
10784                 intel_crtc->cursor_cntl = 0;
10785         }
10786
10787         if (intel_crtc->cursor_base != base) {
10788                 I915_WRITE(CURBASE(PIPE_A), base);
10789                 intel_crtc->cursor_base = base;
10790         }
10791
10792         if (intel_crtc->cursor_size != size) {
10793                 I915_WRITE(CURSIZE, size);
10794                 intel_crtc->cursor_size = size;
10795         }
10796
10797         if (intel_crtc->cursor_cntl != cntl) {
10798                 I915_WRITE(CURCNTR(PIPE_A), cntl);
10799                 POSTING_READ(CURCNTR(PIPE_A));
10800                 intel_crtc->cursor_cntl = cntl;
10801         }
10802 }
10803
10804 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
10805                                const struct intel_plane_state *plane_state)
10806 {
10807         struct drm_device *dev = crtc->dev;
10808         struct drm_i915_private *dev_priv = to_i915(dev);
10809         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10810         int pipe = intel_crtc->pipe;
10811         uint32_t cntl = 0;
10812
10813         if (plane_state && plane_state->base.visible) {
10814                 cntl = MCURSOR_GAMMA_ENABLE;
10815                 switch (plane_state->base.crtc_w) {
10816                         case 64:
10817                                 cntl |= CURSOR_MODE_64_ARGB_AX;
10818                                 break;
10819                         case 128:
10820                                 cntl |= CURSOR_MODE_128_ARGB_AX;
10821                                 break;
10822                         case 256:
10823                                 cntl |= CURSOR_MODE_256_ARGB_AX;
10824                                 break;
10825                         default:
10826                                 MISSING_CASE(plane_state->base.crtc_w);
10827                                 return;
10828                 }
10829                 cntl |= pipe << 28; /* Connect to correct pipe */
10830
10831                 if (HAS_DDI(dev_priv))
10832                         cntl |= CURSOR_PIPE_CSC_ENABLE;
10833
10834                 if (plane_state->base.rotation & DRM_ROTATE_180)
10835                         cntl |= CURSOR_ROTATE_180;
10836         }
10837
10838         if (intel_crtc->cursor_cntl != cntl) {
10839                 I915_WRITE(CURCNTR(pipe), cntl);
10840                 POSTING_READ(CURCNTR(pipe));
10841                 intel_crtc->cursor_cntl = cntl;
10842         }
10843
10844         /* and commit changes on next vblank */
10845         I915_WRITE(CURBASE(pipe), base);
10846         POSTING_READ(CURBASE(pipe));
10847
10848         intel_crtc->cursor_base = base;
10849 }
10850
10851 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10852 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10853                                      const struct intel_plane_state *plane_state)
10854 {
10855         struct drm_device *dev = crtc->dev;
10856         struct drm_i915_private *dev_priv = to_i915(dev);
10857         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10858         int pipe = intel_crtc->pipe;
10859         u32 base = intel_crtc->cursor_addr;
10860         u32 pos = 0;
10861
10862         if (plane_state) {
10863                 int x = plane_state->base.crtc_x;
10864                 int y = plane_state->base.crtc_y;
10865
10866                 if (x < 0) {
10867                         pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10868                         x = -x;
10869                 }
10870                 pos |= x << CURSOR_X_SHIFT;
10871
10872                 if (y < 0) {
10873                         pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10874                         y = -y;
10875                 }
10876                 pos |= y << CURSOR_Y_SHIFT;
10877
10878                 /* ILK+ do this automagically */
10879                 if (HAS_GMCH_DISPLAY(dev_priv) &&
10880                     plane_state->base.rotation & DRM_ROTATE_180) {
10881                         base += (plane_state->base.crtc_h *
10882                                  plane_state->base.crtc_w - 1) * 4;
10883                 }
10884         }
10885
10886         I915_WRITE(CURPOS(pipe), pos);
10887
10888         if (IS_845G(dev_priv) || IS_I865G(dev_priv))
10889                 i845_update_cursor(crtc, base, plane_state);
10890         else
10891                 i9xx_update_cursor(crtc, base, plane_state);
10892 }
10893
10894 static bool cursor_size_ok(struct drm_i915_private *dev_priv,
10895                            uint32_t width, uint32_t height)
10896 {
10897         if (width == 0 || height == 0)
10898                 return false;
10899
10900         /*
10901          * 845g/865g are special in that they are only limited by
10902          * the width of their cursors, the height is arbitrary up to
10903          * the precision of the register. Everything else requires
10904          * square cursors, limited to a few power-of-two sizes.
10905          */
10906         if (IS_845G(dev_priv) || IS_I865G(dev_priv)) {
10907                 if ((width & 63) != 0)
10908                         return false;
10909
10910                 if (width > (IS_845G(dev_priv) ? 64 : 512))
10911                         return false;
10912
10913                 if (height > 1023)
10914                         return false;
10915         } else {
10916                 switch (width | height) {
10917                 case 256:
10918                 case 128:
10919                         if (IS_GEN2(dev_priv))
10920                                 return false;
10921                 case 64:
10922                         break;
10923                 default:
10924                         return false;
10925                 }
10926         }
10927
10928         return true;
10929 }
10930
10931 /* VESA 640x480x72Hz mode to set on the pipe */
10932 static struct drm_display_mode load_detect_mode = {
10933         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10934                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10935 };
10936
10937 struct drm_framebuffer *
10938 __intel_framebuffer_create(struct drm_device *dev,
10939                            struct drm_mode_fb_cmd2 *mode_cmd,
10940                            struct drm_i915_gem_object *obj)
10941 {
10942         struct intel_framebuffer *intel_fb;
10943         int ret;
10944
10945         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10946         if (!intel_fb)
10947                 return ERR_PTR(-ENOMEM);
10948
10949         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10950         if (ret)
10951                 goto err;
10952
10953         return &intel_fb->base;
10954
10955 err:
10956         kfree(intel_fb);
10957         return ERR_PTR(ret);
10958 }
10959
10960 static struct drm_framebuffer *
10961 intel_framebuffer_create(struct drm_device *dev,
10962                          struct drm_mode_fb_cmd2 *mode_cmd,
10963                          struct drm_i915_gem_object *obj)
10964 {
10965         struct drm_framebuffer *fb;
10966         int ret;
10967
10968         ret = i915_mutex_lock_interruptible(dev);
10969         if (ret)
10970                 return ERR_PTR(ret);
10971         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10972         mutex_unlock(&dev->struct_mutex);
10973
10974         return fb;
10975 }
10976
10977 static u32
10978 intel_framebuffer_pitch_for_width(int width, int bpp)
10979 {
10980         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10981         return ALIGN(pitch, 64);
10982 }
10983
10984 static u32
10985 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10986 {
10987         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10988         return PAGE_ALIGN(pitch * mode->vdisplay);
10989 }
10990
10991 static struct drm_framebuffer *
10992 intel_framebuffer_create_for_mode(struct drm_device *dev,
10993                                   struct drm_display_mode *mode,
10994                                   int depth, int bpp)
10995 {
10996         struct drm_framebuffer *fb;
10997         struct drm_i915_gem_object *obj;
10998         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10999
11000         obj = i915_gem_object_create(dev,
11001                                     intel_framebuffer_size_for_mode(mode, bpp));
11002         if (IS_ERR(obj))
11003                 return ERR_CAST(obj);
11004
11005         mode_cmd.width = mode->hdisplay;
11006         mode_cmd.height = mode->vdisplay;
11007         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
11008                                                                 bpp);
11009         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
11010
11011         fb = intel_framebuffer_create(dev, &mode_cmd, obj);
11012         if (IS_ERR(fb))
11013                 i915_gem_object_put(obj);
11014
11015         return fb;
11016 }
11017
11018 static struct drm_framebuffer *
11019 mode_fits_in_fbdev(struct drm_device *dev,
11020                    struct drm_display_mode *mode)
11021 {
11022 #ifdef CONFIG_DRM_FBDEV_EMULATION
11023         struct drm_i915_private *dev_priv = to_i915(dev);
11024         struct drm_i915_gem_object *obj;
11025         struct drm_framebuffer *fb;
11026
11027         if (!dev_priv->fbdev)
11028                 return NULL;
11029
11030         if (!dev_priv->fbdev->fb)
11031                 return NULL;
11032
11033         obj = dev_priv->fbdev->fb->obj;
11034         BUG_ON(!obj);
11035
11036         fb = &dev_priv->fbdev->fb->base;
11037         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
11038                                                                fb->bits_per_pixel))
11039                 return NULL;
11040
11041         if (obj->base.size < mode->vdisplay * fb->pitches[0])
11042                 return NULL;
11043
11044         drm_framebuffer_reference(fb);
11045         return fb;
11046 #else
11047         return NULL;
11048 #endif
11049 }
11050
11051 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
11052                                            struct drm_crtc *crtc,
11053                                            struct drm_display_mode *mode,
11054                                            struct drm_framebuffer *fb,
11055                                            int x, int y)
11056 {
11057         struct drm_plane_state *plane_state;
11058         int hdisplay, vdisplay;
11059         int ret;
11060
11061         plane_state = drm_atomic_get_plane_state(state, crtc->primary);
11062         if (IS_ERR(plane_state))
11063                 return PTR_ERR(plane_state);
11064
11065         if (mode)
11066                 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
11067         else
11068                 hdisplay = vdisplay = 0;
11069
11070         ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
11071         if (ret)
11072                 return ret;
11073         drm_atomic_set_fb_for_plane(plane_state, fb);
11074         plane_state->crtc_x = 0;
11075         plane_state->crtc_y = 0;
11076         plane_state->crtc_w = hdisplay;
11077         plane_state->crtc_h = vdisplay;
11078         plane_state->src_x = x << 16;
11079         plane_state->src_y = y << 16;
11080         plane_state->src_w = hdisplay << 16;
11081         plane_state->src_h = vdisplay << 16;
11082
11083         return 0;
11084 }
11085
11086 bool intel_get_load_detect_pipe(struct drm_connector *connector,
11087                                 struct drm_display_mode *mode,
11088                                 struct intel_load_detect_pipe *old,
11089                                 struct drm_modeset_acquire_ctx *ctx)
11090 {
11091         struct intel_crtc *intel_crtc;
11092         struct intel_encoder *intel_encoder =
11093                 intel_attached_encoder(connector);
11094         struct drm_crtc *possible_crtc;
11095         struct drm_encoder *encoder = &intel_encoder->base;
11096         struct drm_crtc *crtc = NULL;
11097         struct drm_device *dev = encoder->dev;
11098         struct drm_i915_private *dev_priv = to_i915(dev);
11099         struct drm_framebuffer *fb;
11100         struct drm_mode_config *config = &dev->mode_config;
11101         struct drm_atomic_state *state = NULL, *restore_state = NULL;
11102         struct drm_connector_state *connector_state;
11103         struct intel_crtc_state *crtc_state;
11104         int ret, i = -1;
11105
11106         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
11107                       connector->base.id, connector->name,
11108                       encoder->base.id, encoder->name);
11109
11110         old->restore_state = NULL;
11111
11112 retry:
11113         ret = drm_modeset_lock(&config->connection_mutex, ctx);
11114         if (ret)
11115                 goto fail;
11116
11117         /*
11118          * Algorithm gets a little messy:
11119          *
11120          *   - if the connector already has an assigned crtc, use it (but make
11121          *     sure it's on first)
11122          *
11123          *   - try to find the first unused crtc that can drive this connector,
11124          *     and use that if we find one
11125          */
11126
11127         /* See if we already have a CRTC for this connector */
11128         if (connector->state->crtc) {
11129                 crtc = connector->state->crtc;
11130
11131                 ret = drm_modeset_lock(&crtc->mutex, ctx);
11132                 if (ret)
11133                         goto fail;
11134
11135                 /* Make sure the crtc and connector are running */
11136                 goto found;
11137         }
11138
11139         /* Find an unused one (if possible) */
11140         for_each_crtc(dev, possible_crtc) {
11141                 i++;
11142                 if (!(encoder->possible_crtcs & (1 << i)))
11143                         continue;
11144
11145                 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
11146                 if (ret)
11147                         goto fail;
11148
11149                 if (possible_crtc->state->enable) {
11150                         drm_modeset_unlock(&possible_crtc->mutex);
11151                         continue;
11152                 }
11153
11154                 crtc = possible_crtc;
11155                 break;
11156         }
11157
11158         /*
11159          * If we didn't find an unused CRTC, don't use any.
11160          */
11161         if (!crtc) {
11162                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
11163                 goto fail;
11164         }
11165
11166 found:
11167         intel_crtc = to_intel_crtc(crtc);
11168
11169         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
11170         if (ret)
11171                 goto fail;
11172
11173         state = drm_atomic_state_alloc(dev);
11174         restore_state = drm_atomic_state_alloc(dev);
11175         if (!state || !restore_state) {
11176                 ret = -ENOMEM;
11177                 goto fail;
11178         }
11179
11180         state->acquire_ctx = ctx;
11181         restore_state->acquire_ctx = ctx;
11182
11183         connector_state = drm_atomic_get_connector_state(state, connector);
11184         if (IS_ERR(connector_state)) {
11185                 ret = PTR_ERR(connector_state);
11186                 goto fail;
11187         }
11188
11189         ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
11190         if (ret)
11191                 goto fail;
11192
11193         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
11194         if (IS_ERR(crtc_state)) {
11195                 ret = PTR_ERR(crtc_state);
11196                 goto fail;
11197         }
11198
11199         crtc_state->base.active = crtc_state->base.enable = true;
11200
11201         if (!mode)
11202                 mode = &load_detect_mode;
11203
11204         /* We need a framebuffer large enough to accommodate all accesses
11205          * that the plane may generate whilst we perform load detection.
11206          * We can not rely on the fbcon either being present (we get called
11207          * during its initialisation to detect all boot displays, or it may
11208          * not even exist) or that it is large enough to satisfy the
11209          * requested mode.
11210          */
11211         fb = mode_fits_in_fbdev(dev, mode);
11212         if (fb == NULL) {
11213                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
11214                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
11215         } else
11216                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
11217         if (IS_ERR(fb)) {
11218                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
11219                 goto fail;
11220         }
11221
11222         ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
11223         if (ret)
11224                 goto fail;
11225
11226         drm_framebuffer_unreference(fb);
11227
11228         ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
11229         if (ret)
11230                 goto fail;
11231
11232         ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
11233         if (!ret)
11234                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
11235         if (!ret)
11236                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
11237         if (ret) {
11238                 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
11239                 goto fail;
11240         }
11241
11242         ret = drm_atomic_commit(state);
11243         if (ret) {
11244                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
11245                 goto fail;
11246         }
11247
11248         old->restore_state = restore_state;
11249
11250         /* let the connector get through one full cycle before testing */
11251         intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
11252         return true;
11253
11254 fail:
11255         if (state) {
11256                 drm_atomic_state_put(state);
11257                 state = NULL;
11258         }
11259         if (restore_state) {
11260                 drm_atomic_state_put(restore_state);
11261                 restore_state = NULL;
11262         }
11263
11264         if (ret == -EDEADLK) {
11265                 drm_modeset_backoff(ctx);
11266                 goto retry;
11267         }
11268
11269         return false;
11270 }
11271
11272 void intel_release_load_detect_pipe(struct drm_connector *connector,
11273                                     struct intel_load_detect_pipe *old,
11274                                     struct drm_modeset_acquire_ctx *ctx)
11275 {
11276         struct intel_encoder *intel_encoder =
11277                 intel_attached_encoder(connector);
11278         struct drm_encoder *encoder = &intel_encoder->base;
11279         struct drm_atomic_state *state = old->restore_state;
11280         int ret;
11281
11282         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
11283                       connector->base.id, connector->name,
11284                       encoder->base.id, encoder->name);
11285
11286         if (!state)
11287                 return;
11288
11289         ret = drm_atomic_commit(state);
11290         if (ret)
11291                 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
11292         drm_atomic_state_put(state);
11293 }
11294
11295 static int i9xx_pll_refclk(struct drm_device *dev,
11296                            const struct intel_crtc_state *pipe_config)
11297 {
11298         struct drm_i915_private *dev_priv = to_i915(dev);
11299         u32 dpll = pipe_config->dpll_hw_state.dpll;
11300
11301         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
11302                 return dev_priv->vbt.lvds_ssc_freq;
11303         else if (HAS_PCH_SPLIT(dev_priv))
11304                 return 120000;
11305         else if (!IS_GEN2(dev_priv))
11306                 return 96000;
11307         else
11308                 return 48000;
11309 }
11310
11311 /* Returns the clock of the currently programmed mode of the given pipe. */
11312 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
11313                                 struct intel_crtc_state *pipe_config)
11314 {
11315         struct drm_device *dev = crtc->base.dev;
11316         struct drm_i915_private *dev_priv = to_i915(dev);
11317         int pipe = pipe_config->cpu_transcoder;
11318         u32 dpll = pipe_config->dpll_hw_state.dpll;
11319         u32 fp;
11320         struct dpll clock;
11321         int port_clock;
11322         int refclk = i9xx_pll_refclk(dev, pipe_config);
11323
11324         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
11325                 fp = pipe_config->dpll_hw_state.fp0;
11326         else
11327                 fp = pipe_config->dpll_hw_state.fp1;
11328
11329         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
11330         if (IS_PINEVIEW(dev_priv)) {
11331                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
11332                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
11333         } else {
11334                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
11335                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
11336         }
11337
11338         if (!IS_GEN2(dev_priv)) {
11339                 if (IS_PINEVIEW(dev_priv))
11340                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
11341                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
11342                 else
11343                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
11344                                DPLL_FPA01_P1_POST_DIV_SHIFT);
11345
11346                 switch (dpll & DPLL_MODE_MASK) {
11347                 case DPLLB_MODE_DAC_SERIAL:
11348                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
11349                                 5 : 10;
11350                         break;
11351                 case DPLLB_MODE_LVDS:
11352                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
11353                                 7 : 14;
11354                         break;
11355                 default:
11356                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
11357                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
11358                         return;
11359                 }
11360
11361                 if (IS_PINEVIEW(dev_priv))
11362                         port_clock = pnv_calc_dpll_params(refclk, &clock);
11363                 else
11364                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
11365         } else {
11366                 u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS);
11367                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
11368
11369                 if (is_lvds) {
11370                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
11371                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
11372
11373                         if (lvds & LVDS_CLKB_POWER_UP)
11374                                 clock.p2 = 7;
11375                         else
11376                                 clock.p2 = 14;
11377                 } else {
11378                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
11379                                 clock.p1 = 2;
11380                         else {
11381                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
11382                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
11383                         }
11384                         if (dpll & PLL_P2_DIVIDE_BY_4)
11385                                 clock.p2 = 4;
11386                         else
11387                                 clock.p2 = 2;
11388                 }
11389
11390                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
11391         }
11392
11393         /*
11394          * This value includes pixel_multiplier. We will use
11395          * port_clock to compute adjusted_mode.crtc_clock in the
11396          * encoder's get_config() function.
11397          */
11398         pipe_config->port_clock = port_clock;
11399 }
11400
11401 int intel_dotclock_calculate(int link_freq,
11402                              const struct intel_link_m_n *m_n)
11403 {
11404         /*
11405          * The calculation for the data clock is:
11406          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
11407          * But we want to avoid losing precison if possible, so:
11408          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
11409          *
11410          * and the link clock is simpler:
11411          * link_clock = (m * link_clock) / n
11412          */
11413
11414         if (!m_n->link_n)
11415                 return 0;
11416
11417         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
11418 }
11419
11420 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
11421                                    struct intel_crtc_state *pipe_config)
11422 {
11423         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11424
11425         /* read out port_clock from the DPLL */
11426         i9xx_crtc_clock_get(crtc, pipe_config);
11427
11428         /*
11429          * In case there is an active pipe without active ports,
11430          * we may need some idea for the dotclock anyway.
11431          * Calculate one based on the FDI configuration.
11432          */
11433         pipe_config->base.adjusted_mode.crtc_clock =
11434                 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
11435                                          &pipe_config->fdi_m_n);
11436 }
11437
11438 /** Returns the currently programmed mode of the given pipe. */
11439 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
11440                                              struct drm_crtc *crtc)
11441 {
11442         struct drm_i915_private *dev_priv = to_i915(dev);
11443         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11444         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
11445         struct drm_display_mode *mode;
11446         struct intel_crtc_state *pipe_config;
11447         int htot = I915_READ(HTOTAL(cpu_transcoder));
11448         int hsync = I915_READ(HSYNC(cpu_transcoder));
11449         int vtot = I915_READ(VTOTAL(cpu_transcoder));
11450         int vsync = I915_READ(VSYNC(cpu_transcoder));
11451         enum pipe pipe = intel_crtc->pipe;
11452
11453         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
11454         if (!mode)
11455                 return NULL;
11456
11457         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
11458         if (!pipe_config) {
11459                 kfree(mode);
11460                 return NULL;
11461         }
11462
11463         /*
11464          * Construct a pipe_config sufficient for getting the clock info
11465          * back out of crtc_clock_get.
11466          *
11467          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
11468          * to use a real value here instead.
11469          */
11470         pipe_config->cpu_transcoder = (enum transcoder) pipe;
11471         pipe_config->pixel_multiplier = 1;
11472         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
11473         pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
11474         pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
11475         i9xx_crtc_clock_get(intel_crtc, pipe_config);
11476
11477         mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
11478         mode->hdisplay = (htot & 0xffff) + 1;
11479         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
11480         mode->hsync_start = (hsync & 0xffff) + 1;
11481         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
11482         mode->vdisplay = (vtot & 0xffff) + 1;
11483         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
11484         mode->vsync_start = (vsync & 0xffff) + 1;
11485         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
11486
11487         drm_mode_set_name(mode);
11488
11489         kfree(pipe_config);
11490
11491         return mode;
11492 }
11493
11494 static void intel_crtc_destroy(struct drm_crtc *crtc)
11495 {
11496         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11497         struct drm_device *dev = crtc->dev;
11498         struct intel_flip_work *work;
11499
11500         spin_lock_irq(&dev->event_lock);
11501         work = intel_crtc->flip_work;
11502         intel_crtc->flip_work = NULL;
11503         spin_unlock_irq(&dev->event_lock);
11504
11505         if (work) {
11506                 cancel_work_sync(&work->mmio_work);
11507                 cancel_work_sync(&work->unpin_work);
11508                 kfree(work);
11509         }
11510
11511         drm_crtc_cleanup(crtc);
11512
11513         kfree(intel_crtc);
11514 }
11515
11516 static void intel_unpin_work_fn(struct work_struct *__work)
11517 {
11518         struct intel_flip_work *work =
11519                 container_of(__work, struct intel_flip_work, unpin_work);
11520         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
11521         struct drm_device *dev = crtc->base.dev;
11522         struct drm_plane *primary = crtc->base.primary;
11523
11524         if (is_mmio_work(work))
11525                 flush_work(&work->mmio_work);
11526
11527         mutex_lock(&dev->struct_mutex);
11528         intel_unpin_fb_obj(work->old_fb, primary->state->rotation);
11529         i915_gem_object_put(work->pending_flip_obj);
11530         mutex_unlock(&dev->struct_mutex);
11531
11532         i915_gem_request_put(work->flip_queued_req);
11533
11534         intel_frontbuffer_flip_complete(to_i915(dev),
11535                                         to_intel_plane(primary)->frontbuffer_bit);
11536         intel_fbc_post_update(crtc);
11537         drm_framebuffer_unreference(work->old_fb);
11538
11539         BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
11540         atomic_dec(&crtc->unpin_work_count);
11541
11542         kfree(work);
11543 }
11544
11545 /* Is 'a' after or equal to 'b'? */
11546 static bool g4x_flip_count_after_eq(u32 a, u32 b)
11547 {
11548         return !((a - b) & 0x80000000);
11549 }
11550
11551 static bool __pageflip_finished_cs(struct intel_crtc *crtc,
11552                                    struct intel_flip_work *work)
11553 {
11554         struct drm_device *dev = crtc->base.dev;
11555         struct drm_i915_private *dev_priv = to_i915(dev);
11556
11557         if (abort_flip_on_reset(crtc))
11558                 return true;
11559
11560         /*
11561          * The relevant registers doen't exist on pre-ctg.
11562          * As the flip done interrupt doesn't trigger for mmio
11563          * flips on gmch platforms, a flip count check isn't
11564          * really needed there. But since ctg has the registers,
11565          * include it in the check anyway.
11566          */
11567         if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
11568                 return true;
11569
11570         /*
11571          * BDW signals flip done immediately if the plane
11572          * is disabled, even if the plane enable is already
11573          * armed to occur at the next vblank :(
11574          */
11575
11576         /*
11577          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
11578          * used the same base address. In that case the mmio flip might
11579          * have completed, but the CS hasn't even executed the flip yet.
11580          *
11581          * A flip count check isn't enough as the CS might have updated
11582          * the base address just after start of vblank, but before we
11583          * managed to process the interrupt. This means we'd complete the
11584          * CS flip too soon.
11585          *
11586          * Combining both checks should get us a good enough result. It may
11587          * still happen that the CS flip has been executed, but has not
11588          * yet actually completed. But in case the base address is the same
11589          * anyway, we don't really care.
11590          */
11591         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
11592                 crtc->flip_work->gtt_offset &&
11593                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
11594                                     crtc->flip_work->flip_count);
11595 }
11596
11597 static bool
11598 __pageflip_finished_mmio(struct intel_crtc *crtc,
11599                                struct intel_flip_work *work)
11600 {
11601         /*
11602          * MMIO work completes when vblank is different from
11603          * flip_queued_vblank.
11604          *
11605          * Reset counter value doesn't matter, this is handled by
11606          * i915_wait_request finishing early, so no need to handle
11607          * reset here.
11608          */
11609         return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank;
11610 }
11611
11612
11613 static bool pageflip_finished(struct intel_crtc *crtc,
11614                               struct intel_flip_work *work)
11615 {
11616         if (!atomic_read(&work->pending))
11617                 return false;
11618
11619         smp_rmb();
11620
11621         if (is_mmio_work(work))
11622                 return __pageflip_finished_mmio(crtc, work);
11623         else
11624                 return __pageflip_finished_cs(crtc, work);
11625 }
11626
11627 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe)
11628 {
11629         struct drm_device *dev = &dev_priv->drm;
11630         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
11631         struct intel_flip_work *work;
11632         unsigned long flags;
11633
11634         /* Ignore early vblank irqs */
11635         if (!crtc)
11636                 return;
11637
11638         /*
11639          * This is called both by irq handlers and the reset code (to complete
11640          * lost pageflips) so needs the full irqsave spinlocks.
11641          */
11642         spin_lock_irqsave(&dev->event_lock, flags);
11643         work = crtc->flip_work;
11644
11645         if (work != NULL &&
11646             !is_mmio_work(work) &&
11647             pageflip_finished(crtc, work))
11648                 page_flip_completed(crtc);
11649
11650         spin_unlock_irqrestore(&dev->event_lock, flags);
11651 }
11652
11653 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe)
11654 {
11655         struct drm_device *dev = &dev_priv->drm;
11656         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
11657         struct intel_flip_work *work;
11658         unsigned long flags;
11659
11660         /* Ignore early vblank irqs */
11661         if (!crtc)
11662                 return;
11663
11664         /*
11665          * This is called both by irq handlers and the reset code (to complete
11666          * lost pageflips) so needs the full irqsave spinlocks.
11667          */
11668         spin_lock_irqsave(&dev->event_lock, flags);
11669         work = crtc->flip_work;
11670
11671         if (work != NULL &&
11672             is_mmio_work(work) &&
11673             pageflip_finished(crtc, work))
11674                 page_flip_completed(crtc);
11675
11676         spin_unlock_irqrestore(&dev->event_lock, flags);
11677 }
11678
11679 static inline void intel_mark_page_flip_active(struct intel_crtc *crtc,
11680                                                struct intel_flip_work *work)
11681 {
11682         work->flip_queued_vblank = intel_crtc_get_vblank_counter(crtc);
11683
11684         /* Ensure that the work item is consistent when activating it ... */
11685         smp_mb__before_atomic();
11686         atomic_set(&work->pending, 1);
11687 }
11688
11689 static int intel_gen2_queue_flip(struct drm_device *dev,
11690                                  struct drm_crtc *crtc,
11691                                  struct drm_framebuffer *fb,
11692                                  struct drm_i915_gem_object *obj,
11693                                  struct drm_i915_gem_request *req,
11694                                  uint32_t flags)
11695 {
11696         struct intel_ring *ring = req->ring;
11697         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11698         u32 flip_mask;
11699         int ret;
11700
11701         ret = intel_ring_begin(req, 6);
11702         if (ret)
11703                 return ret;
11704
11705         /* Can't queue multiple flips, so wait for the previous
11706          * one to finish before executing the next.
11707          */
11708         if (intel_crtc->plane)
11709                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11710         else
11711                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11712         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11713         intel_ring_emit(ring, MI_NOOP);
11714         intel_ring_emit(ring, MI_DISPLAY_FLIP |
11715                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11716         intel_ring_emit(ring, fb->pitches[0]);
11717         intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11718         intel_ring_emit(ring, 0); /* aux display base address, unused */
11719
11720         return 0;
11721 }
11722
11723 static int intel_gen3_queue_flip(struct drm_device *dev,
11724                                  struct drm_crtc *crtc,
11725                                  struct drm_framebuffer *fb,
11726                                  struct drm_i915_gem_object *obj,
11727                                  struct drm_i915_gem_request *req,
11728                                  uint32_t flags)
11729 {
11730         struct intel_ring *ring = req->ring;
11731         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11732         u32 flip_mask;
11733         int ret;
11734
11735         ret = intel_ring_begin(req, 6);
11736         if (ret)
11737                 return ret;
11738
11739         if (intel_crtc->plane)
11740                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11741         else
11742                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11743         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11744         intel_ring_emit(ring, MI_NOOP);
11745         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
11746                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11747         intel_ring_emit(ring, fb->pitches[0]);
11748         intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11749         intel_ring_emit(ring, MI_NOOP);
11750
11751         return 0;
11752 }
11753
11754 static int intel_gen4_queue_flip(struct drm_device *dev,
11755                                  struct drm_crtc *crtc,
11756                                  struct drm_framebuffer *fb,
11757                                  struct drm_i915_gem_object *obj,
11758                                  struct drm_i915_gem_request *req,
11759                                  uint32_t flags)
11760 {
11761         struct intel_ring *ring = req->ring;
11762         struct drm_i915_private *dev_priv = to_i915(dev);
11763         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11764         uint32_t pf, pipesrc;
11765         int ret;
11766
11767         ret = intel_ring_begin(req, 4);
11768         if (ret)
11769                 return ret;
11770
11771         /* i965+ uses the linear or tiled offsets from the
11772          * Display Registers (which do not change across a page-flip)
11773          * so we need only reprogram the base address.
11774          */
11775         intel_ring_emit(ring, MI_DISPLAY_FLIP |
11776                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11777         intel_ring_emit(ring, fb->pitches[0]);
11778         intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset |
11779                         intel_fb_modifier_to_tiling(fb->modifier));
11780
11781         /* XXX Enabling the panel-fitter across page-flip is so far
11782          * untested on non-native modes, so ignore it for now.
11783          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11784          */
11785         pf = 0;
11786         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11787         intel_ring_emit(ring, pf | pipesrc);
11788
11789         return 0;
11790 }
11791
11792 static int intel_gen6_queue_flip(struct drm_device *dev,
11793                                  struct drm_crtc *crtc,
11794                                  struct drm_framebuffer *fb,
11795                                  struct drm_i915_gem_object *obj,
11796                                  struct drm_i915_gem_request *req,
11797                                  uint32_t flags)
11798 {
11799         struct intel_ring *ring = req->ring;
11800         struct drm_i915_private *dev_priv = to_i915(dev);
11801         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11802         uint32_t pf, pipesrc;
11803         int ret;
11804
11805         ret = intel_ring_begin(req, 4);
11806         if (ret)
11807                 return ret;
11808
11809         intel_ring_emit(ring, MI_DISPLAY_FLIP |
11810                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11811         intel_ring_emit(ring, fb->pitches[0] |
11812                         intel_fb_modifier_to_tiling(fb->modifier));
11813         intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11814
11815         /* Contrary to the suggestions in the documentation,
11816          * "Enable Panel Fitter" does not seem to be required when page
11817          * flipping with a non-native mode, and worse causes a normal
11818          * modeset to fail.
11819          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11820          */
11821         pf = 0;
11822         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11823         intel_ring_emit(ring, pf | pipesrc);
11824
11825         return 0;
11826 }
11827
11828 static int intel_gen7_queue_flip(struct drm_device *dev,
11829                                  struct drm_crtc *crtc,
11830                                  struct drm_framebuffer *fb,
11831                                  struct drm_i915_gem_object *obj,
11832                                  struct drm_i915_gem_request *req,
11833                                  uint32_t flags)
11834 {
11835         struct drm_i915_private *dev_priv = to_i915(dev);
11836         struct intel_ring *ring = req->ring;
11837         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11838         uint32_t plane_bit = 0;
11839         int len, ret;
11840
11841         switch (intel_crtc->plane) {
11842         case PLANE_A:
11843                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11844                 break;
11845         case PLANE_B:
11846                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11847                 break;
11848         case PLANE_C:
11849                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11850                 break;
11851         default:
11852                 WARN_ONCE(1, "unknown plane in flip command\n");
11853                 return -ENODEV;
11854         }
11855
11856         len = 4;
11857         if (req->engine->id == RCS) {
11858                 len += 6;
11859                 /*
11860                  * On Gen 8, SRM is now taking an extra dword to accommodate
11861                  * 48bits addresses, and we need a NOOP for the batch size to
11862                  * stay even.
11863                  */
11864                 if (IS_GEN8(dev_priv))
11865                         len += 2;
11866         }
11867
11868         /*
11869          * BSpec MI_DISPLAY_FLIP for IVB:
11870          * "The full packet must be contained within the same cache line."
11871          *
11872          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11873          * cacheline, if we ever start emitting more commands before
11874          * the MI_DISPLAY_FLIP we may need to first emit everything else,
11875          * then do the cacheline alignment, and finally emit the
11876          * MI_DISPLAY_FLIP.
11877          */
11878         ret = intel_ring_cacheline_align(req);
11879         if (ret)
11880                 return ret;
11881
11882         ret = intel_ring_begin(req, len);
11883         if (ret)
11884                 return ret;
11885
11886         /* Unmask the flip-done completion message. Note that the bspec says that
11887          * we should do this for both the BCS and RCS, and that we must not unmask
11888          * more than one flip event at any time (or ensure that one flip message
11889          * can be sent by waiting for flip-done prior to queueing new flips).
11890          * Experimentation says that BCS works despite DERRMR masking all
11891          * flip-done completion events and that unmasking all planes at once
11892          * for the RCS also doesn't appear to drop events. Setting the DERRMR
11893          * to zero does lead to lockups within MI_DISPLAY_FLIP.
11894          */
11895         if (req->engine->id == RCS) {
11896                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11897                 intel_ring_emit_reg(ring, DERRMR);
11898                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11899                                           DERRMR_PIPEB_PRI_FLIP_DONE |
11900                                           DERRMR_PIPEC_PRI_FLIP_DONE));
11901                 if (IS_GEN8(dev_priv))
11902                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
11903                                               MI_SRM_LRM_GLOBAL_GTT);
11904                 else
11905                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
11906                                               MI_SRM_LRM_GLOBAL_GTT);
11907                 intel_ring_emit_reg(ring, DERRMR);
11908                 intel_ring_emit(ring,
11909                                 i915_ggtt_offset(req->engine->scratch) + 256);
11910                 if (IS_GEN8(dev_priv)) {
11911                         intel_ring_emit(ring, 0);
11912                         intel_ring_emit(ring, MI_NOOP);
11913                 }
11914         }
11915
11916         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11917         intel_ring_emit(ring, fb->pitches[0] |
11918                         intel_fb_modifier_to_tiling(fb->modifier));
11919         intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11920         intel_ring_emit(ring, (MI_NOOP));
11921
11922         return 0;
11923 }
11924
11925 static bool use_mmio_flip(struct intel_engine_cs *engine,
11926                           struct drm_i915_gem_object *obj)
11927 {
11928         /*
11929          * This is not being used for older platforms, because
11930          * non-availability of flip done interrupt forces us to use
11931          * CS flips. Older platforms derive flip done using some clever
11932          * tricks involving the flip_pending status bits and vblank irqs.
11933          * So using MMIO flips there would disrupt this mechanism.
11934          */
11935
11936         if (engine == NULL)
11937                 return true;
11938
11939         if (INTEL_GEN(engine->i915) < 5)
11940                 return false;
11941
11942         if (i915.use_mmio_flip < 0)
11943                 return false;
11944         else if (i915.use_mmio_flip > 0)
11945                 return true;
11946         else if (i915.enable_execlists)
11947                 return true;
11948
11949         return engine != i915_gem_object_last_write_engine(obj);
11950 }
11951
11952 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11953                              unsigned int rotation,
11954                              struct intel_flip_work *work)
11955 {
11956         struct drm_device *dev = intel_crtc->base.dev;
11957         struct drm_i915_private *dev_priv = to_i915(dev);
11958         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11959         const enum pipe pipe = intel_crtc->pipe;
11960         u32 ctl, stride = skl_plane_stride(fb, 0, rotation);
11961
11962         ctl = I915_READ(PLANE_CTL(pipe, 0));
11963         ctl &= ~PLANE_CTL_TILED_MASK;
11964         switch (fb->modifier) {
11965         case DRM_FORMAT_MOD_NONE:
11966                 break;
11967         case I915_FORMAT_MOD_X_TILED:
11968                 ctl |= PLANE_CTL_TILED_X;
11969                 break;
11970         case I915_FORMAT_MOD_Y_TILED:
11971                 ctl |= PLANE_CTL_TILED_Y;
11972                 break;
11973         case I915_FORMAT_MOD_Yf_TILED:
11974                 ctl |= PLANE_CTL_TILED_YF;
11975                 break;
11976         default:
11977                 MISSING_CASE(fb->modifier);
11978         }
11979
11980         /*
11981          * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11982          * PLANE_SURF updates, the update is then guaranteed to be atomic.
11983          */
11984         I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11985         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11986
11987         I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
11988         POSTING_READ(PLANE_SURF(pipe, 0));
11989 }
11990
11991 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
11992                              struct intel_flip_work *work)
11993 {
11994         struct drm_device *dev = intel_crtc->base.dev;
11995         struct drm_i915_private *dev_priv = to_i915(dev);
11996         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11997         i915_reg_t reg = DSPCNTR(intel_crtc->plane);
11998         u32 dspcntr;
11999
12000         dspcntr = I915_READ(reg);
12001
12002         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
12003                 dspcntr |= DISPPLANE_TILED;
12004         else
12005                 dspcntr &= ~DISPPLANE_TILED;
12006
12007         I915_WRITE(reg, dspcntr);
12008
12009         I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
12010         POSTING_READ(DSPSURF(intel_crtc->plane));
12011 }
12012
12013 static void intel_mmio_flip_work_func(struct work_struct *w)
12014 {
12015         struct intel_flip_work *work =
12016                 container_of(w, struct intel_flip_work, mmio_work);
12017         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
12018         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12019         struct intel_framebuffer *intel_fb =
12020                 to_intel_framebuffer(crtc->base.primary->fb);
12021         struct drm_i915_gem_object *obj = intel_fb->obj;
12022
12023         WARN_ON(i915_gem_object_wait(obj, 0, MAX_SCHEDULE_TIMEOUT, NULL) < 0);
12024
12025         intel_pipe_update_start(crtc);
12026
12027         if (INTEL_GEN(dev_priv) >= 9)
12028                 skl_do_mmio_flip(crtc, work->rotation, work);
12029         else
12030                 /* use_mmio_flip() retricts MMIO flips to ilk+ */
12031                 ilk_do_mmio_flip(crtc, work);
12032
12033         intel_pipe_update_end(crtc, work);
12034 }
12035
12036 static int intel_default_queue_flip(struct drm_device *dev,
12037                                     struct drm_crtc *crtc,
12038                                     struct drm_framebuffer *fb,
12039                                     struct drm_i915_gem_object *obj,
12040                                     struct drm_i915_gem_request *req,
12041                                     uint32_t flags)
12042 {
12043         return -ENODEV;
12044 }
12045
12046 static bool __pageflip_stall_check_cs(struct drm_i915_private *dev_priv,
12047                                       struct intel_crtc *intel_crtc,
12048                                       struct intel_flip_work *work)
12049 {
12050         u32 addr, vblank;
12051
12052         if (!atomic_read(&work->pending))
12053                 return false;
12054
12055         smp_rmb();
12056
12057         vblank = intel_crtc_get_vblank_counter(intel_crtc);
12058         if (work->flip_ready_vblank == 0) {
12059                 if (work->flip_queued_req &&
12060                     !i915_gem_request_completed(work->flip_queued_req))
12061                         return false;
12062
12063                 work->flip_ready_vblank = vblank;
12064         }
12065
12066         if (vblank - work->flip_ready_vblank < 3)
12067                 return false;
12068
12069         /* Potential stall - if we see that the flip has happened,
12070          * assume a missed interrupt. */
12071         if (INTEL_GEN(dev_priv) >= 4)
12072                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
12073         else
12074                 addr = I915_READ(DSPADDR(intel_crtc->plane));
12075
12076         /* There is a potential issue here with a false positive after a flip
12077          * to the same address. We could address this by checking for a
12078          * non-incrementing frame counter.
12079          */
12080         return addr == work->gtt_offset;
12081 }
12082
12083 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe)
12084 {
12085         struct drm_device *dev = &dev_priv->drm;
12086         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
12087         struct intel_flip_work *work;
12088
12089         WARN_ON(!in_interrupt());
12090
12091         if (crtc == NULL)
12092                 return;
12093
12094         spin_lock(&dev->event_lock);
12095         work = crtc->flip_work;
12096
12097         if (work != NULL && !is_mmio_work(work) &&
12098             __pageflip_stall_check_cs(dev_priv, crtc, work)) {
12099                 WARN_ONCE(1,
12100                           "Kicking stuck page flip: queued at %d, now %d\n",
12101                         work->flip_queued_vblank, intel_crtc_get_vblank_counter(crtc));
12102                 page_flip_completed(crtc);
12103                 work = NULL;
12104         }
12105
12106         if (work != NULL && !is_mmio_work(work) &&
12107             intel_crtc_get_vblank_counter(crtc) - work->flip_queued_vblank > 1)
12108                 intel_queue_rps_boost_for_request(work->flip_queued_req);
12109         spin_unlock(&dev->event_lock);
12110 }
12111
12112 static int intel_crtc_page_flip(struct drm_crtc *crtc,
12113                                 struct drm_framebuffer *fb,
12114                                 struct drm_pending_vblank_event *event,
12115                                 uint32_t page_flip_flags)
12116 {
12117         struct drm_device *dev = crtc->dev;
12118         struct drm_i915_private *dev_priv = to_i915(dev);
12119         struct drm_framebuffer *old_fb = crtc->primary->fb;
12120         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12121         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12122         struct drm_plane *primary = crtc->primary;
12123         enum pipe pipe = intel_crtc->pipe;
12124         struct intel_flip_work *work;
12125         struct intel_engine_cs *engine;
12126         bool mmio_flip;
12127         struct drm_i915_gem_request *request;
12128         struct i915_vma *vma;
12129         int ret;
12130
12131         /*
12132          * drm_mode_page_flip_ioctl() should already catch this, but double
12133          * check to be safe.  In the future we may enable pageflipping from
12134          * a disabled primary plane.
12135          */
12136         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
12137                 return -EBUSY;
12138
12139         /* Can't change pixel format via MI display flips. */
12140         if (fb->pixel_format != crtc->primary->fb->pixel_format)
12141                 return -EINVAL;
12142
12143         /*
12144          * TILEOFF/LINOFF registers can't be changed via MI display flips.
12145          * Note that pitch changes could also affect these register.
12146          */
12147         if (INTEL_GEN(dev_priv) > 3 &&
12148             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
12149              fb->pitches[0] != crtc->primary->fb->pitches[0]))
12150                 return -EINVAL;
12151
12152         if (i915_terminally_wedged(&dev_priv->gpu_error))
12153                 goto out_hang;
12154
12155         work = kzalloc(sizeof(*work), GFP_KERNEL);
12156         if (work == NULL)
12157                 return -ENOMEM;
12158
12159         work->event = event;
12160         work->crtc = crtc;
12161         work->old_fb = old_fb;
12162         INIT_WORK(&work->unpin_work, intel_unpin_work_fn);
12163
12164         ret = drm_crtc_vblank_get(crtc);
12165         if (ret)
12166                 goto free_work;
12167
12168         /* We borrow the event spin lock for protecting flip_work */
12169         spin_lock_irq(&dev->event_lock);
12170         if (intel_crtc->flip_work) {
12171                 /* Before declaring the flip queue wedged, check if
12172                  * the hardware completed the operation behind our backs.
12173                  */
12174                 if (pageflip_finished(intel_crtc, intel_crtc->flip_work)) {
12175                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
12176                         page_flip_completed(intel_crtc);
12177                 } else {
12178                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
12179                         spin_unlock_irq(&dev->event_lock);
12180
12181                         drm_crtc_vblank_put(crtc);
12182                         kfree(work);
12183                         return -EBUSY;
12184                 }
12185         }
12186         intel_crtc->flip_work = work;
12187         spin_unlock_irq(&dev->event_lock);
12188
12189         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
12190                 flush_workqueue(dev_priv->wq);
12191
12192         /* Reference the objects for the scheduled work. */
12193         drm_framebuffer_reference(work->old_fb);
12194
12195         crtc->primary->fb = fb;
12196         update_state_fb(crtc->primary);
12197
12198         work->pending_flip_obj = i915_gem_object_get(obj);
12199
12200         ret = i915_mutex_lock_interruptible(dev);
12201         if (ret)
12202                 goto cleanup;
12203
12204         intel_crtc->reset_count = i915_reset_count(&dev_priv->gpu_error);
12205         if (i915_reset_in_progress_or_wedged(&dev_priv->gpu_error)) {
12206                 ret = -EIO;
12207                 goto unlock;
12208         }
12209
12210         atomic_inc(&intel_crtc->unpin_work_count);
12211
12212         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
12213                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
12214
12215         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
12216                 engine = dev_priv->engine[BCS];
12217                 if (fb->modifier != old_fb->modifier)
12218                         /* vlv: DISPLAY_FLIP fails to change tiling */
12219                         engine = NULL;
12220         } else if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
12221                 engine = dev_priv->engine[BCS];
12222         } else if (INTEL_GEN(dev_priv) >= 7) {
12223                 engine = i915_gem_object_last_write_engine(obj);
12224                 if (engine == NULL || engine->id != RCS)
12225                         engine = dev_priv->engine[BCS];
12226         } else {
12227                 engine = dev_priv->engine[RCS];
12228         }
12229
12230         mmio_flip = use_mmio_flip(engine, obj);
12231
12232         vma = intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
12233         if (IS_ERR(vma)) {
12234                 ret = PTR_ERR(vma);
12235                 goto cleanup_pending;
12236         }
12237
12238         work->gtt_offset = intel_fb_gtt_offset(fb, primary->state->rotation);
12239         work->gtt_offset += intel_crtc->dspaddr_offset;
12240         work->rotation = crtc->primary->state->rotation;
12241
12242         /*
12243          * There's the potential that the next frame will not be compatible with
12244          * FBC, so we want to call pre_update() before the actual page flip.
12245          * The problem is that pre_update() caches some information about the fb
12246          * object, so we want to do this only after the object is pinned. Let's
12247          * be on the safe side and do this immediately before scheduling the
12248          * flip.
12249          */
12250         intel_fbc_pre_update(intel_crtc, intel_crtc->config,
12251                              to_intel_plane_state(primary->state));
12252
12253         if (mmio_flip) {
12254                 INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func);
12255                 queue_work(system_unbound_wq, &work->mmio_work);
12256         } else {
12257                 request = i915_gem_request_alloc(engine, engine->last_context);
12258                 if (IS_ERR(request)) {
12259                         ret = PTR_ERR(request);
12260                         goto cleanup_unpin;
12261                 }
12262
12263                 ret = i915_gem_request_await_object(request, obj, false);
12264                 if (ret)
12265                         goto cleanup_request;
12266
12267                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
12268                                                    page_flip_flags);
12269                 if (ret)
12270                         goto cleanup_request;
12271
12272                 intel_mark_page_flip_active(intel_crtc, work);
12273
12274                 work->flip_queued_req = i915_gem_request_get(request);
12275                 i915_add_request_no_flush(request);
12276         }
12277
12278         i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY);
12279         i915_gem_track_fb(intel_fb_obj(old_fb), obj,
12280                           to_intel_plane(primary)->frontbuffer_bit);
12281         mutex_unlock(&dev->struct_mutex);
12282
12283         intel_frontbuffer_flip_prepare(to_i915(dev),
12284                                        to_intel_plane(primary)->frontbuffer_bit);
12285
12286         trace_i915_flip_request(intel_crtc->plane, obj);
12287
12288         return 0;
12289
12290 cleanup_request:
12291         i915_add_request_no_flush(request);
12292 cleanup_unpin:
12293         intel_unpin_fb_obj(fb, crtc->primary->state->rotation);
12294 cleanup_pending:
12295         atomic_dec(&intel_crtc->unpin_work_count);
12296 unlock:
12297         mutex_unlock(&dev->struct_mutex);
12298 cleanup:
12299         crtc->primary->fb = old_fb;
12300         update_state_fb(crtc->primary);
12301
12302         i915_gem_object_put(obj);
12303         drm_framebuffer_unreference(work->old_fb);
12304
12305         spin_lock_irq(&dev->event_lock);
12306         intel_crtc->flip_work = NULL;
12307         spin_unlock_irq(&dev->event_lock);
12308
12309         drm_crtc_vblank_put(crtc);
12310 free_work:
12311         kfree(work);
12312
12313         if (ret == -EIO) {
12314                 struct drm_atomic_state *state;
12315                 struct drm_plane_state *plane_state;
12316
12317 out_hang:
12318                 state = drm_atomic_state_alloc(dev);
12319                 if (!state)
12320                         return -ENOMEM;
12321                 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
12322
12323 retry:
12324                 plane_state = drm_atomic_get_plane_state(state, primary);
12325                 ret = PTR_ERR_OR_ZERO(plane_state);
12326                 if (!ret) {
12327                         drm_atomic_set_fb_for_plane(plane_state, fb);
12328
12329                         ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
12330                         if (!ret)
12331                                 ret = drm_atomic_commit(state);
12332                 }
12333
12334                 if (ret == -EDEADLK) {
12335                         drm_modeset_backoff(state->acquire_ctx);
12336                         drm_atomic_state_clear(state);
12337                         goto retry;
12338                 }
12339
12340                 drm_atomic_state_put(state);
12341
12342                 if (ret == 0 && event) {
12343                         spin_lock_irq(&dev->event_lock);
12344                         drm_crtc_send_vblank_event(crtc, event);
12345                         spin_unlock_irq(&dev->event_lock);
12346                 }
12347         }
12348         return ret;
12349 }
12350
12351
12352 /**
12353  * intel_wm_need_update - Check whether watermarks need updating
12354  * @plane: drm plane
12355  * @state: new plane state
12356  *
12357  * Check current plane state versus the new one to determine whether
12358  * watermarks need to be recalculated.
12359  *
12360  * Returns true or false.
12361  */
12362 static bool intel_wm_need_update(struct drm_plane *plane,
12363                                  struct drm_plane_state *state)
12364 {
12365         struct intel_plane_state *new = to_intel_plane_state(state);
12366         struct intel_plane_state *cur = to_intel_plane_state(plane->state);
12367
12368         /* Update watermarks on tiling or size changes. */
12369         if (new->base.visible != cur->base.visible)
12370                 return true;
12371
12372         if (!cur->base.fb || !new->base.fb)
12373                 return false;
12374
12375         if (cur->base.fb->modifier != new->base.fb->modifier ||
12376             cur->base.rotation != new->base.rotation ||
12377             drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) ||
12378             drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) ||
12379             drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) ||
12380             drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst))
12381                 return true;
12382
12383         return false;
12384 }
12385
12386 static bool needs_scaling(struct intel_plane_state *state)
12387 {
12388         int src_w = drm_rect_width(&state->base.src) >> 16;
12389         int src_h = drm_rect_height(&state->base.src) >> 16;
12390         int dst_w = drm_rect_width(&state->base.dst);
12391         int dst_h = drm_rect_height(&state->base.dst);
12392
12393         return (src_w != dst_w || src_h != dst_h);
12394 }
12395
12396 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
12397                                     struct drm_plane_state *plane_state)
12398 {
12399         struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
12400         struct drm_crtc *crtc = crtc_state->crtc;
12401         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12402         struct drm_plane *plane = plane_state->plane;
12403         struct drm_device *dev = crtc->dev;
12404         struct drm_i915_private *dev_priv = to_i915(dev);
12405         struct intel_plane_state *old_plane_state =
12406                 to_intel_plane_state(plane->state);
12407         bool mode_changed = needs_modeset(crtc_state);
12408         bool was_crtc_enabled = crtc->state->active;
12409         bool is_crtc_enabled = crtc_state->active;
12410         bool turn_off, turn_on, visible, was_visible;
12411         struct drm_framebuffer *fb = plane_state->fb;
12412         int ret;
12413
12414         if (INTEL_GEN(dev_priv) >= 9 && plane->type != DRM_PLANE_TYPE_CURSOR) {
12415                 ret = skl_update_scaler_plane(
12416                         to_intel_crtc_state(crtc_state),
12417                         to_intel_plane_state(plane_state));
12418                 if (ret)
12419                         return ret;
12420         }
12421
12422         was_visible = old_plane_state->base.visible;
12423         visible = to_intel_plane_state(plane_state)->base.visible;
12424
12425         if (!was_crtc_enabled && WARN_ON(was_visible))
12426                 was_visible = false;
12427
12428         /*
12429          * Visibility is calculated as if the crtc was on, but
12430          * after scaler setup everything depends on it being off
12431          * when the crtc isn't active.
12432          *
12433          * FIXME this is wrong for watermarks. Watermarks should also
12434          * be computed as if the pipe would be active. Perhaps move
12435          * per-plane wm computation to the .check_plane() hook, and
12436          * only combine the results from all planes in the current place?
12437          */
12438         if (!is_crtc_enabled)
12439                 to_intel_plane_state(plane_state)->base.visible = visible = false;
12440
12441         if (!was_visible && !visible)
12442                 return 0;
12443
12444         if (fb != old_plane_state->base.fb)
12445                 pipe_config->fb_changed = true;
12446
12447         turn_off = was_visible && (!visible || mode_changed);
12448         turn_on = visible && (!was_visible || mode_changed);
12449
12450         DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
12451                          intel_crtc->base.base.id,
12452                          intel_crtc->base.name,
12453                          plane->base.id, plane->name,
12454                          fb ? fb->base.id : -1);
12455
12456         DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
12457                          plane->base.id, plane->name,
12458                          was_visible, visible,
12459                          turn_off, turn_on, mode_changed);
12460
12461         if (turn_on) {
12462                 pipe_config->update_wm_pre = true;
12463
12464                 /* must disable cxsr around plane enable/disable */
12465                 if (plane->type != DRM_PLANE_TYPE_CURSOR)
12466                         pipe_config->disable_cxsr = true;
12467         } else if (turn_off) {
12468                 pipe_config->update_wm_post = true;
12469
12470                 /* must disable cxsr around plane enable/disable */
12471                 if (plane->type != DRM_PLANE_TYPE_CURSOR)
12472                         pipe_config->disable_cxsr = true;
12473         } else if (intel_wm_need_update(plane, plane_state)) {
12474                 /* FIXME bollocks */
12475                 pipe_config->update_wm_pre = true;
12476                 pipe_config->update_wm_post = true;
12477         }
12478
12479         /* Pre-gen9 platforms need two-step watermark updates */
12480         if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) &&
12481             INTEL_GEN(dev_priv) < 9 && dev_priv->display.optimize_watermarks)
12482                 to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true;
12483
12484         if (visible || was_visible)
12485                 pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit;
12486
12487         /*
12488          * WaCxSRDisabledForSpriteScaling:ivb
12489          *
12490          * cstate->update_wm was already set above, so this flag will
12491          * take effect when we commit and program watermarks.
12492          */
12493         if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev_priv) &&
12494             needs_scaling(to_intel_plane_state(plane_state)) &&
12495             !needs_scaling(old_plane_state))
12496                 pipe_config->disable_lp_wm = true;
12497
12498         return 0;
12499 }
12500
12501 static bool encoders_cloneable(const struct intel_encoder *a,
12502                                const struct intel_encoder *b)
12503 {
12504         /* masks could be asymmetric, so check both ways */
12505         return a == b || (a->cloneable & (1 << b->type) &&
12506                           b->cloneable & (1 << a->type));
12507 }
12508
12509 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
12510                                          struct intel_crtc *crtc,
12511                                          struct intel_encoder *encoder)
12512 {
12513         struct intel_encoder *source_encoder;
12514         struct drm_connector *connector;
12515         struct drm_connector_state *connector_state;
12516         int i;
12517
12518         for_each_connector_in_state(state, connector, connector_state, i) {
12519                 if (connector_state->crtc != &crtc->base)
12520                         continue;
12521
12522                 source_encoder =
12523                         to_intel_encoder(connector_state->best_encoder);
12524                 if (!encoders_cloneable(encoder, source_encoder))
12525                         return false;
12526         }
12527
12528         return true;
12529 }
12530
12531 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
12532                                    struct drm_crtc_state *crtc_state)
12533 {
12534         struct drm_device *dev = crtc->dev;
12535         struct drm_i915_private *dev_priv = to_i915(dev);
12536         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12537         struct intel_crtc_state *pipe_config =
12538                 to_intel_crtc_state(crtc_state);
12539         struct drm_atomic_state *state = crtc_state->state;
12540         int ret;
12541         bool mode_changed = needs_modeset(crtc_state);
12542
12543         if (mode_changed && !crtc_state->active)
12544                 pipe_config->update_wm_post = true;
12545
12546         if (mode_changed && crtc_state->enable &&
12547             dev_priv->display.crtc_compute_clock &&
12548             !WARN_ON(pipe_config->shared_dpll)) {
12549                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
12550                                                            pipe_config);
12551                 if (ret)
12552                         return ret;
12553         }
12554
12555         if (crtc_state->color_mgmt_changed) {
12556                 ret = intel_color_check(crtc, crtc_state);
12557                 if (ret)
12558                         return ret;
12559
12560                 /*
12561                  * Changing color management on Intel hardware is
12562                  * handled as part of planes update.
12563                  */
12564                 crtc_state->planes_changed = true;
12565         }
12566
12567         ret = 0;
12568         if (dev_priv->display.compute_pipe_wm) {
12569                 ret = dev_priv->display.compute_pipe_wm(pipe_config);
12570                 if (ret) {
12571                         DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
12572                         return ret;
12573                 }
12574         }
12575
12576         if (dev_priv->display.compute_intermediate_wm &&
12577             !to_intel_atomic_state(state)->skip_intermediate_wm) {
12578                 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
12579                         return 0;
12580
12581                 /*
12582                  * Calculate 'intermediate' watermarks that satisfy both the
12583                  * old state and the new state.  We can program these
12584                  * immediately.
12585                  */
12586                 ret = dev_priv->display.compute_intermediate_wm(dev,
12587                                                                 intel_crtc,
12588                                                                 pipe_config);
12589                 if (ret) {
12590                         DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
12591                         return ret;
12592                 }
12593         } else if (dev_priv->display.compute_intermediate_wm) {
12594                 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
12595                         pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
12596         }
12597
12598         if (INTEL_GEN(dev_priv) >= 9) {
12599                 if (mode_changed)
12600                         ret = skl_update_scaler_crtc(pipe_config);
12601
12602                 if (!ret)
12603                         ret = intel_atomic_setup_scalers(dev, intel_crtc,
12604                                                          pipe_config);
12605         }
12606
12607         return ret;
12608 }
12609
12610 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
12611         .mode_set_base_atomic = intel_pipe_set_base_atomic,
12612         .atomic_begin = intel_begin_crtc_commit,
12613         .atomic_flush = intel_finish_crtc_commit,
12614         .atomic_check = intel_crtc_atomic_check,
12615 };
12616
12617 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
12618 {
12619         struct intel_connector *connector;
12620
12621         for_each_intel_connector(dev, connector) {
12622                 if (connector->base.state->crtc)
12623                         drm_connector_unreference(&connector->base);
12624
12625                 if (connector->base.encoder) {
12626                         connector->base.state->best_encoder =
12627                                 connector->base.encoder;
12628                         connector->base.state->crtc =
12629                                 connector->base.encoder->crtc;
12630
12631                         drm_connector_reference(&connector->base);
12632                 } else {
12633                         connector->base.state->best_encoder = NULL;
12634                         connector->base.state->crtc = NULL;
12635                 }
12636         }
12637 }
12638
12639 static void
12640 connected_sink_compute_bpp(struct intel_connector *connector,
12641                            struct intel_crtc_state *pipe_config)
12642 {
12643         const struct drm_display_info *info = &connector->base.display_info;
12644         int bpp = pipe_config->pipe_bpp;
12645
12646         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
12647                       connector->base.base.id,
12648                       connector->base.name);
12649
12650         /* Don't use an invalid EDID bpc value */
12651         if (info->bpc != 0 && info->bpc * 3 < bpp) {
12652                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
12653                               bpp, info->bpc * 3);
12654                 pipe_config->pipe_bpp = info->bpc * 3;
12655         }
12656
12657         /* Clamp bpp to 8 on screens without EDID 1.4 */
12658         if (info->bpc == 0 && bpp > 24) {
12659                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
12660                               bpp);
12661                 pipe_config->pipe_bpp = 24;
12662         }
12663 }
12664
12665 static int
12666 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12667                           struct intel_crtc_state *pipe_config)
12668 {
12669         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12670         struct drm_atomic_state *state;
12671         struct drm_connector *connector;
12672         struct drm_connector_state *connector_state;
12673         int bpp, i;
12674
12675         if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
12676             IS_CHERRYVIEW(dev_priv)))
12677                 bpp = 10*3;
12678         else if (INTEL_GEN(dev_priv) >= 5)
12679                 bpp = 12*3;
12680         else
12681                 bpp = 8*3;
12682
12683
12684         pipe_config->pipe_bpp = bpp;
12685
12686         state = pipe_config->base.state;
12687
12688         /* Clamp display bpp to EDID value */
12689         for_each_connector_in_state(state, connector, connector_state, i) {
12690                 if (connector_state->crtc != &crtc->base)
12691                         continue;
12692
12693                 connected_sink_compute_bpp(to_intel_connector(connector),
12694                                            pipe_config);
12695         }
12696
12697         return bpp;
12698 }
12699
12700 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12701 {
12702         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12703                         "type: 0x%x flags: 0x%x\n",
12704                 mode->crtc_clock,
12705                 mode->crtc_hdisplay, mode->crtc_hsync_start,
12706                 mode->crtc_hsync_end, mode->crtc_htotal,
12707                 mode->crtc_vdisplay, mode->crtc_vsync_start,
12708                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
12709 }
12710
12711 static inline void
12712 intel_dump_m_n_config(struct intel_crtc_state *pipe_config, char *id,
12713                       unsigned int lane_count, struct intel_link_m_n *m_n)
12714 {
12715         DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12716                       id, lane_count,
12717                       m_n->gmch_m, m_n->gmch_n,
12718                       m_n->link_m, m_n->link_n, m_n->tu);
12719 }
12720
12721 static void intel_dump_pipe_config(struct intel_crtc *crtc,
12722                                    struct intel_crtc_state *pipe_config,
12723                                    const char *context)
12724 {
12725         struct drm_device *dev = crtc->base.dev;
12726         struct drm_i915_private *dev_priv = to_i915(dev);
12727         struct drm_plane *plane;
12728         struct intel_plane *intel_plane;
12729         struct intel_plane_state *state;
12730         struct drm_framebuffer *fb;
12731
12732         DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n",
12733                       crtc->base.base.id, crtc->base.name, context);
12734
12735         DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
12736                       transcoder_name(pipe_config->cpu_transcoder),
12737                       pipe_config->pipe_bpp, pipe_config->dither);
12738
12739         if (pipe_config->has_pch_encoder)
12740                 intel_dump_m_n_config(pipe_config, "fdi",
12741                                       pipe_config->fdi_lanes,
12742                                       &pipe_config->fdi_m_n);
12743
12744         if (intel_crtc_has_dp_encoder(pipe_config)) {
12745                 intel_dump_m_n_config(pipe_config, "dp m_n",
12746                                 pipe_config->lane_count, &pipe_config->dp_m_n);
12747                 if (pipe_config->has_drrs)
12748                         intel_dump_m_n_config(pipe_config, "dp m2_n2",
12749                                               pipe_config->lane_count,
12750                                               &pipe_config->dp_m2_n2);
12751         }
12752
12753         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12754                       pipe_config->has_audio, pipe_config->has_infoframe);
12755
12756         DRM_DEBUG_KMS("requested mode:\n");
12757         drm_mode_debug_printmodeline(&pipe_config->base.mode);
12758         DRM_DEBUG_KMS("adjusted mode:\n");
12759         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12760         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12761         DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d\n",
12762                       pipe_config->port_clock,
12763                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12764
12765         if (INTEL_GEN(dev_priv) >= 9)
12766                 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12767                               crtc->num_scalers,
12768                               pipe_config->scaler_state.scaler_users,
12769                               pipe_config->scaler_state.scaler_id);
12770
12771         if (HAS_GMCH_DISPLAY(dev_priv))
12772                 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12773                               pipe_config->gmch_pfit.control,
12774                               pipe_config->gmch_pfit.pgm_ratios,
12775                               pipe_config->gmch_pfit.lvds_border_bits);
12776         else
12777                 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12778                               pipe_config->pch_pfit.pos,
12779                               pipe_config->pch_pfit.size,
12780                               enableddisabled(pipe_config->pch_pfit.enabled));
12781
12782         DRM_DEBUG_KMS("ips: %i, double wide: %i\n",
12783                       pipe_config->ips_enabled, pipe_config->double_wide);
12784
12785         if (IS_BROXTON(dev_priv)) {
12786                 DRM_DEBUG_KMS("dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12787                               "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12788                               "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12789                               pipe_config->dpll_hw_state.ebb0,
12790                               pipe_config->dpll_hw_state.ebb4,
12791                               pipe_config->dpll_hw_state.pll0,
12792                               pipe_config->dpll_hw_state.pll1,
12793                               pipe_config->dpll_hw_state.pll2,
12794                               pipe_config->dpll_hw_state.pll3,
12795                               pipe_config->dpll_hw_state.pll6,
12796                               pipe_config->dpll_hw_state.pll8,
12797                               pipe_config->dpll_hw_state.pll9,
12798                               pipe_config->dpll_hw_state.pll10,
12799                               pipe_config->dpll_hw_state.pcsdw12);
12800         } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
12801                 DRM_DEBUG_KMS("dpll_hw_state: "
12802                               "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12803                               pipe_config->dpll_hw_state.ctrl1,
12804                               pipe_config->dpll_hw_state.cfgcr1,
12805                               pipe_config->dpll_hw_state.cfgcr2);
12806         } else if (HAS_DDI(dev_priv)) {
12807                 DRM_DEBUG_KMS("dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
12808                               pipe_config->dpll_hw_state.wrpll,
12809                               pipe_config->dpll_hw_state.spll);
12810         } else {
12811                 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12812                               "fp0: 0x%x, fp1: 0x%x\n",
12813                               pipe_config->dpll_hw_state.dpll,
12814                               pipe_config->dpll_hw_state.dpll_md,
12815                               pipe_config->dpll_hw_state.fp0,
12816                               pipe_config->dpll_hw_state.fp1);
12817         }
12818
12819         DRM_DEBUG_KMS("planes on this crtc\n");
12820         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12821                 struct drm_format_name_buf format_name;
12822                 intel_plane = to_intel_plane(plane);
12823                 if (intel_plane->pipe != crtc->pipe)
12824                         continue;
12825
12826                 state = to_intel_plane_state(plane->state);
12827                 fb = state->base.fb;
12828                 if (!fb) {
12829                         DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
12830                                       plane->base.id, plane->name, state->scaler_id);
12831                         continue;
12832                 }
12833
12834                 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d, fb = %ux%u format = %s\n",
12835                               plane->base.id, plane->name,
12836                               fb->base.id, fb->width, fb->height,
12837                               drm_get_format_name(fb->pixel_format, &format_name));
12838                 if (INTEL_GEN(dev_priv) >= 9)
12839                         DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
12840                                       state->scaler_id,
12841                                       state->base.src.x1 >> 16,
12842                                       state->base.src.y1 >> 16,
12843                                       drm_rect_width(&state->base.src) >> 16,
12844                                       drm_rect_height(&state->base.src) >> 16,
12845                                       state->base.dst.x1, state->base.dst.y1,
12846                                       drm_rect_width(&state->base.dst),
12847                                       drm_rect_height(&state->base.dst));
12848         }
12849 }
12850
12851 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12852 {
12853         struct drm_device *dev = state->dev;
12854         struct drm_connector *connector;
12855         unsigned int used_ports = 0;
12856         unsigned int used_mst_ports = 0;
12857
12858         /*
12859          * Walk the connector list instead of the encoder
12860          * list to detect the problem on ddi platforms
12861          * where there's just one encoder per digital port.
12862          */
12863         drm_for_each_connector(connector, dev) {
12864                 struct drm_connector_state *connector_state;
12865                 struct intel_encoder *encoder;
12866
12867                 connector_state = drm_atomic_get_existing_connector_state(state, connector);
12868                 if (!connector_state)
12869                         connector_state = connector->state;
12870
12871                 if (!connector_state->best_encoder)
12872                         continue;
12873
12874                 encoder = to_intel_encoder(connector_state->best_encoder);
12875
12876                 WARN_ON(!connector_state->crtc);
12877
12878                 switch (encoder->type) {
12879                         unsigned int port_mask;
12880                 case INTEL_OUTPUT_UNKNOWN:
12881                         if (WARN_ON(!HAS_DDI(to_i915(dev))))
12882                                 break;
12883                 case INTEL_OUTPUT_DP:
12884                 case INTEL_OUTPUT_HDMI:
12885                 case INTEL_OUTPUT_EDP:
12886                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12887
12888                         /* the same port mustn't appear more than once */
12889                         if (used_ports & port_mask)
12890                                 return false;
12891
12892                         used_ports |= port_mask;
12893                         break;
12894                 case INTEL_OUTPUT_DP_MST:
12895                         used_mst_ports |=
12896                                 1 << enc_to_mst(&encoder->base)->primary->port;
12897                         break;
12898                 default:
12899                         break;
12900                 }
12901         }
12902
12903         /* can't mix MST and SST/HDMI on the same port */
12904         if (used_ports & used_mst_ports)
12905                 return false;
12906
12907         return true;
12908 }
12909
12910 static void
12911 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12912 {
12913         struct drm_crtc_state tmp_state;
12914         struct intel_crtc_scaler_state scaler_state;
12915         struct intel_dpll_hw_state dpll_hw_state;
12916         struct intel_shared_dpll *shared_dpll;
12917         bool force_thru;
12918
12919         /* FIXME: before the switch to atomic started, a new pipe_config was
12920          * kzalloc'd. Code that depends on any field being zero should be
12921          * fixed, so that the crtc_state can be safely duplicated. For now,
12922          * only fields that are know to not cause problems are preserved. */
12923
12924         tmp_state = crtc_state->base;
12925         scaler_state = crtc_state->scaler_state;
12926         shared_dpll = crtc_state->shared_dpll;
12927         dpll_hw_state = crtc_state->dpll_hw_state;
12928         force_thru = crtc_state->pch_pfit.force_thru;
12929
12930         memset(crtc_state, 0, sizeof *crtc_state);
12931
12932         crtc_state->base = tmp_state;
12933         crtc_state->scaler_state = scaler_state;
12934         crtc_state->shared_dpll = shared_dpll;
12935         crtc_state->dpll_hw_state = dpll_hw_state;
12936         crtc_state->pch_pfit.force_thru = force_thru;
12937 }
12938
12939 static int
12940 intel_modeset_pipe_config(struct drm_crtc *crtc,
12941                           struct intel_crtc_state *pipe_config)
12942 {
12943         struct drm_atomic_state *state = pipe_config->base.state;
12944         struct intel_encoder *encoder;
12945         struct drm_connector *connector;
12946         struct drm_connector_state *connector_state;
12947         int base_bpp, ret = -EINVAL;
12948         int i;
12949         bool retry = true;
12950
12951         clear_intel_crtc_state(pipe_config);
12952
12953         pipe_config->cpu_transcoder =
12954                 (enum transcoder) to_intel_crtc(crtc)->pipe;
12955
12956         /*
12957          * Sanitize sync polarity flags based on requested ones. If neither
12958          * positive or negative polarity is requested, treat this as meaning
12959          * negative polarity.
12960          */
12961         if (!(pipe_config->base.adjusted_mode.flags &
12962               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12963                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12964
12965         if (!(pipe_config->base.adjusted_mode.flags &
12966               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12967                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12968
12969         base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12970                                              pipe_config);
12971         if (base_bpp < 0)
12972                 goto fail;
12973
12974         /*
12975          * Determine the real pipe dimensions. Note that stereo modes can
12976          * increase the actual pipe size due to the frame doubling and
12977          * insertion of additional space for blanks between the frame. This
12978          * is stored in the crtc timings. We use the requested mode to do this
12979          * computation to clearly distinguish it from the adjusted mode, which
12980          * can be changed by the connectors in the below retry loop.
12981          */
12982         drm_crtc_get_hv_timing(&pipe_config->base.mode,
12983                                &pipe_config->pipe_src_w,
12984                                &pipe_config->pipe_src_h);
12985
12986         for_each_connector_in_state(state, connector, connector_state, i) {
12987                 if (connector_state->crtc != crtc)
12988                         continue;
12989
12990                 encoder = to_intel_encoder(connector_state->best_encoder);
12991
12992                 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
12993                         DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
12994                         goto fail;
12995                 }
12996
12997                 /*
12998                  * Determine output_types before calling the .compute_config()
12999                  * hooks so that the hooks can use this information safely.
13000                  */
13001                 pipe_config->output_types |= 1 << encoder->type;
13002         }
13003
13004 encoder_retry:
13005         /* Ensure the port clock defaults are reset when retrying. */
13006         pipe_config->port_clock = 0;
13007         pipe_config->pixel_multiplier = 1;
13008
13009         /* Fill in default crtc timings, allow encoders to overwrite them. */
13010         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
13011                               CRTC_STEREO_DOUBLE);
13012
13013         /* Pass our mode to the connectors and the CRTC to give them a chance to
13014          * adjust it according to limitations or connector properties, and also
13015          * a chance to reject the mode entirely.
13016          */
13017         for_each_connector_in_state(state, connector, connector_state, i) {
13018                 if (connector_state->crtc != crtc)
13019                         continue;
13020
13021                 encoder = to_intel_encoder(connector_state->best_encoder);
13022
13023                 if (!(encoder->compute_config(encoder, pipe_config, connector_state))) {
13024                         DRM_DEBUG_KMS("Encoder config failure\n");
13025                         goto fail;
13026                 }
13027         }
13028
13029         /* Set default port clock if not overwritten by the encoder. Needs to be
13030          * done afterwards in case the encoder adjusts the mode. */
13031         if (!pipe_config->port_clock)
13032                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
13033                         * pipe_config->pixel_multiplier;
13034
13035         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
13036         if (ret < 0) {
13037                 DRM_DEBUG_KMS("CRTC fixup failed\n");
13038                 goto fail;
13039         }
13040
13041         if (ret == RETRY) {
13042                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
13043                         ret = -EINVAL;
13044                         goto fail;
13045                 }
13046
13047                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
13048                 retry = false;
13049                 goto encoder_retry;
13050         }
13051
13052         /* Dithering seems to not pass-through bits correctly when it should, so
13053          * only enable it on 6bpc panels. */
13054         pipe_config->dither = pipe_config->pipe_bpp == 6*3;
13055         DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
13056                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
13057
13058 fail:
13059         return ret;
13060 }
13061
13062 static void
13063 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
13064 {
13065         struct drm_crtc *crtc;
13066         struct drm_crtc_state *crtc_state;
13067         int i;
13068
13069         /* Double check state. */
13070         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13071                 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
13072
13073                 /* Update hwmode for vblank functions */
13074                 if (crtc->state->active)
13075                         crtc->hwmode = crtc->state->adjusted_mode;
13076                 else
13077                         crtc->hwmode.crtc_clock = 0;
13078
13079                 /*
13080                  * Update legacy state to satisfy fbc code. This can
13081                  * be removed when fbc uses the atomic state.
13082                  */
13083                 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
13084                         struct drm_plane_state *plane_state = crtc->primary->state;
13085
13086                         crtc->primary->fb = plane_state->fb;
13087                         crtc->x = plane_state->src_x >> 16;
13088                         crtc->y = plane_state->src_y >> 16;
13089                 }
13090         }
13091 }
13092
13093 static bool intel_fuzzy_clock_check(int clock1, int clock2)
13094 {
13095         int diff;
13096
13097         if (clock1 == clock2)
13098                 return true;
13099
13100         if (!clock1 || !clock2)
13101                 return false;
13102
13103         diff = abs(clock1 - clock2);
13104
13105         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
13106                 return true;
13107
13108         return false;
13109 }
13110
13111 static bool
13112 intel_compare_m_n(unsigned int m, unsigned int n,
13113                   unsigned int m2, unsigned int n2,
13114                   bool exact)
13115 {
13116         if (m == m2 && n == n2)
13117                 return true;
13118
13119         if (exact || !m || !n || !m2 || !n2)
13120                 return false;
13121
13122         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
13123
13124         if (n > n2) {
13125                 while (n > n2) {
13126                         m2 <<= 1;
13127                         n2 <<= 1;
13128                 }
13129         } else if (n < n2) {
13130                 while (n < n2) {
13131                         m <<= 1;
13132                         n <<= 1;
13133                 }
13134         }
13135
13136         if (n != n2)
13137                 return false;
13138
13139         return intel_fuzzy_clock_check(m, m2);
13140 }
13141
13142 static bool
13143 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
13144                        struct intel_link_m_n *m2_n2,
13145                        bool adjust)
13146 {
13147         if (m_n->tu == m2_n2->tu &&
13148             intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
13149                               m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
13150             intel_compare_m_n(m_n->link_m, m_n->link_n,
13151                               m2_n2->link_m, m2_n2->link_n, !adjust)) {
13152                 if (adjust)
13153                         *m2_n2 = *m_n;
13154
13155                 return true;
13156         }
13157
13158         return false;
13159 }
13160
13161 static bool
13162 intel_pipe_config_compare(struct drm_i915_private *dev_priv,
13163                           struct intel_crtc_state *current_config,
13164                           struct intel_crtc_state *pipe_config,
13165                           bool adjust)
13166 {
13167         bool ret = true;
13168
13169 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
13170         do { \
13171                 if (!adjust) \
13172                         DRM_ERROR(fmt, ##__VA_ARGS__); \
13173                 else \
13174                         DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
13175         } while (0)
13176
13177 #define PIPE_CONF_CHECK_X(name) \
13178         if (current_config->name != pipe_config->name) { \
13179                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13180                           "(expected 0x%08x, found 0x%08x)\n", \
13181                           current_config->name, \
13182                           pipe_config->name); \
13183                 ret = false; \
13184         }
13185
13186 #define PIPE_CONF_CHECK_I(name) \
13187         if (current_config->name != pipe_config->name) { \
13188                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13189                           "(expected %i, found %i)\n", \
13190                           current_config->name, \
13191                           pipe_config->name); \
13192                 ret = false; \
13193         }
13194
13195 #define PIPE_CONF_CHECK_P(name) \
13196         if (current_config->name != pipe_config->name) { \
13197                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13198                           "(expected %p, found %p)\n", \
13199                           current_config->name, \
13200                           pipe_config->name); \
13201                 ret = false; \
13202         }
13203
13204 #define PIPE_CONF_CHECK_M_N(name) \
13205         if (!intel_compare_link_m_n(&current_config->name, \
13206                                     &pipe_config->name,\
13207                                     adjust)) { \
13208                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13209                           "(expected tu %i gmch %i/%i link %i/%i, " \
13210                           "found tu %i, gmch %i/%i link %i/%i)\n", \
13211                           current_config->name.tu, \
13212                           current_config->name.gmch_m, \
13213                           current_config->name.gmch_n, \
13214                           current_config->name.link_m, \
13215                           current_config->name.link_n, \
13216                           pipe_config->name.tu, \
13217                           pipe_config->name.gmch_m, \
13218                           pipe_config->name.gmch_n, \
13219                           pipe_config->name.link_m, \
13220                           pipe_config->name.link_n); \
13221                 ret = false; \
13222         }
13223
13224 /* This is required for BDW+ where there is only one set of registers for
13225  * switching between high and low RR.
13226  * This macro can be used whenever a comparison has to be made between one
13227  * hw state and multiple sw state variables.
13228  */
13229 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
13230         if (!intel_compare_link_m_n(&current_config->name, \
13231                                     &pipe_config->name, adjust) && \
13232             !intel_compare_link_m_n(&current_config->alt_name, \
13233                                     &pipe_config->name, adjust)) { \
13234                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13235                           "(expected tu %i gmch %i/%i link %i/%i, " \
13236                           "or tu %i gmch %i/%i link %i/%i, " \
13237                           "found tu %i, gmch %i/%i link %i/%i)\n", \
13238                           current_config->name.tu, \
13239                           current_config->name.gmch_m, \
13240                           current_config->name.gmch_n, \
13241                           current_config->name.link_m, \
13242                           current_config->name.link_n, \
13243                           current_config->alt_name.tu, \
13244                           current_config->alt_name.gmch_m, \
13245                           current_config->alt_name.gmch_n, \
13246                           current_config->alt_name.link_m, \
13247                           current_config->alt_name.link_n, \
13248                           pipe_config->name.tu, \
13249                           pipe_config->name.gmch_m, \
13250                           pipe_config->name.gmch_n, \
13251                           pipe_config->name.link_m, \
13252                           pipe_config->name.link_n); \
13253                 ret = false; \
13254         }
13255
13256 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
13257         if ((current_config->name ^ pipe_config->name) & (mask)) { \
13258                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
13259                           "(expected %i, found %i)\n", \
13260                           current_config->name & (mask), \
13261                           pipe_config->name & (mask)); \
13262                 ret = false; \
13263         }
13264
13265 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
13266         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
13267                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13268                           "(expected %i, found %i)\n", \
13269                           current_config->name, \
13270                           pipe_config->name); \
13271                 ret = false; \
13272         }
13273
13274 #define PIPE_CONF_QUIRK(quirk)  \
13275         ((current_config->quirks | pipe_config->quirks) & (quirk))
13276
13277         PIPE_CONF_CHECK_I(cpu_transcoder);
13278
13279         PIPE_CONF_CHECK_I(has_pch_encoder);
13280         PIPE_CONF_CHECK_I(fdi_lanes);
13281         PIPE_CONF_CHECK_M_N(fdi_m_n);
13282
13283         PIPE_CONF_CHECK_I(lane_count);
13284         PIPE_CONF_CHECK_X(lane_lat_optim_mask);
13285
13286         if (INTEL_GEN(dev_priv) < 8) {
13287                 PIPE_CONF_CHECK_M_N(dp_m_n);
13288
13289                 if (current_config->has_drrs)
13290                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
13291         } else
13292                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
13293
13294         PIPE_CONF_CHECK_X(output_types);
13295
13296         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
13297         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
13298         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
13299         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
13300         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
13301         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
13302
13303         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
13304         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
13305         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
13306         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
13307         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
13308         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
13309
13310         PIPE_CONF_CHECK_I(pixel_multiplier);
13311         PIPE_CONF_CHECK_I(has_hdmi_sink);
13312         if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
13313             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13314                 PIPE_CONF_CHECK_I(limited_color_range);
13315         PIPE_CONF_CHECK_I(has_infoframe);
13316
13317         PIPE_CONF_CHECK_I(has_audio);
13318
13319         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13320                               DRM_MODE_FLAG_INTERLACE);
13321
13322         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
13323                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13324                                       DRM_MODE_FLAG_PHSYNC);
13325                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13326                                       DRM_MODE_FLAG_NHSYNC);
13327                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13328                                       DRM_MODE_FLAG_PVSYNC);
13329                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13330                                       DRM_MODE_FLAG_NVSYNC);
13331         }
13332
13333         PIPE_CONF_CHECK_X(gmch_pfit.control);
13334         /* pfit ratios are autocomputed by the hw on gen4+ */
13335         if (INTEL_GEN(dev_priv) < 4)
13336                 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
13337         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
13338
13339         if (!adjust) {
13340                 PIPE_CONF_CHECK_I(pipe_src_w);
13341                 PIPE_CONF_CHECK_I(pipe_src_h);
13342
13343                 PIPE_CONF_CHECK_I(pch_pfit.enabled);
13344                 if (current_config->pch_pfit.enabled) {
13345                         PIPE_CONF_CHECK_X(pch_pfit.pos);
13346                         PIPE_CONF_CHECK_X(pch_pfit.size);
13347                 }
13348
13349                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
13350         }
13351
13352         /* BDW+ don't expose a synchronous way to read the state */
13353         if (IS_HASWELL(dev_priv))
13354                 PIPE_CONF_CHECK_I(ips_enabled);
13355
13356         PIPE_CONF_CHECK_I(double_wide);
13357
13358         PIPE_CONF_CHECK_P(shared_dpll);
13359         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
13360         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
13361         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
13362         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
13363         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
13364         PIPE_CONF_CHECK_X(dpll_hw_state.spll);
13365         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
13366         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
13367         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
13368
13369         PIPE_CONF_CHECK_X(dsi_pll.ctrl);
13370         PIPE_CONF_CHECK_X(dsi_pll.div);
13371
13372         if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
13373                 PIPE_CONF_CHECK_I(pipe_bpp);
13374
13375         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
13376         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
13377
13378 #undef PIPE_CONF_CHECK_X
13379 #undef PIPE_CONF_CHECK_I
13380 #undef PIPE_CONF_CHECK_P
13381 #undef PIPE_CONF_CHECK_FLAGS
13382 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
13383 #undef PIPE_CONF_QUIRK
13384 #undef INTEL_ERR_OR_DBG_KMS
13385
13386         return ret;
13387 }
13388
13389 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
13390                                            const struct intel_crtc_state *pipe_config)
13391 {
13392         if (pipe_config->has_pch_encoder) {
13393                 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
13394                                                             &pipe_config->fdi_m_n);
13395                 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
13396
13397                 /*
13398                  * FDI already provided one idea for the dotclock.
13399                  * Yell if the encoder disagrees.
13400                  */
13401                 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
13402                      "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
13403                      fdi_dotclock, dotclock);
13404         }
13405 }
13406
13407 static void verify_wm_state(struct drm_crtc *crtc,
13408                             struct drm_crtc_state *new_state)
13409 {
13410         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
13411         struct skl_ddb_allocation hw_ddb, *sw_ddb;
13412         struct skl_pipe_wm hw_wm, *sw_wm;
13413         struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
13414         struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
13415         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13416         const enum pipe pipe = intel_crtc->pipe;
13417         int plane, level, max_level = ilk_wm_max_level(dev_priv);
13418
13419         if (INTEL_GEN(dev_priv) < 9 || !new_state->active)
13420                 return;
13421
13422         skl_pipe_wm_get_hw_state(crtc, &hw_wm);
13423         sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal;
13424
13425         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
13426         sw_ddb = &dev_priv->wm.skl_hw.ddb;
13427
13428         /* planes */
13429         for_each_universal_plane(dev_priv, pipe, plane) {
13430                 hw_plane_wm = &hw_wm.planes[plane];
13431                 sw_plane_wm = &sw_wm->planes[plane];
13432
13433                 /* Watermarks */
13434                 for (level = 0; level <= max_level; level++) {
13435                         if (skl_wm_level_equals(&hw_plane_wm->wm[level],
13436                                                 &sw_plane_wm->wm[level]))
13437                                 continue;
13438
13439                         DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
13440                                   pipe_name(pipe), plane + 1, level,
13441                                   sw_plane_wm->wm[level].plane_en,
13442                                   sw_plane_wm->wm[level].plane_res_b,
13443                                   sw_plane_wm->wm[level].plane_res_l,
13444                                   hw_plane_wm->wm[level].plane_en,
13445                                   hw_plane_wm->wm[level].plane_res_b,
13446                                   hw_plane_wm->wm[level].plane_res_l);
13447                 }
13448
13449                 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
13450                                          &sw_plane_wm->trans_wm)) {
13451                         DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
13452                                   pipe_name(pipe), plane + 1,
13453                                   sw_plane_wm->trans_wm.plane_en,
13454                                   sw_plane_wm->trans_wm.plane_res_b,
13455                                   sw_plane_wm->trans_wm.plane_res_l,
13456                                   hw_plane_wm->trans_wm.plane_en,
13457                                   hw_plane_wm->trans_wm.plane_res_b,
13458                                   hw_plane_wm->trans_wm.plane_res_l);
13459                 }
13460
13461                 /* DDB */
13462                 hw_ddb_entry = &hw_ddb.plane[pipe][plane];
13463                 sw_ddb_entry = &sw_ddb->plane[pipe][plane];
13464
13465                 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
13466                         DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
13467                                   pipe_name(pipe), plane + 1,
13468                                   sw_ddb_entry->start, sw_ddb_entry->end,
13469                                   hw_ddb_entry->start, hw_ddb_entry->end);
13470                 }
13471         }
13472
13473         /*
13474          * cursor
13475          * If the cursor plane isn't active, we may not have updated it's ddb
13476          * allocation. In that case since the ddb allocation will be updated
13477          * once the plane becomes visible, we can skip this check
13478          */
13479         if (intel_crtc->cursor_addr) {
13480                 hw_plane_wm = &hw_wm.planes[PLANE_CURSOR];
13481                 sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
13482
13483                 /* Watermarks */
13484                 for (level = 0; level <= max_level; level++) {
13485                         if (skl_wm_level_equals(&hw_plane_wm->wm[level],
13486                                                 &sw_plane_wm->wm[level]))
13487                                 continue;
13488
13489                         DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
13490                                   pipe_name(pipe), level,
13491                                   sw_plane_wm->wm[level].plane_en,
13492                                   sw_plane_wm->wm[level].plane_res_b,
13493                                   sw_plane_wm->wm[level].plane_res_l,
13494                                   hw_plane_wm->wm[level].plane_en,
13495                                   hw_plane_wm->wm[level].plane_res_b,
13496                                   hw_plane_wm->wm[level].plane_res_l);
13497                 }
13498
13499                 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
13500                                          &sw_plane_wm->trans_wm)) {
13501                         DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
13502                                   pipe_name(pipe),
13503                                   sw_plane_wm->trans_wm.plane_en,
13504                                   sw_plane_wm->trans_wm.plane_res_b,
13505                                   sw_plane_wm->trans_wm.plane_res_l,
13506                                   hw_plane_wm->trans_wm.plane_en,
13507                                   hw_plane_wm->trans_wm.plane_res_b,
13508                                   hw_plane_wm->trans_wm.plane_res_l);
13509                 }
13510
13511                 /* DDB */
13512                 hw_ddb_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
13513                 sw_ddb_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
13514
13515                 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
13516                         DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
13517                                   pipe_name(pipe),
13518                                   sw_ddb_entry->start, sw_ddb_entry->end,
13519                                   hw_ddb_entry->start, hw_ddb_entry->end);
13520                 }
13521         }
13522 }
13523
13524 static void
13525 verify_connector_state(struct drm_device *dev,
13526                        struct drm_atomic_state *state,
13527                        struct drm_crtc *crtc)
13528 {
13529         struct drm_connector *connector;
13530         struct drm_connector_state *old_conn_state;
13531         int i;
13532
13533         for_each_connector_in_state(state, connector, old_conn_state, i) {
13534                 struct drm_encoder *encoder = connector->encoder;
13535                 struct drm_connector_state *state = connector->state;
13536
13537                 if (state->crtc != crtc)
13538                         continue;
13539
13540                 intel_connector_verify_state(to_intel_connector(connector));
13541
13542                 I915_STATE_WARN(state->best_encoder != encoder,
13543                      "connector's atomic encoder doesn't match legacy encoder\n");
13544         }
13545 }
13546
13547 static void
13548 verify_encoder_state(struct drm_device *dev)
13549 {
13550         struct intel_encoder *encoder;
13551         struct intel_connector *connector;
13552
13553         for_each_intel_encoder(dev, encoder) {
13554                 bool enabled = false;
13555                 enum pipe pipe;
13556
13557                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
13558                               encoder->base.base.id,
13559                               encoder->base.name);
13560
13561                 for_each_intel_connector(dev, connector) {
13562                         if (connector->base.state->best_encoder != &encoder->base)
13563                                 continue;
13564                         enabled = true;
13565
13566                         I915_STATE_WARN(connector->base.state->crtc !=
13567                                         encoder->base.crtc,
13568                              "connector's crtc doesn't match encoder crtc\n");
13569                 }
13570
13571                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
13572                      "encoder's enabled state mismatch "
13573                      "(expected %i, found %i)\n",
13574                      !!encoder->base.crtc, enabled);
13575
13576                 if (!encoder->base.crtc) {
13577                         bool active;
13578
13579                         active = encoder->get_hw_state(encoder, &pipe);
13580                         I915_STATE_WARN(active,
13581                              "encoder detached but still enabled on pipe %c.\n",
13582                              pipe_name(pipe));
13583                 }
13584         }
13585 }
13586
13587 static void
13588 verify_crtc_state(struct drm_crtc *crtc,
13589                   struct drm_crtc_state *old_crtc_state,
13590                   struct drm_crtc_state *new_crtc_state)
13591 {
13592         struct drm_device *dev = crtc->dev;
13593         struct drm_i915_private *dev_priv = to_i915(dev);
13594         struct intel_encoder *encoder;
13595         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13596         struct intel_crtc_state *pipe_config, *sw_config;
13597         struct drm_atomic_state *old_state;
13598         bool active;
13599
13600         old_state = old_crtc_state->state;
13601         __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
13602         pipe_config = to_intel_crtc_state(old_crtc_state);
13603         memset(pipe_config, 0, sizeof(*pipe_config));
13604         pipe_config->base.crtc = crtc;
13605         pipe_config->base.state = old_state;
13606
13607         DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
13608
13609         active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
13610
13611         /* hw state is inconsistent with the pipe quirk */
13612         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
13613             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
13614                 active = new_crtc_state->active;
13615
13616         I915_STATE_WARN(new_crtc_state->active != active,
13617              "crtc active state doesn't match with hw state "
13618              "(expected %i, found %i)\n", new_crtc_state->active, active);
13619
13620         I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
13621              "transitional active state does not match atomic hw state "
13622              "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
13623
13624         for_each_encoder_on_crtc(dev, crtc, encoder) {
13625                 enum pipe pipe;
13626
13627                 active = encoder->get_hw_state(encoder, &pipe);
13628                 I915_STATE_WARN(active != new_crtc_state->active,
13629                         "[ENCODER:%i] active %i with crtc active %i\n",
13630                         encoder->base.base.id, active, new_crtc_state->active);
13631
13632                 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
13633                                 "Encoder connected to wrong pipe %c\n",
13634                                 pipe_name(pipe));
13635
13636                 if (active) {
13637                         pipe_config->output_types |= 1 << encoder->type;
13638                         encoder->get_config(encoder, pipe_config);
13639                 }
13640         }
13641
13642         if (!new_crtc_state->active)
13643                 return;
13644
13645         intel_pipe_config_sanity_check(dev_priv, pipe_config);
13646
13647         sw_config = to_intel_crtc_state(crtc->state);
13648         if (!intel_pipe_config_compare(dev_priv, sw_config,
13649                                        pipe_config, false)) {
13650                 I915_STATE_WARN(1, "pipe state doesn't match!\n");
13651                 intel_dump_pipe_config(intel_crtc, pipe_config,
13652                                        "[hw state]");
13653                 intel_dump_pipe_config(intel_crtc, sw_config,
13654                                        "[sw state]");
13655         }
13656 }
13657
13658 static void
13659 verify_single_dpll_state(struct drm_i915_private *dev_priv,
13660                          struct intel_shared_dpll *pll,
13661                          struct drm_crtc *crtc,
13662                          struct drm_crtc_state *new_state)
13663 {
13664         struct intel_dpll_hw_state dpll_hw_state;
13665         unsigned crtc_mask;
13666         bool active;
13667
13668         memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
13669
13670         DRM_DEBUG_KMS("%s\n", pll->name);
13671
13672         active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
13673
13674         if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
13675                 I915_STATE_WARN(!pll->on && pll->active_mask,
13676                      "pll in active use but not on in sw tracking\n");
13677                 I915_STATE_WARN(pll->on && !pll->active_mask,
13678                      "pll is on but not used by any active crtc\n");
13679                 I915_STATE_WARN(pll->on != active,
13680                      "pll on state mismatch (expected %i, found %i)\n",
13681                      pll->on, active);
13682         }
13683
13684         if (!crtc) {
13685                 I915_STATE_WARN(pll->active_mask & ~pll->config.crtc_mask,
13686                                 "more active pll users than references: %x vs %x\n",
13687                                 pll->active_mask, pll->config.crtc_mask);
13688
13689                 return;
13690         }
13691
13692         crtc_mask = 1 << drm_crtc_index(crtc);
13693
13694         if (new_state->active)
13695                 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
13696                                 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
13697                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
13698         else
13699                 I915_STATE_WARN(pll->active_mask & crtc_mask,
13700                                 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
13701                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
13702
13703         I915_STATE_WARN(!(pll->config.crtc_mask & crtc_mask),
13704                         "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
13705                         crtc_mask, pll->config.crtc_mask);
13706
13707         I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state,
13708                                           &dpll_hw_state,
13709                                           sizeof(dpll_hw_state)),
13710                         "pll hw state mismatch\n");
13711 }
13712
13713 static void
13714 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
13715                          struct drm_crtc_state *old_crtc_state,
13716                          struct drm_crtc_state *new_crtc_state)
13717 {
13718         struct drm_i915_private *dev_priv = to_i915(dev);
13719         struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
13720         struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
13721
13722         if (new_state->shared_dpll)
13723                 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
13724
13725         if (old_state->shared_dpll &&
13726             old_state->shared_dpll != new_state->shared_dpll) {
13727                 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
13728                 struct intel_shared_dpll *pll = old_state->shared_dpll;
13729
13730                 I915_STATE_WARN(pll->active_mask & crtc_mask,
13731                                 "pll active mismatch (didn't expect pipe %c in active mask)\n",
13732                                 pipe_name(drm_crtc_index(crtc)));
13733                 I915_STATE_WARN(pll->config.crtc_mask & crtc_mask,
13734                                 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
13735                                 pipe_name(drm_crtc_index(crtc)));
13736         }
13737 }
13738
13739 static void
13740 intel_modeset_verify_crtc(struct drm_crtc *crtc,
13741                           struct drm_atomic_state *state,
13742                           struct drm_crtc_state *old_state,
13743                           struct drm_crtc_state *new_state)
13744 {
13745         if (!needs_modeset(new_state) &&
13746             !to_intel_crtc_state(new_state)->update_pipe)
13747                 return;
13748
13749         verify_wm_state(crtc, new_state);
13750         verify_connector_state(crtc->dev, state, crtc);
13751         verify_crtc_state(crtc, old_state, new_state);
13752         verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
13753 }
13754
13755 static void
13756 verify_disabled_dpll_state(struct drm_device *dev)
13757 {
13758         struct drm_i915_private *dev_priv = to_i915(dev);
13759         int i;
13760
13761         for (i = 0; i < dev_priv->num_shared_dpll; i++)
13762                 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
13763 }
13764
13765 static void
13766 intel_modeset_verify_disabled(struct drm_device *dev,
13767                               struct drm_atomic_state *state)
13768 {
13769         verify_encoder_state(dev);
13770         verify_connector_state(dev, state, NULL);
13771         verify_disabled_dpll_state(dev);
13772 }
13773
13774 static void update_scanline_offset(struct intel_crtc *crtc)
13775 {
13776         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13777
13778         /*
13779          * The scanline counter increments at the leading edge of hsync.
13780          *
13781          * On most platforms it starts counting from vtotal-1 on the
13782          * first active line. That means the scanline counter value is
13783          * always one less than what we would expect. Ie. just after
13784          * start of vblank, which also occurs at start of hsync (on the
13785          * last active line), the scanline counter will read vblank_start-1.
13786          *
13787          * On gen2 the scanline counter starts counting from 1 instead
13788          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13789          * to keep the value positive), instead of adding one.
13790          *
13791          * On HSW+ the behaviour of the scanline counter depends on the output
13792          * type. For DP ports it behaves like most other platforms, but on HDMI
13793          * there's an extra 1 line difference. So we need to add two instead of
13794          * one to the value.
13795          */
13796         if (IS_GEN2(dev_priv)) {
13797                 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
13798                 int vtotal;
13799
13800                 vtotal = adjusted_mode->crtc_vtotal;
13801                 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
13802                         vtotal /= 2;
13803
13804                 crtc->scanline_offset = vtotal - 1;
13805         } else if (HAS_DDI(dev_priv) &&
13806                    intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
13807                 crtc->scanline_offset = 2;
13808         } else
13809                 crtc->scanline_offset = 1;
13810 }
13811
13812 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
13813 {
13814         struct drm_device *dev = state->dev;
13815         struct drm_i915_private *dev_priv = to_i915(dev);
13816         struct intel_shared_dpll_config *shared_dpll = NULL;
13817         struct drm_crtc *crtc;
13818         struct drm_crtc_state *crtc_state;
13819         int i;
13820
13821         if (!dev_priv->display.crtc_compute_clock)
13822                 return;
13823
13824         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13825                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13826                 struct intel_shared_dpll *old_dpll =
13827                         to_intel_crtc_state(crtc->state)->shared_dpll;
13828
13829                 if (!needs_modeset(crtc_state))
13830                         continue;
13831
13832                 to_intel_crtc_state(crtc_state)->shared_dpll = NULL;
13833
13834                 if (!old_dpll)
13835                         continue;
13836
13837                 if (!shared_dpll)
13838                         shared_dpll = intel_atomic_get_shared_dpll_state(state);
13839
13840                 intel_shared_dpll_config_put(shared_dpll, old_dpll, intel_crtc);
13841         }
13842 }
13843
13844 /*
13845  * This implements the workaround described in the "notes" section of the mode
13846  * set sequence documentation. When going from no pipes or single pipe to
13847  * multiple pipes, and planes are enabled after the pipe, we need to wait at
13848  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13849  */
13850 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13851 {
13852         struct drm_crtc_state *crtc_state;
13853         struct intel_crtc *intel_crtc;
13854         struct drm_crtc *crtc;
13855         struct intel_crtc_state *first_crtc_state = NULL;
13856         struct intel_crtc_state *other_crtc_state = NULL;
13857         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13858         int i;
13859
13860         /* look at all crtc's that are going to be enabled in during modeset */
13861         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13862                 intel_crtc = to_intel_crtc(crtc);
13863
13864                 if (!crtc_state->active || !needs_modeset(crtc_state))
13865                         continue;
13866
13867                 if (first_crtc_state) {
13868                         other_crtc_state = to_intel_crtc_state(crtc_state);
13869                         break;
13870                 } else {
13871                         first_crtc_state = to_intel_crtc_state(crtc_state);
13872                         first_pipe = intel_crtc->pipe;
13873                 }
13874         }
13875
13876         /* No workaround needed? */
13877         if (!first_crtc_state)
13878                 return 0;
13879
13880         /* w/a possibly needed, check how many crtc's are already enabled. */
13881         for_each_intel_crtc(state->dev, intel_crtc) {
13882                 struct intel_crtc_state *pipe_config;
13883
13884                 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13885                 if (IS_ERR(pipe_config))
13886                         return PTR_ERR(pipe_config);
13887
13888                 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13889
13890                 if (!pipe_config->base.active ||
13891                     needs_modeset(&pipe_config->base))
13892                         continue;
13893
13894                 /* 2 or more enabled crtcs means no need for w/a */
13895                 if (enabled_pipe != INVALID_PIPE)
13896                         return 0;
13897
13898                 enabled_pipe = intel_crtc->pipe;
13899         }
13900
13901         if (enabled_pipe != INVALID_PIPE)
13902                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13903         else if (other_crtc_state)
13904                 other_crtc_state->hsw_workaround_pipe = first_pipe;
13905
13906         return 0;
13907 }
13908
13909 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13910 {
13911         struct drm_crtc *crtc;
13912         struct drm_crtc_state *crtc_state;
13913         int ret = 0;
13914
13915         /* add all active pipes to the state */
13916         for_each_crtc(state->dev, crtc) {
13917                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13918                 if (IS_ERR(crtc_state))
13919                         return PTR_ERR(crtc_state);
13920
13921                 if (!crtc_state->active || needs_modeset(crtc_state))
13922                         continue;
13923
13924                 crtc_state->mode_changed = true;
13925
13926                 ret = drm_atomic_add_affected_connectors(state, crtc);
13927                 if (ret)
13928                         break;
13929
13930                 ret = drm_atomic_add_affected_planes(state, crtc);
13931                 if (ret)
13932                         break;
13933         }
13934
13935         return ret;
13936 }
13937
13938 static int intel_modeset_checks(struct drm_atomic_state *state)
13939 {
13940         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13941         struct drm_i915_private *dev_priv = to_i915(state->dev);
13942         struct drm_crtc *crtc;
13943         struct drm_crtc_state *crtc_state;
13944         int ret = 0, i;
13945
13946         if (!check_digital_port_conflicts(state)) {
13947                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13948                 return -EINVAL;
13949         }
13950
13951         intel_state->modeset = true;
13952         intel_state->active_crtcs = dev_priv->active_crtcs;
13953
13954         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13955                 if (crtc_state->active)
13956                         intel_state->active_crtcs |= 1 << i;
13957                 else
13958                         intel_state->active_crtcs &= ~(1 << i);
13959
13960                 if (crtc_state->active != crtc->state->active)
13961                         intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
13962         }
13963
13964         /*
13965          * See if the config requires any additional preparation, e.g.
13966          * to adjust global state with pipes off.  We need to do this
13967          * here so we can get the modeset_pipe updated config for the new
13968          * mode set on this crtc.  For other crtcs we need to use the
13969          * adjusted_mode bits in the crtc directly.
13970          */
13971         if (dev_priv->display.modeset_calc_cdclk) {
13972                 if (!intel_state->cdclk_pll_vco)
13973                         intel_state->cdclk_pll_vco = dev_priv->cdclk_pll.vco;
13974                 if (!intel_state->cdclk_pll_vco)
13975                         intel_state->cdclk_pll_vco = dev_priv->skl_preferred_vco_freq;
13976
13977                 ret = dev_priv->display.modeset_calc_cdclk(state);
13978                 if (ret < 0)
13979                         return ret;
13980
13981                 if (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
13982                     intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco)
13983                         ret = intel_modeset_all_pipes(state);
13984
13985                 if (ret < 0)
13986                         return ret;
13987
13988                 DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n",
13989                               intel_state->cdclk, intel_state->dev_cdclk);
13990         } else {
13991                 to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq;
13992         }
13993
13994         intel_modeset_clear_plls(state);
13995
13996         if (IS_HASWELL(dev_priv))
13997                 return haswell_mode_set_planes_workaround(state);
13998
13999         return 0;
14000 }
14001
14002 /*
14003  * Handle calculation of various watermark data at the end of the atomic check
14004  * phase.  The code here should be run after the per-crtc and per-plane 'check'
14005  * handlers to ensure that all derived state has been updated.
14006  */
14007 static int calc_watermark_data(struct drm_atomic_state *state)
14008 {
14009         struct drm_device *dev = state->dev;
14010         struct drm_i915_private *dev_priv = to_i915(dev);
14011
14012         /* Is there platform-specific watermark information to calculate? */
14013         if (dev_priv->display.compute_global_watermarks)
14014                 return dev_priv->display.compute_global_watermarks(state);
14015
14016         return 0;
14017 }
14018
14019 /**
14020  * intel_atomic_check - validate state object
14021  * @dev: drm device
14022  * @state: state to validate
14023  */
14024 static int intel_atomic_check(struct drm_device *dev,
14025                               struct drm_atomic_state *state)
14026 {
14027         struct drm_i915_private *dev_priv = to_i915(dev);
14028         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14029         struct drm_crtc *crtc;
14030         struct drm_crtc_state *crtc_state;
14031         int ret, i;
14032         bool any_ms = false;
14033
14034         ret = drm_atomic_helper_check_modeset(dev, state);
14035         if (ret)
14036                 return ret;
14037
14038         for_each_crtc_in_state(state, crtc, crtc_state, i) {
14039                 struct intel_crtc_state *pipe_config =
14040                         to_intel_crtc_state(crtc_state);
14041
14042                 /* Catch I915_MODE_FLAG_INHERITED */
14043                 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
14044                         crtc_state->mode_changed = true;
14045
14046                 if (!needs_modeset(crtc_state))
14047                         continue;
14048
14049                 if (!crtc_state->enable) {
14050                         any_ms = true;
14051                         continue;
14052                 }
14053
14054                 /* FIXME: For only active_changed we shouldn't need to do any
14055                  * state recomputation at all. */
14056
14057                 ret = drm_atomic_add_affected_connectors(state, crtc);
14058                 if (ret)
14059                         return ret;
14060
14061                 ret = intel_modeset_pipe_config(crtc, pipe_config);
14062                 if (ret) {
14063                         intel_dump_pipe_config(to_intel_crtc(crtc),
14064                                                pipe_config, "[failed]");
14065                         return ret;
14066                 }
14067
14068                 if (i915.fastboot &&
14069                     intel_pipe_config_compare(dev_priv,
14070                                         to_intel_crtc_state(crtc->state),
14071                                         pipe_config, true)) {
14072                         crtc_state->mode_changed = false;
14073                         to_intel_crtc_state(crtc_state)->update_pipe = true;
14074                 }
14075
14076                 if (needs_modeset(crtc_state))
14077                         any_ms = true;
14078
14079                 ret = drm_atomic_add_affected_planes(state, crtc);
14080                 if (ret)
14081                         return ret;
14082
14083                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
14084                                        needs_modeset(crtc_state) ?
14085                                        "[modeset]" : "[fastset]");
14086         }
14087
14088         if (any_ms) {
14089                 ret = intel_modeset_checks(state);
14090
14091                 if (ret)
14092                         return ret;
14093         } else {
14094                 intel_state->cdclk = dev_priv->atomic_cdclk_freq;
14095         }
14096
14097         ret = drm_atomic_helper_check_planes(dev, state);
14098         if (ret)
14099                 return ret;
14100
14101         intel_fbc_choose_crtc(dev_priv, state);
14102         return calc_watermark_data(state);
14103 }
14104
14105 static int intel_atomic_prepare_commit(struct drm_device *dev,
14106                                        struct drm_atomic_state *state)
14107 {
14108         struct drm_i915_private *dev_priv = to_i915(dev);
14109         struct drm_crtc_state *crtc_state;
14110         struct drm_crtc *crtc;
14111         int i, ret;
14112
14113         for_each_crtc_in_state(state, crtc, crtc_state, i) {
14114                 if (state->legacy_cursor_update)
14115                         continue;
14116
14117                 ret = intel_crtc_wait_for_pending_flips(crtc);
14118                 if (ret)
14119                         return ret;
14120
14121                 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
14122                         flush_workqueue(dev_priv->wq);
14123         }
14124
14125         ret = mutex_lock_interruptible(&dev->struct_mutex);
14126         if (ret)
14127                 return ret;
14128
14129         ret = drm_atomic_helper_prepare_planes(dev, state);
14130         mutex_unlock(&dev->struct_mutex);
14131
14132         return ret;
14133 }
14134
14135 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
14136 {
14137         struct drm_device *dev = crtc->base.dev;
14138
14139         if (!dev->max_vblank_count)
14140                 return drm_accurate_vblank_count(&crtc->base);
14141
14142         return dev->driver->get_vblank_counter(dev, crtc->pipe);
14143 }
14144
14145 static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
14146                                           struct drm_i915_private *dev_priv,
14147                                           unsigned crtc_mask)
14148 {
14149         unsigned last_vblank_count[I915_MAX_PIPES];
14150         enum pipe pipe;
14151         int ret;
14152
14153         if (!crtc_mask)
14154                 return;
14155
14156         for_each_pipe(dev_priv, pipe) {
14157                 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
14158                                                                   pipe);
14159
14160                 if (!((1 << pipe) & crtc_mask))
14161                         continue;
14162
14163                 ret = drm_crtc_vblank_get(&crtc->base);
14164                 if (WARN_ON(ret != 0)) {
14165                         crtc_mask &= ~(1 << pipe);
14166                         continue;
14167                 }
14168
14169                 last_vblank_count[pipe] = drm_crtc_vblank_count(&crtc->base);
14170         }
14171
14172         for_each_pipe(dev_priv, pipe) {
14173                 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
14174                                                                   pipe);
14175                 long lret;
14176
14177                 if (!((1 << pipe) & crtc_mask))
14178                         continue;
14179
14180                 lret = wait_event_timeout(dev->vblank[pipe].queue,
14181                                 last_vblank_count[pipe] !=
14182                                         drm_crtc_vblank_count(&crtc->base),
14183                                 msecs_to_jiffies(50));
14184
14185                 WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe));
14186
14187                 drm_crtc_vblank_put(&crtc->base);
14188         }
14189 }
14190
14191 static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
14192 {
14193         /* fb updated, need to unpin old fb */
14194         if (crtc_state->fb_changed)
14195                 return true;
14196
14197         /* wm changes, need vblank before final wm's */
14198         if (crtc_state->update_wm_post)
14199                 return true;
14200
14201         /*
14202          * cxsr is re-enabled after vblank.
14203          * This is already handled by crtc_state->update_wm_post,
14204          * but added for clarity.
14205          */
14206         if (crtc_state->disable_cxsr)
14207                 return true;
14208
14209         return false;
14210 }
14211
14212 static void intel_update_crtc(struct drm_crtc *crtc,
14213                               struct drm_atomic_state *state,
14214                               struct drm_crtc_state *old_crtc_state,
14215                               unsigned int *crtc_vblank_mask)
14216 {
14217         struct drm_device *dev = crtc->dev;
14218         struct drm_i915_private *dev_priv = to_i915(dev);
14219         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14220         struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc->state);
14221         bool modeset = needs_modeset(crtc->state);
14222
14223         if (modeset) {
14224                 update_scanline_offset(intel_crtc);
14225                 dev_priv->display.crtc_enable(pipe_config, state);
14226         } else {
14227                 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
14228         }
14229
14230         if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
14231                 intel_fbc_enable(
14232                     intel_crtc, pipe_config,
14233                     to_intel_plane_state(crtc->primary->state));
14234         }
14235
14236         drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
14237
14238         if (needs_vblank_wait(pipe_config))
14239                 *crtc_vblank_mask |= drm_crtc_mask(crtc);
14240 }
14241
14242 static void intel_update_crtcs(struct drm_atomic_state *state,
14243                                unsigned int *crtc_vblank_mask)
14244 {
14245         struct drm_crtc *crtc;
14246         struct drm_crtc_state *old_crtc_state;
14247         int i;
14248
14249         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14250                 if (!crtc->state->active)
14251                         continue;
14252
14253                 intel_update_crtc(crtc, state, old_crtc_state,
14254                                   crtc_vblank_mask);
14255         }
14256 }
14257
14258 static void skl_update_crtcs(struct drm_atomic_state *state,
14259                              unsigned int *crtc_vblank_mask)
14260 {
14261         struct drm_i915_private *dev_priv = to_i915(state->dev);
14262         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14263         struct drm_crtc *crtc;
14264         struct intel_crtc *intel_crtc;
14265         struct drm_crtc_state *old_crtc_state;
14266         struct intel_crtc_state *cstate;
14267         unsigned int updated = 0;
14268         bool progress;
14269         enum pipe pipe;
14270         int i;
14271
14272         const struct skl_ddb_entry *entries[I915_MAX_PIPES] = {};
14273
14274         for_each_crtc_in_state(state, crtc, old_crtc_state, i)
14275                 /* ignore allocations for crtc's that have been turned off. */
14276                 if (crtc->state->active)
14277                         entries[i] = &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb;
14278
14279         /*
14280          * Whenever the number of active pipes changes, we need to make sure we
14281          * update the pipes in the right order so that their ddb allocations
14282          * never overlap with eachother inbetween CRTC updates. Otherwise we'll
14283          * cause pipe underruns and other bad stuff.
14284          */
14285         do {
14286                 progress = false;
14287
14288                 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14289                         bool vbl_wait = false;
14290                         unsigned int cmask = drm_crtc_mask(crtc);
14291
14292                         intel_crtc = to_intel_crtc(crtc);
14293                         cstate = to_intel_crtc_state(crtc->state);
14294                         pipe = intel_crtc->pipe;
14295
14296                         if (updated & cmask || !cstate->base.active)
14297                                 continue;
14298
14299                         if (skl_ddb_allocation_overlaps(entries, &cstate->wm.skl.ddb, i))
14300                                 continue;
14301
14302                         updated |= cmask;
14303                         entries[i] = &cstate->wm.skl.ddb;
14304
14305                         /*
14306                          * If this is an already active pipe, it's DDB changed,
14307                          * and this isn't the last pipe that needs updating
14308                          * then we need to wait for a vblank to pass for the
14309                          * new ddb allocation to take effect.
14310                          */
14311                         if (!skl_ddb_entry_equal(&cstate->wm.skl.ddb,
14312                                                  &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb) &&
14313                             !crtc->state->active_changed &&
14314                             intel_state->wm_results.dirty_pipes != updated)
14315                                 vbl_wait = true;
14316
14317                         intel_update_crtc(crtc, state, old_crtc_state,
14318                                           crtc_vblank_mask);
14319
14320                         if (vbl_wait)
14321                                 intel_wait_for_vblank(dev_priv, pipe);
14322
14323                         progress = true;
14324                 }
14325         } while (progress);
14326 }
14327
14328 static void intel_atomic_commit_tail(struct drm_atomic_state *state)
14329 {
14330         struct drm_device *dev = state->dev;
14331         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14332         struct drm_i915_private *dev_priv = to_i915(dev);
14333         struct drm_crtc_state *old_crtc_state;
14334         struct drm_crtc *crtc;
14335         struct intel_crtc_state *intel_cstate;
14336         bool hw_check = intel_state->modeset;
14337         unsigned long put_domains[I915_MAX_PIPES] = {};
14338         unsigned crtc_vblank_mask = 0;
14339         int i;
14340
14341         drm_atomic_helper_wait_for_dependencies(state);
14342
14343         if (intel_state->modeset)
14344                 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
14345
14346         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14347                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14348
14349                 if (needs_modeset(crtc->state) ||
14350                     to_intel_crtc_state(crtc->state)->update_pipe) {
14351                         hw_check = true;
14352
14353                         put_domains[to_intel_crtc(crtc)->pipe] =
14354                                 modeset_get_crtc_power_domains(crtc,
14355                                         to_intel_crtc_state(crtc->state));
14356                 }
14357
14358                 if (!needs_modeset(crtc->state))
14359                         continue;
14360
14361                 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
14362
14363                 if (old_crtc_state->active) {
14364                         intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
14365                         dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state);
14366                         intel_crtc->active = false;
14367                         intel_fbc_disable(intel_crtc);
14368                         intel_disable_shared_dpll(intel_crtc);
14369
14370                         /*
14371                          * Underruns don't always raise
14372                          * interrupts, so check manually.
14373                          */
14374                         intel_check_cpu_fifo_underruns(dev_priv);
14375                         intel_check_pch_fifo_underruns(dev_priv);
14376
14377                         if (!crtc->state->active) {
14378                                 /*
14379                                  * Make sure we don't call initial_watermarks
14380                                  * for ILK-style watermark updates.
14381                                  */
14382                                 if (dev_priv->display.atomic_update_watermarks)
14383                                         dev_priv->display.initial_watermarks(intel_state,
14384                                                                              to_intel_crtc_state(crtc->state));
14385                                 else
14386                                         intel_update_watermarks(intel_crtc);
14387                         }
14388                 }
14389         }
14390
14391         /* Only after disabling all output pipelines that will be changed can we
14392          * update the the output configuration. */
14393         intel_modeset_update_crtc_state(state);
14394
14395         if (intel_state->modeset) {
14396                 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
14397
14398                 if (dev_priv->display.modeset_commit_cdclk &&
14399                     (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
14400                      intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco))
14401                         dev_priv->display.modeset_commit_cdclk(state);
14402
14403                 /*
14404                  * SKL workaround: bspec recommends we disable the SAGV when we
14405                  * have more then one pipe enabled
14406                  */
14407                 if (!intel_can_enable_sagv(state))
14408                         intel_disable_sagv(dev_priv);
14409
14410                 intel_modeset_verify_disabled(dev, state);
14411         }
14412
14413         /* Complete the events for pipes that have now been disabled */
14414         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14415                 bool modeset = needs_modeset(crtc->state);
14416
14417                 /* Complete events for now disable pipes here. */
14418                 if (modeset && !crtc->state->active && crtc->state->event) {
14419                         spin_lock_irq(&dev->event_lock);
14420                         drm_crtc_send_vblank_event(crtc, crtc->state->event);
14421                         spin_unlock_irq(&dev->event_lock);
14422
14423                         crtc->state->event = NULL;
14424                 }
14425         }
14426
14427         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
14428         dev_priv->display.update_crtcs(state, &crtc_vblank_mask);
14429
14430         /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
14431          * already, but still need the state for the delayed optimization. To
14432          * fix this:
14433          * - wrap the optimization/post_plane_update stuff into a per-crtc work.
14434          * - schedule that vblank worker _before_ calling hw_done
14435          * - at the start of commit_tail, cancel it _synchrously
14436          * - switch over to the vblank wait helper in the core after that since
14437          *   we don't need out special handling any more.
14438          */
14439         if (!state->legacy_cursor_update)
14440                 intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
14441
14442         /*
14443          * Now that the vblank has passed, we can go ahead and program the
14444          * optimal watermarks on platforms that need two-step watermark
14445          * programming.
14446          *
14447          * TODO: Move this (and other cleanup) to an async worker eventually.
14448          */
14449         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14450                 intel_cstate = to_intel_crtc_state(crtc->state);
14451
14452                 if (dev_priv->display.optimize_watermarks)
14453                         dev_priv->display.optimize_watermarks(intel_state,
14454                                                               intel_cstate);
14455         }
14456
14457         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14458                 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
14459
14460                 if (put_domains[i])
14461                         modeset_put_power_domains(dev_priv, put_domains[i]);
14462
14463                 intel_modeset_verify_crtc(crtc, state, old_crtc_state, crtc->state);
14464         }
14465
14466         if (intel_state->modeset && intel_can_enable_sagv(state))
14467                 intel_enable_sagv(dev_priv);
14468
14469         drm_atomic_helper_commit_hw_done(state);
14470
14471         if (intel_state->modeset)
14472                 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
14473
14474         mutex_lock(&dev->struct_mutex);
14475         drm_atomic_helper_cleanup_planes(dev, state);
14476         mutex_unlock(&dev->struct_mutex);
14477
14478         drm_atomic_helper_commit_cleanup_done(state);
14479
14480         drm_atomic_state_put(state);
14481
14482         /* As one of the primary mmio accessors, KMS has a high likelihood
14483          * of triggering bugs in unclaimed access. After we finish
14484          * modesetting, see if an error has been flagged, and if so
14485          * enable debugging for the next modeset - and hope we catch
14486          * the culprit.
14487          *
14488          * XXX note that we assume display power is on at this point.
14489          * This might hold true now but we need to add pm helper to check
14490          * unclaimed only when the hardware is on, as atomic commits
14491          * can happen also when the device is completely off.
14492          */
14493         intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
14494 }
14495
14496 static void intel_atomic_commit_work(struct work_struct *work)
14497 {
14498         struct drm_atomic_state *state =
14499                 container_of(work, struct drm_atomic_state, commit_work);
14500
14501         intel_atomic_commit_tail(state);
14502 }
14503
14504 static int __i915_sw_fence_call
14505 intel_atomic_commit_ready(struct i915_sw_fence *fence,
14506                           enum i915_sw_fence_notify notify)
14507 {
14508         struct intel_atomic_state *state =
14509                 container_of(fence, struct intel_atomic_state, commit_ready);
14510
14511         switch (notify) {
14512         case FENCE_COMPLETE:
14513                 if (state->base.commit_work.func)
14514                         queue_work(system_unbound_wq, &state->base.commit_work);
14515                 break;
14516
14517         case FENCE_FREE:
14518                 drm_atomic_state_put(&state->base);
14519                 break;
14520         }
14521
14522         return NOTIFY_DONE;
14523 }
14524
14525 static void intel_atomic_track_fbs(struct drm_atomic_state *state)
14526 {
14527         struct drm_plane_state *old_plane_state;
14528         struct drm_plane *plane;
14529         int i;
14530
14531         for_each_plane_in_state(state, plane, old_plane_state, i)
14532                 i915_gem_track_fb(intel_fb_obj(old_plane_state->fb),
14533                                   intel_fb_obj(plane->state->fb),
14534                                   to_intel_plane(plane)->frontbuffer_bit);
14535 }
14536
14537 /**
14538  * intel_atomic_commit - commit validated state object
14539  * @dev: DRM device
14540  * @state: the top-level driver state object
14541  * @nonblock: nonblocking commit
14542  *
14543  * This function commits a top-level state object that has been validated
14544  * with drm_atomic_helper_check().
14545  *
14546  * RETURNS
14547  * Zero for success or -errno.
14548  */
14549 static int intel_atomic_commit(struct drm_device *dev,
14550                                struct drm_atomic_state *state,
14551                                bool nonblock)
14552 {
14553         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14554         struct drm_i915_private *dev_priv = to_i915(dev);
14555         int ret = 0;
14556
14557         ret = drm_atomic_helper_setup_commit(state, nonblock);
14558         if (ret)
14559                 return ret;
14560
14561         drm_atomic_state_get(state);
14562         i915_sw_fence_init(&intel_state->commit_ready,
14563                            intel_atomic_commit_ready);
14564
14565         ret = intel_atomic_prepare_commit(dev, state);
14566         if (ret) {
14567                 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
14568                 i915_sw_fence_commit(&intel_state->commit_ready);
14569                 return ret;
14570         }
14571
14572         drm_atomic_helper_swap_state(state, true);
14573         dev_priv->wm.distrust_bios_wm = false;
14574         intel_shared_dpll_commit(state);
14575         intel_atomic_track_fbs(state);
14576
14577         if (intel_state->modeset) {
14578                 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
14579                        sizeof(intel_state->min_pixclk));
14580                 dev_priv->active_crtcs = intel_state->active_crtcs;
14581                 dev_priv->atomic_cdclk_freq = intel_state->cdclk;
14582         }
14583
14584         drm_atomic_state_get(state);
14585         INIT_WORK(&state->commit_work,
14586                   nonblock ? intel_atomic_commit_work : NULL);
14587
14588         i915_sw_fence_commit(&intel_state->commit_ready);
14589         if (!nonblock) {
14590                 i915_sw_fence_wait(&intel_state->commit_ready);
14591                 intel_atomic_commit_tail(state);
14592         }
14593
14594         return 0;
14595 }
14596
14597 void intel_crtc_restore_mode(struct drm_crtc *crtc)
14598 {
14599         struct drm_device *dev = crtc->dev;
14600         struct drm_atomic_state *state;
14601         struct drm_crtc_state *crtc_state;
14602         int ret;
14603
14604         state = drm_atomic_state_alloc(dev);
14605         if (!state) {
14606                 DRM_DEBUG_KMS("[CRTC:%d:%s] crtc restore failed, out of memory",
14607                               crtc->base.id, crtc->name);
14608                 return;
14609         }
14610
14611         state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
14612
14613 retry:
14614         crtc_state = drm_atomic_get_crtc_state(state, crtc);
14615         ret = PTR_ERR_OR_ZERO(crtc_state);
14616         if (!ret) {
14617                 if (!crtc_state->active)
14618                         goto out;
14619
14620                 crtc_state->mode_changed = true;
14621                 ret = drm_atomic_commit(state);
14622         }
14623
14624         if (ret == -EDEADLK) {
14625                 drm_atomic_state_clear(state);
14626                 drm_modeset_backoff(state->acquire_ctx);
14627                 goto retry;
14628         }
14629
14630 out:
14631         drm_atomic_state_put(state);
14632 }
14633
14634 /*
14635  * FIXME: Remove this once i915 is fully DRIVER_ATOMIC by calling
14636  *        drm_atomic_helper_legacy_gamma_set() directly.
14637  */
14638 static int intel_atomic_legacy_gamma_set(struct drm_crtc *crtc,
14639                                          u16 *red, u16 *green, u16 *blue,
14640                                          uint32_t size)
14641 {
14642         struct drm_device *dev = crtc->dev;
14643         struct drm_mode_config *config = &dev->mode_config;
14644         struct drm_crtc_state *state;
14645         int ret;
14646
14647         ret = drm_atomic_helper_legacy_gamma_set(crtc, red, green, blue, size);
14648         if (ret)
14649                 return ret;
14650
14651         /*
14652          * Make sure we update the legacy properties so this works when
14653          * atomic is not enabled.
14654          */
14655
14656         state = crtc->state;
14657
14658         drm_object_property_set_value(&crtc->base,
14659                                       config->degamma_lut_property,
14660                                       (state->degamma_lut) ?
14661                                       state->degamma_lut->base.id : 0);
14662
14663         drm_object_property_set_value(&crtc->base,
14664                                       config->ctm_property,
14665                                       (state->ctm) ?
14666                                       state->ctm->base.id : 0);
14667
14668         drm_object_property_set_value(&crtc->base,
14669                                       config->gamma_lut_property,
14670                                       (state->gamma_lut) ?
14671                                       state->gamma_lut->base.id : 0);
14672
14673         return 0;
14674 }
14675
14676 static const struct drm_crtc_funcs intel_crtc_funcs = {
14677         .gamma_set = intel_atomic_legacy_gamma_set,
14678         .set_config = drm_atomic_helper_set_config,
14679         .set_property = drm_atomic_helper_crtc_set_property,
14680         .destroy = intel_crtc_destroy,
14681         .page_flip = intel_crtc_page_flip,
14682         .atomic_duplicate_state = intel_crtc_duplicate_state,
14683         .atomic_destroy_state = intel_crtc_destroy_state,
14684 };
14685
14686 /**
14687  * intel_prepare_plane_fb - Prepare fb for usage on plane
14688  * @plane: drm plane to prepare for
14689  * @fb: framebuffer to prepare for presentation
14690  *
14691  * Prepares a framebuffer for usage on a display plane.  Generally this
14692  * involves pinning the underlying object and updating the frontbuffer tracking
14693  * bits.  Some older platforms need special physical address handling for
14694  * cursor planes.
14695  *
14696  * Must be called with struct_mutex held.
14697  *
14698  * Returns 0 on success, negative error code on failure.
14699  */
14700 int
14701 intel_prepare_plane_fb(struct drm_plane *plane,
14702                        struct drm_plane_state *new_state)
14703 {
14704         struct intel_atomic_state *intel_state =
14705                 to_intel_atomic_state(new_state->state);
14706         struct drm_i915_private *dev_priv = to_i915(plane->dev);
14707         struct drm_framebuffer *fb = new_state->fb;
14708         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14709         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
14710         int ret;
14711
14712         if (!obj && !old_obj)
14713                 return 0;
14714
14715         if (old_obj) {
14716                 struct drm_crtc_state *crtc_state =
14717                         drm_atomic_get_existing_crtc_state(new_state->state,
14718                                                            plane->state->crtc);
14719
14720                 /* Big Hammer, we also need to ensure that any pending
14721                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
14722                  * current scanout is retired before unpinning the old
14723                  * framebuffer. Note that we rely on userspace rendering
14724                  * into the buffer attached to the pipe they are waiting
14725                  * on. If not, userspace generates a GPU hang with IPEHR
14726                  * point to the MI_WAIT_FOR_EVENT.
14727                  *
14728                  * This should only fail upon a hung GPU, in which case we
14729                  * can safely continue.
14730                  */
14731                 if (needs_modeset(crtc_state)) {
14732                         ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
14733                                                               old_obj->resv, NULL,
14734                                                               false, 0,
14735                                                               GFP_KERNEL);
14736                         if (ret < 0)
14737                                 return ret;
14738                 }
14739         }
14740
14741         if (new_state->fence) { /* explicit fencing */
14742                 ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready,
14743                                                     new_state->fence,
14744                                                     I915_FENCE_TIMEOUT,
14745                                                     GFP_KERNEL);
14746                 if (ret < 0)
14747                         return ret;
14748         }
14749
14750         if (!obj)
14751                 return 0;
14752
14753         if (!new_state->fence) { /* implicit fencing */
14754                 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
14755                                                       obj->resv, NULL,
14756                                                       false, I915_FENCE_TIMEOUT,
14757                                                       GFP_KERNEL);
14758                 if (ret < 0)
14759                         return ret;
14760
14761                 i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY);
14762         }
14763
14764         if (plane->type == DRM_PLANE_TYPE_CURSOR &&
14765             INTEL_INFO(dev_priv)->cursor_needs_physical) {
14766                 int align = IS_I830(dev_priv) ? 16 * 1024 : 256;
14767                 ret = i915_gem_object_attach_phys(obj, align);
14768                 if (ret) {
14769                         DRM_DEBUG_KMS("failed to attach phys object\n");
14770                         return ret;
14771                 }
14772         } else {
14773                 struct i915_vma *vma;
14774
14775                 vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
14776                 if (IS_ERR(vma)) {
14777                         DRM_DEBUG_KMS("failed to pin object\n");
14778                         return PTR_ERR(vma);
14779                 }
14780         }
14781
14782         return 0;
14783 }
14784
14785 /**
14786  * intel_cleanup_plane_fb - Cleans up an fb after plane use
14787  * @plane: drm plane to clean up for
14788  * @fb: old framebuffer that was on plane
14789  *
14790  * Cleans up a framebuffer that has just been removed from a plane.
14791  *
14792  * Must be called with struct_mutex held.
14793  */
14794 void
14795 intel_cleanup_plane_fb(struct drm_plane *plane,
14796                        struct drm_plane_state *old_state)
14797 {
14798         struct drm_i915_private *dev_priv = to_i915(plane->dev);
14799         struct intel_plane_state *old_intel_state;
14800         struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
14801         struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
14802
14803         old_intel_state = to_intel_plane_state(old_state);
14804
14805         if (!obj && !old_obj)
14806                 return;
14807
14808         if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
14809             !INTEL_INFO(dev_priv)->cursor_needs_physical))
14810                 intel_unpin_fb_obj(old_state->fb, old_state->rotation);
14811 }
14812
14813 int
14814 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
14815 {
14816         int max_scale;
14817         int crtc_clock, cdclk;
14818
14819         if (!intel_crtc || !crtc_state->base.enable)
14820                 return DRM_PLANE_HELPER_NO_SCALING;
14821
14822         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
14823         cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
14824
14825         if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
14826                 return DRM_PLANE_HELPER_NO_SCALING;
14827
14828         /*
14829          * skl max scale is lower of:
14830          *    close to 3 but not 3, -1 is for that purpose
14831          *            or
14832          *    cdclk/crtc_clock
14833          */
14834         max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
14835
14836         return max_scale;
14837 }
14838
14839 static int
14840 intel_check_primary_plane(struct drm_plane *plane,
14841                           struct intel_crtc_state *crtc_state,
14842                           struct intel_plane_state *state)
14843 {
14844         struct drm_i915_private *dev_priv = to_i915(plane->dev);
14845         struct drm_crtc *crtc = state->base.crtc;
14846         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
14847         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
14848         bool can_position = false;
14849         int ret;
14850
14851         if (INTEL_GEN(dev_priv) >= 9) {
14852                 /* use scaler when colorkey is not required */
14853                 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
14854                         min_scale = 1;
14855                         max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
14856                 }
14857                 can_position = true;
14858         }
14859
14860         ret = drm_plane_helper_check_state(&state->base,
14861                                            &state->clip,
14862                                            min_scale, max_scale,
14863                                            can_position, true);
14864         if (ret)
14865                 return ret;
14866
14867         if (!state->base.fb)
14868                 return 0;
14869
14870         if (INTEL_GEN(dev_priv) >= 9) {
14871                 ret = skl_check_plane_surface(state);
14872                 if (ret)
14873                         return ret;
14874         }
14875
14876         return 0;
14877 }
14878
14879 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
14880                                     struct drm_crtc_state *old_crtc_state)
14881 {
14882         struct drm_device *dev = crtc->dev;
14883         struct drm_i915_private *dev_priv = to_i915(dev);
14884         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14885         struct intel_crtc_state *intel_cstate =
14886                 to_intel_crtc_state(crtc->state);
14887         struct intel_crtc_state *old_intel_cstate =
14888                 to_intel_crtc_state(old_crtc_state);
14889         struct intel_atomic_state *old_intel_state =
14890                 to_intel_atomic_state(old_crtc_state->state);
14891         bool modeset = needs_modeset(crtc->state);
14892
14893         /* Perform vblank evasion around commit operation */
14894         intel_pipe_update_start(intel_crtc);
14895
14896         if (modeset)
14897                 goto out;
14898
14899         if (crtc->state->color_mgmt_changed || to_intel_crtc_state(crtc->state)->update_pipe) {
14900                 intel_color_set_csc(crtc->state);
14901                 intel_color_load_luts(crtc->state);
14902         }
14903
14904         if (intel_cstate->update_pipe)
14905                 intel_update_pipe_config(intel_crtc, old_intel_cstate);
14906         else if (INTEL_GEN(dev_priv) >= 9)
14907                 skl_detach_scalers(intel_crtc);
14908
14909 out:
14910         if (dev_priv->display.atomic_update_watermarks)
14911                 dev_priv->display.atomic_update_watermarks(old_intel_state,
14912                                                            intel_cstate);
14913 }
14914
14915 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
14916                                      struct drm_crtc_state *old_crtc_state)
14917 {
14918         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14919
14920         intel_pipe_update_end(intel_crtc, NULL);
14921 }
14922
14923 /**
14924  * intel_plane_destroy - destroy a plane
14925  * @plane: plane to destroy
14926  *
14927  * Common destruction function for all types of planes (primary, cursor,
14928  * sprite).
14929  */
14930 void intel_plane_destroy(struct drm_plane *plane)
14931 {
14932         drm_plane_cleanup(plane);
14933         kfree(to_intel_plane(plane));
14934 }
14935
14936 const struct drm_plane_funcs intel_plane_funcs = {
14937         .update_plane = drm_atomic_helper_update_plane,
14938         .disable_plane = drm_atomic_helper_disable_plane,
14939         .destroy = intel_plane_destroy,
14940         .set_property = drm_atomic_helper_plane_set_property,
14941         .atomic_get_property = intel_plane_atomic_get_property,
14942         .atomic_set_property = intel_plane_atomic_set_property,
14943         .atomic_duplicate_state = intel_plane_duplicate_state,
14944         .atomic_destroy_state = intel_plane_destroy_state,
14945 };
14946
14947 static struct intel_plane *
14948 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
14949 {
14950         struct intel_plane *primary = NULL;
14951         struct intel_plane_state *state = NULL;
14952         const uint32_t *intel_primary_formats;
14953         unsigned int supported_rotations;
14954         unsigned int num_formats;
14955         int ret;
14956
14957         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
14958         if (!primary) {
14959                 ret = -ENOMEM;
14960                 goto fail;
14961         }
14962
14963         state = intel_create_plane_state(&primary->base);
14964         if (!state) {
14965                 ret = -ENOMEM;
14966                 goto fail;
14967         }
14968
14969         primary->base.state = &state->base;
14970
14971         primary->can_scale = false;
14972         primary->max_downscale = 1;
14973         if (INTEL_GEN(dev_priv) >= 9) {
14974                 primary->can_scale = true;
14975                 state->scaler_id = -1;
14976         }
14977         primary->pipe = pipe;
14978         /*
14979          * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
14980          * port is hooked to pipe B. Hence we want plane A feeding pipe B.
14981          */
14982         if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
14983                 primary->plane = (enum plane) !pipe;
14984         else
14985                 primary->plane = (enum plane) pipe;
14986         primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
14987         primary->check_plane = intel_check_primary_plane;
14988
14989         if (INTEL_GEN(dev_priv) >= 9) {
14990                 intel_primary_formats = skl_primary_formats;
14991                 num_formats = ARRAY_SIZE(skl_primary_formats);
14992
14993                 primary->update_plane = skylake_update_primary_plane;
14994                 primary->disable_plane = skylake_disable_primary_plane;
14995         } else if (HAS_PCH_SPLIT(dev_priv)) {
14996                 intel_primary_formats = i965_primary_formats;
14997                 num_formats = ARRAY_SIZE(i965_primary_formats);
14998
14999                 primary->update_plane = ironlake_update_primary_plane;
15000                 primary->disable_plane = i9xx_disable_primary_plane;
15001         } else if (INTEL_GEN(dev_priv) >= 4) {
15002                 intel_primary_formats = i965_primary_formats;
15003                 num_formats = ARRAY_SIZE(i965_primary_formats);
15004
15005                 primary->update_plane = i9xx_update_primary_plane;
15006                 primary->disable_plane = i9xx_disable_primary_plane;
15007         } else {
15008                 intel_primary_formats = i8xx_primary_formats;
15009                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
15010
15011                 primary->update_plane = i9xx_update_primary_plane;
15012                 primary->disable_plane = i9xx_disable_primary_plane;
15013         }
15014
15015         if (INTEL_GEN(dev_priv) >= 9)
15016                 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
15017                                                0, &intel_plane_funcs,
15018                                                intel_primary_formats, num_formats,
15019                                                DRM_PLANE_TYPE_PRIMARY,
15020                                                "plane 1%c", pipe_name(pipe));
15021         else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
15022                 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
15023                                                0, &intel_plane_funcs,
15024                                                intel_primary_formats, num_formats,
15025                                                DRM_PLANE_TYPE_PRIMARY,
15026                                                "primary %c", pipe_name(pipe));
15027         else
15028                 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
15029                                                0, &intel_plane_funcs,
15030                                                intel_primary_formats, num_formats,
15031                                                DRM_PLANE_TYPE_PRIMARY,
15032                                                "plane %c", plane_name(primary->plane));
15033         if (ret)
15034                 goto fail;
15035
15036         if (INTEL_GEN(dev_priv) >= 9) {
15037                 supported_rotations =
15038                         DRM_ROTATE_0 | DRM_ROTATE_90 |
15039                         DRM_ROTATE_180 | DRM_ROTATE_270;
15040         } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
15041                 supported_rotations =
15042                         DRM_ROTATE_0 | DRM_ROTATE_180 |
15043                         DRM_REFLECT_X;
15044         } else if (INTEL_GEN(dev_priv) >= 4) {
15045                 supported_rotations =
15046                         DRM_ROTATE_0 | DRM_ROTATE_180;
15047         } else {
15048                 supported_rotations = DRM_ROTATE_0;
15049         }
15050
15051         if (INTEL_GEN(dev_priv) >= 4)
15052                 drm_plane_create_rotation_property(&primary->base,
15053                                                    DRM_ROTATE_0,
15054                                                    supported_rotations);
15055
15056         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
15057
15058         return primary;
15059
15060 fail:
15061         kfree(state);
15062         kfree(primary);
15063
15064         return ERR_PTR(ret);
15065 }
15066
15067 static int
15068 intel_check_cursor_plane(struct drm_plane *plane,
15069                          struct intel_crtc_state *crtc_state,
15070                          struct intel_plane_state *state)
15071 {
15072         struct drm_framebuffer *fb = state->base.fb;
15073         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
15074         enum pipe pipe = to_intel_plane(plane)->pipe;
15075         unsigned stride;
15076         int ret;
15077
15078         ret = drm_plane_helper_check_state(&state->base,
15079                                            &state->clip,
15080                                            DRM_PLANE_HELPER_NO_SCALING,
15081                                            DRM_PLANE_HELPER_NO_SCALING,
15082                                            true, true);
15083         if (ret)
15084                 return ret;
15085
15086         /* if we want to turn off the cursor ignore width and height */
15087         if (!obj)
15088                 return 0;
15089
15090         /* Check for which cursor types we support */
15091         if (!cursor_size_ok(to_i915(plane->dev), state->base.crtc_w,
15092                             state->base.crtc_h)) {
15093                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
15094                           state->base.crtc_w, state->base.crtc_h);
15095                 return -EINVAL;
15096         }
15097
15098         stride = roundup_pow_of_two(state->base.crtc_w) * 4;
15099         if (obj->base.size < stride * state->base.crtc_h) {
15100                 DRM_DEBUG_KMS("buffer is too small\n");
15101                 return -ENOMEM;
15102         }
15103
15104         if (fb->modifier != DRM_FORMAT_MOD_NONE) {
15105                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
15106                 return -EINVAL;
15107         }
15108
15109         /*
15110          * There's something wrong with the cursor on CHV pipe C.
15111          * If it straddles the left edge of the screen then
15112          * moving it away from the edge or disabling it often
15113          * results in a pipe underrun, and often that can lead to
15114          * dead pipe (constant underrun reported, and it scans
15115          * out just a solid color). To recover from that, the
15116          * display power well must be turned off and on again.
15117          * Refuse the put the cursor into that compromised position.
15118          */
15119         if (IS_CHERRYVIEW(to_i915(plane->dev)) && pipe == PIPE_C &&
15120             state->base.visible && state->base.crtc_x < 0) {
15121                 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
15122                 return -EINVAL;
15123         }
15124
15125         return 0;
15126 }
15127
15128 static void
15129 intel_disable_cursor_plane(struct drm_plane *plane,
15130                            struct drm_crtc *crtc)
15131 {
15132         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
15133
15134         intel_crtc->cursor_addr = 0;
15135         intel_crtc_update_cursor(crtc, NULL);
15136 }
15137
15138 static void
15139 intel_update_cursor_plane(struct drm_plane *plane,
15140                           const struct intel_crtc_state *crtc_state,
15141                           const struct intel_plane_state *state)
15142 {
15143         struct drm_crtc *crtc = crtc_state->base.crtc;
15144         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
15145         struct drm_i915_private *dev_priv = to_i915(plane->dev);
15146         struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
15147         uint32_t addr;
15148
15149         if (!obj)
15150                 addr = 0;
15151         else if (!INTEL_INFO(dev_priv)->cursor_needs_physical)
15152                 addr = i915_gem_object_ggtt_offset(obj, NULL);
15153         else
15154                 addr = obj->phys_handle->busaddr;
15155
15156         intel_crtc->cursor_addr = addr;
15157         intel_crtc_update_cursor(crtc, state);
15158 }
15159
15160 static struct intel_plane *
15161 intel_cursor_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
15162 {
15163         struct intel_plane *cursor = NULL;
15164         struct intel_plane_state *state = NULL;
15165         int ret;
15166
15167         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
15168         if (!cursor) {
15169                 ret = -ENOMEM;
15170                 goto fail;
15171         }
15172
15173         state = intel_create_plane_state(&cursor->base);
15174         if (!state) {
15175                 ret = -ENOMEM;
15176                 goto fail;
15177         }
15178
15179         cursor->base.state = &state->base;
15180
15181         cursor->can_scale = false;
15182         cursor->max_downscale = 1;
15183         cursor->pipe = pipe;
15184         cursor->plane = pipe;
15185         cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
15186         cursor->check_plane = intel_check_cursor_plane;
15187         cursor->update_plane = intel_update_cursor_plane;
15188         cursor->disable_plane = intel_disable_cursor_plane;
15189
15190         ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
15191                                        0, &intel_plane_funcs,
15192                                        intel_cursor_formats,
15193                                        ARRAY_SIZE(intel_cursor_formats),
15194                                        DRM_PLANE_TYPE_CURSOR,
15195                                        "cursor %c", pipe_name(pipe));
15196         if (ret)
15197                 goto fail;
15198
15199         if (INTEL_GEN(dev_priv) >= 4)
15200                 drm_plane_create_rotation_property(&cursor->base,
15201                                                    DRM_ROTATE_0,
15202                                                    DRM_ROTATE_0 |
15203                                                    DRM_ROTATE_180);
15204
15205         if (INTEL_GEN(dev_priv) >= 9)
15206                 state->scaler_id = -1;
15207
15208         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
15209
15210         return cursor;
15211
15212 fail:
15213         kfree(state);
15214         kfree(cursor);
15215
15216         return ERR_PTR(ret);
15217 }
15218
15219 static void skl_init_scalers(struct drm_i915_private *dev_priv,
15220                              struct intel_crtc *crtc,
15221                              struct intel_crtc_state *crtc_state)
15222 {
15223         struct intel_crtc_scaler_state *scaler_state =
15224                 &crtc_state->scaler_state;
15225         int i;
15226
15227         for (i = 0; i < crtc->num_scalers; i++) {
15228                 struct intel_scaler *scaler = &scaler_state->scalers[i];
15229
15230                 scaler->in_use = 0;
15231                 scaler->mode = PS_SCALER_MODE_DYN;
15232         }
15233
15234         scaler_state->scaler_id = -1;
15235 }
15236
15237 static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
15238 {
15239         struct intel_crtc *intel_crtc;
15240         struct intel_crtc_state *crtc_state = NULL;
15241         struct intel_plane *primary = NULL;
15242         struct intel_plane *cursor = NULL;
15243         int sprite, ret;
15244
15245         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
15246         if (!intel_crtc)
15247                 return -ENOMEM;
15248
15249         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
15250         if (!crtc_state) {
15251                 ret = -ENOMEM;
15252                 goto fail;
15253         }
15254         intel_crtc->config = crtc_state;
15255         intel_crtc->base.state = &crtc_state->base;
15256         crtc_state->base.crtc = &intel_crtc->base;
15257
15258         /* initialize shared scalers */
15259         if (INTEL_GEN(dev_priv) >= 9) {
15260                 if (pipe == PIPE_C)
15261                         intel_crtc->num_scalers = 1;
15262                 else
15263                         intel_crtc->num_scalers = SKL_NUM_SCALERS;
15264
15265                 skl_init_scalers(dev_priv, intel_crtc, crtc_state);
15266         }
15267
15268         primary = intel_primary_plane_create(dev_priv, pipe);
15269         if (IS_ERR(primary)) {
15270                 ret = PTR_ERR(primary);
15271                 goto fail;
15272         }
15273
15274         for_each_sprite(dev_priv, pipe, sprite) {
15275                 struct intel_plane *plane;
15276
15277                 plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
15278                 if (IS_ERR(plane)) {
15279                         ret = PTR_ERR(plane);
15280                         goto fail;
15281                 }
15282         }
15283
15284         cursor = intel_cursor_plane_create(dev_priv, pipe);
15285         if (IS_ERR(cursor)) {
15286                 ret = PTR_ERR(cursor);
15287                 goto fail;
15288         }
15289
15290         ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base,
15291                                         &primary->base, &cursor->base,
15292                                         &intel_crtc_funcs,
15293                                         "pipe %c", pipe_name(pipe));
15294         if (ret)
15295                 goto fail;
15296
15297         intel_crtc->pipe = pipe;
15298         intel_crtc->plane = primary->plane;
15299
15300         intel_crtc->cursor_base = ~0;
15301         intel_crtc->cursor_cntl = ~0;
15302         intel_crtc->cursor_size = ~0;
15303
15304         intel_crtc->wm.cxsr_allowed = true;
15305
15306         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
15307                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
15308         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = intel_crtc;
15309         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = intel_crtc;
15310
15311         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
15312
15313         intel_color_init(&intel_crtc->base);
15314
15315         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
15316
15317         return 0;
15318
15319 fail:
15320         /*
15321          * drm_mode_config_cleanup() will free up any
15322          * crtcs/planes already initialized.
15323          */
15324         kfree(crtc_state);
15325         kfree(intel_crtc);
15326
15327         return ret;
15328 }
15329
15330 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
15331 {
15332         struct drm_encoder *encoder = connector->base.encoder;
15333         struct drm_device *dev = connector->base.dev;
15334
15335         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
15336
15337         if (!encoder || WARN_ON(!encoder->crtc))
15338                 return INVALID_PIPE;
15339
15340         return to_intel_crtc(encoder->crtc)->pipe;
15341 }
15342
15343 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
15344                                 struct drm_file *file)
15345 {
15346         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
15347         struct drm_crtc *drmmode_crtc;
15348         struct intel_crtc *crtc;
15349
15350         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
15351         if (!drmmode_crtc)
15352                 return -ENOENT;
15353
15354         crtc = to_intel_crtc(drmmode_crtc);
15355         pipe_from_crtc_id->pipe = crtc->pipe;
15356
15357         return 0;
15358 }
15359
15360 static int intel_encoder_clones(struct intel_encoder *encoder)
15361 {
15362         struct drm_device *dev = encoder->base.dev;
15363         struct intel_encoder *source_encoder;
15364         int index_mask = 0;
15365         int entry = 0;
15366
15367         for_each_intel_encoder(dev, source_encoder) {
15368                 if (encoders_cloneable(encoder, source_encoder))
15369                         index_mask |= (1 << entry);
15370
15371                 entry++;
15372         }
15373
15374         return index_mask;
15375 }
15376
15377 static bool has_edp_a(struct drm_i915_private *dev_priv)
15378 {
15379         if (!IS_MOBILE(dev_priv))
15380                 return false;
15381
15382         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
15383                 return false;
15384
15385         if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
15386                 return false;
15387
15388         return true;
15389 }
15390
15391 static bool intel_crt_present(struct drm_i915_private *dev_priv)
15392 {
15393         if (INTEL_GEN(dev_priv) >= 9)
15394                 return false;
15395
15396         if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
15397                 return false;
15398
15399         if (IS_CHERRYVIEW(dev_priv))
15400                 return false;
15401
15402         if (HAS_PCH_LPT_H(dev_priv) &&
15403             I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
15404                 return false;
15405
15406         /* DDI E can't be used if DDI A requires 4 lanes */
15407         if (HAS_DDI(dev_priv) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
15408                 return false;
15409
15410         if (!dev_priv->vbt.int_crt_support)
15411                 return false;
15412
15413         return true;
15414 }
15415
15416 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
15417 {
15418         int pps_num;
15419         int pps_idx;
15420
15421         if (HAS_DDI(dev_priv))
15422                 return;
15423         /*
15424          * This w/a is needed at least on CPT/PPT, but to be sure apply it
15425          * everywhere where registers can be write protected.
15426          */
15427         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15428                 pps_num = 2;
15429         else
15430                 pps_num = 1;
15431
15432         for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
15433                 u32 val = I915_READ(PP_CONTROL(pps_idx));
15434
15435                 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
15436                 I915_WRITE(PP_CONTROL(pps_idx), val);
15437         }
15438 }
15439
15440 static void intel_pps_init(struct drm_i915_private *dev_priv)
15441 {
15442         if (HAS_PCH_SPLIT(dev_priv) || IS_BROXTON(dev_priv))
15443                 dev_priv->pps_mmio_base = PCH_PPS_BASE;
15444         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15445                 dev_priv->pps_mmio_base = VLV_PPS_BASE;
15446         else
15447                 dev_priv->pps_mmio_base = PPS_BASE;
15448
15449         intel_pps_unlock_regs_wa(dev_priv);
15450 }
15451
15452 static void intel_setup_outputs(struct drm_device *dev)
15453 {
15454         struct drm_i915_private *dev_priv = to_i915(dev);
15455         struct intel_encoder *encoder;
15456         bool dpd_is_edp = false;
15457
15458         intel_pps_init(dev_priv);
15459
15460         /*
15461          * intel_edp_init_connector() depends on this completing first, to
15462          * prevent the registeration of both eDP and LVDS and the incorrect
15463          * sharing of the PPS.
15464          */
15465         intel_lvds_init(dev);
15466
15467         if (intel_crt_present(dev_priv))
15468                 intel_crt_init(dev);
15469
15470         if (IS_BROXTON(dev_priv)) {
15471                 /*
15472                  * FIXME: Broxton doesn't support port detection via the
15473                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
15474                  * detect the ports.
15475                  */
15476                 intel_ddi_init(dev, PORT_A);
15477                 intel_ddi_init(dev, PORT_B);
15478                 intel_ddi_init(dev, PORT_C);
15479
15480                 intel_dsi_init(dev);
15481         } else if (HAS_DDI(dev_priv)) {
15482                 int found;
15483
15484                 /*
15485                  * Haswell uses DDI functions to detect digital outputs.
15486                  * On SKL pre-D0 the strap isn't connected, so we assume
15487                  * it's there.
15488                  */
15489                 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
15490                 /* WaIgnoreDDIAStrap: skl */
15491                 if (found || IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
15492                         intel_ddi_init(dev, PORT_A);
15493
15494                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
15495                  * register */
15496                 found = I915_READ(SFUSE_STRAP);
15497
15498                 if (found & SFUSE_STRAP_DDIB_DETECTED)
15499                         intel_ddi_init(dev, PORT_B);
15500                 if (found & SFUSE_STRAP_DDIC_DETECTED)
15501                         intel_ddi_init(dev, PORT_C);
15502                 if (found & SFUSE_STRAP_DDID_DETECTED)
15503                         intel_ddi_init(dev, PORT_D);
15504                 /*
15505                  * On SKL we don't have a way to detect DDI-E so we rely on VBT.
15506                  */
15507                 if ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) &&
15508                     (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
15509                      dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
15510                      dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
15511                         intel_ddi_init(dev, PORT_E);
15512
15513         } else if (HAS_PCH_SPLIT(dev_priv)) {
15514                 int found;
15515                 dpd_is_edp = intel_dp_is_edp(dev_priv, PORT_D);
15516
15517                 if (has_edp_a(dev_priv))
15518                         intel_dp_init(dev, DP_A, PORT_A);
15519
15520                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
15521                         /* PCH SDVOB multiplex with HDMIB */
15522                         found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B);
15523                         if (!found)
15524                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
15525                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
15526                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
15527                 }
15528
15529                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
15530                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
15531
15532                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
15533                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
15534
15535                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
15536                         intel_dp_init(dev, PCH_DP_C, PORT_C);
15537
15538                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
15539                         intel_dp_init(dev, PCH_DP_D, PORT_D);
15540         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15541                 bool has_edp, has_port;
15542
15543                 /*
15544                  * The DP_DETECTED bit is the latched state of the DDC
15545                  * SDA pin at boot. However since eDP doesn't require DDC
15546                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
15547                  * eDP ports may have been muxed to an alternate function.
15548                  * Thus we can't rely on the DP_DETECTED bit alone to detect
15549                  * eDP ports. Consult the VBT as well as DP_DETECTED to
15550                  * detect eDP ports.
15551                  *
15552                  * Sadly the straps seem to be missing sometimes even for HDMI
15553                  * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
15554                  * and VBT for the presence of the port. Additionally we can't
15555                  * trust the port type the VBT declares as we've seen at least
15556                  * HDMI ports that the VBT claim are DP or eDP.
15557                  */
15558                 has_edp = intel_dp_is_edp(dev_priv, PORT_B);
15559                 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
15560                 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
15561                         has_edp &= intel_dp_init(dev, VLV_DP_B, PORT_B);
15562                 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
15563                         intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
15564
15565                 has_edp = intel_dp_is_edp(dev_priv, PORT_C);
15566                 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
15567                 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
15568                         has_edp &= intel_dp_init(dev, VLV_DP_C, PORT_C);
15569                 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
15570                         intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
15571
15572                 if (IS_CHERRYVIEW(dev_priv)) {
15573                         /*
15574                          * eDP not supported on port D,
15575                          * so no need to worry about it
15576                          */
15577                         has_port = intel_bios_is_port_present(dev_priv, PORT_D);
15578                         if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
15579                                 intel_dp_init(dev, CHV_DP_D, PORT_D);
15580                         if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
15581                                 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
15582                 }
15583
15584                 intel_dsi_init(dev);
15585         } else if (!IS_GEN2(dev_priv) && !IS_PINEVIEW(dev_priv)) {
15586                 bool found = false;
15587
15588                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
15589                         DRM_DEBUG_KMS("probing SDVOB\n");
15590                         found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
15591                         if (!found && IS_G4X(dev_priv)) {
15592                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
15593                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
15594                         }
15595
15596                         if (!found && IS_G4X(dev_priv))
15597                                 intel_dp_init(dev, DP_B, PORT_B);
15598                 }
15599
15600                 /* Before G4X SDVOC doesn't have its own detect register */
15601
15602                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
15603                         DRM_DEBUG_KMS("probing SDVOC\n");
15604                         found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C);
15605                 }
15606
15607                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
15608
15609                         if (IS_G4X(dev_priv)) {
15610                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
15611                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
15612                         }
15613                         if (IS_G4X(dev_priv))
15614                                 intel_dp_init(dev, DP_C, PORT_C);
15615                 }
15616
15617                 if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
15618                         intel_dp_init(dev, DP_D, PORT_D);
15619         } else if (IS_GEN2(dev_priv))
15620                 intel_dvo_init(dev);
15621
15622         if (SUPPORTS_TV(dev_priv))
15623                 intel_tv_init(dev);
15624
15625         intel_psr_init(dev);
15626
15627         for_each_intel_encoder(dev, encoder) {
15628                 encoder->base.possible_crtcs = encoder->crtc_mask;
15629                 encoder->base.possible_clones =
15630                         intel_encoder_clones(encoder);
15631         }
15632
15633         intel_init_pch_refclk(dev);
15634
15635         drm_helper_move_panel_connectors_to_head(dev);
15636 }
15637
15638 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
15639 {
15640         struct drm_device *dev = fb->dev;
15641         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
15642
15643         drm_framebuffer_cleanup(fb);
15644         mutex_lock(&dev->struct_mutex);
15645         WARN_ON(!intel_fb->obj->framebuffer_references--);
15646         i915_gem_object_put(intel_fb->obj);
15647         mutex_unlock(&dev->struct_mutex);
15648         kfree(intel_fb);
15649 }
15650
15651 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
15652                                                 struct drm_file *file,
15653                                                 unsigned int *handle)
15654 {
15655         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
15656         struct drm_i915_gem_object *obj = intel_fb->obj;
15657
15658         if (obj->userptr.mm) {
15659                 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
15660                 return -EINVAL;
15661         }
15662
15663         return drm_gem_handle_create(file, &obj->base, handle);
15664 }
15665
15666 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
15667                                         struct drm_file *file,
15668                                         unsigned flags, unsigned color,
15669                                         struct drm_clip_rect *clips,
15670                                         unsigned num_clips)
15671 {
15672         struct drm_device *dev = fb->dev;
15673         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
15674         struct drm_i915_gem_object *obj = intel_fb->obj;
15675
15676         mutex_lock(&dev->struct_mutex);
15677         if (obj->pin_display && obj->cache_dirty)
15678                 i915_gem_clflush_object(obj, true);
15679         intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
15680         mutex_unlock(&dev->struct_mutex);
15681
15682         return 0;
15683 }
15684
15685 static const struct drm_framebuffer_funcs intel_fb_funcs = {
15686         .destroy = intel_user_framebuffer_destroy,
15687         .create_handle = intel_user_framebuffer_create_handle,
15688         .dirty = intel_user_framebuffer_dirty,
15689 };
15690
15691 static
15692 u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv,
15693                          uint64_t fb_modifier, uint32_t pixel_format)
15694 {
15695         u32 gen = INTEL_INFO(dev_priv)->gen;
15696
15697         if (gen >= 9) {
15698                 int cpp = drm_format_plane_cpp(pixel_format, 0);
15699
15700                 /* "The stride in bytes must not exceed the of the size of 8K
15701                  *  pixels and 32K bytes."
15702                  */
15703                 return min(8192 * cpp, 32768);
15704         } else if (gen >= 5 && !IS_VALLEYVIEW(dev_priv) &&
15705                    !IS_CHERRYVIEW(dev_priv)) {
15706                 return 32*1024;
15707         } else if (gen >= 4) {
15708                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
15709                         return 16*1024;
15710                 else
15711                         return 32*1024;
15712         } else if (gen >= 3) {
15713                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
15714                         return 8*1024;
15715                 else
15716                         return 16*1024;
15717         } else {
15718                 /* XXX DSPC is limited to 4k tiled */
15719                 return 8*1024;
15720         }
15721 }
15722
15723 static int intel_framebuffer_init(struct drm_device *dev,
15724                                   struct intel_framebuffer *intel_fb,
15725                                   struct drm_mode_fb_cmd2 *mode_cmd,
15726                                   struct drm_i915_gem_object *obj)
15727 {
15728         struct drm_i915_private *dev_priv = to_i915(dev);
15729         unsigned int tiling = i915_gem_object_get_tiling(obj);
15730         int ret;
15731         u32 pitch_limit, stride_alignment;
15732         struct drm_format_name_buf format_name;
15733
15734         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
15735
15736         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
15737                 /*
15738                  * If there's a fence, enforce that
15739                  * the fb modifier and tiling mode match.
15740                  */
15741                 if (tiling != I915_TILING_NONE &&
15742                     tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
15743                         DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
15744                         return -EINVAL;
15745                 }
15746         } else {
15747                 if (tiling == I915_TILING_X) {
15748                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
15749                 } else if (tiling == I915_TILING_Y) {
15750                         DRM_DEBUG("No Y tiling for legacy addfb\n");
15751                         return -EINVAL;
15752                 }
15753         }
15754
15755         /* Passed in modifier sanity checking. */
15756         switch (mode_cmd->modifier[0]) {
15757         case I915_FORMAT_MOD_Y_TILED:
15758         case I915_FORMAT_MOD_Yf_TILED:
15759                 if (INTEL_GEN(dev_priv) < 9) {
15760                         DRM_DEBUG("Unsupported tiling 0x%llx!\n",
15761                                   mode_cmd->modifier[0]);
15762                         return -EINVAL;
15763                 }
15764         case DRM_FORMAT_MOD_NONE:
15765         case I915_FORMAT_MOD_X_TILED:
15766                 break;
15767         default:
15768                 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
15769                           mode_cmd->modifier[0]);
15770                 return -EINVAL;
15771         }
15772
15773         /*
15774          * gen2/3 display engine uses the fence if present,
15775          * so the tiling mode must match the fb modifier exactly.
15776          */
15777         if (INTEL_INFO(dev_priv)->gen < 4 &&
15778             tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
15779                 DRM_DEBUG("tiling_mode must match fb modifier exactly on gen2/3\n");
15780                 return -EINVAL;
15781         }
15782
15783         stride_alignment = intel_fb_stride_alignment(dev_priv,
15784                                                      mode_cmd->modifier[0],
15785                                                      mode_cmd->pixel_format);
15786         if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
15787                 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
15788                           mode_cmd->pitches[0], stride_alignment);
15789                 return -EINVAL;
15790         }
15791
15792         pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->modifier[0],
15793                                            mode_cmd->pixel_format);
15794         if (mode_cmd->pitches[0] > pitch_limit) {
15795                 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
15796                           mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
15797                           "tiled" : "linear",
15798                           mode_cmd->pitches[0], pitch_limit);
15799                 return -EINVAL;
15800         }
15801
15802         /*
15803          * If there's a fence, enforce that
15804          * the fb pitch and fence stride match.
15805          */
15806         if (tiling != I915_TILING_NONE &&
15807             mode_cmd->pitches[0] != i915_gem_object_get_stride(obj)) {
15808                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
15809                           mode_cmd->pitches[0],
15810                           i915_gem_object_get_stride(obj));
15811                 return -EINVAL;
15812         }
15813
15814         /* Reject formats not supported by any plane early. */
15815         switch (mode_cmd->pixel_format) {
15816         case DRM_FORMAT_C8:
15817         case DRM_FORMAT_RGB565:
15818         case DRM_FORMAT_XRGB8888:
15819         case DRM_FORMAT_ARGB8888:
15820                 break;
15821         case DRM_FORMAT_XRGB1555:
15822                 if (INTEL_GEN(dev_priv) > 3) {
15823                         DRM_DEBUG("unsupported pixel format: %s\n",
15824                                   drm_get_format_name(mode_cmd->pixel_format, &format_name));
15825                         return -EINVAL;
15826                 }
15827                 break;
15828         case DRM_FORMAT_ABGR8888:
15829                 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
15830                     INTEL_GEN(dev_priv) < 9) {
15831                         DRM_DEBUG("unsupported pixel format: %s\n",
15832                                   drm_get_format_name(mode_cmd->pixel_format, &format_name));
15833                         return -EINVAL;
15834                 }
15835                 break;
15836         case DRM_FORMAT_XBGR8888:
15837         case DRM_FORMAT_XRGB2101010:
15838         case DRM_FORMAT_XBGR2101010:
15839                 if (INTEL_GEN(dev_priv) < 4) {
15840                         DRM_DEBUG("unsupported pixel format: %s\n",
15841                                   drm_get_format_name(mode_cmd->pixel_format, &format_name));
15842                         return -EINVAL;
15843                 }
15844                 break;
15845         case DRM_FORMAT_ABGR2101010:
15846                 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
15847                         DRM_DEBUG("unsupported pixel format: %s\n",
15848                                   drm_get_format_name(mode_cmd->pixel_format, &format_name));
15849                         return -EINVAL;
15850                 }
15851                 break;
15852         case DRM_FORMAT_YUYV:
15853         case DRM_FORMAT_UYVY:
15854         case DRM_FORMAT_YVYU:
15855         case DRM_FORMAT_VYUY:
15856                 if (INTEL_GEN(dev_priv) < 5) {
15857                         DRM_DEBUG("unsupported pixel format: %s\n",
15858                                   drm_get_format_name(mode_cmd->pixel_format, &format_name));
15859                         return -EINVAL;
15860                 }
15861                 break;
15862         default:
15863                 DRM_DEBUG("unsupported pixel format: %s\n",
15864                           drm_get_format_name(mode_cmd->pixel_format, &format_name));
15865                 return -EINVAL;
15866         }
15867
15868         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
15869         if (mode_cmd->offsets[0] != 0)
15870                 return -EINVAL;
15871
15872         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
15873         intel_fb->obj = obj;
15874
15875         ret = intel_fill_fb_info(dev_priv, &intel_fb->base);
15876         if (ret)
15877                 return ret;
15878
15879         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
15880         if (ret) {
15881                 DRM_ERROR("framebuffer init failed %d\n", ret);
15882                 return ret;
15883         }
15884
15885         intel_fb->obj->framebuffer_references++;
15886
15887         return 0;
15888 }
15889
15890 static struct drm_framebuffer *
15891 intel_user_framebuffer_create(struct drm_device *dev,
15892                               struct drm_file *filp,
15893                               const struct drm_mode_fb_cmd2 *user_mode_cmd)
15894 {
15895         struct drm_framebuffer *fb;
15896         struct drm_i915_gem_object *obj;
15897         struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
15898
15899         obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
15900         if (!obj)
15901                 return ERR_PTR(-ENOENT);
15902
15903         fb = intel_framebuffer_create(dev, &mode_cmd, obj);
15904         if (IS_ERR(fb))
15905                 i915_gem_object_put(obj);
15906
15907         return fb;
15908 }
15909
15910 static const struct drm_mode_config_funcs intel_mode_funcs = {
15911         .fb_create = intel_user_framebuffer_create,
15912         .output_poll_changed = intel_fbdev_output_poll_changed,
15913         .atomic_check = intel_atomic_check,
15914         .atomic_commit = intel_atomic_commit,
15915         .atomic_state_alloc = intel_atomic_state_alloc,
15916         .atomic_state_clear = intel_atomic_state_clear,
15917 };
15918
15919 /**
15920  * intel_init_display_hooks - initialize the display modesetting hooks
15921  * @dev_priv: device private
15922  */
15923 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
15924 {
15925         if (INTEL_INFO(dev_priv)->gen >= 9) {
15926                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
15927                 dev_priv->display.get_initial_plane_config =
15928                         skylake_get_initial_plane_config;
15929                 dev_priv->display.crtc_compute_clock =
15930                         haswell_crtc_compute_clock;
15931                 dev_priv->display.crtc_enable = haswell_crtc_enable;
15932                 dev_priv->display.crtc_disable = haswell_crtc_disable;
15933         } else if (HAS_DDI(dev_priv)) {
15934                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
15935                 dev_priv->display.get_initial_plane_config =
15936                         ironlake_get_initial_plane_config;
15937                 dev_priv->display.crtc_compute_clock =
15938                         haswell_crtc_compute_clock;
15939                 dev_priv->display.crtc_enable = haswell_crtc_enable;
15940                 dev_priv->display.crtc_disable = haswell_crtc_disable;
15941         } else if (HAS_PCH_SPLIT(dev_priv)) {
15942                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
15943                 dev_priv->display.get_initial_plane_config =
15944                         ironlake_get_initial_plane_config;
15945                 dev_priv->display.crtc_compute_clock =
15946                         ironlake_crtc_compute_clock;
15947                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
15948                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
15949         } else if (IS_CHERRYVIEW(dev_priv)) {
15950                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15951                 dev_priv->display.get_initial_plane_config =
15952                         i9xx_get_initial_plane_config;
15953                 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
15954                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
15955                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15956         } else if (IS_VALLEYVIEW(dev_priv)) {
15957                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15958                 dev_priv->display.get_initial_plane_config =
15959                         i9xx_get_initial_plane_config;
15960                 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
15961                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
15962                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15963         } else if (IS_G4X(dev_priv)) {
15964                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15965                 dev_priv->display.get_initial_plane_config =
15966                         i9xx_get_initial_plane_config;
15967                 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
15968                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15969                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15970         } else if (IS_PINEVIEW(dev_priv)) {
15971                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15972                 dev_priv->display.get_initial_plane_config =
15973                         i9xx_get_initial_plane_config;
15974                 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
15975                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15976                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15977         } else if (!IS_GEN2(dev_priv)) {
15978                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15979                 dev_priv->display.get_initial_plane_config =
15980                         i9xx_get_initial_plane_config;
15981                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
15982                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15983                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15984         } else {
15985                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15986                 dev_priv->display.get_initial_plane_config =
15987                         i9xx_get_initial_plane_config;
15988                 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
15989                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15990                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15991         }
15992
15993         /* Returns the core display clock speed */
15994         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
15995                 dev_priv->display.get_display_clock_speed =
15996                         skylake_get_display_clock_speed;
15997         else if (IS_BROXTON(dev_priv))
15998                 dev_priv->display.get_display_clock_speed =
15999                         broxton_get_display_clock_speed;
16000         else if (IS_BROADWELL(dev_priv))
16001                 dev_priv->display.get_display_clock_speed =
16002                         broadwell_get_display_clock_speed;
16003         else if (IS_HASWELL(dev_priv))
16004                 dev_priv->display.get_display_clock_speed =
16005                         haswell_get_display_clock_speed;
16006         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
16007                 dev_priv->display.get_display_clock_speed =
16008                         valleyview_get_display_clock_speed;
16009         else if (IS_GEN5(dev_priv))
16010                 dev_priv->display.get_display_clock_speed =
16011                         ilk_get_display_clock_speed;
16012         else if (IS_I945G(dev_priv) || IS_BROADWATER(dev_priv) ||
16013                  IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
16014                 dev_priv->display.get_display_clock_speed =
16015                         i945_get_display_clock_speed;
16016         else if (IS_GM45(dev_priv))
16017                 dev_priv->display.get_display_clock_speed =
16018                         gm45_get_display_clock_speed;
16019         else if (IS_CRESTLINE(dev_priv))
16020                 dev_priv->display.get_display_clock_speed =
16021                         i965gm_get_display_clock_speed;
16022         else if (IS_PINEVIEW(dev_priv))
16023                 dev_priv->display.get_display_clock_speed =
16024                         pnv_get_display_clock_speed;
16025         else if (IS_G33(dev_priv) || IS_G4X(dev_priv))
16026                 dev_priv->display.get_display_clock_speed =
16027                         g33_get_display_clock_speed;
16028         else if (IS_I915G(dev_priv))
16029                 dev_priv->display.get_display_clock_speed =
16030                         i915_get_display_clock_speed;
16031         else if (IS_I945GM(dev_priv) || IS_845G(dev_priv))
16032                 dev_priv->display.get_display_clock_speed =
16033                         i9xx_misc_get_display_clock_speed;
16034         else if (IS_I915GM(dev_priv))
16035                 dev_priv->display.get_display_clock_speed =
16036                         i915gm_get_display_clock_speed;
16037         else if (IS_I865G(dev_priv))
16038                 dev_priv->display.get_display_clock_speed =
16039                         i865_get_display_clock_speed;
16040         else if (IS_I85X(dev_priv))
16041                 dev_priv->display.get_display_clock_speed =
16042                         i85x_get_display_clock_speed;
16043         else { /* 830 */
16044                 WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n");
16045                 dev_priv->display.get_display_clock_speed =
16046                         i830_get_display_clock_speed;
16047         }
16048
16049         if (IS_GEN5(dev_priv)) {
16050                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
16051         } else if (IS_GEN6(dev_priv)) {
16052                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
16053         } else if (IS_IVYBRIDGE(dev_priv)) {
16054                 /* FIXME: detect B0+ stepping and use auto training */
16055                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
16056         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
16057                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
16058         }
16059
16060         if (IS_BROADWELL(dev_priv)) {
16061                 dev_priv->display.modeset_commit_cdclk =
16062                         broadwell_modeset_commit_cdclk;
16063                 dev_priv->display.modeset_calc_cdclk =
16064                         broadwell_modeset_calc_cdclk;
16065         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
16066                 dev_priv->display.modeset_commit_cdclk =
16067                         valleyview_modeset_commit_cdclk;
16068                 dev_priv->display.modeset_calc_cdclk =
16069                         valleyview_modeset_calc_cdclk;
16070         } else if (IS_BROXTON(dev_priv)) {
16071                 dev_priv->display.modeset_commit_cdclk =
16072                         bxt_modeset_commit_cdclk;
16073                 dev_priv->display.modeset_calc_cdclk =
16074                         bxt_modeset_calc_cdclk;
16075         } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
16076                 dev_priv->display.modeset_commit_cdclk =
16077                         skl_modeset_commit_cdclk;
16078                 dev_priv->display.modeset_calc_cdclk =
16079                         skl_modeset_calc_cdclk;
16080         }
16081
16082         if (dev_priv->info.gen >= 9)
16083                 dev_priv->display.update_crtcs = skl_update_crtcs;
16084         else
16085                 dev_priv->display.update_crtcs = intel_update_crtcs;
16086
16087         switch (INTEL_INFO(dev_priv)->gen) {
16088         case 2:
16089                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
16090                 break;
16091
16092         case 3:
16093                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
16094                 break;
16095
16096         case 4:
16097         case 5:
16098                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
16099                 break;
16100
16101         case 6:
16102                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
16103                 break;
16104         case 7:
16105         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
16106                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
16107                 break;
16108         case 9:
16109                 /* Drop through - unsupported since execlist only. */
16110         default:
16111                 /* Default just returns -ENODEV to indicate unsupported */
16112                 dev_priv->display.queue_flip = intel_default_queue_flip;
16113         }
16114 }
16115
16116 /*
16117  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
16118  * resume, or other times.  This quirk makes sure that's the case for
16119  * affected systems.
16120  */
16121 static void quirk_pipea_force(struct drm_device *dev)
16122 {
16123         struct drm_i915_private *dev_priv = to_i915(dev);
16124
16125         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
16126         DRM_INFO("applying pipe a force quirk\n");
16127 }
16128
16129 static void quirk_pipeb_force(struct drm_device *dev)
16130 {
16131         struct drm_i915_private *dev_priv = to_i915(dev);
16132
16133         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
16134         DRM_INFO("applying pipe b force quirk\n");
16135 }
16136
16137 /*
16138  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
16139  */
16140 static void quirk_ssc_force_disable(struct drm_device *dev)
16141 {
16142         struct drm_i915_private *dev_priv = to_i915(dev);
16143         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
16144         DRM_INFO("applying lvds SSC disable quirk\n");
16145 }
16146
16147 /*
16148  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
16149  * brightness value
16150  */
16151 static void quirk_invert_brightness(struct drm_device *dev)
16152 {
16153         struct drm_i915_private *dev_priv = to_i915(dev);
16154         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
16155         DRM_INFO("applying inverted panel brightness quirk\n");
16156 }
16157
16158 /* Some VBT's incorrectly indicate no backlight is present */
16159 static void quirk_backlight_present(struct drm_device *dev)
16160 {
16161         struct drm_i915_private *dev_priv = to_i915(dev);
16162         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
16163         DRM_INFO("applying backlight present quirk\n");
16164 }
16165
16166 struct intel_quirk {
16167         int device;
16168         int subsystem_vendor;
16169         int subsystem_device;
16170         void (*hook)(struct drm_device *dev);
16171 };
16172
16173 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
16174 struct intel_dmi_quirk {
16175         void (*hook)(struct drm_device *dev);
16176         const struct dmi_system_id (*dmi_id_list)[];
16177 };
16178
16179 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
16180 {
16181         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
16182         return 1;
16183 }
16184
16185 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
16186         {
16187                 .dmi_id_list = &(const struct dmi_system_id[]) {
16188                         {
16189                                 .callback = intel_dmi_reverse_brightness,
16190                                 .ident = "NCR Corporation",
16191                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
16192                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
16193                                 },
16194                         },
16195                         { }  /* terminating entry */
16196                 },
16197                 .hook = quirk_invert_brightness,
16198         },
16199 };
16200
16201 static struct intel_quirk intel_quirks[] = {
16202         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
16203         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
16204
16205         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
16206         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
16207
16208         /* 830 needs to leave pipe A & dpll A up */
16209         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
16210
16211         /* 830 needs to leave pipe B & dpll B up */
16212         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
16213
16214         /* Lenovo U160 cannot use SSC on LVDS */
16215         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
16216
16217         /* Sony Vaio Y cannot use SSC on LVDS */
16218         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
16219
16220         /* Acer Aspire 5734Z must invert backlight brightness */
16221         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
16222
16223         /* Acer/eMachines G725 */
16224         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
16225
16226         /* Acer/eMachines e725 */
16227         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
16228
16229         /* Acer/Packard Bell NCL20 */
16230         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
16231
16232         /* Acer Aspire 4736Z */
16233         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
16234
16235         /* Acer Aspire 5336 */
16236         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
16237
16238         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
16239         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
16240
16241         /* Acer C720 Chromebook (Core i3 4005U) */
16242         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
16243
16244         /* Apple Macbook 2,1 (Core 2 T7400) */
16245         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
16246
16247         /* Apple Macbook 4,1 */
16248         { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
16249
16250         /* Toshiba CB35 Chromebook (Celeron 2955U) */
16251         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
16252
16253         /* HP Chromebook 14 (Celeron 2955U) */
16254         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
16255
16256         /* Dell Chromebook 11 */
16257         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
16258
16259         /* Dell Chromebook 11 (2015 version) */
16260         { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
16261 };
16262
16263 static void intel_init_quirks(struct drm_device *dev)
16264 {
16265         struct pci_dev *d = dev->pdev;
16266         int i;
16267
16268         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
16269                 struct intel_quirk *q = &intel_quirks[i];
16270
16271                 if (d->device == q->device &&
16272                     (d->subsystem_vendor == q->subsystem_vendor ||
16273                      q->subsystem_vendor == PCI_ANY_ID) &&
16274                     (d->subsystem_device == q->subsystem_device ||
16275                      q->subsystem_device == PCI_ANY_ID))
16276                         q->hook(dev);
16277         }
16278         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
16279                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
16280                         intel_dmi_quirks[i].hook(dev);
16281         }
16282 }
16283
16284 /* Disable the VGA plane that we never use */
16285 static void i915_disable_vga(struct drm_i915_private *dev_priv)
16286 {
16287         struct pci_dev *pdev = dev_priv->drm.pdev;
16288         u8 sr1;
16289         i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
16290
16291         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
16292         vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
16293         outb(SR01, VGA_SR_INDEX);
16294         sr1 = inb(VGA_SR_DATA);
16295         outb(sr1 | 1<<5, VGA_SR_DATA);
16296         vga_put(pdev, VGA_RSRC_LEGACY_IO);
16297         udelay(300);
16298
16299         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
16300         POSTING_READ(vga_reg);
16301 }
16302
16303 void intel_modeset_init_hw(struct drm_device *dev)
16304 {
16305         struct drm_i915_private *dev_priv = to_i915(dev);
16306
16307         intel_update_cdclk(dev_priv);
16308
16309         dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
16310
16311         intel_init_clock_gating(dev_priv);
16312 }
16313
16314 /*
16315  * Calculate what we think the watermarks should be for the state we've read
16316  * out of the hardware and then immediately program those watermarks so that
16317  * we ensure the hardware settings match our internal state.
16318  *
16319  * We can calculate what we think WM's should be by creating a duplicate of the
16320  * current state (which was constructed during hardware readout) and running it
16321  * through the atomic check code to calculate new watermark values in the
16322  * state object.
16323  */
16324 static void sanitize_watermarks(struct drm_device *dev)
16325 {
16326         struct drm_i915_private *dev_priv = to_i915(dev);
16327         struct drm_atomic_state *state;
16328         struct intel_atomic_state *intel_state;
16329         struct drm_crtc *crtc;
16330         struct drm_crtc_state *cstate;
16331         struct drm_modeset_acquire_ctx ctx;
16332         int ret;
16333         int i;
16334
16335         /* Only supported on platforms that use atomic watermark design */
16336         if (!dev_priv->display.optimize_watermarks)
16337                 return;
16338
16339         /*
16340          * We need to hold connection_mutex before calling duplicate_state so
16341          * that the connector loop is protected.
16342          */
16343         drm_modeset_acquire_init(&ctx, 0);
16344 retry:
16345         ret = drm_modeset_lock_all_ctx(dev, &ctx);
16346         if (ret == -EDEADLK) {
16347                 drm_modeset_backoff(&ctx);
16348                 goto retry;
16349         } else if (WARN_ON(ret)) {
16350                 goto fail;
16351         }
16352
16353         state = drm_atomic_helper_duplicate_state(dev, &ctx);
16354         if (WARN_ON(IS_ERR(state)))
16355                 goto fail;
16356
16357         intel_state = to_intel_atomic_state(state);
16358
16359         /*
16360          * Hardware readout is the only time we don't want to calculate
16361          * intermediate watermarks (since we don't trust the current
16362          * watermarks).
16363          */
16364         intel_state->skip_intermediate_wm = true;
16365
16366         ret = intel_atomic_check(dev, state);
16367         if (ret) {
16368                 /*
16369                  * If we fail here, it means that the hardware appears to be
16370                  * programmed in a way that shouldn't be possible, given our
16371                  * understanding of watermark requirements.  This might mean a
16372                  * mistake in the hardware readout code or a mistake in the
16373                  * watermark calculations for a given platform.  Raise a WARN
16374                  * so that this is noticeable.
16375                  *
16376                  * If this actually happens, we'll have to just leave the
16377                  * BIOS-programmed watermarks untouched and hope for the best.
16378                  */
16379                 WARN(true, "Could not determine valid watermarks for inherited state\n");
16380                 goto put_state;
16381         }
16382
16383         /* Write calculated watermark values back */
16384         for_each_crtc_in_state(state, crtc, cstate, i) {
16385                 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
16386
16387                 cs->wm.need_postvbl_update = true;
16388                 dev_priv->display.optimize_watermarks(intel_state, cs);
16389         }
16390
16391 put_state:
16392         drm_atomic_state_put(state);
16393 fail:
16394         drm_modeset_drop_locks(&ctx);
16395         drm_modeset_acquire_fini(&ctx);
16396 }
16397
16398 int intel_modeset_init(struct drm_device *dev)
16399 {
16400         struct drm_i915_private *dev_priv = to_i915(dev);
16401         struct i915_ggtt *ggtt = &dev_priv->ggtt;
16402         enum pipe pipe;
16403         struct intel_crtc *crtc;
16404
16405         drm_mode_config_init(dev);
16406
16407         dev->mode_config.min_width = 0;
16408         dev->mode_config.min_height = 0;
16409
16410         dev->mode_config.preferred_depth = 24;
16411         dev->mode_config.prefer_shadow = 1;
16412
16413         dev->mode_config.allow_fb_modifiers = true;
16414
16415         dev->mode_config.funcs = &intel_mode_funcs;
16416
16417         intel_init_quirks(dev);
16418
16419         intel_init_pm(dev_priv);
16420
16421         if (INTEL_INFO(dev_priv)->num_pipes == 0)
16422                 return 0;
16423
16424         /*
16425          * There may be no VBT; and if the BIOS enabled SSC we can
16426          * just keep using it to avoid unnecessary flicker.  Whereas if the
16427          * BIOS isn't using it, don't assume it will work even if the VBT
16428          * indicates as much.
16429          */
16430         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
16431                 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
16432                                             DREF_SSC1_ENABLE);
16433
16434                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
16435                         DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
16436                                      bios_lvds_use_ssc ? "en" : "dis",
16437                                      dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
16438                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
16439                 }
16440         }
16441
16442         if (IS_GEN2(dev_priv)) {
16443                 dev->mode_config.max_width = 2048;
16444                 dev->mode_config.max_height = 2048;
16445         } else if (IS_GEN3(dev_priv)) {
16446                 dev->mode_config.max_width = 4096;
16447                 dev->mode_config.max_height = 4096;
16448         } else {
16449                 dev->mode_config.max_width = 8192;
16450                 dev->mode_config.max_height = 8192;
16451         }
16452
16453         if (IS_845G(dev_priv) || IS_I865G(dev_priv)) {
16454                 dev->mode_config.cursor_width = IS_845G(dev_priv) ? 64 : 512;
16455                 dev->mode_config.cursor_height = 1023;
16456         } else if (IS_GEN2(dev_priv)) {
16457                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
16458                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
16459         } else {
16460                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
16461                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
16462         }
16463
16464         dev->mode_config.fb_base = ggtt->mappable_base;
16465
16466         DRM_DEBUG_KMS("%d display pipe%s available.\n",
16467                       INTEL_INFO(dev_priv)->num_pipes,
16468                       INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : "");
16469
16470         for_each_pipe(dev_priv, pipe) {
16471                 int ret;
16472
16473                 ret = intel_crtc_init(dev_priv, pipe);
16474                 if (ret) {
16475                         drm_mode_config_cleanup(dev);
16476                         return ret;
16477                 }
16478         }
16479
16480         intel_update_czclk(dev_priv);
16481         intel_update_cdclk(dev_priv);
16482         dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
16483
16484         intel_shared_dpll_init(dev);
16485
16486         if (dev_priv->max_cdclk_freq == 0)
16487                 intel_update_max_cdclk(dev_priv);
16488
16489         /* Just disable it once at startup */
16490         i915_disable_vga(dev_priv);
16491         intel_setup_outputs(dev);
16492
16493         drm_modeset_lock_all(dev);
16494         intel_modeset_setup_hw_state(dev);
16495         drm_modeset_unlock_all(dev);
16496
16497         for_each_intel_crtc(dev, crtc) {
16498                 struct intel_initial_plane_config plane_config = {};
16499
16500                 if (!crtc->active)
16501                         continue;
16502
16503                 /*
16504                  * Note that reserving the BIOS fb up front prevents us
16505                  * from stuffing other stolen allocations like the ring
16506                  * on top.  This prevents some ugliness at boot time, and
16507                  * can even allow for smooth boot transitions if the BIOS
16508                  * fb is large enough for the active pipe configuration.
16509                  */
16510                 dev_priv->display.get_initial_plane_config(crtc,
16511                                                            &plane_config);
16512
16513                 /*
16514                  * If the fb is shared between multiple heads, we'll
16515                  * just get the first one.
16516                  */
16517                 intel_find_initial_plane_obj(crtc, &plane_config);
16518         }
16519
16520         /*
16521          * Make sure hardware watermarks really match the state we read out.
16522          * Note that we need to do this after reconstructing the BIOS fb's
16523          * since the watermark calculation done here will use pstate->fb.
16524          */
16525         sanitize_watermarks(dev);
16526
16527         return 0;
16528 }
16529
16530 static void intel_enable_pipe_a(struct drm_device *dev)
16531 {
16532         struct intel_connector *connector;
16533         struct drm_connector *crt = NULL;
16534         struct intel_load_detect_pipe load_detect_temp;
16535         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
16536
16537         /* We can't just switch on the pipe A, we need to set things up with a
16538          * proper mode and output configuration. As a gross hack, enable pipe A
16539          * by enabling the load detect pipe once. */
16540         for_each_intel_connector(dev, connector) {
16541                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
16542                         crt = &connector->base;
16543                         break;
16544                 }
16545         }
16546
16547         if (!crt)
16548                 return;
16549
16550         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
16551                 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
16552 }
16553
16554 static bool
16555 intel_check_plane_mapping(struct intel_crtc *crtc)
16556 {
16557         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
16558         u32 val;
16559
16560         if (INTEL_INFO(dev_priv)->num_pipes == 1)
16561                 return true;
16562
16563         val = I915_READ(DSPCNTR(!crtc->plane));
16564
16565         if ((val & DISPLAY_PLANE_ENABLE) &&
16566             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
16567                 return false;
16568
16569         return true;
16570 }
16571
16572 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
16573 {
16574         struct drm_device *dev = crtc->base.dev;
16575         struct intel_encoder *encoder;
16576
16577         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
16578                 return true;
16579
16580         return false;
16581 }
16582
16583 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
16584 {
16585         struct drm_device *dev = encoder->base.dev;
16586         struct intel_connector *connector;
16587
16588         for_each_connector_on_encoder(dev, &encoder->base, connector)
16589                 return connector;
16590
16591         return NULL;
16592 }
16593
16594 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
16595                               enum transcoder pch_transcoder)
16596 {
16597         return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
16598                 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == TRANSCODER_A);
16599 }
16600
16601 static void intel_sanitize_crtc(struct intel_crtc *crtc)
16602 {
16603         struct drm_device *dev = crtc->base.dev;
16604         struct drm_i915_private *dev_priv = to_i915(dev);
16605         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
16606
16607         /* Clear any frame start delays used for debugging left by the BIOS */
16608         if (!transcoder_is_dsi(cpu_transcoder)) {
16609                 i915_reg_t reg = PIPECONF(cpu_transcoder);
16610
16611                 I915_WRITE(reg,
16612                            I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
16613         }
16614
16615         /* restore vblank interrupts to correct state */
16616         drm_crtc_vblank_reset(&crtc->base);
16617         if (crtc->active) {
16618                 struct intel_plane *plane;
16619
16620                 drm_crtc_vblank_on(&crtc->base);
16621
16622                 /* Disable everything but the primary plane */
16623                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
16624                         if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
16625                                 continue;
16626
16627                         plane->disable_plane(&plane->base, &crtc->base);
16628                 }
16629         }
16630
16631         /* We need to sanitize the plane -> pipe mapping first because this will
16632          * disable the crtc (and hence change the state) if it is wrong. Note
16633          * that gen4+ has a fixed plane -> pipe mapping.  */
16634         if (INTEL_GEN(dev_priv) < 4 && !intel_check_plane_mapping(crtc)) {
16635                 bool plane;
16636
16637                 DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n",
16638                               crtc->base.base.id, crtc->base.name);
16639
16640                 /* Pipe has the wrong plane attached and the plane is active.
16641                  * Temporarily change the plane mapping and disable everything
16642                  * ...  */
16643                 plane = crtc->plane;
16644                 to_intel_plane_state(crtc->base.primary->state)->base.visible = true;
16645                 crtc->plane = !plane;
16646                 intel_crtc_disable_noatomic(&crtc->base);
16647                 crtc->plane = plane;
16648         }
16649
16650         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
16651             crtc->pipe == PIPE_A && !crtc->active) {
16652                 /* BIOS forgot to enable pipe A, this mostly happens after
16653                  * resume. Force-enable the pipe to fix this, the update_dpms
16654                  * call below we restore the pipe to the right state, but leave
16655                  * the required bits on. */
16656                 intel_enable_pipe_a(dev);
16657         }
16658
16659         /* Adjust the state of the output pipe according to whether we
16660          * have active connectors/encoders. */
16661         if (crtc->active && !intel_crtc_has_encoders(crtc))
16662                 intel_crtc_disable_noatomic(&crtc->base);
16663
16664         if (crtc->active || HAS_GMCH_DISPLAY(dev_priv)) {
16665                 /*
16666                  * We start out with underrun reporting disabled to avoid races.
16667                  * For correct bookkeeping mark this on active crtcs.
16668                  *
16669                  * Also on gmch platforms we dont have any hardware bits to
16670                  * disable the underrun reporting. Which means we need to start
16671                  * out with underrun reporting disabled also on inactive pipes,
16672                  * since otherwise we'll complain about the garbage we read when
16673                  * e.g. coming up after runtime pm.
16674                  *
16675                  * No protection against concurrent access is required - at
16676                  * worst a fifo underrun happens which also sets this to false.
16677                  */
16678                 crtc->cpu_fifo_underrun_disabled = true;
16679                 /*
16680                  * We track the PCH trancoder underrun reporting state
16681                  * within the crtc. With crtc for pipe A housing the underrun
16682                  * reporting state for PCH transcoder A, crtc for pipe B housing
16683                  * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
16684                  * and marking underrun reporting as disabled for the non-existing
16685                  * PCH transcoders B and C would prevent enabling the south
16686                  * error interrupt (see cpt_can_enable_serr_int()).
16687                  */
16688                 if (has_pch_trancoder(dev_priv, (enum transcoder)crtc->pipe))
16689                         crtc->pch_fifo_underrun_disabled = true;
16690         }
16691 }
16692
16693 static void intel_sanitize_encoder(struct intel_encoder *encoder)
16694 {
16695         struct intel_connector *connector;
16696
16697         /* We need to check both for a crtc link (meaning that the
16698          * encoder is active and trying to read from a pipe) and the
16699          * pipe itself being active. */
16700         bool has_active_crtc = encoder->base.crtc &&
16701                 to_intel_crtc(encoder->base.crtc)->active;
16702
16703         connector = intel_encoder_find_connector(encoder);
16704         if (connector && !has_active_crtc) {
16705                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
16706                               encoder->base.base.id,
16707                               encoder->base.name);
16708
16709                 /* Connector is active, but has no active pipe. This is
16710                  * fallout from our resume register restoring. Disable
16711                  * the encoder manually again. */
16712                 if (encoder->base.crtc) {
16713                         struct drm_crtc_state *crtc_state = encoder->base.crtc->state;
16714
16715                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
16716                                       encoder->base.base.id,
16717                                       encoder->base.name);
16718                         encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
16719                         if (encoder->post_disable)
16720                                 encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
16721                 }
16722                 encoder->base.crtc = NULL;
16723
16724                 /* Inconsistent output/port/pipe state happens presumably due to
16725                  * a bug in one of the get_hw_state functions. Or someplace else
16726                  * in our code, like the register restore mess on resume. Clamp
16727                  * things to off as a safer default. */
16728
16729                 connector->base.dpms = DRM_MODE_DPMS_OFF;
16730                 connector->base.encoder = NULL;
16731         }
16732         /* Enabled encoders without active connectors will be fixed in
16733          * the crtc fixup. */
16734 }
16735
16736 void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv)
16737 {
16738         i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
16739
16740         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
16741                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
16742                 i915_disable_vga(dev_priv);
16743         }
16744 }
16745
16746 void i915_redisable_vga(struct drm_i915_private *dev_priv)
16747 {
16748         /* This function can be called both from intel_modeset_setup_hw_state or
16749          * at a very early point in our resume sequence, where the power well
16750          * structures are not yet restored. Since this function is at a very
16751          * paranoid "someone might have enabled VGA while we were not looking"
16752          * level, just check if the power well is enabled instead of trying to
16753          * follow the "don't touch the power well if we don't need it" policy
16754          * the rest of the driver uses. */
16755         if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
16756                 return;
16757
16758         i915_redisable_vga_power_on(dev_priv);
16759
16760         intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
16761 }
16762
16763 static bool primary_get_hw_state(struct intel_plane *plane)
16764 {
16765         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
16766
16767         return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
16768 }
16769
16770 /* FIXME read out full plane state for all planes */
16771 static void readout_plane_state(struct intel_crtc *crtc)
16772 {
16773         struct drm_plane *primary = crtc->base.primary;
16774         struct intel_plane_state *plane_state =
16775                 to_intel_plane_state(primary->state);
16776
16777         plane_state->base.visible = crtc->active &&
16778                 primary_get_hw_state(to_intel_plane(primary));
16779
16780         if (plane_state->base.visible)
16781                 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
16782 }
16783
16784 static void intel_modeset_readout_hw_state(struct drm_device *dev)
16785 {
16786         struct drm_i915_private *dev_priv = to_i915(dev);
16787         enum pipe pipe;
16788         struct intel_crtc *crtc;
16789         struct intel_encoder *encoder;
16790         struct intel_connector *connector;
16791         int i;
16792
16793         dev_priv->active_crtcs = 0;
16794
16795         for_each_intel_crtc(dev, crtc) {
16796                 struct intel_crtc_state *crtc_state = crtc->config;
16797
16798                 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
16799                 memset(crtc_state, 0, sizeof(*crtc_state));
16800                 crtc_state->base.crtc = &crtc->base;
16801
16802                 crtc_state->base.active = crtc_state->base.enable =
16803                         dev_priv->display.get_pipe_config(crtc, crtc_state);
16804
16805                 crtc->base.enabled = crtc_state->base.enable;
16806                 crtc->active = crtc_state->base.active;
16807
16808                 if (crtc_state->base.active)
16809                         dev_priv->active_crtcs |= 1 << crtc->pipe;
16810
16811                 readout_plane_state(crtc);
16812
16813                 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
16814                               crtc->base.base.id, crtc->base.name,
16815                               enableddisabled(crtc->active));
16816         }
16817
16818         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
16819                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
16820
16821                 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
16822                                                   &pll->config.hw_state);
16823                 pll->config.crtc_mask = 0;
16824                 for_each_intel_crtc(dev, crtc) {
16825                         if (crtc->active && crtc->config->shared_dpll == pll)
16826                                 pll->config.crtc_mask |= 1 << crtc->pipe;
16827                 }
16828                 pll->active_mask = pll->config.crtc_mask;
16829
16830                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
16831                               pll->name, pll->config.crtc_mask, pll->on);
16832         }
16833
16834         for_each_intel_encoder(dev, encoder) {
16835                 pipe = 0;
16836
16837                 if (encoder->get_hw_state(encoder, &pipe)) {
16838                         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
16839
16840                         encoder->base.crtc = &crtc->base;
16841                         crtc->config->output_types |= 1 << encoder->type;
16842                         encoder->get_config(encoder, crtc->config);
16843                 } else {
16844                         encoder->base.crtc = NULL;
16845                 }
16846
16847                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
16848                               encoder->base.base.id, encoder->base.name,
16849                               enableddisabled(encoder->base.crtc),
16850                               pipe_name(pipe));
16851         }
16852
16853         for_each_intel_connector(dev, connector) {
16854                 if (connector->get_hw_state(connector)) {
16855                         connector->base.dpms = DRM_MODE_DPMS_ON;
16856
16857                         encoder = connector->encoder;
16858                         connector->base.encoder = &encoder->base;
16859
16860                         if (encoder->base.crtc &&
16861                             encoder->base.crtc->state->active) {
16862                                 /*
16863                                  * This has to be done during hardware readout
16864                                  * because anything calling .crtc_disable may
16865                                  * rely on the connector_mask being accurate.
16866                                  */
16867                                 encoder->base.crtc->state->connector_mask |=
16868                                         1 << drm_connector_index(&connector->base);
16869                                 encoder->base.crtc->state->encoder_mask |=
16870                                         1 << drm_encoder_index(&encoder->base);
16871                         }
16872
16873                 } else {
16874                         connector->base.dpms = DRM_MODE_DPMS_OFF;
16875                         connector->base.encoder = NULL;
16876                 }
16877                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
16878                               connector->base.base.id, connector->base.name,
16879                               enableddisabled(connector->base.encoder));
16880         }
16881
16882         for_each_intel_crtc(dev, crtc) {
16883                 int pixclk = 0;
16884
16885                 crtc->base.hwmode = crtc->config->base.adjusted_mode;
16886
16887                 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
16888                 if (crtc->base.state->active) {
16889                         intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
16890                         intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
16891                         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
16892
16893                         /*
16894                          * The initial mode needs to be set in order to keep
16895                          * the atomic core happy. It wants a valid mode if the
16896                          * crtc's enabled, so we do the above call.
16897                          *
16898                          * At this point some state updated by the connectors
16899                          * in their ->detect() callback has not run yet, so
16900                          * no recalculation can be done yet.
16901                          *
16902                          * Even if we could do a recalculation and modeset
16903                          * right now it would cause a double modeset if
16904                          * fbdev or userspace chooses a different initial mode.
16905                          *
16906                          * If that happens, someone indicated they wanted a
16907                          * mode change, which means it's safe to do a full
16908                          * recalculation.
16909                          */
16910                         crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
16911
16912                         if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
16913                                 pixclk = ilk_pipe_pixel_rate(crtc->config);
16914                         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
16915                                 pixclk = crtc->config->base.adjusted_mode.crtc_clock;
16916                         else
16917                                 WARN_ON(dev_priv->display.modeset_calc_cdclk);
16918
16919                         /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
16920                         if (IS_BROADWELL(dev_priv) && crtc->config->ips_enabled)
16921                                 pixclk = DIV_ROUND_UP(pixclk * 100, 95);
16922
16923                         drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
16924                         update_scanline_offset(crtc);
16925                 }
16926
16927                 dev_priv->min_pixclk[crtc->pipe] = pixclk;
16928
16929                 intel_pipe_config_sanity_check(dev_priv, crtc->config);
16930         }
16931 }
16932
16933 /* Scan out the current hw modeset state,
16934  * and sanitizes it to the current state
16935  */
16936 static void
16937 intel_modeset_setup_hw_state(struct drm_device *dev)
16938 {
16939         struct drm_i915_private *dev_priv = to_i915(dev);
16940         enum pipe pipe;
16941         struct intel_crtc *crtc;
16942         struct intel_encoder *encoder;
16943         int i;
16944
16945         intel_modeset_readout_hw_state(dev);
16946
16947         /* HW state is read out, now we need to sanitize this mess. */
16948         for_each_intel_encoder(dev, encoder) {
16949                 intel_sanitize_encoder(encoder);
16950         }
16951
16952         for_each_pipe(dev_priv, pipe) {
16953                 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
16954
16955                 intel_sanitize_crtc(crtc);
16956                 intel_dump_pipe_config(crtc, crtc->config,
16957                                        "[setup_hw_state]");
16958         }
16959
16960         intel_modeset_update_connector_atomic_state(dev);
16961
16962         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
16963                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
16964
16965                 if (!pll->on || pll->active_mask)
16966                         continue;
16967
16968                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
16969
16970                 pll->funcs.disable(dev_priv, pll);
16971                 pll->on = false;
16972         }
16973
16974         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
16975                 vlv_wm_get_hw_state(dev);
16976         else if (IS_GEN9(dev_priv))
16977                 skl_wm_get_hw_state(dev);
16978         else if (HAS_PCH_SPLIT(dev_priv))
16979                 ilk_wm_get_hw_state(dev);
16980
16981         for_each_intel_crtc(dev, crtc) {
16982                 unsigned long put_domains;
16983
16984                 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
16985                 if (WARN_ON(put_domains))
16986                         modeset_put_power_domains(dev_priv, put_domains);
16987         }
16988         intel_display_set_init_power(dev_priv, false);
16989
16990         intel_fbc_init_pipe_state(dev_priv);
16991 }
16992
16993 void intel_display_resume(struct drm_device *dev)
16994 {
16995         struct drm_i915_private *dev_priv = to_i915(dev);
16996         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
16997         struct drm_modeset_acquire_ctx ctx;
16998         int ret;
16999
17000         dev_priv->modeset_restore_state = NULL;
17001         if (state)
17002                 state->acquire_ctx = &ctx;
17003
17004         /*
17005          * This is a cludge because with real atomic modeset mode_config.mutex
17006          * won't be taken. Unfortunately some probed state like
17007          * audio_codec_enable is still protected by mode_config.mutex, so lock
17008          * it here for now.
17009          */
17010         mutex_lock(&dev->mode_config.mutex);
17011         drm_modeset_acquire_init(&ctx, 0);
17012
17013         while (1) {
17014                 ret = drm_modeset_lock_all_ctx(dev, &ctx);
17015                 if (ret != -EDEADLK)
17016                         break;
17017
17018                 drm_modeset_backoff(&ctx);
17019         }
17020
17021         if (!ret)
17022                 ret = __intel_display_resume(dev, state);
17023
17024         drm_modeset_drop_locks(&ctx);
17025         drm_modeset_acquire_fini(&ctx);
17026         mutex_unlock(&dev->mode_config.mutex);
17027
17028         if (ret)
17029                 DRM_ERROR("Restoring old state failed with %i\n", ret);
17030         drm_atomic_state_put(state);
17031 }
17032
17033 void intel_modeset_gem_init(struct drm_device *dev)
17034 {
17035         struct drm_i915_private *dev_priv = to_i915(dev);
17036         struct drm_crtc *c;
17037         struct drm_i915_gem_object *obj;
17038
17039         intel_init_gt_powersave(dev_priv);
17040
17041         intel_modeset_init_hw(dev);
17042
17043         intel_setup_overlay(dev_priv);
17044
17045         /*
17046          * Make sure any fbs we allocated at startup are properly
17047          * pinned & fenced.  When we do the allocation it's too early
17048          * for this.
17049          */
17050         for_each_crtc(dev, c) {
17051                 struct i915_vma *vma;
17052
17053                 obj = intel_fb_obj(c->primary->fb);
17054                 if (obj == NULL)
17055                         continue;
17056
17057                 mutex_lock(&dev->struct_mutex);
17058                 vma = intel_pin_and_fence_fb_obj(c->primary->fb,
17059                                                  c->primary->state->rotation);
17060                 mutex_unlock(&dev->struct_mutex);
17061                 if (IS_ERR(vma)) {
17062                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
17063                                   to_intel_crtc(c)->pipe);
17064                         drm_framebuffer_unreference(c->primary->fb);
17065                         c->primary->fb = NULL;
17066                         c->primary->crtc = c->primary->state->crtc = NULL;
17067                         update_state_fb(c->primary);
17068                         c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
17069                 }
17070         }
17071 }
17072
17073 int intel_connector_register(struct drm_connector *connector)
17074 {
17075         struct intel_connector *intel_connector = to_intel_connector(connector);
17076         int ret;
17077
17078         ret = intel_backlight_device_register(intel_connector);
17079         if (ret)
17080                 goto err;
17081
17082         return 0;
17083
17084 err:
17085         return ret;
17086 }
17087
17088 void intel_connector_unregister(struct drm_connector *connector)
17089 {
17090         struct intel_connector *intel_connector = to_intel_connector(connector);
17091
17092         intel_backlight_device_unregister(intel_connector);
17093         intel_panel_destroy_backlight(connector);
17094 }
17095
17096 void intel_modeset_cleanup(struct drm_device *dev)
17097 {
17098         struct drm_i915_private *dev_priv = to_i915(dev);
17099
17100         intel_disable_gt_powersave(dev_priv);
17101
17102         /*
17103          * Interrupts and polling as the first thing to avoid creating havoc.
17104          * Too much stuff here (turning of connectors, ...) would
17105          * experience fancy races otherwise.
17106          */
17107         intel_irq_uninstall(dev_priv);
17108
17109         /*
17110          * Due to the hpd irq storm handling the hotplug work can re-arm the
17111          * poll handlers. Hence disable polling after hpd handling is shut down.
17112          */
17113         drm_kms_helper_poll_fini(dev);
17114
17115         intel_unregister_dsm_handler();
17116
17117         intel_fbc_global_disable(dev_priv);
17118
17119         /* flush any delayed tasks or pending work */
17120         flush_scheduled_work();
17121
17122         drm_mode_config_cleanup(dev);
17123
17124         intel_cleanup_overlay(dev_priv);
17125
17126         intel_cleanup_gt_powersave(dev_priv);
17127
17128         intel_teardown_gmbus(dev);
17129 }
17130
17131 void intel_connector_attach_encoder(struct intel_connector *connector,
17132                                     struct intel_encoder *encoder)
17133 {
17134         connector->encoder = encoder;
17135         drm_mode_connector_attach_encoder(&connector->base,
17136                                           &encoder->base);
17137 }
17138
17139 /*
17140  * set vga decode state - true == enable VGA decode
17141  */
17142 int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state)
17143 {
17144         unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
17145         u16 gmch_ctrl;
17146
17147         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
17148                 DRM_ERROR("failed to read control word\n");
17149                 return -EIO;
17150         }
17151
17152         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
17153                 return 0;
17154
17155         if (state)
17156                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
17157         else
17158                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
17159
17160         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
17161                 DRM_ERROR("failed to write control word\n");
17162                 return -EIO;
17163         }
17164
17165         return 0;
17166 }
17167
17168 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
17169
17170 struct intel_display_error_state {
17171
17172         u32 power_well_driver;
17173
17174         int num_transcoders;
17175
17176         struct intel_cursor_error_state {
17177                 u32 control;
17178                 u32 position;
17179                 u32 base;
17180                 u32 size;
17181         } cursor[I915_MAX_PIPES];
17182
17183         struct intel_pipe_error_state {
17184                 bool power_domain_on;
17185                 u32 source;
17186                 u32 stat;
17187         } pipe[I915_MAX_PIPES];
17188
17189         struct intel_plane_error_state {
17190                 u32 control;
17191                 u32 stride;
17192                 u32 size;
17193                 u32 pos;
17194                 u32 addr;
17195                 u32 surface;
17196                 u32 tile_offset;
17197         } plane[I915_MAX_PIPES];
17198
17199         struct intel_transcoder_error_state {
17200                 bool power_domain_on;
17201                 enum transcoder cpu_transcoder;
17202
17203                 u32 conf;
17204
17205                 u32 htotal;
17206                 u32 hblank;
17207                 u32 hsync;
17208                 u32 vtotal;
17209                 u32 vblank;
17210                 u32 vsync;
17211         } transcoder[4];
17212 };
17213
17214 struct intel_display_error_state *
17215 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
17216 {
17217         struct intel_display_error_state *error;
17218         int transcoders[] = {
17219                 TRANSCODER_A,
17220                 TRANSCODER_B,
17221                 TRANSCODER_C,
17222                 TRANSCODER_EDP,
17223         };
17224         int i;
17225
17226         if (INTEL_INFO(dev_priv)->num_pipes == 0)
17227                 return NULL;
17228
17229         error = kzalloc(sizeof(*error), GFP_ATOMIC);
17230         if (error == NULL)
17231                 return NULL;
17232
17233         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
17234                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
17235
17236         for_each_pipe(dev_priv, i) {
17237                 error->pipe[i].power_domain_on =
17238                         __intel_display_power_is_enabled(dev_priv,
17239                                                          POWER_DOMAIN_PIPE(i));
17240                 if (!error->pipe[i].power_domain_on)
17241                         continue;
17242
17243                 error->cursor[i].control = I915_READ(CURCNTR(i));
17244                 error->cursor[i].position = I915_READ(CURPOS(i));
17245                 error->cursor[i].base = I915_READ(CURBASE(i));
17246
17247                 error->plane[i].control = I915_READ(DSPCNTR(i));
17248                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
17249                 if (INTEL_GEN(dev_priv) <= 3) {
17250                         error->plane[i].size = I915_READ(DSPSIZE(i));
17251                         error->plane[i].pos = I915_READ(DSPPOS(i));
17252                 }
17253                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
17254                         error->plane[i].addr = I915_READ(DSPADDR(i));
17255                 if (INTEL_GEN(dev_priv) >= 4) {
17256                         error->plane[i].surface = I915_READ(DSPSURF(i));
17257                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
17258                 }
17259
17260                 error->pipe[i].source = I915_READ(PIPESRC(i));
17261
17262                 if (HAS_GMCH_DISPLAY(dev_priv))
17263                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
17264         }
17265
17266         /* Note: this does not include DSI transcoders. */
17267         error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
17268         if (HAS_DDI(dev_priv))
17269                 error->num_transcoders++; /* Account for eDP. */
17270
17271         for (i = 0; i < error->num_transcoders; i++) {
17272                 enum transcoder cpu_transcoder = transcoders[i];
17273
17274                 error->transcoder[i].power_domain_on =
17275                         __intel_display_power_is_enabled(dev_priv,
17276                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
17277                 if (!error->transcoder[i].power_domain_on)
17278                         continue;
17279
17280                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
17281
17282                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
17283                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
17284                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
17285                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
17286                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
17287                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
17288                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
17289         }
17290
17291         return error;
17292 }
17293
17294 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
17295
17296 void
17297 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
17298                                 struct drm_i915_private *dev_priv,
17299                                 struct intel_display_error_state *error)
17300 {
17301         int i;
17302
17303         if (!error)
17304                 return;
17305
17306         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes);
17307         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
17308                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
17309                            error->power_well_driver);
17310         for_each_pipe(dev_priv, i) {
17311                 err_printf(m, "Pipe [%d]:\n", i);
17312                 err_printf(m, "  Power: %s\n",
17313                            onoff(error->pipe[i].power_domain_on));
17314                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
17315                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
17316
17317                 err_printf(m, "Plane [%d]:\n", i);
17318                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
17319                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
17320                 if (INTEL_GEN(dev_priv) <= 3) {
17321                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
17322                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
17323                 }
17324                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
17325                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
17326                 if (INTEL_GEN(dev_priv) >= 4) {
17327                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
17328                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
17329                 }
17330
17331                 err_printf(m, "Cursor [%d]:\n", i);
17332                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
17333                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
17334                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
17335         }
17336
17337         for (i = 0; i < error->num_transcoders; i++) {
17338                 err_printf(m, "CPU transcoder: %s\n",
17339                            transcoder_name(error->transcoder[i].cpu_transcoder));
17340                 err_printf(m, "  Power: %s\n",
17341                            onoff(error->transcoder[i].power_domain_on));
17342                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
17343                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
17344                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
17345                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
17346                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
17347                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
17348                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
17349         }
17350 }
17351
17352 #endif