drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include "intel_frontbuffer.h"
  38 #include <drm/i915_drm.h>
  39 #include "i915_drv.h"
  40 #include "intel_dsi.h"
  41 #include "i915_trace.h"
  42 #include <drm/drm_atomic.h>
  43 #include <drm/drm_atomic_helper.h>
  44 #include <drm/drm_dp_helper.h>
  45 #include <drm/drm_crtc_helper.h>
  46 #include <drm/drm_plane_helper.h>
  47 #include <drm/drm_rect.h>
  48 #include <linux/dma_remapping.h>
  49 #include <linux/reservation.h>
  50
  51 static bool is_mmio_work(struct intel_flip_work *work)
  52 {
  53         return work->mmio_work.func;
  54 }
  55
  56 /* Primary plane formats for gen <= 3 */
  57 static const uint32_t i8xx_primary_formats[] = {
  58         DRM_FORMAT_C8,
  59         DRM_FORMAT_RGB565,
  60         DRM_FORMAT_XRGB1555,
  61         DRM_FORMAT_XRGB8888,
  62 };
  63
  64 /* Primary plane formats for gen >= 4 */
  65 static const uint32_t i965_primary_formats[] = {
  66         DRM_FORMAT_C8,
  67         DRM_FORMAT_RGB565,
  68         DRM_FORMAT_XRGB8888,
  69         DRM_FORMAT_XBGR8888,
  70         DRM_FORMAT_XRGB2101010,
  71         DRM_FORMAT_XBGR2101010,
  72 };
  73
  74 static const uint32_t skl_primary_formats[] = {
  75         DRM_FORMAT_C8,
  76         DRM_FORMAT_RGB565,
  77         DRM_FORMAT_XRGB8888,
  78         DRM_FORMAT_XBGR8888,
  79         DRM_FORMAT_ARGB8888,
  80         DRM_FORMAT_ABGR8888,
  81         DRM_FORMAT_XRGB2101010,
  82         DRM_FORMAT_XBGR2101010,
  83         DRM_FORMAT_YUYV,
  84         DRM_FORMAT_YVYU,
  85         DRM_FORMAT_UYVY,
  86         DRM_FORMAT_VYUY,
  87 };
  88
  89 /* Cursor formats */
  90 static const uint32_t intel_cursor_formats[] = {
  91         DRM_FORMAT_ARGB8888,
  92 };
  93
  94 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  95                                 struct intel_crtc_state *pipe_config);
  96 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  97                                    struct intel_crtc_state *pipe_config);
  98
  99 static int intel_framebuffer_init(struct drm_device *dev,
 100                                   struct intel_framebuffer *ifb,
 101                                   struct drm_mode_fb_cmd2 *mode_cmd,
 102                                   struct drm_i915_gem_object *obj);
 103 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
 104 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
 105 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
 106 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
 107                                          struct intel_link_m_n *m_n,
 108                                          struct intel_link_m_n *m2_n2);
 109 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 110 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 111 static void haswell_set_pipemisc(struct drm_crtc *crtc);
 112 static void vlv_prepare_pll(struct intel_crtc *crtc,
 113                             const struct intel_crtc_state *pipe_config);
 114 static void chv_prepare_pll(struct intel_crtc *crtc,
 115                             const struct intel_crtc_state *pipe_config);
 116 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 117 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 118 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
 119                                     struct intel_crtc_state *crtc_state);
 120 static void skylake_pfit_enable(struct intel_crtc *crtc);
 121 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
 122 static void ironlake_pfit_enable(struct intel_crtc *crtc);
 123 static void intel_modeset_setup_hw_state(struct drm_device *dev);
 124 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
 125 static int ilk_max_pixel_rate(struct drm_atomic_state *state);
 126 static int glk_calc_cdclk(int max_pixclk);
 127 static int bxt_calc_cdclk(int max_pixclk);
 128
 129 struct intel_limit {
 130         struct {
 131                 int min, max;
 132         } dot, vco, n, m, m1, m2, p, p1;
 133
 134         struct {
 135                 int dot_limit;
 136                 int p2_slow, p2_fast;
 137         } p2;
 138 };
 139
 140 /* returns HPLL frequency in kHz */
 141 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
 142 {
 143         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 144
 145         /* Obtain SKU information */
 146         mutex_lock(&dev_priv->sb_lock);
 147         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 148                 CCK_FUSE_HPLL_FREQ_MASK;
 149         mutex_unlock(&dev_priv->sb_lock);
 150
 151         return vco_freq[hpll_freq] * 1000;
 152 }
 153
 154 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
 155                       const char *name, u32 reg, int ref_freq)
 156 {
 157         u32 val;
 158         int divider;
 159
 160         mutex_lock(&dev_priv->sb_lock);
 161         val = vlv_cck_read(dev_priv, reg);
 162         mutex_unlock(&dev_priv->sb_lock);
 163
 164         divider = val & CCK_FREQUENCY_VALUES;
 165
 166         WARN((val & CCK_FREQUENCY_STATUS) !=
 167              (divider << CCK_FREQUENCY_STATUS_SHIFT),
 168              "%s change in progress\n", name);
 169
 170         return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
 171 }
 172
 173 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 174                                   const char *name, u32 reg)
 175 {
 176         if (dev_priv->hpll_freq == 0)
 177                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
 178
 179         return vlv_get_cck_clock(dev_priv, name, reg,
 180                                  dev_priv->hpll_freq);
 181 }
 182
 183 static int
 184 intel_pch_rawclk(struct drm_i915_private *dev_priv)
 185 {
 186         return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
 187 }
 188
 189 static int
 190 intel_vlv_hrawclk(struct drm_i915_private *dev_priv)
 191 {
 192         /* RAWCLK_FREQ_VLV register updated from power well code */
 193         return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
 194                                       CCK_DISPLAY_REF_CLOCK_CONTROL);
 195 }
 196
 197 static int
 198 intel_g4x_hrawclk(struct drm_i915_private *dev_priv)
 199 {
 200         uint32_t clkcfg;
 201
 202         /* hrawclock is 1/4 the FSB frequency */
 203         clkcfg = I915_READ(CLKCFG);
 204         switch (clkcfg & CLKCFG_FSB_MASK) {
 205         case CLKCFG_FSB_400:
 206                 return 100000;
 207         case CLKCFG_FSB_533:
 208                 return 133333;
 209         case CLKCFG_FSB_667:
 210                 return 166667;
 211         case CLKCFG_FSB_800:
 212                 return 200000;
 213         case CLKCFG_FSB_1067:
 214                 return 266667;
 215         case CLKCFG_FSB_1333:
 216                 return 333333;
 217         /* these two are just a guess; one of them might be right */
 218         case CLKCFG_FSB_1600:
 219         case CLKCFG_FSB_1600_ALT:
 220                 return 400000;
 221         default:
 222                 return 133333;
 223         }
 224 }
 225
 226 void intel_update_rawclk(struct drm_i915_private *dev_priv)
 227 {
 228         if (HAS_PCH_SPLIT(dev_priv))
 229                 dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv);
 230         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 231                 dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv);
 232         else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
 233                 dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv);
 234         else
 235                 return; /* no rawclk on other platforms, or no need to know it */
 236
 237         DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
 238 }
 239
 240 static void intel_update_czclk(struct drm_i915_private *dev_priv)
 241 {
 242         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
 243                 return;
 244
 245         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 246                                                       CCK_CZ_CLOCK_CONTROL);
 247
 248         DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
 249 }
 250
 251 static inline u32 /* units of 100MHz */
 252 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
 253                     const struct intel_crtc_state *pipe_config)
 254 {
 255         if (HAS_DDI(dev_priv))
 256                 return pipe_config->port_clock; /* SPLL */
 257         else if (IS_GEN5(dev_priv))
 258                 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
 259         else
 260                 return 270000;
 261 }
 262
 263 static const struct intel_limit intel_limits_i8xx_dac = {
 264         .dot = { .min = 25000, .max = 350000 },
 265         .vco = { .min = 908000, .max = 1512000 },
 266         .n = { .min = 2, .max = 16 },
 267         .m = { .min = 96, .max = 140 },
 268         .m1 = { .min = 18, .max = 26 },
 269         .m2 = { .min = 6, .max = 16 },
 270         .p = { .min = 4, .max = 128 },
 271         .p1 = { .min = 2, .max = 33 },
 272         .p2 = { .dot_limit = 165000,
 273                 .p2_slow = 4, .p2_fast = 2 },
 274 };
 275
 276 static const struct intel_limit intel_limits_i8xx_dvo = {
 277         .dot = { .min = 25000, .max = 350000 },
 278         .vco = { .min = 908000, .max = 1512000 },
 279         .n = { .min = 2, .max = 16 },
 280         .m = { .min = 96, .max = 140 },
 281         .m1 = { .min = 18, .max = 26 },
 282         .m2 = { .min = 6, .max = 16 },
 283         .p = { .min = 4, .max = 128 },
 284         .p1 = { .min = 2, .max = 33 },
 285         .p2 = { .dot_limit = 165000,
 286                 .p2_slow = 4, .p2_fast = 4 },
 287 };
 288
 289 static const struct intel_limit intel_limits_i8xx_lvds = {
 290         .dot = { .min = 25000, .max = 350000 },
 291         .vco = { .min = 908000, .max = 1512000 },
 292         .n = { .min = 2, .max = 16 },
 293         .m = { .min = 96, .max = 140 },
 294         .m1 = { .min = 18, .max = 26 },
 295         .m2 = { .min = 6, .max = 16 },
 296         .p = { .min = 4, .max = 128 },
 297         .p1 = { .min = 1, .max = 6 },
 298         .p2 = { .dot_limit = 165000,
 299                 .p2_slow = 14, .p2_fast = 7 },
 300 };
 301
 302 static const struct intel_limit intel_limits_i9xx_sdvo = {
 303         .dot = { .min = 20000, .max = 400000 },
 304         .vco = { .min = 1400000, .max = 2800000 },
 305         .n = { .min = 1, .max = 6 },
 306         .m = { .min = 70, .max = 120 },
 307         .m1 = { .min = 8, .max = 18 },
 308         .m2 = { .min = 3, .max = 7 },
 309         .p = { .min = 5, .max = 80 },
 310         .p1 = { .min = 1, .max = 8 },
 311         .p2 = { .dot_limit = 200000,
 312                 .p2_slow = 10, .p2_fast = 5 },
 313 };
 314
 315 static const struct intel_limit intel_limits_i9xx_lvds = {
 316         .dot = { .min = 20000, .max = 400000 },
 317         .vco = { .min = 1400000, .max = 2800000 },
 318         .n = { .min = 1, .max = 6 },
 319         .m = { .min = 70, .max = 120 },
 320         .m1 = { .min = 8, .max = 18 },
 321         .m2 = { .min = 3, .max = 7 },
 322         .p = { .min = 7, .max = 98 },
 323         .p1 = { .min = 1, .max = 8 },
 324         .p2 = { .dot_limit = 112000,
 325                 .p2_slow = 14, .p2_fast = 7 },
 326 };
 327
 328
 329 static const struct intel_limit intel_limits_g4x_sdvo = {
 330         .dot = { .min = 25000, .max = 270000 },
 331         .vco = { .min = 1750000, .max = 3500000},
 332         .n = { .min = 1, .max = 4 },
 333         .m = { .min = 104, .max = 138 },
 334         .m1 = { .min = 17, .max = 23 },
 335         .m2 = { .min = 5, .max = 11 },
 336         .p = { .min = 10, .max = 30 },
 337         .p1 = { .min = 1, .max = 3},
 338         .p2 = { .dot_limit = 270000,
 339                 .p2_slow = 10,
 340                 .p2_fast = 10
 341         },
 342 };
 343
 344 static const struct intel_limit intel_limits_g4x_hdmi = {
 345         .dot = { .min = 22000, .max = 400000 },
 346         .vco = { .min = 1750000, .max = 3500000},
 347         .n = { .min = 1, .max = 4 },
 348         .m = { .min = 104, .max = 138 },
 349         .m1 = { .min = 16, .max = 23 },
 350         .m2 = { .min = 5, .max = 11 },
 351         .p = { .min = 5, .max = 80 },
 352         .p1 = { .min = 1, .max = 8},
 353         .p2 = { .dot_limit = 165000,
 354                 .p2_slow = 10, .p2_fast = 5 },
 355 };
 356
 357 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
 358         .dot = { .min = 20000, .max = 115000 },
 359         .vco = { .min = 1750000, .max = 3500000 },
 360         .n = { .min = 1, .max = 3 },
 361         .m = { .min = 104, .max = 138 },
 362         .m1 = { .min = 17, .max = 23 },
 363         .m2 = { .min = 5, .max = 11 },
 364         .p = { .min = 28, .max = 112 },
 365         .p1 = { .min = 2, .max = 8 },
 366         .p2 = { .dot_limit = 0,
 367                 .p2_slow = 14, .p2_fast = 14
 368         },
 369 };
 370
 371 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
 372         .dot = { .min = 80000, .max = 224000 },
 373         .vco = { .min = 1750000, .max = 3500000 },
 374         .n = { .min = 1, .max = 3 },
 375         .m = { .min = 104, .max = 138 },
 376         .m1 = { .min = 17, .max = 23 },
 377         .m2 = { .min = 5, .max = 11 },
 378         .p = { .min = 14, .max = 42 },
 379         .p1 = { .min = 2, .max = 6 },
 380         .p2 = { .dot_limit = 0,
 381                 .p2_slow = 7, .p2_fast = 7
 382         },
 383 };
 384
 385 static const struct intel_limit intel_limits_pineview_sdvo = {
 386         .dot = { .min = 20000, .max = 400000},
 387         .vco = { .min = 1700000, .max = 3500000 },
 388         /* Pineview's Ncounter is a ring counter */
 389         .n = { .min = 3, .max = 6 },
 390         .m = { .min = 2, .max = 256 },
 391         /* Pineview only has one combined m divider, which we treat as m2. */
 392         .m1 = { .min = 0, .max = 0 },
 393         .m2 = { .min = 0, .max = 254 },
 394         .p = { .min = 5, .max = 80 },
 395         .p1 = { .min = 1, .max = 8 },
 396         .p2 = { .dot_limit = 200000,
 397                 .p2_slow = 10, .p2_fast = 5 },
 398 };
 399
 400 static const struct intel_limit intel_limits_pineview_lvds = {
 401         .dot = { .min = 20000, .max = 400000 },
 402         .vco = { .min = 1700000, .max = 3500000 },
 403         .n = { .min = 3, .max = 6 },
 404         .m = { .min = 2, .max = 256 },
 405         .m1 = { .min = 0, .max = 0 },
 406         .m2 = { .min = 0, .max = 254 },
 407         .p = { .min = 7, .max = 112 },
 408         .p1 = { .min = 1, .max = 8 },
 409         .p2 = { .dot_limit = 112000,
 410                 .p2_slow = 14, .p2_fast = 14 },
 411 };
 412
 413 /* Ironlake / Sandybridge
 414  *
 415  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 416  * the range value for them is (actual_value - 2).
 417  */
 418 static const struct intel_limit intel_limits_ironlake_dac = {
 419         .dot = { .min = 25000, .max = 350000 },
 420         .vco = { .min = 1760000, .max = 3510000 },
 421         .n = { .min = 1, .max = 5 },
 422         .m = { .min = 79, .max = 127 },
 423         .m1 = { .min = 12, .max = 22 },
 424         .m2 = { .min = 5, .max = 9 },
 425         .p = { .min = 5, .max = 80 },
 426         .p1 = { .min = 1, .max = 8 },
 427         .p2 = { .dot_limit = 225000,
 428                 .p2_slow = 10, .p2_fast = 5 },
 429 };
 430
 431 static const struct intel_limit intel_limits_ironlake_single_lvds = {
 432         .dot = { .min = 25000, .max = 350000 },
 433         .vco = { .min = 1760000, .max = 3510000 },
 434         .n = { .min = 1, .max = 3 },
 435         .m = { .min = 79, .max = 118 },
 436         .m1 = { .min = 12, .max = 22 },
 437         .m2 = { .min = 5, .max = 9 },
 438         .p = { .min = 28, .max = 112 },
 439         .p1 = { .min = 2, .max = 8 },
 440         .p2 = { .dot_limit = 225000,
 441                 .p2_slow = 14, .p2_fast = 14 },
 442 };
 443
 444 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
 445         .dot = { .min = 25000, .max = 350000 },
 446         .vco = { .min = 1760000, .max = 3510000 },
 447         .n = { .min = 1, .max = 3 },
 448         .m = { .min = 79, .max = 127 },
 449         .m1 = { .min = 12, .max = 22 },
 450         .m2 = { .min = 5, .max = 9 },
 451         .p = { .min = 14, .max = 56 },
 452         .p1 = { .min = 2, .max = 8 },
 453         .p2 = { .dot_limit = 225000,
 454                 .p2_slow = 7, .p2_fast = 7 },
 455 };
 456
 457 /* LVDS 100mhz refclk limits. */
 458 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
 459         .dot = { .min = 25000, .max = 350000 },
 460         .vco = { .min = 1760000, .max = 3510000 },
 461         .n = { .min = 1, .max = 2 },
 462         .m = { .min = 79, .max = 126 },
 463         .m1 = { .min = 12, .max = 22 },
 464         .m2 = { .min = 5, .max = 9 },
 465         .p = { .min = 28, .max = 112 },
 466         .p1 = { .min = 2, .max = 8 },
 467         .p2 = { .dot_limit = 225000,
 468                 .p2_slow = 14, .p2_fast = 14 },
 469 };
 470
 471 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
 472         .dot = { .min = 25000, .max = 350000 },
 473         .vco = { .min = 1760000, .max = 3510000 },
 474         .n = { .min = 1, .max = 3 },
 475         .m = { .min = 79, .max = 126 },
 476         .m1 = { .min = 12, .max = 22 },
 477         .m2 = { .min = 5, .max = 9 },
 478         .p = { .min = 14, .max = 42 },
 479         .p1 = { .min = 2, .max = 6 },
 480         .p2 = { .dot_limit = 225000,
 481                 .p2_slow = 7, .p2_fast = 7 },
 482 };
 483
 484 static const struct intel_limit intel_limits_vlv = {
 485          /*
 486           * These are the data rate limits (measured in fast clocks)
 487           * since those are the strictest limits we have. The fast
 488           * clock and actual rate limits are more relaxed, so checking
 489           * them would make no difference.
 490           */
 491         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 492         .vco = { .min = 4000000, .max = 6000000 },
 493         .n = { .min = 1, .max = 7 },
 494         .m1 = { .min = 2, .max = 3 },
 495         .m2 = { .min = 11, .max = 156 },
 496         .p1 = { .min = 2, .max = 3 },
 497         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 498 };
 499
 500 static const struct intel_limit intel_limits_chv = {
 501         /*
 502          * These are the data rate limits (measured in fast clocks)
 503          * since those are the strictest limits we have.  The fast
 504          * clock and actual rate limits are more relaxed, so checking
 505          * them would make no difference.
 506          */
 507         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 508         .vco = { .min = 4800000, .max = 6480000 },
 509         .n = { .min = 1, .max = 1 },
 510         .m1 = { .min = 2, .max = 2 },
 511         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 512         .p1 = { .min = 2, .max = 4 },
 513         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 514 };
 515
 516 static const struct intel_limit intel_limits_bxt = {
 517         /* FIXME: find real dot limits */
 518         .dot = { .min = 0, .max = INT_MAX },
 519         .vco = { .min = 4800000, .max = 6700000 },
 520         .n = { .min = 1, .max = 1 },
 521         .m1 = { .min = 2, .max = 2 },
 522         /* FIXME: find real m2 limits */
 523         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 524         .p1 = { .min = 2, .max = 4 },
 525         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 526 };
 527
 528 static bool
 529 needs_modeset(struct drm_crtc_state *state)
 530 {
 531         return drm_atomic_crtc_needs_modeset(state);
 532 }
 533
 534 /*
 535  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 536  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 537  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 538  * The helpers' return value is the rate of the clock that is fed to the
 539  * display engine's pipe which can be the above fast dot clock rate or a
 540  * divided-down version of it.
 541  */
 542 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 543 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
 544 {
 545         clock->m = clock->m2 + 2;
 546         clock->p = clock->p1 * clock->p2;
 547         if (WARN_ON(clock->n == 0 || clock->p == 0))
 548                 return 0;
 549         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 550         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 551
 552         return clock->dot;
 553 }
 554
 555 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 556 {
 557         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 558 }
 559
 560 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
 561 {
 562         clock->m = i9xx_dpll_compute_m(clock);
 563         clock->p = clock->p1 * clock->p2;
 564         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 565                 return 0;
 566         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 567         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 568
 569         return clock->dot;
 570 }
 571
 572 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
 573 {
 574         clock->m = clock->m1 * clock->m2;
 575         clock->p = clock->p1 * clock->p2;
 576         if (WARN_ON(clock->n == 0 || clock->p == 0))
 577                 return 0;
 578         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 579         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 580
 581         return clock->dot / 5;
 582 }
 583
 584 int chv_calc_dpll_params(int refclk, struct dpll *clock)
 585 {
 586         clock->m = clock->m1 * clock->m2;
 587         clock->p = clock->p1 * clock->p2;
 588         if (WARN_ON(clock->n == 0 || clock->p == 0))
 589                 return 0;
 590         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 591                         clock->n << 22);
 592         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 593
 594         return clock->dot / 5;
 595 }
 596
 597 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 598 /**
 599  * Returns whether the given set of divisors are valid for a given refclk with
 600  * the given connectors.
 601  */
 602
 603 static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
 604                                const struct intel_limit *limit,
 605                                const struct dpll *clock)
 606 {
 607         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 608                 INTELPllInvalid("n out of range\n");
 609         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 610                 INTELPllInvalid("p1 out of range\n");
 611         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 612                 INTELPllInvalid("m2 out of range\n");
 613         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 614                 INTELPllInvalid("m1 out of range\n");
 615
 616         if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
 617             !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
 618                 if (clock->m1 <= clock->m2)
 619                         INTELPllInvalid("m1 <= m2\n");
 620
 621         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
 622             !IS_GEN9_LP(dev_priv)) {
 623                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 624                         INTELPllInvalid("p out of range\n");
 625                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 626                         INTELPllInvalid("m out of range\n");
 627         }
 628
 629         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 630                 INTELPllInvalid("vco out of range\n");
 631         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 632          * connector, etc., rather than just a single range.
 633          */
 634         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 635                 INTELPllInvalid("dot out of range\n");
 636
 637         return true;
 638 }
 639
 640 static int
 641 i9xx_select_p2_div(const struct intel_limit *limit,
 642                    const struct intel_crtc_state *crtc_state,
 643                    int target)
 644 {
 645         struct drm_device *dev = crtc_state->base.crtc->dev;
 646
 647         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 648                 /*
 649                  * For LVDS just rely on its current settings for dual-channel.
 650                  * We haven't figured out how to reliably set up different
 651                  * single/dual channel state, if we even can.
 652                  */
 653                 if (intel_is_dual_link_lvds(dev))
 654                         return limit->p2.p2_fast;
 655                 else
 656                         return limit->p2.p2_slow;
 657         } else {
 658                 if (target < limit->p2.dot_limit)
 659                         return limit->p2.p2_slow;
 660                 else
 661                         return limit->p2.p2_fast;
 662         }
 663 }
 664
 665 /*
 666  * Returns a set of divisors for the desired target clock with the given
 667  * refclk, or FALSE.  The returned values represent the clock equation:
 668  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 669  *
 670  * Target and reference clocks are specified in kHz.
 671  *
 672  * If match_clock is provided, then best_clock P divider must match the P
 673  * divider from @match_clock used for LVDS downclocking.
 674  */
 675 static bool
 676 i9xx_find_best_dpll(const struct intel_limit *limit,
 677                     struct intel_crtc_state *crtc_state,
 678                     int target, int refclk, struct dpll *match_clock,
 679                     struct dpll *best_clock)
 680 {
 681         struct drm_device *dev = crtc_state->base.crtc->dev;
 682         struct dpll clock;
 683         int err = target;
 684
 685         memset(best_clock, 0, sizeof(*best_clock));
 686
 687         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 688
 689         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 690              clock.m1++) {
 691                 for (clock.m2 = limit->m2.min;
 692                      clock.m2 <= limit->m2.max; clock.m2++) {
 693                         if (clock.m2 >= clock.m1)
 694                                 break;
 695                         for (clock.n = limit->n.min;
 696                              clock.n <= limit->n.max; clock.n++) {
 697                                 for (clock.p1 = limit->p1.min;
 698                                         clock.p1 <= limit->p1.max; clock.p1++) {
 699                                         int this_err;
 700
 701                                         i9xx_calc_dpll_params(refclk, &clock);
 702                                         if (!intel_PLL_is_valid(to_i915(dev),
 703                                                                 limit,
 704                                                                 &clock))
 705                                                 continue;
 706                                         if (match_clock &&
 707                                             clock.p != match_clock->p)
 708                                                 continue;
 709
 710                                         this_err = abs(clock.dot - target);
 711                                         if (this_err < err) {
 712                                                 *best_clock = clock;
 713                                                 err = this_err;
 714                                         }
 715                                 }
 716                         }
 717                 }
 718         }
 719
 720         return (err != target);
 721 }
 722
 723 /*
 724  * Returns a set of divisors for the desired target clock with the given
 725  * refclk, or FALSE.  The returned values represent the clock equation:
 726  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 727  *
 728  * Target and reference clocks are specified in kHz.
 729  *
 730  * If match_clock is provided, then best_clock P divider must match the P
 731  * divider from @match_clock used for LVDS downclocking.
 732  */
 733 static bool
 734 pnv_find_best_dpll(const struct intel_limit *limit,
 735                    struct intel_crtc_state *crtc_state,
 736                    int target, int refclk, struct dpll *match_clock,
 737                    struct dpll *best_clock)
 738 {
 739         struct drm_device *dev = crtc_state->base.crtc->dev;
 740         struct dpll clock;
 741         int err = target;
 742
 743         memset(best_clock, 0, sizeof(*best_clock));
 744
 745         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 746
 747         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 748              clock.m1++) {
 749                 for (clock.m2 = limit->m2.min;
 750                      clock.m2 <= limit->m2.max; clock.m2++) {
 751                         for (clock.n = limit->n.min;
 752                              clock.n <= limit->n.max; clock.n++) {
 753                                 for (clock.p1 = limit->p1.min;
 754                                         clock.p1 <= limit->p1.max; clock.p1++) {
 755                                         int this_err;
 756
 757                                         pnv_calc_dpll_params(refclk, &clock);
 758                                         if (!intel_PLL_is_valid(to_i915(dev),
 759                                                                 limit,
 760                                                                 &clock))
 761                                                 continue;
 762                                         if (match_clock &&
 763                                             clock.p != match_clock->p)
 764                                                 continue;
 765
 766                                         this_err = abs(clock.dot - target);
 767                                         if (this_err < err) {
 768                                                 *best_clock = clock;
 769                                                 err = this_err;
 770                                         }
 771                                 }
 772                         }
 773                 }
 774         }
 775
 776         return (err != target);
 777 }
 778
 779 /*
 780  * Returns a set of divisors for the desired target clock with the given
 781  * refclk, or FALSE.  The returned values represent the clock equation:
 782  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 783  *
 784  * Target and reference clocks are specified in kHz.
 785  *
 786  * If match_clock is provided, then best_clock P divider must match the P
 787  * divider from @match_clock used for LVDS downclocking.
 788  */
 789 static bool
 790 g4x_find_best_dpll(const struct intel_limit *limit,
 791                    struct intel_crtc_state *crtc_state,
 792                    int target, int refclk, struct dpll *match_clock,
 793                    struct dpll *best_clock)
 794 {
 795         struct drm_device *dev = crtc_state->base.crtc->dev;
 796         struct dpll clock;
 797         int max_n;
 798         bool found = false;
 799         /* approximately equals target * 0.00585 */
 800         int err_most = (target >> 8) + (target >> 9);
 801
 802         memset(best_clock, 0, sizeof(*best_clock));
 803
 804         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 805
 806         max_n = limit->n.max;
 807         /* based on hardware requirement, prefer smaller n to precision */
 808         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 809                 /* based on hardware requirement, prefere larger m1,m2 */
 810                 for (clock.m1 = limit->m1.max;
 811                      clock.m1 >= limit->m1.min; clock.m1--) {
 812                         for (clock.m2 = limit->m2.max;
 813                              clock.m2 >= limit->m2.min; clock.m2--) {
 814                                 for (clock.p1 = limit->p1.max;
 815                                      clock.p1 >= limit->p1.min; clock.p1--) {
 816                                         int this_err;
 817
 818                                         i9xx_calc_dpll_params(refclk, &clock);
 819                                         if (!intel_PLL_is_valid(to_i915(dev),
 820                                                                 limit,
 821                                                                 &clock))
 822                                                 continue;
 823
 824                                         this_err = abs(clock.dot - target);
 825                                         if (this_err < err_most) {
 826                                                 *best_clock = clock;
 827                                                 err_most = this_err;
 828                                                 max_n = clock.n;
 829                                                 found = true;
 830                                         }
 831                                 }
 832                         }
 833                 }
 834         }
 835         return found;
 836 }
 837
 838 /*
 839  * Check if the calculated PLL configuration is more optimal compared to the
 840  * best configuration and error found so far. Return the calculated error.
 841  */
 842 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 843                                const struct dpll *calculated_clock,
 844                                const struct dpll *best_clock,
 845                                unsigned int best_error_ppm,
 846                                unsigned int *error_ppm)
 847 {
 848         /*
 849          * For CHV ignore the error and consider only the P value.
 850          * Prefer a bigger P value based on HW requirements.
 851          */
 852         if (IS_CHERRYVIEW(to_i915(dev))) {
 853                 *error_ppm = 0;
 854
 855                 return calculated_clock->p > best_clock->p;
 856         }
 857
 858         if (WARN_ON_ONCE(!target_freq))
 859                 return false;
 860
 861         *error_ppm = div_u64(1000000ULL *
 862                                 abs(target_freq - calculated_clock->dot),
 863                              target_freq);
 864         /*
 865          * Prefer a better P value over a better (smaller) error if the error
 866          * is small. Ensure this preference for future configurations too by
 867          * setting the error to 0.
 868          */
 869         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 870                 *error_ppm = 0;
 871
 872                 return true;
 873         }
 874
 875         return *error_ppm + 10 < best_error_ppm;
 876 }
 877
 878 /*
 879  * Returns a set of divisors for the desired target clock with the given
 880  * refclk, or FALSE.  The returned values represent the clock equation:
 881  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 882  */
 883 static bool
 884 vlv_find_best_dpll(const struct intel_limit *limit,
 885                    struct intel_crtc_state *crtc_state,
 886                    int target, int refclk, struct dpll *match_clock,
 887                    struct dpll *best_clock)
 888 {
 889         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 890         struct drm_device *dev = crtc->base.dev;
 891         struct dpll clock;
 892         unsigned int bestppm = 1000000;
 893         /* min update 19.2 MHz */
 894         int max_n = min(limit->n.max, refclk / 19200);
 895         bool found = false;
 896
 897         target *= 5; /* fast clock */
 898
 899         memset(best_clock, 0, sizeof(*best_clock));
 900
 901         /* based on hardware requirement, prefer smaller n to precision */
 902         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 903                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 904                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 905                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 906                                 clock.p = clock.p1 * clock.p2;
 907                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 908                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 909                                         unsigned int ppm;
 910
 911                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 912                                                                      refclk * clock.m1);
 913
 914                                         vlv_calc_dpll_params(refclk, &clock);
 915
 916                                         if (!intel_PLL_is_valid(to_i915(dev),
 917                                                                 limit,
 918                                                                 &clock))
 919                                                 continue;
 920
 921                                         if (!vlv_PLL_is_optimal(dev, target,
 922                                                                 &clock,
 923                                                                 best_clock,
 924                                                                 bestppm, &ppm))
 925                                                 continue;
 926
 927                                         *best_clock = clock;
 928                                         bestppm = ppm;
 929                                         found = true;
 930                                 }
 931                         }
 932                 }
 933         }
 934
 935         return found;
 936 }
 937
 938 /*
 939  * Returns a set of divisors for the desired target clock with the given
 940  * refclk, or FALSE.  The returned values represent the clock equation:
 941  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 942  */
 943 static bool
 944 chv_find_best_dpll(const struct intel_limit *limit,
 945                    struct intel_crtc_state *crtc_state,
 946                    int target, int refclk, struct dpll *match_clock,
 947                    struct dpll *best_clock)
 948 {
 949         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 950         struct drm_device *dev = crtc->base.dev;
 951         unsigned int best_error_ppm;
 952         struct dpll clock;
 953         uint64_t m2;
 954         int found = false;
 955
 956         memset(best_clock, 0, sizeof(*best_clock));
 957         best_error_ppm = 1000000;
 958
 959         /*
 960          * Based on hardware doc, the n always set to 1, and m1 always
 961          * set to 2.  If requires to support 200Mhz refclk, we need to
 962          * revisit this because n may not 1 anymore.
 963          */
 964         clock.n = 1, clock.m1 = 2;
 965         target *= 5;    /* fast clock */
 966
 967         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 968                 for (clock.p2 = limit->p2.p2_fast;
 969                                 clock.p2 >= limit->p2.p2_slow;
 970                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 971                         unsigned int error_ppm;
 972
 973                         clock.p = clock.p1 * clock.p2;
 974
 975                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 976                                         clock.n) << 22, refclk * clock.m1);
 977
 978                         if (m2 > INT_MAX/clock.m1)
 979                                 continue;
 980
 981                         clock.m2 = m2;
 982
 983                         chv_calc_dpll_params(refclk, &clock);
 984
 985                         if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))
 986                                 continue;
 987
 988                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
 989                                                 best_error_ppm, &error_ppm))
 990                                 continue;
 991
 992                         *best_clock = clock;
 993                         best_error_ppm = error_ppm;
 994                         found = true;
 995                 }
 996         }
 997
 998         return found;
 999 }
1000
1001 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1002                         struct dpll *best_clock)
1003 {
1004         int refclk = 100000;
1005         const struct intel_limit *limit = &intel_limits_bxt;
1006
1007         return chv_find_best_dpll(limit, crtc_state,
1008                                   target_clock, refclk, NULL, best_clock);
1009 }
1010
1011 bool intel_crtc_active(struct intel_crtc *crtc)
1012 {
1013         /* Be paranoid as we can arrive here with only partial
1014          * state retrieved from the hardware during setup.
1015          *
1016          * We can ditch the adjusted_mode.crtc_clock check as soon
1017          * as Haswell has gained clock readout/fastboot support.
1018          *
1019          * We can ditch the crtc->primary->fb check as soon as we can
1020          * properly reconstruct framebuffers.
1021          *
1022          * FIXME: The intel_crtc->active here should be switched to
1023          * crtc->state->active once we have proper CRTC states wired up
1024          * for atomic.
1025          */
1026         return crtc->active && crtc->base.primary->state->fb &&
1027                 crtc->config->base.adjusted_mode.crtc_clock;
1028 }
1029
1030 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1031                                              enum pipe pipe)
1032 {
1033         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1034
1035         return crtc->config->cpu_transcoder;
1036 }
1037
1038 static bool pipe_dsl_stopped(struct drm_i915_private *dev_priv, enum pipe pipe)
1039 {
1040         i915_reg_t reg = PIPEDSL(pipe);
1041         u32 line1, line2;
1042         u32 line_mask;
1043
1044         if (IS_GEN2(dev_priv))
1045                 line_mask = DSL_LINEMASK_GEN2;
1046         else
1047                 line_mask = DSL_LINEMASK_GEN3;
1048
1049         line1 = I915_READ(reg) & line_mask;
1050         msleep(5);
1051         line2 = I915_READ(reg) & line_mask;
1052
1053         return line1 == line2;
1054 }
1055
1056 /*
1057  * intel_wait_for_pipe_off - wait for pipe to turn off
1058  * @crtc: crtc whose pipe to wait for
1059  *
1060  * After disabling a pipe, we can't wait for vblank in the usual way,
1061  * spinning on the vblank interrupt status bit, since we won't actually
1062  * see an interrupt when the pipe is disabled.
1063  *
1064  * On Gen4 and above:
1065  *   wait for the pipe register state bit to turn off
1066  *
1067  * Otherwise:
1068  *   wait for the display line value to settle (it usually
1069  *   ends up stopping at the start of the next frame).
1070  *
1071  */
1072 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1073 {
1074         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1075         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1076         enum pipe pipe = crtc->pipe;
1077
1078         if (INTEL_GEN(dev_priv) >= 4) {
1079                 i915_reg_t reg = PIPECONF(cpu_transcoder);
1080
1081                 /* Wait for the Pipe State to go off */
1082                 if (intel_wait_for_register(dev_priv,
1083                                             reg, I965_PIPECONF_ACTIVE, 0,
1084                                             100))
1085                         WARN(1, "pipe_off wait timed out\n");
1086         } else {
1087                 /* Wait for the display line to settle */
1088                 if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100))
1089                         WARN(1, "pipe_off wait timed out\n");
1090         }
1091 }
1092
1093 /* Only for pre-ILK configs */
1094 void assert_pll(struct drm_i915_private *dev_priv,
1095                 enum pipe pipe, bool state)
1096 {
1097         u32 val;
1098         bool cur_state;
1099
1100         val = I915_READ(DPLL(pipe));
1101         cur_state = !!(val & DPLL_VCO_ENABLE);
1102         I915_STATE_WARN(cur_state != state,
1103              "PLL state assertion failure (expected %s, current %s)\n",
1104                         onoff(state), onoff(cur_state));
1105 }
1106
1107 /* XXX: the dsi pll is shared between MIPI DSI ports */
1108 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1109 {
1110         u32 val;
1111         bool cur_state;
1112
1113         mutex_lock(&dev_priv->sb_lock);
1114         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1115         mutex_unlock(&dev_priv->sb_lock);
1116
1117         cur_state = val & DSI_PLL_VCO_EN;
1118         I915_STATE_WARN(cur_state != state,
1119              "DSI PLL state assertion failure (expected %s, current %s)\n",
1120                         onoff(state), onoff(cur_state));
1121 }
1122
1123 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1124                           enum pipe pipe, bool state)
1125 {
1126         bool cur_state;
1127         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1128                                                                       pipe);
1129
1130         if (HAS_DDI(dev_priv)) {
1131                 /* DDI does not have a specific FDI_TX register */
1132                 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1133                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1134         } else {
1135                 u32 val = I915_READ(FDI_TX_CTL(pipe));
1136                 cur_state = !!(val & FDI_TX_ENABLE);
1137         }
1138         I915_STATE_WARN(cur_state != state,
1139              "FDI TX state assertion failure (expected %s, current %s)\n",
1140                         onoff(state), onoff(cur_state));
1141 }
1142 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1143 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1144
1145 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1146                           enum pipe pipe, bool state)
1147 {
1148         u32 val;
1149         bool cur_state;
1150
1151         val = I915_READ(FDI_RX_CTL(pipe));
1152         cur_state = !!(val & FDI_RX_ENABLE);
1153         I915_STATE_WARN(cur_state != state,
1154              "FDI RX state assertion failure (expected %s, current %s)\n",
1155                         onoff(state), onoff(cur_state));
1156 }
1157 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1158 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1159
1160 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1161                                       enum pipe pipe)
1162 {
1163         u32 val;
1164
1165         /* ILK FDI PLL is always enabled */
1166         if (IS_GEN5(dev_priv))
1167                 return;
1168
1169         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1170         if (HAS_DDI(dev_priv))
1171                 return;
1172
1173         val = I915_READ(FDI_TX_CTL(pipe));
1174         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1175 }
1176
1177 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1178                        enum pipe pipe, bool state)
1179 {
1180         u32 val;
1181         bool cur_state;
1182
1183         val = I915_READ(FDI_RX_CTL(pipe));
1184         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1185         I915_STATE_WARN(cur_state != state,
1186              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1187                         onoff(state), onoff(cur_state));
1188 }
1189
1190 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1191 {
1192         i915_reg_t pp_reg;
1193         u32 val;
1194         enum pipe panel_pipe = PIPE_A;
1195         bool locked = true;
1196
1197         if (WARN_ON(HAS_DDI(dev_priv)))
1198                 return;
1199
1200         if (HAS_PCH_SPLIT(dev_priv)) {
1201                 u32 port_sel;
1202
1203                 pp_reg = PP_CONTROL(0);
1204                 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1205
1206                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1207                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1208                         panel_pipe = PIPE_B;
1209                 /* XXX: else fix for eDP */
1210         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1211                 /* presumably write lock depends on pipe, not port select */
1212                 pp_reg = PP_CONTROL(pipe);
1213                 panel_pipe = pipe;
1214         } else {
1215                 pp_reg = PP_CONTROL(0);
1216                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1217                         panel_pipe = PIPE_B;
1218         }
1219
1220         val = I915_READ(pp_reg);
1221         if (!(val & PANEL_POWER_ON) ||
1222             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1223                 locked = false;
1224
1225         I915_STATE_WARN(panel_pipe == pipe && locked,
1226              "panel assertion failure, pipe %c regs locked\n",
1227              pipe_name(pipe));
1228 }
1229
1230 static void assert_cursor(struct drm_i915_private *dev_priv,
1231                           enum pipe pipe, bool state)
1232 {
1233         bool cur_state;
1234
1235         if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
1236                 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1237         else
1238                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1239
1240         I915_STATE_WARN(cur_state != state,
1241              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1242                         pipe_name(pipe), onoff(state), onoff(cur_state));
1243 }
1244 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1245 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1246
1247 void assert_pipe(struct drm_i915_private *dev_priv,
1248                  enum pipe pipe, bool state)
1249 {
1250         bool cur_state;
1251         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1252                                                                       pipe);
1253         enum intel_display_power_domain power_domain;
1254
1255         /* if we need the pipe quirk it must be always on */
1256         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1257             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1258                 state = true;
1259
1260         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1261         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1262                 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1263                 cur_state = !!(val & PIPECONF_ENABLE);
1264
1265                 intel_display_power_put(dev_priv, power_domain);
1266         } else {
1267                 cur_state = false;
1268         }
1269
1270         I915_STATE_WARN(cur_state != state,
1271              "pipe %c assertion failure (expected %s, current %s)\n",
1272                         pipe_name(pipe), onoff(state), onoff(cur_state));
1273 }
1274
1275 static void assert_plane(struct drm_i915_private *dev_priv,
1276                          enum plane plane, bool state)
1277 {
1278         u32 val;
1279         bool cur_state;
1280
1281         val = I915_READ(DSPCNTR(plane));
1282         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1283         I915_STATE_WARN(cur_state != state,
1284              "plane %c assertion failure (expected %s, current %s)\n",
1285                         plane_name(plane), onoff(state), onoff(cur_state));
1286 }
1287
1288 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1289 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1290
1291 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1292                                    enum pipe pipe)
1293 {
1294         int i;
1295
1296         /* Primary planes are fixed to pipes on gen4+ */
1297         if (INTEL_GEN(dev_priv) >= 4) {
1298                 u32 val = I915_READ(DSPCNTR(pipe));
1299                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1300                      "plane %c assertion failure, should be disabled but not\n",
1301                      plane_name(pipe));
1302                 return;
1303         }
1304
1305         /* Need to check both planes against the pipe */
1306         for_each_pipe(dev_priv, i) {
1307                 u32 val = I915_READ(DSPCNTR(i));
1308                 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1309                         DISPPLANE_SEL_PIPE_SHIFT;
1310                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1311                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1312                      plane_name(i), pipe_name(pipe));
1313         }
1314 }
1315
1316 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1317                                     enum pipe pipe)
1318 {
1319         int sprite;
1320
1321         if (INTEL_GEN(dev_priv) >= 9) {
1322                 for_each_sprite(dev_priv, pipe, sprite) {
1323                         u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1324                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1325                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1326                              sprite, pipe_name(pipe));
1327                 }
1328         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1329                 for_each_sprite(dev_priv, pipe, sprite) {
1330                         u32 val = I915_READ(SPCNTR(pipe, PLANE_SPRITE0 + sprite));
1331                         I915_STATE_WARN(val & SP_ENABLE,
1332                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1333                              sprite_name(pipe, sprite), pipe_name(pipe));
1334                 }
1335         } else if (INTEL_GEN(dev_priv) >= 7) {
1336                 u32 val = I915_READ(SPRCTL(pipe));
1337                 I915_STATE_WARN(val & SPRITE_ENABLE,
1338                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1339                      plane_name(pipe), pipe_name(pipe));
1340         } else if (INTEL_GEN(dev_priv) >= 5) {
1341                 u32 val = I915_READ(DVSCNTR(pipe));
1342                 I915_STATE_WARN(val & DVS_ENABLE,
1343                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1344                      plane_name(pipe), pipe_name(pipe));
1345         }
1346 }
1347
1348 static void assert_vblank_disabled(struct drm_crtc *crtc)
1349 {
1350         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1351                 drm_crtc_vblank_put(crtc);
1352 }
1353
1354 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1355                                     enum pipe pipe)
1356 {
1357         u32 val;
1358         bool enabled;
1359
1360         val = I915_READ(PCH_TRANSCONF(pipe));
1361         enabled = !!(val & TRANS_ENABLE);
1362         I915_STATE_WARN(enabled,
1363              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1364              pipe_name(pipe));
1365 }
1366
1367 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1368                             enum pipe pipe, u32 port_sel, u32 val)
1369 {
1370         if ((val & DP_PORT_EN) == 0)
1371                 return false;
1372
1373         if (HAS_PCH_CPT(dev_priv)) {
1374                 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1375                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1376                         return false;
1377         } else if (IS_CHERRYVIEW(dev_priv)) {
1378                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1379                         return false;
1380         } else {
1381                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1382                         return false;
1383         }
1384         return true;
1385 }
1386
1387 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1388                               enum pipe pipe, u32 val)
1389 {
1390         if ((val & SDVO_ENABLE) == 0)
1391                 return false;
1392
1393         if (HAS_PCH_CPT(dev_priv)) {
1394                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1395                         return false;
1396         } else if (IS_CHERRYVIEW(dev_priv)) {
1397                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1398                         return false;
1399         } else {
1400                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1401                         return false;
1402         }
1403         return true;
1404 }
1405
1406 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1407                               enum pipe pipe, u32 val)
1408 {
1409         if ((val & LVDS_PORT_EN) == 0)
1410                 return false;
1411
1412         if (HAS_PCH_CPT(dev_priv)) {
1413                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1414                         return false;
1415         } else {
1416                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1417                         return false;
1418         }
1419         return true;
1420 }
1421
1422 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1423                               enum pipe pipe, u32 val)
1424 {
1425         if ((val & ADPA_DAC_ENABLE) == 0)
1426                 return false;
1427         if (HAS_PCH_CPT(dev_priv)) {
1428                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1429                         return false;
1430         } else {
1431                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1432                         return false;
1433         }
1434         return true;
1435 }
1436
1437 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1438                                    enum pipe pipe, i915_reg_t reg,
1439                                    u32 port_sel)
1440 {
1441         u32 val = I915_READ(reg);
1442         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1443              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1444              i915_mmio_reg_offset(reg), pipe_name(pipe));
1445
1446         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1447              && (val & DP_PIPEB_SELECT),
1448              "IBX PCH dp port still using transcoder B\n");
1449 }
1450
1451 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1452                                      enum pipe pipe, i915_reg_t reg)
1453 {
1454         u32 val = I915_READ(reg);
1455         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1456              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1457              i915_mmio_reg_offset(reg), pipe_name(pipe));
1458
1459         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1460              && (val & SDVO_PIPE_B_SELECT),
1461              "IBX PCH hdmi port still using transcoder B\n");
1462 }
1463
1464 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1465                                       enum pipe pipe)
1466 {
1467         u32 val;
1468
1469         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1470         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1471         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1472
1473         val = I915_READ(PCH_ADPA);
1474         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1475              "PCH VGA enabled on transcoder %c, should be disabled\n",
1476              pipe_name(pipe));
1477
1478         val = I915_READ(PCH_LVDS);
1479         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1480              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1481              pipe_name(pipe));
1482
1483         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1484         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1485         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1486 }
1487
1488 static void _vlv_enable_pll(struct intel_crtc *crtc,
1489                             const struct intel_crtc_state *pipe_config)
1490 {
1491         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1492         enum pipe pipe = crtc->pipe;
1493
1494         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1495         POSTING_READ(DPLL(pipe));
1496         udelay(150);
1497
1498         if (intel_wait_for_register(dev_priv,
1499                                     DPLL(pipe),
1500                                     DPLL_LOCK_VLV,
1501                                     DPLL_LOCK_VLV,
1502                                     1))
1503                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1504 }
1505
1506 static void vlv_enable_pll(struct intel_crtc *crtc,
1507                            const struct intel_crtc_state *pipe_config)
1508 {
1509         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1510         enum pipe pipe = crtc->pipe;
1511
1512         assert_pipe_disabled(dev_priv, pipe);
1513
1514         /* PLL is protected by panel, make sure we can write it */
1515         assert_panel_unlocked(dev_priv, pipe);
1516
1517         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1518                 _vlv_enable_pll(crtc, pipe_config);
1519
1520         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1521         POSTING_READ(DPLL_MD(pipe));
1522 }
1523
1524
1525 static void _chv_enable_pll(struct intel_crtc *crtc,
1526                             const struct intel_crtc_state *pipe_config)
1527 {
1528         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1529         enum pipe pipe = crtc->pipe;
1530         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1531         u32 tmp;
1532
1533         mutex_lock(&dev_priv->sb_lock);
1534
1535         /* Enable back the 10bit clock to display controller */
1536         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1537         tmp |= DPIO_DCLKP_EN;
1538         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1539
1540         mutex_unlock(&dev_priv->sb_lock);
1541
1542         /*
1543          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1544          */
1545         udelay(1);
1546
1547         /* Enable PLL */
1548         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1549
1550         /* Check PLL is locked */
1551         if (intel_wait_for_register(dev_priv,
1552                                     DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1553                                     1))
1554                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1555 }
1556
1557 static void chv_enable_pll(struct intel_crtc *crtc,
1558                            const struct intel_crtc_state *pipe_config)
1559 {
1560         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1561         enum pipe pipe = crtc->pipe;
1562
1563         assert_pipe_disabled(dev_priv, pipe);
1564
1565         /* PLL is protected by panel, make sure we can write it */
1566         assert_panel_unlocked(dev_priv, pipe);
1567
1568         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1569                 _chv_enable_pll(crtc, pipe_config);
1570
1571         if (pipe != PIPE_A) {
1572                 /*
1573                  * WaPixelRepeatModeFixForC0:chv
1574                  *
1575                  * DPLLCMD is AWOL. Use chicken bits to propagate
1576                  * the value from DPLLBMD to either pipe B or C.
1577                  */
1578                 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1579                 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1580                 I915_WRITE(CBR4_VLV, 0);
1581                 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1582
1583                 /*
1584                  * DPLLB VGA mode also seems to cause problems.
1585                  * We should always have it disabled.
1586                  */
1587                 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1588         } else {
1589                 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1590                 POSTING_READ(DPLL_MD(pipe));
1591         }
1592 }
1593
1594 static int intel_num_dvo_pipes(struct drm_i915_private *dev_priv)
1595 {
1596         struct intel_crtc *crtc;
1597         int count = 0;
1598
1599         for_each_intel_crtc(&dev_priv->drm, crtc) {
1600                 count += crtc->base.state->active &&
1601                         intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO);
1602         }
1603
1604         return count;
1605 }
1606
1607 static void i9xx_enable_pll(struct intel_crtc *crtc)
1608 {
1609         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1610         i915_reg_t reg = DPLL(crtc->pipe);
1611         u32 dpll = crtc->config->dpll_hw_state.dpll;
1612
1613         assert_pipe_disabled(dev_priv, crtc->pipe);
1614
1615         /* PLL is protected by panel, make sure we can write it */
1616         if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
1617                 assert_panel_unlocked(dev_priv, crtc->pipe);
1618
1619         /* Enable DVO 2x clock on both PLLs if necessary */
1620         if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev_priv) > 0) {
1621                 /*
1622                  * It appears to be important that we don't enable this
1623                  * for the current pipe before otherwise configuring the
1624                  * PLL. No idea how this should be handled if multiple
1625                  * DVO outputs are enabled simultaneosly.
1626                  */
1627                 dpll |= DPLL_DVO_2X_MODE;
1628                 I915_WRITE(DPLL(!crtc->pipe),
1629                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1630         }
1631
1632         /*
1633          * Apparently we need to have VGA mode enabled prior to changing
1634          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1635          * dividers, even though the register value does change.
1636          */
1637         I915_WRITE(reg, 0);
1638
1639         I915_WRITE(reg, dpll);
1640
1641         /* Wait for the clocks to stabilize. */
1642         POSTING_READ(reg);
1643         udelay(150);
1644
1645         if (INTEL_GEN(dev_priv) >= 4) {
1646                 I915_WRITE(DPLL_MD(crtc->pipe),
1647                            crtc->config->dpll_hw_state.dpll_md);
1648         } else {
1649                 /* The pixel multiplier can only be updated once the
1650                  * DPLL is enabled and the clocks are stable.
1651                  *
1652                  * So write it again.
1653                  */
1654                 I915_WRITE(reg, dpll);
1655         }
1656
1657         /* We do this three times for luck */
1658         I915_WRITE(reg, dpll);
1659         POSTING_READ(reg);
1660         udelay(150); /* wait for warmup */
1661         I915_WRITE(reg, dpll);
1662         POSTING_READ(reg);
1663         udelay(150); /* wait for warmup */
1664         I915_WRITE(reg, dpll);
1665         POSTING_READ(reg);
1666         udelay(150); /* wait for warmup */
1667 }
1668
1669 /**
1670  * i9xx_disable_pll - disable a PLL
1671  * @dev_priv: i915 private structure
1672  * @pipe: pipe PLL to disable
1673  *
1674  * Disable the PLL for @pipe, making sure the pipe is off first.
1675  *
1676  * Note!  This is for pre-ILK only.
1677  */
1678 static void i9xx_disable_pll(struct intel_crtc *crtc)
1679 {
1680         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1681         enum pipe pipe = crtc->pipe;
1682
1683         /* Disable DVO 2x clock on both PLLs if necessary */
1684         if (IS_I830(dev_priv) &&
1685             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
1686             !intel_num_dvo_pipes(dev_priv)) {
1687                 I915_WRITE(DPLL(PIPE_B),
1688                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1689                 I915_WRITE(DPLL(PIPE_A),
1690                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1691         }
1692
1693         /* Don't disable pipe or pipe PLLs if needed */
1694         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1695             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1696                 return;
1697
1698         /* Make sure the pipe isn't still relying on us */
1699         assert_pipe_disabled(dev_priv, pipe);
1700
1701         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1702         POSTING_READ(DPLL(pipe));
1703 }
1704
1705 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1706 {
1707         u32 val;
1708
1709         /* Make sure the pipe isn't still relying on us */
1710         assert_pipe_disabled(dev_priv, pipe);
1711
1712         val = DPLL_INTEGRATED_REF_CLK_VLV |
1713                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1714         if (pipe != PIPE_A)
1715                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1716
1717         I915_WRITE(DPLL(pipe), val);
1718         POSTING_READ(DPLL(pipe));
1719 }
1720
1721 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1722 {
1723         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1724         u32 val;
1725
1726         /* Make sure the pipe isn't still relying on us */
1727         assert_pipe_disabled(dev_priv, pipe);
1728
1729         val = DPLL_SSC_REF_CLK_CHV |
1730                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1731         if (pipe != PIPE_A)
1732                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1733
1734         I915_WRITE(DPLL(pipe), val);
1735         POSTING_READ(DPLL(pipe));
1736
1737         mutex_lock(&dev_priv->sb_lock);
1738
1739         /* Disable 10bit clock to display controller */
1740         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1741         val &= ~DPIO_DCLKP_EN;
1742         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1743
1744         mutex_unlock(&dev_priv->sb_lock);
1745 }
1746
1747 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1748                          struct intel_digital_port *dport,
1749                          unsigned int expected_mask)
1750 {
1751         u32 port_mask;
1752         i915_reg_t dpll_reg;
1753
1754         switch (dport->port) {
1755         case PORT_B:
1756                 port_mask = DPLL_PORTB_READY_MASK;
1757                 dpll_reg = DPLL(0);
1758                 break;
1759         case PORT_C:
1760                 port_mask = DPLL_PORTC_READY_MASK;
1761                 dpll_reg = DPLL(0);
1762                 expected_mask <<= 4;
1763                 break;
1764         case PORT_D:
1765                 port_mask = DPLL_PORTD_READY_MASK;
1766                 dpll_reg = DPIO_PHY_STATUS;
1767                 break;
1768         default:
1769                 BUG();
1770         }
1771
1772         if (intel_wait_for_register(dev_priv,
1773                                     dpll_reg, port_mask, expected_mask,
1774                                     1000))
1775                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1776                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1777 }
1778
1779 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1780                                            enum pipe pipe)
1781 {
1782         struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
1783                                                                 pipe);
1784         i915_reg_t reg;
1785         uint32_t val, pipeconf_val;
1786
1787         /* Make sure PCH DPLL is enabled */
1788         assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1789
1790         /* FDI must be feeding us bits for PCH ports */
1791         assert_fdi_tx_enabled(dev_priv, pipe);
1792         assert_fdi_rx_enabled(dev_priv, pipe);
1793
1794         if (HAS_PCH_CPT(dev_priv)) {
1795                 /* Workaround: Set the timing override bit before enabling the
1796                  * pch transcoder. */
1797                 reg = TRANS_CHICKEN2(pipe);
1798                 val = I915_READ(reg);
1799                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1800                 I915_WRITE(reg, val);
1801         }
1802
1803         reg = PCH_TRANSCONF(pipe);
1804         val = I915_READ(reg);
1805         pipeconf_val = I915_READ(PIPECONF(pipe));
1806
1807         if (HAS_PCH_IBX(dev_priv)) {
1808                 /*
1809                  * Make the BPC in transcoder be consistent with
1810                  * that in pipeconf reg. For HDMI we must use 8bpc
1811                  * here for both 8bpc and 12bpc.
1812                  */
1813                 val &= ~PIPECONF_BPC_MASK;
1814                 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI))
1815                         val |= PIPECONF_8BPC;
1816                 else
1817                         val |= pipeconf_val & PIPECONF_BPC_MASK;
1818         }
1819
1820         val &= ~TRANS_INTERLACE_MASK;
1821         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1822                 if (HAS_PCH_IBX(dev_priv) &&
1823                     intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
1824                         val |= TRANS_LEGACY_INTERLACED_ILK;
1825                 else
1826                         val |= TRANS_INTERLACED;
1827         else
1828                 val |= TRANS_PROGRESSIVE;
1829
1830         I915_WRITE(reg, val | TRANS_ENABLE);
1831         if (intel_wait_for_register(dev_priv,
1832                                     reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1833                                     100))
1834                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1835 }
1836
1837 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1838                                       enum transcoder cpu_transcoder)
1839 {
1840         u32 val, pipeconf_val;
1841
1842         /* FDI must be feeding us bits for PCH ports */
1843         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1844         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1845
1846         /* Workaround: set timing override bit. */
1847         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1848         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1849         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1850
1851         val = TRANS_ENABLE;
1852         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1853
1854         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1855             PIPECONF_INTERLACED_ILK)
1856                 val |= TRANS_INTERLACED;
1857         else
1858                 val |= TRANS_PROGRESSIVE;
1859
1860         I915_WRITE(LPT_TRANSCONF, val);
1861         if (intel_wait_for_register(dev_priv,
1862                                     LPT_TRANSCONF,
1863                                     TRANS_STATE_ENABLE,
1864                                     TRANS_STATE_ENABLE,
1865                                     100))
1866                 DRM_ERROR("Failed to enable PCH transcoder\n");
1867 }
1868
1869 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1870                                             enum pipe pipe)
1871 {
1872         i915_reg_t reg;
1873         uint32_t val;
1874
1875         /* FDI relies on the transcoder */
1876         assert_fdi_tx_disabled(dev_priv, pipe);
1877         assert_fdi_rx_disabled(dev_priv, pipe);
1878
1879         /* Ports must be off as well */
1880         assert_pch_ports_disabled(dev_priv, pipe);
1881
1882         reg = PCH_TRANSCONF(pipe);
1883         val = I915_READ(reg);
1884         val &= ~TRANS_ENABLE;
1885         I915_WRITE(reg, val);
1886         /* wait for PCH transcoder off, transcoder state */
1887         if (intel_wait_for_register(dev_priv,
1888                                     reg, TRANS_STATE_ENABLE, 0,
1889                                     50))
1890                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1891
1892         if (HAS_PCH_CPT(dev_priv)) {
1893                 /* Workaround: Clear the timing override chicken bit again. */
1894                 reg = TRANS_CHICKEN2(pipe);
1895                 val = I915_READ(reg);
1896                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1897                 I915_WRITE(reg, val);
1898         }
1899 }
1900
1901 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1902 {
1903         u32 val;
1904
1905         val = I915_READ(LPT_TRANSCONF);
1906         val &= ~TRANS_ENABLE;
1907         I915_WRITE(LPT_TRANSCONF, val);
1908         /* wait for PCH transcoder off, transcoder state */
1909         if (intel_wait_for_register(dev_priv,
1910                                     LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1911                                     50))
1912                 DRM_ERROR("Failed to disable PCH transcoder\n");
1913
1914         /* Workaround: clear timing override bit. */
1915         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1916         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1917         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1918 }
1919
1920 enum transcoder intel_crtc_pch_transcoder(struct intel_crtc *crtc)
1921 {
1922         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1923
1924         WARN_ON(!crtc->config->has_pch_encoder);
1925
1926         if (HAS_PCH_LPT(dev_priv))
1927                 return TRANSCODER_A;
1928         else
1929                 return (enum transcoder) crtc->pipe;
1930 }
1931
1932 /**
1933  * intel_enable_pipe - enable a pipe, asserting requirements
1934  * @crtc: crtc responsible for the pipe
1935  *
1936  * Enable @crtc's pipe, making sure that various hardware specific requirements
1937  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1938  */
1939 static void intel_enable_pipe(struct intel_crtc *crtc)
1940 {
1941         struct drm_device *dev = crtc->base.dev;
1942         struct drm_i915_private *dev_priv = to_i915(dev);
1943         enum pipe pipe = crtc->pipe;
1944         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1945         i915_reg_t reg;
1946         u32 val;
1947
1948         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1949
1950         assert_planes_disabled(dev_priv, pipe);
1951         assert_cursor_disabled(dev_priv, pipe);
1952         assert_sprites_disabled(dev_priv, pipe);
1953
1954         /*
1955          * A pipe without a PLL won't actually be able to drive bits from
1956          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1957          * need the check.
1958          */
1959         if (HAS_GMCH_DISPLAY(dev_priv)) {
1960                 if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI))
1961                         assert_dsi_pll_enabled(dev_priv);
1962                 else
1963                         assert_pll_enabled(dev_priv, pipe);
1964         } else {
1965                 if (crtc->config->has_pch_encoder) {
1966                         /* if driving the PCH, we need FDI enabled */
1967                         assert_fdi_rx_pll_enabled(dev_priv,
1968                                                   (enum pipe) intel_crtc_pch_transcoder(crtc));
1969                         assert_fdi_tx_pll_enabled(dev_priv,
1970                                                   (enum pipe) cpu_transcoder);
1971                 }
1972                 /* FIXME: assert CPU port conditions for SNB+ */
1973         }
1974
1975         reg = PIPECONF(cpu_transcoder);
1976         val = I915_READ(reg);
1977         if (val & PIPECONF_ENABLE) {
1978                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1979                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
1980                 return;
1981         }
1982
1983         I915_WRITE(reg, val | PIPECONF_ENABLE);
1984         POSTING_READ(reg);
1985
1986         /*
1987          * Until the pipe starts DSL will read as 0, which would cause
1988          * an apparent vblank timestamp jump, which messes up also the
1989          * frame count when it's derived from the timestamps. So let's
1990          * wait for the pipe to start properly before we call
1991          * drm_crtc_vblank_on()
1992          */
1993         if (dev->max_vblank_count == 0 &&
1994             wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
1995                 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
1996 }
1997
1998 /**
1999  * intel_disable_pipe - disable a pipe, asserting requirements
2000  * @crtc: crtc whose pipes is to be disabled
2001  *
2002  * Disable the pipe of @crtc, making sure that various hardware
2003  * specific requirements are met, if applicable, e.g. plane
2004  * disabled, panel fitter off, etc.
2005  *
2006  * Will wait until the pipe has shut down before returning.
2007  */
2008 static void intel_disable_pipe(struct intel_crtc *crtc)
2009 {
2010         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2011         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2012         enum pipe pipe = crtc->pipe;
2013         i915_reg_t reg;
2014         u32 val;
2015
2016         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2017
2018         /*
2019          * Make sure planes won't keep trying to pump pixels to us,
2020          * or we might hang the display.
2021          */
2022         assert_planes_disabled(dev_priv, pipe);
2023         assert_cursor_disabled(dev_priv, pipe);
2024         assert_sprites_disabled(dev_priv, pipe);
2025
2026         reg = PIPECONF(cpu_transcoder);
2027         val = I915_READ(reg);
2028         if ((val & PIPECONF_ENABLE) == 0)
2029                 return;
2030
2031         /*
2032          * Double wide has implications for planes
2033          * so best keep it disabled when not needed.
2034          */
2035         if (crtc->config->double_wide)
2036                 val &= ~PIPECONF_DOUBLE_WIDE;
2037
2038         /* Don't disable pipe or pipe PLLs if needed */
2039         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2040             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2041                 val &= ~PIPECONF_ENABLE;
2042
2043         I915_WRITE(reg, val);
2044         if ((val & PIPECONF_ENABLE) == 0)
2045                 intel_wait_for_pipe_off(crtc);
2046 }
2047
2048 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
2049 {
2050         return IS_GEN2(dev_priv) ? 2048 : 4096;
2051 }
2052
2053 static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv,
2054                                            uint64_t fb_modifier, unsigned int cpp)
2055 {
2056         switch (fb_modifier) {
2057         case DRM_FORMAT_MOD_NONE:
2058                 return cpp;
2059         case I915_FORMAT_MOD_X_TILED:
2060                 if (IS_GEN2(dev_priv))
2061                         return 128;
2062                 else
2063                         return 512;
2064         case I915_FORMAT_MOD_Y_TILED:
2065                 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2066                         return 128;
2067                 else
2068                         return 512;
2069         case I915_FORMAT_MOD_Yf_TILED:
2070                 switch (cpp) {
2071                 case 1:
2072                         return 64;
2073                 case 2:
2074                 case 4:
2075                         return 128;
2076                 case 8:
2077                 case 16:
2078                         return 256;
2079                 default:
2080                         MISSING_CASE(cpp);
2081                         return cpp;
2082                 }
2083                 break;
2084         default:
2085                 MISSING_CASE(fb_modifier);
2086                 return cpp;
2087         }
2088 }
2089
2090 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
2091                                uint64_t fb_modifier, unsigned int cpp)
2092 {
2093         if (fb_modifier == DRM_FORMAT_MOD_NONE)
2094                 return 1;
2095         else
2096                 return intel_tile_size(dev_priv) /
2097                         intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2098 }
2099
2100 /* Return the tile dimensions in pixel units */
2101 static void intel_tile_dims(const struct drm_i915_private *dev_priv,
2102                             unsigned int *tile_width,
2103                             unsigned int *tile_height,
2104                             uint64_t fb_modifier,
2105                             unsigned int cpp)
2106 {
2107         unsigned int tile_width_bytes =
2108                 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2109
2110         *tile_width = tile_width_bytes / cpp;
2111         *tile_height = intel_tile_size(dev_priv) / tile_width_bytes;
2112 }
2113
2114 unsigned int
2115 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2116                       uint32_t pixel_format, uint64_t fb_modifier)
2117 {
2118         unsigned int cpp = drm_format_plane_cpp(pixel_format, 0);
2119         unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp);
2120
2121         return ALIGN(height, tile_height);
2122 }
2123
2124 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2125 {
2126         unsigned int size = 0;
2127         int i;
2128
2129         for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2130                 size += rot_info->plane[i].width * rot_info->plane[i].height;
2131
2132         return size;
2133 }
2134
2135 static void
2136 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2137                         const struct drm_framebuffer *fb,
2138                         unsigned int rotation)
2139 {
2140         view->type = I915_GGTT_VIEW_NORMAL;
2141         if (drm_rotation_90_or_270(rotation)) {
2142                 view->type = I915_GGTT_VIEW_ROTATED;
2143                 view->rotated = to_intel_framebuffer(fb)->rot_info;
2144         }
2145 }
2146
2147 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2148 {
2149         if (INTEL_INFO(dev_priv)->gen >= 9)
2150                 return 256 * 1024;
2151         else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
2152                  IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2153                 return 128 * 1024;
2154         else if (INTEL_INFO(dev_priv)->gen >= 4)
2155                 return 4 * 1024;
2156         else
2157                 return 0;
2158 }
2159
2160 static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv,
2161                                          uint64_t fb_modifier)
2162 {
2163         switch (fb_modifier) {
2164         case DRM_FORMAT_MOD_NONE:
2165                 return intel_linear_alignment(dev_priv);
2166         case I915_FORMAT_MOD_X_TILED:
2167                 if (INTEL_INFO(dev_priv)->gen >= 9)
2168                         return 256 * 1024;
2169                 return 0;
2170         case I915_FORMAT_MOD_Y_TILED:
2171         case I915_FORMAT_MOD_Yf_TILED:
2172                 return 1 * 1024 * 1024;
2173         default:
2174                 MISSING_CASE(fb_modifier);
2175                 return 0;
2176         }
2177 }
2178
2179 struct i915_vma *
2180 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2181 {
2182         struct drm_device *dev = fb->dev;
2183         struct drm_i915_private *dev_priv = to_i915(dev);
2184         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2185         struct i915_ggtt_view view;
2186         struct i915_vma *vma;
2187         u32 alignment;
2188
2189         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2190
2191         alignment = intel_surf_alignment(dev_priv, fb->modifier);
2192
2193         intel_fill_fb_ggtt_view(&view, fb, rotation);
2194
2195         /* Note that the w/a also requires 64 PTE of padding following the
2196          * bo. We currently fill all unused PTE with the shadow page and so
2197          * we should always have valid PTE following the scanout preventing
2198          * the VT-d warning.
2199          */
2200         if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2201                 alignment = 256 * 1024;
2202
2203         /*
2204          * Global gtt pte registers are special registers which actually forward
2205          * writes to a chunk of system memory. Which means that there is no risk
2206          * that the register values disappear as soon as we call
2207          * intel_runtime_pm_put(), so it is correct to wrap only the
2208          * pin/unpin/fence and not more.
2209          */
2210         intel_runtime_pm_get(dev_priv);
2211
2212         vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view);
2213         if (IS_ERR(vma))
2214                 goto err;
2215
2216         if (i915_vma_is_map_and_fenceable(vma)) {
2217                 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2218                  * fence, whereas 965+ only requires a fence if using
2219                  * framebuffer compression.  For simplicity, we always, when
2220                  * possible, install a fence as the cost is not that onerous.
2221                  *
2222                  * If we fail to fence the tiled scanout, then either the
2223                  * modeset will reject the change (which is highly unlikely as
2224                  * the affected systems, all but one, do not have unmappable
2225                  * space) or we will not be able to enable full powersaving
2226                  * techniques (also likely not to apply due to various limits
2227                  * FBC and the like impose on the size of the buffer, which
2228                  * presumably we violated anyway with this unmappable buffer).
2229                  * Anyway, it is presumably better to stumble onwards with
2230                  * something and try to run the system in a "less than optimal"
2231                  * mode that matches the user configuration.
2232                  */
2233                 if (i915_vma_get_fence(vma) == 0)
2234                         i915_vma_pin_fence(vma);
2235         }
2236
2237         i915_vma_get(vma);
2238 err:
2239         intel_runtime_pm_put(dev_priv);
2240         return vma;
2241 }
2242
2243 void intel_unpin_fb_vma(struct i915_vma *vma)
2244 {
2245         lockdep_assert_held(&vma->vm->i915->drm.struct_mutex);
2246
2247         i915_vma_unpin_fence(vma);
2248         i915_gem_object_unpin_from_display_plane(vma);
2249         i915_vma_put(vma);
2250 }
2251
2252 static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane,
2253                           unsigned int rotation)
2254 {
2255         if (drm_rotation_90_or_270(rotation))
2256                 return to_intel_framebuffer(fb)->rotated[plane].pitch;
2257         else
2258                 return fb->pitches[plane];
2259 }
2260
2261 /*
2262  * Convert the x/y offsets into a linear offset.
2263  * Only valid with 0/180 degree rotation, which is fine since linear
2264  * offset is only used with linear buffers on pre-hsw and tiled buffers
2265  * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2266  */
2267 u32 intel_fb_xy_to_linear(int x, int y,
2268                           const struct intel_plane_state *state,
2269                           int plane)
2270 {
2271         const struct drm_framebuffer *fb = state->base.fb;
2272         unsigned int cpp = fb->format->cpp[plane];
2273         unsigned int pitch = fb->pitches[plane];
2274
2275         return y * pitch + x * cpp;
2276 }
2277
2278 /*
2279  * Add the x/y offsets derived from fb->offsets[] to the user
2280  * specified plane src x/y offsets. The resulting x/y offsets
2281  * specify the start of scanout from the beginning of the gtt mapping.
2282  */
2283 void intel_add_fb_offsets(int *x, int *y,
2284                           const struct intel_plane_state *state,
2285                           int plane)
2286
2287 {
2288         const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
2289         unsigned int rotation = state->base.rotation;
2290
2291         if (drm_rotation_90_or_270(rotation)) {
2292                 *x += intel_fb->rotated[plane].x;
2293                 *y += intel_fb->rotated[plane].y;
2294         } else {
2295                 *x += intel_fb->normal[plane].x;
2296                 *y += intel_fb->normal[plane].y;
2297         }
2298 }
2299
2300 /*
2301  * Input tile dimensions and pitch must already be
2302  * rotated to match x and y, and in pixel units.
2303  */
2304 static u32 _intel_adjust_tile_offset(int *x, int *y,
2305                                      unsigned int tile_width,
2306                                      unsigned int tile_height,
2307                                      unsigned int tile_size,
2308                                      unsigned int pitch_tiles,
2309                                      u32 old_offset,
2310                                      u32 new_offset)
2311 {
2312         unsigned int pitch_pixels = pitch_tiles * tile_width;
2313         unsigned int tiles;
2314
2315         WARN_ON(old_offset & (tile_size - 1));
2316         WARN_ON(new_offset & (tile_size - 1));
2317         WARN_ON(new_offset > old_offset);
2318
2319         tiles = (old_offset - new_offset) / tile_size;
2320
2321         *y += tiles / pitch_tiles * tile_height;
2322         *x += tiles % pitch_tiles * tile_width;
2323
2324         /* minimize x in case it got needlessly big */
2325         *y += *x / pitch_pixels * tile_height;
2326         *x %= pitch_pixels;
2327
2328         return new_offset;
2329 }
2330
2331 /*
2332  * Adjust the tile offset by moving the difference into
2333  * the x/y offsets.
2334  */
2335 static u32 intel_adjust_tile_offset(int *x, int *y,
2336                                     const struct intel_plane_state *state, int plane,
2337                                     u32 old_offset, u32 new_offset)
2338 {
2339         const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2340         const struct drm_framebuffer *fb = state->base.fb;
2341         unsigned int cpp = fb->format->cpp[plane];
2342         unsigned int rotation = state->base.rotation;
2343         unsigned int pitch = intel_fb_pitch(fb, plane, rotation);
2344
2345         WARN_ON(new_offset > old_offset);
2346
2347         if (fb->modifier != DRM_FORMAT_MOD_NONE) {
2348                 unsigned int tile_size, tile_width, tile_height;
2349                 unsigned int pitch_tiles;
2350
2351                 tile_size = intel_tile_size(dev_priv);
2352                 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2353                                 fb->modifier, cpp);
2354
2355                 if (drm_rotation_90_or_270(rotation)) {
2356                         pitch_tiles = pitch / tile_height;
2357                         swap(tile_width, tile_height);
2358                 } else {
2359                         pitch_tiles = pitch / (tile_width * cpp);
2360                 }
2361
2362                 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2363                                           tile_size, pitch_tiles,
2364                                           old_offset, new_offset);
2365         } else {
2366                 old_offset += *y * pitch + *x * cpp;
2367
2368                 *y = (old_offset - new_offset) / pitch;
2369                 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2370         }
2371
2372         return new_offset;
2373 }
2374
2375 /*
2376  * Computes the linear offset to the base tile and adjusts
2377  * x, y. bytes per pixel is assumed to be a power-of-two.
2378  *
2379  * In the 90/270 rotated case, x and y are assumed
2380  * to be already rotated to match the rotated GTT view, and
2381  * pitch is the tile_height aligned framebuffer height.
2382  *
2383  * This function is used when computing the derived information
2384  * under intel_framebuffer, so using any of that information
2385  * here is not allowed. Anything under drm_framebuffer can be
2386  * used. This is why the user has to pass in the pitch since it
2387  * is specified in the rotated orientation.
2388  */
2389 static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv,
2390                                       int *x, int *y,
2391                                       const struct drm_framebuffer *fb, int plane,
2392                                       unsigned int pitch,
2393                                       unsigned int rotation,
2394                                       u32 alignment)
2395 {
2396         uint64_t fb_modifier = fb->modifier;
2397         unsigned int cpp = fb->format->cpp[plane];
2398         u32 offset, offset_aligned;
2399
2400         if (alignment)
2401                 alignment--;
2402
2403         if (fb_modifier != DRM_FORMAT_MOD_NONE) {
2404                 unsigned int tile_size, tile_width, tile_height;
2405                 unsigned int tile_rows, tiles, pitch_tiles;
2406
2407                 tile_size = intel_tile_size(dev_priv);
2408                 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2409                                 fb_modifier, cpp);
2410
2411                 if (drm_rotation_90_or_270(rotation)) {
2412                         pitch_tiles = pitch / tile_height;
2413                         swap(tile_width, tile_height);
2414                 } else {
2415                         pitch_tiles = pitch / (tile_width * cpp);
2416                 }
2417
2418                 tile_rows = *y / tile_height;
2419                 *y %= tile_height;
2420
2421                 tiles = *x / tile_width;
2422                 *x %= tile_width;
2423
2424                 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2425                 offset_aligned = offset & ~alignment;
2426
2427                 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2428                                           tile_size, pitch_tiles,
2429                                           offset, offset_aligned);
2430         } else {
2431                 offset = *y * pitch + *x * cpp;
2432                 offset_aligned = offset & ~alignment;
2433
2434                 *y = (offset & alignment) / pitch;
2435                 *x = ((offset & alignment) - *y * pitch) / cpp;
2436         }
2437
2438         return offset_aligned;
2439 }
2440
2441 u32 intel_compute_tile_offset(int *x, int *y,
2442                               const struct intel_plane_state *state,
2443                               int plane)
2444 {
2445         const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2446         const struct drm_framebuffer *fb = state->base.fb;
2447         unsigned int rotation = state->base.rotation;
2448         int pitch = intel_fb_pitch(fb, plane, rotation);
2449         u32 alignment;
2450
2451         /* AUX_DIST needs only 4K alignment */
2452         if (fb->format->format == DRM_FORMAT_NV12 && plane == 1)
2453                 alignment = 4096;
2454         else
2455                 alignment = intel_surf_alignment(dev_priv, fb->modifier);
2456
2457         return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch,
2458                                           rotation, alignment);
2459 }
2460
2461 /* Convert the fb->offset[] linear offset into x/y offsets */
2462 static void intel_fb_offset_to_xy(int *x, int *y,
2463                                   const struct drm_framebuffer *fb, int plane)
2464 {
2465         unsigned int cpp = fb->format->cpp[plane];
2466         unsigned int pitch = fb->pitches[plane];
2467         u32 linear_offset = fb->offsets[plane];
2468
2469         *y = linear_offset / pitch;
2470         *x = linear_offset % pitch / cpp;
2471 }
2472
2473 static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier)
2474 {
2475         switch (fb_modifier) {
2476         case I915_FORMAT_MOD_X_TILED:
2477                 return I915_TILING_X;
2478         case I915_FORMAT_MOD_Y_TILED:
2479                 return I915_TILING_Y;
2480         default:
2481                 return I915_TILING_NONE;
2482         }
2483 }
2484
2485 static int
2486 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2487                    struct drm_framebuffer *fb)
2488 {
2489         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2490         struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2491         u32 gtt_offset_rotated = 0;
2492         unsigned int max_size = 0;
2493         int i, num_planes = fb->format->num_planes;
2494         unsigned int tile_size = intel_tile_size(dev_priv);
2495
2496         for (i = 0; i < num_planes; i++) {
2497                 unsigned int width, height;
2498                 unsigned int cpp, size;
2499                 u32 offset;
2500                 int x, y;
2501
2502                 cpp = fb->format->cpp[i];
2503                 width = drm_framebuffer_plane_width(fb->width, fb, i);
2504                 height = drm_framebuffer_plane_height(fb->height, fb, i);
2505
2506                 intel_fb_offset_to_xy(&x, &y, fb, i);
2507
2508                 /*
2509                  * The fence (if used) is aligned to the start of the object
2510                  * so having the framebuffer wrap around across the edge of the
2511                  * fenced region doesn't really work. We have no API to configure
2512                  * the fence start offset within the object (nor could we probably
2513                  * on gen2/3). So it's just easier if we just require that the
2514                  * fb layout agrees with the fence layout. We already check that the
2515                  * fb stride matches the fence stride elsewhere.
2516                  */
2517                 if (i915_gem_object_is_tiled(intel_fb->obj) &&
2518                     (x + width) * cpp > fb->pitches[i]) {
2519                         DRM_DEBUG("bad fb plane %d offset: 0x%x\n",
2520                                   i, fb->offsets[i]);
2521                         return -EINVAL;
2522                 }
2523
2524                 /*
2525                  * First pixel of the framebuffer from
2526                  * the start of the normal gtt mapping.
2527                  */
2528                 intel_fb->normal[i].x = x;
2529                 intel_fb->normal[i].y = y;
2530
2531                 offset = _intel_compute_tile_offset(dev_priv, &x, &y,
2532                                                     fb, 0, fb->pitches[i],
2533                                                     DRM_ROTATE_0, tile_size);
2534                 offset /= tile_size;
2535
2536                 if (fb->modifier != DRM_FORMAT_MOD_NONE) {
2537                         unsigned int tile_width, tile_height;
2538                         unsigned int pitch_tiles;
2539                         struct drm_rect r;
2540
2541                         intel_tile_dims(dev_priv, &tile_width, &tile_height,
2542                                         fb->modifier, cpp);
2543
2544                         rot_info->plane[i].offset = offset;
2545                         rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2546                         rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2547                         rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2548
2549                         intel_fb->rotated[i].pitch =
2550                                 rot_info->plane[i].height * tile_height;
2551
2552                         /* how many tiles does this plane need */
2553                         size = rot_info->plane[i].stride * rot_info->plane[i].height;
2554                         /*
2555                          * If the plane isn't horizontally tile aligned,
2556                          * we need one more tile.
2557                          */
2558                         if (x != 0)
2559                                 size++;
2560
2561                         /* rotate the x/y offsets to match the GTT view */
2562                         r.x1 = x;
2563                         r.y1 = y;
2564                         r.x2 = x + width;
2565                         r.y2 = y + height;
2566                         drm_rect_rotate(&r,
2567                                         rot_info->plane[i].width * tile_width,
2568                                         rot_info->plane[i].height * tile_height,
2569                                         DRM_ROTATE_270);
2570                         x = r.x1;
2571                         y = r.y1;
2572
2573                         /* rotate the tile dimensions to match the GTT view */
2574                         pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2575                         swap(tile_width, tile_height);
2576
2577                         /*
2578                          * We only keep the x/y offsets, so push all of the
2579                          * gtt offset into the x/y offsets.
2580                          */
2581                         _intel_adjust_tile_offset(&x, &y,
2582                                                   tile_width, tile_height,
2583                                                   tile_size, pitch_tiles,
2584                                                   gtt_offset_rotated * tile_size, 0);
2585
2586                         gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2587
2588                         /*
2589                          * First pixel of the framebuffer from
2590                          * the start of the rotated gtt mapping.
2591                          */
2592                         intel_fb->rotated[i].x = x;
2593                         intel_fb->rotated[i].y = y;
2594                 } else {
2595                         size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2596                                             x * cpp, tile_size);
2597                 }
2598
2599                 /* how many tiles in total needed in the bo */
2600                 max_size = max(max_size, offset + size);
2601         }
2602
2603         if (max_size * tile_size > to_intel_framebuffer(fb)->obj->base.size) {
2604                 DRM_DEBUG("fb too big for bo (need %u bytes, have %zu bytes)\n",
2605                           max_size * tile_size, to_intel_framebuffer(fb)->obj->base.size);
2606                 return -EINVAL;
2607         }
2608
2609         return 0;
2610 }
2611
2612 static int i9xx_format_to_fourcc(int format)
2613 {
2614         switch (format) {
2615         case DISPPLANE_8BPP:
2616                 return DRM_FORMAT_C8;
2617         case DISPPLANE_BGRX555:
2618                 return DRM_FORMAT_XRGB1555;
2619         case DISPPLANE_BGRX565:
2620                 return DRM_FORMAT_RGB565;
2621         default:
2622         case DISPPLANE_BGRX888:
2623                 return DRM_FORMAT_XRGB8888;
2624         case DISPPLANE_RGBX888:
2625                 return DRM_FORMAT_XBGR8888;
2626         case DISPPLANE_BGRX101010:
2627                 return DRM_FORMAT_XRGB2101010;
2628         case DISPPLANE_RGBX101010:
2629                 return DRM_FORMAT_XBGR2101010;
2630         }
2631 }
2632
2633 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2634 {
2635         switch (format) {
2636         case PLANE_CTL_FORMAT_RGB_565:
2637                 return DRM_FORMAT_RGB565;
2638         default:
2639         case PLANE_CTL_FORMAT_XRGB_8888:
2640                 if (rgb_order) {
2641                         if (alpha)
2642                                 return DRM_FORMAT_ABGR8888;
2643                         else
2644                                 return DRM_FORMAT_XBGR8888;
2645                 } else {
2646                         if (alpha)
2647                                 return DRM_FORMAT_ARGB8888;
2648                         else
2649                                 return DRM_FORMAT_XRGB8888;
2650                 }
2651         case PLANE_CTL_FORMAT_XRGB_2101010:
2652                 if (rgb_order)
2653                         return DRM_FORMAT_XBGR2101010;
2654                 else
2655                         return DRM_FORMAT_XRGB2101010;
2656         }
2657 }
2658
2659 static bool
2660 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2661                               struct intel_initial_plane_config *plane_config)
2662 {
2663         struct drm_device *dev = crtc->base.dev;
2664         struct drm_i915_private *dev_priv = to_i915(dev);
2665         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2666         struct drm_i915_gem_object *obj = NULL;
2667         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2668         struct drm_framebuffer *fb = &plane_config->fb->base;
2669         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2670         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2671                                     PAGE_SIZE);
2672
2673         size_aligned -= base_aligned;
2674
2675         if (plane_config->size == 0)
2676                 return false;
2677
2678         /* If the FB is too big, just don't use it since fbdev is not very
2679          * important and we should probably use that space with FBC or other
2680          * features. */
2681         if (size_aligned * 2 > ggtt->stolen_usable_size)
2682                 return false;
2683
2684         mutex_lock(&dev->struct_mutex);
2685
2686         obj = i915_gem_object_create_stolen_for_preallocated(dev_priv,
2687                                                              base_aligned,
2688                                                              base_aligned,
2689                                                              size_aligned);
2690         if (!obj) {
2691                 mutex_unlock(&dev->struct_mutex);
2692                 return false;
2693         }
2694
2695         if (plane_config->tiling == I915_TILING_X)
2696                 obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X;
2697
2698         mode_cmd.pixel_format = fb->format->format;
2699         mode_cmd.width = fb->width;
2700         mode_cmd.height = fb->height;
2701         mode_cmd.pitches[0] = fb->pitches[0];
2702         mode_cmd.modifier[0] = fb->modifier;
2703         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2704
2705         if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2706                                    &mode_cmd, obj)) {
2707                 DRM_DEBUG_KMS("intel fb init failed\n");
2708                 goto out_unref_obj;
2709         }
2710
2711         mutex_unlock(&dev->struct_mutex);
2712
2713         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2714         return true;
2715
2716 out_unref_obj:
2717         i915_gem_object_put(obj);
2718         mutex_unlock(&dev->struct_mutex);
2719         return false;
2720 }
2721
2722 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2723 static void
2724 update_state_fb(struct drm_plane *plane)
2725 {
2726         if (plane->fb == plane->state->fb)
2727                 return;
2728
2729         if (plane->state->fb)
2730                 drm_framebuffer_unreference(plane->state->fb);
2731         plane->state->fb = plane->fb;
2732         if (plane->state->fb)
2733                 drm_framebuffer_reference(plane->state->fb);
2734 }
2735
2736 static void
2737 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2738                              struct intel_initial_plane_config *plane_config)
2739 {
2740         struct drm_device *dev = intel_crtc->base.dev;
2741         struct drm_i915_private *dev_priv = to_i915(dev);
2742         struct drm_crtc *c;
2743         struct drm_i915_gem_object *obj;
2744         struct drm_plane *primary = intel_crtc->base.primary;
2745         struct drm_plane_state *plane_state = primary->state;
2746         struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2747         struct intel_plane *intel_plane = to_intel_plane(primary);
2748         struct intel_plane_state *intel_state =
2749                 to_intel_plane_state(plane_state);
2750         struct drm_framebuffer *fb;
2751
2752         if (!plane_config->fb)
2753                 return;
2754
2755         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2756                 fb = &plane_config->fb->base;
2757                 goto valid_fb;
2758         }
2759
2760         kfree(plane_config->fb);
2761
2762         /*
2763          * Failed to alloc the obj, check to see if we should share
2764          * an fb with another CRTC instead
2765          */
2766         for_each_crtc(dev, c) {
2767                 struct intel_plane_state *state;
2768
2769                 if (c == &intel_crtc->base)
2770                         continue;
2771
2772                 if (!to_intel_crtc(c)->active)
2773                         continue;
2774
2775                 state = to_intel_plane_state(c->primary->state);
2776                 if (!state->vma)
2777                         continue;
2778
2779                 if (intel_plane_ggtt_offset(state) == plane_config->base) {
2780                         fb = c->primary->fb;
2781                         drm_framebuffer_reference(fb);
2782                         goto valid_fb;
2783                 }
2784         }
2785
2786         /*
2787          * We've failed to reconstruct the BIOS FB.  Current display state
2788          * indicates that the primary plane is visible, but has a NULL FB,
2789          * which will lead to problems later if we don't fix it up.  The
2790          * simplest solution is to just disable the primary plane now and
2791          * pretend the BIOS never had it enabled.
2792          */
2793         plane_state->visible = false;
2794         crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
2795         intel_pre_disable_primary_noatomic(&intel_crtc->base);
2796         intel_plane->disable_plane(primary, &intel_crtc->base);
2797
2798         return;
2799
2800 valid_fb:
2801         mutex_lock(&dev->struct_mutex);
2802         intel_state->vma =
2803                 intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
2804         mutex_unlock(&dev->struct_mutex);
2805         if (IS_ERR(intel_state->vma)) {
2806                 DRM_ERROR("failed to pin boot fb on pipe %d: %li\n",
2807                           intel_crtc->pipe, PTR_ERR(intel_state->vma));
2808
2809                 intel_state->vma = NULL;
2810                 drm_framebuffer_unreference(fb);
2811                 return;
2812         }
2813
2814         plane_state->src_x = 0;
2815         plane_state->src_y = 0;
2816         plane_state->src_w = fb->width << 16;
2817         plane_state->src_h = fb->height << 16;
2818
2819         plane_state->crtc_x = 0;
2820         plane_state->crtc_y = 0;
2821         plane_state->crtc_w = fb->width;
2822         plane_state->crtc_h = fb->height;
2823
2824         intel_state->base.src = drm_plane_state_src(plane_state);
2825         intel_state->base.dst = drm_plane_state_dest(plane_state);
2826
2827         obj = intel_fb_obj(fb);
2828         if (i915_gem_object_is_tiled(obj))
2829                 dev_priv->preserve_bios_swizzle = true;
2830
2831         drm_framebuffer_reference(fb);
2832         primary->fb = primary->state->fb = fb;
2833         primary->crtc = primary->state->crtc = &intel_crtc->base;
2834         intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2835         atomic_or(to_intel_plane(primary)->frontbuffer_bit,
2836                   &obj->frontbuffer_bits);
2837 }
2838
2839 static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane,
2840                                unsigned int rotation)
2841 {
2842         int cpp = fb->format->cpp[plane];
2843
2844         switch (fb->modifier) {
2845         case DRM_FORMAT_MOD_NONE:
2846         case I915_FORMAT_MOD_X_TILED:
2847                 switch (cpp) {
2848                 case 8:
2849                         return 4096;
2850                 case 4:
2851                 case 2:
2852                 case 1:
2853                         return 8192;
2854                 default:
2855                         MISSING_CASE(cpp);
2856                         break;
2857                 }
2858                 break;
2859         case I915_FORMAT_MOD_Y_TILED:
2860         case I915_FORMAT_MOD_Yf_TILED:
2861                 switch (cpp) {
2862                 case 8:
2863                         return 2048;
2864                 case 4:
2865                         return 4096;
2866                 case 2:
2867                 case 1:
2868                         return 8192;
2869                 default:
2870                         MISSING_CASE(cpp);
2871                         break;
2872                 }
2873                 break;
2874         default:
2875                 MISSING_CASE(fb->modifier);
2876         }
2877
2878         return 2048;
2879 }
2880
2881 static int skl_check_main_surface(struct intel_plane_state *plane_state)
2882 {
2883         const struct drm_i915_private *dev_priv = to_i915(plane_state->base.plane->dev);
2884         const struct drm_framebuffer *fb = plane_state->base.fb;
2885         unsigned int rotation = plane_state->base.rotation;
2886         int x = plane_state->base.src.x1 >> 16;
2887         int y = plane_state->base.src.y1 >> 16;
2888         int w = drm_rect_width(&plane_state->base.src) >> 16;
2889         int h = drm_rect_height(&plane_state->base.src) >> 16;
2890         int max_width = skl_max_plane_width(fb, 0, rotation);
2891         int max_height = 4096;
2892         u32 alignment, offset, aux_offset = plane_state->aux.offset;
2893
2894         if (w > max_width || h > max_height) {
2895                 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
2896                               w, h, max_width, max_height);
2897                 return -EINVAL;
2898         }
2899
2900         intel_add_fb_offsets(&x, &y, plane_state, 0);
2901         offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
2902
2903         alignment = intel_surf_alignment(dev_priv, fb->modifier);
2904
2905         /*
2906          * AUX surface offset is specified as the distance from the
2907          * main surface offset, and it must be non-negative. Make
2908          * sure that is what we will get.
2909          */
2910         if (offset > aux_offset)
2911                 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2912                                                   offset, aux_offset & ~(alignment - 1));
2913
2914         /*
2915          * When using an X-tiled surface, the plane blows up
2916          * if the x offset + width exceed the stride.
2917          *
2918          * TODO: linear and Y-tiled seem fine, Yf untested,
2919          */
2920         if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
2921                 int cpp = fb->format->cpp[0];
2922
2923                 while ((x + w) * cpp > fb->pitches[0]) {
2924                         if (offset == 0) {
2925                                 DRM_DEBUG_KMS("Unable to find suitable display surface offset\n");
2926                                 return -EINVAL;
2927                         }
2928
2929                         offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2930                                                           offset, offset - alignment);
2931                 }
2932         }
2933
2934         plane_state->main.offset = offset;
2935         plane_state->main.x = x;
2936         plane_state->main.y = y;
2937
2938         return 0;
2939 }
2940
2941 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
2942 {
2943         const struct drm_framebuffer *fb = plane_state->base.fb;
2944         unsigned int rotation = plane_state->base.rotation;
2945         int max_width = skl_max_plane_width(fb, 1, rotation);
2946         int max_height = 4096;
2947         int x = plane_state->base.src.x1 >> 17;
2948         int y = plane_state->base.src.y1 >> 17;
2949         int w = drm_rect_width(&plane_state->base.src) >> 17;
2950         int h = drm_rect_height(&plane_state->base.src) >> 17;
2951         u32 offset;
2952
2953         intel_add_fb_offsets(&x, &y, plane_state, 1);
2954         offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
2955
2956         /* FIXME not quite sure how/if these apply to the chroma plane */
2957         if (w > max_width || h > max_height) {
2958                 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
2959                               w, h, max_width, max_height);
2960                 return -EINVAL;
2961         }
2962
2963         plane_state->aux.offset = offset;
2964         plane_state->aux.x = x;
2965         plane_state->aux.y = y;
2966
2967         return 0;
2968 }
2969
2970 int skl_check_plane_surface(struct intel_plane_state *plane_state)
2971 {
2972         const struct drm_framebuffer *fb = plane_state->base.fb;
2973         unsigned int rotation = plane_state->base.rotation;
2974         int ret;
2975
2976         if (!plane_state->base.visible)
2977                 return 0;
2978
2979         /* Rotate src coordinates to match rotated GTT view */
2980         if (drm_rotation_90_or_270(rotation))
2981                 drm_rect_rotate(&plane_state->base.src,
2982                                 fb->width << 16, fb->height << 16,
2983                                 DRM_ROTATE_270);
2984
2985         /*
2986          * Handle the AUX surface first since
2987          * the main surface setup depends on it.
2988          */
2989         if (fb->format->format == DRM_FORMAT_NV12) {
2990                 ret = skl_check_nv12_aux_surface(plane_state);
2991                 if (ret)
2992                         return ret;
2993         } else {
2994                 plane_state->aux.offset = ~0xfff;
2995                 plane_state->aux.x = 0;
2996                 plane_state->aux.y = 0;
2997         }
2998
2999         ret = skl_check_main_surface(plane_state);
3000         if (ret)
3001                 return ret;
3002
3003         return 0;
3004 }
3005
3006 static void i9xx_update_primary_plane(struct drm_plane *primary,
3007                                       const struct intel_crtc_state *crtc_state,
3008                                       const struct intel_plane_state *plane_state)
3009 {
3010         struct drm_i915_private *dev_priv = to_i915(primary->dev);
3011         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3012         struct drm_framebuffer *fb = plane_state->base.fb;
3013         int plane = intel_crtc->plane;
3014         u32 linear_offset;
3015         u32 dspcntr;
3016         i915_reg_t reg = DSPCNTR(plane);
3017         unsigned int rotation = plane_state->base.rotation;
3018         int x = plane_state->base.src.x1 >> 16;
3019         int y = plane_state->base.src.y1 >> 16;
3020
3021         dspcntr = DISPPLANE_GAMMA_ENABLE;
3022
3023         dspcntr |= DISPLAY_PLANE_ENABLE;
3024
3025         if (INTEL_GEN(dev_priv) < 4) {
3026                 if (intel_crtc->pipe == PIPE_B)
3027                         dspcntr |= DISPPLANE_SEL_PIPE_B;
3028
3029                 /* pipesrc and dspsize control the size that is scaled from,
3030                  * which should always be the user's requested size.
3031                  */
3032                 I915_WRITE(DSPSIZE(plane),
3033                            ((crtc_state->pipe_src_h - 1) << 16) |
3034                            (crtc_state->pipe_src_w - 1));
3035                 I915_WRITE(DSPPOS(plane), 0);
3036         } else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) {
3037                 I915_WRITE(PRIMSIZE(plane),
3038                            ((crtc_state->pipe_src_h - 1) << 16) |
3039                            (crtc_state->pipe_src_w - 1));
3040                 I915_WRITE(PRIMPOS(plane), 0);
3041                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
3042         }
3043
3044         switch (fb->format->format) {
3045         case DRM_FORMAT_C8:
3046                 dspcntr |= DISPPLANE_8BPP;
3047                 break;
3048         case DRM_FORMAT_XRGB1555:
3049                 dspcntr |= DISPPLANE_BGRX555;
3050                 break;
3051         case DRM_FORMAT_RGB565:
3052                 dspcntr |= DISPPLANE_BGRX565;
3053                 break;
3054         case DRM_FORMAT_XRGB8888:
3055                 dspcntr |= DISPPLANE_BGRX888;
3056                 break;
3057         case DRM_FORMAT_XBGR8888:
3058                 dspcntr |= DISPPLANE_RGBX888;
3059                 break;
3060         case DRM_FORMAT_XRGB2101010:
3061                 dspcntr |= DISPPLANE_BGRX101010;
3062                 break;
3063         case DRM_FORMAT_XBGR2101010:
3064                 dspcntr |= DISPPLANE_RGBX101010;
3065                 break;
3066         default:
3067                 BUG();
3068         }
3069
3070         if (INTEL_GEN(dev_priv) >= 4 &&
3071             fb->modifier == I915_FORMAT_MOD_X_TILED)
3072                 dspcntr |= DISPPLANE_TILED;
3073
3074         if (rotation & DRM_ROTATE_180)
3075                 dspcntr |= DISPPLANE_ROTATE_180;
3076
3077         if (rotation & DRM_REFLECT_X)
3078                 dspcntr |= DISPPLANE_MIRROR;
3079
3080         if (IS_G4X(dev_priv))
3081                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3082
3083         intel_add_fb_offsets(&x, &y, plane_state, 0);
3084
3085         if (INTEL_GEN(dev_priv) >= 4)
3086                 intel_crtc->dspaddr_offset =
3087                         intel_compute_tile_offset(&x, &y, plane_state, 0);
3088
3089         if (rotation & DRM_ROTATE_180) {
3090                 x += crtc_state->pipe_src_w - 1;
3091                 y += crtc_state->pipe_src_h - 1;
3092         } else if (rotation & DRM_REFLECT_X) {
3093                 x += crtc_state->pipe_src_w - 1;
3094         }
3095
3096         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3097
3098         if (INTEL_GEN(dev_priv) < 4)
3099                 intel_crtc->dspaddr_offset = linear_offset;
3100
3101         intel_crtc->adjusted_x = x;
3102         intel_crtc->adjusted_y = y;
3103
3104         I915_WRITE(reg, dspcntr);
3105
3106         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
3107         if (INTEL_GEN(dev_priv) >= 4) {
3108                 I915_WRITE(DSPSURF(plane),
3109                            intel_plane_ggtt_offset(plane_state) +
3110                            intel_crtc->dspaddr_offset);
3111                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
3112                 I915_WRITE(DSPLINOFF(plane), linear_offset);
3113         } else {
3114                 I915_WRITE(DSPADDR(plane),
3115                            intel_plane_ggtt_offset(plane_state) +
3116                            intel_crtc->dspaddr_offset);
3117         }
3118         POSTING_READ(reg);
3119 }
3120
3121 static void i9xx_disable_primary_plane(struct drm_plane *primary,
3122                                        struct drm_crtc *crtc)
3123 {
3124         struct drm_device *dev = crtc->dev;
3125         struct drm_i915_private *dev_priv = to_i915(dev);
3126         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3127         int plane = intel_crtc->plane;
3128
3129         I915_WRITE(DSPCNTR(plane), 0);
3130         if (INTEL_INFO(dev_priv)->gen >= 4)
3131                 I915_WRITE(DSPSURF(plane), 0);
3132         else
3133                 I915_WRITE(DSPADDR(plane), 0);
3134         POSTING_READ(DSPCNTR(plane));
3135 }
3136
3137 static void ironlake_update_primary_plane(struct drm_plane *primary,
3138                                           const struct intel_crtc_state *crtc_state,
3139                                           const struct intel_plane_state *plane_state)
3140 {
3141         struct drm_device *dev = primary->dev;
3142         struct drm_i915_private *dev_priv = to_i915(dev);
3143         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3144         struct drm_framebuffer *fb = plane_state->base.fb;
3145         int plane = intel_crtc->plane;
3146         u32 linear_offset;
3147         u32 dspcntr;
3148         i915_reg_t reg = DSPCNTR(plane);
3149         unsigned int rotation = plane_state->base.rotation;
3150         int x = plane_state->base.src.x1 >> 16;
3151         int y = plane_state->base.src.y1 >> 16;
3152
3153         dspcntr = DISPPLANE_GAMMA_ENABLE;
3154         dspcntr |= DISPLAY_PLANE_ENABLE;
3155
3156         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
3157                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
3158
3159         switch (fb->format->format) {
3160         case DRM_FORMAT_C8:
3161                 dspcntr |= DISPPLANE_8BPP;
3162                 break;
3163         case DRM_FORMAT_RGB565:
3164                 dspcntr |= DISPPLANE_BGRX565;
3165                 break;
3166         case DRM_FORMAT_XRGB8888:
3167                 dspcntr |= DISPPLANE_BGRX888;
3168                 break;
3169         case DRM_FORMAT_XBGR8888:
3170                 dspcntr |= DISPPLANE_RGBX888;
3171                 break;
3172         case DRM_FORMAT_XRGB2101010:
3173                 dspcntr |= DISPPLANE_BGRX101010;
3174                 break;
3175         case DRM_FORMAT_XBGR2101010:
3176                 dspcntr |= DISPPLANE_RGBX101010;
3177                 break;
3178         default:
3179                 BUG();
3180         }
3181
3182         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
3183                 dspcntr |= DISPPLANE_TILED;
3184
3185         if (rotation & DRM_ROTATE_180)
3186                 dspcntr |= DISPPLANE_ROTATE_180;
3187
3188         if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv))
3189                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3190
3191         intel_add_fb_offsets(&x, &y, plane_state, 0);
3192
3193         intel_crtc->dspaddr_offset =
3194                 intel_compute_tile_offset(&x, &y, plane_state, 0);
3195
3196         /* HSW+ does this automagically in hardware */
3197         if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv) &&
3198             rotation & DRM_ROTATE_180) {
3199                 x += crtc_state->pipe_src_w - 1;
3200                 y += crtc_state->pipe_src_h - 1;
3201         }
3202
3203         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3204
3205         intel_crtc->adjusted_x = x;
3206         intel_crtc->adjusted_y = y;
3207
3208         I915_WRITE(reg, dspcntr);
3209
3210         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
3211         I915_WRITE(DSPSURF(plane),
3212                    intel_plane_ggtt_offset(plane_state) +
3213                    intel_crtc->dspaddr_offset);
3214         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3215                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
3216         } else {
3217                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
3218                 I915_WRITE(DSPLINOFF(plane), linear_offset);
3219         }
3220         POSTING_READ(reg);
3221 }
3222
3223 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
3224                               uint64_t fb_modifier, uint32_t pixel_format)
3225 {
3226         if (fb_modifier == DRM_FORMAT_MOD_NONE) {
3227                 return 64;
3228         } else {
3229                 int cpp = drm_format_plane_cpp(pixel_format, 0);
3230
3231                 return intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
3232         }
3233 }
3234
3235 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
3236 {
3237         struct drm_device *dev = intel_crtc->base.dev;
3238         struct drm_i915_private *dev_priv = to_i915(dev);
3239
3240         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
3241         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
3242         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
3243 }
3244
3245 /*
3246  * This function detaches (aka. unbinds) unused scalers in hardware
3247  */
3248 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
3249 {
3250         struct intel_crtc_scaler_state *scaler_state;
3251         int i;
3252
3253         scaler_state = &intel_crtc->config->scaler_state;
3254
3255         /* loop through and disable scalers that aren't in use */
3256         for (i = 0; i < intel_crtc->num_scalers; i++) {
3257                 if (!scaler_state->scalers[i].in_use)
3258                         skl_detach_scaler(intel_crtc, i);
3259         }
3260 }
3261
3262 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
3263                      unsigned int rotation)
3264 {
3265         const struct drm_i915_private *dev_priv = to_i915(fb->dev);
3266         u32 stride = intel_fb_pitch(fb, plane, rotation);
3267
3268         /*
3269          * The stride is either expressed as a multiple of 64 bytes chunks for
3270          * linear buffers or in number of tiles for tiled buffers.
3271          */
3272         if (drm_rotation_90_or_270(rotation)) {
3273                 int cpp = fb->format->cpp[plane];
3274
3275                 stride /= intel_tile_height(dev_priv, fb->modifier, cpp);
3276         } else {
3277                 stride /= intel_fb_stride_alignment(dev_priv, fb->modifier,
3278                                                     fb->format->format);
3279         }
3280
3281         return stride;
3282 }
3283
3284 u32 skl_plane_ctl_format(uint32_t pixel_format)
3285 {
3286         switch (pixel_format) {
3287         case DRM_FORMAT_C8:
3288                 return PLANE_CTL_FORMAT_INDEXED;
3289         case DRM_FORMAT_RGB565:
3290                 return PLANE_CTL_FORMAT_RGB_565;
3291         case DRM_FORMAT_XBGR8888:
3292                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3293         case DRM_FORMAT_XRGB8888:
3294                 return PLANE_CTL_FORMAT_XRGB_8888;
3295         /*
3296          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3297          * to be already pre-multiplied. We need to add a knob (or a different
3298          * DRM_FORMAT) for user-space to configure that.
3299          */
3300         case DRM_FORMAT_ABGR8888:
3301                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3302                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3303         case DRM_FORMAT_ARGB8888:
3304                 return PLANE_CTL_FORMAT_XRGB_8888 |
3305                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3306         case DRM_FORMAT_XRGB2101010:
3307                 return PLANE_CTL_FORMAT_XRGB_2101010;
3308         case DRM_FORMAT_XBGR2101010:
3309                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3310         case DRM_FORMAT_YUYV:
3311                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3312         case DRM_FORMAT_YVYU:
3313                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3314         case DRM_FORMAT_UYVY:
3315                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3316         case DRM_FORMAT_VYUY:
3317                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3318         default:
3319                 MISSING_CASE(pixel_format);
3320         }
3321
3322         return 0;
3323 }
3324
3325 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3326 {
3327         switch (fb_modifier) {
3328         case DRM_FORMAT_MOD_NONE:
3329                 break;
3330         case I915_FORMAT_MOD_X_TILED:
3331                 return PLANE_CTL_TILED_X;
3332         case I915_FORMAT_MOD_Y_TILED:
3333                 return PLANE_CTL_TILED_Y;
3334         case I915_FORMAT_MOD_Yf_TILED:
3335                 return PLANE_CTL_TILED_YF;
3336         default:
3337                 MISSING_CASE(fb_modifier);
3338         }
3339
3340         return 0;
3341 }
3342
3343 u32 skl_plane_ctl_rotation(unsigned int rotation)
3344 {
3345         switch (rotation) {
3346         case DRM_ROTATE_0:
3347                 break;
3348         /*
3349          * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3350          * while i915 HW rotation is clockwise, thats why this swapping.
3351          */
3352         case DRM_ROTATE_90:
3353                 return PLANE_CTL_ROTATE_270;
3354         case DRM_ROTATE_180:
3355                 return PLANE_CTL_ROTATE_180;
3356         case DRM_ROTATE_270:
3357                 return PLANE_CTL_ROTATE_90;
3358         default:
3359                 MISSING_CASE(rotation);
3360         }
3361
3362         return 0;
3363 }
3364
3365 static void skylake_update_primary_plane(struct drm_plane *plane,
3366                                          const struct intel_crtc_state *crtc_state,
3367                                          const struct intel_plane_state *plane_state)
3368 {
3369         struct drm_device *dev = plane->dev;
3370         struct drm_i915_private *dev_priv = to_i915(dev);
3371         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3372         struct drm_framebuffer *fb = plane_state->base.fb;
3373         enum plane_id plane_id = to_intel_plane(plane)->id;
3374         enum pipe pipe = to_intel_plane(plane)->pipe;
3375         u32 plane_ctl;
3376         unsigned int rotation = plane_state->base.rotation;
3377         u32 stride = skl_plane_stride(fb, 0, rotation);
3378         u32 surf_addr = plane_state->main.offset;
3379         int scaler_id = plane_state->scaler_id;
3380         int src_x = plane_state->main.x;
3381         int src_y = plane_state->main.y;
3382         int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3383         int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3384         int dst_x = plane_state->base.dst.x1;
3385         int dst_y = plane_state->base.dst.y1;
3386         int dst_w = drm_rect_width(&plane_state->base.dst);
3387         int dst_h = drm_rect_height(&plane_state->base.dst);
3388
3389         plane_ctl = PLANE_CTL_ENABLE |
3390                     PLANE_CTL_PIPE_GAMMA_ENABLE |
3391                     PLANE_CTL_PIPE_CSC_ENABLE;
3392
3393         plane_ctl |= skl_plane_ctl_format(fb->format->format);
3394         plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
3395         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3396         plane_ctl |= skl_plane_ctl_rotation(rotation);
3397
3398         /* Sizes are 0 based */
3399         src_w--;
3400         src_h--;
3401         dst_w--;
3402         dst_h--;
3403
3404         intel_crtc->dspaddr_offset = surf_addr;
3405
3406         intel_crtc->adjusted_x = src_x;
3407         intel_crtc->adjusted_y = src_y;
3408
3409         I915_WRITE(PLANE_CTL(pipe, plane_id), plane_ctl);
3410         I915_WRITE(PLANE_OFFSET(pipe, plane_id), (src_y << 16) | src_x);
3411         I915_WRITE(PLANE_STRIDE(pipe, plane_id), stride);
3412         I915_WRITE(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
3413
3414         if (scaler_id >= 0) {
3415                 uint32_t ps_ctrl = 0;
3416
3417                 WARN_ON(!dst_w || !dst_h);
3418                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane_id) |
3419                         crtc_state->scaler_state.scalers[scaler_id].mode;
3420                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3421                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3422                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3423                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3424                 I915_WRITE(PLANE_POS(pipe, plane_id), 0);
3425         } else {
3426                 I915_WRITE(PLANE_POS(pipe, plane_id), (dst_y << 16) | dst_x);
3427         }
3428
3429         I915_WRITE(PLANE_SURF(pipe, plane_id),
3430                    intel_plane_ggtt_offset(plane_state) + surf_addr);
3431
3432         POSTING_READ(PLANE_SURF(pipe, plane_id));
3433 }
3434
3435 static void skylake_disable_primary_plane(struct drm_plane *primary,
3436                                           struct drm_crtc *crtc)
3437 {
3438         struct drm_device *dev = crtc->dev;
3439         struct drm_i915_private *dev_priv = to_i915(dev);
3440         enum plane_id plane_id = to_intel_plane(primary)->id;
3441         enum pipe pipe = to_intel_plane(primary)->pipe;
3442
3443         I915_WRITE(PLANE_CTL(pipe, plane_id), 0);
3444         I915_WRITE(PLANE_SURF(pipe, plane_id), 0);
3445         POSTING_READ(PLANE_SURF(pipe, plane_id));
3446 }
3447
3448 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3449 static int
3450 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3451                            int x, int y, enum mode_set_atomic state)
3452 {
3453         /* Support for kgdboc is disabled, this needs a major rework. */
3454         DRM_ERROR("legacy panic handler not supported any more.\n");
3455
3456         return -ENODEV;
3457 }
3458
3459 static void intel_complete_page_flips(struct drm_i915_private *dev_priv)
3460 {
3461         struct intel_crtc *crtc;
3462
3463         for_each_intel_crtc(&dev_priv->drm, crtc)
3464                 intel_finish_page_flip_cs(dev_priv, crtc->pipe);
3465 }
3466
3467 static void intel_update_primary_planes(struct drm_device *dev)
3468 {
3469         struct drm_crtc *crtc;
3470
3471         for_each_crtc(dev, crtc) {
3472                 struct intel_plane *plane = to_intel_plane(crtc->primary);
3473                 struct intel_plane_state *plane_state =
3474                         to_intel_plane_state(plane->base.state);
3475
3476                 if (plane_state->base.visible)
3477                         plane->update_plane(&plane->base,
3478                                             to_intel_crtc_state(crtc->state),
3479                                             plane_state);
3480         }
3481 }
3482
3483 static int
3484 __intel_display_resume(struct drm_device *dev,
3485                        struct drm_atomic_state *state)
3486 {
3487         struct drm_crtc_state *crtc_state;
3488         struct drm_crtc *crtc;
3489         int i, ret;
3490
3491         intel_modeset_setup_hw_state(dev);
3492         i915_redisable_vga(to_i915(dev));
3493
3494         if (!state)
3495                 return 0;
3496
3497         for_each_crtc_in_state(state, crtc, crtc_state, i) {
3498                 /*
3499                  * Force recalculation even if we restore
3500                  * current state. With fast modeset this may not result
3501                  * in a modeset when the state is compatible.
3502                  */
3503                 crtc_state->mode_changed = true;
3504         }
3505
3506         /* ignore any reset values/BIOS leftovers in the WM registers */
3507         to_intel_atomic_state(state)->skip_intermediate_wm = true;
3508
3509         ret = drm_atomic_commit(state);
3510
3511         WARN_ON(ret == -EDEADLK);
3512         return ret;
3513 }
3514
3515 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
3516 {
3517         return intel_has_gpu_reset(dev_priv) &&
3518                 INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv);
3519 }
3520
3521 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3522 {
3523         struct drm_device *dev = &dev_priv->drm;
3524         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3525         struct drm_atomic_state *state;
3526         int ret;
3527
3528         /*
3529          * Need mode_config.mutex so that we don't
3530          * trample ongoing ->detect() and whatnot.
3531          */
3532         mutex_lock(&dev->mode_config.mutex);
3533         drm_modeset_acquire_init(ctx, 0);
3534         while (1) {
3535                 ret = drm_modeset_lock_all_ctx(dev, ctx);
3536                 if (ret != -EDEADLK)
3537                         break;
3538
3539                 drm_modeset_backoff(ctx);
3540         }
3541
3542         /* reset doesn't touch the display, but flips might get nuked anyway, */
3543         if (!i915.force_reset_modeset_test &&
3544             !gpu_reset_clobbers_display(dev_priv))
3545                 return;
3546
3547         /*
3548          * Disabling the crtcs gracefully seems nicer. Also the
3549          * g33 docs say we should at least disable all the planes.
3550          */
3551         state = drm_atomic_helper_duplicate_state(dev, ctx);
3552         if (IS_ERR(state)) {
3553                 ret = PTR_ERR(state);
3554                 DRM_ERROR("Duplicating state failed with %i\n", ret);
3555                 return;
3556         }
3557
3558         ret = drm_atomic_helper_disable_all(dev, ctx);
3559         if (ret) {
3560                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
3561                 drm_atomic_state_put(state);
3562                 return;
3563         }
3564
3565         dev_priv->modeset_restore_state = state;
3566         state->acquire_ctx = ctx;
3567 }
3568
3569 void intel_finish_reset(struct drm_i915_private *dev_priv)
3570 {
3571         struct drm_device *dev = &dev_priv->drm;
3572         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3573         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
3574         int ret;
3575
3576         /*
3577          * Flips in the rings will be nuked by the reset,
3578          * so complete all pending flips so that user space
3579          * will get its events and not get stuck.
3580          */
3581         intel_complete_page_flips(dev_priv);
3582
3583         dev_priv->modeset_restore_state = NULL;
3584
3585         /* reset doesn't touch the display */
3586         if (!gpu_reset_clobbers_display(dev_priv)) {
3587                 if (!state) {
3588                         /*
3589                          * Flips in the rings have been nuked by the reset,
3590                          * so update the base address of all primary
3591                          * planes to the the last fb to make sure we're
3592                          * showing the correct fb after a reset.
3593                          *
3594                          * FIXME: Atomic will make this obsolete since we won't schedule
3595                          * CS-based flips (which might get lost in gpu resets) any more.
3596                          */
3597                         intel_update_primary_planes(dev);
3598                 } else {
3599                         ret = __intel_display_resume(dev, state);
3600                         if (ret)
3601                                 DRM_ERROR("Restoring old state failed with %i\n", ret);
3602                 }
3603         } else {
3604                 /*
3605                  * The display has been reset as well,
3606                  * so need a full re-initialization.
3607                  */
3608                 intel_runtime_pm_disable_interrupts(dev_priv);
3609                 intel_runtime_pm_enable_interrupts(dev_priv);
3610
3611                 intel_pps_unlock_regs_wa(dev_priv);
3612                 intel_modeset_init_hw(dev);
3613
3614                 spin_lock_irq(&dev_priv->irq_lock);
3615                 if (dev_priv->display.hpd_irq_setup)
3616                         dev_priv->display.hpd_irq_setup(dev_priv);
3617                 spin_unlock_irq(&dev_priv->irq_lock);
3618
3619                 ret = __intel_display_resume(dev, state);
3620                 if (ret)
3621                         DRM_ERROR("Restoring old state failed with %i\n", ret);
3622
3623                 intel_hpd_init(dev_priv);
3624         }
3625
3626         if (state)
3627                 drm_atomic_state_put(state);
3628         drm_modeset_drop_locks(ctx);
3629         drm_modeset_acquire_fini(ctx);
3630         mutex_unlock(&dev->mode_config.mutex);
3631 }
3632
3633 static bool abort_flip_on_reset(struct intel_crtc *crtc)
3634 {
3635         struct i915_gpu_error *error = &to_i915(crtc->base.dev)->gpu_error;
3636
3637         if (i915_reset_in_progress(error))
3638                 return true;
3639
3640         if (crtc->reset_count != i915_reset_count(error))
3641                 return true;
3642
3643         return false;
3644 }
3645
3646 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3647 {
3648         struct drm_device *dev = crtc->dev;
3649         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3650         bool pending;
3651
3652         if (abort_flip_on_reset(intel_crtc))
3653                 return false;
3654
3655         spin_lock_irq(&dev->event_lock);
3656         pending = to_intel_crtc(crtc)->flip_work != NULL;
3657         spin_unlock_irq(&dev->event_lock);
3658
3659         return pending;
3660 }
3661
3662 static void intel_update_pipe_config(struct intel_crtc *crtc,
3663                                      struct intel_crtc_state *old_crtc_state)
3664 {
3665         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3666         struct intel_crtc_state *pipe_config =
3667                 to_intel_crtc_state(crtc->base.state);
3668
3669         /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3670         crtc->base.mode = crtc->base.state->mode;
3671
3672         DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3673                       old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3674                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3675
3676         /*
3677          * Update pipe size and adjust fitter if needed: the reason for this is
3678          * that in compute_mode_changes we check the native mode (not the pfit
3679          * mode) to see if we can flip rather than do a full mode set. In the
3680          * fastboot case, we'll flip, but if we don't update the pipesrc and
3681          * pfit state, we'll end up with a big fb scanned out into the wrong
3682          * sized surface.
3683          */
3684
3685         I915_WRITE(PIPESRC(crtc->pipe),
3686                    ((pipe_config->pipe_src_w - 1) << 16) |
3687                    (pipe_config->pipe_src_h - 1));
3688
3689         /* on skylake this is done by detaching scalers */
3690         if (INTEL_GEN(dev_priv) >= 9) {
3691                 skl_detach_scalers(crtc);
3692
3693                 if (pipe_config->pch_pfit.enabled)
3694                         skylake_pfit_enable(crtc);
3695         } else if (HAS_PCH_SPLIT(dev_priv)) {
3696                 if (pipe_config->pch_pfit.enabled)
3697                         ironlake_pfit_enable(crtc);
3698                 else if (old_crtc_state->pch_pfit.enabled)
3699                         ironlake_pfit_disable(crtc, true);
3700         }
3701 }
3702
3703 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3704 {
3705         struct drm_device *dev = crtc->dev;
3706         struct drm_i915_private *dev_priv = to_i915(dev);
3707         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3708         int pipe = intel_crtc->pipe;
3709         i915_reg_t reg;
3710         u32 temp;
3711
3712         /* enable normal train */
3713         reg = FDI_TX_CTL(pipe);
3714         temp = I915_READ(reg);
3715         if (IS_IVYBRIDGE(dev_priv)) {
3716                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3717                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3718         } else {
3719                 temp &= ~FDI_LINK_TRAIN_NONE;
3720                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3721         }
3722         I915_WRITE(reg, temp);
3723
3724         reg = FDI_RX_CTL(pipe);
3725         temp = I915_READ(reg);
3726         if (HAS_PCH_CPT(dev_priv)) {
3727                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3728                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3729         } else {
3730                 temp &= ~FDI_LINK_TRAIN_NONE;
3731                 temp |= FDI_LINK_TRAIN_NONE;
3732         }
3733         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3734
3735         /* wait one idle pattern time */
3736         POSTING_READ(reg);
3737         udelay(1000);
3738
3739         /* IVB wants error correction enabled */
3740         if (IS_IVYBRIDGE(dev_priv))
3741                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3742                            FDI_FE_ERRC_ENABLE);
3743 }
3744
3745 /* The FDI link training functions for ILK/Ibexpeak. */
3746 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3747 {
3748         struct drm_device *dev = crtc->dev;
3749         struct drm_i915_private *dev_priv = to_i915(dev);
3750         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3751         int pipe = intel_crtc->pipe;
3752         i915_reg_t reg;
3753         u32 temp, tries;
3754
3755         /* FDI needs bits from pipe first */
3756         assert_pipe_enabled(dev_priv, pipe);
3757
3758         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3759            for train result */
3760         reg = FDI_RX_IMR(pipe);
3761         temp = I915_READ(reg);
3762         temp &= ~FDI_RX_SYMBOL_LOCK;
3763         temp &= ~FDI_RX_BIT_LOCK;
3764         I915_WRITE(reg, temp);
3765         I915_READ(reg);
3766         udelay(150);
3767
3768         /* enable CPU FDI TX and PCH FDI RX */
3769         reg = FDI_TX_CTL(pipe);
3770         temp = I915_READ(reg);
3771         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3772         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3773         temp &= ~FDI_LINK_TRAIN_NONE;
3774         temp |= FDI_LINK_TRAIN_PATTERN_1;
3775         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3776
3777         reg = FDI_RX_CTL(pipe);
3778         temp = I915_READ(reg);
3779         temp &= ~FDI_LINK_TRAIN_NONE;
3780         temp |= FDI_LINK_TRAIN_PATTERN_1;
3781         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3782
3783         POSTING_READ(reg);
3784         udelay(150);
3785
3786         /* Ironlake workaround, enable clock pointer after FDI enable*/
3787         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3788         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3789                    FDI_RX_PHASE_SYNC_POINTER_EN);
3790
3791         reg = FDI_RX_IIR(pipe);
3792         for (tries = 0; tries < 5; tries++) {
3793                 temp = I915_READ(reg);
3794                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3795
3796                 if ((temp & FDI_RX_BIT_LOCK)) {
3797                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3798                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3799                         break;
3800                 }
3801         }
3802         if (tries == 5)
3803                 DRM_ERROR("FDI train 1 fail!\n");
3804
3805         /* Train 2 */
3806         reg = FDI_TX_CTL(pipe);
3807         temp = I915_READ(reg);
3808         temp &= ~FDI_LINK_TRAIN_NONE;
3809         temp |= FDI_LINK_TRAIN_PATTERN_2;
3810         I915_WRITE(reg, temp);
3811
3812         reg = FDI_RX_CTL(pipe);
3813         temp = I915_READ(reg);
3814         temp &= ~FDI_LINK_TRAIN_NONE;
3815         temp |= FDI_LINK_TRAIN_PATTERN_2;
3816         I915_WRITE(reg, temp);
3817
3818         POSTING_READ(reg);
3819         udelay(150);
3820
3821         reg = FDI_RX_IIR(pipe);
3822         for (tries = 0; tries < 5; tries++) {
3823                 temp = I915_READ(reg);
3824                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3825
3826                 if (temp & FDI_RX_SYMBOL_LOCK) {
3827                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3828                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3829                         break;
3830                 }
3831         }
3832         if (tries == 5)
3833                 DRM_ERROR("FDI train 2 fail!\n");
3834
3835         DRM_DEBUG_KMS("FDI train done\n");
3836
3837 }
3838
3839 static const int snb_b_fdi_train_param[] = {
3840         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3841         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3842         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3843         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3844 };
3845
3846 /* The FDI link training functions for SNB/Cougarpoint. */
3847 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3848 {
3849         struct drm_device *dev = crtc->dev;
3850         struct drm_i915_private *dev_priv = to_i915(dev);
3851         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3852         int pipe = intel_crtc->pipe;
3853         i915_reg_t reg;
3854         u32 temp, i, retry;
3855
3856         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3857            for train result */
3858         reg = FDI_RX_IMR(pipe);
3859         temp = I915_READ(reg);
3860         temp &= ~FDI_RX_SYMBOL_LOCK;
3861         temp &= ~FDI_RX_BIT_LOCK;
3862         I915_WRITE(reg, temp);
3863
3864         POSTING_READ(reg);
3865         udelay(150);
3866
3867         /* enable CPU FDI TX and PCH FDI RX */
3868         reg = FDI_TX_CTL(pipe);
3869         temp = I915_READ(reg);
3870         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3871         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3872         temp &= ~FDI_LINK_TRAIN_NONE;
3873         temp |= FDI_LINK_TRAIN_PATTERN_1;
3874         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3875         /* SNB-B */
3876         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3877         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3878
3879         I915_WRITE(FDI_RX_MISC(pipe),
3880                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3881
3882         reg = FDI_RX_CTL(pipe);
3883         temp = I915_READ(reg);
3884         if (HAS_PCH_CPT(dev_priv)) {
3885                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3886                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3887         } else {
3888                 temp &= ~FDI_LINK_TRAIN_NONE;
3889                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3890         }
3891         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3892
3893         POSTING_READ(reg);
3894         udelay(150);
3895
3896         for (i = 0; i < 4; i++) {
3897                 reg = FDI_TX_CTL(pipe);
3898                 temp = I915_READ(reg);
3899                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3900                 temp |= snb_b_fdi_train_param[i];
3901                 I915_WRITE(reg, temp);
3902
3903                 POSTING_READ(reg);
3904                 udelay(500);
3905
3906                 for (retry = 0; retry < 5; retry++) {
3907                         reg = FDI_RX_IIR(pipe);
3908                         temp = I915_READ(reg);
3909                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3910                         if (temp & FDI_RX_BIT_LOCK) {
3911                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3912                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3913                                 break;
3914                         }
3915                         udelay(50);
3916                 }
3917                 if (retry < 5)
3918                         break;
3919         }
3920         if (i == 4)
3921                 DRM_ERROR("FDI train 1 fail!\n");
3922
3923         /* Train 2 */
3924         reg = FDI_TX_CTL(pipe);
3925         temp = I915_READ(reg);
3926         temp &= ~FDI_LINK_TRAIN_NONE;
3927         temp |= FDI_LINK_TRAIN_PATTERN_2;
3928         if (IS_GEN6(dev_priv)) {
3929                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3930                 /* SNB-B */
3931                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3932         }
3933         I915_WRITE(reg, temp);
3934
3935         reg = FDI_RX_CTL(pipe);
3936         temp = I915_READ(reg);
3937         if (HAS_PCH_CPT(dev_priv)) {
3938                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3939                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3940         } else {
3941                 temp &= ~FDI_LINK_TRAIN_NONE;
3942                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3943         }
3944         I915_WRITE(reg, temp);
3945
3946         POSTING_READ(reg);
3947         udelay(150);
3948
3949         for (i = 0; i < 4; i++) {
3950                 reg = FDI_TX_CTL(pipe);
3951                 temp = I915_READ(reg);
3952                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3953                 temp |= snb_b_fdi_train_param[i];
3954                 I915_WRITE(reg, temp);
3955
3956                 POSTING_READ(reg);
3957                 udelay(500);
3958
3959                 for (retry = 0; retry < 5; retry++) {
3960                         reg = FDI_RX_IIR(pipe);
3961                         temp = I915_READ(reg);
3962                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3963                         if (temp & FDI_RX_SYMBOL_LOCK) {
3964                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3965                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3966                                 break;
3967                         }
3968                         udelay(50);
3969                 }
3970                 if (retry < 5)
3971                         break;
3972         }
3973         if (i == 4)
3974                 DRM_ERROR("FDI train 2 fail!\n");
3975
3976         DRM_DEBUG_KMS("FDI train done.\n");
3977 }
3978
3979 /* Manual link training for Ivy Bridge A0 parts */
3980 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3981 {
3982         struct drm_device *dev = crtc->dev;
3983         struct drm_i915_private *dev_priv = to_i915(dev);
3984         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3985         int pipe = intel_crtc->pipe;
3986         i915_reg_t reg;
3987         u32 temp, i, j;
3988
3989         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3990            for train result */
3991         reg = FDI_RX_IMR(pipe);
3992         temp = I915_READ(reg);
3993         temp &= ~FDI_RX_SYMBOL_LOCK;
3994         temp &= ~FDI_RX_BIT_LOCK;
3995         I915_WRITE(reg, temp);
3996
3997         POSTING_READ(reg);
3998         udelay(150);
3999
4000         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
4001                       I915_READ(FDI_RX_IIR(pipe)));
4002
4003         /* Try each vswing and preemphasis setting twice before moving on */
4004         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
4005                 /* disable first in case we need to retry */
4006                 reg = FDI_TX_CTL(pipe);
4007                 temp = I915_READ(reg);
4008                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
4009                 temp &= ~FDI_TX_ENABLE;
4010                 I915_WRITE(reg, temp);
4011
4012                 reg = FDI_RX_CTL(pipe);
4013                 temp = I915_READ(reg);
4014                 temp &= ~FDI_LINK_TRAIN_AUTO;
4015                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4016                 temp &= ~FDI_RX_ENABLE;
4017                 I915_WRITE(reg, temp);
4018
4019                 /* enable CPU FDI TX and PCH FDI RX */
4020                 reg = FDI_TX_CTL(pipe);
4021                 temp = I915_READ(reg);
4022                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
4023                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4024                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
4025                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4026                 temp |= snb_b_fdi_train_param[j/2];
4027                 temp |= FDI_COMPOSITE_SYNC;
4028                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4029
4030                 I915_WRITE(FDI_RX_MISC(pipe),
4031                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4032
4033                 reg = FDI_RX_CTL(pipe);
4034                 temp = I915_READ(reg);
4035                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4036                 temp |= FDI_COMPOSITE_SYNC;
4037                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4038
4039                 POSTING_READ(reg);
4040                 udelay(1); /* should be 0.5us */
4041
4042                 for (i = 0; i < 4; i++) {
4043                         reg = FDI_RX_IIR(pipe);
4044                         temp = I915_READ(reg);
4045                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4046
4047                         if (temp & FDI_RX_BIT_LOCK ||
4048                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
4049                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4050                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4051                                               i);
4052                                 break;
4053                         }
4054                         udelay(1); /* should be 0.5us */
4055                 }
4056                 if (i == 4) {
4057                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
4058                         continue;
4059                 }
4060
4061                 /* Train 2 */
4062                 reg = FDI_TX_CTL(pipe);
4063                 temp = I915_READ(reg);
4064                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4065                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
4066                 I915_WRITE(reg, temp);
4067
4068                 reg = FDI_RX_CTL(pipe);
4069                 temp = I915_READ(reg);
4070                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4071                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4072                 I915_WRITE(reg, temp);
4073
4074                 POSTING_READ(reg);
4075                 udelay(2); /* should be 1.5us */
4076
4077                 for (i = 0; i < 4; i++) {
4078                         reg = FDI_RX_IIR(pipe);
4079                         temp = I915_READ(reg);
4080                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4081
4082                         if (temp & FDI_RX_SYMBOL_LOCK ||
4083                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
4084                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4085                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4086                                               i);
4087                                 goto train_done;
4088                         }
4089                         udelay(2); /* should be 1.5us */
4090                 }
4091                 if (i == 4)
4092                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
4093         }
4094
4095 train_done:
4096         DRM_DEBUG_KMS("FDI train done.\n");
4097 }
4098
4099 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
4100 {
4101         struct drm_device *dev = intel_crtc->base.dev;
4102         struct drm_i915_private *dev_priv = to_i915(dev);
4103         int pipe = intel_crtc->pipe;
4104         i915_reg_t reg;
4105         u32 temp;
4106
4107         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
4108         reg = FDI_RX_CTL(pipe);
4109         temp = I915_READ(reg);
4110         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
4111         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4112         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4113         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4114
4115         POSTING_READ(reg);
4116         udelay(200);
4117
4118         /* Switch from Rawclk to PCDclk */
4119         temp = I915_READ(reg);
4120         I915_WRITE(reg, temp | FDI_PCDCLK);
4121
4122         POSTING_READ(reg);
4123         udelay(200);
4124
4125         /* Enable CPU FDI TX PLL, always on for Ironlake */
4126         reg = FDI_TX_CTL(pipe);
4127         temp = I915_READ(reg);
4128         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
4129                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
4130
4131                 POSTING_READ(reg);
4132                 udelay(100);
4133         }
4134 }
4135
4136 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
4137 {
4138         struct drm_device *dev = intel_crtc->base.dev;
4139         struct drm_i915_private *dev_priv = to_i915(dev);
4140         int pipe = intel_crtc->pipe;
4141         i915_reg_t reg;
4142         u32 temp;
4143
4144         /* Switch from PCDclk to Rawclk */
4145         reg = FDI_RX_CTL(pipe);
4146         temp = I915_READ(reg);
4147         I915_WRITE(reg, temp & ~FDI_PCDCLK);
4148
4149         /* Disable CPU FDI TX PLL */
4150         reg = FDI_TX_CTL(pipe);
4151         temp = I915_READ(reg);
4152         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
4153
4154         POSTING_READ(reg);
4155         udelay(100);
4156
4157         reg = FDI_RX_CTL(pipe);
4158         temp = I915_READ(reg);
4159         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
4160
4161         /* Wait for the clocks to turn off. */
4162         POSTING_READ(reg);
4163         udelay(100);
4164 }
4165
4166 static void ironlake_fdi_disable(struct drm_crtc *crtc)
4167 {
4168         struct drm_device *dev = crtc->dev;
4169         struct drm_i915_private *dev_priv = to_i915(dev);
4170         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4171         int pipe = intel_crtc->pipe;
4172         i915_reg_t reg;
4173         u32 temp;
4174
4175         /* disable CPU FDI tx and PCH FDI rx */
4176         reg = FDI_TX_CTL(pipe);
4177         temp = I915_READ(reg);
4178         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
4179         POSTING_READ(reg);
4180
4181         reg = FDI_RX_CTL(pipe);
4182         temp = I915_READ(reg);
4183         temp &= ~(0x7 << 16);
4184         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4185         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
4186
4187         POSTING_READ(reg);
4188         udelay(100);
4189
4190         /* Ironlake workaround, disable clock pointer after downing FDI */
4191         if (HAS_PCH_IBX(dev_priv))
4192                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4193
4194         /* still set train pattern 1 */
4195         reg = FDI_TX_CTL(pipe);
4196         temp = I915_READ(reg);
4197         temp &= ~FDI_LINK_TRAIN_NONE;
4198         temp |= FDI_LINK_TRAIN_PATTERN_1;
4199         I915_WRITE(reg, temp);
4200
4201         reg = FDI_RX_CTL(pipe);
4202         temp = I915_READ(reg);
4203         if (HAS_PCH_CPT(dev_priv)) {
4204                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4205                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4206         } else {
4207                 temp &= ~FDI_LINK_TRAIN_NONE;
4208                 temp |= FDI_LINK_TRAIN_PATTERN_1;
4209         }
4210         /* BPC in FDI rx is consistent with that in PIPECONF */
4211         temp &= ~(0x07 << 16);
4212         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4213         I915_WRITE(reg, temp);
4214
4215         POSTING_READ(reg);
4216         udelay(100);
4217 }
4218
4219 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
4220 {
4221         struct intel_crtc *crtc;
4222
4223         /* Note that we don't need to be called with mode_config.lock here
4224          * as our list of CRTC objects is static for the lifetime of the
4225          * device and so cannot disappear as we iterate. Similarly, we can
4226          * happily treat the predicates as racy, atomic checks as userspace
4227          * cannot claim and pin a new fb without at least acquring the
4228          * struct_mutex and so serialising with us.
4229          */
4230         for_each_intel_crtc(&dev_priv->drm, crtc) {
4231                 if (atomic_read(&crtc->unpin_work_count) == 0)
4232                         continue;
4233
4234                 if (crtc->flip_work)
4235                         intel_wait_for_vblank(dev_priv, crtc->pipe);
4236
4237                 return true;
4238         }
4239
4240         return false;
4241 }
4242
4243 static void page_flip_completed(struct intel_crtc *intel_crtc)
4244 {
4245         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4246         struct intel_flip_work *work = intel_crtc->flip_work;
4247
4248         intel_crtc->flip_work = NULL;
4249
4250         if (work->event)
4251                 drm_crtc_send_vblank_event(&intel_crtc->base, work->event);
4252
4253         drm_crtc_vblank_put(&intel_crtc->base);
4254
4255         wake_up_all(&dev_priv->pending_flip_queue);
4256         queue_work(dev_priv->wq, &work->unpin_work);
4257
4258         trace_i915_flip_complete(intel_crtc->plane,
4259                                  work->pending_flip_obj);
4260 }
4261
4262 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
4263 {
4264         struct drm_device *dev = crtc->dev;
4265         struct drm_i915_private *dev_priv = to_i915(dev);
4266         long ret;
4267
4268         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
4269
4270         ret = wait_event_interruptible_timeout(
4271                                         dev_priv->pending_flip_queue,
4272                                         !intel_crtc_has_pending_flip(crtc),
4273                                         60*HZ);
4274
4275         if (ret < 0)
4276                 return ret;
4277
4278         if (ret == 0) {
4279                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4280                 struct intel_flip_work *work;
4281
4282                 spin_lock_irq(&dev->event_lock);
4283                 work = intel_crtc->flip_work;
4284                 if (work && !is_mmio_work(work)) {
4285                         WARN_ONCE(1, "Removing stuck page flip\n");
4286                         page_flip_completed(intel_crtc);
4287                 }
4288                 spin_unlock_irq(&dev->event_lock);
4289         }
4290
4291         return 0;
4292 }
4293
4294 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
4295 {
4296         u32 temp;
4297
4298         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
4299
4300         mutex_lock(&dev_priv->sb_lock);
4301
4302         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4303         temp |= SBI_SSCCTL_DISABLE;
4304         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4305
4306         mutex_unlock(&dev_priv->sb_lock);
4307 }
4308
4309 /* Program iCLKIP clock to the desired frequency */
4310 static void lpt_program_iclkip(struct drm_crtc *crtc)
4311 {
4312         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
4313         int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
4314         u32 divsel, phaseinc, auxdiv, phasedir = 0;
4315         u32 temp;
4316
4317         lpt_disable_iclkip(dev_priv);
4318
4319         /* The iCLK virtual clock root frequency is in MHz,
4320          * but the adjusted_mode->crtc_clock in in KHz. To get the
4321          * divisors, it is necessary to divide one by another, so we
4322          * convert the virtual clock precision to KHz here for higher
4323          * precision.
4324          */
4325         for (auxdiv = 0; auxdiv < 2; auxdiv++) {
4326                 u32 iclk_virtual_root_freq = 172800 * 1000;
4327                 u32 iclk_pi_range = 64;
4328                 u32 desired_divisor;
4329
4330                 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4331                                                     clock << auxdiv);
4332                 divsel = (desired_divisor / iclk_pi_range) - 2;
4333                 phaseinc = desired_divisor % iclk_pi_range;
4334
4335                 /*
4336                  * Near 20MHz is a corner case which is
4337                  * out of range for the 7-bit divisor
4338                  */
4339                 if (divsel <= 0x7f)
4340                         break;
4341         }
4342
4343         /* This should not happen with any sane values */
4344         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4345                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4346         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4347                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4348
4349         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4350                         clock,
4351                         auxdiv,
4352                         divsel,
4353                         phasedir,
4354                         phaseinc);
4355
4356         mutex_lock(&dev_priv->sb_lock);
4357
4358         /* Program SSCDIVINTPHASE6 */
4359         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4360         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4361         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4362         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4363         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4364         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4365         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4366         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4367
4368         /* Program SSCAUXDIV */
4369         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4370         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4371         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4372         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4373
4374         /* Enable modulator and associated divider */
4375         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4376         temp &= ~SBI_SSCCTL_DISABLE;
4377         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4378
4379         mutex_unlock(&dev_priv->sb_lock);
4380
4381         /* Wait for initialization time */
4382         udelay(24);
4383
4384         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4385 }
4386
4387 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
4388 {
4389         u32 divsel, phaseinc, auxdiv;
4390         u32 iclk_virtual_root_freq = 172800 * 1000;
4391         u32 iclk_pi_range = 64;
4392         u32 desired_divisor;
4393         u32 temp;
4394
4395         if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
4396                 return 0;
4397
4398         mutex_lock(&dev_priv->sb_lock);
4399
4400         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4401         if (temp & SBI_SSCCTL_DISABLE) {
4402                 mutex_unlock(&dev_priv->sb_lock);
4403                 return 0;
4404         }
4405
4406         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4407         divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
4408                 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
4409         phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
4410                 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
4411
4412         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4413         auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4414                 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4415
4416         mutex_unlock(&dev_priv->sb_lock);
4417
4418         desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4419
4420         return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4421                                  desired_divisor << auxdiv);
4422 }
4423
4424 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4425                                                 enum pipe pch_transcoder)
4426 {
4427         struct drm_device *dev = crtc->base.dev;
4428         struct drm_i915_private *dev_priv = to_i915(dev);
4429         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4430
4431         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4432                    I915_READ(HTOTAL(cpu_transcoder)));
4433         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4434                    I915_READ(HBLANK(cpu_transcoder)));
4435         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4436                    I915_READ(HSYNC(cpu_transcoder)));
4437
4438         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4439                    I915_READ(VTOTAL(cpu_transcoder)));
4440         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4441                    I915_READ(VBLANK(cpu_transcoder)));
4442         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4443                    I915_READ(VSYNC(cpu_transcoder)));
4444         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4445                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
4446 }
4447
4448 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4449 {
4450         struct drm_i915_private *dev_priv = to_i915(dev);
4451         uint32_t temp;
4452
4453         temp = I915_READ(SOUTH_CHICKEN1);
4454         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4455                 return;
4456
4457         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4458         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4459
4460         temp &= ~FDI_BC_BIFURCATION_SELECT;
4461         if (enable)
4462                 temp |= FDI_BC_BIFURCATION_SELECT;
4463
4464         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4465         I915_WRITE(SOUTH_CHICKEN1, temp);
4466         POSTING_READ(SOUTH_CHICKEN1);
4467 }
4468
4469 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4470 {
4471         struct drm_device *dev = intel_crtc->base.dev;
4472
4473         switch (intel_crtc->pipe) {
4474         case PIPE_A:
4475                 break;
4476         case PIPE_B:
4477                 if (intel_crtc->config->fdi_lanes > 2)
4478                         cpt_set_fdi_bc_bifurcation(dev, false);
4479                 else
4480                         cpt_set_fdi_bc_bifurcation(dev, true);
4481
4482                 break;
4483         case PIPE_C:
4484                 cpt_set_fdi_bc_bifurcation(dev, true);
4485
4486                 break;
4487         default:
4488                 BUG();
4489         }
4490 }
4491
4492 /* Return which DP Port should be selected for Transcoder DP control */
4493 static enum port
4494 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4495 {
4496         struct drm_device *dev = crtc->dev;
4497         struct intel_encoder *encoder;
4498
4499         for_each_encoder_on_crtc(dev, crtc, encoder) {
4500                 if (encoder->type == INTEL_OUTPUT_DP ||
4501                     encoder->type == INTEL_OUTPUT_EDP)
4502                         return enc_to_dig_port(&encoder->base)->port;
4503         }
4504
4505         return -1;
4506 }
4507
4508 /*
4509  * Enable PCH resources required for PCH ports:
4510  *   - PCH PLLs
4511  *   - FDI training & RX/TX
4512  *   - update transcoder timings
4513  *   - DP transcoding bits
4514  *   - transcoder
4515  */
4516 static void ironlake_pch_enable(struct drm_crtc *crtc)
4517 {
4518         struct drm_device *dev = crtc->dev;
4519         struct drm_i915_private *dev_priv = to_i915(dev);
4520         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4521         int pipe = intel_crtc->pipe;
4522         u32 temp;
4523
4524         assert_pch_transcoder_disabled(dev_priv, pipe);
4525
4526         if (IS_IVYBRIDGE(dev_priv))
4527                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4528
4529         /* Write the TU size bits before fdi link training, so that error
4530          * detection works. */
4531         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4532                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4533
4534         /* For PCH output, training FDI link */
4535         dev_priv->display.fdi_link_train(crtc);
4536
4537         /* We need to program the right clock selection before writing the pixel
4538          * mutliplier into the DPLL. */
4539         if (HAS_PCH_CPT(dev_priv)) {
4540                 u32 sel;
4541
4542                 temp = I915_READ(PCH_DPLL_SEL);
4543                 temp |= TRANS_DPLL_ENABLE(pipe);
4544                 sel = TRANS_DPLLB_SEL(pipe);
4545                 if (intel_crtc->config->shared_dpll ==
4546                     intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4547                         temp |= sel;
4548                 else
4549                         temp &= ~sel;
4550                 I915_WRITE(PCH_DPLL_SEL, temp);
4551         }
4552
4553         /* XXX: pch pll's can be enabled any time before we enable the PCH
4554          * transcoder, and we actually should do this to not upset any PCH
4555          * transcoder that already use the clock when we share it.
4556          *
4557          * Note that enable_shared_dpll tries to do the right thing, but
4558          * get_shared_dpll unconditionally resets the pll - we need that to have
4559          * the right LVDS enable sequence. */
4560         intel_enable_shared_dpll(intel_crtc);
4561
4562         /* set transcoder timing, panel must allow it */
4563         assert_panel_unlocked(dev_priv, pipe);
4564         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4565
4566         intel_fdi_normal_train(crtc);
4567
4568         /* For PCH DP, enable TRANS_DP_CTL */
4569         if (HAS_PCH_CPT(dev_priv) &&
4570             intel_crtc_has_dp_encoder(intel_crtc->config)) {
4571                 const struct drm_display_mode *adjusted_mode =
4572                         &intel_crtc->config->base.adjusted_mode;
4573                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4574                 i915_reg_t reg = TRANS_DP_CTL(pipe);
4575                 temp = I915_READ(reg);
4576                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4577                           TRANS_DP_SYNC_MASK |
4578                           TRANS_DP_BPC_MASK);
4579                 temp |= TRANS_DP_OUTPUT_ENABLE;
4580                 temp |= bpc << 9; /* same format but at 11:9 */
4581
4582                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4583                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4584                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4585                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4586
4587                 switch (intel_trans_dp_port_sel(crtc)) {
4588                 case PORT_B:
4589                         temp |= TRANS_DP_PORT_SEL_B;
4590                         break;
4591                 case PORT_C:
4592                         temp |= TRANS_DP_PORT_SEL_C;
4593                         break;
4594                 case PORT_D:
4595                         temp |= TRANS_DP_PORT_SEL_D;
4596                         break;
4597                 default:
4598                         BUG();
4599                 }
4600
4601                 I915_WRITE(reg, temp);
4602         }
4603
4604         ironlake_enable_pch_transcoder(dev_priv, pipe);
4605 }
4606
4607 static void lpt_pch_enable(struct drm_crtc *crtc)
4608 {
4609         struct drm_device *dev = crtc->dev;
4610         struct drm_i915_private *dev_priv = to_i915(dev);
4611         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4612         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4613
4614         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4615
4616         lpt_program_iclkip(crtc);
4617
4618         /* Set transcoder timing. */
4619         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4620
4621         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4622 }
4623
4624 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4625 {
4626         struct drm_i915_private *dev_priv = to_i915(dev);
4627         i915_reg_t dslreg = PIPEDSL(pipe);
4628         u32 temp;
4629
4630         temp = I915_READ(dslreg);
4631         udelay(500);
4632         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4633                 if (wait_for(I915_READ(dslreg) != temp, 5))
4634                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4635         }
4636 }
4637
4638 static int
4639 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4640                   unsigned scaler_user, int *scaler_id, unsigned int rotation,
4641                   int src_w, int src_h, int dst_w, int dst_h)
4642 {
4643         struct intel_crtc_scaler_state *scaler_state =
4644                 &crtc_state->scaler_state;
4645         struct intel_crtc *intel_crtc =
4646                 to_intel_crtc(crtc_state->base.crtc);
4647         int need_scaling;
4648
4649         need_scaling = drm_rotation_90_or_270(rotation) ?
4650                 (src_h != dst_w || src_w != dst_h):
4651                 (src_w != dst_w || src_h != dst_h);
4652
4653         /*
4654          * if plane is being disabled or scaler is no more required or force detach
4655          *  - free scaler binded to this plane/crtc
4656          *  - in order to do this, update crtc->scaler_usage
4657          *
4658          * Here scaler state in crtc_state is set free so that
4659          * scaler can be assigned to other user. Actual register
4660          * update to free the scaler is done in plane/panel-fit programming.
4661          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4662          */
4663         if (force_detach || !need_scaling) {
4664                 if (*scaler_id >= 0) {
4665                         scaler_state->scaler_users &= ~(1 << scaler_user);
4666                         scaler_state->scalers[*scaler_id].in_use = 0;
4667
4668                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4669                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4670                                 intel_crtc->pipe, scaler_user, *scaler_id,
4671                                 scaler_state->scaler_users);
4672                         *scaler_id = -1;
4673                 }
4674                 return 0;
4675         }
4676
4677         /* range checks */
4678         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4679                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4680
4681                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4682                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4683                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4684                         "size is out of scaler range\n",
4685                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4686                 return -EINVAL;
4687         }
4688
4689         /* mark this plane as a scaler user in crtc_state */
4690         scaler_state->scaler_users |= (1 << scaler_user);
4691         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4692                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4693                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4694                 scaler_state->scaler_users);
4695
4696         return 0;
4697 }
4698
4699 /**
4700  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4701  *
4702  * @state: crtc's scaler state
4703  *
4704  * Return
4705  *     0 - scaler_usage updated successfully
4706  *    error - requested scaling cannot be supported or other error condition
4707  */
4708 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4709 {
4710         const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4711
4712         return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4713                 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4714                 state->pipe_src_w, state->pipe_src_h,
4715                 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4716 }
4717
4718 /**
4719  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4720  *
4721  * @state: crtc's scaler state
4722  * @plane_state: atomic plane state to update
4723  *
4724  * Return
4725  *     0 - scaler_usage updated successfully
4726  *    error - requested scaling cannot be supported or other error condition
4727  */
4728 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4729                                    struct intel_plane_state *plane_state)
4730 {
4731
4732         struct intel_plane *intel_plane =
4733                 to_intel_plane(plane_state->base.plane);
4734         struct drm_framebuffer *fb = plane_state->base.fb;
4735         int ret;
4736
4737         bool force_detach = !fb || !plane_state->base.visible;
4738
4739         ret = skl_update_scaler(crtc_state, force_detach,
4740                                 drm_plane_index(&intel_plane->base),
4741                                 &plane_state->scaler_id,
4742                                 plane_state->base.rotation,
4743                                 drm_rect_width(&plane_state->base.src) >> 16,
4744                                 drm_rect_height(&plane_state->base.src) >> 16,
4745                                 drm_rect_width(&plane_state->base.dst),
4746                                 drm_rect_height(&plane_state->base.dst));
4747
4748         if (ret || plane_state->scaler_id < 0)
4749                 return ret;
4750
4751         /* check colorkey */
4752         if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4753                 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4754                               intel_plane->base.base.id,
4755                               intel_plane->base.name);
4756                 return -EINVAL;
4757         }
4758
4759         /* Check src format */
4760         switch (fb->format->format) {
4761         case DRM_FORMAT_RGB565:
4762         case DRM_FORMAT_XBGR8888:
4763         case DRM_FORMAT_XRGB8888:
4764         case DRM_FORMAT_ABGR8888:
4765         case DRM_FORMAT_ARGB8888:
4766         case DRM_FORMAT_XRGB2101010:
4767         case DRM_FORMAT_XBGR2101010:
4768         case DRM_FORMAT_YUYV:
4769         case DRM_FORMAT_YVYU:
4770         case DRM_FORMAT_UYVY:
4771         case DRM_FORMAT_VYUY:
4772                 break;
4773         default:
4774                 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4775                               intel_plane->base.base.id, intel_plane->base.name,
4776                               fb->base.id, fb->format->format);
4777                 return -EINVAL;
4778         }
4779
4780         return 0;
4781 }
4782
4783 static void skylake_scaler_disable(struct intel_crtc *crtc)
4784 {
4785         int i;
4786
4787         for (i = 0; i < crtc->num_scalers; i++)
4788                 skl_detach_scaler(crtc, i);
4789 }
4790
4791 static void skylake_pfit_enable(struct intel_crtc *crtc)
4792 {
4793         struct drm_device *dev = crtc->base.dev;
4794         struct drm_i915_private *dev_priv = to_i915(dev);
4795         int pipe = crtc->pipe;
4796         struct intel_crtc_scaler_state *scaler_state =
4797                 &crtc->config->scaler_state;
4798
4799         DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4800
4801         if (crtc->config->pch_pfit.enabled) {
4802                 int id;
4803
4804                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4805                         DRM_ERROR("Requesting pfit without getting a scaler first\n");
4806                         return;
4807                 }
4808
4809                 id = scaler_state->scaler_id;
4810                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4811                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4812                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4813                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4814
4815                 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4816         }
4817 }
4818
4819 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4820 {
4821         struct drm_device *dev = crtc->base.dev;
4822         struct drm_i915_private *dev_priv = to_i915(dev);
4823         int pipe = crtc->pipe;
4824
4825         if (crtc->config->pch_pfit.enabled) {
4826                 /* Force use of hard-coded filter coefficients
4827                  * as some pre-programmed values are broken,
4828                  * e.g. x201.
4829                  */
4830                 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
4831                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4832                                                  PF_PIPE_SEL_IVB(pipe));
4833                 else
4834                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4835                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4836                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4837         }
4838 }
4839
4840 void hsw_enable_ips(struct intel_crtc *crtc)
4841 {
4842         struct drm_device *dev = crtc->base.dev;
4843         struct drm_i915_private *dev_priv = to_i915(dev);
4844
4845         if (!crtc->config->ips_enabled)
4846                 return;
4847
4848         /*
4849          * We can only enable IPS after we enable a plane and wait for a vblank
4850          * This function is called from post_plane_update, which is run after
4851          * a vblank wait.
4852          */
4853
4854         assert_plane_enabled(dev_priv, crtc->plane);
4855         if (IS_BROADWELL(dev_priv)) {
4856                 mutex_lock(&dev_priv->rps.hw_lock);
4857                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4858                 mutex_unlock(&dev_priv->rps.hw_lock);
4859                 /* Quoting Art Runyan: "its not safe to expect any particular
4860                  * value in IPS_CTL bit 31 after enabling IPS through the
4861                  * mailbox." Moreover, the mailbox may return a bogus state,
4862                  * so we need to just enable it and continue on.
4863                  */
4864         } else {
4865                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4866                 /* The bit only becomes 1 in the next vblank, so this wait here
4867                  * is essentially intel_wait_for_vblank. If we don't have this
4868                  * and don't wait for vblanks until the end of crtc_enable, then
4869                  * the HW state readout code will complain that the expected
4870                  * IPS_CTL value is not the one we read. */
4871                 if (intel_wait_for_register(dev_priv,
4872                                             IPS_CTL, IPS_ENABLE, IPS_ENABLE,
4873                                             50))
4874                         DRM_ERROR("Timed out waiting for IPS enable\n");
4875         }
4876 }
4877
4878 void hsw_disable_ips(struct intel_crtc *crtc)
4879 {
4880         struct drm_device *dev = crtc->base.dev;
4881         struct drm_i915_private *dev_priv = to_i915(dev);
4882
4883         if (!crtc->config->ips_enabled)
4884                 return;
4885
4886         assert_plane_enabled(dev_priv, crtc->plane);
4887         if (IS_BROADWELL(dev_priv)) {
4888                 mutex_lock(&dev_priv->rps.hw_lock);
4889                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4890                 mutex_unlock(&dev_priv->rps.hw_lock);
4891                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4892                 if (intel_wait_for_register(dev_priv,
4893                                             IPS_CTL, IPS_ENABLE, 0,
4894                                             42))
4895                         DRM_ERROR("Timed out waiting for IPS disable\n");
4896         } else {
4897                 I915_WRITE(IPS_CTL, 0);
4898                 POSTING_READ(IPS_CTL);
4899         }
4900
4901         /* We need to wait for a vblank before we can disable the plane. */
4902         intel_wait_for_vblank(dev_priv, crtc->pipe);
4903 }
4904
4905 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4906 {
4907         if (intel_crtc->overlay) {
4908                 struct drm_device *dev = intel_crtc->base.dev;
4909                 struct drm_i915_private *dev_priv = to_i915(dev);
4910
4911                 mutex_lock(&dev->struct_mutex);
4912                 dev_priv->mm.interruptible = false;
4913                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4914                 dev_priv->mm.interruptible = true;
4915                 mutex_unlock(&dev->struct_mutex);
4916         }
4917
4918         /* Let userspace switch the overlay on again. In most cases userspace
4919          * has to recompute where to put it anyway.
4920          */
4921 }
4922
4923 /**
4924  * intel_post_enable_primary - Perform operations after enabling primary plane
4925  * @crtc: the CRTC whose primary plane was just enabled
4926  *
4927  * Performs potentially sleeping operations that must be done after the primary
4928  * plane is enabled, such as updating FBC and IPS.  Note that this may be
4929  * called due to an explicit primary plane update, or due to an implicit
4930  * re-enable that is caused when a sprite plane is updated to no longer
4931  * completely hide the primary plane.
4932  */
4933 static void
4934 intel_post_enable_primary(struct drm_crtc *crtc)
4935 {
4936         struct drm_device *dev = crtc->dev;
4937         struct drm_i915_private *dev_priv = to_i915(dev);
4938         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4939         int pipe = intel_crtc->pipe;
4940
4941         /*
4942          * FIXME IPS should be fine as long as one plane is
4943          * enabled, but in practice it seems to have problems
4944          * when going from primary only to sprite only and vice
4945          * versa.
4946          */
4947         hsw_enable_ips(intel_crtc);
4948
4949         /*
4950          * Gen2 reports pipe underruns whenever all planes are disabled.
4951          * So don't enable underrun reporting before at least some planes
4952          * are enabled.
4953          * FIXME: Need to fix the logic to work when we turn off all planes
4954          * but leave the pipe running.
4955          */
4956         if (IS_GEN2(dev_priv))
4957                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4958
4959         /* Underruns don't always raise interrupts, so check manually. */
4960         intel_check_cpu_fifo_underruns(dev_priv);
4961         intel_check_pch_fifo_underruns(dev_priv);
4962 }
4963
4964 /* FIXME move all this to pre_plane_update() with proper state tracking */
4965 static void
4966 intel_pre_disable_primary(struct drm_crtc *crtc)
4967 {
4968         struct drm_device *dev = crtc->dev;
4969         struct drm_i915_private *dev_priv = to_i915(dev);
4970         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4971         int pipe = intel_crtc->pipe;
4972
4973         /*
4974          * Gen2 reports pipe underruns whenever all planes are disabled.
4975          * So diasble underrun reporting before all the planes get disabled.
4976          * FIXME: Need to fix the logic to work when we turn off all planes
4977          * but leave the pipe running.
4978          */
4979         if (IS_GEN2(dev_priv))
4980                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4981
4982         /*
4983          * FIXME IPS should be fine as long as one plane is
4984          * enabled, but in practice it seems to have problems
4985          * when going from primary only to sprite only and vice
4986          * versa.
4987          */
4988         hsw_disable_ips(intel_crtc);
4989 }
4990
4991 /* FIXME get rid of this and use pre_plane_update */
4992 static void
4993 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
4994 {
4995         struct drm_device *dev = crtc->dev;
4996         struct drm_i915_private *dev_priv = to_i915(dev);
4997         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4998         int pipe = intel_crtc->pipe;
4999
5000         intel_pre_disable_primary(crtc);
5001
5002         /*
5003          * Vblank time updates from the shadow to live plane control register
5004          * are blocked if the memory self-refresh mode is active at that
5005          * moment. So to make sure the plane gets truly disabled, disable
5006          * first the self-refresh mode. The self-refresh enable bit in turn
5007          * will be checked/applied by the HW only at the next frame start
5008          * event which is after the vblank start event, so we need to have a
5009          * wait-for-vblank between disabling the plane and the pipe.
5010          */
5011         if (HAS_GMCH_DISPLAY(dev_priv) &&
5012             intel_set_memory_cxsr(dev_priv, false))
5013                 intel_wait_for_vblank(dev_priv, pipe);
5014 }
5015
5016 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
5017 {
5018         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5019         struct drm_atomic_state *old_state = old_crtc_state->base.state;
5020         struct intel_crtc_state *pipe_config =
5021                 to_intel_crtc_state(crtc->base.state);
5022         struct drm_plane *primary = crtc->base.primary;
5023         struct drm_plane_state *old_pri_state =
5024                 drm_atomic_get_existing_plane_state(old_state, primary);
5025
5026         intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
5027
5028         crtc->wm.cxsr_allowed = true;
5029
5030         if (pipe_config->update_wm_post && pipe_config->base.active)
5031                 intel_update_watermarks(crtc);
5032
5033         if (old_pri_state) {
5034                 struct intel_plane_state *primary_state =
5035                         to_intel_plane_state(primary->state);
5036                 struct intel_plane_state *old_primary_state =
5037                         to_intel_plane_state(old_pri_state);
5038
5039                 intel_fbc_post_update(crtc);
5040
5041                 if (primary_state->base.visible &&
5042                     (needs_modeset(&pipe_config->base) ||
5043                      !old_primary_state->base.visible))
5044                         intel_post_enable_primary(&crtc->base);
5045         }
5046 }
5047
5048 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
5049 {
5050         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5051         struct drm_device *dev = crtc->base.dev;
5052         struct drm_i915_private *dev_priv = to_i915(dev);
5053         struct intel_crtc_state *pipe_config =
5054                 to_intel_crtc_state(crtc->base.state);
5055         struct drm_atomic_state *old_state = old_crtc_state->base.state;
5056         struct drm_plane *primary = crtc->base.primary;
5057         struct drm_plane_state *old_pri_state =
5058                 drm_atomic_get_existing_plane_state(old_state, primary);
5059         bool modeset = needs_modeset(&pipe_config->base);
5060         struct intel_atomic_state *old_intel_state =
5061                 to_intel_atomic_state(old_state);
5062
5063         if (old_pri_state) {
5064                 struct intel_plane_state *primary_state =
5065                         to_intel_plane_state(primary->state);
5066                 struct intel_plane_state *old_primary_state =
5067                         to_intel_plane_state(old_pri_state);
5068
5069                 intel_fbc_pre_update(crtc, pipe_config, primary_state);
5070
5071                 if (old_primary_state->base.visible &&
5072                     (modeset || !primary_state->base.visible))
5073                         intel_pre_disable_primary(&crtc->base);
5074         }
5075
5076         if (pipe_config->disable_cxsr && HAS_GMCH_DISPLAY(dev_priv)) {
5077                 crtc->wm.cxsr_allowed = false;
5078
5079                 /*
5080                  * Vblank time updates from the shadow to live plane control register
5081                  * are blocked if the memory self-refresh mode is active at that
5082                  * moment. So to make sure the plane gets truly disabled, disable
5083                  * first the self-refresh mode. The self-refresh enable bit in turn
5084                  * will be checked/applied by the HW only at the next frame start
5085                  * event which is after the vblank start event, so we need to have a
5086                  * wait-for-vblank between disabling the plane and the pipe.
5087                  */
5088                 if (old_crtc_state->base.active &&
5089                     intel_set_memory_cxsr(dev_priv, false))
5090                         intel_wait_for_vblank(dev_priv, crtc->pipe);
5091         }
5092
5093         /*
5094          * IVB workaround: must disable low power watermarks for at least
5095          * one frame before enabling scaling.  LP watermarks can be re-enabled
5096          * when scaling is disabled.
5097          *
5098          * WaCxSRDisabledForSpriteScaling:ivb
5099          */
5100         if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev))
5101                 intel_wait_for_vblank(dev_priv, crtc->pipe);
5102
5103         /*
5104          * If we're doing a modeset, we're done.  No need to do any pre-vblank
5105          * watermark programming here.
5106          */
5107         if (needs_modeset(&pipe_config->base))
5108                 return;
5109
5110         /*
5111          * For platforms that support atomic watermarks, program the
5112          * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
5113          * will be the intermediate values that are safe for both pre- and
5114          * post- vblank; when vblank happens, the 'active' values will be set
5115          * to the final 'target' values and we'll do this again to get the
5116          * optimal watermarks.  For gen9+ platforms, the values we program here
5117          * will be the final target values which will get automatically latched
5118          * at vblank time; no further programming will be necessary.
5119          *
5120          * If a platform hasn't been transitioned to atomic watermarks yet,
5121          * we'll continue to update watermarks the old way, if flags tell
5122          * us to.
5123          */
5124         if (dev_priv->display.initial_watermarks != NULL)
5125                 dev_priv->display.initial_watermarks(old_intel_state,
5126                                                      pipe_config);
5127         else if (pipe_config->update_wm_pre)
5128                 intel_update_watermarks(crtc);
5129 }
5130
5131 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
5132 {
5133         struct drm_device *dev = crtc->dev;
5134         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5135         struct drm_plane *p;
5136         int pipe = intel_crtc->pipe;
5137
5138         intel_crtc_dpms_overlay_disable(intel_crtc);
5139
5140         drm_for_each_plane_mask(p, dev, plane_mask)
5141                 to_intel_plane(p)->disable_plane(p, crtc);
5142
5143         /*
5144          * FIXME: Once we grow proper nuclear flip support out of this we need
5145          * to compute the mask of flip planes precisely. For the time being
5146          * consider this a flip to a NULL plane.
5147          */
5148         intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe));
5149 }
5150
5151 static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc,
5152                                           struct intel_crtc_state *crtc_state,
5153                                           struct drm_atomic_state *old_state)
5154 {
5155         struct drm_connector_state *old_conn_state;
5156         struct drm_connector *conn;
5157         int i;
5158
5159         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5160                 struct drm_connector_state *conn_state = conn->state;
5161                 struct intel_encoder *encoder =
5162                         to_intel_encoder(conn_state->best_encoder);
5163
5164                 if (conn_state->crtc != crtc)
5165                         continue;
5166
5167                 if (encoder->pre_pll_enable)
5168                         encoder->pre_pll_enable(encoder, crtc_state, conn_state);
5169         }
5170 }
5171
5172 static void intel_encoders_pre_enable(struct drm_crtc *crtc,
5173                                       struct intel_crtc_state *crtc_state,
5174                                       struct drm_atomic_state *old_state)
5175 {
5176         struct drm_connector_state *old_conn_state;
5177         struct drm_connector *conn;
5178         int i;
5179
5180         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5181                 struct drm_connector_state *conn_state = conn->state;
5182                 struct intel_encoder *encoder =
5183                         to_intel_encoder(conn_state->best_encoder);
5184
5185                 if (conn_state->crtc != crtc)
5186                         continue;
5187
5188                 if (encoder->pre_enable)
5189                         encoder->pre_enable(encoder, crtc_state, conn_state);
5190         }
5191 }
5192
5193 static void intel_encoders_enable(struct drm_crtc *crtc,
5194                                   struct intel_crtc_state *crtc_state,
5195                                   struct drm_atomic_state *old_state)
5196 {
5197         struct drm_connector_state *old_conn_state;
5198         struct drm_connector *conn;
5199         int i;
5200
5201         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5202                 struct drm_connector_state *conn_state = conn->state;
5203                 struct intel_encoder *encoder =
5204                         to_intel_encoder(conn_state->best_encoder);
5205
5206                 if (conn_state->crtc != crtc)
5207                         continue;
5208
5209                 encoder->enable(encoder, crtc_state, conn_state);
5210                 intel_opregion_notify_encoder(encoder, true);
5211         }
5212 }
5213
5214 static void intel_encoders_disable(struct drm_crtc *crtc,
5215                                    struct intel_crtc_state *old_crtc_state,
5216                                    struct drm_atomic_state *old_state)
5217 {
5218         struct drm_connector_state *old_conn_state;
5219         struct drm_connector *conn;
5220         int i;
5221
5222         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5223                 struct intel_encoder *encoder =
5224                         to_intel_encoder(old_conn_state->best_encoder);
5225
5226                 if (old_conn_state->crtc != crtc)
5227                         continue;
5228
5229                 intel_opregion_notify_encoder(encoder, false);
5230                 encoder->disable(encoder, old_crtc_state, old_conn_state);
5231         }
5232 }
5233
5234 static void intel_encoders_post_disable(struct drm_crtc *crtc,
5235                                         struct intel_crtc_state *old_crtc_state,
5236                                         struct drm_atomic_state *old_state)
5237 {
5238         struct drm_connector_state *old_conn_state;
5239         struct drm_connector *conn;
5240         int i;
5241
5242         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5243                 struct intel_encoder *encoder =
5244                         to_intel_encoder(old_conn_state->best_encoder);
5245
5246                 if (old_conn_state->crtc != crtc)
5247                         continue;
5248
5249                 if (encoder->post_disable)
5250                         encoder->post_disable(encoder, old_crtc_state, old_conn_state);
5251         }
5252 }
5253
5254 static void intel_encoders_post_pll_disable(struct drm_crtc *crtc,
5255                                             struct intel_crtc_state *old_crtc_state,
5256                                             struct drm_atomic_state *old_state)
5257 {
5258         struct drm_connector_state *old_conn_state;
5259         struct drm_connector *conn;
5260         int i;
5261
5262         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5263                 struct intel_encoder *encoder =
5264                         to_intel_encoder(old_conn_state->best_encoder);
5265
5266                 if (old_conn_state->crtc != crtc)
5267                         continue;
5268
5269                 if (encoder->post_pll_disable)
5270                         encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state);
5271         }
5272 }
5273
5274 static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
5275                                  struct drm_atomic_state *old_state)
5276 {
5277         struct drm_crtc *crtc = pipe_config->base.crtc;
5278         struct drm_device *dev = crtc->dev;
5279         struct drm_i915_private *dev_priv = to_i915(dev);
5280         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5281         int pipe = intel_crtc->pipe;
5282         struct intel_atomic_state *old_intel_state =
5283                 to_intel_atomic_state(old_state);
5284
5285         if (WARN_ON(intel_crtc->active))
5286                 return;
5287
5288         /*
5289          * Sometimes spurious CPU pipe underruns happen during FDI
5290          * training, at least with VGA+HDMI cloning. Suppress them.
5291          *
5292          * On ILK we get an occasional spurious CPU pipe underruns
5293          * between eDP port A enable and vdd enable. Also PCH port
5294          * enable seems to result in the occasional CPU pipe underrun.
5295          *
5296          * Spurious PCH underruns also occur during PCH enabling.
5297          */
5298         if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
5299                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5300         if (intel_crtc->config->has_pch_encoder)
5301                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5302
5303         if (intel_crtc->config->has_pch_encoder)
5304                 intel_prepare_shared_dpll(intel_crtc);
5305
5306         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5307                 intel_dp_set_m_n(intel_crtc, M1_N1);
5308
5309         intel_set_pipe_timings(intel_crtc);
5310         intel_set_pipe_src_size(intel_crtc);
5311
5312         if (intel_crtc->config->has_pch_encoder) {
5313                 intel_cpu_transcoder_set_m_n(intel_crtc,
5314                                      &intel_crtc->config->fdi_m_n, NULL);
5315         }
5316
5317         ironlake_set_pipeconf(crtc);
5318
5319         intel_crtc->active = true;
5320
5321         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5322
5323         if (intel_crtc->config->has_pch_encoder) {
5324                 /* Note: FDI PLL enabling _must_ be done before we enable the
5325                  * cpu pipes, hence this is separate from all the other fdi/pch
5326                  * enabling. */
5327                 ironlake_fdi_pll_enable(intel_crtc);
5328         } else {
5329                 assert_fdi_tx_disabled(dev_priv, pipe);
5330                 assert_fdi_rx_disabled(dev_priv, pipe);
5331         }
5332
5333         ironlake_pfit_enable(intel_crtc);
5334
5335         /*
5336          * On ILK+ LUT must be loaded before the pipe is running but with
5337          * clocks enabled
5338          */
5339         intel_color_load_luts(&pipe_config->base);
5340
5341         if (dev_priv->display.initial_watermarks != NULL)
5342                 dev_priv->display.initial_watermarks(old_intel_state, intel_crtc->config);
5343         intel_enable_pipe(intel_crtc);
5344
5345         if (intel_crtc->config->has_pch_encoder)
5346                 ironlake_pch_enable(crtc);
5347
5348         assert_vblank_disabled(crtc);
5349         drm_crtc_vblank_on(crtc);
5350
5351         intel_encoders_enable(crtc, pipe_config, old_state);
5352
5353         if (HAS_PCH_CPT(dev_priv))
5354                 cpt_verify_modeset(dev, intel_crtc->pipe);
5355
5356         /* Must wait for vblank to avoid spurious PCH FIFO underruns */
5357         if (intel_crtc->config->has_pch_encoder)
5358                 intel_wait_for_vblank(dev_priv, pipe);
5359         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5360         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5361 }
5362
5363 /* IPS only exists on ULT machines and is tied to pipe A. */
5364 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
5365 {
5366         return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
5367 }
5368
5369 static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
5370                                 struct drm_atomic_state *old_state)
5371 {
5372         struct drm_crtc *crtc = pipe_config->base.crtc;
5373         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5374         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5375         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
5376         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5377         struct intel_atomic_state *old_intel_state =
5378                 to_intel_atomic_state(old_state);
5379
5380         if (WARN_ON(intel_crtc->active))
5381                 return;
5382
5383         if (intel_crtc->config->has_pch_encoder)
5384                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5385                                                       false);
5386
5387         intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5388
5389         if (intel_crtc->config->shared_dpll)
5390                 intel_enable_shared_dpll(intel_crtc);
5391
5392         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5393                 intel_dp_set_m_n(intel_crtc, M1_N1);
5394
5395         if (!transcoder_is_dsi(cpu_transcoder))
5396                 intel_set_pipe_timings(intel_crtc);
5397
5398         intel_set_pipe_src_size(intel_crtc);
5399
5400         if (cpu_transcoder != TRANSCODER_EDP &&
5401             !transcoder_is_dsi(cpu_transcoder)) {
5402                 I915_WRITE(PIPE_MULT(cpu_transcoder),
5403                            intel_crtc->config->pixel_multiplier - 1);
5404         }
5405
5406         if (intel_crtc->config->has_pch_encoder) {
5407                 intel_cpu_transcoder_set_m_n(intel_crtc,
5408                                      &intel_crtc->config->fdi_m_n, NULL);
5409         }
5410
5411         if (!transcoder_is_dsi(cpu_transcoder))
5412                 haswell_set_pipeconf(crtc);
5413
5414         haswell_set_pipemisc(crtc);
5415
5416         intel_color_set_csc(&pipe_config->base);
5417
5418         intel_crtc->active = true;
5419
5420         if (intel_crtc->config->has_pch_encoder)
5421                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5422         else
5423                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5424
5425         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5426
5427         if (intel_crtc->config->has_pch_encoder)
5428                 dev_priv->display.fdi_link_train(crtc);
5429
5430         if (!transcoder_is_dsi(cpu_transcoder))
5431                 intel_ddi_enable_pipe_clock(intel_crtc);
5432
5433         if (INTEL_GEN(dev_priv) >= 9)
5434                 skylake_pfit_enable(intel_crtc);
5435         else
5436                 ironlake_pfit_enable(intel_crtc);
5437
5438         /*
5439          * On ILK+ LUT must be loaded before the pipe is running but with
5440          * clocks enabled
5441          */
5442         intel_color_load_luts(&pipe_config->base);
5443
5444         intel_ddi_set_pipe_settings(crtc);
5445         if (!transcoder_is_dsi(cpu_transcoder))
5446                 intel_ddi_enable_transcoder_func(crtc);
5447
5448         if (dev_priv->display.initial_watermarks != NULL)
5449                 dev_priv->display.initial_watermarks(old_intel_state, pipe_config);
5450
5451         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5452         if (!transcoder_is_dsi(cpu_transcoder))
5453                 intel_enable_pipe(intel_crtc);
5454
5455         if (intel_crtc->config->has_pch_encoder)
5456                 lpt_pch_enable(crtc);
5457
5458         if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5459                 intel_ddi_set_vc_payload_alloc(crtc, true);
5460
5461         assert_vblank_disabled(crtc);
5462         drm_crtc_vblank_on(crtc);
5463
5464         intel_encoders_enable(crtc, pipe_config, old_state);
5465
5466         if (intel_crtc->config->has_pch_encoder) {
5467                 intel_wait_for_vblank(dev_priv, pipe);
5468                 intel_wait_for_vblank(dev_priv, pipe);
5469                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5470                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5471                                                       true);
5472         }
5473
5474         /* If we change the relative order between pipe/planes enabling, we need
5475          * to change the workaround. */
5476         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5477         if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
5478                 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5479                 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5480         }
5481 }
5482
5483 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5484 {
5485         struct drm_device *dev = crtc->base.dev;
5486         struct drm_i915_private *dev_priv = to_i915(dev);
5487         int pipe = crtc->pipe;
5488
5489         /* To avoid upsetting the power well on haswell only disable the pfit if
5490          * it's in use. The hw state code will make sure we get this right. */
5491         if (force || crtc->config->pch_pfit.enabled) {
5492                 I915_WRITE(PF_CTL(pipe), 0);
5493                 I915_WRITE(PF_WIN_POS(pipe), 0);
5494                 I915_WRITE(PF_WIN_SZ(pipe), 0);
5495         }
5496 }
5497
5498 static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
5499                                   struct drm_atomic_state *old_state)
5500 {
5501         struct drm_crtc *crtc = old_crtc_state->base.crtc;
5502         struct drm_device *dev = crtc->dev;
5503         struct drm_i915_private *dev_priv = to_i915(dev);
5504         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5505         int pipe = intel_crtc->pipe;
5506
5507         /*
5508          * Sometimes spurious CPU pipe underruns happen when the
5509          * pipe is already disabled, but FDI RX/TX is still enabled.
5510          * Happens at least with VGA+HDMI cloning. Suppress them.
5511          */
5512         if (intel_crtc->config->has_pch_encoder) {
5513                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5514                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5515         }
5516
5517         intel_encoders_disable(crtc, old_crtc_state, old_state);
5518
5519         drm_crtc_vblank_off(crtc);
5520         assert_vblank_disabled(crtc);
5521
5522         intel_disable_pipe(intel_crtc);
5523
5524         ironlake_pfit_disable(intel_crtc, false);
5525
5526         if (intel_crtc->config->has_pch_encoder)
5527                 ironlake_fdi_disable(crtc);
5528
5529         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5530
5531         if (intel_crtc->config->has_pch_encoder) {
5532                 ironlake_disable_pch_transcoder(dev_priv, pipe);
5533
5534                 if (HAS_PCH_CPT(dev_priv)) {
5535                         i915_reg_t reg;
5536                         u32 temp;
5537
5538                         /* disable TRANS_DP_CTL */
5539                         reg = TRANS_DP_CTL(pipe);
5540                         temp = I915_READ(reg);
5541                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5542                                   TRANS_DP_PORT_SEL_MASK);
5543                         temp |= TRANS_DP_PORT_SEL_NONE;
5544                         I915_WRITE(reg, temp);
5545
5546                         /* disable DPLL_SEL */
5547                         temp = I915_READ(PCH_DPLL_SEL);
5548                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5549                         I915_WRITE(PCH_DPLL_SEL, temp);
5550                 }
5551
5552                 ironlake_fdi_pll_disable(intel_crtc);
5553         }
5554
5555         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5556         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5557 }
5558
5559 static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
5560                                  struct drm_atomic_state *old_state)
5561 {
5562         struct drm_crtc *crtc = old_crtc_state->base.crtc;
5563         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5564         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5565         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5566
5567         if (intel_crtc->config->has_pch_encoder)
5568                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5569                                                       false);
5570
5571         intel_encoders_disable(crtc, old_crtc_state, old_state);
5572
5573         drm_crtc_vblank_off(crtc);
5574         assert_vblank_disabled(crtc);
5575
5576         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5577         if (!transcoder_is_dsi(cpu_transcoder))
5578                 intel_disable_pipe(intel_crtc);
5579
5580         if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5581                 intel_ddi_set_vc_payload_alloc(crtc, false);
5582
5583         if (!transcoder_is_dsi(cpu_transcoder))
5584                 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5585
5586         if (INTEL_GEN(dev_priv) >= 9)
5587                 skylake_scaler_disable(intel_crtc);
5588         else
5589                 ironlake_pfit_disable(intel_crtc, false);
5590
5591         if (!transcoder_is_dsi(cpu_transcoder))
5592                 intel_ddi_disable_pipe_clock(intel_crtc);
5593
5594         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5595
5596         if (old_crtc_state->has_pch_encoder)
5597                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5598                                                       true);
5599 }
5600
5601 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5602 {
5603         struct drm_device *dev = crtc->base.dev;
5604         struct drm_i915_private *dev_priv = to_i915(dev);
5605         struct intel_crtc_state *pipe_config = crtc->config;
5606
5607         if (!pipe_config->gmch_pfit.control)
5608                 return;
5609
5610         /*
5611          * The panel fitter should only be adjusted whilst the pipe is disabled,
5612          * according to register description and PRM.
5613          */
5614         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5615         assert_pipe_disabled(dev_priv, crtc->pipe);
5616
5617         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5618         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5619
5620         /* Border color in case we don't scale up to the full screen. Black by
5621          * default, change to something else for debugging. */
5622         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5623 }
5624
5625 static enum intel_display_power_domain port_to_power_domain(enum port port)
5626 {
5627         switch (port) {
5628         case PORT_A:
5629                 return POWER_DOMAIN_PORT_DDI_A_LANES;
5630         case PORT_B:
5631                 return POWER_DOMAIN_PORT_DDI_B_LANES;
5632         case PORT_C:
5633                 return POWER_DOMAIN_PORT_DDI_C_LANES;
5634         case PORT_D:
5635                 return POWER_DOMAIN_PORT_DDI_D_LANES;
5636         case PORT_E:
5637                 return POWER_DOMAIN_PORT_DDI_E_LANES;
5638         default:
5639                 MISSING_CASE(port);
5640                 return POWER_DOMAIN_PORT_OTHER;
5641         }
5642 }
5643
5644 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5645 {
5646         switch (port) {
5647         case PORT_A:
5648                 return POWER_DOMAIN_AUX_A;
5649         case PORT_B:
5650                 return POWER_DOMAIN_AUX_B;
5651         case PORT_C:
5652                 return POWER_DOMAIN_AUX_C;
5653         case PORT_D:
5654                 return POWER_DOMAIN_AUX_D;
5655         case PORT_E:
5656                 /* FIXME: Check VBT for actual wiring of PORT E */
5657                 return POWER_DOMAIN_AUX_D;
5658         default:
5659                 MISSING_CASE(port);
5660                 return POWER_DOMAIN_AUX_A;
5661         }
5662 }
5663
5664 enum intel_display_power_domain
5665 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5666 {
5667         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
5668         struct intel_digital_port *intel_dig_port;
5669
5670         switch (intel_encoder->type) {
5671         case INTEL_OUTPUT_UNKNOWN:
5672                 /* Only DDI platforms should ever use this output type */
5673                 WARN_ON_ONCE(!HAS_DDI(dev_priv));
5674         case INTEL_OUTPUT_DP:
5675         case INTEL_OUTPUT_HDMI:
5676         case INTEL_OUTPUT_EDP:
5677                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5678                 return port_to_power_domain(intel_dig_port->port);
5679         case INTEL_OUTPUT_DP_MST:
5680                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5681                 return port_to_power_domain(intel_dig_port->port);
5682         case INTEL_OUTPUT_ANALOG:
5683                 return POWER_DOMAIN_PORT_CRT;
5684         case INTEL_OUTPUT_DSI:
5685                 return POWER_DOMAIN_PORT_DSI;
5686         default:
5687                 return POWER_DOMAIN_PORT_OTHER;
5688         }
5689 }
5690
5691 enum intel_display_power_domain
5692 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5693 {
5694         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
5695         struct intel_digital_port *intel_dig_port;
5696
5697         switch (intel_encoder->type) {
5698         case INTEL_OUTPUT_UNKNOWN:
5699         case INTEL_OUTPUT_HDMI:
5700                 /*
5701                  * Only DDI platforms should ever use these output types.
5702                  * We can get here after the HDMI detect code has already set
5703                  * the type of the shared encoder. Since we can't be sure
5704                  * what's the status of the given connectors, play safe and
5705                  * run the DP detection too.
5706                  */
5707                 WARN_ON_ONCE(!HAS_DDI(dev_priv));
5708         case INTEL_OUTPUT_DP:
5709         case INTEL_OUTPUT_EDP:
5710                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5711                 return port_to_aux_power_domain(intel_dig_port->port);
5712         case INTEL_OUTPUT_DP_MST:
5713                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5714                 return port_to_aux_power_domain(intel_dig_port->port);
5715         default:
5716                 MISSING_CASE(intel_encoder->type);
5717                 return POWER_DOMAIN_AUX_A;
5718         }
5719 }
5720
5721 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc,
5722                                             struct intel_crtc_state *crtc_state)
5723 {
5724         struct drm_device *dev = crtc->dev;
5725         struct drm_encoder *encoder;
5726         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5727         enum pipe pipe = intel_crtc->pipe;
5728         unsigned long mask;
5729         enum transcoder transcoder = crtc_state->cpu_transcoder;
5730
5731         if (!crtc_state->base.active)
5732                 return 0;
5733
5734         mask = BIT(POWER_DOMAIN_PIPE(pipe));
5735         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5736         if (crtc_state->pch_pfit.enabled ||
5737             crtc_state->pch_pfit.force_thru)
5738                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5739
5740         drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5741                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5742
5743                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5744         }
5745
5746         if (crtc_state->shared_dpll)
5747                 mask |= BIT(POWER_DOMAIN_PLLS);
5748
5749         return mask;
5750 }
5751
5752 static unsigned long
5753 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5754                                struct intel_crtc_state *crtc_state)
5755 {
5756         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5757         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5758         enum intel_display_power_domain domain;
5759         unsigned long domains, new_domains, old_domains;
5760
5761         old_domains = intel_crtc->enabled_power_domains;
5762         intel_crtc->enabled_power_domains = new_domains =
5763                 get_crtc_power_domains(crtc, crtc_state);
5764
5765         domains = new_domains & ~old_domains;
5766
5767         for_each_power_domain(domain, domains)
5768                 intel_display_power_get(dev_priv, domain);
5769
5770         return old_domains & ~new_domains;
5771 }
5772
5773 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5774                                       unsigned long domains)
5775 {
5776         enum intel_display_power_domain domain;
5777
5778         for_each_power_domain(domain, domains)
5779                 intel_display_power_put(dev_priv, domain);
5780 }
5781
5782 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5783 {
5784         int max_cdclk_freq = dev_priv->max_cdclk_freq;
5785
5786         if (IS_GEMINILAKE(dev_priv))
5787                 return 2 * max_cdclk_freq;
5788         else if (INTEL_INFO(dev_priv)->gen >= 9 ||
5789                  IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5790                 return max_cdclk_freq;
5791         else if (IS_CHERRYVIEW(dev_priv))
5792                 return max_cdclk_freq*95/100;
5793         else if (INTEL_INFO(dev_priv)->gen < 4)
5794                 return 2*max_cdclk_freq*90/100;
5795         else
5796                 return max_cdclk_freq*90/100;
5797 }
5798
5799 static int skl_calc_cdclk(int max_pixclk, int vco);
5800
5801 static void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
5802 {
5803         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5804                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5805                 int max_cdclk, vco;
5806
5807                 vco = dev_priv->skl_preferred_vco_freq;
5808                 WARN_ON(vco != 8100000 && vco != 8640000);
5809
5810                 /*
5811                  * Use the lower (vco 8640) cdclk values as a
5812                  * first guess. skl_calc_cdclk() will correct it
5813                  * if the preferred vco is 8100 instead.
5814                  */
5815                 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5816                         max_cdclk = 617143;
5817                 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5818                         max_cdclk = 540000;
5819                 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5820                         max_cdclk = 432000;
5821                 else
5822                         max_cdclk = 308571;
5823
5824                 dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
5825         } else if (IS_GEMINILAKE(dev_priv)) {
5826                 dev_priv->max_cdclk_freq = 316800;
5827         } else if (IS_BROXTON(dev_priv)) {
5828                 dev_priv->max_cdclk_freq = 624000;
5829         } else if (IS_BROADWELL(dev_priv))  {
5830                 /*
5831                  * FIXME with extra cooling we can allow
5832                  * 540 MHz for ULX and 675 Mhz for ULT.
5833                  * How can we know if extra cooling is
5834                  * available? PCI ID, VTB, something else?
5835                  */
5836                 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5837                         dev_priv->max_cdclk_freq = 450000;
5838                 else if (IS_BDW_ULX(dev_priv))
5839                         dev_priv->max_cdclk_freq = 450000;
5840                 else if (IS_BDW_ULT(dev_priv))
5841                         dev_priv->max_cdclk_freq = 540000;
5842                 else
5843                         dev_priv->max_cdclk_freq = 675000;
5844         } else if (IS_CHERRYVIEW(dev_priv)) {
5845                 dev_priv->max_cdclk_freq = 320000;
5846         } else if (IS_VALLEYVIEW(dev_priv)) {
5847                 dev_priv->max_cdclk_freq = 400000;
5848         } else {
5849                 /* otherwise assume cdclk is fixed */
5850                 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5851         }
5852
5853         dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5854
5855         DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5856                          dev_priv->max_cdclk_freq);
5857
5858         DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5859                          dev_priv->max_dotclk_freq);
5860 }
5861
5862 static void intel_update_cdclk(struct drm_i915_private *dev_priv)
5863 {
5864         dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev_priv);
5865
5866         if (INTEL_GEN(dev_priv) >= 9)
5867                 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n",
5868                                  dev_priv->cdclk_freq, dev_priv->cdclk_pll.vco,
5869                                  dev_priv->cdclk_pll.ref);
5870         else
5871                 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5872                                  dev_priv->cdclk_freq);
5873
5874         /*
5875          * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
5876          * Programmng [sic] note: bit[9:2] should be programmed to the number
5877          * of cdclk that generates 4MHz reference clock freq which is used to
5878          * generate GMBus clock. This will vary with the cdclk freq.
5879          */
5880         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5881                 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5882 }
5883
5884 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5885 static int skl_cdclk_decimal(int cdclk)
5886 {
5887         return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
5888 }
5889
5890 static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
5891 {
5892         int ratio;
5893
5894         if (cdclk == dev_priv->cdclk_pll.ref)
5895                 return 0;
5896
5897         switch (cdclk) {
5898         default:
5899                 MISSING_CASE(cdclk);
5900         case 144000:
5901         case 288000:
5902         case 384000:
5903         case 576000:
5904                 ratio = 60;
5905                 break;
5906         case 624000:
5907                 ratio = 65;
5908                 break;
5909         }
5910
5911         return dev_priv->cdclk_pll.ref * ratio;
5912 }
5913
5914 static int glk_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
5915 {
5916         int ratio;
5917
5918         if (cdclk == dev_priv->cdclk_pll.ref)
5919                 return 0;
5920
5921         switch (cdclk) {
5922         default:
5923                 MISSING_CASE(cdclk);
5924         case  79200:
5925         case 158400:
5926         case 316800:
5927                 ratio = 33;
5928                 break;
5929         }
5930
5931         return dev_priv->cdclk_pll.ref * ratio;
5932 }
5933
5934 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
5935 {
5936         I915_WRITE(BXT_DE_PLL_ENABLE, 0);
5937
5938         /* Timeout 200us */
5939         if (intel_wait_for_register(dev_priv,
5940                                     BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 0,
5941                                     1))
5942                 DRM_ERROR("timeout waiting for DE PLL unlock\n");
5943
5944         dev_priv->cdclk_pll.vco = 0;
5945 }
5946
5947 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
5948 {
5949         int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk_pll.ref);
5950         u32 val;
5951
5952         val = I915_READ(BXT_DE_PLL_CTL);
5953         val &= ~BXT_DE_PLL_RATIO_MASK;
5954         val |= BXT_DE_PLL_RATIO(ratio);
5955         I915_WRITE(BXT_DE_PLL_CTL, val);
5956
5957         I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5958
5959         /* Timeout 200us */
5960         if (intel_wait_for_register(dev_priv,
5961                                     BXT_DE_PLL_ENABLE,
5962                                     BXT_DE_PLL_LOCK,
5963                                     BXT_DE_PLL_LOCK,
5964                                     1))
5965                 DRM_ERROR("timeout waiting for DE PLL lock\n");
5966
5967         dev_priv->cdclk_pll.vco = vco;
5968 }
5969
5970 static void bxt_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
5971 {
5972         u32 val, divider;
5973         int vco, ret;
5974
5975         if (IS_GEMINILAKE(dev_priv))
5976                 vco = glk_de_pll_vco(dev_priv, cdclk);
5977         else
5978                 vco = bxt_de_pll_vco(dev_priv, cdclk);
5979
5980         DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
5981
5982         /* cdclk = vco / 2 / div{1,1.5,2,4} */
5983         switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
5984         case 8:
5985                 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5986                 break;
5987         case 4:
5988                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5989                 break;
5990         case 3:
5991                 WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n");
5992                 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5993                 break;
5994         case 2:
5995                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5996                 break;
5997         default:
5998                 WARN_ON(cdclk != dev_priv->cdclk_pll.ref);
5999                 WARN_ON(vco != 0);
6000
6001                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
6002                 break;
6003         }
6004
6005         /* Inform power controller of upcoming frequency change */
6006         mutex_lock(&dev_priv->rps.hw_lock);
6007         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
6008                                       0x80000000);
6009         mutex_unlock(&dev_priv->rps.hw_lock);
6010
6011         if (ret) {
6012                 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
6013                           ret, cdclk);
6014                 return;
6015         }
6016
6017         if (dev_priv->cdclk_pll.vco != 0 &&
6018             dev_priv->cdclk_pll.vco != vco)
6019                 bxt_de_pll_disable(dev_priv);
6020
6021         if (dev_priv->cdclk_pll.vco != vco)
6022                 bxt_de_pll_enable(dev_priv, vco);
6023
6024         val = divider | skl_cdclk_decimal(cdclk);
6025         /*
6026          * FIXME if only the cd2x divider needs changing, it could be done
6027          * without shutting off the pipe (if only one pipe is active).
6028          */
6029         val |= BXT_CDCLK_CD2X_PIPE_NONE;
6030         /*
6031          * Disable SSA Precharge when CD clock frequency < 500 MHz,
6032          * enable otherwise.
6033          */
6034         if (cdclk >= 500000)
6035                 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
6036         I915_WRITE(CDCLK_CTL, val);
6037
6038         mutex_lock(&dev_priv->rps.hw_lock);
6039         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
6040                                       DIV_ROUND_UP(cdclk, 25000));
6041         mutex_unlock(&dev_priv->rps.hw_lock);
6042
6043         if (ret) {
6044                 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
6045                           ret, cdclk);
6046                 return;
6047         }
6048
6049         intel_update_cdclk(dev_priv);
6050 }
6051
6052 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
6053 {
6054         u32 cdctl, expected;
6055
6056         intel_update_cdclk(dev_priv);
6057
6058         if (dev_priv->cdclk_pll.vco == 0 ||
6059             dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
6060                 goto sanitize;
6061
6062         /* DPLL okay; verify the cdclock
6063          *
6064          * Some BIOS versions leave an incorrect decimal frequency value and
6065          * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
6066          * so sanitize this register.
6067          */
6068         cdctl = I915_READ(CDCLK_CTL);
6069         /*
6070          * Let's ignore the pipe field, since BIOS could have configured the
6071          * dividers both synching to an active pipe, or asynchronously
6072          * (PIPE_NONE).
6073          */
6074         cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
6075
6076         expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
6077                    skl_cdclk_decimal(dev_priv->cdclk_freq);
6078         /*
6079          * Disable SSA Precharge when CD clock frequency < 500 MHz,
6080          * enable otherwise.
6081          */
6082         if (dev_priv->cdclk_freq >= 500000)
6083                 expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
6084
6085         if (cdctl == expected)
6086                 /* All well; nothing to sanitize */
6087                 return;
6088
6089 sanitize:
6090         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
6091
6092         /* force cdclk programming */
6093         dev_priv->cdclk_freq = 0;
6094
6095         /* force full PLL disable + enable */
6096         dev_priv->cdclk_pll.vco = -1;
6097 }
6098
6099 void bxt_init_cdclk(struct drm_i915_private *dev_priv)
6100 {
6101         int cdclk;
6102
6103         bxt_sanitize_cdclk(dev_priv);
6104
6105         if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0)
6106                 return;
6107
6108         /*
6109          * FIXME:
6110          * - The initial CDCLK needs to be read from VBT.
6111          *   Need to make this change after VBT has changes for BXT.
6112          */
6113         if (IS_GEMINILAKE(dev_priv))
6114                 cdclk = glk_calc_cdclk(0);
6115         else
6116                 cdclk = bxt_calc_cdclk(0);
6117
6118         bxt_set_cdclk(dev_priv, cdclk);
6119 }
6120
6121 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
6122 {
6123         bxt_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref);
6124 }
6125
6126 static int skl_calc_cdclk(int max_pixclk, int vco)
6127 {
6128         if (vco == 8640000) {
6129                 if (max_pixclk > 540000)
6130                         return 617143;
6131                 else if (max_pixclk > 432000)
6132                         return 540000;
6133                 else if (max_pixclk > 308571)
6134                         return 432000;
6135                 else
6136                         return 308571;
6137         } else {
6138                 if (max_pixclk > 540000)
6139                         return 675000;
6140                 else if (max_pixclk > 450000)
6141                         return 540000;
6142                 else if (max_pixclk > 337500)
6143                         return 450000;
6144                 else
6145                         return 337500;
6146         }
6147 }
6148
6149 static void
6150 skl_dpll0_update(struct drm_i915_private *dev_priv)
6151 {
6152         u32 val;
6153
6154         dev_priv->cdclk_pll.ref = 24000;
6155         dev_priv->cdclk_pll.vco = 0;
6156
6157         val = I915_READ(LCPLL1_CTL);
6158         if ((val & LCPLL_PLL_ENABLE) == 0)
6159                 return;
6160
6161         if (WARN_ON((val & LCPLL_PLL_LOCK) == 0))
6162                 return;
6163
6164         val = I915_READ(DPLL_CTRL1);
6165
6166         if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
6167                             DPLL_CTRL1_SSC(SKL_DPLL0) |
6168                             DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
6169                     DPLL_CTRL1_OVERRIDE(SKL_DPLL0)))
6170                 return;
6171
6172         switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
6173         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
6174         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
6175         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
6176         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
6177                 dev_priv->cdclk_pll.vco = 8100000;
6178                 break;
6179         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
6180         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
6181                 dev_priv->cdclk_pll.vco = 8640000;
6182                 break;
6183         default:
6184                 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
6185                 break;
6186         }
6187 }
6188
6189 void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco)
6190 {
6191         bool changed = dev_priv->skl_preferred_vco_freq != vco;
6192
6193         dev_priv->skl_preferred_vco_freq = vco;
6194
6195         if (changed)
6196                 intel_update_max_cdclk(dev_priv);
6197 }
6198
6199 static void
6200 skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
6201 {
6202         int min_cdclk = skl_calc_cdclk(0, vco);
6203         u32 val;
6204
6205         WARN_ON(vco != 8100000 && vco != 8640000);
6206
6207         /* select the minimum CDCLK before enabling DPLL 0 */
6208         val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk);
6209         I915_WRITE(CDCLK_CTL, val);
6210         POSTING_READ(CDCLK_CTL);
6211
6212         /*
6213          * We always enable DPLL0 with the lowest link rate possible, but still
6214          * taking into account the VCO required to operate the eDP panel at the
6215          * desired frequency. The usual DP link rates operate with a VCO of
6216          * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
6217          * The modeset code is responsible for the selection of the exact link
6218          * rate later on, with the constraint of choosing a frequency that
6219          * works with vco.
6220          */
6221         val = I915_READ(DPLL_CTRL1);
6222
6223         val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
6224                  DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
6225         val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
6226         if (vco == 8640000)
6227                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
6228                                             SKL_DPLL0);
6229         else
6230                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
6231                                             SKL_DPLL0);
6232
6233         I915_WRITE(DPLL_CTRL1, val);
6234         POSTING_READ(DPLL_CTRL1);
6235
6236         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
6237
6238         if (intel_wait_for_register(dev_priv,
6239                                     LCPLL1_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
6240                                     5))
6241                 DRM_ERROR("DPLL0 not locked\n");
6242
6243         dev_priv->cdclk_pll.vco = vco;
6244
6245         /* We'll want to keep using the current vco from now on. */
6246         skl_set_preferred_cdclk_vco(dev_priv, vco);
6247 }
6248
6249 static void
6250 skl_dpll0_disable(struct drm_i915_private *dev_priv)
6251 {
6252         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
6253         if (intel_wait_for_register(dev_priv,
6254                                    LCPLL1_CTL, LCPLL_PLL_LOCK, 0,
6255                                    1))
6256                 DRM_ERROR("Couldn't disable DPLL0\n");
6257
6258         dev_priv->cdclk_pll.vco = 0;
6259 }
6260
6261 static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco)
6262 {
6263         u32 freq_select, pcu_ack;
6264         int ret;
6265
6266         WARN_ON((cdclk == 24000) != (vco == 0));
6267
6268         DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
6269
6270         mutex_lock(&dev_priv->rps.hw_lock);
6271         ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
6272                                 SKL_CDCLK_PREPARE_FOR_CHANGE,
6273                                 SKL_CDCLK_READY_FOR_CHANGE,
6274                                 SKL_CDCLK_READY_FOR_CHANGE, 3);
6275         mutex_unlock(&dev_priv->rps.hw_lock);
6276         if (ret) {
6277                 DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
6278                           ret);
6279                 return;
6280         }
6281
6282         /* set CDCLK_CTL */
6283         switch (cdclk) {
6284         case 450000:
6285         case 432000:
6286                 freq_select = CDCLK_FREQ_450_432;
6287                 pcu_ack = 1;
6288                 break;
6289         case 540000:
6290                 freq_select = CDCLK_FREQ_540;
6291                 pcu_ack = 2;
6292                 break;
6293         case 308571:
6294         case 337500:
6295         default:
6296                 freq_select = CDCLK_FREQ_337_308;
6297                 pcu_ack = 0;
6298                 break;
6299         case 617143:
6300         case 675000:
6301                 freq_select = CDCLK_FREQ_675_617;
6302                 pcu_ack = 3;
6303                 break;
6304         }
6305
6306         if (dev_priv->cdclk_pll.vco != 0 &&
6307             dev_priv->cdclk_pll.vco != vco)
6308                 skl_dpll0_disable(dev_priv);
6309
6310         if (dev_priv->cdclk_pll.vco != vco)
6311                 skl_dpll0_enable(dev_priv, vco);
6312
6313         I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk));
6314         POSTING_READ(CDCLK_CTL);
6315
6316         /* inform PCU of the change */
6317         mutex_lock(&dev_priv->rps.hw_lock);
6318         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
6319         mutex_unlock(&dev_priv->rps.hw_lock);
6320
6321         intel_update_cdclk(dev_priv);
6322 }
6323
6324 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
6325
6326 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
6327 {
6328         skl_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref, 0);
6329 }
6330
6331 void skl_init_cdclk(struct drm_i915_private *dev_priv)
6332 {
6333         int cdclk, vco;
6334
6335         skl_sanitize_cdclk(dev_priv);
6336
6337         if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0) {
6338                 /*
6339                  * Use the current vco as our initial
6340                  * guess as to what the preferred vco is.
6341                  */
6342                 if (dev_priv->skl_preferred_vco_freq == 0)
6343                         skl_set_preferred_cdclk_vco(dev_priv,
6344                                                     dev_priv->cdclk_pll.vco);
6345                 return;
6346         }
6347
6348         vco = dev_priv->skl_preferred_vco_freq;
6349         if (vco == 0)
6350                 vco = 8100000;
6351         cdclk = skl_calc_cdclk(0, vco);
6352
6353         skl_set_cdclk(dev_priv, cdclk, vco);
6354 }
6355
6356 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
6357 {
6358         uint32_t cdctl, expected;
6359
6360         /*
6361          * check if the pre-os intialized the display
6362          * There is SWF18 scratchpad register defined which is set by the
6363          * pre-os which can be used by the OS drivers to check the status
6364          */
6365         if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
6366                 goto sanitize;
6367
6368         intel_update_cdclk(dev_priv);
6369         /* Is PLL enabled and locked ? */
6370         if (dev_priv->cdclk_pll.vco == 0 ||
6371             dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
6372                 goto sanitize;
6373
6374         /* DPLL okay; verify the cdclock
6375          *
6376          * Noticed in some instances that the freq selection is correct but
6377          * decimal part is programmed wrong from BIOS where pre-os does not
6378          * enable display. Verify the same as well.
6379          */
6380         cdctl = I915_READ(CDCLK_CTL);
6381         expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
6382                 skl_cdclk_decimal(dev_priv->cdclk_freq);
6383         if (cdctl == expected)
6384                 /* All well; nothing to sanitize */
6385                 return;
6386
6387 sanitize:
6388         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
6389
6390         /* force cdclk programming */
6391         dev_priv->cdclk_freq = 0;
6392         /* force full PLL disable + enable */
6393         dev_priv->cdclk_pll.vco = -1;
6394 }
6395
6396 /* Adjust CDclk dividers to allow high res or save power if possible */
6397 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
6398 {
6399         struct drm_i915_private *dev_priv = to_i915(dev);
6400         u32 val, cmd;
6401
6402         WARN_ON(dev_priv->display.get_display_clock_speed(dev_priv)
6403                                         != dev_priv->cdclk_freq);
6404
6405         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
6406                 cmd = 2;
6407         else if (cdclk == 266667)
6408                 cmd = 1;
6409         else
6410                 cmd = 0;
6411
6412         mutex_lock(&dev_priv->rps.hw_lock);
6413         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
6414         val &= ~DSPFREQGUAR_MASK;
6415         val |= (cmd << DSPFREQGUAR_SHIFT);
6416         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
6417         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
6418                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
6419                      50)) {
6420                 DRM_ERROR("timed out waiting for CDclk change\n");
6421         }
6422         mutex_unlock(&dev_priv->rps.hw_lock);
6423
6424         mutex_lock(&dev_priv->sb_lock);
6425
6426         if (cdclk == 400000) {
6427                 u32 divider;
6428
6429                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
6430
6431                 /* adjust cdclk divider */
6432                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6433                 val &= ~CCK_FREQUENCY_VALUES;
6434                 val |= divider;
6435                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
6436
6437                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
6438                               CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
6439                              50))
6440                         DRM_ERROR("timed out waiting for CDclk change\n");
6441         }
6442
6443         /* adjust self-refresh exit latency value */
6444         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
6445         val &= ~0x7f;
6446
6447         /*
6448          * For high bandwidth configs, we set a higher latency in the bunit
6449          * so that the core display fetch happens in time to avoid underruns.
6450          */
6451         if (cdclk == 400000)
6452                 val |= 4500 / 250; /* 4.5 usec */
6453         else
6454                 val |= 3000 / 250; /* 3.0 usec */
6455         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
6456
6457         mutex_unlock(&dev_priv->sb_lock);
6458
6459         intel_update_cdclk(dev_priv);
6460 }
6461
6462 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
6463 {
6464         struct drm_i915_private *dev_priv = to_i915(dev);
6465         u32 val, cmd;
6466
6467         WARN_ON(dev_priv->display.get_display_clock_speed(dev_priv)
6468                                                 != dev_priv->cdclk_freq);
6469
6470         switch (cdclk) {
6471         case 333333:
6472         case 320000:
6473         case 266667:
6474         case 200000:
6475                 break;
6476         default:
6477                 MISSING_CASE(cdclk);
6478                 return;
6479         }
6480
6481         /*
6482          * Specs are full of misinformation, but testing on actual
6483          * hardware has shown that we just need to write the desired
6484          * CCK divider into the Punit register.
6485          */
6486         cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
6487
6488         mutex_lock(&dev_priv->rps.hw_lock);
6489         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
6490         val &= ~DSPFREQGUAR_MASK_CHV;
6491         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
6492         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
6493         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
6494                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
6495                      50)) {
6496                 DRM_ERROR("timed out waiting for CDclk change\n");
6497         }
6498         mutex_unlock(&dev_priv->rps.hw_lock);
6499
6500         intel_update_cdclk(dev_priv);
6501 }
6502
6503 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
6504                                  int max_pixclk)
6505 {
6506         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
6507         int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
6508
6509         /*
6510          * Really only a few cases to deal with, as only 4 CDclks are supported:
6511          *   200MHz
6512          *   267MHz
6513          *   320/333MHz (depends on HPLL freq)
6514          *   400MHz (VLV only)
6515          * So we check to see whether we're above 90% (VLV) or 95% (CHV)
6516          * of the lower bin and adjust if needed.
6517          *
6518          * We seem to get an unstable or solid color picture at 200MHz.
6519          * Not sure what's wrong. For now use 200MHz only when all pipes
6520          * are off.
6521          */
6522         if (!IS_CHERRYVIEW(dev_priv) &&
6523             max_pixclk > freq_320*limit/100)
6524                 return 400000;
6525         else if (max_pixclk > 266667*limit/100)
6526                 return freq_320;
6527         else if (max_pixclk > 0)
6528                 return 266667;
6529         else
6530                 return 200000;
6531 }
6532
6533 static int glk_calc_cdclk(int max_pixclk)
6534 {
6535         if (max_pixclk > 2 * 158400)
6536                 return 316800;
6537         else if (max_pixclk > 2 * 79200)
6538                 return 158400;
6539         else
6540                 return 79200;
6541 }
6542
6543 static int bxt_calc_cdclk(int max_pixclk)
6544 {
6545         if (max_pixclk > 576000)
6546                 return 624000;
6547         else if (max_pixclk > 384000)
6548                 return 576000;
6549         else if (max_pixclk > 288000)
6550                 return 384000;
6551         else if (max_pixclk > 144000)
6552                 return 288000;
6553         else
6554                 return 144000;
6555 }
6556
6557 /* Compute the max pixel clock for new configuration. */
6558 static int intel_mode_max_pixclk(struct drm_device *dev,
6559                                  struct drm_atomic_state *state)
6560 {
6561         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
6562         struct drm_i915_private *dev_priv = to_i915(dev);
6563         struct drm_crtc *crtc;
6564         struct drm_crtc_state *crtc_state;
6565         unsigned max_pixclk = 0, i;
6566         enum pipe pipe;
6567
6568         memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
6569                sizeof(intel_state->min_pixclk));
6570
6571         for_each_crtc_in_state(state, crtc, crtc_state, i) {
6572                 int pixclk = 0;
6573
6574                 if (crtc_state->enable)
6575                         pixclk = crtc_state->adjusted_mode.crtc_clock;
6576
6577                 intel_state->min_pixclk[i] = pixclk;
6578         }
6579
6580         for_each_pipe(dev_priv, pipe)
6581                 max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk);
6582
6583         return max_pixclk;
6584 }
6585
6586 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
6587 {
6588         struct drm_device *dev = state->dev;
6589         struct drm_i915_private *dev_priv = to_i915(dev);
6590         int max_pixclk = intel_mode_max_pixclk(dev, state);
6591         struct intel_atomic_state *intel_state =
6592                 to_intel_atomic_state(state);
6593
6594         intel_state->cdclk = intel_state->dev_cdclk =
6595                 valleyview_calc_cdclk(dev_priv, max_pixclk);
6596
6597         if (!intel_state->active_crtcs)
6598                 intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0);
6599
6600         return 0;
6601 }
6602
6603 static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
6604 {
6605         struct drm_i915_private *dev_priv = to_i915(state->dev);
6606         int max_pixclk = ilk_max_pixel_rate(state);
6607         struct intel_atomic_state *intel_state =
6608                 to_intel_atomic_state(state);
6609         int cdclk;
6610
6611         if (IS_GEMINILAKE(dev_priv))
6612                 cdclk = glk_calc_cdclk(max_pixclk);
6613         else
6614                 cdclk = bxt_calc_cdclk(max_pixclk);
6615
6616         intel_state->cdclk = intel_state->dev_cdclk = cdclk;
6617
6618         if (!intel_state->active_crtcs) {
6619                 if (IS_GEMINILAKE(dev_priv))
6620                         cdclk = glk_calc_cdclk(0);
6621                 else
6622                         cdclk = bxt_calc_cdclk(0);
6623
6624                 intel_state->dev_cdclk = cdclk;
6625         }
6626
6627         return 0;
6628 }
6629
6630 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6631 {
6632         unsigned int credits, default_credits;
6633
6634         if (IS_CHERRYVIEW(dev_priv))
6635                 default_credits = PFI_CREDIT(12);
6636         else
6637                 default_credits = PFI_CREDIT(8);
6638
6639         if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
6640                 /* CHV suggested value is 31 or 63 */
6641                 if (IS_CHERRYVIEW(dev_priv))
6642                         credits = PFI_CREDIT_63;
6643                 else
6644                         credits = PFI_CREDIT(15);
6645         } else {
6646                 credits = default_credits;
6647         }
6648
6649         /*
6650          * WA - write default credits before re-programming
6651          * FIXME: should we also set the resend bit here?
6652          */
6653         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6654                    default_credits);
6655
6656         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6657                    credits | PFI_CREDIT_RESEND);
6658
6659         /*
6660          * FIXME is this guaranteed to clear
6661          * immediately or should we poll for it?
6662          */
6663         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6664 }
6665
6666 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6667 {
6668         struct drm_device *dev = old_state->dev;
6669         struct drm_i915_private *dev_priv = to_i915(dev);
6670         struct intel_atomic_state *old_intel_state =
6671                 to_intel_atomic_state(old_state);
6672         unsigned req_cdclk = old_intel_state->dev_cdclk;
6673
6674         /*
6675          * FIXME: We can end up here with all power domains off, yet
6676          * with a CDCLK frequency other than the minimum. To account
6677          * for this take the PIPE-A power domain, which covers the HW
6678          * blocks needed for the following programming. This can be
6679          * removed once it's guaranteed that we get here either with
6680          * the minimum CDCLK set, or the required power domains
6681          * enabled.
6682          */
6683         intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6684
6685         if (IS_CHERRYVIEW(dev_priv))
6686                 cherryview_set_cdclk(dev, req_cdclk);
6687         else
6688                 valleyview_set_cdclk(dev, req_cdclk);
6689
6690         vlv_program_pfi_credits(dev_priv);
6691
6692         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6693 }
6694
6695 static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
6696                                    struct drm_atomic_state *old_state)
6697 {
6698         struct drm_crtc *crtc = pipe_config->base.crtc;
6699         struct drm_device *dev = crtc->dev;
6700         struct drm_i915_private *dev_priv = to_i915(dev);
6701         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6702         int pipe = intel_crtc->pipe;
6703
6704         if (WARN_ON(intel_crtc->active))
6705                 return;
6706
6707         if (intel_crtc_has_dp_encoder(intel_crtc->config))
6708                 intel_dp_set_m_n(intel_crtc, M1_N1);
6709
6710         intel_set_pipe_timings(intel_crtc);
6711         intel_set_pipe_src_size(intel_crtc);
6712
6713         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
6714                 struct drm_i915_private *dev_priv = to_i915(dev);
6715
6716                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6717                 I915_WRITE(CHV_CANVAS(pipe), 0);
6718         }
6719
6720         i9xx_set_pipeconf(intel_crtc);
6721
6722         intel_crtc->active = true;
6723
6724         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6725
6726         intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
6727
6728         if (IS_CHERRYVIEW(dev_priv)) {
6729                 chv_prepare_pll(intel_crtc, intel_crtc->config);
6730                 chv_enable_pll(intel_crtc, intel_crtc->config);
6731         } else {
6732                 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6733                 vlv_enable_pll(intel_crtc, intel_crtc->config);
6734         }
6735
6736         intel_encoders_pre_enable(crtc, pipe_config, old_state);
6737
6738         i9xx_pfit_enable(intel_crtc);
6739
6740         intel_color_load_luts(&pipe_config->base);
6741
6742         intel_update_watermarks(intel_crtc);
6743         intel_enable_pipe(intel_crtc);
6744
6745         assert_vblank_disabled(crtc);
6746         drm_crtc_vblank_on(crtc);
6747
6748         intel_encoders_enable(crtc, pipe_config, old_state);
6749 }
6750
6751 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6752 {
6753         struct drm_device *dev = crtc->base.dev;
6754         struct drm_i915_private *dev_priv = to_i915(dev);
6755
6756         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6757         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6758 }
6759
6760 static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
6761                              struct drm_atomic_state *old_state)
6762 {
6763         struct drm_crtc *crtc = pipe_config->base.crtc;
6764         struct drm_device *dev = crtc->dev;
6765         struct drm_i915_private *dev_priv = to_i915(dev);
6766         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6767         enum pipe pipe = intel_crtc->pipe;
6768
6769         if (WARN_ON(intel_crtc->active))
6770                 return;
6771
6772         i9xx_set_pll_dividers(intel_crtc);
6773
6774         if (intel_crtc_has_dp_encoder(intel_crtc->config))
6775                 intel_dp_set_m_n(intel_crtc, M1_N1);
6776
6777         intel_set_pipe_timings(intel_crtc);
6778         intel_set_pipe_src_size(intel_crtc);
6779
6780         i9xx_set_pipeconf(intel_crtc);
6781
6782         intel_crtc->active = true;
6783
6784         if (!IS_GEN2(dev_priv))
6785                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6786
6787         intel_encoders_pre_enable(crtc, pipe_config, old_state);
6788
6789         i9xx_enable_pll(intel_crtc);
6790
6791         i9xx_pfit_enable(intel_crtc);
6792
6793         intel_color_load_luts(&pipe_config->base);
6794
6795         intel_update_watermarks(intel_crtc);
6796         intel_enable_pipe(intel_crtc);
6797
6798         assert_vblank_disabled(crtc);
6799         drm_crtc_vblank_on(crtc);
6800
6801         intel_encoders_enable(crtc, pipe_config, old_state);
6802 }
6803
6804 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6805 {
6806         struct drm_device *dev = crtc->base.dev;
6807         struct drm_i915_private *dev_priv = to_i915(dev);
6808
6809         if (!crtc->config->gmch_pfit.control)
6810                 return;
6811
6812         assert_pipe_disabled(dev_priv, crtc->pipe);
6813
6814         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6815                          I915_READ(PFIT_CONTROL));
6816         I915_WRITE(PFIT_CONTROL, 0);
6817 }
6818
6819 static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
6820                               struct drm_atomic_state *old_state)
6821 {
6822         struct drm_crtc *crtc = old_crtc_state->base.crtc;
6823         struct drm_device *dev = crtc->dev;
6824         struct drm_i915_private *dev_priv = to_i915(dev);
6825         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6826         int pipe = intel_crtc->pipe;
6827
6828         /*
6829          * On gen2 planes are double buffered but the pipe isn't, so we must
6830          * wait for planes to fully turn off before disabling the pipe.
6831          */
6832         if (IS_GEN2(dev_priv))
6833                 intel_wait_for_vblank(dev_priv, pipe);
6834
6835         intel_encoders_disable(crtc, old_crtc_state, old_state);
6836
6837         drm_crtc_vblank_off(crtc);
6838         assert_vblank_disabled(crtc);
6839
6840         intel_disable_pipe(intel_crtc);
6841
6842         i9xx_pfit_disable(intel_crtc);
6843
6844         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
6845
6846         if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) {
6847                 if (IS_CHERRYVIEW(dev_priv))
6848                         chv_disable_pll(dev_priv, pipe);
6849                 else if (IS_VALLEYVIEW(dev_priv))
6850                         vlv_disable_pll(dev_priv, pipe);
6851                 else
6852                         i9xx_disable_pll(intel_crtc);
6853         }
6854
6855         intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
6856
6857         if (!IS_GEN2(dev_priv))
6858                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6859 }
6860
6861 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6862 {
6863         struct intel_encoder *encoder;
6864         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6865         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6866         enum intel_display_power_domain domain;
6867         unsigned long domains;
6868         struct drm_atomic_state *state;
6869         struct intel_crtc_state *crtc_state;
6870         int ret;
6871
6872         if (!intel_crtc->active)
6873                 return;
6874
6875         if (crtc->primary->state->visible) {
6876                 WARN_ON(intel_crtc->flip_work);
6877
6878                 intel_pre_disable_primary_noatomic(crtc);
6879
6880                 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
6881                 crtc->primary->state->visible = false;
6882         }
6883
6884         state = drm_atomic_state_alloc(crtc->dev);
6885         if (!state) {
6886                 DRM_DEBUG_KMS("failed to disable [CRTC:%d:%s], out of memory",
6887                               crtc->base.id, crtc->name);
6888                 return;
6889         }
6890
6891         state->acquire_ctx = crtc->dev->mode_config.acquire_ctx;
6892
6893         /* Everything's already locked, -EDEADLK can't happen. */
6894         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
6895         ret = drm_atomic_add_affected_connectors(state, crtc);
6896
6897         WARN_ON(IS_ERR(crtc_state) || ret);
6898
6899         dev_priv->display.crtc_disable(crtc_state, state);
6900
6901         drm_atomic_state_put(state);
6902
6903         DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
6904                       crtc->base.id, crtc->name);
6905
6906         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
6907         crtc->state->active = false;
6908         intel_crtc->active = false;
6909         crtc->enabled = false;
6910         crtc->state->connector_mask = 0;
6911         crtc->state->encoder_mask = 0;
6912
6913         for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
6914                 encoder->base.crtc = NULL;
6915
6916         intel_fbc_disable(intel_crtc);
6917         intel_update_watermarks(intel_crtc);
6918         intel_disable_shared_dpll(intel_crtc);
6919
6920         domains = intel_crtc->enabled_power_domains;
6921         for_each_power_domain(domain, domains)
6922                 intel_display_power_put(dev_priv, domain);
6923         intel_crtc->enabled_power_domains = 0;
6924
6925         dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6926         dev_priv->min_pixclk[intel_crtc->pipe] = 0;
6927 }
6928
6929 /*
6930  * turn all crtc's off, but do not adjust state
6931  * This has to be paired with a call to intel_modeset_setup_hw_state.
6932  */
6933 int intel_display_suspend(struct drm_device *dev)
6934 {
6935         struct drm_i915_private *dev_priv = to_i915(dev);
6936         struct drm_atomic_state *state;
6937         int ret;
6938
6939         state = drm_atomic_helper_suspend(dev);
6940         ret = PTR_ERR_OR_ZERO(state);
6941         if (ret)
6942                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6943         else
6944                 dev_priv->modeset_restore_state = state;
6945         return ret;
6946 }
6947
6948 void intel_encoder_destroy(struct drm_encoder *encoder)
6949 {
6950         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6951
6952         drm_encoder_cleanup(encoder);
6953         kfree(intel_encoder);
6954 }
6955
6956 /* Cross check the actual hw state with our own modeset state tracking (and it's
6957  * internal consistency). */
6958 static void intel_connector_verify_state(struct intel_connector *connector)
6959 {
6960         struct drm_crtc *crtc = connector->base.state->crtc;
6961
6962         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6963                       connector->base.base.id,
6964                       connector->base.name);
6965
6966         if (connector->get_hw_state(connector)) {
6967                 struct intel_encoder *encoder = connector->encoder;
6968                 struct drm_connector_state *conn_state = connector->base.state;
6969
6970                 I915_STATE_WARN(!crtc,
6971                          "connector enabled without attached crtc\n");
6972
6973                 if (!crtc)
6974                         return;
6975
6976                 I915_STATE_WARN(!crtc->state->active,
6977                       "connector is active, but attached crtc isn't\n");
6978
6979                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6980                         return;
6981
6982                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6983                         "atomic encoder doesn't match attached encoder\n");
6984
6985                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6986                         "attached encoder crtc differs from connector crtc\n");
6987         } else {
6988                 I915_STATE_WARN(crtc && crtc->state->active,
6989                         "attached crtc is active, but connector isn't\n");
6990                 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6991                         "best encoder set without crtc!\n");
6992         }
6993 }
6994
6995 int intel_connector_init(struct intel_connector *connector)
6996 {
6997         drm_atomic_helper_connector_reset(&connector->base);
6998
6999         if (!connector->base.state)
7000                 return -ENOMEM;
7001
7002         return 0;
7003 }
7004
7005 struct intel_connector *intel_connector_alloc(void)
7006 {
7007         struct intel_connector *connector;
7008
7009         connector = kzalloc(sizeof *connector, GFP_KERNEL);
7010         if (!connector)
7011                 return NULL;
7012
7013         if (intel_connector_init(connector) < 0) {
7014                 kfree(connector);
7015                 return NULL;
7016         }
7017
7018         return connector;
7019 }
7020
7021 /* Simple connector->get_hw_state implementation for encoders that support only
7022  * one connector and no cloning and hence the encoder state determines the state
7023  * of the connector. */
7024 bool intel_connector_get_hw_state(struct intel_connector *connector)
7025 {
7026         enum pipe pipe = 0;
7027         struct intel_encoder *encoder = connector->encoder;
7028
7029         return encoder->get_hw_state(encoder, &pipe);
7030 }
7031
7032 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
7033 {
7034         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
7035                 return crtc_state->fdi_lanes;
7036
7037         return 0;
7038 }
7039
7040 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
7041                                      struct intel_crtc_state *pipe_config)
7042 {
7043         struct drm_i915_private *dev_priv = to_i915(dev);
7044         struct drm_atomic_state *state = pipe_config->base.state;
7045         struct intel_crtc *other_crtc;
7046         struct intel_crtc_state *other_crtc_state;
7047
7048         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
7049                       pipe_name(pipe), pipe_config->fdi_lanes);
7050         if (pipe_config->fdi_lanes > 4) {
7051                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
7052                               pipe_name(pipe), pipe_config->fdi_lanes);
7053                 return -EINVAL;
7054         }
7055
7056         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
7057                 if (pipe_config->fdi_lanes > 2) {
7058                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
7059                                       pipe_config->fdi_lanes);
7060                         return -EINVAL;
7061                 } else {
7062                         return 0;
7063                 }
7064         }
7065
7066         if (INTEL_INFO(dev_priv)->num_pipes == 2)
7067                 return 0;
7068
7069         /* Ivybridge 3 pipe is really complicated */
7070         switch (pipe) {
7071         case PIPE_A:
7072                 return 0;
7073         case PIPE_B:
7074                 if (pipe_config->fdi_lanes <= 2)
7075                         return 0;
7076
7077                 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C);
7078                 other_crtc_state =
7079                         intel_atomic_get_crtc_state(state, other_crtc);
7080                 if (IS_ERR(other_crtc_state))
7081                         return PTR_ERR(other_crtc_state);
7082
7083                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
7084                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
7085                                       pipe_name(pipe), pipe_config->fdi_lanes);
7086                         return -EINVAL;
7087                 }
7088                 return 0;
7089         case PIPE_C:
7090                 if (pipe_config->fdi_lanes > 2) {
7091                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
7092                                       pipe_name(pipe), pipe_config->fdi_lanes);
7093                         return -EINVAL;
7094                 }
7095
7096                 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B);
7097                 other_crtc_state =
7098                         intel_atomic_get_crtc_state(state, other_crtc);
7099                 if (IS_ERR(other_crtc_state))
7100                         return PTR_ERR(other_crtc_state);
7101
7102                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
7103                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
7104                         return -EINVAL;
7105                 }
7106                 return 0;
7107         default:
7108                 BUG();
7109         }
7110 }
7111
7112 #define RETRY 1
7113 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
7114                                        struct intel_crtc_state *pipe_config)
7115 {
7116         struct drm_device *dev = intel_crtc->base.dev;
7117         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
7118         int lane, link_bw, fdi_dotclock, ret;
7119         bool needs_recompute = false;
7120
7121 retry:
7122         /* FDI is a binary signal running at ~2.7GHz, encoding
7123          * each output octet as 10 bits. The actual frequency
7124          * is stored as a divider into a 100MHz clock, and the
7125          * mode pixel clock is stored in units of 1KHz.
7126          * Hence the bw of each lane in terms of the mode signal
7127          * is:
7128          */
7129         link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
7130
7131         fdi_dotclock = adjusted_mode->crtc_clock;
7132
7133         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
7134                                            pipe_config->pipe_bpp);
7135
7136         pipe_config->fdi_lanes = lane;
7137
7138         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
7139                                link_bw, &pipe_config->fdi_m_n);
7140
7141         ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
7142         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
7143                 pipe_config->pipe_bpp -= 2*3;
7144                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
7145                               pipe_config->pipe_bpp);
7146                 needs_recompute = true;
7147                 pipe_config->bw_constrained = true;
7148
7149                 goto retry;
7150         }
7151
7152         if (needs_recompute)
7153                 return RETRY;
7154
7155         return ret;
7156 }
7157
7158 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
7159                                      struct intel_crtc_state *pipe_config)
7160 {
7161         if (pipe_config->pipe_bpp > 24)
7162                 return false;
7163
7164         /* HSW can handle pixel rate up to cdclk? */
7165         if (IS_HASWELL(dev_priv))
7166                 return true;
7167
7168         /*
7169          * We compare against max which means we must take
7170          * the increased cdclk requirement into account when
7171          * calculating the new cdclk.
7172          *
7173          * Should measure whether using a lower cdclk w/o IPS
7174          */
7175         return ilk_pipe_pixel_rate(pipe_config) <=
7176                 dev_priv->max_cdclk_freq * 95 / 100;
7177 }
7178
7179 static void hsw_compute_ips_config(struct intel_crtc *crtc,
7180                                    struct intel_crtc_state *pipe_config)
7181 {
7182         struct drm_device *dev = crtc->base.dev;
7183         struct drm_i915_private *dev_priv = to_i915(dev);
7184
7185         pipe_config->ips_enabled = i915.enable_ips &&
7186                 hsw_crtc_supports_ips(crtc) &&
7187                 pipe_config_supports_ips(dev_priv, pipe_config);
7188 }
7189
7190 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
7191 {
7192         const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7193
7194         /* GDG double wide on either pipe, otherwise pipe A only */
7195         return INTEL_INFO(dev_priv)->gen < 4 &&
7196                 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
7197 }
7198
7199 static int intel_crtc_compute_config(struct intel_crtc *crtc,
7200                                      struct intel_crtc_state *pipe_config)
7201 {
7202         struct drm_device *dev = crtc->base.dev;
7203         struct drm_i915_private *dev_priv = to_i915(dev);
7204         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
7205         int clock_limit = dev_priv->max_dotclk_freq;
7206
7207         if (INTEL_GEN(dev_priv) < 4) {
7208                 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
7209
7210                 /*
7211                  * Enable double wide mode when the dot clock
7212                  * is > 90% of the (display) core speed.
7213                  */
7214                 if (intel_crtc_supports_double_wide(crtc) &&
7215                     adjusted_mode->crtc_clock > clock_limit) {
7216                         clock_limit = dev_priv->max_dotclk_freq;
7217                         pipe_config->double_wide = true;
7218                 }
7219         }
7220
7221         if (adjusted_mode->crtc_clock > clock_limit) {
7222                 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
7223                               adjusted_mode->crtc_clock, clock_limit,
7224                               yesno(pipe_config->double_wide));
7225                 return -EINVAL;
7226         }
7227
7228         /*
7229          * Pipe horizontal size must be even in:
7230          * - DVO ganged mode
7231          * - LVDS dual channel mode
7232          * - Double wide pipe
7233          */
7234         if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
7235              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
7236                 pipe_config->pipe_src_w &= ~1;
7237
7238         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
7239          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
7240          */
7241         if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
7242                 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
7243                 return -EINVAL;
7244
7245         if (HAS_IPS(dev_priv))
7246                 hsw_compute_ips_config(crtc, pipe_config);
7247
7248         if (pipe_config->has_pch_encoder)
7249                 return ironlake_fdi_compute_config(crtc, pipe_config);
7250
7251         return 0;
7252 }
7253
7254 static int skylake_get_display_clock_speed(struct drm_i915_private *dev_priv)
7255 {
7256         u32 cdctl;
7257
7258         skl_dpll0_update(dev_priv);
7259
7260         if (dev_priv->cdclk_pll.vco == 0)
7261                 return dev_priv->cdclk_pll.ref;
7262
7263         cdctl = I915_READ(CDCLK_CTL);
7264
7265         if (dev_priv->cdclk_pll.vco == 8640000) {
7266                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
7267                 case CDCLK_FREQ_450_432:
7268                         return 432000;
7269                 case CDCLK_FREQ_337_308:
7270                         return 308571;
7271                 case CDCLK_FREQ_540:
7272                         return 540000;
7273                 case CDCLK_FREQ_675_617:
7274                         return 617143;
7275                 default:
7276                         MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
7277                 }
7278         } else {
7279                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
7280                 case CDCLK_FREQ_450_432:
7281                         return 450000;
7282                 case CDCLK_FREQ_337_308:
7283                         return 337500;
7284                 case CDCLK_FREQ_540:
7285                         return 540000;
7286                 case CDCLK_FREQ_675_617:
7287                         return 675000;
7288                 default:
7289                         MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
7290                 }
7291         }
7292
7293         return dev_priv->cdclk_pll.ref;
7294 }
7295
7296 static void bxt_de_pll_update(struct drm_i915_private *dev_priv)
7297 {
7298         u32 val;
7299
7300         dev_priv->cdclk_pll.ref = 19200;
7301         dev_priv->cdclk_pll.vco = 0;
7302
7303         val = I915_READ(BXT_DE_PLL_ENABLE);
7304         if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
7305                 return;
7306
7307         if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
7308                 return;
7309
7310         val = I915_READ(BXT_DE_PLL_CTL);
7311         dev_priv->cdclk_pll.vco = (val & BXT_DE_PLL_RATIO_MASK) *
7312                 dev_priv->cdclk_pll.ref;
7313 }
7314
7315 static int broxton_get_display_clock_speed(struct drm_i915_private *dev_priv)
7316 {
7317         u32 divider;
7318         int div, vco;
7319
7320         bxt_de_pll_update(dev_priv);
7321
7322         vco = dev_priv->cdclk_pll.vco;
7323         if (vco == 0)
7324                 return dev_priv->cdclk_pll.ref;
7325
7326         divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
7327
7328         switch (divider) {
7329         case BXT_CDCLK_CD2X_DIV_SEL_1:
7330                 div = 2;
7331                 break;
7332         case BXT_CDCLK_CD2X_DIV_SEL_1_5:
7333                 WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n");
7334                 div = 3;
7335                 break;
7336         case BXT_CDCLK_CD2X_DIV_SEL_2:
7337                 div = 4;
7338                 break;
7339         case BXT_CDCLK_CD2X_DIV_SEL_4:
7340                 div = 8;
7341                 break;
7342         default:
7343                 MISSING_CASE(divider);
7344                 return dev_priv->cdclk_pll.ref;
7345         }
7346
7347         return DIV_ROUND_CLOSEST(vco, div);
7348 }
7349
7350 static int broadwell_get_display_clock_speed(struct drm_i915_private *dev_priv)
7351 {
7352         uint32_t lcpll = I915_READ(LCPLL_CTL);
7353         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
7354
7355         if (lcpll & LCPLL_CD_SOURCE_FCLK)
7356                 return 800000;
7357         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
7358                 return 450000;
7359         else if (freq == LCPLL_CLK_FREQ_450)
7360                 return 450000;
7361         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
7362                 return 540000;
7363         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
7364                 return 337500;
7365         else
7366                 return 675000;
7367 }
7368
7369 static int haswell_get_display_clock_speed(struct drm_i915_private *dev_priv)
7370 {
7371         uint32_t lcpll = I915_READ(LCPLL_CTL);
7372         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
7373
7374         if (lcpll & LCPLL_CD_SOURCE_FCLK)
7375                 return 800000;
7376         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
7377                 return 450000;
7378         else if (freq == LCPLL_CLK_FREQ_450)
7379                 return 450000;
7380         else if (IS_HSW_ULT(dev_priv))
7381                 return 337500;
7382         else
7383                 return 540000;
7384 }
7385
7386 static int valleyview_get_display_clock_speed(struct drm_i915_private *dev_priv)
7387 {
7388         return vlv_get_cck_clock_hpll(dev_priv, "cdclk",
7389                                       CCK_DISPLAY_CLOCK_CONTROL);
7390 }
7391
7392 static int ilk_get_display_clock_speed(struct drm_i915_private *dev_priv)
7393 {
7394         return 450000;
7395 }
7396
7397 static int i945_get_display_clock_speed(struct drm_i915_private *dev_priv)
7398 {
7399         return 400000;
7400 }
7401
7402 static int i915_get_display_clock_speed(struct drm_i915_private *dev_priv)
7403 {
7404         return 333333;
7405 }
7406
7407 static int i9xx_misc_get_display_clock_speed(struct drm_i915_private *dev_priv)
7408 {
7409         return 200000;
7410 }
7411
7412 static int pnv_get_display_clock_speed(struct drm_i915_private *dev_priv)
7413 {
7414         struct pci_dev *pdev = dev_priv->drm.pdev;
7415         u16 gcfgc = 0;
7416
7417         pci_read_config_word(pdev, GCFGC, &gcfgc);
7418
7419         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
7420         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
7421                 return 266667;
7422         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
7423                 return 333333;
7424         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
7425                 return 444444;
7426         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
7427                 return 200000;
7428         default:
7429                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
7430         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
7431                 return 133333;
7432         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
7433                 return 166667;
7434         }
7435 }
7436
7437 static int i915gm_get_display_clock_speed(struct drm_i915_private *dev_priv)
7438 {
7439         struct pci_dev *pdev = dev_priv->drm.pdev;
7440         u16 gcfgc = 0;
7441
7442         pci_read_config_word(pdev, GCFGC, &gcfgc);
7443
7444         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
7445                 return 133333;
7446         else {
7447                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
7448                 case GC_DISPLAY_CLOCK_333_MHZ:
7449                         return 333333;
7450                 default:
7451                 case GC_DISPLAY_CLOCK_190_200_MHZ:
7452                         return 190000;
7453                 }
7454         }
7455 }
7456
7457 static int i865_get_display_clock_speed(struct drm_i915_private *dev_priv)
7458 {
7459         return 266667;
7460 }
7461
7462 static int i85x_get_display_clock_speed(struct drm_i915_private *dev_priv)
7463 {
7464         struct pci_dev *pdev = dev_priv->drm.pdev;
7465         u16 hpllcc = 0;
7466
7467         /*
7468          * 852GM/852GMV only supports 133 MHz and the HPLLCC
7469          * encoding is different :(
7470          * FIXME is this the right way to detect 852GM/852GMV?
7471          */
7472         if (pdev->revision == 0x1)
7473                 return 133333;
7474
7475         pci_bus_read_config_word(pdev->bus,
7476                                  PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
7477
7478         /* Assume that the hardware is in the high speed state.  This
7479          * should be the default.
7480          */
7481         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
7482         case GC_CLOCK_133_200:
7483         case GC_CLOCK_133_200_2:
7484         case GC_CLOCK_100_200:
7485                 return 200000;
7486         case GC_CLOCK_166_250:
7487                 return 250000;
7488         case GC_CLOCK_100_133:
7489                 return 133333;
7490         case GC_CLOCK_133_266:
7491         case GC_CLOCK_133_266_2:
7492         case GC_CLOCK_166_266:
7493                 return 266667;
7494         }
7495
7496         /* Shouldn't happen */
7497         return 0;
7498 }
7499
7500 static int i830_get_display_clock_speed(struct drm_i915_private *dev_priv)
7501 {
7502         return 133333;
7503 }
7504
7505 static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv)
7506 {
7507         static const unsigned int blb_vco[8] = {
7508                 [0] = 3200000,
7509                 [1] = 4000000,
7510                 [2] = 5333333,
7511                 [3] = 4800000,
7512                 [4] = 6400000,
7513         };
7514         static const unsigned int pnv_vco[8] = {
7515                 [0] = 3200000,
7516                 [1] = 4000000,
7517                 [2] = 5333333,
7518                 [3] = 4800000,
7519                 [4] = 2666667,
7520         };
7521         static const unsigned int cl_vco[8] = {
7522                 [0] = 3200000,
7523                 [1] = 4000000,
7524                 [2] = 5333333,
7525                 [3] = 6400000,
7526                 [4] = 3333333,
7527                 [5] = 3566667,
7528                 [6] = 4266667,
7529         };
7530         static const unsigned int elk_vco[8] = {
7531                 [0] = 3200000,
7532                 [1] = 4000000,
7533                 [2] = 5333333,
7534                 [3] = 4800000,
7535         };
7536         static const unsigned int ctg_vco[8] = {
7537                 [0] = 3200000,
7538                 [1] = 4000000,
7539                 [2] = 5333333,
7540                 [3] = 6400000,
7541                 [4] = 2666667,
7542                 [5] = 4266667,
7543         };
7544         const unsigned int *vco_table;
7545         unsigned int vco;
7546         uint8_t tmp = 0;
7547
7548         /* FIXME other chipsets? */
7549         if (IS_GM45(dev_priv))
7550                 vco_table = ctg_vco;
7551         else if (IS_G4X(dev_priv))
7552                 vco_table = elk_vco;
7553         else if (IS_I965GM(dev_priv))
7554                 vco_table = cl_vco;
7555         else if (IS_PINEVIEW(dev_priv))
7556                 vco_table = pnv_vco;
7557         else if (IS_G33(dev_priv))
7558                 vco_table = blb_vco;
7559         else
7560                 return 0;
7561
7562         tmp = I915_READ(IS_MOBILE(dev_priv) ? HPLLVCO_MOBILE : HPLLVCO);
7563
7564         vco = vco_table[tmp & 0x7];
7565         if (vco == 0)
7566                 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
7567         else
7568                 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
7569
7570         return vco;
7571 }
7572
7573 static int gm45_get_display_clock_speed(struct drm_i915_private *dev_priv)
7574 {
7575         struct pci_dev *pdev = dev_priv->drm.pdev;
7576         unsigned int cdclk_sel, vco = intel_hpll_vco(dev_priv);
7577         uint16_t tmp = 0;
7578
7579         pci_read_config_word(pdev, GCFGC, &tmp);
7580
7581         cdclk_sel = (tmp >> 12) & 0x1;
7582
7583         switch (vco) {
7584         case 2666667:
7585         case 4000000:
7586         case 5333333:
7587                 return cdclk_sel ? 333333 : 222222;
7588         case 3200000:
7589                 return cdclk_sel ? 320000 : 228571;
7590         default:
7591                 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
7592                 return 222222;
7593         }
7594 }
7595
7596 static int i965gm_get_display_clock_speed(struct drm_i915_private *dev_priv)
7597 {
7598         struct pci_dev *pdev = dev_priv->drm.pdev;
7599         static const uint8_t div_3200[] = { 16, 10,  8 };
7600         static const uint8_t div_4000[] = { 20, 12, 10 };
7601         static const uint8_t div_5333[] = { 24, 16, 14 };
7602         const uint8_t *div_table;
7603         unsigned int cdclk_sel, vco = intel_hpll_vco(dev_priv);
7604         uint16_t tmp = 0;
7605
7606         pci_read_config_word(pdev, GCFGC, &tmp);
7607
7608         cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
7609
7610         if (cdclk_sel >= ARRAY_SIZE(div_3200))
7611                 goto fail;
7612
7613         switch (vco) {
7614         case 3200000:
7615                 div_table = div_3200;
7616                 break;
7617         case 4000000:
7618                 div_table = div_4000;
7619                 break;
7620         case 5333333:
7621                 div_table = div_5333;
7622                 break;
7623         default:
7624                 goto fail;
7625         }
7626
7627         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7628
7629 fail:
7630         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
7631         return 200000;
7632 }
7633
7634 static int g33_get_display_clock_speed(struct drm_i915_private *dev_priv)
7635 {
7636         struct pci_dev *pdev = dev_priv->drm.pdev;
7637         static const uint8_t div_3200[] = { 12, 10,  8,  7, 5, 16 };
7638         static const uint8_t div_4000[] = { 14, 12, 10,  8, 6, 20 };
7639         static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7640         static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7641         const uint8_t *div_table;
7642         unsigned int cdclk_sel, vco = intel_hpll_vco(dev_priv);
7643         uint16_t tmp = 0;
7644
7645         pci_read_config_word(pdev, GCFGC, &tmp);
7646
7647         cdclk_sel = (tmp >> 4) & 0x7;
7648
7649         if (cdclk_sel >= ARRAY_SIZE(div_3200))
7650                 goto fail;
7651
7652         switch (vco) {
7653         case 3200000:
7654                 div_table = div_3200;
7655                 break;
7656         case 4000000:
7657                 div_table = div_4000;
7658                 break;
7659         case 4800000:
7660                 div_table = div_4800;
7661                 break;
7662         case 5333333:
7663                 div_table = div_5333;
7664                 break;
7665         default:
7666                 goto fail;
7667         }
7668
7669         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7670
7671 fail:
7672         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7673         return 190476;
7674 }
7675
7676 static void
7677 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7678 {
7679         while (*num > DATA_LINK_M_N_MASK ||
7680                *den > DATA_LINK_M_N_MASK) {
7681                 *num >>= 1;
7682                 *den >>= 1;
7683         }
7684 }
7685
7686 static void compute_m_n(unsigned int m, unsigned int n,
7687                         uint32_t *ret_m, uint32_t *ret_n)
7688 {
7689         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7690         *ret_m = div_u64((uint64_t) m * *ret_n, n);
7691         intel_reduce_m_n_ratio(ret_m, ret_n);
7692 }
7693
7694 void
7695 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7696                        int pixel_clock, int link_clock,
7697                        struct intel_link_m_n *m_n)
7698 {
7699         m_n->tu = 64;
7700
7701         compute_m_n(bits_per_pixel * pixel_clock,
7702                     link_clock * nlanes * 8,
7703                     &m_n->gmch_m, &m_n->gmch_n);
7704
7705         compute_m_n(pixel_clock, link_clock,
7706                     &m_n->link_m, &m_n->link_n);
7707 }
7708
7709 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7710 {
7711         if (i915.panel_use_ssc >= 0)
7712                 return i915.panel_use_ssc != 0;
7713         return dev_priv->vbt.lvds_use_ssc
7714                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7715 }
7716
7717 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7718 {
7719         return (1 << dpll->n) << 16 | dpll->m2;
7720 }
7721
7722 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7723 {
7724         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7725 }
7726
7727 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7728                                      struct intel_crtc_state *crtc_state,
7729                                      struct dpll *reduced_clock)
7730 {
7731         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7732         u32 fp, fp2 = 0;
7733
7734         if (IS_PINEVIEW(dev_priv)) {
7735                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7736                 if (reduced_clock)
7737                         fp2 = pnv_dpll_compute_fp(reduced_clock);
7738         } else {
7739                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7740                 if (reduced_clock)
7741                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
7742         }
7743
7744         crtc_state->dpll_hw_state.fp0 = fp;
7745
7746         crtc->lowfreq_avail = false;
7747         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7748             reduced_clock) {
7749                 crtc_state->dpll_hw_state.fp1 = fp2;
7750                 crtc->lowfreq_avail = true;
7751         } else {
7752                 crtc_state->dpll_hw_state.fp1 = fp;
7753         }
7754 }
7755
7756 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7757                 pipe)
7758 {
7759         u32 reg_val;
7760
7761         /*
7762          * PLLB opamp always calibrates to max value of 0x3f, force enable it
7763          * and set it to a reasonable value instead.
7764          */
7765         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7766         reg_val &= 0xffffff00;
7767         reg_val |= 0x00000030;
7768         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7769
7770         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7771         reg_val &= 0x8cffffff;
7772         reg_val = 0x8c000000;
7773         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7774
7775         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7776         reg_val &= 0xffffff00;
7777         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7778
7779         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7780         reg_val &= 0x00ffffff;
7781         reg_val |= 0xb0000000;
7782         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7783 }
7784
7785 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7786                                          struct intel_link_m_n *m_n)
7787 {
7788         struct drm_device *dev = crtc->base.dev;
7789         struct drm_i915_private *dev_priv = to_i915(dev);
7790         int pipe = crtc->pipe;
7791
7792         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7793         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7794         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7795         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7796 }
7797
7798 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7799                                          struct intel_link_m_n *m_n,
7800                                          struct intel_link_m_n *m2_n2)
7801 {
7802         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7803         int pipe = crtc->pipe;
7804         enum transcoder transcoder = crtc->config->cpu_transcoder;
7805
7806         if (INTEL_GEN(dev_priv) >= 5) {
7807                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7808                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7809                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7810                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7811                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7812                  * for gen < 8) and if DRRS is supported (to make sure the
7813                  * registers are not unnecessarily accessed).
7814                  */
7815                 if (m2_n2 && (IS_CHERRYVIEW(dev_priv) ||
7816                     INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) {
7817                         I915_WRITE(PIPE_DATA_M2(transcoder),
7818                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7819                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7820                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7821                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7822                 }
7823         } else {
7824                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7825                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7826                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7827                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7828         }
7829 }
7830
7831 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7832 {
7833         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7834
7835         if (m_n == M1_N1) {
7836                 dp_m_n = &crtc->config->dp_m_n;
7837                 dp_m2_n2 = &crtc->config->dp_m2_n2;
7838         } else if (m_n == M2_N2) {
7839
7840                 /*
7841                  * M2_N2 registers are not supported. Hence m2_n2 divider value
7842                  * needs to be programmed into M1_N1.
7843                  */
7844                 dp_m_n = &crtc->config->dp_m2_n2;
7845         } else {
7846                 DRM_ERROR("Unsupported divider value\n");
7847                 return;
7848         }
7849
7850         if (crtc->config->has_pch_encoder)
7851                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7852         else
7853                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7854 }
7855
7856 static void vlv_compute_dpll(struct intel_crtc *crtc,
7857                              struct intel_crtc_state *pipe_config)
7858 {
7859         pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
7860                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7861         if (crtc->pipe != PIPE_A)
7862                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7863
7864         /* DPLL not used with DSI, but still need the rest set up */
7865         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
7866                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
7867                         DPLL_EXT_BUFFER_ENABLE_VLV;
7868
7869         pipe_config->dpll_hw_state.dpll_md =
7870                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7871 }
7872
7873 static void chv_compute_dpll(struct intel_crtc *crtc,
7874                              struct intel_crtc_state *pipe_config)
7875 {
7876         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7877                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7878         if (crtc->pipe != PIPE_A)
7879                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7880
7881         /* DPLL not used with DSI, but still need the rest set up */
7882         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
7883                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
7884
7885         pipe_config->dpll_hw_state.dpll_md =
7886                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7887 }
7888
7889 static void vlv_prepare_pll(struct intel_crtc *crtc,
7890                             const struct intel_crtc_state *pipe_config)
7891 {
7892         struct drm_device *dev = crtc->base.dev;
7893         struct drm_i915_private *dev_priv = to_i915(dev);
7894         enum pipe pipe = crtc->pipe;
7895         u32 mdiv;
7896         u32 bestn, bestm1, bestm2, bestp1, bestp2;
7897         u32 coreclk, reg_val;
7898
7899         /* Enable Refclk */
7900         I915_WRITE(DPLL(pipe),
7901                    pipe_config->dpll_hw_state.dpll &
7902                    ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
7903
7904         /* No need to actually set up the DPLL with DSI */
7905         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7906                 return;
7907
7908         mutex_lock(&dev_priv->sb_lock);
7909
7910         bestn = pipe_config->dpll.n;
7911         bestm1 = pipe_config->dpll.m1;
7912         bestm2 = pipe_config->dpll.m2;
7913         bestp1 = pipe_config->dpll.p1;
7914         bestp2 = pipe_config->dpll.p2;
7915
7916         /* See eDP HDMI DPIO driver vbios notes doc */
7917
7918         /* PLL B needs special handling */
7919         if (pipe == PIPE_B)
7920                 vlv_pllb_recal_opamp(dev_priv, pipe);
7921
7922         /* Set up Tx target for periodic Rcomp update */
7923         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7924
7925         /* Disable target IRef on PLL */
7926         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7927         reg_val &= 0x00ffffff;
7928         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7929
7930         /* Disable fast lock */
7931         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7932
7933         /* Set idtafcrecal before PLL is enabled */
7934         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7935         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7936         mdiv |= ((bestn << DPIO_N_SHIFT));
7937         mdiv |= (1 << DPIO_K_SHIFT);
7938
7939         /*
7940          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7941          * but we don't support that).
7942          * Note: don't use the DAC post divider as it seems unstable.
7943          */
7944         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7945         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7946
7947         mdiv |= DPIO_ENABLE_CALIBRATION;
7948         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7949
7950         /* Set HBR and RBR LPF coefficients */
7951         if (pipe_config->port_clock == 162000 ||
7952             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) ||
7953             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI))
7954                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7955                                  0x009f0003);
7956         else
7957                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7958                                  0x00d0000f);
7959
7960         if (intel_crtc_has_dp_encoder(pipe_config)) {
7961                 /* Use SSC source */
7962                 if (pipe == PIPE_A)
7963                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7964                                          0x0df40000);
7965                 else
7966                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7967                                          0x0df70000);
7968         } else { /* HDMI or VGA */
7969                 /* Use bend source */
7970                 if (pipe == PIPE_A)
7971                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7972                                          0x0df70000);
7973                 else
7974                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7975                                          0x0df40000);
7976         }
7977
7978         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7979         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7980         if (intel_crtc_has_dp_encoder(crtc->config))
7981                 coreclk |= 0x01000000;
7982         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7983
7984         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7985         mutex_unlock(&dev_priv->sb_lock);
7986 }
7987
7988 static void chv_prepare_pll(struct intel_crtc *crtc,
7989                             const struct intel_crtc_state *pipe_config)
7990 {
7991         struct drm_device *dev = crtc->base.dev;
7992         struct drm_i915_private *dev_priv = to_i915(dev);
7993         enum pipe pipe = crtc->pipe;
7994         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7995         u32 loopfilter, tribuf_calcntr;
7996         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7997         u32 dpio_val;
7998         int vco;
7999
8000         /* Enable Refclk and SSC */
8001         I915_WRITE(DPLL(pipe),
8002                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
8003
8004         /* No need to actually set up the DPLL with DSI */
8005         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8006                 return;
8007
8008         bestn = pipe_config->dpll.n;
8009         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
8010         bestm1 = pipe_config->dpll.m1;
8011         bestm2 = pipe_config->dpll.m2 >> 22;
8012         bestp1 = pipe_config->dpll.p1;
8013         bestp2 = pipe_config->dpll.p2;
8014         vco = pipe_config->dpll.vco;
8015         dpio_val = 0;
8016         loopfilter = 0;
8017
8018         mutex_lock(&dev_priv->sb_lock);
8019
8020         /* p1 and p2 divider */
8021         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
8022                         5 << DPIO_CHV_S1_DIV_SHIFT |
8023                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
8024                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
8025                         1 << DPIO_CHV_K_DIV_SHIFT);
8026
8027         /* Feedback post-divider - m2 */
8028         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
8029
8030         /* Feedback refclk divider - n and m1 */
8031         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
8032                         DPIO_CHV_M1_DIV_BY_2 |
8033                         1 << DPIO_CHV_N_DIV_SHIFT);
8034
8035         /* M2 fraction division */
8036         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
8037
8038         /* M2 fraction division enable */
8039         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8040         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
8041         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
8042         if (bestm2_frac)
8043                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
8044         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
8045
8046         /* Program digital lock detect threshold */
8047         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
8048         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
8049                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
8050         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
8051         if (!bestm2_frac)
8052                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
8053         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
8054
8055         /* Loop filter */
8056         if (vco == 5400000) {
8057                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
8058                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
8059                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
8060                 tribuf_calcntr = 0x9;
8061         } else if (vco <= 6200000) {
8062                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
8063                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
8064                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8065                 tribuf_calcntr = 0x9;
8066         } else if (vco <= 6480000) {
8067                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
8068                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
8069                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8070                 tribuf_calcntr = 0x8;
8071         } else {
8072                 /* Not supported. Apply the same limits as in the max case */
8073                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
8074                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
8075                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8076                 tribuf_calcntr = 0;
8077         }
8078         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
8079
8080         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
8081         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
8082         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
8083         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
8084
8085         /* AFC Recal */
8086         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
8087                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
8088                         DPIO_AFC_RECAL);
8089
8090         mutex_unlock(&dev_priv->sb_lock);
8091 }
8092
8093 /**
8094  * vlv_force_pll_on - forcibly enable just the PLL
8095  * @dev_priv: i915 private structure
8096  * @pipe: pipe PLL to enable
8097  * @dpll: PLL configuration
8098  *
8099  * Enable the PLL for @pipe using the supplied @dpll config. To be used
8100  * in cases where we need the PLL enabled even when @pipe is not going to
8101  * be enabled.
8102  */
8103 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
8104                      const struct dpll *dpll)
8105 {
8106         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
8107         struct intel_crtc_state *pipe_config;
8108
8109         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8110         if (!pipe_config)
8111                 return -ENOMEM;
8112
8113         pipe_config->base.crtc = &crtc->base;
8114         pipe_config->pixel_multiplier = 1;
8115         pipe_config->dpll = *dpll;
8116
8117         if (IS_CHERRYVIEW(dev_priv)) {
8118                 chv_compute_dpll(crtc, pipe_config);
8119                 chv_prepare_pll(crtc, pipe_config);
8120                 chv_enable_pll(crtc, pipe_config);
8121         } else {
8122                 vlv_compute_dpll(crtc, pipe_config);
8123                 vlv_prepare_pll(crtc, pipe_config);
8124                 vlv_enable_pll(crtc, pipe_config);
8125         }
8126
8127         kfree(pipe_config);
8128
8129         return 0;
8130 }
8131
8132 /**
8133  * vlv_force_pll_off - forcibly disable just the PLL
8134  * @dev_priv: i915 private structure
8135  * @pipe: pipe PLL to disable
8136  *
8137  * Disable the PLL for @pipe. To be used in cases where we need
8138  * the PLL enabled even when @pipe is not going to be enabled.
8139  */
8140 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
8141 {
8142         if (IS_CHERRYVIEW(dev_priv))
8143                 chv_disable_pll(dev_priv, pipe);
8144         else
8145                 vlv_disable_pll(dev_priv, pipe);
8146 }
8147
8148 static void i9xx_compute_dpll(struct intel_crtc *crtc,
8149                               struct intel_crtc_state *crtc_state,
8150                               struct dpll *reduced_clock)
8151 {
8152         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8153         u32 dpll;
8154         struct dpll *clock = &crtc_state->dpll;
8155
8156         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8157
8158         dpll = DPLL_VGA_MODE_DIS;
8159
8160         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8161                 dpll |= DPLLB_MODE_LVDS;
8162         else
8163                 dpll |= DPLLB_MODE_DAC_SERIAL;
8164
8165         if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
8166             IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
8167                 dpll |= (crtc_state->pixel_multiplier - 1)
8168                         << SDVO_MULTIPLIER_SHIFT_HIRES;
8169         }
8170
8171         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8172             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8173                 dpll |= DPLL_SDVO_HIGH_SPEED;
8174
8175         if (intel_crtc_has_dp_encoder(crtc_state))
8176                 dpll |= DPLL_SDVO_HIGH_SPEED;
8177
8178         /* compute bitmask from p1 value */
8179         if (IS_PINEVIEW(dev_priv))
8180                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
8181         else {
8182                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8183                 if (IS_G4X(dev_priv) && reduced_clock)
8184                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8185         }
8186         switch (clock->p2) {
8187         case 5:
8188                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8189                 break;
8190         case 7:
8191                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8192                 break;
8193         case 10:
8194                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8195                 break;
8196         case 14:
8197                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8198                 break;
8199         }
8200         if (INTEL_GEN(dev_priv) >= 4)
8201                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
8202
8203         if (crtc_state->sdvo_tv_clock)
8204                 dpll |= PLL_REF_INPUT_TVCLKINBC;
8205         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8206                  intel_panel_use_ssc(dev_priv))
8207                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8208         else
8209                 dpll |= PLL_REF_INPUT_DREFCLK;
8210
8211         dpll |= DPLL_VCO_ENABLE;
8212         crtc_state->dpll_hw_state.dpll = dpll;
8213
8214         if (INTEL_GEN(dev_priv) >= 4) {
8215                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
8216                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8217                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
8218         }
8219 }
8220
8221 static void i8xx_compute_dpll(struct intel_crtc *crtc,
8222                               struct intel_crtc_state *crtc_state,
8223                               struct dpll *reduced_clock)
8224 {
8225         struct drm_device *dev = crtc->base.dev;
8226         struct drm_i915_private *dev_priv = to_i915(dev);
8227         u32 dpll;
8228         struct dpll *clock = &crtc_state->dpll;
8229
8230         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8231
8232         dpll = DPLL_VGA_MODE_DIS;
8233
8234         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8235                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8236         } else {
8237                 if (clock->p1 == 2)
8238                         dpll |= PLL_P1_DIVIDE_BY_TWO;
8239                 else
8240                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8241                 if (clock->p2 == 4)
8242                         dpll |= PLL_P2_DIVIDE_BY_4;
8243         }
8244
8245         if (!IS_I830(dev_priv) &&
8246             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
8247                 dpll |= DPLL_DVO_2X_MODE;
8248
8249         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8250             intel_panel_use_ssc(dev_priv))
8251                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8252         else
8253                 dpll |= PLL_REF_INPUT_DREFCLK;
8254
8255         dpll |= DPLL_VCO_ENABLE;
8256         crtc_state->dpll_hw_state.dpll = dpll;
8257 }
8258
8259 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
8260 {
8261         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
8262         enum pipe pipe = intel_crtc->pipe;
8263         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8264         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
8265         uint32_t crtc_vtotal, crtc_vblank_end;
8266         int vsyncshift = 0;
8267
8268         /* We need to be careful not to changed the adjusted mode, for otherwise
8269          * the hw state checker will get angry at the mismatch. */
8270         crtc_vtotal = adjusted_mode->crtc_vtotal;
8271         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
8272
8273         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
8274                 /* the chip adds 2 halflines automatically */
8275                 crtc_vtotal -= 1;
8276                 crtc_vblank_end -= 1;
8277
8278                 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
8279                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
8280                 else
8281                         vsyncshift = adjusted_mode->crtc_hsync_start -
8282                                 adjusted_mode->crtc_htotal / 2;
8283                 if (vsyncshift < 0)
8284                         vsyncshift += adjusted_mode->crtc_htotal;
8285         }
8286
8287         if (INTEL_GEN(dev_priv) > 3)
8288                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
8289
8290         I915_WRITE(HTOTAL(cpu_transcoder),
8291                    (adjusted_mode->crtc_hdisplay - 1) |
8292                    ((adjusted_mode->crtc_htotal - 1) << 16));
8293         I915_WRITE(HBLANK(cpu_transcoder),
8294                    (adjusted_mode->crtc_hblank_start - 1) |
8295                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
8296         I915_WRITE(HSYNC(cpu_transcoder),
8297                    (adjusted_mode->crtc_hsync_start - 1) |
8298                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
8299
8300         I915_WRITE(VTOTAL(cpu_transcoder),
8301                    (adjusted_mode->crtc_vdisplay - 1) |
8302                    ((crtc_vtotal - 1) << 16));
8303         I915_WRITE(VBLANK(cpu_transcoder),
8304                    (adjusted_mode->crtc_vblank_start - 1) |
8305                    ((crtc_vblank_end - 1) << 16));
8306         I915_WRITE(VSYNC(cpu_transcoder),
8307                    (adjusted_mode->crtc_vsync_start - 1) |
8308                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
8309
8310         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
8311          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
8312          * documented on the DDI_FUNC_CTL register description, EDP Input Select
8313          * bits. */
8314         if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
8315             (pipe == PIPE_B || pipe == PIPE_C))
8316                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
8317
8318 }
8319
8320 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
8321 {
8322         struct drm_device *dev = intel_crtc->base.dev;
8323         struct drm_i915_private *dev_priv = to_i915(dev);
8324         enum pipe pipe = intel_crtc->pipe;
8325
8326         /* pipesrc controls the size that is scaled from, which should
8327          * always be the user's requested size.
8328          */
8329         I915_WRITE(PIPESRC(pipe),
8330                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
8331                    (intel_crtc->config->pipe_src_h - 1));
8332 }
8333
8334 static void intel_get_pipe_timings(struct intel_crtc *crtc,
8335                                    struct intel_crtc_state *pipe_config)
8336 {
8337         struct drm_device *dev = crtc->base.dev;
8338         struct drm_i915_private *dev_priv = to_i915(dev);
8339         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
8340         uint32_t tmp;
8341
8342         tmp = I915_READ(HTOTAL(cpu_transcoder));
8343         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
8344         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
8345         tmp = I915_READ(HBLANK(cpu_transcoder));
8346         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
8347         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
8348         tmp = I915_READ(HSYNC(cpu_transcoder));
8349         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
8350         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
8351
8352         tmp = I915_READ(VTOTAL(cpu_transcoder));
8353         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
8354         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
8355         tmp = I915_READ(VBLANK(cpu_transcoder));
8356         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
8357         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
8358         tmp = I915_READ(VSYNC(cpu_transcoder));
8359         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
8360         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
8361
8362         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
8363                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
8364                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
8365                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
8366         }
8367 }
8368
8369 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
8370                                     struct intel_crtc_state *pipe_config)
8371 {
8372         struct drm_device *dev = crtc->base.dev;
8373         struct drm_i915_private *dev_priv = to_i915(dev);
8374         u32 tmp;
8375
8376         tmp = I915_READ(PIPESRC(crtc->pipe));
8377         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
8378         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
8379
8380         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
8381         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
8382 }
8383
8384 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
8385                                  struct intel_crtc_state *pipe_config)
8386 {
8387         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
8388         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
8389         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
8390         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
8391
8392         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
8393         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
8394         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
8395         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
8396
8397         mode->flags = pipe_config->base.adjusted_mode.flags;
8398         mode->type = DRM_MODE_TYPE_DRIVER;
8399
8400         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
8401
8402         mode->hsync = drm_mode_hsync(mode);
8403         mode->vrefresh = drm_mode_vrefresh(mode);
8404         drm_mode_set_name(mode);
8405 }
8406
8407 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
8408 {
8409         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
8410         uint32_t pipeconf;
8411
8412         pipeconf = 0;
8413
8414         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
8415             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
8416                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
8417
8418         if (intel_crtc->config->double_wide)
8419                 pipeconf |= PIPECONF_DOUBLE_WIDE;
8420
8421         /* only g4x and later have fancy bpc/dither controls */
8422         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
8423             IS_CHERRYVIEW(dev_priv)) {
8424                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
8425                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
8426                         pipeconf |= PIPECONF_DITHER_EN |
8427                                     PIPECONF_DITHER_TYPE_SP;
8428
8429                 switch (intel_crtc->config->pipe_bpp) {
8430                 case 18:
8431                         pipeconf |= PIPECONF_6BPC;
8432                         break;
8433                 case 24:
8434                         pipeconf |= PIPECONF_8BPC;
8435                         break;
8436                 case 30:
8437                         pipeconf |= PIPECONF_10BPC;
8438                         break;
8439                 default:
8440                         /* Case prevented by intel_choose_pipe_bpp_dither. */
8441                         BUG();
8442                 }
8443         }
8444
8445         if (HAS_PIPE_CXSR(dev_priv)) {
8446                 if (intel_crtc->lowfreq_avail) {
8447                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
8448                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
8449                 } else {
8450                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
8451                 }
8452         }
8453
8454         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
8455                 if (INTEL_GEN(dev_priv) < 4 ||
8456                     intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
8457                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
8458                 else
8459                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
8460         } else
8461                 pipeconf |= PIPECONF_PROGRESSIVE;
8462
8463         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
8464              intel_crtc->config->limited_color_range)
8465                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
8466
8467         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
8468         POSTING_READ(PIPECONF(intel_crtc->pipe));
8469 }
8470
8471 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
8472                                    struct intel_crtc_state *crtc_state)
8473 {
8474         struct drm_device *dev = crtc->base.dev;
8475         struct drm_i915_private *dev_priv = to_i915(dev);
8476         const struct intel_limit *limit;
8477         int refclk = 48000;
8478
8479         memset(&crtc_state->dpll_hw_state, 0,
8480                sizeof(crtc_state->dpll_hw_state));
8481
8482         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8483                 if (intel_panel_use_ssc(dev_priv)) {
8484                         refclk = dev_priv->vbt.lvds_ssc_freq;
8485                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8486                 }
8487
8488                 limit = &intel_limits_i8xx_lvds;
8489         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
8490                 limit = &intel_limits_i8xx_dvo;
8491         } else {
8492                 limit = &intel_limits_i8xx_dac;
8493         }
8494
8495         if (!crtc_state->clock_set &&
8496             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8497                                  refclk, NULL, &crtc_state->dpll)) {
8498                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8499                 return -EINVAL;
8500         }
8501
8502         i8xx_compute_dpll(crtc, crtc_state, NULL);
8503
8504         return 0;
8505 }
8506
8507 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
8508                                   struct intel_crtc_state *crtc_state)
8509 {
8510         struct drm_device *dev = crtc->base.dev;
8511         struct drm_i915_private *dev_priv = to_i915(dev);
8512         const struct intel_limit *limit;
8513         int refclk = 96000;
8514
8515         memset(&crtc_state->dpll_hw_state, 0,
8516                sizeof(crtc_state->dpll_hw_state));
8517
8518         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8519                 if (intel_panel_use_ssc(dev_priv)) {
8520                         refclk = dev_priv->vbt.lvds_ssc_freq;
8521                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8522                 }
8523
8524                 if (intel_is_dual_link_lvds(dev))
8525                         limit = &intel_limits_g4x_dual_channel_lvds;
8526                 else
8527                         limit = &intel_limits_g4x_single_channel_lvds;
8528         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
8529                    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
8530                 limit = &intel_limits_g4x_hdmi;
8531         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
8532                 limit = &intel_limits_g4x_sdvo;
8533         } else {
8534                 /* The option is for other outputs */
8535                 limit = &intel_limits_i9xx_sdvo;
8536         }
8537
8538         if (!crtc_state->clock_set &&
8539             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8540                                 refclk, NULL, &crtc_state->dpll)) {
8541                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8542                 return -EINVAL;
8543         }
8544
8545         i9xx_compute_dpll(crtc, crtc_state, NULL);
8546
8547         return 0;
8548 }
8549
8550 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
8551                                   struct intel_crtc_state *crtc_state)
8552 {
8553         struct drm_device *dev = crtc->base.dev;
8554         struct drm_i915_private *dev_priv = to_i915(dev);
8555         const struct intel_limit *limit;
8556         int refclk = 96000;
8557
8558         memset(&crtc_state->dpll_hw_state, 0,
8559                sizeof(crtc_state->dpll_hw_state));
8560
8561         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8562                 if (intel_panel_use_ssc(dev_priv)) {
8563                         refclk = dev_priv->vbt.lvds_ssc_freq;
8564                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8565                 }
8566
8567                 limit = &intel_limits_pineview_lvds;
8568         } else {
8569                 limit = &intel_limits_pineview_sdvo;
8570         }
8571
8572         if (!crtc_state->clock_set &&
8573             !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8574                                 refclk, NULL, &crtc_state->dpll)) {
8575                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8576                 return -EINVAL;
8577         }
8578
8579         i9xx_compute_dpll(crtc, crtc_state, NULL);
8580
8581         return 0;
8582 }
8583
8584 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
8585                                    struct intel_crtc_state *crtc_state)
8586 {
8587         struct drm_device *dev = crtc->base.dev;
8588         struct drm_i915_private *dev_priv = to_i915(dev);
8589         const struct intel_limit *limit;
8590         int refclk = 96000;
8591
8592         memset(&crtc_state->dpll_hw_state, 0,
8593                sizeof(crtc_state->dpll_hw_state));
8594
8595         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8596                 if (intel_panel_use_ssc(dev_priv)) {
8597                         refclk = dev_priv->vbt.lvds_ssc_freq;
8598                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8599                 }
8600
8601                 limit = &intel_limits_i9xx_lvds;
8602         } else {
8603                 limit = &intel_limits_i9xx_sdvo;
8604         }
8605
8606         if (!crtc_state->clock_set &&
8607             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8608                                  refclk, NULL, &crtc_state->dpll)) {
8609                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8610                 return -EINVAL;
8611         }
8612
8613         i9xx_compute_dpll(crtc, crtc_state, NULL);
8614
8615         return 0;
8616 }
8617
8618 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
8619                                   struct intel_crtc_state *crtc_state)
8620 {
8621         int refclk = 100000;
8622         const struct intel_limit *limit = &intel_limits_chv;
8623
8624         memset(&crtc_state->dpll_hw_state, 0,
8625                sizeof(crtc_state->dpll_hw_state));
8626
8627         if (!crtc_state->clock_set &&
8628             !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8629                                 refclk, NULL, &crtc_state->dpll)) {
8630                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8631                 return -EINVAL;
8632         }
8633
8634         chv_compute_dpll(crtc, crtc_state);
8635
8636         return 0;
8637 }
8638
8639 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
8640                                   struct intel_crtc_state *crtc_state)
8641 {
8642         int refclk = 100000;
8643         const struct intel_limit *limit = &intel_limits_vlv;
8644
8645         memset(&crtc_state->dpll_hw_state, 0,
8646                sizeof(crtc_state->dpll_hw_state));
8647
8648         if (!crtc_state->clock_set &&
8649             !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8650                                 refclk, NULL, &crtc_state->dpll)) {
8651                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8652                 return -EINVAL;
8653         }
8654
8655         vlv_compute_dpll(crtc, crtc_state);
8656
8657         return 0;
8658 }
8659
8660 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
8661                                  struct intel_crtc_state *pipe_config)
8662 {
8663         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8664         uint32_t tmp;
8665
8666         if (INTEL_GEN(dev_priv) <= 3 &&
8667             (IS_I830(dev_priv) || !IS_MOBILE(dev_priv)))
8668                 return;
8669
8670         tmp = I915_READ(PFIT_CONTROL);
8671         if (!(tmp & PFIT_ENABLE))
8672                 return;
8673
8674         /* Check whether the pfit is attached to our pipe. */
8675         if (INTEL_GEN(dev_priv) < 4) {
8676                 if (crtc->pipe != PIPE_B)
8677                         return;
8678         } else {
8679                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
8680                         return;
8681         }
8682
8683         pipe_config->gmch_pfit.control = tmp;
8684         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
8685 }
8686
8687 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8688                                struct intel_crtc_state *pipe_config)
8689 {
8690         struct drm_device *dev = crtc->base.dev;
8691         struct drm_i915_private *dev_priv = to_i915(dev);
8692         int pipe = pipe_config->cpu_transcoder;
8693         struct dpll clock;
8694         u32 mdiv;
8695         int refclk = 100000;
8696
8697         /* In case of DSI, DPLL will not be used */
8698         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8699                 return;
8700
8701         mutex_lock(&dev_priv->sb_lock);
8702         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8703         mutex_unlock(&dev_priv->sb_lock);
8704
8705         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8706         clock.m2 = mdiv & DPIO_M2DIV_MASK;
8707         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8708         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8709         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8710
8711         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8712 }
8713
8714 static void
8715 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8716                               struct intel_initial_plane_config *plane_config)
8717 {
8718         struct drm_device *dev = crtc->base.dev;
8719         struct drm_i915_private *dev_priv = to_i915(dev);
8720         u32 val, base, offset;
8721         int pipe = crtc->pipe, plane = crtc->plane;
8722         int fourcc, pixel_format;
8723         unsigned int aligned_height;
8724         struct drm_framebuffer *fb;
8725         struct intel_framebuffer *intel_fb;
8726
8727         val = I915_READ(DSPCNTR(plane));
8728         if (!(val & DISPLAY_PLANE_ENABLE))
8729                 return;
8730
8731         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8732         if (!intel_fb) {
8733                 DRM_DEBUG_KMS("failed to alloc fb\n");
8734                 return;
8735         }
8736
8737         fb = &intel_fb->base;
8738
8739         fb->dev = dev;
8740
8741         if (INTEL_GEN(dev_priv) >= 4) {
8742                 if (val & DISPPLANE_TILED) {
8743                         plane_config->tiling = I915_TILING_X;
8744                         fb->modifier = I915_FORMAT_MOD_X_TILED;
8745                 }
8746         }
8747
8748         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8749         fourcc = i9xx_format_to_fourcc(pixel_format);
8750         fb->format = drm_format_info(fourcc);
8751
8752         if (INTEL_GEN(dev_priv) >= 4) {
8753                 if (plane_config->tiling)
8754                         offset = I915_READ(DSPTILEOFF(plane));
8755                 else
8756                         offset = I915_READ(DSPLINOFF(plane));
8757                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8758         } else {
8759                 base = I915_READ(DSPADDR(plane));
8760         }
8761         plane_config->base = base;
8762
8763         val = I915_READ(PIPESRC(pipe));
8764         fb->width = ((val >> 16) & 0xfff) + 1;
8765         fb->height = ((val >> 0) & 0xfff) + 1;
8766
8767         val = I915_READ(DSPSTRIDE(pipe));
8768         fb->pitches[0] = val & 0xffffffc0;
8769
8770         aligned_height = intel_fb_align_height(dev, fb->height,
8771                                                fb->format->format,
8772                                                fb->modifier);
8773
8774         plane_config->size = fb->pitches[0] * aligned_height;
8775
8776         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8777                       pipe_name(pipe), plane, fb->width, fb->height,
8778                       fb->format->cpp[0] * 8, base, fb->pitches[0],
8779                       plane_config->size);
8780
8781         plane_config->fb = intel_fb;
8782 }
8783
8784 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8785                                struct intel_crtc_state *pipe_config)
8786 {
8787         struct drm_device *dev = crtc->base.dev;
8788         struct drm_i915_private *dev_priv = to_i915(dev);
8789         int pipe = pipe_config->cpu_transcoder;
8790         enum dpio_channel port = vlv_pipe_to_channel(pipe);
8791         struct dpll clock;
8792         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8793         int refclk = 100000;
8794
8795         /* In case of DSI, DPLL will not be used */
8796         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8797                 return;
8798
8799         mutex_lock(&dev_priv->sb_lock);
8800         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8801         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8802         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8803         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8804         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8805         mutex_unlock(&dev_priv->sb_lock);
8806
8807         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8808         clock.m2 = (pll_dw0 & 0xff) << 22;
8809         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8810                 clock.m2 |= pll_dw2 & 0x3fffff;
8811         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8812         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8813         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8814
8815         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8816 }
8817
8818 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8819                                  struct intel_crtc_state *pipe_config)
8820 {
8821         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8822         enum intel_display_power_domain power_domain;
8823         uint32_t tmp;
8824         bool ret;
8825
8826         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8827         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8828                 return false;
8829
8830         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8831         pipe_config->shared_dpll = NULL;
8832
8833         ret = false;
8834
8835         tmp = I915_READ(PIPECONF(crtc->pipe));
8836         if (!(tmp & PIPECONF_ENABLE))
8837                 goto out;
8838
8839         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
8840             IS_CHERRYVIEW(dev_priv)) {
8841                 switch (tmp & PIPECONF_BPC_MASK) {
8842                 case PIPECONF_6BPC:
8843                         pipe_config->pipe_bpp = 18;
8844                         break;
8845                 case PIPECONF_8BPC:
8846                         pipe_config->pipe_bpp = 24;
8847                         break;
8848                 case PIPECONF_10BPC:
8849                         pipe_config->pipe_bpp = 30;
8850                         break;
8851                 default:
8852                         break;
8853                 }
8854         }
8855
8856         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
8857             (tmp & PIPECONF_COLOR_RANGE_SELECT))
8858                 pipe_config->limited_color_range = true;
8859
8860         if (INTEL_GEN(dev_priv) < 4)
8861                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8862
8863         intel_get_pipe_timings(crtc, pipe_config);
8864         intel_get_pipe_src_size(crtc, pipe_config);
8865
8866         i9xx_get_pfit_config(crtc, pipe_config);
8867
8868         if (INTEL_GEN(dev_priv) >= 4) {
8869                 /* No way to read it out on pipes B and C */
8870                 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
8871                         tmp = dev_priv->chv_dpll_md[crtc->pipe];
8872                 else
8873                         tmp = I915_READ(DPLL_MD(crtc->pipe));
8874                 pipe_config->pixel_multiplier =
8875                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8876                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8877                 pipe_config->dpll_hw_state.dpll_md = tmp;
8878         } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
8879                    IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
8880                 tmp = I915_READ(DPLL(crtc->pipe));
8881                 pipe_config->pixel_multiplier =
8882                         ((tmp & SDVO_MULTIPLIER_MASK)
8883                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8884         } else {
8885                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8886                  * port and will be fixed up in the encoder->get_config
8887                  * function. */
8888                 pipe_config->pixel_multiplier = 1;
8889         }
8890         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8891         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
8892                 /*
8893                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8894                  * on 830. Filter it out here so that we don't
8895                  * report errors due to that.
8896                  */
8897                 if (IS_I830(dev_priv))
8898                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8899
8900                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8901                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8902         } else {
8903                 /* Mask out read-only status bits. */
8904                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8905                                                      DPLL_PORTC_READY_MASK |
8906                                                      DPLL_PORTB_READY_MASK);
8907         }
8908
8909         if (IS_CHERRYVIEW(dev_priv))
8910                 chv_crtc_clock_get(crtc, pipe_config);
8911         else if (IS_VALLEYVIEW(dev_priv))
8912                 vlv_crtc_clock_get(crtc, pipe_config);
8913         else
8914                 i9xx_crtc_clock_get(crtc, pipe_config);
8915
8916         /*
8917          * Normally the dotclock is filled in by the encoder .get_config()
8918          * but in case the pipe is enabled w/o any ports we need a sane
8919          * default.
8920          */
8921         pipe_config->base.adjusted_mode.crtc_clock =
8922                 pipe_config->port_clock / pipe_config->pixel_multiplier;
8923
8924         ret = true;
8925
8926 out:
8927         intel_display_power_put(dev_priv, power_domain);
8928
8929         return ret;
8930 }
8931
8932 static void ironlake_init_pch_refclk(struct drm_i915_private *dev_priv)
8933 {
8934         struct intel_encoder *encoder;
8935         int i;
8936         u32 val, final;
8937         bool has_lvds = false;
8938         bool has_cpu_edp = false;
8939         bool has_panel = false;
8940         bool has_ck505 = false;
8941         bool can_ssc = false;
8942         bool using_ssc_source = false;
8943
8944         /* We need to take the global config into account */
8945         for_each_intel_encoder(&dev_priv->drm, encoder) {
8946                 switch (encoder->type) {
8947                 case INTEL_OUTPUT_LVDS:
8948                         has_panel = true;
8949                         has_lvds = true;
8950                         break;
8951                 case INTEL_OUTPUT_EDP:
8952                         has_panel = true;
8953                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8954                                 has_cpu_edp = true;
8955                         break;
8956                 default:
8957                         break;
8958                 }
8959         }
8960
8961         if (HAS_PCH_IBX(dev_priv)) {
8962                 has_ck505 = dev_priv->vbt.display_clock_mode;
8963                 can_ssc = has_ck505;
8964         } else {
8965                 has_ck505 = false;
8966                 can_ssc = true;
8967         }
8968
8969         /* Check if any DPLLs are using the SSC source */
8970         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8971                 u32 temp = I915_READ(PCH_DPLL(i));
8972
8973                 if (!(temp & DPLL_VCO_ENABLE))
8974                         continue;
8975
8976                 if ((temp & PLL_REF_INPUT_MASK) ==
8977                     PLLB_REF_INPUT_SPREADSPECTRUMIN) {
8978                         using_ssc_source = true;
8979                         break;
8980                 }
8981         }
8982
8983         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
8984                       has_panel, has_lvds, has_ck505, using_ssc_source);
8985
8986         /* Ironlake: try to setup display ref clock before DPLL
8987          * enabling. This is only under driver's control after
8988          * PCH B stepping, previous chipset stepping should be
8989          * ignoring this setting.
8990          */
8991         val = I915_READ(PCH_DREF_CONTROL);
8992
8993         /* As we must carefully and slowly disable/enable each source in turn,
8994          * compute the final state we want first and check if we need to
8995          * make any changes at all.
8996          */
8997         final = val;
8998         final &= ~DREF_NONSPREAD_SOURCE_MASK;
8999         if (has_ck505)
9000                 final |= DREF_NONSPREAD_CK505_ENABLE;
9001         else
9002                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
9003
9004         final &= ~DREF_SSC_SOURCE_MASK;
9005         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9006         final &= ~DREF_SSC1_ENABLE;
9007
9008         if (has_panel) {
9009                 final |= DREF_SSC_SOURCE_ENABLE;
9010
9011                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
9012                         final |= DREF_SSC1_ENABLE;
9013
9014                 if (has_cpu_edp) {
9015                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
9016                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
9017                         else
9018                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
9019                 } else
9020                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9021         } else if (using_ssc_source) {
9022                 final |= DREF_SSC_SOURCE_ENABLE;
9023                 final |= DREF_SSC1_ENABLE;
9024         }
9025
9026         if (final == val)
9027                 return;
9028
9029         /* Always enable nonspread source */
9030         val &= ~DREF_NONSPREAD_SOURCE_MASK;
9031
9032         if (has_ck505)
9033                 val |= DREF_NONSPREAD_CK505_ENABLE;
9034         else
9035                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
9036
9037         if (has_panel) {
9038                 val &= ~DREF_SSC_SOURCE_MASK;
9039                 val |= DREF_SSC_SOURCE_ENABLE;
9040
9041                 /* SSC must be turned on before enabling the CPU output  */
9042                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
9043                         DRM_DEBUG_KMS("Using SSC on panel\n");
9044                         val |= DREF_SSC1_ENABLE;
9045                 } else
9046                         val &= ~DREF_SSC1_ENABLE;
9047
9048                 /* Get SSC going before enabling the outputs */
9049                 I915_WRITE(PCH_DREF_CONTROL, val);
9050                 POSTING_READ(PCH_DREF_CONTROL);
9051                 udelay(200);
9052
9053                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9054
9055                 /* Enable CPU source on CPU attached eDP */
9056                 if (has_cpu_edp) {
9057                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
9058                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
9059                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
9060                         } else
9061                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
9062                 } else
9063                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9064
9065                 I915_WRITE(PCH_DREF_CONTROL, val);
9066                 POSTING_READ(PCH_DREF_CONTROL);
9067                 udelay(200);
9068         } else {
9069                 DRM_DEBUG_KMS("Disabling CPU source output\n");
9070
9071                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9072
9073                 /* Turn off CPU output */
9074                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9075
9076                 I915_WRITE(PCH_DREF_CONTROL, val);
9077                 POSTING_READ(PCH_DREF_CONTROL);
9078                 udelay(200);
9079
9080                 if (!using_ssc_source) {
9081                         DRM_DEBUG_KMS("Disabling SSC source\n");
9082
9083                         /* Turn off the SSC source */
9084                         val &= ~DREF_SSC_SOURCE_MASK;
9085                         val |= DREF_SSC_SOURCE_DISABLE;
9086
9087                         /* Turn off SSC1 */
9088                         val &= ~DREF_SSC1_ENABLE;
9089
9090                         I915_WRITE(PCH_DREF_CONTROL, val);
9091                         POSTING_READ(PCH_DREF_CONTROL);
9092                         udelay(200);
9093                 }
9094         }
9095
9096         BUG_ON(val != final);
9097 }
9098
9099 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
9100 {
9101         uint32_t tmp;
9102
9103         tmp = I915_READ(SOUTH_CHICKEN2);
9104         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
9105         I915_WRITE(SOUTH_CHICKEN2, tmp);
9106
9107         if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
9108                         FDI_MPHY_IOSFSB_RESET_STATUS, 100))
9109                 DRM_ERROR("FDI mPHY reset assert timeout\n");
9110
9111         tmp = I915_READ(SOUTH_CHICKEN2);
9112         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
9113         I915_WRITE(SOUTH_CHICKEN2, tmp);
9114
9115         if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
9116                          FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
9117                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
9118 }
9119
9120 /* WaMPhyProgramming:hsw */
9121 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
9122 {
9123         uint32_t tmp;
9124
9125         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
9126         tmp &= ~(0xFF << 24);
9127         tmp |= (0x12 << 24);
9128         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
9129
9130         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
9131         tmp |= (1 << 11);
9132         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
9133
9134         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
9135         tmp |= (1 << 11);
9136         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
9137
9138         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
9139         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9140         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
9141
9142         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
9143         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9144         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
9145
9146         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
9147         tmp &= ~(7 << 13);
9148         tmp |= (5 << 13);
9149         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
9150
9151         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
9152         tmp &= ~(7 << 13);
9153         tmp |= (5 << 13);
9154         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
9155
9156         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
9157         tmp &= ~0xFF;
9158         tmp |= 0x1C;
9159         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
9160
9161         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
9162         tmp &= ~0xFF;
9163         tmp |= 0x1C;
9164         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
9165
9166         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
9167         tmp &= ~(0xFF << 16);
9168         tmp |= (0x1C << 16);
9169         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
9170
9171         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
9172         tmp &= ~(0xFF << 16);
9173         tmp |= (0x1C << 16);
9174         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
9175
9176         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
9177         tmp |= (1 << 27);
9178         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
9179
9180         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
9181         tmp |= (1 << 27);
9182         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
9183
9184         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
9185         tmp &= ~(0xF << 28);
9186         tmp |= (4 << 28);
9187         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
9188
9189         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
9190         tmp &= ~(0xF << 28);
9191         tmp |= (4 << 28);
9192         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
9193 }
9194
9195 /* Implements 3 different sequences from BSpec chapter "Display iCLK
9196  * Programming" based on the parameters passed:
9197  * - Sequence to enable CLKOUT_DP
9198  * - Sequence to enable CLKOUT_DP without spread
9199  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
9200  */
9201 static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
9202                                  bool with_spread, bool with_fdi)
9203 {
9204         uint32_t reg, tmp;
9205
9206         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
9207                 with_spread = true;
9208         if (WARN(HAS_PCH_LPT_LP(dev_priv) &&
9209             with_fdi, "LP PCH doesn't have FDI\n"))
9210                 with_fdi = false;
9211
9212         mutex_lock(&dev_priv->sb_lock);
9213
9214         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9215         tmp &= ~SBI_SSCCTL_DISABLE;
9216         tmp |= SBI_SSCCTL_PATHALT;
9217         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9218
9219         udelay(24);
9220
9221         if (with_spread) {
9222                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9223                 tmp &= ~SBI_SSCCTL_PATHALT;
9224                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9225
9226                 if (with_fdi) {
9227                         lpt_reset_fdi_mphy(dev_priv);
9228                         lpt_program_fdi_mphy(dev_priv);
9229                 }
9230         }
9231
9232         reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
9233         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9234         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9235         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9236
9237         mutex_unlock(&dev_priv->sb_lock);
9238 }
9239
9240 /* Sequence to disable CLKOUT_DP */
9241 static void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
9242 {
9243         uint32_t reg, tmp;
9244
9245         mutex_lock(&dev_priv->sb_lock);
9246
9247         reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
9248         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9249         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9250         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9251
9252         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9253         if (!(tmp & SBI_SSCCTL_DISABLE)) {
9254                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
9255                         tmp |= SBI_SSCCTL_PATHALT;
9256                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9257                         udelay(32);
9258                 }
9259                 tmp |= SBI_SSCCTL_DISABLE;
9260                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9261         }
9262
9263         mutex_unlock(&dev_priv->sb_lock);
9264 }
9265
9266 #define BEND_IDX(steps) ((50 + (steps)) / 5)
9267
9268 static const uint16_t sscdivintphase[] = {
9269         [BEND_IDX( 50)] = 0x3B23,
9270         [BEND_IDX( 45)] = 0x3B23,
9271         [BEND_IDX( 40)] = 0x3C23,
9272         [BEND_IDX( 35)] = 0x3C23,
9273         [BEND_IDX( 30)] = 0x3D23,
9274         [BEND_IDX( 25)] = 0x3D23,
9275         [BEND_IDX( 20)] = 0x3E23,
9276         [BEND_IDX( 15)] = 0x3E23,
9277         [BEND_IDX( 10)] = 0x3F23,
9278         [BEND_IDX(  5)] = 0x3F23,
9279         [BEND_IDX(  0)] = 0x0025,
9280         [BEND_IDX( -5)] = 0x0025,
9281         [BEND_IDX(-10)] = 0x0125,
9282         [BEND_IDX(-15)] = 0x0125,
9283         [BEND_IDX(-20)] = 0x0225,
9284         [BEND_IDX(-25)] = 0x0225,
9285         [BEND_IDX(-30)] = 0x0325,
9286         [BEND_IDX(-35)] = 0x0325,
9287         [BEND_IDX(-40)] = 0x0425,
9288         [BEND_IDX(-45)] = 0x0425,
9289         [BEND_IDX(-50)] = 0x0525,
9290 };
9291
9292 /*
9293  * Bend CLKOUT_DP
9294  * steps -50 to 50 inclusive, in steps of 5
9295  * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
9296  * change in clock period = -(steps / 10) * 5.787 ps
9297  */
9298 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
9299 {
9300         uint32_t tmp;
9301         int idx = BEND_IDX(steps);
9302
9303         if (WARN_ON(steps % 5 != 0))
9304                 return;
9305
9306         if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
9307                 return;
9308
9309         mutex_lock(&dev_priv->sb_lock);
9310
9311         if (steps % 10 != 0)
9312                 tmp = 0xAAAAAAAB;
9313         else
9314                 tmp = 0x00000000;
9315         intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
9316
9317         tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
9318         tmp &= 0xffff0000;
9319         tmp |= sscdivintphase[idx];
9320         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
9321
9322         mutex_unlock(&dev_priv->sb_lock);
9323 }
9324
9325 #undef BEND_IDX
9326
9327 static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
9328 {
9329         struct intel_encoder *encoder;
9330         bool has_vga = false;
9331
9332         for_each_intel_encoder(&dev_priv->drm, encoder) {
9333                 switch (encoder->type) {
9334                 case INTEL_OUTPUT_ANALOG:
9335                         has_vga = true;
9336                         break;
9337                 default:
9338                         break;
9339                 }
9340         }
9341
9342         if (has_vga) {
9343                 lpt_bend_clkout_dp(dev_priv, 0);
9344                 lpt_enable_clkout_dp(dev_priv, true, true);
9345         } else {
9346                 lpt_disable_clkout_dp(dev_priv);
9347         }
9348 }
9349
9350 /*
9351  * Initialize reference clocks when the driver loads
9352  */
9353 void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
9354 {
9355         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
9356                 ironlake_init_pch_refclk(dev_priv);
9357         else if (HAS_PCH_LPT(dev_priv))
9358                 lpt_init_pch_refclk(dev_priv);
9359 }
9360
9361 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
9362 {
9363         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
9364         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9365         int pipe = intel_crtc->pipe;
9366         uint32_t val;
9367
9368         val = 0;
9369
9370         switch (intel_crtc->config->pipe_bpp) {
9371         case 18:
9372                 val |= PIPECONF_6BPC;
9373                 break;
9374         case 24:
9375                 val |= PIPECONF_8BPC;
9376                 break;
9377         case 30:
9378                 val |= PIPECONF_10BPC;
9379                 break;
9380         case 36:
9381                 val |= PIPECONF_12BPC;
9382                 break;
9383         default:
9384                 /* Case prevented by intel_choose_pipe_bpp_dither. */
9385                 BUG();
9386         }
9387
9388         if (intel_crtc->config->dither)
9389                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
9390
9391         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
9392                 val |= PIPECONF_INTERLACED_ILK;
9393         else
9394                 val |= PIPECONF_PROGRESSIVE;
9395
9396         if (intel_crtc->config->limited_color_range)
9397                 val |= PIPECONF_COLOR_RANGE_SELECT;
9398
9399         I915_WRITE(PIPECONF(pipe), val);
9400         POSTING_READ(PIPECONF(pipe));
9401 }
9402
9403 static void haswell_set_pipeconf(struct drm_crtc *crtc)
9404 {
9405         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
9406         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9407         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
9408         u32 val = 0;
9409
9410         if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
9411                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
9412
9413         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
9414                 val |= PIPECONF_INTERLACED_ILK;
9415         else
9416                 val |= PIPECONF_PROGRESSIVE;
9417
9418         I915_WRITE(PIPECONF(cpu_transcoder), val);
9419         POSTING_READ(PIPECONF(cpu_transcoder));
9420 }
9421
9422 static void haswell_set_pipemisc(struct drm_crtc *crtc)
9423 {
9424         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
9425         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9426
9427         if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
9428                 u32 val = 0;
9429
9430                 switch (intel_crtc->config->pipe_bpp) {
9431                 case 18:
9432                         val |= PIPEMISC_DITHER_6_BPC;
9433                         break;
9434                 case 24:
9435                         val |= PIPEMISC_DITHER_8_BPC;
9436                         break;
9437                 case 30:
9438                         val |= PIPEMISC_DITHER_10_BPC;
9439                         break;
9440                 case 36:
9441                         val |= PIPEMISC_DITHER_12_BPC;
9442                         break;
9443                 default:
9444                         /* Case prevented by pipe_config_set_bpp. */
9445                         BUG();
9446                 }
9447
9448                 if (intel_crtc->config->dither)
9449                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
9450
9451                 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
9452         }
9453 }
9454
9455 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
9456 {
9457         /*
9458          * Account for spread spectrum to avoid
9459          * oversubscribing the link. Max center spread
9460          * is 2.5%; use 5% for safety's sake.
9461          */
9462         u32 bps = target_clock * bpp * 21 / 20;
9463         return DIV_ROUND_UP(bps, link_bw * 8);
9464 }
9465
9466 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
9467 {
9468         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
9469 }
9470
9471 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
9472                                   struct intel_crtc_state *crtc_state,
9473                                   struct dpll *reduced_clock)
9474 {
9475         struct drm_crtc *crtc = &intel_crtc->base;
9476         struct drm_device *dev = crtc->dev;
9477         struct drm_i915_private *dev_priv = to_i915(dev);
9478         u32 dpll, fp, fp2;
9479         int factor;
9480
9481         /* Enable autotuning of the PLL clock (if permissible) */
9482         factor = 21;
9483         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9484                 if ((intel_panel_use_ssc(dev_priv) &&
9485                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
9486                     (HAS_PCH_IBX(dev_priv) && intel_is_dual_link_lvds(dev)))
9487                         factor = 25;
9488         } else if (crtc_state->sdvo_tv_clock)
9489                 factor = 20;
9490
9491         fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
9492
9493         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
9494                 fp |= FP_CB_TUNE;
9495
9496         if (reduced_clock) {
9497                 fp2 = i9xx_dpll_compute_fp(reduced_clock);
9498
9499                 if (reduced_clock->m < factor * reduced_clock->n)
9500                         fp2 |= FP_CB_TUNE;
9501         } else {
9502                 fp2 = fp;
9503         }
9504
9505         dpll = 0;
9506
9507         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
9508                 dpll |= DPLLB_MODE_LVDS;
9509         else
9510                 dpll |= DPLLB_MODE_DAC_SERIAL;
9511
9512         dpll |= (crtc_state->pixel_multiplier - 1)
9513                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
9514
9515         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
9516             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
9517                 dpll |= DPLL_SDVO_HIGH_SPEED;
9518
9519         if (intel_crtc_has_dp_encoder(crtc_state))
9520                 dpll |= DPLL_SDVO_HIGH_SPEED;
9521
9522         /*
9523          * The high speed IO clock is only really required for
9524          * SDVO/HDMI/DP, but we also enable it for CRT to make it
9525          * possible to share the DPLL between CRT and HDMI. Enabling
9526          * the clock needlessly does no real harm, except use up a
9527          * bit of power potentially.
9528          *
9529          * We'll limit this to IVB with 3 pipes, since it has only two
9530          * DPLLs and so DPLL sharing is the only way to get three pipes
9531          * driving PCH ports at the same time. On SNB we could do this,
9532          * and potentially avoid enabling the second DPLL, but it's not
9533          * clear if it''s a win or loss power wise. No point in doing
9534          * this on ILK at all since it has a fixed DPLL<->pipe mapping.
9535          */
9536         if (INTEL_INFO(dev_priv)->num_pipes == 3 &&
9537             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
9538                 dpll |= DPLL_SDVO_HIGH_SPEED;
9539
9540         /* compute bitmask from p1 value */
9541         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
9542         /* also FPA1 */
9543         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
9544
9545         switch (crtc_state->dpll.p2) {
9546         case 5:
9547                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
9548                 break;
9549         case 7:
9550                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
9551                 break;
9552         case 10:
9553                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
9554                 break;
9555         case 14:
9556                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
9557                 break;
9558         }
9559
9560         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
9561             intel_panel_use_ssc(dev_priv))
9562                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
9563         else
9564                 dpll |= PLL_REF_INPUT_DREFCLK;
9565
9566         dpll |= DPLL_VCO_ENABLE;
9567
9568         crtc_state->dpll_hw_state.dpll = dpll;
9569         crtc_state->dpll_hw_state.fp0 = fp;
9570         crtc_state->dpll_hw_state.fp1 = fp2;
9571 }
9572
9573 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
9574                                        struct intel_crtc_state *crtc_state)
9575 {
9576         struct drm_device *dev = crtc->base.dev;
9577         struct drm_i915_private *dev_priv = to_i915(dev);
9578         struct dpll reduced_clock;
9579         bool has_reduced_clock = false;
9580         struct intel_shared_dpll *pll;
9581         const struct intel_limit *limit;
9582         int refclk = 120000;
9583
9584         memset(&crtc_state->dpll_hw_state, 0,
9585                sizeof(crtc_state->dpll_hw_state));
9586
9587         crtc->lowfreq_avail = false;
9588
9589         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
9590         if (!crtc_state->has_pch_encoder)
9591                 return 0;
9592
9593         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9594                 if (intel_panel_use_ssc(dev_priv)) {
9595                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
9596                                       dev_priv->vbt.lvds_ssc_freq);
9597                         refclk = dev_priv->vbt.lvds_ssc_freq;
9598                 }
9599
9600                 if (intel_is_dual_link_lvds(dev)) {
9601                         if (refclk == 100000)
9602                                 limit = &intel_limits_ironlake_dual_lvds_100m;
9603                         else
9604                                 limit = &intel_limits_ironlake_dual_lvds;
9605                 } else {
9606                         if (refclk == 100000)
9607                                 limit = &intel_limits_ironlake_single_lvds_100m;
9608                         else
9609                                 limit = &intel_limits_ironlake_single_lvds;
9610                 }
9611         } else {
9612                 limit = &intel_limits_ironlake_dac;
9613         }
9614
9615         if (!crtc_state->clock_set &&
9616             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9617                                 refclk, NULL, &crtc_state->dpll)) {
9618                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
9619                 return -EINVAL;
9620         }
9621
9622         ironlake_compute_dpll(crtc, crtc_state,
9623                               has_reduced_clock ? &reduced_clock : NULL);
9624
9625         pll = intel_get_shared_dpll(crtc, crtc_state, NULL);
9626         if (pll == NULL) {
9627                 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
9628                                  pipe_name(crtc->pipe));
9629                 return -EINVAL;
9630         }
9631
9632         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
9633             has_reduced_clock)
9634                 crtc->lowfreq_avail = true;
9635
9636         return 0;
9637 }
9638
9639 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
9640                                          struct intel_link_m_n *m_n)
9641 {
9642         struct drm_device *dev = crtc->base.dev;
9643         struct drm_i915_private *dev_priv = to_i915(dev);
9644         enum pipe pipe = crtc->pipe;
9645
9646         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
9647         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
9648         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
9649                 & ~TU_SIZE_MASK;
9650         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
9651         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
9652                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9653 }
9654
9655 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
9656                                          enum transcoder transcoder,
9657                                          struct intel_link_m_n *m_n,
9658                                          struct intel_link_m_n *m2_n2)
9659 {
9660         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9661         enum pipe pipe = crtc->pipe;
9662
9663         if (INTEL_GEN(dev_priv) >= 5) {
9664                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
9665                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
9666                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
9667                         & ~TU_SIZE_MASK;
9668                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9669                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9670                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9671                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
9672                  * gen < 8) and if DRRS is supported (to make sure the
9673                  * registers are not unnecessarily read).
9674                  */
9675                 if (m2_n2 && INTEL_GEN(dev_priv) < 8 &&
9676                         crtc->config->has_drrs) {
9677                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9678                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9679                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9680                                         & ~TU_SIZE_MASK;
9681                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9682                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9683                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9684                 }
9685         } else {
9686                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9687                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9688                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9689                         & ~TU_SIZE_MASK;
9690                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9691                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9692                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9693         }
9694 }
9695
9696 void intel_dp_get_m_n(struct intel_crtc *crtc,
9697                       struct intel_crtc_state *pipe_config)
9698 {
9699         if (pipe_config->has_pch_encoder)
9700                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9701         else
9702                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9703                                              &pipe_config->dp_m_n,
9704                                              &pipe_config->dp_m2_n2);
9705 }
9706
9707 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9708                                         struct intel_crtc_state *pipe_config)
9709 {
9710         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9711                                      &pipe_config->fdi_m_n, NULL);
9712 }
9713
9714 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9715                                     struct intel_crtc_state *pipe_config)
9716 {
9717         struct drm_device *dev = crtc->base.dev;
9718         struct drm_i915_private *dev_priv = to_i915(dev);
9719         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9720         uint32_t ps_ctrl = 0;
9721         int id = -1;
9722         int i;
9723
9724         /* find scaler attached to this pipe */
9725         for (i = 0; i < crtc->num_scalers; i++) {
9726                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9727                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9728                         id = i;
9729                         pipe_config->pch_pfit.enabled = true;
9730                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9731                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9732                         break;
9733                 }
9734         }
9735
9736         scaler_state->scaler_id = id;
9737         if (id >= 0) {
9738                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9739         } else {
9740                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9741         }
9742 }
9743
9744 static void
9745 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9746                                  struct intel_initial_plane_config *plane_config)
9747 {
9748         struct drm_device *dev = crtc->base.dev;
9749         struct drm_i915_private *dev_priv = to_i915(dev);
9750         u32 val, base, offset, stride_mult, tiling;
9751         int pipe = crtc->pipe;
9752         int fourcc, pixel_format;
9753         unsigned int aligned_height;
9754         struct drm_framebuffer *fb;
9755         struct intel_framebuffer *intel_fb;
9756
9757         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9758         if (!intel_fb) {
9759                 DRM_DEBUG_KMS("failed to alloc fb\n");
9760                 return;
9761         }
9762
9763         fb = &intel_fb->base;
9764
9765         fb->dev = dev;
9766
9767         val = I915_READ(PLANE_CTL(pipe, 0));
9768         if (!(val & PLANE_CTL_ENABLE))
9769                 goto error;
9770
9771         pixel_format = val & PLANE_CTL_FORMAT_MASK;
9772         fourcc = skl_format_to_fourcc(pixel_format,
9773                                       val & PLANE_CTL_ORDER_RGBX,
9774                                       val & PLANE_CTL_ALPHA_MASK);
9775         fb->format = drm_format_info(fourcc);
9776
9777         tiling = val & PLANE_CTL_TILED_MASK;
9778         switch (tiling) {
9779         case PLANE_CTL_TILED_LINEAR:
9780                 fb->modifier = DRM_FORMAT_MOD_NONE;
9781                 break;
9782         case PLANE_CTL_TILED_X:
9783                 plane_config->tiling = I915_TILING_X;
9784                 fb->modifier = I915_FORMAT_MOD_X_TILED;
9785                 break;
9786         case PLANE_CTL_TILED_Y:
9787                 fb->modifier = I915_FORMAT_MOD_Y_TILED;
9788                 break;
9789         case PLANE_CTL_TILED_YF:
9790                 fb->modifier = I915_FORMAT_MOD_Yf_TILED;
9791                 break;
9792         default:
9793                 MISSING_CASE(tiling);
9794                 goto error;
9795         }
9796
9797         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9798         plane_config->base = base;
9799
9800         offset = I915_READ(PLANE_OFFSET(pipe, 0));
9801
9802         val = I915_READ(PLANE_SIZE(pipe, 0));
9803         fb->height = ((val >> 16) & 0xfff) + 1;
9804         fb->width = ((val >> 0) & 0x1fff) + 1;
9805
9806         val = I915_READ(PLANE_STRIDE(pipe, 0));
9807         stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier,
9808                                                 fb->format->format);
9809         fb->pitches[0] = (val & 0x3ff) * stride_mult;
9810
9811         aligned_height = intel_fb_align_height(dev, fb->height,
9812                                                fb->format->format,
9813                                                fb->modifier);
9814
9815         plane_config->size = fb->pitches[0] * aligned_height;
9816
9817         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9818                       pipe_name(pipe), fb->width, fb->height,
9819                       fb->format->cpp[0] * 8, base, fb->pitches[0],
9820                       plane_config->size);
9821
9822         plane_config->fb = intel_fb;
9823         return;
9824
9825 error:
9826         kfree(intel_fb);
9827 }
9828
9829 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9830                                      struct intel_crtc_state *pipe_config)
9831 {
9832         struct drm_device *dev = crtc->base.dev;
9833         struct drm_i915_private *dev_priv = to_i915(dev);
9834         uint32_t tmp;
9835
9836         tmp = I915_READ(PF_CTL(crtc->pipe));
9837
9838         if (tmp & PF_ENABLE) {
9839                 pipe_config->pch_pfit.enabled = true;
9840                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9841                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9842
9843                 /* We currently do not free assignements of panel fitters on
9844                  * ivb/hsw (since we don't use the higher upscaling modes which
9845                  * differentiates them) so just WARN about this case for now. */
9846                 if (IS_GEN7(dev_priv)) {
9847                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9848                                 PF_PIPE_SEL_IVB(crtc->pipe));
9849                 }
9850         }
9851 }
9852
9853 static void
9854 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9855                                   struct intel_initial_plane_config *plane_config)
9856 {
9857         struct drm_device *dev = crtc->base.dev;
9858         struct drm_i915_private *dev_priv = to_i915(dev);
9859         u32 val, base, offset;
9860         int pipe = crtc->pipe;
9861         int fourcc, pixel_format;
9862         unsigned int aligned_height;
9863         struct drm_framebuffer *fb;
9864         struct intel_framebuffer *intel_fb;
9865
9866         val = I915_READ(DSPCNTR(pipe));
9867         if (!(val & DISPLAY_PLANE_ENABLE))
9868                 return;
9869
9870         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9871         if (!intel_fb) {
9872                 DRM_DEBUG_KMS("failed to alloc fb\n");
9873                 return;
9874         }
9875
9876         fb = &intel_fb->base;
9877
9878         fb->dev = dev;
9879
9880         if (INTEL_GEN(dev_priv) >= 4) {
9881                 if (val & DISPPLANE_TILED) {
9882                         plane_config->tiling = I915_TILING_X;
9883                         fb->modifier = I915_FORMAT_MOD_X_TILED;
9884                 }
9885         }
9886
9887         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9888         fourcc = i9xx_format_to_fourcc(pixel_format);
9889         fb->format = drm_format_info(fourcc);
9890
9891         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9892         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
9893                 offset = I915_READ(DSPOFFSET(pipe));
9894         } else {
9895                 if (plane_config->tiling)
9896                         offset = I915_READ(DSPTILEOFF(pipe));
9897                 else
9898                         offset = I915_READ(DSPLINOFF(pipe));
9899         }
9900         plane_config->base = base;
9901
9902         val = I915_READ(PIPESRC(pipe));
9903         fb->width = ((val >> 16) & 0xfff) + 1;
9904         fb->height = ((val >> 0) & 0xfff) + 1;
9905
9906         val = I915_READ(DSPSTRIDE(pipe));
9907         fb->pitches[0] = val & 0xffffffc0;
9908
9909         aligned_height = intel_fb_align_height(dev, fb->height,
9910                                                fb->format->format,
9911                                                fb->modifier);
9912
9913         plane_config->size = fb->pitches[0] * aligned_height;
9914
9915         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9916                       pipe_name(pipe), fb->width, fb->height,
9917                       fb->format->cpp[0] * 8, base, fb->pitches[0],
9918                       plane_config->size);
9919
9920         plane_config->fb = intel_fb;
9921 }
9922
9923 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9924                                      struct intel_crtc_state *pipe_config)
9925 {
9926         struct drm_device *dev = crtc->base.dev;
9927         struct drm_i915_private *dev_priv = to_i915(dev);
9928         enum intel_display_power_domain power_domain;
9929         uint32_t tmp;
9930         bool ret;
9931
9932         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9933         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9934                 return false;
9935
9936         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9937         pipe_config->shared_dpll = NULL;
9938
9939         ret = false;
9940         tmp = I915_READ(PIPECONF(crtc->pipe));
9941         if (!(tmp & PIPECONF_ENABLE))
9942                 goto out;
9943
9944         switch (tmp & PIPECONF_BPC_MASK) {
9945         case PIPECONF_6BPC:
9946                 pipe_config->pipe_bpp = 18;
9947                 break;
9948         case PIPECONF_8BPC:
9949                 pipe_config->pipe_bpp = 24;
9950                 break;
9951         case PIPECONF_10BPC:
9952                 pipe_config->pipe_bpp = 30;
9953                 break;
9954         case PIPECONF_12BPC:
9955                 pipe_config->pipe_bpp = 36;
9956                 break;
9957         default:
9958                 break;
9959         }
9960
9961         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9962                 pipe_config->limited_color_range = true;
9963
9964         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9965                 struct intel_shared_dpll *pll;
9966                 enum intel_dpll_id pll_id;
9967
9968                 pipe_config->has_pch_encoder = true;
9969
9970                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9971                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9972                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9973
9974                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9975
9976                 if (HAS_PCH_IBX(dev_priv)) {
9977                         /*
9978                          * The pipe->pch transcoder and pch transcoder->pll
9979                          * mapping is fixed.
9980                          */
9981                         pll_id = (enum intel_dpll_id) crtc->pipe;
9982                 } else {
9983                         tmp = I915_READ(PCH_DPLL_SEL);
9984                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9985                                 pll_id = DPLL_ID_PCH_PLL_B;
9986                         else
9987                                 pll_id= DPLL_ID_PCH_PLL_A;
9988                 }
9989
9990                 pipe_config->shared_dpll =
9991                         intel_get_shared_dpll_by_id(dev_priv, pll_id);
9992                 pll = pipe_config->shared_dpll;
9993
9994                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9995                                                  &pipe_config->dpll_hw_state));
9996
9997                 tmp = pipe_config->dpll_hw_state.dpll;
9998                 pipe_config->pixel_multiplier =
9999                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
10000                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
10001
10002                 ironlake_pch_clock_get(crtc, pipe_config);
10003         } else {
10004                 pipe_config->pixel_multiplier = 1;
10005         }
10006
10007         intel_get_pipe_timings(crtc, pipe_config);
10008         intel_get_pipe_src_size(crtc, pipe_config);
10009
10010         ironlake_get_pfit_config(crtc, pipe_config);
10011
10012         ret = true;
10013
10014 out:
10015         intel_display_power_put(dev_priv, power_domain);
10016
10017         return ret;
10018 }
10019
10020 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
10021 {
10022         struct drm_device *dev = &dev_priv->drm;
10023         struct intel_crtc *crtc;
10024
10025         for_each_intel_crtc(dev, crtc)
10026                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
10027                      pipe_name(crtc->pipe));
10028
10029         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
10030         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
10031         I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
10032         I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
10033         I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n");
10034         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
10035              "CPU PWM1 enabled\n");
10036         if (IS_HASWELL(dev_priv))
10037                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
10038                      "CPU PWM2 enabled\n");
10039         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
10040              "PCH PWM1 enabled\n");
10041         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
10042              "Utility pin enabled\n");
10043         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
10044
10045         /*
10046          * In theory we can still leave IRQs enabled, as long as only the HPD
10047          * interrupts remain enabled. We used to check for that, but since it's
10048          * gen-specific and since we only disable LCPLL after we fully disable
10049          * the interrupts, the check below should be enough.
10050          */
10051         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
10052 }
10053
10054 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
10055 {
10056         if (IS_HASWELL(dev_priv))
10057                 return I915_READ(D_COMP_HSW);
10058         else
10059                 return I915_READ(D_COMP_BDW);
10060 }
10061
10062 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
10063 {
10064         if (IS_HASWELL(dev_priv)) {
10065                 mutex_lock(&dev_priv->rps.hw_lock);
10066                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
10067                                             val))
10068                         DRM_DEBUG_KMS("Failed to write to D_COMP\n");
10069                 mutex_unlock(&dev_priv->rps.hw_lock);
10070         } else {
10071                 I915_WRITE(D_COMP_BDW, val);
10072                 POSTING_READ(D_COMP_BDW);
10073         }
10074 }
10075
10076 /*
10077  * This function implements pieces of two sequences from BSpec:
10078  * - Sequence for display software to disable LCPLL
10079  * - Sequence for display software to allow package C8+
10080  * The steps implemented here are just the steps that actually touch the LCPLL
10081  * register. Callers should take care of disabling all the display engine
10082  * functions, doing the mode unset, fixing interrupts, etc.
10083  */
10084 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
10085                               bool switch_to_fclk, bool allow_power_down)
10086 {
10087         uint32_t val;
10088
10089         assert_can_disable_lcpll(dev_priv);
10090
10091         val = I915_READ(LCPLL_CTL);
10092
10093         if (switch_to_fclk) {
10094                 val |= LCPLL_CD_SOURCE_FCLK;
10095                 I915_WRITE(LCPLL_CTL, val);
10096
10097                 if (wait_for_us(I915_READ(LCPLL_CTL) &
10098                                 LCPLL_CD_SOURCE_FCLK_DONE, 1))
10099                         DRM_ERROR("Switching to FCLK failed\n");
10100
10101                 val = I915_READ(LCPLL_CTL);
10102         }
10103
10104         val |= LCPLL_PLL_DISABLE;
10105         I915_WRITE(LCPLL_CTL, val);
10106         POSTING_READ(LCPLL_CTL);
10107
10108         if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
10109                 DRM_ERROR("LCPLL still locked\n");
10110
10111         val = hsw_read_dcomp(dev_priv);
10112         val |= D_COMP_COMP_DISABLE;
10113         hsw_write_dcomp(dev_priv, val);
10114         ndelay(100);
10115
10116         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
10117                      1))
10118                 DRM_ERROR("D_COMP RCOMP still in progress\n");
10119
10120         if (allow_power_down) {
10121                 val = I915_READ(LCPLL_CTL);
10122                 val |= LCPLL_POWER_DOWN_ALLOW;
10123                 I915_WRITE(LCPLL_CTL, val);
10124                 POSTING_READ(LCPLL_CTL);
10125         }
10126 }
10127
10128 /*
10129  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
10130  * source.
10131  */
10132 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
10133 {
10134         uint32_t val;
10135
10136         val = I915_READ(LCPLL_CTL);
10137
10138         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
10139                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
10140                 return;
10141
10142         /*
10143          * Make sure we're not on PC8 state before disabling PC8, otherwise
10144          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
10145          */
10146         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
10147
10148         if (val & LCPLL_POWER_DOWN_ALLOW) {
10149                 val &= ~LCPLL_POWER_DOWN_ALLOW;
10150                 I915_WRITE(LCPLL_CTL, val);
10151                 POSTING_READ(LCPLL_CTL);
10152         }
10153
10154         val = hsw_read_dcomp(dev_priv);
10155         val |= D_COMP_COMP_FORCE;
10156         val &= ~D_COMP_COMP_DISABLE;
10157         hsw_write_dcomp(dev_priv, val);
10158
10159         val = I915_READ(LCPLL_CTL);
10160         val &= ~LCPLL_PLL_DISABLE;
10161         I915_WRITE(LCPLL_CTL, val);
10162
10163         if (intel_wait_for_register(dev_priv,
10164                                     LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
10165                                     5))
10166                 DRM_ERROR("LCPLL not locked yet\n");
10167
10168         if (val & LCPLL_CD_SOURCE_FCLK) {
10169                 val = I915_READ(LCPLL_CTL);
10170                 val &= ~LCPLL_CD_SOURCE_FCLK;
10171                 I915_WRITE(LCPLL_CTL, val);
10172
10173                 if (wait_for_us((I915_READ(LCPLL_CTL) &
10174                                  LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
10175                         DRM_ERROR("Switching back to LCPLL failed\n");
10176         }
10177
10178         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
10179         intel_update_cdclk(dev_priv);
10180 }
10181
10182 /*
10183  * Package states C8 and deeper are really deep PC states that can only be
10184  * reached when all the devices on the system allow it, so even if the graphics
10185  * device allows PC8+, it doesn't mean the system will actually get to these
10186  * states. Our driver only allows PC8+ when going into runtime PM.
10187  *
10188  * The requirements for PC8+ are that all the outputs are disabled, the power
10189  * well is disabled and most interrupts are disabled, and these are also
10190  * requirements for runtime PM. When these conditions are met, we manually do
10191  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
10192  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
10193  * hang the machine.
10194  *
10195  * When we really reach PC8 or deeper states (not just when we allow it) we lose
10196  * the state of some registers, so when we come back from PC8+ we need to
10197  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
10198  * need to take care of the registers kept by RC6. Notice that this happens even
10199  * if we don't put the device in PCI D3 state (which is what currently happens
10200  * because of the runtime PM support).
10201  *
10202  * For more, read "Display Sequences for Package C8" on the hardware
10203  * documentation.
10204  */
10205 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
10206 {
10207         uint32_t val;
10208
10209         DRM_DEBUG_KMS("Enabling package C8+\n");
10210
10211         if (HAS_PCH_LPT_LP(dev_priv)) {
10212                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
10213                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
10214                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
10215         }
10216
10217         lpt_disable_clkout_dp(dev_priv);
10218         hsw_disable_lcpll(dev_priv, true, true);
10219 }
10220
10221 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
10222 {
10223         uint32_t val;
10224
10225         DRM_DEBUG_KMS("Disabling package C8+\n");
10226
10227         hsw_restore_lcpll(dev_priv);
10228         lpt_init_pch_refclk(dev_priv);
10229
10230         if (HAS_PCH_LPT_LP(dev_priv)) {
10231                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
10232                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
10233                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
10234         }
10235 }
10236
10237 static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state)
10238 {
10239         struct drm_device *dev = old_state->dev;
10240         struct intel_atomic_state *old_intel_state =
10241                 to_intel_atomic_state(old_state);
10242         unsigned int req_cdclk = old_intel_state->dev_cdclk;
10243
10244         bxt_set_cdclk(to_i915(dev), req_cdclk);
10245 }
10246
10247 static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state,
10248                                           int pixel_rate)
10249 {
10250         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
10251
10252         /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
10253         if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
10254                 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
10255
10256         /* BSpec says "Do not use DisplayPort with CDCLK less than
10257          * 432 MHz, audio enabled, port width x4, and link rate
10258          * HBR2 (5.4 GHz), or else there may be audio corruption or
10259          * screen corruption."
10260          */
10261         if (intel_crtc_has_dp_encoder(crtc_state) &&
10262             crtc_state->has_audio &&
10263             crtc_state->port_clock >= 540000 &&
10264             crtc_state->lane_count == 4)
10265                 pixel_rate = max(432000, pixel_rate);
10266
10267         return pixel_rate;
10268 }
10269
10270 /* compute the max rate for new configuration */
10271 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
10272 {
10273         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
10274         struct drm_i915_private *dev_priv = to_i915(state->dev);
10275         struct drm_crtc *crtc;
10276         struct drm_crtc_state *cstate;
10277         struct intel_crtc_state *crtc_state;
10278         unsigned max_pixel_rate = 0, i;
10279         enum pipe pipe;
10280
10281         memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
10282                sizeof(intel_state->min_pixclk));
10283
10284         for_each_crtc_in_state(state, crtc, cstate, i) {
10285                 int pixel_rate;
10286
10287                 crtc_state = to_intel_crtc_state(cstate);
10288                 if (!crtc_state->base.enable) {
10289                         intel_state->min_pixclk[i] = 0;
10290                         continue;
10291                 }
10292
10293                 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
10294
10295                 if (IS_BROADWELL(dev_priv) || IS_GEN9(dev_priv))
10296                         pixel_rate = bdw_adjust_min_pipe_pixel_rate(crtc_state,
10297                                                                     pixel_rate);
10298
10299                 intel_state->min_pixclk[i] = pixel_rate;
10300         }
10301
10302         for_each_pipe(dev_priv, pipe)
10303                 max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate);
10304
10305         return max_pixel_rate;
10306 }
10307
10308 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
10309 {
10310         struct drm_i915_private *dev_priv = to_i915(dev);
10311         uint32_t val, data;
10312         int ret;
10313
10314         if (WARN((I915_READ(LCPLL_CTL) &
10315                   (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
10316                    LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
10317                    LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
10318                    LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
10319                  "trying to change cdclk frequency with cdclk not enabled\n"))
10320                 return;
10321
10322         mutex_lock(&dev_priv->rps.hw_lock);
10323         ret = sandybridge_pcode_write(dev_priv,
10324                                       BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
10325         mutex_unlock(&dev_priv->rps.hw_lock);
10326         if (ret) {
10327                 DRM_ERROR("failed to inform pcode about cdclk change\n");
10328                 return;
10329         }
10330
10331         val = I915_READ(LCPLL_CTL);
10332         val |= LCPLL_CD_SOURCE_FCLK;
10333         I915_WRITE(LCPLL_CTL, val);
10334
10335         if (wait_for_us(I915_READ(LCPLL_CTL) &
10336                         LCPLL_CD_SOURCE_FCLK_DONE, 1))
10337                 DRM_ERROR("Switching to FCLK failed\n");
10338
10339         val = I915_READ(LCPLL_CTL);
10340         val &= ~LCPLL_CLK_FREQ_MASK;
10341
10342         switch (cdclk) {
10343         case 450000:
10344                 val |= LCPLL_CLK_FREQ_450;
10345                 data = 0;
10346                 break;
10347         case 540000:
10348                 val |= LCPLL_CLK_FREQ_54O_BDW;
10349                 data = 1;
10350                 break;
10351         case 337500:
10352                 val |= LCPLL_CLK_FREQ_337_5_BDW;
10353                 data = 2;
10354                 break;
10355         case 675000:
10356                 val |= LCPLL_CLK_FREQ_675_BDW;
10357                 data = 3;
10358                 break;
10359         default:
10360                 WARN(1, "invalid cdclk frequency\n");
10361                 return;
10362         }
10363
10364         I915_WRITE(LCPLL_CTL, val);
10365
10366         val = I915_READ(LCPLL_CTL);
10367         val &= ~LCPLL_CD_SOURCE_FCLK;
10368         I915_WRITE(LCPLL_CTL, val);
10369
10370         if (wait_for_us((I915_READ(LCPLL_CTL) &
10371                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
10372                 DRM_ERROR("Switching back to LCPLL failed\n");
10373
10374         mutex_lock(&dev_priv->rps.hw_lock);
10375         sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
10376         mutex_unlock(&dev_priv->rps.hw_lock);
10377
10378         I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
10379
10380         intel_update_cdclk(dev_priv);
10381
10382         WARN(cdclk != dev_priv->cdclk_freq,
10383              "cdclk requested %d kHz but got %d kHz\n",
10384              cdclk, dev_priv->cdclk_freq);
10385 }
10386
10387 static int broadwell_calc_cdclk(int max_pixclk)
10388 {
10389         if (max_pixclk > 540000)
10390                 return 675000;
10391         else if (max_pixclk > 450000)
10392                 return 540000;
10393         else if (max_pixclk > 337500)
10394                 return 450000;
10395         else
10396                 return 337500;
10397 }
10398
10399 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
10400 {
10401         struct drm_i915_private *dev_priv = to_i915(state->dev);
10402         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
10403         int max_pixclk = ilk_max_pixel_rate(state);
10404         int cdclk;
10405
10406         /*
10407          * FIXME should also account for plane ratio
10408          * once 64bpp pixel formats are supported.
10409          */
10410         cdclk = broadwell_calc_cdclk(max_pixclk);
10411
10412         if (cdclk > dev_priv->max_cdclk_freq) {
10413                 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
10414                               cdclk, dev_priv->max_cdclk_freq);
10415                 return -EINVAL;
10416         }
10417
10418         intel_state->cdclk = intel_state->dev_cdclk = cdclk;
10419         if (!intel_state->active_crtcs)
10420                 intel_state->dev_cdclk = broadwell_calc_cdclk(0);
10421
10422         return 0;
10423 }
10424
10425 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
10426 {
10427         struct drm_device *dev = old_state->dev;
10428         struct intel_atomic_state *old_intel_state =
10429                 to_intel_atomic_state(old_state);
10430         unsigned req_cdclk = old_intel_state->dev_cdclk;
10431
10432         broadwell_set_cdclk(dev, req_cdclk);
10433 }
10434
10435 static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
10436 {
10437         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
10438         struct drm_i915_private *dev_priv = to_i915(state->dev);
10439         const int max_pixclk = ilk_max_pixel_rate(state);
10440         int vco = intel_state->cdclk_pll_vco;
10441         int cdclk;
10442
10443         /*
10444          * FIXME should also account for plane ratio
10445          * once 64bpp pixel formats are supported.
10446          */
10447         cdclk = skl_calc_cdclk(max_pixclk, vco);
10448
10449         /*
10450          * FIXME move the cdclk caclulation to
10451          * compute_config() so we can fail gracegully.
10452          */
10453         if (cdclk > dev_priv->max_cdclk_freq) {
10454                 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
10455                           cdclk, dev_priv->max_cdclk_freq);
10456                 cdclk = dev_priv->max_cdclk_freq;
10457         }
10458
10459         intel_state->cdclk = intel_state->dev_cdclk = cdclk;
10460         if (!intel_state->active_crtcs)
10461                 intel_state->dev_cdclk = skl_calc_cdclk(0, vco);
10462
10463         return 0;
10464 }
10465
10466 static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state)
10467 {
10468         struct drm_i915_private *dev_priv = to_i915(old_state->dev);
10469         struct intel_atomic_state *intel_state = to_intel_atomic_state(old_state);
10470         unsigned int req_cdclk = intel_state->dev_cdclk;
10471         unsigned int req_vco = intel_state->cdclk_pll_vco;
10472
10473         skl_set_cdclk(dev_priv, req_cdclk, req_vco);
10474 }
10475
10476 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
10477                                       struct intel_crtc_state *crtc_state)
10478 {
10479         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
10480                 if (!intel_ddi_pll_select(crtc, crtc_state))
10481                         return -EINVAL;
10482         }
10483
10484         crtc->lowfreq_avail = false;
10485
10486         return 0;
10487 }
10488
10489 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
10490                                 enum port port,
10491                                 struct intel_crtc_state *pipe_config)
10492 {
10493         enum intel_dpll_id id;
10494
10495         switch (port) {
10496         case PORT_A:
10497                 id = DPLL_ID_SKL_DPLL0;
10498                 break;
10499         case PORT_B:
10500                 id = DPLL_ID_SKL_DPLL1;
10501                 break;
10502         case PORT_C:
10503                 id = DPLL_ID_SKL_DPLL2;
10504                 break;
10505         default:
10506                 DRM_ERROR("Incorrect port type\n");
10507                 return;
10508         }
10509
10510         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10511 }
10512
10513 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
10514                                 enum port port,
10515                                 struct intel_crtc_state *pipe_config)
10516 {
10517         enum intel_dpll_id id;
10518         u32 temp;
10519
10520         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
10521         id = temp >> (port * 3 + 1);
10522
10523         if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3))
10524                 return;
10525
10526         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10527 }
10528
10529 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
10530                                 enum port port,
10531                                 struct intel_crtc_state *pipe_config)
10532 {
10533         enum intel_dpll_id id;
10534         uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
10535
10536         switch (ddi_pll_sel) {
10537         case PORT_CLK_SEL_WRPLL1:
10538                 id = DPLL_ID_WRPLL1;
10539                 break;
10540         case PORT_CLK_SEL_WRPLL2:
10541                 id = DPLL_ID_WRPLL2;
10542                 break;
10543         case PORT_CLK_SEL_SPLL:
10544                 id = DPLL_ID_SPLL;
10545                 break;
10546         case PORT_CLK_SEL_LCPLL_810:
10547                 id = DPLL_ID_LCPLL_810;
10548                 break;
10549         case PORT_CLK_SEL_LCPLL_1350:
10550                 id = DPLL_ID_LCPLL_1350;
10551                 break;
10552         case PORT_CLK_SEL_LCPLL_2700:
10553                 id = DPLL_ID_LCPLL_2700;
10554                 break;
10555         default:
10556                 MISSING_CASE(ddi_pll_sel);
10557                 /* fall through */
10558         case PORT_CLK_SEL_NONE:
10559                 return;
10560         }
10561
10562         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10563 }
10564
10565 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
10566                                      struct intel_crtc_state *pipe_config,
10567                                      unsigned long *power_domain_mask)
10568 {
10569         struct drm_device *dev = crtc->base.dev;
10570         struct drm_i915_private *dev_priv = to_i915(dev);
10571         enum intel_display_power_domain power_domain;
10572         u32 tmp;
10573
10574         /*
10575          * The pipe->transcoder mapping is fixed with the exception of the eDP
10576          * transcoder handled below.
10577          */
10578         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
10579
10580         /*
10581          * XXX: Do intel_display_power_get_if_enabled before reading this (for
10582          * consistency and less surprising code; it's in always on power).
10583          */
10584         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
10585         if (tmp & TRANS_DDI_FUNC_ENABLE) {
10586                 enum pipe trans_edp_pipe;
10587                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
10588                 default:
10589                         WARN(1, "unknown pipe linked to edp transcoder\n");
10590                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
10591                 case TRANS_DDI_EDP_INPUT_A_ON:
10592                         trans_edp_pipe = PIPE_A;
10593                         break;
10594                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
10595                         trans_edp_pipe = PIPE_B;
10596                         break;
10597                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
10598                         trans_edp_pipe = PIPE_C;
10599                         break;
10600                 }
10601
10602                 if (trans_edp_pipe == crtc->pipe)
10603                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
10604         }
10605
10606         power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
10607         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10608                 return false;
10609         *power_domain_mask |= BIT(power_domain);
10610
10611         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
10612
10613         return tmp & PIPECONF_ENABLE;
10614 }
10615
10616 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
10617                                          struct intel_crtc_state *pipe_config,
10618                                          unsigned long *power_domain_mask)
10619 {
10620         struct drm_device *dev = crtc->base.dev;
10621         struct drm_i915_private *dev_priv = to_i915(dev);
10622         enum intel_display_power_domain power_domain;
10623         enum port port;
10624         enum transcoder cpu_transcoder;
10625         u32 tmp;
10626
10627         for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
10628                 if (port == PORT_A)
10629                         cpu_transcoder = TRANSCODER_DSI_A;
10630                 else
10631                         cpu_transcoder = TRANSCODER_DSI_C;
10632
10633                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
10634                 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10635                         continue;
10636                 *power_domain_mask |= BIT(power_domain);
10637
10638                 /*
10639                  * The PLL needs to be enabled with a valid divider
10640                  * configuration, otherwise accessing DSI registers will hang
10641                  * the machine. See BSpec North Display Engine
10642                  * registers/MIPI[BXT]. We can break out here early, since we
10643                  * need the same DSI PLL to be enabled for both DSI ports.
10644                  */
10645                 if (!intel_dsi_pll_is_enabled(dev_priv))
10646                         break;
10647
10648                 /* XXX: this works for video mode only */
10649                 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
10650                 if (!(tmp & DPI_ENABLE))
10651                         continue;
10652
10653                 tmp = I915_READ(MIPI_CTRL(port));
10654                 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
10655                         continue;
10656
10657                 pipe_config->cpu_transcoder = cpu_transcoder;
10658                 break;
10659         }
10660
10661         return transcoder_is_dsi(pipe_config->cpu_transcoder);
10662 }
10663
10664 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
10665                                        struct intel_crtc_state *pipe_config)
10666 {
10667         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10668         struct intel_shared_dpll *pll;
10669         enum port port;
10670         uint32_t tmp;
10671
10672         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
10673
10674         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
10675
10676         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
10677                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
10678         else if (IS_GEN9_LP(dev_priv))
10679                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
10680         else
10681                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
10682
10683         pll = pipe_config->shared_dpll;
10684         if (pll) {
10685                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
10686                                                  &pipe_config->dpll_hw_state));
10687         }
10688
10689         /*
10690          * Haswell has only FDI/PCH transcoder A. It is which is connected to
10691          * DDI E. So just check whether this pipe is wired to DDI E and whether
10692          * the PCH transcoder is on.
10693          */
10694         if (INTEL_GEN(dev_priv) < 9 &&
10695             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
10696                 pipe_config->has_pch_encoder = true;
10697
10698                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
10699                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
10700                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
10701
10702                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
10703         }
10704 }
10705
10706 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
10707                                     struct intel_crtc_state *pipe_config)
10708 {
10709         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10710         enum intel_display_power_domain power_domain;
10711         unsigned long power_domain_mask;
10712         bool active;
10713
10714         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
10715         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10716                 return false;
10717         power_domain_mask = BIT(power_domain);
10718
10719         pipe_config->shared_dpll = NULL;
10720
10721         active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
10722
10723         if (IS_GEN9_LP(dev_priv) &&
10724             bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) {
10725                 WARN_ON(active);
10726                 active = true;
10727         }
10728
10729         if (!active)
10730                 goto out;
10731
10732         if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10733                 haswell_get_ddi_port_state(crtc, pipe_config);
10734                 intel_get_pipe_timings(crtc, pipe_config);
10735         }
10736
10737         intel_get_pipe_src_size(crtc, pipe_config);
10738
10739         pipe_config->gamma_mode =
10740                 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
10741
10742         if (INTEL_GEN(dev_priv) >= 9) {
10743                 intel_crtc_init_scalers(crtc, pipe_config);
10744
10745                 pipe_config->scaler_state.scaler_id = -1;
10746                 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
10747         }
10748
10749         power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
10750         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
10751                 power_domain_mask |= BIT(power_domain);
10752                 if (INTEL_GEN(dev_priv) >= 9)
10753                         skylake_get_pfit_config(crtc, pipe_config);
10754                 else
10755                         ironlake_get_pfit_config(crtc, pipe_config);
10756         }
10757
10758         if (IS_HASWELL(dev_priv))
10759                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
10760                         (I915_READ(IPS_CTL) & IPS_ENABLE);
10761
10762         if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
10763             !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10764                 pipe_config->pixel_multiplier =
10765                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
10766         } else {
10767                 pipe_config->pixel_multiplier = 1;
10768         }
10769
10770 out:
10771         for_each_power_domain(power_domain, power_domain_mask)
10772                 intel_display_power_put(dev_priv, power_domain);
10773
10774         return active;
10775 }
10776
10777 static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
10778                                const struct intel_plane_state *plane_state)
10779 {
10780         struct drm_device *dev = crtc->dev;
10781         struct drm_i915_private *dev_priv = to_i915(dev);
10782         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10783         uint32_t cntl = 0, size = 0;
10784
10785         if (plane_state && plane_state->base.visible) {
10786                 unsigned int width = plane_state->base.crtc_w;
10787                 unsigned int height = plane_state->base.crtc_h;
10788                 unsigned int stride = roundup_pow_of_two(width) * 4;
10789
10790                 switch (stride) {
10791                 default:
10792                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10793                                   width, stride);
10794                         stride = 256;
10795                         /* fallthrough */
10796                 case 256:
10797                 case 512:
10798                 case 1024:
10799                 case 2048:
10800                         break;
10801                 }
10802
10803                 cntl |= CURSOR_ENABLE |
10804                         CURSOR_GAMMA_ENABLE |
10805                         CURSOR_FORMAT_ARGB |
10806                         CURSOR_STRIDE(stride);
10807
10808                 size = (height << 12) | width;
10809         }
10810
10811         if (intel_crtc->cursor_cntl != 0 &&
10812             (intel_crtc->cursor_base != base ||
10813              intel_crtc->cursor_size != size ||
10814              intel_crtc->cursor_cntl != cntl)) {
10815                 /* On these chipsets we can only modify the base/size/stride
10816                  * whilst the cursor is disabled.
10817                  */
10818                 I915_WRITE(CURCNTR(PIPE_A), 0);
10819                 POSTING_READ(CURCNTR(PIPE_A));
10820                 intel_crtc->cursor_cntl = 0;
10821         }
10822
10823         if (intel_crtc->cursor_base != base) {
10824                 I915_WRITE(CURBASE(PIPE_A), base);
10825                 intel_crtc->cursor_base = base;
10826         }
10827
10828         if (intel_crtc->cursor_size != size) {
10829                 I915_WRITE(CURSIZE, size);
10830                 intel_crtc->cursor_size = size;
10831         }
10832
10833         if (intel_crtc->cursor_cntl != cntl) {
10834                 I915_WRITE(CURCNTR(PIPE_A), cntl);
10835                 POSTING_READ(CURCNTR(PIPE_A));
10836                 intel_crtc->cursor_cntl = cntl;
10837         }
10838 }
10839
10840 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
10841                                const struct intel_plane_state *plane_state)
10842 {
10843         struct drm_device *dev = crtc->dev;
10844         struct drm_i915_private *dev_priv = to_i915(dev);
10845         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10846         int pipe = intel_crtc->pipe;
10847         uint32_t cntl = 0;
10848
10849         if (plane_state && plane_state->base.visible) {
10850                 cntl = MCURSOR_GAMMA_ENABLE;
10851                 switch (plane_state->base.crtc_w) {
10852                         case 64:
10853                                 cntl |= CURSOR_MODE_64_ARGB_AX;
10854                                 break;
10855                         case 128:
10856                                 cntl |= CURSOR_MODE_128_ARGB_AX;
10857                                 break;
10858                         case 256:
10859                                 cntl |= CURSOR_MODE_256_ARGB_AX;
10860                                 break;
10861                         default:
10862                                 MISSING_CASE(plane_state->base.crtc_w);
10863                                 return;
10864                 }
10865                 cntl |= pipe << 28; /* Connect to correct pipe */
10866
10867                 if (HAS_DDI(dev_priv))
10868                         cntl |= CURSOR_PIPE_CSC_ENABLE;
10869
10870                 if (plane_state->base.rotation & DRM_ROTATE_180)
10871                         cntl |= CURSOR_ROTATE_180;
10872         }
10873
10874         if (intel_crtc->cursor_cntl != cntl) {
10875                 I915_WRITE(CURCNTR(pipe), cntl);
10876                 POSTING_READ(CURCNTR(pipe));
10877                 intel_crtc->cursor_cntl = cntl;
10878         }
10879
10880         /* and commit changes on next vblank */
10881         I915_WRITE(CURBASE(pipe), base);
10882         POSTING_READ(CURBASE(pipe));
10883
10884         intel_crtc->cursor_base = base;
10885 }
10886
10887 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10888 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10889                                      const struct intel_plane_state *plane_state)
10890 {
10891         struct drm_device *dev = crtc->dev;
10892         struct drm_i915_private *dev_priv = to_i915(dev);
10893         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10894         int pipe = intel_crtc->pipe;
10895         u32 base = intel_crtc->cursor_addr;
10896         u32 pos = 0;
10897
10898         if (plane_state) {
10899                 int x = plane_state->base.crtc_x;
10900                 int y = plane_state->base.crtc_y;
10901
10902                 if (x < 0) {
10903                         pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10904                         x = -x;
10905                 }
10906                 pos |= x << CURSOR_X_SHIFT;
10907
10908                 if (y < 0) {
10909                         pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10910                         y = -y;
10911                 }
10912                 pos |= y << CURSOR_Y_SHIFT;
10913
10914                 /* ILK+ do this automagically */
10915                 if (HAS_GMCH_DISPLAY(dev_priv) &&
10916                     plane_state->base.rotation & DRM_ROTATE_180) {
10917                         base += (plane_state->base.crtc_h *
10918                                  plane_state->base.crtc_w - 1) * 4;
10919                 }
10920         }
10921
10922         I915_WRITE(CURPOS(pipe), pos);
10923
10924         if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
10925                 i845_update_cursor(crtc, base, plane_state);
10926         else
10927                 i9xx_update_cursor(crtc, base, plane_state);
10928 }
10929
10930 static bool cursor_size_ok(struct drm_i915_private *dev_priv,
10931                            uint32_t width, uint32_t height)
10932 {
10933         if (width == 0 || height == 0)
10934                 return false;
10935
10936         /*
10937          * 845g/865g are special in that they are only limited by
10938          * the width of their cursors, the height is arbitrary up to
10939          * the precision of the register. Everything else requires
10940          * square cursors, limited to a few power-of-two sizes.
10941          */
10942         if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
10943                 if ((width & 63) != 0)
10944                         return false;
10945
10946                 if (width > (IS_I845G(dev_priv) ? 64 : 512))
10947                         return false;
10948
10949                 if (height > 1023)
10950                         return false;
10951         } else {
10952                 switch (width | height) {
10953                 case 256:
10954                 case 128:
10955                         if (IS_GEN2(dev_priv))
10956                                 return false;
10957                 case 64:
10958                         break;
10959                 default:
10960                         return false;
10961                 }
10962         }
10963
10964         return true;
10965 }
10966
10967 /* VESA 640x480x72Hz mode to set on the pipe */
10968 static struct drm_display_mode load_detect_mode = {
10969         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10970                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10971 };
10972
10973 struct drm_framebuffer *
10974 __intel_framebuffer_create(struct drm_device *dev,
10975                            struct drm_mode_fb_cmd2 *mode_cmd,
10976                            struct drm_i915_gem_object *obj)
10977 {
10978         struct intel_framebuffer *intel_fb;
10979         int ret;
10980
10981         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10982         if (!intel_fb)
10983                 return ERR_PTR(-ENOMEM);
10984
10985         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10986         if (ret)
10987                 goto err;
10988
10989         return &intel_fb->base;
10990
10991 err:
10992         kfree(intel_fb);
10993         return ERR_PTR(ret);
10994 }
10995
10996 static struct drm_framebuffer *
10997 intel_framebuffer_create(struct drm_device *dev,
10998                          struct drm_mode_fb_cmd2 *mode_cmd,
10999                          struct drm_i915_gem_object *obj)
11000 {
11001         struct drm_framebuffer *fb;
11002         int ret;
11003
11004         ret = i915_mutex_lock_interruptible(dev);
11005         if (ret)
11006                 return ERR_PTR(ret);
11007         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
11008         mutex_unlock(&dev->struct_mutex);
11009
11010         return fb;
11011 }
11012
11013 static u32
11014 intel_framebuffer_pitch_for_width(int width, int bpp)
11015 {
11016         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
11017         return ALIGN(pitch, 64);
11018 }
11019
11020 static u32
11021 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
11022 {
11023         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
11024         return PAGE_ALIGN(pitch * mode->vdisplay);
11025 }
11026
11027 static struct drm_framebuffer *
11028 intel_framebuffer_create_for_mode(struct drm_device *dev,
11029                                   struct drm_display_mode *mode,
11030                                   int depth, int bpp)
11031 {
11032         struct drm_framebuffer *fb;
11033         struct drm_i915_gem_object *obj;
11034         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
11035
11036         obj = i915_gem_object_create(to_i915(dev),
11037                                     intel_framebuffer_size_for_mode(mode, bpp));
11038         if (IS_ERR(obj))
11039                 return ERR_CAST(obj);
11040
11041         mode_cmd.width = mode->hdisplay;
11042         mode_cmd.height = mode->vdisplay;
11043         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
11044                                                                 bpp);
11045         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
11046
11047         fb = intel_framebuffer_create(dev, &mode_cmd, obj);
11048         if (IS_ERR(fb))
11049                 i915_gem_object_put(obj);
11050
11051         return fb;
11052 }
11053
11054 static struct drm_framebuffer *
11055 mode_fits_in_fbdev(struct drm_device *dev,
11056                    struct drm_display_mode *mode)
11057 {
11058 #ifdef CONFIG_DRM_FBDEV_EMULATION
11059         struct drm_i915_private *dev_priv = to_i915(dev);
11060         struct drm_i915_gem_object *obj;
11061         struct drm_framebuffer *fb;
11062
11063         if (!dev_priv->fbdev)
11064                 return NULL;
11065
11066         if (!dev_priv->fbdev->fb)
11067                 return NULL;
11068
11069         obj = dev_priv->fbdev->fb->obj;
11070         BUG_ON(!obj);
11071
11072         fb = &dev_priv->fbdev->fb->base;
11073         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
11074                                                                fb->format->cpp[0] * 8))
11075                 return NULL;
11076
11077         if (obj->base.size < mode->vdisplay * fb->pitches[0])
11078                 return NULL;
11079
11080         drm_framebuffer_reference(fb);
11081         return fb;
11082 #else
11083         return NULL;
11084 #endif
11085 }
11086
11087 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
11088                                            struct drm_crtc *crtc,
11089                                            struct drm_display_mode *mode,
11090                                            struct drm_framebuffer *fb,
11091                                            int x, int y)
11092 {
11093         struct drm_plane_state *plane_state;
11094         int hdisplay, vdisplay;
11095         int ret;
11096
11097         plane_state = drm_atomic_get_plane_state(state, crtc->primary);
11098         if (IS_ERR(plane_state))
11099                 return PTR_ERR(plane_state);
11100
11101         if (mode)
11102                 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
11103         else
11104                 hdisplay = vdisplay = 0;
11105
11106         ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
11107         if (ret)
11108                 return ret;
11109         drm_atomic_set_fb_for_plane(plane_state, fb);
11110         plane_state->crtc_x = 0;
11111         plane_state->crtc_y = 0;
11112         plane_state->crtc_w = hdisplay;
11113         plane_state->crtc_h = vdisplay;
11114         plane_state->src_x = x << 16;
11115         plane_state->src_y = y << 16;
11116         plane_state->src_w = hdisplay << 16;
11117         plane_state->src_h = vdisplay << 16;
11118
11119         return 0;
11120 }
11121
11122 bool intel_get_load_detect_pipe(struct drm_connector *connector,
11123                                 struct drm_display_mode *mode,
11124                                 struct intel_load_detect_pipe *old,
11125                                 struct drm_modeset_acquire_ctx *ctx)
11126 {
11127         struct intel_crtc *intel_crtc;
11128         struct intel_encoder *intel_encoder =
11129                 intel_attached_encoder(connector);
11130         struct drm_crtc *possible_crtc;
11131         struct drm_encoder *encoder = &intel_encoder->base;
11132         struct drm_crtc *crtc = NULL;
11133         struct drm_device *dev = encoder->dev;
11134         struct drm_i915_private *dev_priv = to_i915(dev);
11135         struct drm_framebuffer *fb;
11136         struct drm_mode_config *config = &dev->mode_config;
11137         struct drm_atomic_state *state = NULL, *restore_state = NULL;
11138         struct drm_connector_state *connector_state;
11139         struct intel_crtc_state *crtc_state;
11140         int ret, i = -1;
11141
11142         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
11143                       connector->base.id, connector->name,
11144                       encoder->base.id, encoder->name);
11145
11146         old->restore_state = NULL;
11147
11148 retry:
11149         ret = drm_modeset_lock(&config->connection_mutex, ctx);
11150         if (ret)
11151                 goto fail;
11152
11153         /*
11154          * Algorithm gets a little messy:
11155          *
11156          *   - if the connector already has an assigned crtc, use it (but make
11157          *     sure it's on first)
11158          *
11159          *   - try to find the first unused crtc that can drive this connector,
11160          *     and use that if we find one
11161          */
11162
11163         /* See if we already have a CRTC for this connector */
11164         if (connector->state->crtc) {
11165                 crtc = connector->state->crtc;
11166
11167                 ret = drm_modeset_lock(&crtc->mutex, ctx);
11168                 if (ret)
11169                         goto fail;
11170
11171                 /* Make sure the crtc and connector are running */
11172                 goto found;
11173         }
11174
11175         /* Find an unused one (if possible) */
11176         for_each_crtc(dev, possible_crtc) {
11177                 i++;
11178                 if (!(encoder->possible_crtcs & (1 << i)))
11179                         continue;
11180
11181                 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
11182                 if (ret)
11183                         goto fail;
11184
11185                 if (possible_crtc->state->enable) {
11186                         drm_modeset_unlock(&possible_crtc->mutex);
11187                         continue;
11188                 }
11189
11190                 crtc = possible_crtc;
11191                 break;
11192         }
11193
11194         /*
11195          * If we didn't find an unused CRTC, don't use any.
11196          */
11197         if (!crtc) {
11198                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
11199                 goto fail;
11200         }
11201
11202 found:
11203         intel_crtc = to_intel_crtc(crtc);
11204
11205         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
11206         if (ret)
11207                 goto fail;
11208
11209         state = drm_atomic_state_alloc(dev);
11210         restore_state = drm_atomic_state_alloc(dev);
11211         if (!state || !restore_state) {
11212                 ret = -ENOMEM;
11213                 goto fail;
11214         }
11215
11216         state->acquire_ctx = ctx;
11217         restore_state->acquire_ctx = ctx;
11218
11219         connector_state = drm_atomic_get_connector_state(state, connector);
11220         if (IS_ERR(connector_state)) {
11221                 ret = PTR_ERR(connector_state);
11222                 goto fail;
11223         }
11224
11225         ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
11226         if (ret)
11227                 goto fail;
11228
11229         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
11230         if (IS_ERR(crtc_state)) {
11231                 ret = PTR_ERR(crtc_state);
11232                 goto fail;
11233         }
11234
11235         crtc_state->base.active = crtc_state->base.enable = true;
11236
11237         if (!mode)
11238                 mode = &load_detect_mode;
11239
11240         /* We need a framebuffer large enough to accommodate all accesses
11241          * that the plane may generate whilst we perform load detection.
11242          * We can not rely on the fbcon either being present (we get called
11243          * during its initialisation to detect all boot displays, or it may
11244          * not even exist) or that it is large enough to satisfy the
11245          * requested mode.
11246          */
11247         fb = mode_fits_in_fbdev(dev, mode);
11248         if (fb == NULL) {
11249                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
11250                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
11251         } else
11252                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
11253         if (IS_ERR(fb)) {
11254                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
11255                 goto fail;
11256         }
11257
11258         ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
11259         if (ret)
11260                 goto fail;
11261
11262         drm_framebuffer_unreference(fb);
11263
11264         ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
11265         if (ret)
11266                 goto fail;
11267
11268         ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
11269         if (!ret)
11270                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
11271         if (!ret)
11272                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
11273         if (ret) {
11274                 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
11275                 goto fail;
11276         }
11277
11278         ret = drm_atomic_commit(state);
11279         if (ret) {
11280                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
11281                 goto fail;
11282         }
11283
11284         old->restore_state = restore_state;
11285         drm_atomic_state_put(state);
11286
11287         /* let the connector get through one full cycle before testing */
11288         intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
11289         return true;
11290
11291 fail:
11292         if (state) {
11293                 drm_atomic_state_put(state);
11294                 state = NULL;
11295         }
11296         if (restore_state) {
11297                 drm_atomic_state_put(restore_state);
11298                 restore_state = NULL;
11299         }
11300
11301         if (ret == -EDEADLK) {
11302                 drm_modeset_backoff(ctx);
11303                 goto retry;
11304         }
11305
11306         return false;
11307 }
11308
11309 void intel_release_load_detect_pipe(struct drm_connector *connector,
11310                                     struct intel_load_detect_pipe *old,
11311                                     struct drm_modeset_acquire_ctx *ctx)
11312 {
11313         struct intel_encoder *intel_encoder =
11314                 intel_attached_encoder(connector);
11315         struct drm_encoder *encoder = &intel_encoder->base;
11316         struct drm_atomic_state *state = old->restore_state;
11317         int ret;
11318
11319         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
11320                       connector->base.id, connector->name,
11321                       encoder->base.id, encoder->name);
11322
11323         if (!state)
11324                 return;
11325
11326         ret = drm_atomic_commit(state);
11327         if (ret)
11328                 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
11329         drm_atomic_state_put(state);
11330 }
11331
11332 static int i9xx_pll_refclk(struct drm_device *dev,
11333                            const struct intel_crtc_state *pipe_config)
11334 {
11335         struct drm_i915_private *dev_priv = to_i915(dev);
11336         u32 dpll = pipe_config->dpll_hw_state.dpll;
11337
11338         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
11339                 return dev_priv->vbt.lvds_ssc_freq;
11340         else if (HAS_PCH_SPLIT(dev_priv))
11341                 return 120000;
11342         else if (!IS_GEN2(dev_priv))
11343                 return 96000;
11344         else
11345                 return 48000;
11346 }
11347
11348 /* Returns the clock of the currently programmed mode of the given pipe. */
11349 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
11350                                 struct intel_crtc_state *pipe_config)
11351 {
11352         struct drm_device *dev = crtc->base.dev;
11353         struct drm_i915_private *dev_priv = to_i915(dev);
11354         int pipe = pipe_config->cpu_transcoder;
11355         u32 dpll = pipe_config->dpll_hw_state.dpll;
11356         u32 fp;
11357         struct dpll clock;
11358         int port_clock;
11359         int refclk = i9xx_pll_refclk(dev, pipe_config);
11360
11361         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
11362                 fp = pipe_config->dpll_hw_state.fp0;
11363         else
11364                 fp = pipe_config->dpll_hw_state.fp1;
11365
11366         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
11367         if (IS_PINEVIEW(dev_priv)) {
11368                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
11369                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
11370         } else {
11371                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
11372                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
11373         }
11374
11375         if (!IS_GEN2(dev_priv)) {
11376                 if (IS_PINEVIEW(dev_priv))
11377                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
11378                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
11379                 else
11380                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
11381                                DPLL_FPA01_P1_POST_DIV_SHIFT);
11382
11383                 switch (dpll & DPLL_MODE_MASK) {
11384                 case DPLLB_MODE_DAC_SERIAL:
11385                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
11386                                 5 : 10;
11387                         break;
11388                 case DPLLB_MODE_LVDS:
11389                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
11390                                 7 : 14;
11391                         break;
11392                 default:
11393                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
11394                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
11395                         return;
11396                 }
11397
11398                 if (IS_PINEVIEW(dev_priv))
11399                         port_clock = pnv_calc_dpll_params(refclk, &clock);
11400                 else
11401                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
11402         } else {
11403                 u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS);
11404                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
11405
11406                 if (is_lvds) {
11407                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
11408                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
11409
11410                         if (lvds & LVDS_CLKB_POWER_UP)
11411                                 clock.p2 = 7;
11412                         else
11413                                 clock.p2 = 14;
11414                 } else {
11415                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
11416                                 clock.p1 = 2;
11417                         else {
11418                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
11419                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
11420                         }
11421                         if (dpll & PLL_P2_DIVIDE_BY_4)
11422                                 clock.p2 = 4;
11423                         else
11424                                 clock.p2 = 2;
11425                 }
11426
11427                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
11428         }
11429
11430         /*
11431          * This value includes pixel_multiplier. We will use
11432          * port_clock to compute adjusted_mode.crtc_clock in the
11433          * encoder's get_config() function.
11434          */
11435         pipe_config->port_clock = port_clock;
11436 }
11437
11438 int intel_dotclock_calculate(int link_freq,
11439                              const struct intel_link_m_n *m_n)
11440 {
11441         /*
11442          * The calculation for the data clock is:
11443          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
11444          * But we want to avoid losing precison if possible, so:
11445          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
11446          *
11447          * and the link clock is simpler:
11448          * link_clock = (m * link_clock) / n
11449          */
11450
11451         if (!m_n->link_n)
11452                 return 0;
11453
11454         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
11455 }
11456
11457 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
11458                                    struct intel_crtc_state *pipe_config)
11459 {
11460         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11461
11462         /* read out port_clock from the DPLL */
11463         i9xx_crtc_clock_get(crtc, pipe_config);
11464
11465         /*
11466          * In case there is an active pipe without active ports,
11467          * we may need some idea for the dotclock anyway.
11468          * Calculate one based on the FDI configuration.
11469          */
11470         pipe_config->base.adjusted_mode.crtc_clock =
11471                 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
11472                                          &pipe_config->fdi_m_n);
11473 }
11474
11475 /** Returns the currently programmed mode of the given pipe. */
11476 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
11477                                              struct drm_crtc *crtc)
11478 {
11479         struct drm_i915_private *dev_priv = to_i915(dev);
11480         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11481         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
11482         struct drm_display_mode *mode;
11483         struct intel_crtc_state *pipe_config;
11484         int htot = I915_READ(HTOTAL(cpu_transcoder));
11485         int hsync = I915_READ(HSYNC(cpu_transcoder));
11486         int vtot = I915_READ(VTOTAL(cpu_transcoder));
11487         int vsync = I915_READ(VSYNC(cpu_transcoder));
11488         enum pipe pipe = intel_crtc->pipe;
11489
11490         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
11491         if (!mode)
11492                 return NULL;
11493
11494         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
11495         if (!pipe_config) {
11496                 kfree(mode);
11497                 return NULL;
11498         }
11499
11500         /*
11501          * Construct a pipe_config sufficient for getting the clock info
11502          * back out of crtc_clock_get.
11503          *
11504          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
11505          * to use a real value here instead.
11506          */
11507         pipe_config->cpu_transcoder = (enum transcoder) pipe;
11508         pipe_config->pixel_multiplier = 1;
11509         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
11510         pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
11511         pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
11512         i9xx_crtc_clock_get(intel_crtc, pipe_config);
11513
11514         mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
11515         mode->hdisplay = (htot & 0xffff) + 1;
11516         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
11517         mode->hsync_start = (hsync & 0xffff) + 1;
11518         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
11519         mode->vdisplay = (vtot & 0xffff) + 1;
11520         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
11521         mode->vsync_start = (vsync & 0xffff) + 1;
11522         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
11523
11524         drm_mode_set_name(mode);
11525
11526         kfree(pipe_config);
11527
11528         return mode;
11529 }
11530
11531 static void intel_crtc_destroy(struct drm_crtc *crtc)
11532 {
11533         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11534         struct drm_device *dev = crtc->dev;
11535         struct intel_flip_work *work;
11536
11537         spin_lock_irq(&dev->event_lock);
11538         work = intel_crtc->flip_work;
11539         intel_crtc->flip_work = NULL;
11540         spin_unlock_irq(&dev->event_lock);
11541
11542         if (work) {
11543                 cancel_work_sync(&work->mmio_work);
11544                 cancel_work_sync(&work->unpin_work);
11545                 kfree(work);
11546         }
11547
11548         drm_crtc_cleanup(crtc);
11549
11550         kfree(intel_crtc);
11551 }
11552
11553 static void intel_unpin_work_fn(struct work_struct *__work)
11554 {
11555         struct intel_flip_work *work =
11556                 container_of(__work, struct intel_flip_work, unpin_work);
11557         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
11558         struct drm_device *dev = crtc->base.dev;
11559         struct drm_plane *primary = crtc->base.primary;
11560
11561         if (is_mmio_work(work))
11562                 flush_work(&work->mmio_work);
11563
11564         mutex_lock(&dev->struct_mutex);
11565         intel_unpin_fb_vma(work->old_vma);
11566         i915_gem_object_put(work->pending_flip_obj);
11567         mutex_unlock(&dev->struct_mutex);
11568
11569         i915_gem_request_put(work->flip_queued_req);
11570
11571         intel_frontbuffer_flip_complete(to_i915(dev),
11572                                         to_intel_plane(primary)->frontbuffer_bit);
11573         intel_fbc_post_update(crtc);
11574         drm_framebuffer_unreference(work->old_fb);
11575
11576         BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
11577         atomic_dec(&crtc->unpin_work_count);
11578
11579         kfree(work);
11580 }
11581
11582 /* Is 'a' after or equal to 'b'? */
11583 static bool g4x_flip_count_after_eq(u32 a, u32 b)
11584 {
11585         return !((a - b) & 0x80000000);
11586 }
11587
11588 static bool __pageflip_finished_cs(struct intel_crtc *crtc,
11589                                    struct intel_flip_work *work)
11590 {
11591         struct drm_device *dev = crtc->base.dev;
11592         struct drm_i915_private *dev_priv = to_i915(dev);
11593
11594         if (abort_flip_on_reset(crtc))
11595                 return true;
11596
11597         /*
11598          * The relevant registers doen't exist on pre-ctg.
11599          * As the flip done interrupt doesn't trigger for mmio
11600          * flips on gmch platforms, a flip count check isn't
11601          * really needed there. But since ctg has the registers,
11602          * include it in the check anyway.
11603          */
11604         if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
11605                 return true;
11606
11607         /*
11608          * BDW signals flip done immediately if the plane
11609          * is disabled, even if the plane enable is already
11610          * armed to occur at the next vblank :(
11611          */
11612
11613         /*
11614          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
11615          * used the same base address. In that case the mmio flip might
11616          * have completed, but the CS hasn't even executed the flip yet.
11617          *
11618          * A flip count check isn't enough as the CS might have updated
11619          * the base address just after start of vblank, but before we
11620          * managed to process the interrupt. This means we'd complete the
11621          * CS flip too soon.
11622          *
11623          * Combining both checks should get us a good enough result. It may
11624          * still happen that the CS flip has been executed, but has not
11625          * yet actually completed. But in case the base address is the same
11626          * anyway, we don't really care.
11627          */
11628         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
11629                 crtc->flip_work->gtt_offset &&
11630                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
11631                                     crtc->flip_work->flip_count);
11632 }
11633
11634 static bool
11635 __pageflip_finished_mmio(struct intel_crtc *crtc,
11636                                struct intel_flip_work *work)
11637 {
11638         /*
11639          * MMIO work completes when vblank is different from
11640          * flip_queued_vblank.
11641          *
11642          * Reset counter value doesn't matter, this is handled by
11643          * i915_wait_request finishing early, so no need to handle
11644          * reset here.
11645          */
11646         return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank;
11647 }
11648
11649
11650 static bool pageflip_finished(struct intel_crtc *crtc,
11651                               struct intel_flip_work *work)
11652 {
11653         if (!atomic_read(&work->pending))
11654                 return false;
11655
11656         smp_rmb();
11657
11658         if (is_mmio_work(work))
11659                 return __pageflip_finished_mmio(crtc, work);
11660         else
11661                 return __pageflip_finished_cs(crtc, work);
11662 }
11663
11664 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe)
11665 {
11666         struct drm_device *dev = &dev_priv->drm;
11667         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
11668         struct intel_flip_work *work;
11669         unsigned long flags;
11670
11671         /* Ignore early vblank irqs */
11672         if (!crtc)
11673                 return;
11674
11675         /*
11676          * This is called both by irq handlers and the reset code (to complete
11677          * lost pageflips) so needs the full irqsave spinlocks.
11678          */
11679         spin_lock_irqsave(&dev->event_lock, flags);
11680         work = crtc->flip_work;
11681
11682         if (work != NULL &&
11683             !is_mmio_work(work) &&
11684             pageflip_finished(crtc, work))
11685                 page_flip_completed(crtc);
11686
11687         spin_unlock_irqrestore(&dev->event_lock, flags);
11688 }
11689
11690 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe)
11691 {
11692         struct drm_device *dev = &dev_priv->drm;
11693         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
11694         struct intel_flip_work *work;
11695         unsigned long flags;
11696
11697         /* Ignore early vblank irqs */
11698         if (!crtc)
11699                 return;
11700
11701         /*
11702          * This is called both by irq handlers and the reset code (to complete
11703          * lost pageflips) so needs the full irqsave spinlocks.
11704          */
11705         spin_lock_irqsave(&dev->event_lock, flags);
11706         work = crtc->flip_work;
11707
11708         if (work != NULL &&
11709             is_mmio_work(work) &&
11710             pageflip_finished(crtc, work))
11711                 page_flip_completed(crtc);
11712
11713         spin_unlock_irqrestore(&dev->event_lock, flags);
11714 }
11715
11716 static inline void intel_mark_page_flip_active(struct intel_crtc *crtc,
11717                                                struct intel_flip_work *work)
11718 {
11719         work->flip_queued_vblank = intel_crtc_get_vblank_counter(crtc);
11720
11721         /* Ensure that the work item is consistent when activating it ... */
11722         smp_mb__before_atomic();
11723         atomic_set(&work->pending, 1);
11724 }
11725
11726 static int intel_gen2_queue_flip(struct drm_device *dev,
11727                                  struct drm_crtc *crtc,
11728                                  struct drm_framebuffer *fb,
11729                                  struct drm_i915_gem_object *obj,
11730                                  struct drm_i915_gem_request *req,
11731                                  uint32_t flags)
11732 {
11733         struct intel_ring *ring = req->ring;
11734         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11735         u32 flip_mask;
11736         int ret;
11737
11738         ret = intel_ring_begin(req, 6);
11739         if (ret)
11740                 return ret;
11741
11742         /* Can't queue multiple flips, so wait for the previous
11743          * one to finish before executing the next.
11744          */
11745         if (intel_crtc->plane)
11746                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11747         else
11748                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11749         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11750         intel_ring_emit(ring, MI_NOOP);
11751         intel_ring_emit(ring, MI_DISPLAY_FLIP |
11752                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11753         intel_ring_emit(ring, fb->pitches[0]);
11754         intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11755         intel_ring_emit(ring, 0); /* aux display base address, unused */
11756
11757         return 0;
11758 }
11759
11760 static int intel_gen3_queue_flip(struct drm_device *dev,
11761                                  struct drm_crtc *crtc,
11762                                  struct drm_framebuffer *fb,
11763                                  struct drm_i915_gem_object *obj,
11764                                  struct drm_i915_gem_request *req,
11765                                  uint32_t flags)
11766 {
11767         struct intel_ring *ring = req->ring;
11768         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11769         u32 flip_mask;
11770         int ret;
11771
11772         ret = intel_ring_begin(req, 6);
11773         if (ret)
11774                 return ret;
11775
11776         if (intel_crtc->plane)
11777                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11778         else
11779                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11780         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11781         intel_ring_emit(ring, MI_NOOP);
11782         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
11783                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11784         intel_ring_emit(ring, fb->pitches[0]);
11785         intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11786         intel_ring_emit(ring, MI_NOOP);
11787
11788         return 0;
11789 }
11790
11791 static int intel_gen4_queue_flip(struct drm_device *dev,
11792                                  struct drm_crtc *crtc,
11793                                  struct drm_framebuffer *fb,
11794                                  struct drm_i915_gem_object *obj,
11795                                  struct drm_i915_gem_request *req,
11796                                  uint32_t flags)
11797 {
11798         struct intel_ring *ring = req->ring;
11799         struct drm_i915_private *dev_priv = to_i915(dev);
11800         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11801         uint32_t pf, pipesrc;
11802         int ret;
11803
11804         ret = intel_ring_begin(req, 4);
11805         if (ret)
11806                 return ret;
11807
11808         /* i965+ uses the linear or tiled offsets from the
11809          * Display Registers (which do not change across a page-flip)
11810          * so we need only reprogram the base address.
11811          */
11812         intel_ring_emit(ring, MI_DISPLAY_FLIP |
11813                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11814         intel_ring_emit(ring, fb->pitches[0]);
11815         intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset |
11816                         intel_fb_modifier_to_tiling(fb->modifier));
11817
11818         /* XXX Enabling the panel-fitter across page-flip is so far
11819          * untested on non-native modes, so ignore it for now.
11820          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11821          */
11822         pf = 0;
11823         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11824         intel_ring_emit(ring, pf | pipesrc);
11825
11826         return 0;
11827 }
11828
11829 static int intel_gen6_queue_flip(struct drm_device *dev,
11830                                  struct drm_crtc *crtc,
11831                                  struct drm_framebuffer *fb,
11832                                  struct drm_i915_gem_object *obj,
11833                                  struct drm_i915_gem_request *req,
11834                                  uint32_t flags)
11835 {
11836         struct intel_ring *ring = req->ring;
11837         struct drm_i915_private *dev_priv = to_i915(dev);
11838         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11839         uint32_t pf, pipesrc;
11840         int ret;
11841
11842         ret = intel_ring_begin(req, 4);
11843         if (ret)
11844                 return ret;
11845
11846         intel_ring_emit(ring, MI_DISPLAY_FLIP |
11847                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11848         intel_ring_emit(ring, fb->pitches[0] |
11849                         intel_fb_modifier_to_tiling(fb->modifier));
11850         intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11851
11852         /* Contrary to the suggestions in the documentation,
11853          * "Enable Panel Fitter" does not seem to be required when page
11854          * flipping with a non-native mode, and worse causes a normal
11855          * modeset to fail.
11856          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11857          */
11858         pf = 0;
11859         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11860         intel_ring_emit(ring, pf | pipesrc);
11861
11862         return 0;
11863 }
11864
11865 static int intel_gen7_queue_flip(struct drm_device *dev,
11866                                  struct drm_crtc *crtc,
11867                                  struct drm_framebuffer *fb,
11868                                  struct drm_i915_gem_object *obj,
11869                                  struct drm_i915_gem_request *req,
11870                                  uint32_t flags)
11871 {
11872         struct drm_i915_private *dev_priv = to_i915(dev);
11873         struct intel_ring *ring = req->ring;
11874         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11875         uint32_t plane_bit = 0;
11876         int len, ret;
11877
11878         switch (intel_crtc->plane) {
11879         case PLANE_A:
11880                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11881                 break;
11882         case PLANE_B:
11883                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11884                 break;
11885         case PLANE_C:
11886                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11887                 break;
11888         default:
11889                 WARN_ONCE(1, "unknown plane in flip command\n");
11890                 return -ENODEV;
11891         }
11892
11893         len = 4;
11894         if (req->engine->id == RCS) {
11895                 len += 6;
11896                 /*
11897                  * On Gen 8, SRM is now taking an extra dword to accommodate
11898                  * 48bits addresses, and we need a NOOP for the batch size to
11899                  * stay even.
11900                  */
11901                 if (IS_GEN8(dev_priv))
11902                         len += 2;
11903         }
11904
11905         /*
11906          * BSpec MI_DISPLAY_FLIP for IVB:
11907          * "The full packet must be contained within the same cache line."
11908          *
11909          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11910          * cacheline, if we ever start emitting more commands before
11911          * the MI_DISPLAY_FLIP we may need to first emit everything else,
11912          * then do the cacheline alignment, and finally emit the
11913          * MI_DISPLAY_FLIP.
11914          */
11915         ret = intel_ring_cacheline_align(req);
11916         if (ret)
11917                 return ret;
11918
11919         ret = intel_ring_begin(req, len);
11920         if (ret)
11921                 return ret;
11922
11923         /* Unmask the flip-done completion message. Note that the bspec says that
11924          * we should do this for both the BCS and RCS, and that we must not unmask
11925          * more than one flip event at any time (or ensure that one flip message
11926          * can be sent by waiting for flip-done prior to queueing new flips).
11927          * Experimentation says that BCS works despite DERRMR masking all
11928          * flip-done completion events and that unmasking all planes at once
11929          * for the RCS also doesn't appear to drop events. Setting the DERRMR
11930          * to zero does lead to lockups within MI_DISPLAY_FLIP.
11931          */
11932         if (req->engine->id == RCS) {
11933                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11934                 intel_ring_emit_reg(ring, DERRMR);
11935                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11936                                           DERRMR_PIPEB_PRI_FLIP_DONE |
11937                                           DERRMR_PIPEC_PRI_FLIP_DONE));
11938                 if (IS_GEN8(dev_priv))
11939                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
11940                                               MI_SRM_LRM_GLOBAL_GTT);
11941                 else
11942                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
11943                                               MI_SRM_LRM_GLOBAL_GTT);
11944                 intel_ring_emit_reg(ring, DERRMR);
11945                 intel_ring_emit(ring,
11946                                 i915_ggtt_offset(req->engine->scratch) + 256);
11947                 if (IS_GEN8(dev_priv)) {
11948                         intel_ring_emit(ring, 0);
11949                         intel_ring_emit(ring, MI_NOOP);
11950                 }
11951         }
11952
11953         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11954         intel_ring_emit(ring, fb->pitches[0] |
11955                         intel_fb_modifier_to_tiling(fb->modifier));
11956         intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11957         intel_ring_emit(ring, (MI_NOOP));
11958
11959         return 0;
11960 }
11961
11962 static bool use_mmio_flip(struct intel_engine_cs *engine,
11963                           struct drm_i915_gem_object *obj)
11964 {
11965         /*
11966          * This is not being used for older platforms, because
11967          * non-availability of flip done interrupt forces us to use
11968          * CS flips. Older platforms derive flip done using some clever
11969          * tricks involving the flip_pending status bits and vblank irqs.
11970          * So using MMIO flips there would disrupt this mechanism.
11971          */
11972
11973         if (engine == NULL)
11974                 return true;
11975
11976         if (INTEL_GEN(engine->i915) < 5)
11977                 return false;
11978
11979         if (i915.use_mmio_flip < 0)
11980                 return false;
11981         else if (i915.use_mmio_flip > 0)
11982                 return true;
11983         else if (i915.enable_execlists)
11984                 return true;
11985
11986         return engine != i915_gem_object_last_write_engine(obj);
11987 }
11988
11989 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11990                              unsigned int rotation,
11991                              struct intel_flip_work *work)
11992 {
11993         struct drm_device *dev = intel_crtc->base.dev;
11994         struct drm_i915_private *dev_priv = to_i915(dev);
11995         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11996         const enum pipe pipe = intel_crtc->pipe;
11997         u32 ctl, stride = skl_plane_stride(fb, 0, rotation);
11998
11999         ctl = I915_READ(PLANE_CTL(pipe, 0));
12000         ctl &= ~PLANE_CTL_TILED_MASK;
12001         switch (fb->modifier) {
12002         case DRM_FORMAT_MOD_NONE:
12003                 break;
12004         case I915_FORMAT_MOD_X_TILED:
12005                 ctl |= PLANE_CTL_TILED_X;
12006                 break;
12007         case I915_FORMAT_MOD_Y_TILED:
12008                 ctl |= PLANE_CTL_TILED_Y;
12009                 break;
12010         case I915_FORMAT_MOD_Yf_TILED:
12011                 ctl |= PLANE_CTL_TILED_YF;
12012                 break;
12013         default:
12014                 MISSING_CASE(fb->modifier);
12015         }
12016
12017         /*
12018          * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
12019          * PLANE_SURF updates, the update is then guaranteed to be atomic.
12020          */
12021         I915_WRITE(PLANE_CTL(pipe, 0), ctl);
12022         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
12023
12024         I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
12025         POSTING_READ(PLANE_SURF(pipe, 0));
12026 }
12027
12028 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
12029                              struct intel_flip_work *work)
12030 {
12031         struct drm_device *dev = intel_crtc->base.dev;
12032         struct drm_i915_private *dev_priv = to_i915(dev);
12033         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
12034         i915_reg_t reg = DSPCNTR(intel_crtc->plane);
12035         u32 dspcntr;
12036
12037         dspcntr = I915_READ(reg);
12038
12039         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
12040                 dspcntr |= DISPPLANE_TILED;
12041         else
12042                 dspcntr &= ~DISPPLANE_TILED;
12043
12044         I915_WRITE(reg, dspcntr);
12045
12046         I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
12047         POSTING_READ(DSPSURF(intel_crtc->plane));
12048 }
12049
12050 static void intel_mmio_flip_work_func(struct work_struct *w)
12051 {
12052         struct intel_flip_work *work =
12053                 container_of(w, struct intel_flip_work, mmio_work);
12054         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
12055         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12056         struct intel_framebuffer *intel_fb =
12057                 to_intel_framebuffer(crtc->base.primary->fb);
12058         struct drm_i915_gem_object *obj = intel_fb->obj;
12059
12060         WARN_ON(i915_gem_object_wait(obj, 0, MAX_SCHEDULE_TIMEOUT, NULL) < 0);
12061
12062         intel_pipe_update_start(crtc);
12063
12064         if (INTEL_GEN(dev_priv) >= 9)
12065                 skl_do_mmio_flip(crtc, work->rotation, work);
12066         else
12067                 /* use_mmio_flip() retricts MMIO flips to ilk+ */
12068                 ilk_do_mmio_flip(crtc, work);
12069
12070         intel_pipe_update_end(crtc, work);
12071 }
12072
12073 static int intel_default_queue_flip(struct drm_device *dev,
12074                                     struct drm_crtc *crtc,
12075                                     struct drm_framebuffer *fb,
12076                                     struct drm_i915_gem_object *obj,
12077                                     struct drm_i915_gem_request *req,
12078                                     uint32_t flags)
12079 {
12080         return -ENODEV;
12081 }
12082
12083 static bool __pageflip_stall_check_cs(struct drm_i915_private *dev_priv,
12084                                       struct intel_crtc *intel_crtc,
12085                                       struct intel_flip_work *work)
12086 {
12087         u32 addr, vblank;
12088
12089         if (!atomic_read(&work->pending))
12090                 return false;
12091
12092         smp_rmb();
12093
12094         vblank = intel_crtc_get_vblank_counter(intel_crtc);
12095         if (work->flip_ready_vblank == 0) {
12096                 if (work->flip_queued_req &&
12097                     !i915_gem_request_completed(work->flip_queued_req))
12098                         return false;
12099
12100                 work->flip_ready_vblank = vblank;
12101         }
12102
12103         if (vblank - work->flip_ready_vblank < 3)
12104                 return false;
12105
12106         /* Potential stall - if we see that the flip has happened,
12107          * assume a missed interrupt. */
12108         if (INTEL_GEN(dev_priv) >= 4)
12109                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
12110         else
12111                 addr = I915_READ(DSPADDR(intel_crtc->plane));
12112
12113         /* There is a potential issue here with a false positive after a flip
12114          * to the same address. We could address this by checking for a
12115          * non-incrementing frame counter.
12116          */
12117         return addr == work->gtt_offset;
12118 }
12119
12120 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe)
12121 {
12122         struct drm_device *dev = &dev_priv->drm;
12123         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
12124         struct intel_flip_work *work;
12125
12126         WARN_ON(!in_interrupt());
12127
12128         if (crtc == NULL)
12129                 return;
12130
12131         spin_lock(&dev->event_lock);
12132         work = crtc->flip_work;
12133
12134         if (work != NULL && !is_mmio_work(work) &&
12135             __pageflip_stall_check_cs(dev_priv, crtc, work)) {
12136                 WARN_ONCE(1,
12137                           "Kicking stuck page flip: queued at %d, now %d\n",
12138                         work->flip_queued_vblank, intel_crtc_get_vblank_counter(crtc));
12139                 page_flip_completed(crtc);
12140                 work = NULL;
12141         }
12142
12143         if (work != NULL && !is_mmio_work(work) &&
12144             intel_crtc_get_vblank_counter(crtc) - work->flip_queued_vblank > 1)
12145                 intel_queue_rps_boost_for_request(work->flip_queued_req);
12146         spin_unlock(&dev->event_lock);
12147 }
12148
12149 __maybe_unused
12150 static int intel_crtc_page_flip(struct drm_crtc *crtc,
12151                                 struct drm_framebuffer *fb,
12152                                 struct drm_pending_vblank_event *event,
12153                                 uint32_t page_flip_flags)
12154 {
12155         struct drm_device *dev = crtc->dev;
12156         struct drm_i915_private *dev_priv = to_i915(dev);
12157         struct drm_framebuffer *old_fb = crtc->primary->fb;
12158         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12159         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12160         struct drm_plane *primary = crtc->primary;
12161         enum pipe pipe = intel_crtc->pipe;
12162         struct intel_flip_work *work;
12163         struct intel_engine_cs *engine;
12164         bool mmio_flip;
12165         struct drm_i915_gem_request *request;
12166         struct i915_vma *vma;
12167         int ret;
12168
12169         /*
12170          * drm_mode_page_flip_ioctl() should already catch this, but double
12171          * check to be safe.  In the future we may enable pageflipping from
12172          * a disabled primary plane.
12173          */
12174         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
12175                 return -EBUSY;
12176
12177         /* Can't change pixel format via MI display flips. */
12178         if (fb->format != crtc->primary->fb->format)
12179                 return -EINVAL;
12180
12181         /*
12182          * TILEOFF/LINOFF registers can't be changed via MI display flips.
12183          * Note that pitch changes could also affect these register.
12184          */
12185         if (INTEL_GEN(dev_priv) > 3 &&
12186             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
12187              fb->pitches[0] != crtc->primary->fb->pitches[0]))
12188                 return -EINVAL;
12189
12190         if (i915_terminally_wedged(&dev_priv->gpu_error))
12191                 goto out_hang;
12192
12193         work = kzalloc(sizeof(*work), GFP_KERNEL);
12194         if (work == NULL)
12195                 return -ENOMEM;
12196
12197         work->event = event;
12198         work->crtc = crtc;
12199         work->old_fb = old_fb;
12200         INIT_WORK(&work->unpin_work, intel_unpin_work_fn);
12201
12202         ret = drm_crtc_vblank_get(crtc);
12203         if (ret)
12204                 goto free_work;
12205
12206         /* We borrow the event spin lock for protecting flip_work */
12207         spin_lock_irq(&dev->event_lock);
12208         if (intel_crtc->flip_work) {
12209                 /* Before declaring the flip queue wedged, check if
12210                  * the hardware completed the operation behind our backs.
12211                  */
12212                 if (pageflip_finished(intel_crtc, intel_crtc->flip_work)) {
12213                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
12214                         page_flip_completed(intel_crtc);
12215                 } else {
12216                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
12217                         spin_unlock_irq(&dev->event_lock);
12218
12219                         drm_crtc_vblank_put(crtc);
12220                         kfree(work);
12221                         return -EBUSY;
12222                 }
12223         }
12224         intel_crtc->flip_work = work;
12225         spin_unlock_irq(&dev->event_lock);
12226
12227         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
12228                 flush_workqueue(dev_priv->wq);
12229
12230         /* Reference the objects for the scheduled work. */
12231         drm_framebuffer_reference(work->old_fb);
12232
12233         crtc->primary->fb = fb;
12234         update_state_fb(crtc->primary);
12235
12236         work->pending_flip_obj = i915_gem_object_get(obj);
12237
12238         ret = i915_mutex_lock_interruptible(dev);
12239         if (ret)
12240                 goto cleanup;
12241
12242         intel_crtc->reset_count = i915_reset_count(&dev_priv->gpu_error);
12243         if (i915_reset_in_progress_or_wedged(&dev_priv->gpu_error)) {
12244                 ret = -EIO;
12245                 goto unlock;
12246         }
12247
12248         atomic_inc(&intel_crtc->unpin_work_count);
12249
12250         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
12251                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
12252
12253         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
12254                 engine = dev_priv->engine[BCS];
12255                 if (fb->modifier != old_fb->modifier)
12256                         /* vlv: DISPLAY_FLIP fails to change tiling */
12257                         engine = NULL;
12258         } else if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
12259                 engine = dev_priv->engine[BCS];
12260         } else if (INTEL_GEN(dev_priv) >= 7) {
12261                 engine = i915_gem_object_last_write_engine(obj);
12262                 if (engine == NULL || engine->id != RCS)
12263                         engine = dev_priv->engine[BCS];
12264         } else {
12265                 engine = dev_priv->engine[RCS];
12266         }
12267
12268         mmio_flip = use_mmio_flip(engine, obj);
12269
12270         vma = intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
12271         if (IS_ERR(vma)) {
12272                 ret = PTR_ERR(vma);
12273                 goto cleanup_pending;
12274         }
12275
12276         work->old_vma = to_intel_plane_state(primary->state)->vma;
12277         to_intel_plane_state(primary->state)->vma = vma;
12278
12279         work->gtt_offset = i915_ggtt_offset(vma) + intel_crtc->dspaddr_offset;
12280         work->rotation = crtc->primary->state->rotation;
12281
12282         /*
12283          * There's the potential that the next frame will not be compatible with
12284          * FBC, so we want to call pre_update() before the actual page flip.
12285          * The problem is that pre_update() caches some information about the fb
12286          * object, so we want to do this only after the object is pinned. Let's
12287          * be on the safe side and do this immediately before scheduling the
12288          * flip.
12289          */
12290         intel_fbc_pre_update(intel_crtc, intel_crtc->config,
12291                              to_intel_plane_state(primary->state));
12292
12293         if (mmio_flip) {
12294                 INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func);
12295                 queue_work(system_unbound_wq, &work->mmio_work);
12296         } else {
12297                 request = i915_gem_request_alloc(engine,
12298                                                  dev_priv->kernel_context);
12299                 if (IS_ERR(request)) {
12300                         ret = PTR_ERR(request);
12301                         goto cleanup_unpin;
12302                 }
12303
12304                 ret = i915_gem_request_await_object(request, obj, false);
12305                 if (ret)
12306                         goto cleanup_request;
12307
12308                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
12309                                                    page_flip_flags);
12310                 if (ret)
12311                         goto cleanup_request;
12312
12313                 intel_mark_page_flip_active(intel_crtc, work);
12314
12315                 work->flip_queued_req = i915_gem_request_get(request);
12316                 i915_add_request_no_flush(request);
12317         }
12318
12319         i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY);
12320         i915_gem_track_fb(intel_fb_obj(old_fb), obj,
12321                           to_intel_plane(primary)->frontbuffer_bit);
12322         mutex_unlock(&dev->struct_mutex);
12323
12324         intel_frontbuffer_flip_prepare(to_i915(dev),
12325                                        to_intel_plane(primary)->frontbuffer_bit);
12326
12327         trace_i915_flip_request(intel_crtc->plane, obj);
12328
12329         return 0;
12330
12331 cleanup_request:
12332         i915_add_request_no_flush(request);
12333 cleanup_unpin:
12334         to_intel_plane_state(primary->state)->vma = work->old_vma;
12335         intel_unpin_fb_vma(vma);
12336 cleanup_pending:
12337         atomic_dec(&intel_crtc->unpin_work_count);
12338 unlock:
12339         mutex_unlock(&dev->struct_mutex);
12340 cleanup:
12341         crtc->primary->fb = old_fb;
12342         update_state_fb(crtc->primary);
12343
12344         i915_gem_object_put(obj);
12345         drm_framebuffer_unreference(work->old_fb);
12346
12347         spin_lock_irq(&dev->event_lock);
12348         intel_crtc->flip_work = NULL;
12349         spin_unlock_irq(&dev->event_lock);
12350
12351         drm_crtc_vblank_put(crtc);
12352 free_work:
12353         kfree(work);
12354
12355         if (ret == -EIO) {
12356                 struct drm_atomic_state *state;
12357                 struct drm_plane_state *plane_state;
12358
12359 out_hang:
12360                 state = drm_atomic_state_alloc(dev);
12361                 if (!state)
12362                         return -ENOMEM;
12363                 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
12364
12365 retry:
12366                 plane_state = drm_atomic_get_plane_state(state, primary);
12367                 ret = PTR_ERR_OR_ZERO(plane_state);
12368                 if (!ret) {
12369                         drm_atomic_set_fb_for_plane(plane_state, fb);
12370
12371                         ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
12372                         if (!ret)
12373                                 ret = drm_atomic_commit(state);
12374                 }
12375
12376                 if (ret == -EDEADLK) {
12377                         drm_modeset_backoff(state->acquire_ctx);
12378                         drm_atomic_state_clear(state);
12379                         goto retry;
12380                 }
12381
12382                 drm_atomic_state_put(state);
12383
12384                 if (ret == 0 && event) {
12385                         spin_lock_irq(&dev->event_lock);
12386                         drm_crtc_send_vblank_event(crtc, event);
12387                         spin_unlock_irq(&dev->event_lock);
12388                 }
12389         }
12390         return ret;
12391 }
12392
12393
12394 /**
12395  * intel_wm_need_update - Check whether watermarks need updating
12396  * @plane: drm plane
12397  * @state: new plane state
12398  *
12399  * Check current plane state versus the new one to determine whether
12400  * watermarks need to be recalculated.
12401  *
12402  * Returns true or false.
12403  */
12404 static bool intel_wm_need_update(struct drm_plane *plane,
12405                                  struct drm_plane_state *state)
12406 {
12407         struct intel_plane_state *new = to_intel_plane_state(state);
12408         struct intel_plane_state *cur = to_intel_plane_state(plane->state);
12409
12410         /* Update watermarks on tiling or size changes. */
12411         if (new->base.visible != cur->base.visible)
12412                 return true;
12413
12414         if (!cur->base.fb || !new->base.fb)
12415                 return false;
12416
12417         if (cur->base.fb->modifier != new->base.fb->modifier ||
12418             cur->base.rotation != new->base.rotation ||
12419             drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) ||
12420             drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) ||
12421             drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) ||
12422             drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst))
12423                 return true;
12424
12425         return false;
12426 }
12427
12428 static bool needs_scaling(struct intel_plane_state *state)
12429 {
12430         int src_w = drm_rect_width(&state->base.src) >> 16;
12431         int src_h = drm_rect_height(&state->base.src) >> 16;
12432         int dst_w = drm_rect_width(&state->base.dst);
12433         int dst_h = drm_rect_height(&state->base.dst);
12434
12435         return (src_w != dst_w || src_h != dst_h);
12436 }
12437
12438 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
12439                                     struct drm_plane_state *plane_state)
12440 {
12441         struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
12442         struct drm_crtc *crtc = crtc_state->crtc;
12443         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12444         struct drm_plane *plane = plane_state->plane;
12445         struct drm_device *dev = crtc->dev;
12446         struct drm_i915_private *dev_priv = to_i915(dev);
12447         struct intel_plane_state *old_plane_state =
12448                 to_intel_plane_state(plane->state);
12449         bool mode_changed = needs_modeset(crtc_state);
12450         bool was_crtc_enabled = crtc->state->active;
12451         bool is_crtc_enabled = crtc_state->active;
12452         bool turn_off, turn_on, visible, was_visible;
12453         struct drm_framebuffer *fb = plane_state->fb;
12454         int ret;
12455
12456         if (INTEL_GEN(dev_priv) >= 9 && plane->type != DRM_PLANE_TYPE_CURSOR) {
12457                 ret = skl_update_scaler_plane(
12458                         to_intel_crtc_state(crtc_state),
12459                         to_intel_plane_state(plane_state));
12460                 if (ret)
12461                         return ret;
12462         }
12463
12464         was_visible = old_plane_state->base.visible;
12465         visible = plane_state->visible;
12466
12467         if (!was_crtc_enabled && WARN_ON(was_visible))
12468                 was_visible = false;
12469
12470         /*
12471          * Visibility is calculated as if the crtc was on, but
12472          * after scaler setup everything depends on it being off
12473          * when the crtc isn't active.
12474          *
12475          * FIXME this is wrong for watermarks. Watermarks should also
12476          * be computed as if the pipe would be active. Perhaps move
12477          * per-plane wm computation to the .check_plane() hook, and
12478          * only combine the results from all planes in the current place?
12479          */
12480         if (!is_crtc_enabled)
12481                 plane_state->visible = visible = false;
12482
12483         if (!was_visible && !visible)
12484                 return 0;
12485
12486         if (fb != old_plane_state->base.fb)
12487                 pipe_config->fb_changed = true;
12488
12489         turn_off = was_visible && (!visible || mode_changed);
12490         turn_on = visible && (!was_visible || mode_changed);
12491
12492         DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
12493                          intel_crtc->base.base.id,
12494                          intel_crtc->base.name,
12495                          plane->base.id, plane->name,
12496                          fb ? fb->base.id : -1);
12497
12498         DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
12499                          plane->base.id, plane->name,
12500                          was_visible, visible,
12501                          turn_off, turn_on, mode_changed);
12502
12503         if (turn_on) {
12504                 pipe_config->update_wm_pre = true;
12505
12506                 /* must disable cxsr around plane enable/disable */
12507                 if (plane->type != DRM_PLANE_TYPE_CURSOR)
12508                         pipe_config->disable_cxsr = true;
12509         } else if (turn_off) {
12510                 pipe_config->update_wm_post = true;
12511
12512                 /* must disable cxsr around plane enable/disable */
12513                 if (plane->type != DRM_PLANE_TYPE_CURSOR)
12514                         pipe_config->disable_cxsr = true;
12515         } else if (intel_wm_need_update(plane, plane_state)) {
12516                 /* FIXME bollocks */
12517                 pipe_config->update_wm_pre = true;
12518                 pipe_config->update_wm_post = true;
12519         }
12520
12521         /* Pre-gen9 platforms need two-step watermark updates */
12522         if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) &&
12523             INTEL_GEN(dev_priv) < 9 && dev_priv->display.optimize_watermarks)
12524                 to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true;
12525
12526         if (visible || was_visible)
12527                 pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit;
12528
12529         /*
12530          * WaCxSRDisabledForSpriteScaling:ivb
12531          *
12532          * cstate->update_wm was already set above, so this flag will
12533          * take effect when we commit and program watermarks.
12534          */
12535         if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev_priv) &&
12536             needs_scaling(to_intel_plane_state(plane_state)) &&
12537             !needs_scaling(old_plane_state))
12538                 pipe_config->disable_lp_wm = true;
12539
12540         return 0;
12541 }
12542
12543 static bool encoders_cloneable(const struct intel_encoder *a,
12544                                const struct intel_encoder *b)
12545 {
12546         /* masks could be asymmetric, so check both ways */
12547         return a == b || (a->cloneable & (1 << b->type) &&
12548                           b->cloneable & (1 << a->type));
12549 }
12550
12551 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
12552                                          struct intel_crtc *crtc,
12553                                          struct intel_encoder *encoder)
12554 {
12555         struct intel_encoder *source_encoder;
12556         struct drm_connector *connector;
12557         struct drm_connector_state *connector_state;
12558         int i;
12559
12560         for_each_connector_in_state(state, connector, connector_state, i) {
12561                 if (connector_state->crtc != &crtc->base)
12562                         continue;
12563
12564                 source_encoder =
12565                         to_intel_encoder(connector_state->best_encoder);
12566                 if (!encoders_cloneable(encoder, source_encoder))
12567                         return false;
12568         }
12569
12570         return true;
12571 }
12572
12573 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
12574                                    struct drm_crtc_state *crtc_state)
12575 {
12576         struct drm_device *dev = crtc->dev;
12577         struct drm_i915_private *dev_priv = to_i915(dev);
12578         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12579         struct intel_crtc_state *pipe_config =
12580                 to_intel_crtc_state(crtc_state);
12581         struct drm_atomic_state *state = crtc_state->state;
12582         int ret;
12583         bool mode_changed = needs_modeset(crtc_state);
12584
12585         if (mode_changed && !crtc_state->active)
12586                 pipe_config->update_wm_post = true;
12587
12588         if (mode_changed && crtc_state->enable &&
12589             dev_priv->display.crtc_compute_clock &&
12590             !WARN_ON(pipe_config->shared_dpll)) {
12591                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
12592                                                            pipe_config);
12593                 if (ret)
12594                         return ret;
12595         }
12596
12597         if (crtc_state->color_mgmt_changed) {
12598                 ret = intel_color_check(crtc, crtc_state);
12599                 if (ret)
12600                         return ret;
12601
12602                 /*
12603                  * Changing color management on Intel hardware is
12604                  * handled as part of planes update.
12605                  */
12606                 crtc_state->planes_changed = true;
12607         }
12608
12609         ret = 0;
12610         if (dev_priv->display.compute_pipe_wm) {
12611                 ret = dev_priv->display.compute_pipe_wm(pipe_config);
12612                 if (ret) {
12613                         DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
12614                         return ret;
12615                 }
12616         }
12617
12618         if (dev_priv->display.compute_intermediate_wm &&
12619             !to_intel_atomic_state(state)->skip_intermediate_wm) {
12620                 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
12621                         return 0;
12622
12623                 /*
12624                  * Calculate 'intermediate' watermarks that satisfy both the
12625                  * old state and the new state.  We can program these
12626                  * immediately.
12627                  */
12628                 ret = dev_priv->display.compute_intermediate_wm(dev,
12629                                                                 intel_crtc,
12630                                                                 pipe_config);
12631                 if (ret) {
12632                         DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
12633                         return ret;
12634                 }
12635         } else if (dev_priv->display.compute_intermediate_wm) {
12636                 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
12637                         pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
12638         }
12639
12640         if (INTEL_GEN(dev_priv) >= 9) {
12641                 if (mode_changed)
12642                         ret = skl_update_scaler_crtc(pipe_config);
12643
12644                 if (!ret)
12645                         ret = intel_atomic_setup_scalers(dev, intel_crtc,
12646                                                          pipe_config);
12647         }
12648
12649         return ret;
12650 }
12651
12652 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
12653         .mode_set_base_atomic = intel_pipe_set_base_atomic,
12654         .atomic_begin = intel_begin_crtc_commit,
12655         .atomic_flush = intel_finish_crtc_commit,
12656         .atomic_check = intel_crtc_atomic_check,
12657 };
12658
12659 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
12660 {
12661         struct intel_connector *connector;
12662
12663         for_each_intel_connector(dev, connector) {
12664                 if (connector->base.state->crtc)
12665                         drm_connector_unreference(&connector->base);
12666
12667                 if (connector->base.encoder) {
12668                         connector->base.state->best_encoder =
12669                                 connector->base.encoder;
12670                         connector->base.state->crtc =
12671                                 connector->base.encoder->crtc;
12672
12673                         drm_connector_reference(&connector->base);
12674                 } else {
12675                         connector->base.state->best_encoder = NULL;
12676                         connector->base.state->crtc = NULL;
12677                 }
12678         }
12679 }
12680
12681 static void
12682 connected_sink_compute_bpp(struct intel_connector *connector,
12683                            struct intel_crtc_state *pipe_config)
12684 {
12685         const struct drm_display_info *info = &connector->base.display_info;
12686         int bpp = pipe_config->pipe_bpp;
12687
12688         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
12689                       connector->base.base.id,
12690                       connector->base.name);
12691
12692         /* Don't use an invalid EDID bpc value */
12693         if (info->bpc != 0 && info->bpc * 3 < bpp) {
12694                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
12695                               bpp, info->bpc * 3);
12696                 pipe_config->pipe_bpp = info->bpc * 3;
12697         }
12698
12699         /* Clamp bpp to 8 on screens without EDID 1.4 */
12700         if (info->bpc == 0 && bpp > 24) {
12701                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
12702                               bpp);
12703                 pipe_config->pipe_bpp = 24;
12704         }
12705 }
12706
12707 static int
12708 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12709                           struct intel_crtc_state *pipe_config)
12710 {
12711         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12712         struct drm_atomic_state *state;
12713         struct drm_connector *connector;
12714         struct drm_connector_state *connector_state;
12715         int bpp, i;
12716
12717         if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
12718             IS_CHERRYVIEW(dev_priv)))
12719                 bpp = 10*3;
12720         else if (INTEL_GEN(dev_priv) >= 5)
12721                 bpp = 12*3;
12722         else
12723                 bpp = 8*3;
12724
12725
12726         pipe_config->pipe_bpp = bpp;
12727
12728         state = pipe_config->base.state;
12729
12730         /* Clamp display bpp to EDID value */
12731         for_each_connector_in_state(state, connector, connector_state, i) {
12732                 if (connector_state->crtc != &crtc->base)
12733                         continue;
12734
12735                 connected_sink_compute_bpp(to_intel_connector(connector),
12736                                            pipe_config);
12737         }
12738
12739         return bpp;
12740 }
12741
12742 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12743 {
12744         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12745                         "type: 0x%x flags: 0x%x\n",
12746                 mode->crtc_clock,
12747                 mode->crtc_hdisplay, mode->crtc_hsync_start,
12748                 mode->crtc_hsync_end, mode->crtc_htotal,
12749                 mode->crtc_vdisplay, mode->crtc_vsync_start,
12750                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
12751 }
12752
12753 static inline void
12754 intel_dump_m_n_config(struct intel_crtc_state *pipe_config, char *id,
12755                       unsigned int lane_count, struct intel_link_m_n *m_n)
12756 {
12757         DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12758                       id, lane_count,
12759                       m_n->gmch_m, m_n->gmch_n,
12760                       m_n->link_m, m_n->link_n, m_n->tu);
12761 }
12762
12763 static void intel_dump_pipe_config(struct intel_crtc *crtc,
12764                                    struct intel_crtc_state *pipe_config,
12765                                    const char *context)
12766 {
12767         struct drm_device *dev = crtc->base.dev;
12768         struct drm_i915_private *dev_priv = to_i915(dev);
12769         struct drm_plane *plane;
12770         struct intel_plane *intel_plane;
12771         struct intel_plane_state *state;
12772         struct drm_framebuffer *fb;
12773
12774         DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n",
12775                       crtc->base.base.id, crtc->base.name, context);
12776
12777         DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
12778                       transcoder_name(pipe_config->cpu_transcoder),
12779                       pipe_config->pipe_bpp, pipe_config->dither);
12780
12781         if (pipe_config->has_pch_encoder)
12782                 intel_dump_m_n_config(pipe_config, "fdi",
12783                                       pipe_config->fdi_lanes,
12784                                       &pipe_config->fdi_m_n);
12785
12786         if (intel_crtc_has_dp_encoder(pipe_config)) {
12787                 intel_dump_m_n_config(pipe_config, "dp m_n",
12788                                 pipe_config->lane_count, &pipe_config->dp_m_n);
12789                 if (pipe_config->has_drrs)
12790                         intel_dump_m_n_config(pipe_config, "dp m2_n2",
12791                                               pipe_config->lane_count,
12792                                               &pipe_config->dp_m2_n2);
12793         }
12794
12795         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12796                       pipe_config->has_audio, pipe_config->has_infoframe);
12797
12798         DRM_DEBUG_KMS("requested mode:\n");
12799         drm_mode_debug_printmodeline(&pipe_config->base.mode);
12800         DRM_DEBUG_KMS("adjusted mode:\n");
12801         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12802         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12803         DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d\n",
12804                       pipe_config->port_clock,
12805                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12806
12807         if (INTEL_GEN(dev_priv) >= 9)
12808                 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12809                               crtc->num_scalers,
12810                               pipe_config->scaler_state.scaler_users,
12811                               pipe_config->scaler_state.scaler_id);
12812
12813         if (HAS_GMCH_DISPLAY(dev_priv))
12814                 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12815                               pipe_config->gmch_pfit.control,
12816                               pipe_config->gmch_pfit.pgm_ratios,
12817                               pipe_config->gmch_pfit.lvds_border_bits);
12818         else
12819                 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12820                               pipe_config->pch_pfit.pos,
12821                               pipe_config->pch_pfit.size,
12822                               enableddisabled(pipe_config->pch_pfit.enabled));
12823
12824         DRM_DEBUG_KMS("ips: %i, double wide: %i\n",
12825                       pipe_config->ips_enabled, pipe_config->double_wide);
12826
12827         intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
12828
12829         DRM_DEBUG_KMS("planes on this crtc\n");
12830         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12831                 struct drm_format_name_buf format_name;
12832                 intel_plane = to_intel_plane(plane);
12833                 if (intel_plane->pipe != crtc->pipe)
12834                         continue;
12835
12836                 state = to_intel_plane_state(plane->state);
12837                 fb = state->base.fb;
12838                 if (!fb) {
12839                         DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
12840                                       plane->base.id, plane->name, state->scaler_id);
12841                         continue;
12842                 }
12843
12844                 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d, fb = %ux%u format = %s\n",
12845                               plane->base.id, plane->name,
12846                               fb->base.id, fb->width, fb->height,
12847                               drm_get_format_name(fb->format->format, &format_name));
12848                 if (INTEL_GEN(dev_priv) >= 9)
12849                         DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
12850                                       state->scaler_id,
12851                                       state->base.src.x1 >> 16,
12852                                       state->base.src.y1 >> 16,
12853                                       drm_rect_width(&state->base.src) >> 16,
12854                                       drm_rect_height(&state->base.src) >> 16,
12855                                       state->base.dst.x1, state->base.dst.y1,
12856                                       drm_rect_width(&state->base.dst),
12857                                       drm_rect_height(&state->base.dst));
12858         }
12859 }
12860
12861 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12862 {
12863         struct drm_device *dev = state->dev;
12864         struct drm_connector *connector;
12865         unsigned int used_ports = 0;
12866         unsigned int used_mst_ports = 0;
12867
12868         /*
12869          * Walk the connector list instead of the encoder
12870          * list to detect the problem on ddi platforms
12871          * where there's just one encoder per digital port.
12872          */
12873         drm_for_each_connector(connector, dev) {
12874                 struct drm_connector_state *connector_state;
12875                 struct intel_encoder *encoder;
12876
12877                 connector_state = drm_atomic_get_existing_connector_state(state, connector);
12878                 if (!connector_state)
12879                         connector_state = connector->state;
12880
12881                 if (!connector_state->best_encoder)
12882                         continue;
12883
12884                 encoder = to_intel_encoder(connector_state->best_encoder);
12885
12886                 WARN_ON(!connector_state->crtc);
12887
12888                 switch (encoder->type) {
12889                         unsigned int port_mask;
12890                 case INTEL_OUTPUT_UNKNOWN:
12891                         if (WARN_ON(!HAS_DDI(to_i915(dev))))
12892                                 break;
12893                 case INTEL_OUTPUT_DP:
12894                 case INTEL_OUTPUT_HDMI:
12895                 case INTEL_OUTPUT_EDP:
12896                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12897
12898                         /* the same port mustn't appear more than once */
12899                         if (used_ports & port_mask)
12900                                 return false;
12901
12902                         used_ports |= port_mask;
12903                         break;
12904                 case INTEL_OUTPUT_DP_MST:
12905                         used_mst_ports |=
12906                                 1 << enc_to_mst(&encoder->base)->primary->port;
12907                         break;
12908                 default:
12909                         break;
12910                 }
12911         }
12912
12913         /* can't mix MST and SST/HDMI on the same port */
12914         if (used_ports & used_mst_ports)
12915                 return false;
12916
12917         return true;
12918 }
12919
12920 static void
12921 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12922 {
12923         struct drm_crtc_state tmp_state;
12924         struct intel_crtc_scaler_state scaler_state;
12925         struct intel_dpll_hw_state dpll_hw_state;
12926         struct intel_shared_dpll *shared_dpll;
12927         bool force_thru;
12928
12929         /* FIXME: before the switch to atomic started, a new pipe_config was
12930          * kzalloc'd. Code that depends on any field being zero should be
12931          * fixed, so that the crtc_state can be safely duplicated. For now,
12932          * only fields that are know to not cause problems are preserved. */
12933
12934         tmp_state = crtc_state->base;
12935         scaler_state = crtc_state->scaler_state;
12936         shared_dpll = crtc_state->shared_dpll;
12937         dpll_hw_state = crtc_state->dpll_hw_state;
12938         force_thru = crtc_state->pch_pfit.force_thru;
12939
12940         memset(crtc_state, 0, sizeof *crtc_state);
12941
12942         crtc_state->base = tmp_state;
12943         crtc_state->scaler_state = scaler_state;
12944         crtc_state->shared_dpll = shared_dpll;
12945         crtc_state->dpll_hw_state = dpll_hw_state;
12946         crtc_state->pch_pfit.force_thru = force_thru;
12947 }
12948
12949 static int
12950 intel_modeset_pipe_config(struct drm_crtc *crtc,
12951                           struct intel_crtc_state *pipe_config)
12952 {
12953         struct drm_atomic_state *state = pipe_config->base.state;
12954         struct intel_encoder *encoder;
12955         struct drm_connector *connector;
12956         struct drm_connector_state *connector_state;
12957         int base_bpp, ret = -EINVAL;
12958         int i;
12959         bool retry = true;
12960
12961         clear_intel_crtc_state(pipe_config);
12962
12963         pipe_config->cpu_transcoder =
12964                 (enum transcoder) to_intel_crtc(crtc)->pipe;
12965
12966         /*
12967          * Sanitize sync polarity flags based on requested ones. If neither
12968          * positive or negative polarity is requested, treat this as meaning
12969          * negative polarity.
12970          */
12971         if (!(pipe_config->base.adjusted_mode.flags &
12972               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12973                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12974
12975         if (!(pipe_config->base.adjusted_mode.flags &
12976               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12977                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12978
12979         base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12980                                              pipe_config);
12981         if (base_bpp < 0)
12982                 goto fail;
12983
12984         /*
12985          * Determine the real pipe dimensions. Note that stereo modes can
12986          * increase the actual pipe size due to the frame doubling and
12987          * insertion of additional space for blanks between the frame. This
12988          * is stored in the crtc timings. We use the requested mode to do this
12989          * computation to clearly distinguish it from the adjusted mode, which
12990          * can be changed by the connectors in the below retry loop.
12991          */
12992         drm_crtc_get_hv_timing(&pipe_config->base.mode,
12993                                &pipe_config->pipe_src_w,
12994                                &pipe_config->pipe_src_h);
12995
12996         for_each_connector_in_state(state, connector, connector_state, i) {
12997                 if (connector_state->crtc != crtc)
12998                         continue;
12999
13000                 encoder = to_intel_encoder(connector_state->best_encoder);
13001
13002                 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
13003                         DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
13004                         goto fail;
13005                 }
13006
13007                 /*
13008                  * Determine output_types before calling the .compute_config()
13009                  * hooks so that the hooks can use this information safely.
13010                  */
13011                 pipe_config->output_types |= 1 << encoder->type;
13012         }
13013
13014 encoder_retry:
13015         /* Ensure the port clock defaults are reset when retrying. */
13016         pipe_config->port_clock = 0;
13017         pipe_config->pixel_multiplier = 1;
13018
13019         /* Fill in default crtc timings, allow encoders to overwrite them. */
13020         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
13021                               CRTC_STEREO_DOUBLE);
13022
13023         /* Pass our mode to the connectors and the CRTC to give them a chance to
13024          * adjust it according to limitations or connector properties, and also
13025          * a chance to reject the mode entirely.
13026          */
13027         for_each_connector_in_state(state, connector, connector_state, i) {
13028                 if (connector_state->crtc != crtc)
13029                         continue;
13030
13031                 encoder = to_intel_encoder(connector_state->best_encoder);
13032
13033                 if (!(encoder->compute_config(encoder, pipe_config, connector_state))) {
13034                         DRM_DEBUG_KMS("Encoder config failure\n");
13035                         goto fail;
13036                 }
13037         }
13038
13039         /* Set default port clock if not overwritten by the encoder. Needs to be
13040          * done afterwards in case the encoder adjusts the mode. */
13041         if (!pipe_config->port_clock)
13042                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
13043                         * pipe_config->pixel_multiplier;
13044
13045         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
13046         if (ret < 0) {
13047                 DRM_DEBUG_KMS("CRTC fixup failed\n");
13048                 goto fail;
13049         }
13050
13051         if (ret == RETRY) {
13052                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
13053                         ret = -EINVAL;
13054                         goto fail;
13055                 }
13056
13057                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
13058                 retry = false;
13059                 goto encoder_retry;
13060         }
13061
13062         /* Dithering seems to not pass-through bits correctly when it should, so
13063          * only enable it on 6bpc panels. */
13064         pipe_config->dither = pipe_config->pipe_bpp == 6*3;
13065         DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
13066                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
13067
13068 fail:
13069         return ret;
13070 }
13071
13072 static void
13073 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
13074 {
13075         struct drm_crtc *crtc;
13076         struct drm_crtc_state *crtc_state;
13077         int i;
13078
13079         /* Double check state. */
13080         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13081                 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
13082
13083                 /* Update hwmode for vblank functions */
13084                 if (crtc->state->active)
13085                         crtc->hwmode = crtc->state->adjusted_mode;
13086                 else
13087                         crtc->hwmode.crtc_clock = 0;
13088
13089                 /*
13090                  * Update legacy state to satisfy fbc code. This can
13091                  * be removed when fbc uses the atomic state.
13092                  */
13093                 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
13094                         struct drm_plane_state *plane_state = crtc->primary->state;
13095
13096                         crtc->primary->fb = plane_state->fb;
13097                         crtc->x = plane_state->src_x >> 16;
13098                         crtc->y = plane_state->src_y >> 16;
13099                 }
13100         }
13101 }
13102
13103 static bool intel_fuzzy_clock_check(int clock1, int clock2)
13104 {
13105         int diff;
13106
13107         if (clock1 == clock2)
13108                 return true;
13109
13110         if (!clock1 || !clock2)
13111                 return false;
13112
13113         diff = abs(clock1 - clock2);
13114
13115         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
13116                 return true;
13117
13118         return false;
13119 }
13120
13121 static bool
13122 intel_compare_m_n(unsigned int m, unsigned int n,
13123                   unsigned int m2, unsigned int n2,
13124                   bool exact)
13125 {
13126         if (m == m2 && n == n2)
13127                 return true;
13128
13129         if (exact || !m || !n || !m2 || !n2)
13130                 return false;
13131
13132         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
13133
13134         if (n > n2) {
13135                 while (n > n2) {
13136                         m2 <<= 1;
13137                         n2 <<= 1;
13138                 }
13139         } else if (n < n2) {
13140                 while (n < n2) {
13141                         m <<= 1;
13142                         n <<= 1;
13143                 }
13144         }
13145
13146         if (n != n2)
13147                 return false;
13148
13149         return intel_fuzzy_clock_check(m, m2);
13150 }
13151
13152 static bool
13153 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
13154                        struct intel_link_m_n *m2_n2,
13155                        bool adjust)
13156 {
13157         if (m_n->tu == m2_n2->tu &&
13158             intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
13159                               m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
13160             intel_compare_m_n(m_n->link_m, m_n->link_n,
13161                               m2_n2->link_m, m2_n2->link_n, !adjust)) {
13162                 if (adjust)
13163                         *m2_n2 = *m_n;
13164
13165                 return true;
13166         }
13167
13168         return false;
13169 }
13170
13171 static void __printf(3, 4)
13172 pipe_config_err(bool adjust, const char *name, const char *format, ...)
13173 {
13174         char *level;
13175         unsigned int category;
13176         struct va_format vaf;
13177         va_list args;
13178
13179         if (adjust) {
13180                 level = KERN_DEBUG;
13181                 category = DRM_UT_KMS;
13182         } else {
13183                 level = KERN_ERR;
13184                 category = DRM_UT_NONE;
13185         }
13186
13187         va_start(args, format);
13188         vaf.fmt = format;
13189         vaf.va = &args;
13190
13191         drm_printk(level, category, "mismatch in %s %pV", name, &vaf);
13192
13193         va_end(args);
13194 }
13195
13196 static bool
13197 intel_pipe_config_compare(struct drm_i915_private *dev_priv,
13198                           struct intel_crtc_state *current_config,
13199                           struct intel_crtc_state *pipe_config,
13200                           bool adjust)
13201 {
13202         bool ret = true;
13203
13204 #define PIPE_CONF_CHECK_X(name) \
13205         if (current_config->name != pipe_config->name) { \
13206                 pipe_config_err(adjust, __stringify(name), \
13207                           "(expected 0x%08x, found 0x%08x)\n", \
13208                           current_config->name, \
13209                           pipe_config->name); \
13210                 ret = false; \
13211         }
13212
13213 #define PIPE_CONF_CHECK_I(name) \
13214         if (current_config->name != pipe_config->name) { \
13215                 pipe_config_err(adjust, __stringify(name), \
13216                           "(expected %i, found %i)\n", \
13217                           current_config->name, \
13218                           pipe_config->name); \
13219                 ret = false; \
13220         }
13221
13222 #define PIPE_CONF_CHECK_P(name) \
13223         if (current_config->name != pipe_config->name) { \
13224                 pipe_config_err(adjust, __stringify(name), \
13225                           "(expected %p, found %p)\n", \
13226                           current_config->name, \
13227                           pipe_config->name); \
13228                 ret = false; \
13229         }
13230
13231 #define PIPE_CONF_CHECK_M_N(name) \
13232         if (!intel_compare_link_m_n(&current_config->name, \
13233                                     &pipe_config->name,\
13234                                     adjust)) { \
13235                 pipe_config_err(adjust, __stringify(name), \
13236                           "(expected tu %i gmch %i/%i link %i/%i, " \
13237                           "found tu %i, gmch %i/%i link %i/%i)\n", \
13238                           current_config->name.tu, \
13239                           current_config->name.gmch_m, \
13240                           current_config->name.gmch_n, \
13241                           current_config->name.link_m, \
13242                           current_config->name.link_n, \
13243                           pipe_config->name.tu, \
13244                           pipe_config->name.gmch_m, \
13245                           pipe_config->name.gmch_n, \
13246                           pipe_config->name.link_m, \
13247                           pipe_config->name.link_n); \
13248                 ret = false; \
13249         }
13250
13251 /* This is required for BDW+ where there is only one set of registers for
13252  * switching between high and low RR.
13253  * This macro can be used whenever a comparison has to be made between one
13254  * hw state and multiple sw state variables.
13255  */
13256 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
13257         if (!intel_compare_link_m_n(&current_config->name, \
13258                                     &pipe_config->name, adjust) && \
13259             !intel_compare_link_m_n(&current_config->alt_name, \
13260                                     &pipe_config->name, adjust)) { \
13261                 pipe_config_err(adjust, __stringify(name), \
13262                           "(expected tu %i gmch %i/%i link %i/%i, " \
13263                           "or tu %i gmch %i/%i link %i/%i, " \
13264                           "found tu %i, gmch %i/%i link %i/%i)\n", \
13265                           current_config->name.tu, \
13266                           current_config->name.gmch_m, \
13267                           current_config->name.gmch_n, \
13268                           current_config->name.link_m, \
13269                           current_config->name.link_n, \
13270                           current_config->alt_name.tu, \
13271                           current_config->alt_name.gmch_m, \
13272                           current_config->alt_name.gmch_n, \
13273                           current_config->alt_name.link_m, \
13274                           current_config->alt_name.link_n, \
13275                           pipe_config->name.tu, \
13276                           pipe_config->name.gmch_m, \
13277                           pipe_config->name.gmch_n, \
13278                           pipe_config->name.link_m, \
13279                           pipe_config->name.link_n); \
13280                 ret = false; \
13281         }
13282
13283 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
13284         if ((current_config->name ^ pipe_config->name) & (mask)) { \
13285                 pipe_config_err(adjust, __stringify(name), \
13286                           "(%x) (expected %i, found %i)\n", \
13287                           (mask), \
13288                           current_config->name & (mask), \
13289                           pipe_config->name & (mask)); \
13290                 ret = false; \
13291         }
13292
13293 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
13294         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
13295                 pipe_config_err(adjust, __stringify(name), \
13296                           "(expected %i, found %i)\n", \
13297                           current_config->name, \
13298                           pipe_config->name); \
13299                 ret = false; \
13300         }
13301
13302 #define PIPE_CONF_QUIRK(quirk)  \
13303         ((current_config->quirks | pipe_config->quirks) & (quirk))
13304
13305         PIPE_CONF_CHECK_I(cpu_transcoder);
13306
13307         PIPE_CONF_CHECK_I(has_pch_encoder);
13308         PIPE_CONF_CHECK_I(fdi_lanes);
13309         PIPE_CONF_CHECK_M_N(fdi_m_n);
13310
13311         PIPE_CONF_CHECK_I(lane_count);
13312         PIPE_CONF_CHECK_X(lane_lat_optim_mask);
13313
13314         if (INTEL_GEN(dev_priv) < 8) {
13315                 PIPE_CONF_CHECK_M_N(dp_m_n);
13316
13317                 if (current_config->has_drrs)
13318                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
13319         } else
13320                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
13321
13322         PIPE_CONF_CHECK_X(output_types);
13323
13324         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
13325         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
13326         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
13327         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
13328         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
13329         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
13330
13331         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
13332         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
13333         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
13334         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
13335         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
13336         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
13337
13338         PIPE_CONF_CHECK_I(pixel_multiplier);
13339         PIPE_CONF_CHECK_I(has_hdmi_sink);
13340         if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
13341             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13342                 PIPE_CONF_CHECK_I(limited_color_range);
13343         PIPE_CONF_CHECK_I(has_infoframe);
13344
13345         PIPE_CONF_CHECK_I(has_audio);
13346
13347         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13348                               DRM_MODE_FLAG_INTERLACE);
13349
13350         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
13351                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13352                                       DRM_MODE_FLAG_PHSYNC);
13353                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13354                                       DRM_MODE_FLAG_NHSYNC);
13355                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13356                                       DRM_MODE_FLAG_PVSYNC);
13357                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13358                                       DRM_MODE_FLAG_NVSYNC);
13359         }
13360
13361         PIPE_CONF_CHECK_X(gmch_pfit.control);
13362         /* pfit ratios are autocomputed by the hw on gen4+ */
13363         if (INTEL_GEN(dev_priv) < 4)
13364                 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
13365         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
13366
13367         if (!adjust) {
13368                 PIPE_CONF_CHECK_I(pipe_src_w);
13369                 PIPE_CONF_CHECK_I(pipe_src_h);
13370
13371                 PIPE_CONF_CHECK_I(pch_pfit.enabled);
13372                 if (current_config->pch_pfit.enabled) {
13373                         PIPE_CONF_CHECK_X(pch_pfit.pos);
13374                         PIPE_CONF_CHECK_X(pch_pfit.size);
13375                 }
13376
13377                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
13378         }
13379
13380         /* BDW+ don't expose a synchronous way to read the state */
13381         if (IS_HASWELL(dev_priv))
13382                 PIPE_CONF_CHECK_I(ips_enabled);
13383
13384         PIPE_CONF_CHECK_I(double_wide);
13385
13386         PIPE_CONF_CHECK_P(shared_dpll);
13387         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
13388         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
13389         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
13390         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
13391         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
13392         PIPE_CONF_CHECK_X(dpll_hw_state.spll);
13393         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
13394         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
13395         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
13396
13397         PIPE_CONF_CHECK_X(dsi_pll.ctrl);
13398         PIPE_CONF_CHECK_X(dsi_pll.div);
13399
13400         if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
13401                 PIPE_CONF_CHECK_I(pipe_bpp);
13402
13403         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
13404         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
13405
13406 #undef PIPE_CONF_CHECK_X
13407 #undef PIPE_CONF_CHECK_I
13408 #undef PIPE_CONF_CHECK_P
13409 #undef PIPE_CONF_CHECK_FLAGS
13410 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
13411 #undef PIPE_CONF_QUIRK
13412
13413         return ret;
13414 }
13415
13416 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
13417                                            const struct intel_crtc_state *pipe_config)
13418 {
13419         if (pipe_config->has_pch_encoder) {
13420                 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
13421                                                             &pipe_config->fdi_m_n);
13422                 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
13423
13424                 /*
13425                  * FDI already provided one idea for the dotclock.
13426                  * Yell if the encoder disagrees.
13427                  */
13428                 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
13429                      "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
13430                      fdi_dotclock, dotclock);
13431         }
13432 }
13433
13434 static void verify_wm_state(struct drm_crtc *crtc,
13435                             struct drm_crtc_state *new_state)
13436 {
13437         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
13438         struct skl_ddb_allocation hw_ddb, *sw_ddb;
13439         struct skl_pipe_wm hw_wm, *sw_wm;
13440         struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
13441         struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
13442         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13443         const enum pipe pipe = intel_crtc->pipe;
13444         int plane, level, max_level = ilk_wm_max_level(dev_priv);
13445
13446         if (INTEL_GEN(dev_priv) < 9 || !new_state->active)
13447                 return;
13448
13449         skl_pipe_wm_get_hw_state(crtc, &hw_wm);
13450         sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal;
13451
13452         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
13453         sw_ddb = &dev_priv->wm.skl_hw.ddb;
13454
13455         /* planes */
13456         for_each_universal_plane(dev_priv, pipe, plane) {
13457                 hw_plane_wm = &hw_wm.planes[plane];
13458                 sw_plane_wm = &sw_wm->planes[plane];
13459
13460                 /* Watermarks */
13461                 for (level = 0; level <= max_level; level++) {
13462                         if (skl_wm_level_equals(&hw_plane_wm->wm[level],
13463                                                 &sw_plane_wm->wm[level]))
13464                                 continue;
13465
13466                         DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
13467                                   pipe_name(pipe), plane + 1, level,
13468                                   sw_plane_wm->wm[level].plane_en,
13469                                   sw_plane_wm->wm[level].plane_res_b,
13470                                   sw_plane_wm->wm[level].plane_res_l,
13471                                   hw_plane_wm->wm[level].plane_en,
13472                                   hw_plane_wm->wm[level].plane_res_b,
13473                                   hw_plane_wm->wm[level].plane_res_l);
13474                 }
13475
13476                 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
13477                                          &sw_plane_wm->trans_wm)) {
13478                         DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
13479                                   pipe_name(pipe), plane + 1,
13480                                   sw_plane_wm->trans_wm.plane_en,
13481                                   sw_plane_wm->trans_wm.plane_res_b,
13482                                   sw_plane_wm->trans_wm.plane_res_l,
13483                                   hw_plane_wm->trans_wm.plane_en,
13484                                   hw_plane_wm->trans_wm.plane_res_b,
13485                                   hw_plane_wm->trans_wm.plane_res_l);
13486                 }
13487
13488                 /* DDB */
13489                 hw_ddb_entry = &hw_ddb.plane[pipe][plane];
13490                 sw_ddb_entry = &sw_ddb->plane[pipe][plane];
13491
13492                 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
13493                         DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
13494                                   pipe_name(pipe), plane + 1,
13495                                   sw_ddb_entry->start, sw_ddb_entry->end,
13496                                   hw_ddb_entry->start, hw_ddb_entry->end);
13497                 }
13498         }
13499
13500         /*
13501          * cursor
13502          * If the cursor plane isn't active, we may not have updated it's ddb
13503          * allocation. In that case since the ddb allocation will be updated
13504          * once the plane becomes visible, we can skip this check
13505          */
13506         if (intel_crtc->cursor_addr) {
13507                 hw_plane_wm = &hw_wm.planes[PLANE_CURSOR];
13508                 sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
13509
13510                 /* Watermarks */
13511                 for (level = 0; level <= max_level; level++) {
13512                         if (skl_wm_level_equals(&hw_plane_wm->wm[level],
13513                                                 &sw_plane_wm->wm[level]))
13514                                 continue;
13515
13516                         DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
13517                                   pipe_name(pipe), level,
13518                                   sw_plane_wm->wm[level].plane_en,
13519                                   sw_plane_wm->wm[level].plane_res_b,
13520                                   sw_plane_wm->wm[level].plane_res_l,
13521                                   hw_plane_wm->wm[level].plane_en,
13522                                   hw_plane_wm->wm[level].plane_res_b,
13523                                   hw_plane_wm->wm[level].plane_res_l);
13524                 }
13525
13526                 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
13527                                          &sw_plane_wm->trans_wm)) {
13528                         DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
13529                                   pipe_name(pipe),
13530                                   sw_plane_wm->trans_wm.plane_en,
13531                                   sw_plane_wm->trans_wm.plane_res_b,
13532                                   sw_plane_wm->trans_wm.plane_res_l,
13533                                   hw_plane_wm->trans_wm.plane_en,
13534                                   hw_plane_wm->trans_wm.plane_res_b,
13535                                   hw_plane_wm->trans_wm.plane_res_l);
13536                 }
13537
13538                 /* DDB */
13539                 hw_ddb_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
13540                 sw_ddb_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
13541
13542                 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
13543                         DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
13544                                   pipe_name(pipe),
13545                                   sw_ddb_entry->start, sw_ddb_entry->end,
13546                                   hw_ddb_entry->start, hw_ddb_entry->end);
13547                 }
13548         }
13549 }
13550
13551 static void
13552 verify_connector_state(struct drm_device *dev,
13553                        struct drm_atomic_state *state,
13554                        struct drm_crtc *crtc)
13555 {
13556         struct drm_connector *connector;
13557         struct drm_connector_state *old_conn_state;
13558         int i;
13559
13560         for_each_connector_in_state(state, connector, old_conn_state, i) {
13561                 struct drm_encoder *encoder = connector->encoder;
13562                 struct drm_connector_state *state = connector->state;
13563
13564                 if (state->crtc != crtc)
13565                         continue;
13566
13567                 intel_connector_verify_state(to_intel_connector(connector));
13568
13569                 I915_STATE_WARN(state->best_encoder != encoder,
13570                      "connector's atomic encoder doesn't match legacy encoder\n");
13571         }
13572 }
13573
13574 static void
13575 verify_encoder_state(struct drm_device *dev)
13576 {
13577         struct intel_encoder *encoder;
13578         struct intel_connector *connector;
13579
13580         for_each_intel_encoder(dev, encoder) {
13581                 bool enabled = false;
13582                 enum pipe pipe;
13583
13584                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
13585                               encoder->base.base.id,
13586                               encoder->base.name);
13587
13588                 for_each_intel_connector(dev, connector) {
13589                         if (connector->base.state->best_encoder != &encoder->base)
13590                                 continue;
13591                         enabled = true;
13592
13593                         I915_STATE_WARN(connector->base.state->crtc !=
13594                                         encoder->base.crtc,
13595                              "connector's crtc doesn't match encoder crtc\n");
13596                 }
13597
13598                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
13599                      "encoder's enabled state mismatch "
13600                      "(expected %i, found %i)\n",
13601                      !!encoder->base.crtc, enabled);
13602
13603                 if (!encoder->base.crtc) {
13604                         bool active;
13605
13606                         active = encoder->get_hw_state(encoder, &pipe);
13607                         I915_STATE_WARN(active,
13608                              "encoder detached but still enabled on pipe %c.\n",
13609                              pipe_name(pipe));
13610                 }
13611         }
13612 }
13613
13614 static void
13615 verify_crtc_state(struct drm_crtc *crtc,
13616                   struct drm_crtc_state *old_crtc_state,
13617                   struct drm_crtc_state *new_crtc_state)
13618 {
13619         struct drm_device *dev = crtc->dev;
13620         struct drm_i915_private *dev_priv = to_i915(dev);
13621         struct intel_encoder *encoder;
13622         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13623         struct intel_crtc_state *pipe_config, *sw_config;
13624         struct drm_atomic_state *old_state;
13625         bool active;
13626
13627         old_state = old_crtc_state->state;
13628         __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
13629         pipe_config = to_intel_crtc_state(old_crtc_state);
13630         memset(pipe_config, 0, sizeof(*pipe_config));
13631         pipe_config->base.crtc = crtc;
13632         pipe_config->base.state = old_state;
13633
13634         DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
13635
13636         active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
13637
13638         /* hw state is inconsistent with the pipe quirk */
13639         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
13640             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
13641                 active = new_crtc_state->active;
13642
13643         I915_STATE_WARN(new_crtc_state->active != active,
13644              "crtc active state doesn't match with hw state "
13645              "(expected %i, found %i)\n", new_crtc_state->active, active);
13646
13647         I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
13648              "transitional active state does not match atomic hw state "
13649              "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
13650
13651         for_each_encoder_on_crtc(dev, crtc, encoder) {
13652                 enum pipe pipe;
13653
13654                 active = encoder->get_hw_state(encoder, &pipe);
13655                 I915_STATE_WARN(active != new_crtc_state->active,
13656                         "[ENCODER:%i] active %i with crtc active %i\n",
13657                         encoder->base.base.id, active, new_crtc_state->active);
13658
13659                 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
13660                                 "Encoder connected to wrong pipe %c\n",
13661                                 pipe_name(pipe));
13662
13663                 if (active) {
13664                         pipe_config->output_types |= 1 << encoder->type;
13665                         encoder->get_config(encoder, pipe_config);
13666                 }
13667         }
13668
13669         if (!new_crtc_state->active)
13670                 return;
13671
13672         intel_pipe_config_sanity_check(dev_priv, pipe_config);
13673
13674         sw_config = to_intel_crtc_state(crtc->state);
13675         if (!intel_pipe_config_compare(dev_priv, sw_config,
13676                                        pipe_config, false)) {
13677                 I915_STATE_WARN(1, "pipe state doesn't match!\n");
13678                 intel_dump_pipe_config(intel_crtc, pipe_config,
13679                                        "[hw state]");
13680                 intel_dump_pipe_config(intel_crtc, sw_config,
13681                                        "[sw state]");
13682         }
13683 }
13684
13685 static void
13686 verify_single_dpll_state(struct drm_i915_private *dev_priv,
13687                          struct intel_shared_dpll *pll,
13688                          struct drm_crtc *crtc,
13689                          struct drm_crtc_state *new_state)
13690 {
13691         struct intel_dpll_hw_state dpll_hw_state;
13692         unsigned crtc_mask;
13693         bool active;
13694
13695         memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
13696
13697         DRM_DEBUG_KMS("%s\n", pll->name);
13698
13699         active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
13700
13701         if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
13702                 I915_STATE_WARN(!pll->on && pll->active_mask,
13703                      "pll in active use but not on in sw tracking\n");
13704                 I915_STATE_WARN(pll->on && !pll->active_mask,
13705                      "pll is on but not used by any active crtc\n");
13706                 I915_STATE_WARN(pll->on != active,
13707                      "pll on state mismatch (expected %i, found %i)\n",
13708                      pll->on, active);
13709         }
13710
13711         if (!crtc) {
13712                 I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask,
13713                                 "more active pll users than references: %x vs %x\n",
13714                                 pll->active_mask, pll->state.crtc_mask);
13715
13716                 return;
13717         }
13718
13719         crtc_mask = 1 << drm_crtc_index(crtc);
13720
13721         if (new_state->active)
13722                 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
13723                                 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
13724                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
13725         else
13726                 I915_STATE_WARN(pll->active_mask & crtc_mask,
13727                                 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
13728                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
13729
13730         I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),
13731                         "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
13732                         crtc_mask, pll->state.crtc_mask);
13733
13734         I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
13735                                           &dpll_hw_state,
13736                                           sizeof(dpll_hw_state)),
13737                         "pll hw state mismatch\n");
13738 }
13739
13740 static void
13741 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
13742                          struct drm_crtc_state *old_crtc_state,
13743                          struct drm_crtc_state *new_crtc_state)
13744 {
13745         struct drm_i915_private *dev_priv = to_i915(dev);
13746         struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
13747         struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
13748
13749         if (new_state->shared_dpll)
13750                 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
13751
13752         if (old_state->shared_dpll &&
13753             old_state->shared_dpll != new_state->shared_dpll) {
13754                 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
13755                 struct intel_shared_dpll *pll = old_state->shared_dpll;
13756
13757                 I915_STATE_WARN(pll->active_mask & crtc_mask,
13758                                 "pll active mismatch (didn't expect pipe %c in active mask)\n",
13759                                 pipe_name(drm_crtc_index(crtc)));
13760                 I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,
13761                                 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
13762                                 pipe_name(drm_crtc_index(crtc)));
13763         }
13764 }
13765
13766 static void
13767 intel_modeset_verify_crtc(struct drm_crtc *crtc,
13768                           struct drm_atomic_state *state,
13769                           struct drm_crtc_state *old_state,
13770                           struct drm_crtc_state *new_state)
13771 {
13772         if (!needs_modeset(new_state) &&
13773             !to_intel_crtc_state(new_state)->update_pipe)
13774                 return;
13775
13776         verify_wm_state(crtc, new_state);
13777         verify_connector_state(crtc->dev, state, crtc);
13778         verify_crtc_state(crtc, old_state, new_state);
13779         verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
13780 }
13781
13782 static void
13783 verify_disabled_dpll_state(struct drm_device *dev)
13784 {
13785         struct drm_i915_private *dev_priv = to_i915(dev);
13786         int i;
13787
13788         for (i = 0; i < dev_priv->num_shared_dpll; i++)
13789                 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
13790 }
13791
13792 static void
13793 intel_modeset_verify_disabled(struct drm_device *dev,
13794                               struct drm_atomic_state *state)
13795 {
13796         verify_encoder_state(dev);
13797         verify_connector_state(dev, state, NULL);
13798         verify_disabled_dpll_state(dev);
13799 }
13800
13801 static void update_scanline_offset(struct intel_crtc *crtc)
13802 {
13803         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13804
13805         /*
13806          * The scanline counter increments at the leading edge of hsync.
13807          *
13808          * On most platforms it starts counting from vtotal-1 on the
13809          * first active line. That means the scanline counter value is
13810          * always one less than what we would expect. Ie. just after
13811          * start of vblank, which also occurs at start of hsync (on the
13812          * last active line), the scanline counter will read vblank_start-1.
13813          *
13814          * On gen2 the scanline counter starts counting from 1 instead
13815          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13816          * to keep the value positive), instead of adding one.
13817          *
13818          * On HSW+ the behaviour of the scanline counter depends on the output
13819          * type. For DP ports it behaves like most other platforms, but on HDMI
13820          * there's an extra 1 line difference. So we need to add two instead of
13821          * one to the value.
13822          */
13823         if (IS_GEN2(dev_priv)) {
13824                 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
13825                 int vtotal;
13826
13827                 vtotal = adjusted_mode->crtc_vtotal;
13828                 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
13829                         vtotal /= 2;
13830
13831                 crtc->scanline_offset = vtotal - 1;
13832         } else if (HAS_DDI(dev_priv) &&
13833                    intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
13834                 crtc->scanline_offset = 2;
13835         } else
13836                 crtc->scanline_offset = 1;
13837 }
13838
13839 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
13840 {
13841         struct drm_device *dev = state->dev;
13842         struct drm_i915_private *dev_priv = to_i915(dev);
13843         struct drm_crtc *crtc;
13844         struct drm_crtc_state *crtc_state;
13845         int i;
13846
13847         if (!dev_priv->display.crtc_compute_clock)
13848                 return;
13849
13850         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13851                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13852                 struct intel_shared_dpll *old_dpll =
13853                         to_intel_crtc_state(crtc->state)->shared_dpll;
13854
13855                 if (!needs_modeset(crtc_state))
13856                         continue;
13857
13858                 to_intel_crtc_state(crtc_state)->shared_dpll = NULL;
13859
13860                 if (!old_dpll)
13861                         continue;
13862
13863                 intel_release_shared_dpll(old_dpll, intel_crtc, state);
13864         }
13865 }
13866
13867 /*
13868  * This implements the workaround described in the "notes" section of the mode
13869  * set sequence documentation. When going from no pipes or single pipe to
13870  * multiple pipes, and planes are enabled after the pipe, we need to wait at
13871  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13872  */
13873 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13874 {
13875         struct drm_crtc_state *crtc_state;
13876         struct intel_crtc *intel_crtc;
13877         struct drm_crtc *crtc;
13878         struct intel_crtc_state *first_crtc_state = NULL;
13879         struct intel_crtc_state *other_crtc_state = NULL;
13880         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13881         int i;
13882
13883         /* look at all crtc's that are going to be enabled in during modeset */
13884         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13885                 intel_crtc = to_intel_crtc(crtc);
13886
13887                 if (!crtc_state->active || !needs_modeset(crtc_state))
13888                         continue;
13889
13890                 if (first_crtc_state) {
13891                         other_crtc_state = to_intel_crtc_state(crtc_state);
13892                         break;
13893                 } else {
13894                         first_crtc_state = to_intel_crtc_state(crtc_state);
13895                         first_pipe = intel_crtc->pipe;
13896                 }
13897         }
13898
13899         /* No workaround needed? */
13900         if (!first_crtc_state)
13901                 return 0;
13902
13903         /* w/a possibly needed, check how many crtc's are already enabled. */
13904         for_each_intel_crtc(state->dev, intel_crtc) {
13905                 struct intel_crtc_state *pipe_config;
13906
13907                 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13908                 if (IS_ERR(pipe_config))
13909                         return PTR_ERR(pipe_config);
13910
13911                 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13912
13913                 if (!pipe_config->base.active ||
13914                     needs_modeset(&pipe_config->base))
13915                         continue;
13916
13917                 /* 2 or more enabled crtcs means no need for w/a */
13918                 if (enabled_pipe != INVALID_PIPE)
13919                         return 0;
13920
13921                 enabled_pipe = intel_crtc->pipe;
13922         }
13923
13924         if (enabled_pipe != INVALID_PIPE)
13925                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13926         else if (other_crtc_state)
13927                 other_crtc_state->hsw_workaround_pipe = first_pipe;
13928
13929         return 0;
13930 }
13931
13932 static int intel_lock_all_pipes(struct drm_atomic_state *state)
13933 {
13934         struct drm_crtc *crtc;
13935
13936         /* Add all pipes to the state */
13937         for_each_crtc(state->dev, crtc) {
13938                 struct drm_crtc_state *crtc_state;
13939
13940                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13941                 if (IS_ERR(crtc_state))
13942                         return PTR_ERR(crtc_state);
13943         }
13944
13945         return 0;
13946 }
13947
13948 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13949 {
13950         struct drm_crtc *crtc;
13951
13952         /*
13953          * Add all pipes to the state, and force
13954          * a modeset on all the active ones.
13955          */
13956         for_each_crtc(state->dev, crtc) {
13957                 struct drm_crtc_state *crtc_state;
13958                 int ret;
13959
13960                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13961                 if (IS_ERR(crtc_state))
13962                         return PTR_ERR(crtc_state);
13963
13964                 if (!crtc_state->active || needs_modeset(crtc_state))
13965                         continue;
13966
13967                 crtc_state->mode_changed = true;
13968
13969                 ret = drm_atomic_add_affected_connectors(state, crtc);
13970                 if (ret)
13971                         return ret;
13972
13973                 ret = drm_atomic_add_affected_planes(state, crtc);
13974                 if (ret)
13975                         return ret;
13976         }
13977
13978         return 0;
13979 }
13980
13981 static int intel_modeset_checks(struct drm_atomic_state *state)
13982 {
13983         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13984         struct drm_i915_private *dev_priv = to_i915(state->dev);
13985         struct drm_crtc *crtc;
13986         struct drm_crtc_state *crtc_state;
13987         int ret = 0, i;
13988
13989         if (!check_digital_port_conflicts(state)) {
13990                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13991                 return -EINVAL;
13992         }
13993
13994         intel_state->modeset = true;
13995         intel_state->active_crtcs = dev_priv->active_crtcs;
13996
13997         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13998                 if (crtc_state->active)
13999                         intel_state->active_crtcs |= 1 << i;
14000                 else
14001                         intel_state->active_crtcs &= ~(1 << i);
14002
14003                 if (crtc_state->active != crtc->state->active)
14004                         intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
14005         }
14006
14007         /*
14008          * See if the config requires any additional preparation, e.g.
14009          * to adjust global state with pipes off.  We need to do this
14010          * here so we can get the modeset_pipe updated config for the new
14011          * mode set on this crtc.  For other crtcs we need to use the
14012          * adjusted_mode bits in the crtc directly.
14013          */
14014         if (dev_priv->display.modeset_calc_cdclk) {
14015                 if (!intel_state->cdclk_pll_vco)
14016                         intel_state->cdclk_pll_vco = dev_priv->cdclk_pll.vco;
14017                 if (!intel_state->cdclk_pll_vco)
14018                         intel_state->cdclk_pll_vco = dev_priv->skl_preferred_vco_freq;
14019
14020                 ret = dev_priv->display.modeset_calc_cdclk(state);
14021                 if (ret < 0)
14022                         return ret;
14023
14024                 /*
14025                  * Writes to dev_priv->atomic_cdclk_freq must protected by
14026                  * holding all the crtc locks, even if we don't end up
14027                  * touching the hardware
14028                  */
14029                 if (intel_state->cdclk != dev_priv->atomic_cdclk_freq) {
14030                         ret = intel_lock_all_pipes(state);
14031                         if (ret < 0)
14032                                 return ret;
14033                 }
14034
14035                 /* All pipes must be switched off while we change the cdclk. */
14036                 if (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
14037                     intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco) {
14038                         ret = intel_modeset_all_pipes(state);
14039                         if (ret < 0)
14040                                 return ret;
14041                 }
14042
14043                 DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n",
14044                               intel_state->cdclk, intel_state->dev_cdclk);
14045         } else {
14046                 to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq;
14047         }
14048
14049         intel_modeset_clear_plls(state);
14050
14051         if (IS_HASWELL(dev_priv))
14052                 return haswell_mode_set_planes_workaround(state);
14053
14054         return 0;
14055 }
14056
14057 /*
14058  * Handle calculation of various watermark data at the end of the atomic check
14059  * phase.  The code here should be run after the per-crtc and per-plane 'check'
14060  * handlers to ensure that all derived state has been updated.
14061  */
14062 static int calc_watermark_data(struct drm_atomic_state *state)
14063 {
14064         struct drm_device *dev = state->dev;
14065         struct drm_i915_private *dev_priv = to_i915(dev);
14066
14067         /* Is there platform-specific watermark information to calculate? */
14068         if (dev_priv->display.compute_global_watermarks)
14069                 return dev_priv->display.compute_global_watermarks(state);
14070
14071         return 0;
14072 }
14073
14074 /**
14075  * intel_atomic_check - validate state object
14076  * @dev: drm device
14077  * @state: state to validate
14078  */
14079 static int intel_atomic_check(struct drm_device *dev,
14080                               struct drm_atomic_state *state)
14081 {
14082         struct drm_i915_private *dev_priv = to_i915(dev);
14083         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14084         struct drm_crtc *crtc;
14085         struct drm_crtc_state *crtc_state;
14086         int ret, i;
14087         bool any_ms = false;
14088
14089         ret = drm_atomic_helper_check_modeset(dev, state);
14090         if (ret)
14091                 return ret;
14092
14093         for_each_crtc_in_state(state, crtc, crtc_state, i) {
14094                 struct intel_crtc_state *pipe_config =
14095                         to_intel_crtc_state(crtc_state);
14096
14097                 /* Catch I915_MODE_FLAG_INHERITED */
14098                 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
14099                         crtc_state->mode_changed = true;
14100
14101                 if (!needs_modeset(crtc_state))
14102                         continue;
14103
14104                 if (!crtc_state->enable) {
14105                         any_ms = true;
14106                         continue;
14107                 }
14108
14109                 /* FIXME: For only active_changed we shouldn't need to do any
14110                  * state recomputation at all. */
14111
14112                 ret = drm_atomic_add_affected_connectors(state, crtc);
14113                 if (ret)
14114                         return ret;
14115
14116                 ret = intel_modeset_pipe_config(crtc, pipe_config);
14117                 if (ret) {
14118                         intel_dump_pipe_config(to_intel_crtc(crtc),
14119                                                pipe_config, "[failed]");
14120                         return ret;
14121                 }
14122
14123                 if (i915.fastboot &&
14124                     intel_pipe_config_compare(dev_priv,
14125                                         to_intel_crtc_state(crtc->state),
14126                                         pipe_config, true)) {
14127                         crtc_state->mode_changed = false;
14128                         to_intel_crtc_state(crtc_state)->update_pipe = true;
14129                 }
14130
14131                 if (needs_modeset(crtc_state))
14132                         any_ms = true;
14133
14134                 ret = drm_atomic_add_affected_planes(state, crtc);
14135                 if (ret)
14136                         return ret;
14137
14138                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
14139                                        needs_modeset(crtc_state) ?
14140                                        "[modeset]" : "[fastset]");
14141         }
14142
14143         if (any_ms) {
14144                 ret = intel_modeset_checks(state);
14145
14146                 if (ret)
14147                         return ret;
14148         } else {
14149                 intel_state->cdclk = dev_priv->atomic_cdclk_freq;
14150         }
14151
14152         ret = drm_atomic_helper_check_planes(dev, state);
14153         if (ret)
14154                 return ret;
14155
14156         intel_fbc_choose_crtc(dev_priv, state);
14157         return calc_watermark_data(state);
14158 }
14159
14160 static int intel_atomic_prepare_commit(struct drm_device *dev,
14161                                        struct drm_atomic_state *state)
14162 {
14163         struct drm_i915_private *dev_priv = to_i915(dev);
14164         struct drm_crtc_state *crtc_state;
14165         struct drm_crtc *crtc;
14166         int i, ret;
14167
14168         for_each_crtc_in_state(state, crtc, crtc_state, i) {
14169                 if (state->legacy_cursor_update)
14170                         continue;
14171
14172                 ret = intel_crtc_wait_for_pending_flips(crtc);
14173                 if (ret)
14174                         return ret;
14175
14176                 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
14177                         flush_workqueue(dev_priv->wq);
14178         }
14179
14180         ret = mutex_lock_interruptible(&dev->struct_mutex);
14181         if (ret)
14182                 return ret;
14183
14184         ret = drm_atomic_helper_prepare_planes(dev, state);
14185         mutex_unlock(&dev->struct_mutex);
14186
14187         return ret;
14188 }
14189
14190 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
14191 {
14192         struct drm_device *dev = crtc->base.dev;
14193
14194         if (!dev->max_vblank_count)
14195                 return drm_accurate_vblank_count(&crtc->base);
14196
14197         return dev->driver->get_vblank_counter(dev, crtc->pipe);
14198 }
14199
14200 static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
14201                                           struct drm_i915_private *dev_priv,
14202                                           unsigned crtc_mask)
14203 {
14204         unsigned last_vblank_count[I915_MAX_PIPES];
14205         enum pipe pipe;
14206         int ret;
14207
14208         if (!crtc_mask)
14209                 return;
14210
14211         for_each_pipe(dev_priv, pipe) {
14212                 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
14213                                                                   pipe);
14214
14215                 if (!((1 << pipe) & crtc_mask))
14216                         continue;
14217
14218                 ret = drm_crtc_vblank_get(&crtc->base);
14219                 if (WARN_ON(ret != 0)) {
14220                         crtc_mask &= ~(1 << pipe);
14221                         continue;
14222                 }
14223
14224                 last_vblank_count[pipe] = drm_crtc_vblank_count(&crtc->base);
14225         }
14226
14227         for_each_pipe(dev_priv, pipe) {
14228                 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
14229                                                                   pipe);
14230                 long lret;
14231
14232                 if (!((1 << pipe) & crtc_mask))
14233                         continue;
14234
14235                 lret = wait_event_timeout(dev->vblank[pipe].queue,
14236                                 last_vblank_count[pipe] !=
14237                                         drm_crtc_vblank_count(&crtc->base),
14238                                 msecs_to_jiffies(50));
14239
14240                 WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe));
14241
14242                 drm_crtc_vblank_put(&crtc->base);
14243         }
14244 }
14245
14246 static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
14247 {
14248         /* fb updated, need to unpin old fb */
14249         if (crtc_state->fb_changed)
14250                 return true;
14251
14252         /* wm changes, need vblank before final wm's */
14253         if (crtc_state->update_wm_post)
14254                 return true;
14255
14256         /*
14257          * cxsr is re-enabled after vblank.
14258          * This is already handled by crtc_state->update_wm_post,
14259          * but added for clarity.
14260          */
14261         if (crtc_state->disable_cxsr)
14262                 return true;
14263
14264         return false;
14265 }
14266
14267 static void intel_update_crtc(struct drm_crtc *crtc,
14268                               struct drm_atomic_state *state,
14269                               struct drm_crtc_state *old_crtc_state,
14270                               unsigned int *crtc_vblank_mask)
14271 {
14272         struct drm_device *dev = crtc->dev;
14273         struct drm_i915_private *dev_priv = to_i915(dev);
14274         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14275         struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc->state);
14276         bool modeset = needs_modeset(crtc->state);
14277
14278         if (modeset) {
14279                 update_scanline_offset(intel_crtc);
14280                 dev_priv->display.crtc_enable(pipe_config, state);
14281         } else {
14282                 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
14283         }
14284
14285         if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
14286                 intel_fbc_enable(
14287                     intel_crtc, pipe_config,
14288                     to_intel_plane_state(crtc->primary->state));
14289         }
14290
14291         drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
14292
14293         if (needs_vblank_wait(pipe_config))
14294                 *crtc_vblank_mask |= drm_crtc_mask(crtc);
14295 }
14296
14297 static void intel_update_crtcs(struct drm_atomic_state *state,
14298                                unsigned int *crtc_vblank_mask)
14299 {
14300         struct drm_crtc *crtc;
14301         struct drm_crtc_state *old_crtc_state;
14302         int i;
14303
14304         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14305                 if (!crtc->state->active)
14306                         continue;
14307
14308                 intel_update_crtc(crtc, state, old_crtc_state,
14309                                   crtc_vblank_mask);
14310         }
14311 }
14312
14313 static void skl_update_crtcs(struct drm_atomic_state *state,
14314                              unsigned int *crtc_vblank_mask)
14315 {
14316         struct drm_i915_private *dev_priv = to_i915(state->dev);
14317         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14318         struct drm_crtc *crtc;
14319         struct intel_crtc *intel_crtc;
14320         struct drm_crtc_state *old_crtc_state;
14321         struct intel_crtc_state *cstate;
14322         unsigned int updated = 0;
14323         bool progress;
14324         enum pipe pipe;
14325         int i;
14326
14327         const struct skl_ddb_entry *entries[I915_MAX_PIPES] = {};
14328
14329         for_each_crtc_in_state(state, crtc, old_crtc_state, i)
14330                 /* ignore allocations for crtc's that have been turned off. */
14331                 if (crtc->state->active)
14332                         entries[i] = &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb;
14333
14334         /*
14335          * Whenever the number of active pipes changes, we need to make sure we
14336          * update the pipes in the right order so that their ddb allocations
14337          * never overlap with eachother inbetween CRTC updates. Otherwise we'll
14338          * cause pipe underruns and other bad stuff.
14339          */
14340         do {
14341                 progress = false;
14342
14343                 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14344                         bool vbl_wait = false;
14345                         unsigned int cmask = drm_crtc_mask(crtc);
14346
14347                         intel_crtc = to_intel_crtc(crtc);
14348                         cstate = to_intel_crtc_state(crtc->state);
14349                         pipe = intel_crtc->pipe;
14350
14351                         if (updated & cmask || !cstate->base.active)
14352                                 continue;
14353
14354                         if (skl_ddb_allocation_overlaps(entries, &cstate->wm.skl.ddb, i))
14355                                 continue;
14356
14357                         updated |= cmask;
14358                         entries[i] = &cstate->wm.skl.ddb;
14359
14360                         /*
14361                          * If this is an already active pipe, it's DDB changed,
14362                          * and this isn't the last pipe that needs updating
14363                          * then we need to wait for a vblank to pass for the
14364                          * new ddb allocation to take effect.
14365                          */
14366                         if (!skl_ddb_entry_equal(&cstate->wm.skl.ddb,
14367                                                  &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb) &&
14368                             !crtc->state->active_changed &&
14369                             intel_state->wm_results.dirty_pipes != updated)
14370                                 vbl_wait = true;
14371
14372                         intel_update_crtc(crtc, state, old_crtc_state,
14373                                           crtc_vblank_mask);
14374
14375                         if (vbl_wait)
14376                                 intel_wait_for_vblank(dev_priv, pipe);
14377
14378                         progress = true;
14379                 }
14380         } while (progress);
14381 }
14382
14383 static void intel_atomic_commit_tail(struct drm_atomic_state *state)
14384 {
14385         struct drm_device *dev = state->dev;
14386         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14387         struct drm_i915_private *dev_priv = to_i915(dev);
14388         struct drm_crtc_state *old_crtc_state;
14389         struct drm_crtc *crtc;
14390         struct intel_crtc_state *intel_cstate;
14391         bool hw_check = intel_state->modeset;
14392         unsigned long put_domains[I915_MAX_PIPES] = {};
14393         unsigned crtc_vblank_mask = 0;
14394         int i;
14395
14396         drm_atomic_helper_wait_for_dependencies(state);
14397
14398         if (intel_state->modeset)
14399                 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
14400
14401         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14402                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14403
14404                 if (needs_modeset(crtc->state) ||
14405                     to_intel_crtc_state(crtc->state)->update_pipe) {
14406                         hw_check = true;
14407
14408                         put_domains[to_intel_crtc(crtc)->pipe] =
14409                                 modeset_get_crtc_power_domains(crtc,
14410                                         to_intel_crtc_state(crtc->state));
14411                 }
14412
14413                 if (!needs_modeset(crtc->state))
14414                         continue;
14415
14416                 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
14417
14418                 if (old_crtc_state->active) {
14419                         intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
14420                         dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state);
14421                         intel_crtc->active = false;
14422                         intel_fbc_disable(intel_crtc);
14423                         intel_disable_shared_dpll(intel_crtc);
14424
14425                         /*
14426                          * Underruns don't always raise
14427                          * interrupts, so check manually.
14428                          */
14429                         intel_check_cpu_fifo_underruns(dev_priv);
14430                         intel_check_pch_fifo_underruns(dev_priv);
14431
14432                         if (!crtc->state->active) {
14433                                 /*
14434                                  * Make sure we don't call initial_watermarks
14435                                  * for ILK-style watermark updates.
14436                                  */
14437                                 if (dev_priv->display.atomic_update_watermarks)
14438                                         dev_priv->display.initial_watermarks(intel_state,
14439                                                                              to_intel_crtc_state(crtc->state));
14440                                 else
14441                                         intel_update_watermarks(intel_crtc);
14442                         }
14443                 }
14444         }
14445
14446         /* Only after disabling all output pipelines that will be changed can we
14447          * update the the output configuration. */
14448         intel_modeset_update_crtc_state(state);
14449
14450         if (intel_state->modeset) {
14451                 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
14452
14453                 if (dev_priv->display.modeset_commit_cdclk &&
14454                     (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
14455                      intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco))
14456                         dev_priv->display.modeset_commit_cdclk(state);
14457
14458                 /*
14459                  * SKL workaround: bspec recommends we disable the SAGV when we
14460                  * have more then one pipe enabled
14461                  */
14462                 if (!intel_can_enable_sagv(state))
14463                         intel_disable_sagv(dev_priv);
14464
14465                 intel_modeset_verify_disabled(dev, state);
14466         }
14467
14468         /* Complete the events for pipes that have now been disabled */
14469         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14470                 bool modeset = needs_modeset(crtc->state);
14471
14472                 /* Complete events for now disable pipes here. */
14473                 if (modeset && !crtc->state->active && crtc->state->event) {
14474                         spin_lock_irq(&dev->event_lock);
14475                         drm_crtc_send_vblank_event(crtc, crtc->state->event);
14476                         spin_unlock_irq(&dev->event_lock);
14477
14478                         crtc->state->event = NULL;
14479                 }
14480         }
14481
14482         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
14483         dev_priv->display.update_crtcs(state, &crtc_vblank_mask);
14484
14485         /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
14486          * already, but still need the state for the delayed optimization. To
14487          * fix this:
14488          * - wrap the optimization/post_plane_update stuff into a per-crtc work.
14489          * - schedule that vblank worker _before_ calling hw_done
14490          * - at the start of commit_tail, cancel it _synchrously
14491          * - switch over to the vblank wait helper in the core after that since
14492          *   we don't need out special handling any more.
14493          */
14494         if (!state->legacy_cursor_update)
14495                 intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
14496
14497         /*
14498          * Now that the vblank has passed, we can go ahead and program the
14499          * optimal watermarks on platforms that need two-step watermark
14500          * programming.
14501          *
14502          * TODO: Move this (and other cleanup) to an async worker eventually.
14503          */
14504         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14505                 intel_cstate = to_intel_crtc_state(crtc->state);
14506
14507                 if (dev_priv->display.optimize_watermarks)
14508                         dev_priv->display.optimize_watermarks(intel_state,
14509                                                               intel_cstate);
14510         }
14511
14512         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14513                 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
14514
14515                 if (put_domains[i])
14516                         modeset_put_power_domains(dev_priv, put_domains[i]);
14517
14518                 intel_modeset_verify_crtc(crtc, state, old_crtc_state, crtc->state);
14519         }
14520
14521         if (intel_state->modeset && intel_can_enable_sagv(state))
14522                 intel_enable_sagv(dev_priv);
14523
14524         drm_atomic_helper_commit_hw_done(state);
14525
14526         if (intel_state->modeset)
14527                 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
14528
14529         mutex_lock(&dev->struct_mutex);
14530         drm_atomic_helper_cleanup_planes(dev, state);
14531         mutex_unlock(&dev->struct_mutex);
14532
14533         drm_atomic_helper_commit_cleanup_done(state);
14534
14535         drm_atomic_state_put(state);
14536
14537         /* As one of the primary mmio accessors, KMS has a high likelihood
14538          * of triggering bugs in unclaimed access. After we finish
14539          * modesetting, see if an error has been flagged, and if so
14540          * enable debugging for the next modeset - and hope we catch
14541          * the culprit.
14542          *
14543          * XXX note that we assume display power is on at this point.
14544          * This might hold true now but we need to add pm helper to check
14545          * unclaimed only when the hardware is on, as atomic commits
14546          * can happen also when the device is completely off.
14547          */
14548         intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
14549 }
14550
14551 static void intel_atomic_commit_work(struct work_struct *work)
14552 {
14553         struct drm_atomic_state *state =
14554                 container_of(work, struct drm_atomic_state, commit_work);
14555
14556         intel_atomic_commit_tail(state);
14557 }
14558
14559 static int __i915_sw_fence_call
14560 intel_atomic_commit_ready(struct i915_sw_fence *fence,
14561                           enum i915_sw_fence_notify notify)
14562 {
14563         struct intel_atomic_state *state =
14564                 container_of(fence, struct intel_atomic_state, commit_ready);
14565
14566         switch (notify) {
14567         case FENCE_COMPLETE:
14568                 if (state->base.commit_work.func)
14569                         queue_work(system_unbound_wq, &state->base.commit_work);
14570                 break;
14571
14572         case FENCE_FREE:
14573                 drm_atomic_state_put(&state->base);
14574                 break;
14575         }
14576
14577         return NOTIFY_DONE;
14578 }
14579
14580 static void intel_atomic_track_fbs(struct drm_atomic_state *state)
14581 {
14582         struct drm_plane_state *old_plane_state;
14583         struct drm_plane *plane;
14584         int i;
14585
14586         for_each_plane_in_state(state, plane, old_plane_state, i)
14587                 i915_gem_track_fb(intel_fb_obj(old_plane_state->fb),
14588                                   intel_fb_obj(plane->state->fb),
14589                                   to_intel_plane(plane)->frontbuffer_bit);
14590 }
14591
14592 /**
14593  * intel_atomic_commit - commit validated state object
14594  * @dev: DRM device
14595  * @state: the top-level driver state object
14596  * @nonblock: nonblocking commit
14597  *
14598  * This function commits a top-level state object that has been validated
14599  * with drm_atomic_helper_check().
14600  *
14601  * RETURNS
14602  * Zero for success or -errno.
14603  */
14604 static int intel_atomic_commit(struct drm_device *dev,
14605                                struct drm_atomic_state *state,
14606                                bool nonblock)
14607 {
14608         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14609         struct drm_i915_private *dev_priv = to_i915(dev);
14610         int ret = 0;
14611
14612         ret = drm_atomic_helper_setup_commit(state, nonblock);
14613         if (ret)
14614                 return ret;
14615
14616         drm_atomic_state_get(state);
14617         i915_sw_fence_init(&intel_state->commit_ready,
14618                            intel_atomic_commit_ready);
14619
14620         ret = intel_atomic_prepare_commit(dev, state);
14621         if (ret) {
14622                 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
14623                 i915_sw_fence_commit(&intel_state->commit_ready);
14624                 return ret;
14625         }
14626
14627         drm_atomic_helper_swap_state(state, true);
14628         dev_priv->wm.distrust_bios_wm = false;
14629         intel_shared_dpll_swap_state(state);
14630         intel_atomic_track_fbs(state);
14631
14632         if (intel_state->modeset) {
14633                 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
14634                        sizeof(intel_state->min_pixclk));
14635                 dev_priv->active_crtcs = intel_state->active_crtcs;
14636                 dev_priv->atomic_cdclk_freq = intel_state->cdclk;
14637         }
14638
14639         drm_atomic_state_get(state);
14640         INIT_WORK(&state->commit_work,
14641                   nonblock ? intel_atomic_commit_work : NULL);
14642
14643         i915_sw_fence_commit(&intel_state->commit_ready);
14644         if (!nonblock) {
14645                 i915_sw_fence_wait(&intel_state->commit_ready);
14646                 intel_atomic_commit_tail(state);
14647         }
14648
14649         return 0;
14650 }
14651
14652 void intel_crtc_restore_mode(struct drm_crtc *crtc)
14653 {
14654         struct drm_device *dev = crtc->dev;
14655         struct drm_atomic_state *state;
14656         struct drm_crtc_state *crtc_state;
14657         int ret;
14658
14659         state = drm_atomic_state_alloc(dev);
14660         if (!state) {
14661                 DRM_DEBUG_KMS("[CRTC:%d:%s] crtc restore failed, out of memory",
14662                               crtc->base.id, crtc->name);
14663                 return;
14664         }
14665
14666         state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
14667
14668 retry:
14669         crtc_state = drm_atomic_get_crtc_state(state, crtc);
14670         ret = PTR_ERR_OR_ZERO(crtc_state);
14671         if (!ret) {
14672                 if (!crtc_state->active)
14673                         goto out;
14674
14675                 crtc_state->mode_changed = true;
14676                 ret = drm_atomic_commit(state);
14677         }
14678
14679         if (ret == -EDEADLK) {
14680                 drm_atomic_state_clear(state);
14681                 drm_modeset_backoff(state->acquire_ctx);
14682                 goto retry;
14683         }
14684
14685 out:
14686         drm_atomic_state_put(state);
14687 }
14688
14689 /*
14690  * FIXME: Remove this once i915 is fully DRIVER_ATOMIC by calling
14691  *        drm_atomic_helper_legacy_gamma_set() directly.
14692  */
14693 static int intel_atomic_legacy_gamma_set(struct drm_crtc *crtc,
14694                                          u16 *red, u16 *green, u16 *blue,
14695                                          uint32_t size)
14696 {
14697         struct drm_device *dev = crtc->dev;
14698         struct drm_mode_config *config = &dev->mode_config;
14699         struct drm_crtc_state *state;
14700         int ret;
14701
14702         ret = drm_atomic_helper_legacy_gamma_set(crtc, red, green, blue, size);
14703         if (ret)
14704                 return ret;
14705
14706         /*
14707          * Make sure we update the legacy properties so this works when
14708          * atomic is not enabled.
14709          */
14710
14711         state = crtc->state;
14712
14713         drm_object_property_set_value(&crtc->base,
14714                                       config->degamma_lut_property,
14715                                       (state->degamma_lut) ?
14716                                       state->degamma_lut->base.id : 0);
14717
14718         drm_object_property_set_value(&crtc->base,
14719                                       config->ctm_property,
14720                                       (state->ctm) ?
14721                                       state->ctm->base.id : 0);
14722
14723         drm_object_property_set_value(&crtc->base,
14724                                       config->gamma_lut_property,
14725                                       (state->gamma_lut) ?
14726                                       state->gamma_lut->base.id : 0);
14727
14728         return 0;
14729 }
14730
14731 static const struct drm_crtc_funcs intel_crtc_funcs = {
14732         .gamma_set = intel_atomic_legacy_gamma_set,
14733         .set_config = drm_atomic_helper_set_config,
14734         .set_property = drm_atomic_helper_crtc_set_property,
14735         .destroy = intel_crtc_destroy,
14736         .page_flip = drm_atomic_helper_page_flip,
14737         .atomic_duplicate_state = intel_crtc_duplicate_state,
14738         .atomic_destroy_state = intel_crtc_destroy_state,
14739         .set_crc_source = intel_crtc_set_crc_source,
14740 };
14741
14742 /**
14743  * intel_prepare_plane_fb - Prepare fb for usage on plane
14744  * @plane: drm plane to prepare for
14745  * @fb: framebuffer to prepare for presentation
14746  *
14747  * Prepares a framebuffer for usage on a display plane.  Generally this
14748  * involves pinning the underlying object and updating the frontbuffer tracking
14749  * bits.  Some older platforms need special physical address handling for
14750  * cursor planes.
14751  *
14752  * Must be called with struct_mutex held.
14753  *
14754  * Returns 0 on success, negative error code on failure.
14755  */
14756 int
14757 intel_prepare_plane_fb(struct drm_plane *plane,
14758                        struct drm_plane_state *new_state)
14759 {
14760         struct intel_atomic_state *intel_state =
14761                 to_intel_atomic_state(new_state->state);
14762         struct drm_i915_private *dev_priv = to_i915(plane->dev);
14763         struct drm_framebuffer *fb = new_state->fb;
14764         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14765         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
14766         int ret;
14767
14768         if (!obj && !old_obj)
14769                 return 0;
14770
14771         if (old_obj) {
14772                 struct drm_crtc_state *crtc_state =
14773                         drm_atomic_get_existing_crtc_state(new_state->state,
14774                                                            plane->state->crtc);
14775
14776                 /* Big Hammer, we also need to ensure that any pending
14777                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
14778                  * current scanout is retired before unpinning the old
14779                  * framebuffer. Note that we rely on userspace rendering
14780                  * into the buffer attached to the pipe they are waiting
14781                  * on. If not, userspace generates a GPU hang with IPEHR
14782                  * point to the MI_WAIT_FOR_EVENT.
14783                  *
14784                  * This should only fail upon a hung GPU, in which case we
14785                  * can safely continue.
14786                  */
14787                 if (needs_modeset(crtc_state)) {
14788                         ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
14789                                                               old_obj->resv, NULL,
14790                                                               false, 0,
14791                                                               GFP_KERNEL);
14792                         if (ret < 0)
14793                                 return ret;
14794                 }
14795         }
14796
14797         if (new_state->fence) { /* explicit fencing */
14798                 ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready,
14799                                                     new_state->fence,
14800                                                     I915_FENCE_TIMEOUT,
14801                                                     GFP_KERNEL);
14802                 if (ret < 0)
14803                         return ret;
14804         }
14805
14806         if (!obj)
14807                 return 0;
14808
14809         if (!new_state->fence) { /* implicit fencing */
14810                 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
14811                                                       obj->resv, NULL,
14812                                                       false, I915_FENCE_TIMEOUT,
14813                                                       GFP_KERNEL);
14814                 if (ret < 0)
14815                         return ret;
14816
14817                 i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY);
14818         }
14819
14820         if (plane->type == DRM_PLANE_TYPE_CURSOR &&
14821             INTEL_INFO(dev_priv)->cursor_needs_physical) {
14822                 int align = IS_I830(dev_priv) ? 16 * 1024 : 256;
14823                 ret = i915_gem_object_attach_phys(obj, align);
14824                 if (ret) {
14825                         DRM_DEBUG_KMS("failed to attach phys object\n");
14826                         return ret;
14827                 }
14828         } else {
14829                 struct i915_vma *vma;
14830
14831                 vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
14832                 if (IS_ERR(vma)) {
14833                         DRM_DEBUG_KMS("failed to pin object\n");
14834                         return PTR_ERR(vma);
14835                 }
14836
14837                 to_intel_plane_state(new_state)->vma = vma;
14838         }
14839
14840         return 0;
14841 }
14842
14843 /**
14844  * intel_cleanup_plane_fb - Cleans up an fb after plane use
14845  * @plane: drm plane to clean up for
14846  * @fb: old framebuffer that was on plane
14847  *
14848  * Cleans up a framebuffer that has just been removed from a plane.
14849  *
14850  * Must be called with struct_mutex held.
14851  */
14852 void
14853 intel_cleanup_plane_fb(struct drm_plane *plane,
14854                        struct drm_plane_state *old_state)
14855 {
14856         struct i915_vma *vma;
14857
14858         /* Should only be called after a successful intel_prepare_plane_fb()! */
14859         vma = fetch_and_zero(&to_intel_plane_state(old_state)->vma);
14860         if (vma)
14861                 intel_unpin_fb_vma(vma);
14862 }
14863
14864 int
14865 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
14866 {
14867         int max_scale;
14868         int crtc_clock, cdclk;
14869
14870         if (!intel_crtc || !crtc_state->base.enable)
14871                 return DRM_PLANE_HELPER_NO_SCALING;
14872
14873         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
14874         cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
14875
14876         if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
14877                 return DRM_PLANE_HELPER_NO_SCALING;
14878
14879         /*
14880          * skl max scale is lower of:
14881          *    close to 3 but not 3, -1 is for that purpose
14882          *            or
14883          *    cdclk/crtc_clock
14884          */
14885         max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
14886
14887         return max_scale;
14888 }
14889
14890 static int
14891 intel_check_primary_plane(struct drm_plane *plane,
14892                           struct intel_crtc_state *crtc_state,
14893                           struct intel_plane_state *state)
14894 {
14895         struct drm_i915_private *dev_priv = to_i915(plane->dev);
14896         struct drm_crtc *crtc = state->base.crtc;
14897         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
14898         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
14899         bool can_position = false;
14900         int ret;
14901
14902         if (INTEL_GEN(dev_priv) >= 9) {
14903                 /* use scaler when colorkey is not required */
14904                 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
14905                         min_scale = 1;
14906                         max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
14907                 }
14908                 can_position = true;
14909         }
14910
14911         ret = drm_plane_helper_check_state(&state->base,
14912                                            &state->clip,
14913                                            min_scale, max_scale,
14914                                            can_position, true);
14915         if (ret)
14916                 return ret;
14917
14918         if (!state->base.fb)
14919                 return 0;
14920
14921         if (INTEL_GEN(dev_priv) >= 9) {
14922                 ret = skl_check_plane_surface(state);
14923                 if (ret)
14924                         return ret;
14925         }
14926
14927         return 0;
14928 }
14929
14930 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
14931                                     struct drm_crtc_state *old_crtc_state)
14932 {
14933         struct drm_device *dev = crtc->dev;
14934         struct drm_i915_private *dev_priv = to_i915(dev);
14935         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14936         struct intel_crtc_state *intel_cstate =
14937                 to_intel_crtc_state(crtc->state);
14938         struct intel_crtc_state *old_intel_cstate =
14939                 to_intel_crtc_state(old_crtc_state);
14940         struct intel_atomic_state *old_intel_state =
14941                 to_intel_atomic_state(old_crtc_state->state);
14942         bool modeset = needs_modeset(crtc->state);
14943
14944         /* Perform vblank evasion around commit operation */
14945         intel_pipe_update_start(intel_crtc);
14946
14947         if (modeset)
14948                 goto out;
14949
14950         if (crtc->state->color_mgmt_changed || to_intel_crtc_state(crtc->state)->update_pipe) {
14951                 intel_color_set_csc(crtc->state);
14952                 intel_color_load_luts(crtc->state);
14953         }
14954
14955         if (intel_cstate->update_pipe)
14956                 intel_update_pipe_config(intel_crtc, old_intel_cstate);
14957         else if (INTEL_GEN(dev_priv) >= 9)
14958                 skl_detach_scalers(intel_crtc);
14959
14960 out:
14961         if (dev_priv->display.atomic_update_watermarks)
14962                 dev_priv->display.atomic_update_watermarks(old_intel_state,
14963                                                            intel_cstate);
14964 }
14965
14966 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
14967                                      struct drm_crtc_state *old_crtc_state)
14968 {
14969         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14970
14971         intel_pipe_update_end(intel_crtc, NULL);
14972 }
14973
14974 /**
14975  * intel_plane_destroy - destroy a plane
14976  * @plane: plane to destroy
14977  *
14978  * Common destruction function for all types of planes (primary, cursor,
14979  * sprite).
14980  */
14981 void intel_plane_destroy(struct drm_plane *plane)
14982 {
14983         drm_plane_cleanup(plane);
14984         kfree(to_intel_plane(plane));
14985 }
14986
14987 const struct drm_plane_funcs intel_plane_funcs = {
14988         .update_plane = drm_atomic_helper_update_plane,
14989         .disable_plane = drm_atomic_helper_disable_plane,
14990         .destroy = intel_plane_destroy,
14991         .set_property = drm_atomic_helper_plane_set_property,
14992         .atomic_get_property = intel_plane_atomic_get_property,
14993         .atomic_set_property = intel_plane_atomic_set_property,
14994         .atomic_duplicate_state = intel_plane_duplicate_state,
14995         .atomic_destroy_state = intel_plane_destroy_state,
14996 };
14997
14998 static int
14999 intel_legacy_cursor_update(struct drm_plane *plane,
15000                            struct drm_crtc *crtc,
15001                            struct drm_framebuffer *fb,
15002                            int crtc_x, int crtc_y,
15003                            unsigned int crtc_w, unsigned int crtc_h,
15004                            uint32_t src_x, uint32_t src_y,
15005                            uint32_t src_w, uint32_t src_h)
15006 {
15007         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
15008         int ret;
15009         struct drm_plane_state *old_plane_state, *new_plane_state;
15010         struct intel_plane *intel_plane = to_intel_plane(plane);
15011         struct drm_framebuffer *old_fb;
15012         struct drm_crtc_state *crtc_state = crtc->state;
15013         struct i915_vma *old_vma;
15014
15015         /*
15016          * When crtc is inactive or there is a modeset pending,
15017          * wait for it to complete in the slowpath
15018          */
15019         if (!crtc_state->active || needs_modeset(crtc_state) ||
15020             to_intel_crtc_state(crtc_state)->update_pipe)
15021                 goto slow;
15022
15023         old_plane_state = plane->state;
15024
15025         /*
15026          * If any parameters change that may affect watermarks,
15027          * take the slowpath. Only changing fb or position should be
15028          * in the fastpath.
15029          */
15030         if (old_plane_state->crtc != crtc ||
15031             old_plane_state->src_w != src_w ||
15032             old_plane_state->src_h != src_h ||
15033             old_plane_state->crtc_w != crtc_w ||
15034             old_plane_state->crtc_h != crtc_h ||
15035             !old_plane_state->visible ||
15036             old_plane_state->fb->modifier != fb->modifier)
15037                 goto slow;
15038
15039         new_plane_state = intel_plane_duplicate_state(plane);
15040         if (!new_plane_state)
15041                 return -ENOMEM;
15042
15043         drm_atomic_set_fb_for_plane(new_plane_state, fb);
15044
15045         new_plane_state->src_x = src_x;
15046         new_plane_state->src_y = src_y;
15047         new_plane_state->src_w = src_w;
15048         new_plane_state->src_h = src_h;
15049         new_plane_state->crtc_x = crtc_x;
15050         new_plane_state->crtc_y = crtc_y;
15051         new_plane_state->crtc_w = crtc_w;
15052         new_plane_state->crtc_h = crtc_h;
15053
15054         ret = intel_plane_atomic_check_with_state(to_intel_crtc_state(crtc->state),
15055                                                   to_intel_plane_state(new_plane_state));
15056         if (ret)
15057                 goto out_free;
15058
15059         /* Visibility changed, must take slowpath. */
15060         if (!new_plane_state->visible)
15061                 goto slow_free;
15062
15063         ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
15064         if (ret)
15065                 goto out_free;
15066
15067         if (INTEL_INFO(dev_priv)->cursor_needs_physical) {
15068                 int align = IS_I830(dev_priv) ? 16 * 1024 : 256;
15069
15070                 ret = i915_gem_object_attach_phys(intel_fb_obj(fb), align);
15071                 if (ret) {
15072                         DRM_DEBUG_KMS("failed to attach phys object\n");
15073                         goto out_unlock;
15074                 }
15075         } else {
15076                 struct i915_vma *vma;
15077
15078                 vma = intel_pin_and_fence_fb_obj(fb, new_plane_state->rotation);
15079                 if (IS_ERR(vma)) {
15080                         DRM_DEBUG_KMS("failed to pin object\n");
15081
15082                         ret = PTR_ERR(vma);
15083                         goto out_unlock;
15084                 }
15085
15086                 to_intel_plane_state(new_plane_state)->vma = vma;
15087         }
15088
15089         old_fb = old_plane_state->fb;
15090         old_vma = to_intel_plane_state(old_plane_state)->vma;
15091
15092         i915_gem_track_fb(intel_fb_obj(old_fb), intel_fb_obj(fb),
15093                           intel_plane->frontbuffer_bit);
15094
15095         /* Swap plane state */
15096         new_plane_state->fence = old_plane_state->fence;
15097         *to_intel_plane_state(old_plane_state) = *to_intel_plane_state(new_plane_state);
15098         new_plane_state->fence = NULL;
15099         new_plane_state->fb = old_fb;
15100         to_intel_plane_state(new_plane_state)->vma = old_vma;
15101
15102         intel_plane->update_plane(plane,
15103                                   to_intel_crtc_state(crtc->state),
15104                                   to_intel_plane_state(plane->state));
15105
15106         intel_cleanup_plane_fb(plane, new_plane_state);
15107
15108 out_unlock:
15109         mutex_unlock(&dev_priv->drm.struct_mutex);
15110 out_free:
15111         intel_plane_destroy_state(plane, new_plane_state);
15112         return ret;
15113
15114 slow_free:
15115         intel_plane_destroy_state(plane, new_plane_state);
15116 slow:
15117         return drm_atomic_helper_update_plane(plane, crtc, fb,
15118                                               crtc_x, crtc_y, crtc_w, crtc_h,
15119                                               src_x, src_y, src_w, src_h);
15120 }
15121
15122 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
15123         .update_plane = intel_legacy_cursor_update,
15124         .disable_plane = drm_atomic_helper_disable_plane,
15125         .destroy = intel_plane_destroy,
15126         .set_property = drm_atomic_helper_plane_set_property,
15127         .atomic_get_property = intel_plane_atomic_get_property,
15128         .atomic_set_property = intel_plane_atomic_set_property,
15129         .atomic_duplicate_state = intel_plane_duplicate_state,
15130         .atomic_destroy_state = intel_plane_destroy_state,
15131 };
15132
15133 static struct intel_plane *
15134 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
15135 {
15136         struct intel_plane *primary = NULL;
15137         struct intel_plane_state *state = NULL;
15138         const uint32_t *intel_primary_formats;
15139         unsigned int supported_rotations;
15140         unsigned int num_formats;
15141         int ret;
15142
15143         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
15144         if (!primary) {
15145                 ret = -ENOMEM;
15146                 goto fail;
15147         }
15148
15149         state = intel_create_plane_state(&primary->base);
15150         if (!state) {
15151                 ret = -ENOMEM;
15152                 goto fail;
15153         }
15154
15155         primary->base.state = &state->base;
15156
15157         primary->can_scale = false;
15158         primary->max_downscale = 1;
15159         if (INTEL_GEN(dev_priv) >= 9) {
15160                 primary->can_scale = true;
15161                 state->scaler_id = -1;
15162         }
15163         primary->pipe = pipe;
15164         /*
15165          * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
15166          * port is hooked to pipe B. Hence we want plane A feeding pipe B.
15167          */
15168         if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
15169                 primary->plane = (enum plane) !pipe;
15170         else
15171                 primary->plane = (enum plane) pipe;
15172         primary->id = PLANE_PRIMARY;
15173         primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
15174         primary->check_plane = intel_check_primary_plane;
15175
15176         if (INTEL_GEN(dev_priv) >= 9) {
15177                 intel_primary_formats = skl_primary_formats;
15178                 num_formats = ARRAY_SIZE(skl_primary_formats);
15179
15180                 primary->update_plane = skylake_update_primary_plane;
15181                 primary->disable_plane = skylake_disable_primary_plane;
15182         } else if (HAS_PCH_SPLIT(dev_priv)) {
15183                 intel_primary_formats = i965_primary_formats;
15184                 num_formats = ARRAY_SIZE(i965_primary_formats);
15185
15186                 primary->update_plane = ironlake_update_primary_plane;
15187                 primary->disable_plane = i9xx_disable_primary_plane;
15188         } else if (INTEL_GEN(dev_priv) >= 4) {
15189                 intel_primary_formats = i965_primary_formats;
15190                 num_formats = ARRAY_SIZE(i965_primary_formats);
15191
15192                 primary->update_plane = i9xx_update_primary_plane;
15193                 primary->disable_plane = i9xx_disable_primary_plane;
15194         } else {
15195                 intel_primary_formats = i8xx_primary_formats;
15196                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
15197
15198                 primary->update_plane = i9xx_update_primary_plane;
15199                 primary->disable_plane = i9xx_disable_primary_plane;
15200         }
15201
15202         if (INTEL_GEN(dev_priv) >= 9)
15203                 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
15204                                                0, &intel_plane_funcs,
15205                                                intel_primary_formats, num_formats,
15206                                                DRM_PLANE_TYPE_PRIMARY,
15207                                                "plane 1%c", pipe_name(pipe));
15208         else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
15209                 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
15210                                                0, &intel_plane_funcs,
15211                                                intel_primary_formats, num_formats,
15212                                                DRM_PLANE_TYPE_PRIMARY,
15213                                                "primary %c", pipe_name(pipe));
15214         else
15215                 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
15216                                                0, &intel_plane_funcs,
15217                                                intel_primary_formats, num_formats,
15218                                                DRM_PLANE_TYPE_PRIMARY,
15219                                                "plane %c", plane_name(primary->plane));
15220         if (ret)
15221                 goto fail;
15222
15223         if (INTEL_GEN(dev_priv) >= 9) {
15224                 supported_rotations =
15225                         DRM_ROTATE_0 | DRM_ROTATE_90 |
15226                         DRM_ROTATE_180 | DRM_ROTATE_270;
15227         } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
15228                 supported_rotations =
15229                         DRM_ROTATE_0 | DRM_ROTATE_180 |
15230                         DRM_REFLECT_X;
15231         } else if (INTEL_GEN(dev_priv) >= 4) {
15232                 supported_rotations =
15233                         DRM_ROTATE_0 | DRM_ROTATE_180;
15234         } else {
15235                 supported_rotations = DRM_ROTATE_0;
15236         }
15237
15238         if (INTEL_GEN(dev_priv) >= 4)
15239                 drm_plane_create_rotation_property(&primary->base,
15240                                                    DRM_ROTATE_0,
15241                                                    supported_rotations);
15242
15243         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
15244
15245         return primary;
15246
15247 fail:
15248         kfree(state);
15249         kfree(primary);
15250
15251         return ERR_PTR(ret);
15252 }
15253
15254 static int
15255 intel_check_cursor_plane(struct drm_plane *plane,
15256                          struct intel_crtc_state *crtc_state,
15257                          struct intel_plane_state *state)
15258 {
15259         struct drm_framebuffer *fb = state->base.fb;
15260         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
15261         enum pipe pipe = to_intel_plane(plane)->pipe;
15262         unsigned stride;
15263         int ret;
15264
15265         ret = drm_plane_helper_check_state(&state->base,
15266                                            &state->clip,
15267                                            DRM_PLANE_HELPER_NO_SCALING,
15268                                            DRM_PLANE_HELPER_NO_SCALING,
15269                                            true, true);
15270         if (ret)
15271                 return ret;
15272
15273         /* if we want to turn off the cursor ignore width and height */
15274         if (!obj)
15275                 return 0;
15276
15277         /* Check for which cursor types we support */
15278         if (!cursor_size_ok(to_i915(plane->dev), state->base.crtc_w,
15279                             state->base.crtc_h)) {
15280                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
15281                           state->base.crtc_w, state->base.crtc_h);
15282                 return -EINVAL;
15283         }
15284
15285         stride = roundup_pow_of_two(state->base.crtc_w) * 4;
15286         if (obj->base.size < stride * state->base.crtc_h) {
15287                 DRM_DEBUG_KMS("buffer is too small\n");
15288                 return -ENOMEM;
15289         }
15290
15291         if (fb->modifier != DRM_FORMAT_MOD_NONE) {
15292                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
15293                 return -EINVAL;
15294         }
15295
15296         /*
15297          * There's something wrong with the cursor on CHV pipe C.
15298          * If it straddles the left edge of the screen then
15299          * moving it away from the edge or disabling it often
15300          * results in a pipe underrun, and often that can lead to
15301          * dead pipe (constant underrun reported, and it scans
15302          * out just a solid color). To recover from that, the
15303          * display power well must be turned off and on again.
15304          * Refuse the put the cursor into that compromised position.
15305          */
15306         if (IS_CHERRYVIEW(to_i915(plane->dev)) && pipe == PIPE_C &&
15307             state->base.visible && state->base.crtc_x < 0) {
15308                 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
15309                 return -EINVAL;
15310         }
15311
15312         return 0;
15313 }
15314
15315 static void
15316 intel_disable_cursor_plane(struct drm_plane *plane,
15317                            struct drm_crtc *crtc)
15318 {
15319         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
15320
15321         intel_crtc->cursor_addr = 0;
15322         intel_crtc_update_cursor(crtc, NULL);
15323 }
15324
15325 static void
15326 intel_update_cursor_plane(struct drm_plane *plane,
15327                           const struct intel_crtc_state *crtc_state,
15328                           const struct intel_plane_state *state)
15329 {
15330         struct drm_crtc *crtc = crtc_state->base.crtc;
15331         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
15332         struct drm_i915_private *dev_priv = to_i915(plane->dev);
15333         struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
15334         uint32_t addr;
15335
15336         if (!obj)
15337                 addr = 0;
15338         else if (!INTEL_INFO(dev_priv)->cursor_needs_physical)
15339                 addr = intel_plane_ggtt_offset(state);
15340         else
15341                 addr = obj->phys_handle->busaddr;
15342
15343         intel_crtc->cursor_addr = addr;
15344         intel_crtc_update_cursor(crtc, state);
15345 }
15346
15347 static struct intel_plane *
15348 intel_cursor_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
15349 {
15350         struct intel_plane *cursor = NULL;
15351         struct intel_plane_state *state = NULL;
15352         int ret;
15353
15354         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
15355         if (!cursor) {
15356                 ret = -ENOMEM;
15357                 goto fail;
15358         }
15359
15360         state = intel_create_plane_state(&cursor->base);
15361         if (!state) {
15362                 ret = -ENOMEM;
15363                 goto fail;
15364         }
15365
15366         cursor->base.state = &state->base;
15367
15368         cursor->can_scale = false;
15369         cursor->max_downscale = 1;
15370         cursor->pipe = pipe;
15371         cursor->plane = pipe;
15372         cursor->id = PLANE_CURSOR;
15373         cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
15374         cursor->check_plane = intel_check_cursor_plane;
15375         cursor->update_plane = intel_update_cursor_plane;
15376         cursor->disable_plane = intel_disable_cursor_plane;
15377
15378         ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
15379                                        0, &intel_cursor_plane_funcs,
15380                                        intel_cursor_formats,
15381                                        ARRAY_SIZE(intel_cursor_formats),
15382                                        DRM_PLANE_TYPE_CURSOR,
15383                                        "cursor %c", pipe_name(pipe));
15384         if (ret)
15385                 goto fail;
15386
15387         if (INTEL_GEN(dev_priv) >= 4)
15388                 drm_plane_create_rotation_property(&cursor->base,
15389                                                    DRM_ROTATE_0,
15390                                                    DRM_ROTATE_0 |
15391                                                    DRM_ROTATE_180);
15392
15393         if (INTEL_GEN(dev_priv) >= 9)
15394                 state->scaler_id = -1;
15395
15396         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
15397
15398         return cursor;
15399
15400 fail:
15401         kfree(state);
15402         kfree(cursor);
15403
15404         return ERR_PTR(ret);
15405 }
15406
15407 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
15408                                     struct intel_crtc_state *crtc_state)
15409 {
15410         struct intel_crtc_scaler_state *scaler_state =
15411                 &crtc_state->scaler_state;
15412         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
15413         int i;
15414
15415         crtc->num_scalers = dev_priv->info.num_scalers[crtc->pipe];
15416         if (!crtc->num_scalers)
15417                 return;
15418
15419         for (i = 0; i < crtc->num_scalers; i++) {
15420                 struct intel_scaler *scaler = &scaler_state->scalers[i];
15421
15422                 scaler->in_use = 0;
15423                 scaler->mode = PS_SCALER_MODE_DYN;
15424         }
15425
15426         scaler_state->scaler_id = -1;
15427 }
15428
15429 static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
15430 {
15431         struct intel_crtc *intel_crtc;
15432         struct intel_crtc_state *crtc_state = NULL;
15433         struct intel_plane *primary = NULL;
15434         struct intel_plane *cursor = NULL;
15435         int sprite, ret;
15436
15437         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
15438         if (!intel_crtc)
15439                 return -ENOMEM;
15440
15441         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
15442         if (!crtc_state) {
15443                 ret = -ENOMEM;
15444                 goto fail;
15445         }
15446         intel_crtc->config = crtc_state;
15447         intel_crtc->base.state = &crtc_state->base;
15448         crtc_state->base.crtc = &intel_crtc->base;
15449
15450         primary = intel_primary_plane_create(dev_priv, pipe);
15451         if (IS_ERR(primary)) {
15452                 ret = PTR_ERR(primary);
15453                 goto fail;
15454         }
15455         intel_crtc->plane_ids_mask |= BIT(primary->id);
15456
15457         for_each_sprite(dev_priv, pipe, sprite) {
15458                 struct intel_plane *plane;
15459
15460                 plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
15461                 if (IS_ERR(plane)) {
15462                         ret = PTR_ERR(plane);
15463                         goto fail;
15464                 }
15465                 intel_crtc->plane_ids_mask |= BIT(plane->id);
15466         }
15467
15468         cursor = intel_cursor_plane_create(dev_priv, pipe);
15469         if (IS_ERR(cursor)) {
15470                 ret = PTR_ERR(cursor);
15471                 goto fail;
15472         }
15473         intel_crtc->plane_ids_mask |= BIT(cursor->id);
15474
15475         ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base,
15476                                         &primary->base, &cursor->base,
15477                                         &intel_crtc_funcs,
15478                                         "pipe %c", pipe_name(pipe));
15479         if (ret)
15480                 goto fail;
15481
15482         intel_crtc->pipe = pipe;
15483         intel_crtc->plane = primary->plane;
15484
15485         intel_crtc->cursor_base = ~0;
15486         intel_crtc->cursor_cntl = ~0;
15487         intel_crtc->cursor_size = ~0;
15488
15489         intel_crtc->wm.cxsr_allowed = true;
15490
15491         /* initialize shared scalers */
15492         intel_crtc_init_scalers(intel_crtc, crtc_state);
15493
15494         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
15495                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
15496         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = intel_crtc;
15497         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = intel_crtc;
15498
15499         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
15500
15501         intel_color_init(&intel_crtc->base);
15502
15503         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
15504
15505         return 0;
15506
15507 fail:
15508         /*
15509          * drm_mode_config_cleanup() will free up any
15510          * crtcs/planes already initialized.
15511          */
15512         kfree(crtc_state);
15513         kfree(intel_crtc);
15514
15515         return ret;
15516 }
15517
15518 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
15519 {
15520         struct drm_encoder *encoder = connector->base.encoder;
15521         struct drm_device *dev = connector->base.dev;
15522
15523         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
15524
15525         if (!encoder || WARN_ON(!encoder->crtc))
15526                 return INVALID_PIPE;
15527
15528         return to_intel_crtc(encoder->crtc)->pipe;
15529 }
15530
15531 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
15532                                 struct drm_file *file)
15533 {
15534         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
15535         struct drm_crtc *drmmode_crtc;
15536         struct intel_crtc *crtc;
15537
15538         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
15539         if (!drmmode_crtc)
15540                 return -ENOENT;
15541
15542         crtc = to_intel_crtc(drmmode_crtc);
15543         pipe_from_crtc_id->pipe = crtc->pipe;
15544
15545         return 0;
15546 }
15547
15548 static int intel_encoder_clones(struct intel_encoder *encoder)
15549 {
15550         struct drm_device *dev = encoder->base.dev;
15551         struct intel_encoder *source_encoder;
15552         int index_mask = 0;
15553         int entry = 0;
15554
15555         for_each_intel_encoder(dev, source_encoder) {
15556                 if (encoders_cloneable(encoder, source_encoder))
15557                         index_mask |= (1 << entry);
15558
15559                 entry++;
15560         }
15561
15562         return index_mask;
15563 }
15564
15565 static bool has_edp_a(struct drm_i915_private *dev_priv)
15566 {
15567         if (!IS_MOBILE(dev_priv))
15568                 return false;
15569
15570         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
15571                 return false;
15572
15573         if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
15574                 return false;
15575
15576         return true;
15577 }
15578
15579 static bool intel_crt_present(struct drm_i915_private *dev_priv)
15580 {
15581         if (INTEL_GEN(dev_priv) >= 9)
15582                 return false;
15583
15584         if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
15585                 return false;
15586
15587         if (IS_CHERRYVIEW(dev_priv))
15588                 return false;
15589
15590         if (HAS_PCH_LPT_H(dev_priv) &&
15591             I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
15592                 return false;
15593
15594         /* DDI E can't be used if DDI A requires 4 lanes */
15595         if (HAS_DDI(dev_priv) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
15596                 return false;
15597
15598         if (!dev_priv->vbt.int_crt_support)
15599                 return false;
15600
15601         return true;
15602 }
15603
15604 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
15605 {
15606         int pps_num;
15607         int pps_idx;
15608
15609         if (HAS_DDI(dev_priv))
15610                 return;
15611         /*
15612          * This w/a is needed at least on CPT/PPT, but to be sure apply it
15613          * everywhere where registers can be write protected.
15614          */
15615         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15616                 pps_num = 2;
15617         else
15618                 pps_num = 1;
15619
15620         for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
15621                 u32 val = I915_READ(PP_CONTROL(pps_idx));
15622
15623                 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
15624                 I915_WRITE(PP_CONTROL(pps_idx), val);
15625         }
15626 }
15627
15628 static void intel_pps_init(struct drm_i915_private *dev_priv)
15629 {
15630         if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv))
15631                 dev_priv->pps_mmio_base = PCH_PPS_BASE;
15632         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15633                 dev_priv->pps_mmio_base = VLV_PPS_BASE;
15634         else
15635                 dev_priv->pps_mmio_base = PPS_BASE;
15636
15637         intel_pps_unlock_regs_wa(dev_priv);
15638 }
15639
15640 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
15641 {
15642         struct intel_encoder *encoder;
15643         bool dpd_is_edp = false;
15644
15645         intel_pps_init(dev_priv);
15646
15647         /*
15648          * intel_edp_init_connector() depends on this completing first, to
15649          * prevent the registeration of both eDP and LVDS and the incorrect
15650          * sharing of the PPS.
15651          */
15652         intel_lvds_init(dev_priv);
15653
15654         if (intel_crt_present(dev_priv))
15655                 intel_crt_init(dev_priv);
15656
15657         if (IS_GEN9_LP(dev_priv)) {
15658                 /*
15659                  * FIXME: Broxton doesn't support port detection via the
15660                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
15661                  * detect the ports.
15662                  */
15663                 intel_ddi_init(dev_priv, PORT_A);
15664                 intel_ddi_init(dev_priv, PORT_B);
15665                 intel_ddi_init(dev_priv, PORT_C);
15666
15667                 intel_dsi_init(dev_priv);
15668         } else if (HAS_DDI(dev_priv)) {
15669                 int found;
15670
15671                 /*
15672                  * Haswell uses DDI functions to detect digital outputs.
15673                  * On SKL pre-D0 the strap isn't connected, so we assume
15674                  * it's there.
15675                  */
15676                 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
15677                 /* WaIgnoreDDIAStrap: skl */
15678                 if (found || IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
15679                         intel_ddi_init(dev_priv, PORT_A);
15680
15681                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
15682                  * register */
15683                 found = I915_READ(SFUSE_STRAP);
15684
15685                 if (found & SFUSE_STRAP_DDIB_DETECTED)
15686                         intel_ddi_init(dev_priv, PORT_B);
15687                 if (found & SFUSE_STRAP_DDIC_DETECTED)
15688                         intel_ddi_init(dev_priv, PORT_C);
15689                 if (found & SFUSE_STRAP_DDID_DETECTED)
15690                         intel_ddi_init(dev_priv, PORT_D);
15691                 /*
15692                  * On SKL we don't have a way to detect DDI-E so we rely on VBT.
15693                  */
15694                 if ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) &&
15695                     (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
15696                      dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
15697                      dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
15698                         intel_ddi_init(dev_priv, PORT_E);
15699
15700         } else if (HAS_PCH_SPLIT(dev_priv)) {
15701                 int found;
15702                 dpd_is_edp = intel_dp_is_edp(dev_priv, PORT_D);
15703
15704                 if (has_edp_a(dev_priv))
15705                         intel_dp_init(dev_priv, DP_A, PORT_A);
15706
15707                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
15708                         /* PCH SDVOB multiplex with HDMIB */
15709                         found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
15710                         if (!found)
15711                                 intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
15712                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
15713                                 intel_dp_init(dev_priv, PCH_DP_B, PORT_B);
15714                 }
15715
15716                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
15717                         intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
15718
15719                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
15720                         intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
15721
15722                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
15723                         intel_dp_init(dev_priv, PCH_DP_C, PORT_C);
15724
15725                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
15726                         intel_dp_init(dev_priv, PCH_DP_D, PORT_D);
15727         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15728                 bool has_edp, has_port;
15729
15730                 /*
15731                  * The DP_DETECTED bit is the latched state of the DDC
15732                  * SDA pin at boot. However since eDP doesn't require DDC
15733                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
15734                  * eDP ports may have been muxed to an alternate function.
15735                  * Thus we can't rely on the DP_DETECTED bit alone to detect
15736                  * eDP ports. Consult the VBT as well as DP_DETECTED to
15737                  * detect eDP ports.
15738                  *
15739                  * Sadly the straps seem to be missing sometimes even for HDMI
15740                  * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
15741                  * and VBT for the presence of the port. Additionally we can't
15742                  * trust the port type the VBT declares as we've seen at least
15743                  * HDMI ports that the VBT claim are DP or eDP.
15744                  */
15745                 has_edp = intel_dp_is_edp(dev_priv, PORT_B);
15746                 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
15747                 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
15748                         has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B);
15749                 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
15750                         intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
15751
15752                 has_edp = intel_dp_is_edp(dev_priv, PORT_C);
15753                 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
15754                 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
15755                         has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C);
15756                 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
15757                         intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
15758
15759                 if (IS_CHERRYVIEW(dev_priv)) {
15760                         /*
15761                          * eDP not supported on port D,
15762                          * so no need to worry about it
15763                          */
15764                         has_port = intel_bios_is_port_present(dev_priv, PORT_D);
15765                         if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
15766                                 intel_dp_init(dev_priv, CHV_DP_D, PORT_D);
15767                         if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
15768                                 intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
15769                 }
15770
15771                 intel_dsi_init(dev_priv);
15772         } else if (!IS_GEN2(dev_priv) && !IS_PINEVIEW(dev_priv)) {
15773                 bool found = false;
15774
15775                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
15776                         DRM_DEBUG_KMS("probing SDVOB\n");
15777                         found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
15778                         if (!found && IS_G4X(dev_priv)) {
15779                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
15780                                 intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
15781                         }
15782
15783                         if (!found && IS_G4X(dev_priv))
15784                                 intel_dp_init(dev_priv, DP_B, PORT_B);
15785                 }
15786
15787                 /* Before G4X SDVOC doesn't have its own detect register */
15788
15789                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
15790                         DRM_DEBUG_KMS("probing SDVOC\n");
15791                         found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
15792                 }
15793
15794                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
15795
15796                         if (IS_G4X(dev_priv)) {
15797                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
15798                                 intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
15799                         }
15800                         if (IS_G4X(dev_priv))
15801                                 intel_dp_init(dev_priv, DP_C, PORT_C);
15802                 }
15803
15804                 if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
15805                         intel_dp_init(dev_priv, DP_D, PORT_D);
15806         } else if (IS_GEN2(dev_priv))
15807                 intel_dvo_init(dev_priv);
15808
15809         if (SUPPORTS_TV(dev_priv))
15810                 intel_tv_init(dev_priv);
15811
15812         intel_psr_init(dev_priv);
15813
15814         for_each_intel_encoder(&dev_priv->drm, encoder) {
15815                 encoder->base.possible_crtcs = encoder->crtc_mask;
15816                 encoder->base.possible_clones =
15817                         intel_encoder_clones(encoder);
15818         }
15819
15820         intel_init_pch_refclk(dev_priv);
15821
15822         drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
15823 }
15824
15825 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
15826 {
15827         struct drm_device *dev = fb->dev;
15828         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
15829
15830         drm_framebuffer_cleanup(fb);
15831         mutex_lock(&dev->struct_mutex);
15832         WARN_ON(!intel_fb->obj->framebuffer_references--);
15833         i915_gem_object_put(intel_fb->obj);
15834         mutex_unlock(&dev->struct_mutex);
15835         kfree(intel_fb);
15836 }
15837
15838 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
15839                                                 struct drm_file *file,
15840                                                 unsigned int *handle)
15841 {
15842         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
15843         struct drm_i915_gem_object *obj = intel_fb->obj;
15844
15845         if (obj->userptr.mm) {
15846                 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
15847                 return -EINVAL;
15848         }
15849
15850         return drm_gem_handle_create(file, &obj->base, handle);
15851 }
15852
15853 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
15854                                         struct drm_file *file,
15855                                         unsigned flags, unsigned color,
15856                                         struct drm_clip_rect *clips,
15857                                         unsigned num_clips)
15858 {
15859         struct drm_device *dev = fb->dev;
15860         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
15861         struct drm_i915_gem_object *obj = intel_fb->obj;
15862
15863         mutex_lock(&dev->struct_mutex);
15864         if (obj->pin_display && obj->cache_dirty)
15865                 i915_gem_clflush_object(obj, true);
15866         intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
15867         mutex_unlock(&dev->struct_mutex);
15868
15869         return 0;
15870 }
15871
15872 static const struct drm_framebuffer_funcs intel_fb_funcs = {
15873         .destroy = intel_user_framebuffer_destroy,
15874         .create_handle = intel_user_framebuffer_create_handle,
15875         .dirty = intel_user_framebuffer_dirty,
15876 };
15877
15878 static
15879 u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv,
15880                          uint64_t fb_modifier, uint32_t pixel_format)
15881 {
15882         u32 gen = INTEL_INFO(dev_priv)->gen;
15883
15884         if (gen >= 9) {
15885                 int cpp = drm_format_plane_cpp(pixel_format, 0);
15886
15887                 /* "The stride in bytes must not exceed the of the size of 8K
15888                  *  pixels and 32K bytes."
15889                  */
15890                 return min(8192 * cpp, 32768);
15891         } else if (gen >= 5 && !IS_VALLEYVIEW(dev_priv) &&
15892                    !IS_CHERRYVIEW(dev_priv)) {
15893                 return 32*1024;
15894         } else if (gen >= 4) {
15895                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
15896                         return 16*1024;
15897                 else
15898                         return 32*1024;
15899         } else if (gen >= 3) {
15900                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
15901                         return 8*1024;
15902                 else
15903                         return 16*1024;
15904         } else {
15905                 /* XXX DSPC is limited to 4k tiled */
15906                 return 8*1024;
15907         }
15908 }
15909
15910 static int intel_framebuffer_init(struct drm_device *dev,
15911                                   struct intel_framebuffer *intel_fb,
15912                                   struct drm_mode_fb_cmd2 *mode_cmd,
15913                                   struct drm_i915_gem_object *obj)
15914 {
15915         struct drm_i915_private *dev_priv = to_i915(dev);
15916         unsigned int tiling = i915_gem_object_get_tiling(obj);
15917         int ret;
15918         u32 pitch_limit, stride_alignment;
15919         struct drm_format_name_buf format_name;
15920
15921         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
15922
15923         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
15924                 /*
15925                  * If there's a fence, enforce that
15926                  * the fb modifier and tiling mode match.
15927                  */
15928                 if (tiling != I915_TILING_NONE &&
15929                     tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
15930                         DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
15931                         return -EINVAL;
15932                 }
15933         } else {
15934                 if (tiling == I915_TILING_X) {
15935                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
15936                 } else if (tiling == I915_TILING_Y) {
15937                         DRM_DEBUG("No Y tiling for legacy addfb\n");
15938                         return -EINVAL;
15939                 }
15940         }
15941
15942         /* Passed in modifier sanity checking. */
15943         switch (mode_cmd->modifier[0]) {
15944         case I915_FORMAT_MOD_Y_TILED:
15945         case I915_FORMAT_MOD_Yf_TILED:
15946                 if (INTEL_GEN(dev_priv) < 9) {
15947                         DRM_DEBUG("Unsupported tiling 0x%llx!\n",
15948                                   mode_cmd->modifier[0]);
15949                         return -EINVAL;
15950                 }
15951         case DRM_FORMAT_MOD_NONE:
15952         case I915_FORMAT_MOD_X_TILED:
15953                 break;
15954         default:
15955                 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
15956                           mode_cmd->modifier[0]);
15957                 return -EINVAL;
15958         }
15959
15960         /*
15961          * gen2/3 display engine uses the fence if present,
15962          * so the tiling mode must match the fb modifier exactly.
15963          */
15964         if (INTEL_INFO(dev_priv)->gen < 4 &&
15965             tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
15966                 DRM_DEBUG("tiling_mode must match fb modifier exactly on gen2/3\n");
15967                 return -EINVAL;
15968         }
15969
15970         stride_alignment = intel_fb_stride_alignment(dev_priv,
15971                                                      mode_cmd->modifier[0],
15972                                                      mode_cmd->pixel_format);
15973         if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
15974                 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
15975                           mode_cmd->pitches[0], stride_alignment);
15976                 return -EINVAL;
15977         }
15978
15979         pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->modifier[0],
15980                                            mode_cmd->pixel_format);
15981         if (mode_cmd->pitches[0] > pitch_limit) {
15982                 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
15983                           mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
15984                           "tiled" : "linear",
15985                           mode_cmd->pitches[0], pitch_limit);
15986                 return -EINVAL;
15987         }
15988
15989         /*
15990          * If there's a fence, enforce that
15991          * the fb pitch and fence stride match.
15992          */
15993         if (tiling != I915_TILING_NONE &&
15994             mode_cmd->pitches[0] != i915_gem_object_get_stride(obj)) {
15995                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
15996                           mode_cmd->pitches[0],
15997                           i915_gem_object_get_stride(obj));
15998                 return -EINVAL;
15999         }
16000
16001         /* Reject formats not supported by any plane early. */
16002         switch (mode_cmd->pixel_format) {
16003         case DRM_FORMAT_C8:
16004         case DRM_FORMAT_RGB565:
16005         case DRM_FORMAT_XRGB8888:
16006         case DRM_FORMAT_ARGB8888:
16007                 break;
16008         case DRM_FORMAT_XRGB1555:
16009                 if (INTEL_GEN(dev_priv) > 3) {
16010                         DRM_DEBUG("unsupported pixel format: %s\n",
16011                                   drm_get_format_name(mode_cmd->pixel_format, &format_name));
16012                         return -EINVAL;
16013                 }
16014                 break;
16015         case DRM_FORMAT_ABGR8888:
16016                 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
16017                     INTEL_GEN(dev_priv) < 9) {
16018                         DRM_DEBUG("unsupported pixel format: %s\n",
16019                                   drm_get_format_name(mode_cmd->pixel_format, &format_name));
16020                         return -EINVAL;
16021                 }
16022                 break;
16023         case DRM_FORMAT_XBGR8888:
16024         case DRM_FORMAT_XRGB2101010:
16025         case DRM_FORMAT_XBGR2101010:
16026                 if (INTEL_GEN(dev_priv) < 4) {
16027                         DRM_DEBUG("unsupported pixel format: %s\n",
16028                                   drm_get_format_name(mode_cmd->pixel_format, &format_name));
16029                         return -EINVAL;
16030                 }
16031                 break;
16032         case DRM_FORMAT_ABGR2101010:
16033                 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
16034                         DRM_DEBUG("unsupported pixel format: %s\n",
16035                                   drm_get_format_name(mode_cmd->pixel_format, &format_name));
16036                         return -EINVAL;
16037                 }
16038                 break;
16039         case DRM_FORMAT_YUYV:
16040         case DRM_FORMAT_UYVY:
16041         case DRM_FORMAT_YVYU:
16042         case DRM_FORMAT_VYUY:
16043                 if (INTEL_GEN(dev_priv) < 5) {
16044                         DRM_DEBUG("unsupported pixel format: %s\n",
16045                                   drm_get_format_name(mode_cmd->pixel_format, &format_name));
16046                         return -EINVAL;
16047                 }
16048                 break;
16049         default:
16050                 DRM_DEBUG("unsupported pixel format: %s\n",
16051                           drm_get_format_name(mode_cmd->pixel_format, &format_name));
16052                 return -EINVAL;
16053         }
16054
16055         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
16056         if (mode_cmd->offsets[0] != 0)
16057                 return -EINVAL;
16058
16059         drm_helper_mode_fill_fb_struct(dev, &intel_fb->base, mode_cmd);
16060         intel_fb->obj = obj;
16061
16062         ret = intel_fill_fb_info(dev_priv, &intel_fb->base);
16063         if (ret)
16064                 return ret;
16065
16066         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
16067         if (ret) {
16068                 DRM_ERROR("framebuffer init failed %d\n", ret);
16069                 return ret;
16070         }
16071
16072         intel_fb->obj->framebuffer_references++;
16073
16074         return 0;
16075 }
16076
16077 static struct drm_framebuffer *
16078 intel_user_framebuffer_create(struct drm_device *dev,
16079                               struct drm_file *filp,
16080                               const struct drm_mode_fb_cmd2 *user_mode_cmd)
16081 {
16082         struct drm_framebuffer *fb;
16083         struct drm_i915_gem_object *obj;
16084         struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
16085
16086         obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
16087         if (!obj)
16088                 return ERR_PTR(-ENOENT);
16089
16090         fb = intel_framebuffer_create(dev, &mode_cmd, obj);
16091         if (IS_ERR(fb))
16092                 i915_gem_object_put(obj);
16093
16094         return fb;
16095 }
16096
16097 static void intel_atomic_state_free(struct drm_atomic_state *state)
16098 {
16099         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
16100
16101         drm_atomic_state_default_release(state);
16102
16103         i915_sw_fence_fini(&intel_state->commit_ready);
16104
16105         kfree(state);
16106 }
16107
16108 static const struct drm_mode_config_funcs intel_mode_funcs = {
16109         .fb_create = intel_user_framebuffer_create,
16110         .output_poll_changed = intel_fbdev_output_poll_changed,
16111         .atomic_check = intel_atomic_check,
16112         .atomic_commit = intel_atomic_commit,
16113         .atomic_state_alloc = intel_atomic_state_alloc,
16114         .atomic_state_clear = intel_atomic_state_clear,
16115         .atomic_state_free = intel_atomic_state_free,
16116 };
16117
16118 /**
16119  * intel_init_display_hooks - initialize the display modesetting hooks
16120  * @dev_priv: device private
16121  */
16122 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
16123 {
16124         if (INTEL_INFO(dev_priv)->gen >= 9) {
16125                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
16126                 dev_priv->display.get_initial_plane_config =
16127                         skylake_get_initial_plane_config;
16128                 dev_priv->display.crtc_compute_clock =
16129                         haswell_crtc_compute_clock;
16130                 dev_priv->display.crtc_enable = haswell_crtc_enable;
16131                 dev_priv->display.crtc_disable = haswell_crtc_disable;
16132         } else if (HAS_DDI(dev_priv)) {
16133                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
16134                 dev_priv->display.get_initial_plane_config =
16135                         ironlake_get_initial_plane_config;
16136                 dev_priv->display.crtc_compute_clock =
16137                         haswell_crtc_compute_clock;
16138                 dev_priv->display.crtc_enable = haswell_crtc_enable;
16139                 dev_priv->display.crtc_disable = haswell_crtc_disable;
16140         } else if (HAS_PCH_SPLIT(dev_priv)) {
16141                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
16142                 dev_priv->display.get_initial_plane_config =
16143                         ironlake_get_initial_plane_config;
16144                 dev_priv->display.crtc_compute_clock =
16145                         ironlake_crtc_compute_clock;
16146                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
16147                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
16148         } else if (IS_CHERRYVIEW(dev_priv)) {
16149                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
16150                 dev_priv->display.get_initial_plane_config =
16151                         i9xx_get_initial_plane_config;
16152                 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
16153                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
16154                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
16155         } else if (IS_VALLEYVIEW(dev_priv)) {
16156                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
16157                 dev_priv->display.get_initial_plane_config =
16158                         i9xx_get_initial_plane_config;
16159                 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
16160                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
16161                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
16162         } else if (IS_G4X(dev_priv)) {
16163                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
16164                 dev_priv->display.get_initial_plane_config =
16165                         i9xx_get_initial_plane_config;
16166                 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
16167                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
16168                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
16169         } else if (IS_PINEVIEW(dev_priv)) {
16170                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
16171                 dev_priv->display.get_initial_plane_config =
16172                         i9xx_get_initial_plane_config;
16173                 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
16174                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
16175                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
16176         } else if (!IS_GEN2(dev_priv)) {
16177                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
16178                 dev_priv->display.get_initial_plane_config =
16179                         i9xx_get_initial_plane_config;
16180                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
16181                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
16182                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
16183         } else {
16184                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
16185                 dev_priv->display.get_initial_plane_config =
16186                         i9xx_get_initial_plane_config;
16187                 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
16188                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
16189                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
16190         }
16191
16192         /* Returns the core display clock speed */
16193         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
16194                 dev_priv->display.get_display_clock_speed =
16195                         skylake_get_display_clock_speed;
16196         else if (IS_GEN9_LP(dev_priv))
16197                 dev_priv->display.get_display_clock_speed =
16198                         broxton_get_display_clock_speed;
16199         else if (IS_BROADWELL(dev_priv))
16200                 dev_priv->display.get_display_clock_speed =
16201                         broadwell_get_display_clock_speed;
16202         else if (IS_HASWELL(dev_priv))
16203                 dev_priv->display.get_display_clock_speed =
16204                         haswell_get_display_clock_speed;
16205         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
16206                 dev_priv->display.get_display_clock_speed =
16207                         valleyview_get_display_clock_speed;
16208         else if (IS_GEN5(dev_priv))
16209                 dev_priv->display.get_display_clock_speed =
16210                         ilk_get_display_clock_speed;
16211         else if (IS_I945G(dev_priv) || IS_I965G(dev_priv) ||
16212                  IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
16213                 dev_priv->display.get_display_clock_speed =
16214                         i945_get_display_clock_speed;
16215         else if (IS_GM45(dev_priv))
16216                 dev_priv->display.get_display_clock_speed =
16217                         gm45_get_display_clock_speed;
16218         else if (IS_I965GM(dev_priv))
16219                 dev_priv->display.get_display_clock_speed =
16220                         i965gm_get_display_clock_speed;
16221         else if (IS_PINEVIEW(dev_priv))
16222                 dev_priv->display.get_display_clock_speed =
16223                         pnv_get_display_clock_speed;
16224         else if (IS_G33(dev_priv) || IS_G4X(dev_priv))
16225                 dev_priv->display.get_display_clock_speed =
16226                         g33_get_display_clock_speed;
16227         else if (IS_I915G(dev_priv))
16228                 dev_priv->display.get_display_clock_speed =
16229                         i915_get_display_clock_speed;
16230         else if (IS_I945GM(dev_priv) || IS_I845G(dev_priv))
16231                 dev_priv->display.get_display_clock_speed =
16232                         i9xx_misc_get_display_clock_speed;
16233         else if (IS_I915GM(dev_priv))
16234                 dev_priv->display.get_display_clock_speed =
16235                         i915gm_get_display_clock_speed;
16236         else if (IS_I865G(dev_priv))
16237                 dev_priv->display.get_display_clock_speed =
16238                         i865_get_display_clock_speed;
16239         else if (IS_I85X(dev_priv))
16240                 dev_priv->display.get_display_clock_speed =
16241                         i85x_get_display_clock_speed;
16242         else { /* 830 */
16243                 WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n");
16244                 dev_priv->display.get_display_clock_speed =
16245                         i830_get_display_clock_speed;
16246         }
16247
16248         if (IS_GEN5(dev_priv)) {
16249                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
16250         } else if (IS_GEN6(dev_priv)) {
16251                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
16252         } else if (IS_IVYBRIDGE(dev_priv)) {
16253                 /* FIXME: detect B0+ stepping and use auto training */
16254                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
16255         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
16256                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
16257         }
16258
16259         if (IS_BROADWELL(dev_priv)) {
16260                 dev_priv->display.modeset_commit_cdclk =
16261                         broadwell_modeset_commit_cdclk;
16262                 dev_priv->display.modeset_calc_cdclk =
16263                         broadwell_modeset_calc_cdclk;
16264         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
16265                 dev_priv->display.modeset_commit_cdclk =
16266                         valleyview_modeset_commit_cdclk;
16267                 dev_priv->display.modeset_calc_cdclk =
16268                         valleyview_modeset_calc_cdclk;
16269         } else if (IS_GEN9_LP(dev_priv)) {
16270                 dev_priv->display.modeset_commit_cdclk =
16271                         bxt_modeset_commit_cdclk;
16272                 dev_priv->display.modeset_calc_cdclk =
16273                         bxt_modeset_calc_cdclk;
16274         } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
16275                 dev_priv->display.modeset_commit_cdclk =
16276                         skl_modeset_commit_cdclk;
16277                 dev_priv->display.modeset_calc_cdclk =
16278                         skl_modeset_calc_cdclk;
16279         }
16280
16281         if (dev_priv->info.gen >= 9)
16282                 dev_priv->display.update_crtcs = skl_update_crtcs;
16283         else
16284                 dev_priv->display.update_crtcs = intel_update_crtcs;
16285
16286         switch (INTEL_INFO(dev_priv)->gen) {
16287         case 2:
16288                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
16289                 break;
16290
16291         case 3:
16292                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
16293                 break;
16294
16295         case 4:
16296         case 5:
16297                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
16298                 break;
16299
16300         case 6:
16301                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
16302                 break;
16303         case 7:
16304         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
16305                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
16306                 break;
16307         case 9:
16308                 /* Drop through - unsupported since execlist only. */
16309         default:
16310                 /* Default just returns -ENODEV to indicate unsupported */
16311                 dev_priv->display.queue_flip = intel_default_queue_flip;
16312         }
16313 }
16314
16315 /*
16316  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
16317  * resume, or other times.  This quirk makes sure that's the case for
16318  * affected systems.
16319  */
16320 static void quirk_pipea_force(struct drm_device *dev)
16321 {
16322         struct drm_i915_private *dev_priv = to_i915(dev);
16323
16324         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
16325         DRM_INFO("applying pipe a force quirk\n");
16326 }
16327
16328 static void quirk_pipeb_force(struct drm_device *dev)
16329 {
16330         struct drm_i915_private *dev_priv = to_i915(dev);
16331
16332         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
16333         DRM_INFO("applying pipe b force quirk\n");
16334 }
16335
16336 /*
16337  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
16338  */
16339 static void quirk_ssc_force_disable(struct drm_device *dev)
16340 {
16341         struct drm_i915_private *dev_priv = to_i915(dev);
16342         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
16343         DRM_INFO("applying lvds SSC disable quirk\n");
16344 }
16345
16346 /*
16347  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
16348  * brightness value
16349  */
16350 static void quirk_invert_brightness(struct drm_device *dev)
16351 {
16352         struct drm_i915_private *dev_priv = to_i915(dev);
16353         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
16354         DRM_INFO("applying inverted panel brightness quirk\n");
16355 }
16356
16357 /* Some VBT's incorrectly indicate no backlight is present */
16358 static void quirk_backlight_present(struct drm_device *dev)
16359 {
16360         struct drm_i915_private *dev_priv = to_i915(dev);
16361         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
16362         DRM_INFO("applying backlight present quirk\n");
16363 }
16364
16365 struct intel_quirk {
16366         int device;
16367         int subsystem_vendor;
16368         int subsystem_device;
16369         void (*hook)(struct drm_device *dev);
16370 };
16371
16372 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
16373 struct intel_dmi_quirk {
16374         void (*hook)(struct drm_device *dev);
16375         const struct dmi_system_id (*dmi_id_list)[];
16376 };
16377
16378 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
16379 {
16380         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
16381         return 1;
16382 }
16383
16384 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
16385         {
16386                 .dmi_id_list = &(const struct dmi_system_id[]) {
16387                         {
16388                                 .callback = intel_dmi_reverse_brightness,
16389                                 .ident = "NCR Corporation",
16390                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
16391                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
16392                                 },
16393                         },
16394                         { }  /* terminating entry */
16395                 },
16396                 .hook = quirk_invert_brightness,
16397         },
16398 };
16399
16400 static struct intel_quirk intel_quirks[] = {
16401         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
16402         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
16403
16404         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
16405         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
16406
16407         /* 830 needs to leave pipe A & dpll A up */
16408         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
16409
16410         /* 830 needs to leave pipe B & dpll B up */
16411         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
16412
16413         /* Lenovo U160 cannot use SSC on LVDS */
16414         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
16415
16416         /* Sony Vaio Y cannot use SSC on LVDS */
16417         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
16418
16419         /* Acer Aspire 5734Z must invert backlight brightness */
16420         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
16421
16422         /* Acer/eMachines G725 */
16423         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
16424
16425         /* Acer/eMachines e725 */
16426         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
16427
16428         /* Acer/Packard Bell NCL20 */
16429         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
16430
16431         /* Acer Aspire 4736Z */
16432         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
16433
16434         /* Acer Aspire 5336 */
16435         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
16436
16437         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
16438         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
16439
16440         /* Acer C720 Chromebook (Core i3 4005U) */
16441         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
16442
16443         /* Apple Macbook 2,1 (Core 2 T7400) */
16444         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
16445
16446         /* Apple Macbook 4,1 */
16447         { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
16448
16449         /* Toshiba CB35 Chromebook (Celeron 2955U) */
16450         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
16451
16452         /* HP Chromebook 14 (Celeron 2955U) */
16453         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
16454
16455         /* Dell Chromebook 11 */
16456         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
16457
16458         /* Dell Chromebook 11 (2015 version) */
16459         { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
16460 };
16461
16462 static void intel_init_quirks(struct drm_device *dev)
16463 {
16464         struct pci_dev *d = dev->pdev;
16465         int i;
16466
16467         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
16468                 struct intel_quirk *q = &intel_quirks[i];
16469
16470                 if (d->device == q->device &&
16471                     (d->subsystem_vendor == q->subsystem_vendor ||
16472                      q->subsystem_vendor == PCI_ANY_ID) &&
16473                     (d->subsystem_device == q->subsystem_device ||
16474                      q->subsystem_device == PCI_ANY_ID))
16475                         q->hook(dev);
16476         }
16477         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
16478                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
16479                         intel_dmi_quirks[i].hook(dev);
16480         }
16481 }
16482
16483 /* Disable the VGA plane that we never use */
16484 static void i915_disable_vga(struct drm_i915_private *dev_priv)
16485 {
16486         struct pci_dev *pdev = dev_priv->drm.pdev;
16487         u8 sr1;
16488         i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
16489
16490         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
16491         vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
16492         outb(SR01, VGA_SR_INDEX);
16493         sr1 = inb(VGA_SR_DATA);
16494         outb(sr1 | 1<<5, VGA_SR_DATA);
16495         vga_put(pdev, VGA_RSRC_LEGACY_IO);
16496         udelay(300);
16497
16498         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
16499         POSTING_READ(vga_reg);
16500 }
16501
16502 void intel_modeset_init_hw(struct drm_device *dev)
16503 {
16504         struct drm_i915_private *dev_priv = to_i915(dev);
16505
16506         intel_update_cdclk(dev_priv);
16507
16508         dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
16509
16510         intel_init_clock_gating(dev_priv);
16511 }
16512
16513 /*
16514  * Calculate what we think the watermarks should be for the state we've read
16515  * out of the hardware and then immediately program those watermarks so that
16516  * we ensure the hardware settings match our internal state.
16517  *
16518  * We can calculate what we think WM's should be by creating a duplicate of the
16519  * current state (which was constructed during hardware readout) and running it
16520  * through the atomic check code to calculate new watermark values in the
16521  * state object.
16522  */
16523 static void sanitize_watermarks(struct drm_device *dev)
16524 {
16525         struct drm_i915_private *dev_priv = to_i915(dev);
16526         struct drm_atomic_state *state;
16527         struct intel_atomic_state *intel_state;
16528         struct drm_crtc *crtc;
16529         struct drm_crtc_state *cstate;
16530         struct drm_modeset_acquire_ctx ctx;
16531         int ret;
16532         int i;
16533
16534         /* Only supported on platforms that use atomic watermark design */
16535         if (!dev_priv->display.optimize_watermarks)
16536                 return;
16537
16538         /*
16539          * We need to hold connection_mutex before calling duplicate_state so
16540          * that the connector loop is protected.
16541          */
16542         drm_modeset_acquire_init(&ctx, 0);
16543 retry:
16544         ret = drm_modeset_lock_all_ctx(dev, &ctx);
16545         if (ret == -EDEADLK) {
16546                 drm_modeset_backoff(&ctx);
16547                 goto retry;
16548         } else if (WARN_ON(ret)) {
16549                 goto fail;
16550         }
16551
16552         state = drm_atomic_helper_duplicate_state(dev, &ctx);
16553         if (WARN_ON(IS_ERR(state)))
16554                 goto fail;
16555
16556         intel_state = to_intel_atomic_state(state);
16557
16558         /*
16559          * Hardware readout is the only time we don't want to calculate
16560          * intermediate watermarks (since we don't trust the current
16561          * watermarks).
16562          */
16563         intel_state->skip_intermediate_wm = true;
16564
16565         ret = intel_atomic_check(dev, state);
16566         if (ret) {
16567                 /*
16568                  * If we fail here, it means that the hardware appears to be
16569                  * programmed in a way that shouldn't be possible, given our
16570                  * understanding of watermark requirements.  This might mean a
16571                  * mistake in the hardware readout code or a mistake in the
16572                  * watermark calculations for a given platform.  Raise a WARN
16573                  * so that this is noticeable.
16574                  *
16575                  * If this actually happens, we'll have to just leave the
16576                  * BIOS-programmed watermarks untouched and hope for the best.
16577                  */
16578                 WARN(true, "Could not determine valid watermarks for inherited state\n");
16579                 goto put_state;
16580         }
16581
16582         /* Write calculated watermark values back */
16583         for_each_crtc_in_state(state, crtc, cstate, i) {
16584                 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
16585
16586                 cs->wm.need_postvbl_update = true;
16587                 dev_priv->display.optimize_watermarks(intel_state, cs);
16588         }
16589
16590 put_state:
16591         drm_atomic_state_put(state);
16592 fail:
16593         drm_modeset_drop_locks(&ctx);
16594         drm_modeset_acquire_fini(&ctx);
16595 }
16596
16597 int intel_modeset_init(struct drm_device *dev)
16598 {
16599         struct drm_i915_private *dev_priv = to_i915(dev);
16600         struct i915_ggtt *ggtt = &dev_priv->ggtt;
16601         enum pipe pipe;
16602         struct intel_crtc *crtc;
16603
16604         drm_mode_config_init(dev);
16605
16606         dev->mode_config.min_width = 0;
16607         dev->mode_config.min_height = 0;
16608
16609         dev->mode_config.preferred_depth = 24;
16610         dev->mode_config.prefer_shadow = 1;
16611
16612         dev->mode_config.allow_fb_modifiers = true;
16613
16614         dev->mode_config.funcs = &intel_mode_funcs;
16615
16616         intel_init_quirks(dev);
16617
16618         intel_init_pm(dev_priv);
16619
16620         if (INTEL_INFO(dev_priv)->num_pipes == 0)
16621                 return 0;
16622
16623         /*
16624          * There may be no VBT; and if the BIOS enabled SSC we can
16625          * just keep using it to avoid unnecessary flicker.  Whereas if the
16626          * BIOS isn't using it, don't assume it will work even if the VBT
16627          * indicates as much.
16628          */
16629         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
16630                 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
16631                                             DREF_SSC1_ENABLE);
16632
16633                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
16634                         DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
16635                                      bios_lvds_use_ssc ? "en" : "dis",
16636                                      dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
16637                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
16638                 }
16639         }
16640
16641         if (IS_GEN2(dev_priv)) {
16642                 dev->mode_config.max_width = 2048;
16643                 dev->mode_config.max_height = 2048;
16644         } else if (IS_GEN3(dev_priv)) {
16645                 dev->mode_config.max_width = 4096;
16646                 dev->mode_config.max_height = 4096;
16647         } else {
16648                 dev->mode_config.max_width = 8192;
16649                 dev->mode_config.max_height = 8192;
16650         }
16651
16652         if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
16653                 dev->mode_config.cursor_width = IS_I845G(dev_priv) ? 64 : 512;
16654                 dev->mode_config.cursor_height = 1023;
16655         } else if (IS_GEN2(dev_priv)) {
16656                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
16657                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
16658         } else {
16659                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
16660                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
16661         }
16662
16663         dev->mode_config.fb_base = ggtt->mappable_base;
16664
16665         DRM_DEBUG_KMS("%d display pipe%s available.\n",
16666                       INTEL_INFO(dev_priv)->num_pipes,
16667                       INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : "");
16668
16669         for_each_pipe(dev_priv, pipe) {
16670                 int ret;
16671
16672                 ret = intel_crtc_init(dev_priv, pipe);
16673                 if (ret) {
16674                         drm_mode_config_cleanup(dev);
16675                         return ret;
16676                 }
16677         }
16678
16679         intel_update_czclk(dev_priv);
16680         intel_update_cdclk(dev_priv);
16681         dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
16682
16683         intel_shared_dpll_init(dev);
16684
16685         if (dev_priv->max_cdclk_freq == 0)
16686                 intel_update_max_cdclk(dev_priv);
16687
16688         /* Just disable it once at startup */
16689         i915_disable_vga(dev_priv);
16690         intel_setup_outputs(dev_priv);
16691
16692         drm_modeset_lock_all(dev);
16693         intel_modeset_setup_hw_state(dev);
16694         drm_modeset_unlock_all(dev);
16695
16696         for_each_intel_crtc(dev, crtc) {
16697                 struct intel_initial_plane_config plane_config = {};
16698
16699                 if (!crtc->active)
16700                         continue;
16701
16702                 /*
16703                  * Note that reserving the BIOS fb up front prevents us
16704                  * from stuffing other stolen allocations like the ring
16705                  * on top.  This prevents some ugliness at boot time, and
16706                  * can even allow for smooth boot transitions if the BIOS
16707                  * fb is large enough for the active pipe configuration.
16708                  */
16709                 dev_priv->display.get_initial_plane_config(crtc,
16710                                                            &plane_config);
16711
16712                 /*
16713                  * If the fb is shared between multiple heads, we'll
16714                  * just get the first one.
16715                  */
16716                 intel_find_initial_plane_obj(crtc, &plane_config);
16717         }
16718
16719         /*
16720          * Make sure hardware watermarks really match the state we read out.
16721          * Note that we need to do this after reconstructing the BIOS fb's
16722          * since the watermark calculation done here will use pstate->fb.
16723          */
16724         sanitize_watermarks(dev);
16725
16726         return 0;
16727 }
16728
16729 static void intel_enable_pipe_a(struct drm_device *dev)
16730 {
16731         struct intel_connector *connector;
16732         struct drm_connector *crt = NULL;
16733         struct intel_load_detect_pipe load_detect_temp;
16734         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
16735
16736         /* We can't just switch on the pipe A, we need to set things up with a
16737          * proper mode and output configuration. As a gross hack, enable pipe A
16738          * by enabling the load detect pipe once. */
16739         for_each_intel_connector(dev, connector) {
16740                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
16741                         crt = &connector->base;
16742                         break;
16743                 }
16744         }
16745
16746         if (!crt)
16747                 return;
16748
16749         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
16750                 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
16751 }
16752
16753 static bool
16754 intel_check_plane_mapping(struct intel_crtc *crtc)
16755 {
16756         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
16757         u32 val;
16758
16759         if (INTEL_INFO(dev_priv)->num_pipes == 1)
16760                 return true;
16761
16762         val = I915_READ(DSPCNTR(!crtc->plane));
16763
16764         if ((val & DISPLAY_PLANE_ENABLE) &&
16765             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
16766                 return false;
16767
16768         return true;
16769 }
16770
16771 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
16772 {
16773         struct drm_device *dev = crtc->base.dev;
16774         struct intel_encoder *encoder;
16775
16776         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
16777                 return true;
16778
16779         return false;
16780 }
16781
16782 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
16783 {
16784         struct drm_device *dev = encoder->base.dev;
16785         struct intel_connector *connector;
16786
16787         for_each_connector_on_encoder(dev, &encoder->base, connector)
16788                 return connector;
16789
16790         return NULL;
16791 }
16792
16793 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
16794                               enum transcoder pch_transcoder)
16795 {
16796         return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
16797                 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == TRANSCODER_A);
16798 }
16799
16800 static void intel_sanitize_crtc(struct intel_crtc *crtc)
16801 {
16802         struct drm_device *dev = crtc->base.dev;
16803         struct drm_i915_private *dev_priv = to_i915(dev);
16804         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
16805
16806         /* Clear any frame start delays used for debugging left by the BIOS */
16807         if (!transcoder_is_dsi(cpu_transcoder)) {
16808                 i915_reg_t reg = PIPECONF(cpu_transcoder);
16809
16810                 I915_WRITE(reg,
16811                            I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
16812         }
16813
16814         /* restore vblank interrupts to correct state */
16815         drm_crtc_vblank_reset(&crtc->base);
16816         if (crtc->active) {
16817                 struct intel_plane *plane;
16818
16819                 drm_crtc_vblank_on(&crtc->base);
16820
16821                 /* Disable everything but the primary plane */
16822                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
16823                         if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
16824                                 continue;
16825
16826                         plane->disable_plane(&plane->base, &crtc->base);
16827                 }
16828         }
16829
16830         /* We need to sanitize the plane -> pipe mapping first because this will
16831          * disable the crtc (and hence change the state) if it is wrong. Note
16832          * that gen4+ has a fixed plane -> pipe mapping.  */
16833         if (INTEL_GEN(dev_priv) < 4 && !intel_check_plane_mapping(crtc)) {
16834                 bool plane;
16835
16836                 DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n",
16837                               crtc->base.base.id, crtc->base.name);
16838
16839                 /* Pipe has the wrong plane attached and the plane is active.
16840                  * Temporarily change the plane mapping and disable everything
16841                  * ...  */
16842                 plane = crtc->plane;
16843                 crtc->base.primary->state->visible = true;
16844                 crtc->plane = !plane;
16845                 intel_crtc_disable_noatomic(&crtc->base);
16846                 crtc->plane = plane;
16847         }
16848
16849         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
16850             crtc->pipe == PIPE_A && !crtc->active) {
16851                 /* BIOS forgot to enable pipe A, this mostly happens after
16852                  * resume. Force-enable the pipe to fix this, the update_dpms
16853                  * call below we restore the pipe to the right state, but leave
16854                  * the required bits on. */
16855                 intel_enable_pipe_a(dev);
16856         }
16857
16858         /* Adjust the state of the output pipe according to whether we
16859          * have active connectors/encoders. */
16860         if (crtc->active && !intel_crtc_has_encoders(crtc))
16861                 intel_crtc_disable_noatomic(&crtc->base);
16862
16863         if (crtc->active || HAS_GMCH_DISPLAY(dev_priv)) {
16864                 /*
16865                  * We start out with underrun reporting disabled to avoid races.
16866                  * For correct bookkeeping mark this on active crtcs.
16867                  *
16868                  * Also on gmch platforms we dont have any hardware bits to
16869                  * disable the underrun reporting. Which means we need to start
16870                  * out with underrun reporting disabled also on inactive pipes,
16871                  * since otherwise we'll complain about the garbage we read when
16872                  * e.g. coming up after runtime pm.
16873                  *
16874                  * No protection against concurrent access is required - at
16875                  * worst a fifo underrun happens which also sets this to false.
16876                  */
16877                 crtc->cpu_fifo_underrun_disabled = true;
16878                 /*
16879                  * We track the PCH trancoder underrun reporting state
16880                  * within the crtc. With crtc for pipe A housing the underrun
16881                  * reporting state for PCH transcoder A, crtc for pipe B housing
16882                  * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
16883                  * and marking underrun reporting as disabled for the non-existing
16884                  * PCH transcoders B and C would prevent enabling the south
16885                  * error interrupt (see cpt_can_enable_serr_int()).
16886                  */
16887                 if (has_pch_trancoder(dev_priv, (enum transcoder)crtc->pipe))
16888                         crtc->pch_fifo_underrun_disabled = true;
16889         }
16890 }
16891
16892 static void intel_sanitize_encoder(struct intel_encoder *encoder)
16893 {
16894         struct intel_connector *connector;
16895
16896         /* We need to check both for a crtc link (meaning that the
16897          * encoder is active and trying to read from a pipe) and the
16898          * pipe itself being active. */
16899         bool has_active_crtc = encoder->base.crtc &&
16900                 to_intel_crtc(encoder->base.crtc)->active;
16901
16902         connector = intel_encoder_find_connector(encoder);
16903         if (connector && !has_active_crtc) {
16904                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
16905                               encoder->base.base.id,
16906                               encoder->base.name);
16907
16908                 /* Connector is active, but has no active pipe. This is
16909                  * fallout from our resume register restoring. Disable
16910                  * the encoder manually again. */
16911                 if (encoder->base.crtc) {
16912                         struct drm_crtc_state *crtc_state = encoder->base.crtc->state;
16913
16914                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
16915                                       encoder->base.base.id,
16916                                       encoder->base.name);
16917                         encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
16918                         if (encoder->post_disable)
16919                                 encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
16920                 }
16921                 encoder->base.crtc = NULL;
16922
16923                 /* Inconsistent output/port/pipe state happens presumably due to
16924                  * a bug in one of the get_hw_state functions. Or someplace else
16925                  * in our code, like the register restore mess on resume. Clamp
16926                  * things to off as a safer default. */
16927
16928                 connector->base.dpms = DRM_MODE_DPMS_OFF;
16929                 connector->base.encoder = NULL;
16930         }
16931         /* Enabled encoders without active connectors will be fixed in
16932          * the crtc fixup. */
16933 }
16934
16935 void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv)
16936 {
16937         i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
16938
16939         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
16940                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
16941                 i915_disable_vga(dev_priv);
16942         }
16943 }
16944
16945 void i915_redisable_vga(struct drm_i915_private *dev_priv)
16946 {
16947         /* This function can be called both from intel_modeset_setup_hw_state or
16948          * at a very early point in our resume sequence, where the power well
16949          * structures are not yet restored. Since this function is at a very
16950          * paranoid "someone might have enabled VGA while we were not looking"
16951          * level, just check if the power well is enabled instead of trying to
16952          * follow the "don't touch the power well if we don't need it" policy
16953          * the rest of the driver uses. */
16954         if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
16955                 return;
16956
16957         i915_redisable_vga_power_on(dev_priv);
16958
16959         intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
16960 }
16961
16962 static bool primary_get_hw_state(struct intel_plane *plane)
16963 {
16964         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
16965
16966         return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
16967 }
16968
16969 /* FIXME read out full plane state for all planes */
16970 static void readout_plane_state(struct intel_crtc *crtc)
16971 {
16972         struct drm_plane *primary = crtc->base.primary;
16973         struct intel_plane_state *plane_state =
16974                 to_intel_plane_state(primary->state);
16975
16976         plane_state->base.visible = crtc->active &&
16977                 primary_get_hw_state(to_intel_plane(primary));
16978
16979         if (plane_state->base.visible)
16980                 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
16981 }
16982
16983 static void intel_modeset_readout_hw_state(struct drm_device *dev)
16984 {
16985         struct drm_i915_private *dev_priv = to_i915(dev);
16986         enum pipe pipe;
16987         struct intel_crtc *crtc;
16988         struct intel_encoder *encoder;
16989         struct intel_connector *connector;
16990         int i;
16991
16992         dev_priv->active_crtcs = 0;
16993
16994         for_each_intel_crtc(dev, crtc) {
16995                 struct intel_crtc_state *crtc_state =
16996                         to_intel_crtc_state(crtc->base.state);
16997
16998                 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
16999                 memset(crtc_state, 0, sizeof(*crtc_state));
17000                 crtc_state->base.crtc = &crtc->base;
17001
17002                 crtc_state->base.active = crtc_state->base.enable =
17003                         dev_priv->display.get_pipe_config(crtc, crtc_state);
17004
17005                 crtc->base.enabled = crtc_state->base.enable;
17006                 crtc->active = crtc_state->base.active;
17007
17008                 if (crtc_state->base.active)
17009                         dev_priv->active_crtcs |= 1 << crtc->pipe;
17010
17011                 readout_plane_state(crtc);
17012
17013                 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
17014                               crtc->base.base.id, crtc->base.name,
17015                               enableddisabled(crtc_state->base.active));
17016         }
17017
17018         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
17019                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
17020
17021                 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
17022                                                   &pll->state.hw_state);
17023                 pll->state.crtc_mask = 0;
17024                 for_each_intel_crtc(dev, crtc) {
17025                         struct intel_crtc_state *crtc_state =
17026                                 to_intel_crtc_state(crtc->base.state);
17027
17028                         if (crtc_state->base.active &&
17029                             crtc_state->shared_dpll == pll)
17030                                 pll->state.crtc_mask |= 1 << crtc->pipe;
17031                 }
17032                 pll->active_mask = pll->state.crtc_mask;
17033
17034                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
17035                               pll->name, pll->state.crtc_mask, pll->on);
17036         }
17037
17038         for_each_intel_encoder(dev, encoder) {
17039                 pipe = 0;
17040
17041                 if (encoder->get_hw_state(encoder, &pipe)) {
17042                         struct intel_crtc_state *crtc_state;
17043
17044                         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
17045                         crtc_state = to_intel_crtc_state(crtc->base.state);
17046
17047                         encoder->base.crtc = &crtc->base;
17048                         crtc_state->output_types |= 1 << encoder->type;
17049                         encoder->get_config(encoder, crtc_state);
17050                 } else {
17051                         encoder->base.crtc = NULL;
17052                 }
17053
17054                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
17055                               encoder->base.base.id, encoder->base.name,
17056                               enableddisabled(encoder->base.crtc),
17057                               pipe_name(pipe));
17058         }
17059
17060         for_each_intel_connector(dev, connector) {
17061                 if (connector->get_hw_state(connector)) {
17062                         connector->base.dpms = DRM_MODE_DPMS_ON;
17063
17064                         encoder = connector->encoder;
17065                         connector->base.encoder = &encoder->base;
17066
17067                         if (encoder->base.crtc &&
17068                             encoder->base.crtc->state->active) {
17069                                 /*
17070                                  * This has to be done during hardware readout
17071                                  * because anything calling .crtc_disable may
17072                                  * rely on the connector_mask being accurate.
17073                                  */
17074                                 encoder->base.crtc->state->connector_mask |=
17075                                         1 << drm_connector_index(&connector->base);
17076                                 encoder->base.crtc->state->encoder_mask |=
17077                                         1 << drm_encoder_index(&encoder->base);
17078                         }
17079
17080                 } else {
17081                         connector->base.dpms = DRM_MODE_DPMS_OFF;
17082                         connector->base.encoder = NULL;
17083                 }
17084                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
17085                               connector->base.base.id, connector->base.name,
17086                               enableddisabled(connector->base.encoder));
17087         }
17088
17089         for_each_intel_crtc(dev, crtc) {
17090                 struct intel_crtc_state *crtc_state =
17091                         to_intel_crtc_state(crtc->base.state);
17092                 int pixclk = 0;
17093
17094                 crtc->base.hwmode = crtc_state->base.adjusted_mode;
17095
17096                 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
17097                 if (crtc_state->base.active) {
17098                         intel_mode_from_pipe_config(&crtc->base.mode, crtc_state);
17099                         intel_mode_from_pipe_config(&crtc_state->base.adjusted_mode, crtc_state);
17100                         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
17101
17102                         /*
17103                          * The initial mode needs to be set in order to keep
17104                          * the atomic core happy. It wants a valid mode if the
17105                          * crtc's enabled, so we do the above call.
17106                          *
17107                          * But we don't set all the derived state fully, hence
17108                          * set a flag to indicate that a full recalculation is
17109                          * needed on the next commit.
17110                          */
17111                         crtc_state->base.mode.private_flags = I915_MODE_FLAG_INHERITED;
17112
17113                         if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
17114                                 pixclk = ilk_pipe_pixel_rate(crtc_state);
17115                         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
17116                                 pixclk = crtc_state->base.adjusted_mode.crtc_clock;
17117                         else
17118                                 WARN_ON(dev_priv->display.modeset_calc_cdclk);
17119
17120                         /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
17121                         if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
17122                                 pixclk = DIV_ROUND_UP(pixclk * 100, 95);
17123
17124                         drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
17125                         update_scanline_offset(crtc);
17126                 }
17127
17128                 dev_priv->min_pixclk[crtc->pipe] = pixclk;
17129
17130                 intel_pipe_config_sanity_check(dev_priv, crtc_state);
17131         }
17132 }
17133
17134 /* Scan out the current hw modeset state,
17135  * and sanitizes it to the current state
17136  */
17137 static void
17138 intel_modeset_setup_hw_state(struct drm_device *dev)
17139 {
17140         struct drm_i915_private *dev_priv = to_i915(dev);
17141         enum pipe pipe;
17142         struct intel_crtc *crtc;
17143         struct intel_encoder *encoder;
17144         int i;
17145
17146         intel_modeset_readout_hw_state(dev);
17147
17148         /* HW state is read out, now we need to sanitize this mess. */
17149         for_each_intel_encoder(dev, encoder) {
17150                 intel_sanitize_encoder(encoder);
17151         }
17152
17153         for_each_pipe(dev_priv, pipe) {
17154                 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
17155
17156                 intel_sanitize_crtc(crtc);
17157                 intel_dump_pipe_config(crtc, crtc->config,
17158                                        "[setup_hw_state]");
17159         }
17160
17161         intel_modeset_update_connector_atomic_state(dev);
17162
17163         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
17164                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
17165
17166                 if (!pll->on || pll->active_mask)
17167                         continue;
17168
17169                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
17170
17171                 pll->funcs.disable(dev_priv, pll);
17172                 pll->on = false;
17173         }
17174
17175         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
17176                 vlv_wm_get_hw_state(dev);
17177         else if (IS_GEN9(dev_priv))
17178                 skl_wm_get_hw_state(dev);
17179         else if (HAS_PCH_SPLIT(dev_priv))
17180                 ilk_wm_get_hw_state(dev);
17181
17182         for_each_intel_crtc(dev, crtc) {
17183                 unsigned long put_domains;
17184
17185                 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
17186                 if (WARN_ON(put_domains))
17187                         modeset_put_power_domains(dev_priv, put_domains);
17188         }
17189         intel_display_set_init_power(dev_priv, false);
17190
17191         intel_fbc_init_pipe_state(dev_priv);
17192 }
17193
17194 void intel_display_resume(struct drm_device *dev)
17195 {
17196         struct drm_i915_private *dev_priv = to_i915(dev);
17197         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
17198         struct drm_modeset_acquire_ctx ctx;
17199         int ret;
17200
17201         dev_priv->modeset_restore_state = NULL;
17202         if (state)
17203                 state->acquire_ctx = &ctx;
17204
17205         /*
17206          * This is a cludge because with real atomic modeset mode_config.mutex
17207          * won't be taken. Unfortunately some probed state like
17208          * audio_codec_enable is still protected by mode_config.mutex, so lock
17209          * it here for now.
17210          */
17211         mutex_lock(&dev->mode_config.mutex);
17212         drm_modeset_acquire_init(&ctx, 0);
17213
17214         while (1) {
17215                 ret = drm_modeset_lock_all_ctx(dev, &ctx);
17216                 if (ret != -EDEADLK)
17217                         break;
17218
17219                 drm_modeset_backoff(&ctx);
17220         }
17221
17222         if (!ret)
17223                 ret = __intel_display_resume(dev, state);
17224
17225         drm_modeset_drop_locks(&ctx);
17226         drm_modeset_acquire_fini(&ctx);
17227         mutex_unlock(&dev->mode_config.mutex);
17228
17229         if (ret)
17230                 DRM_ERROR("Restoring old state failed with %i\n", ret);
17231         if (state)
17232                 drm_atomic_state_put(state);
17233 }
17234
17235 void intel_modeset_gem_init(struct drm_device *dev)
17236 {
17237         struct drm_i915_private *dev_priv = to_i915(dev);
17238
17239         intel_init_gt_powersave(dev_priv);
17240
17241         intel_modeset_init_hw(dev);
17242
17243         intel_setup_overlay(dev_priv);
17244 }
17245
17246 int intel_connector_register(struct drm_connector *connector)
17247 {
17248         struct intel_connector *intel_connector = to_intel_connector(connector);
17249         int ret;
17250
17251         ret = intel_backlight_device_register(intel_connector);
17252         if (ret)
17253                 goto err;
17254
17255         return 0;
17256
17257 err:
17258         return ret;
17259 }
17260
17261 void intel_connector_unregister(struct drm_connector *connector)
17262 {
17263         struct intel_connector *intel_connector = to_intel_connector(connector);
17264
17265         intel_backlight_device_unregister(intel_connector);
17266         intel_panel_destroy_backlight(connector);
17267 }
17268
17269 void intel_modeset_cleanup(struct drm_device *dev)
17270 {
17271         struct drm_i915_private *dev_priv = to_i915(dev);
17272
17273         intel_disable_gt_powersave(dev_priv);
17274
17275         /*
17276          * Interrupts and polling as the first thing to avoid creating havoc.
17277          * Too much stuff here (turning of connectors, ...) would
17278          * experience fancy races otherwise.
17279          */
17280         intel_irq_uninstall(dev_priv);
17281
17282         /*
17283          * Due to the hpd irq storm handling the hotplug work can re-arm the
17284          * poll handlers. Hence disable polling after hpd handling is shut down.
17285          */
17286         drm_kms_helper_poll_fini(dev);
17287
17288         intel_unregister_dsm_handler();
17289
17290         intel_fbc_global_disable(dev_priv);
17291
17292         /* flush any delayed tasks or pending work */
17293         flush_scheduled_work();
17294
17295         drm_mode_config_cleanup(dev);
17296
17297         intel_cleanup_overlay(dev_priv);
17298
17299         intel_cleanup_gt_powersave(dev_priv);
17300
17301         intel_teardown_gmbus(dev_priv);
17302 }
17303
17304 void intel_connector_attach_encoder(struct intel_connector *connector,
17305                                     struct intel_encoder *encoder)
17306 {
17307         connector->encoder = encoder;
17308         drm_mode_connector_attach_encoder(&connector->base,
17309                                           &encoder->base);
17310 }
17311
17312 /*
17313  * set vga decode state - true == enable VGA decode
17314  */
17315 int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state)
17316 {
17317         unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
17318         u16 gmch_ctrl;
17319
17320         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
17321                 DRM_ERROR("failed to read control word\n");
17322                 return -EIO;
17323         }
17324
17325         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
17326                 return 0;
17327
17328         if (state)
17329                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
17330         else
17331                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
17332
17333         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
17334                 DRM_ERROR("failed to write control word\n");
17335                 return -EIO;
17336         }
17337
17338         return 0;
17339 }
17340
17341 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
17342
17343 struct intel_display_error_state {
17344
17345         u32 power_well_driver;
17346
17347         int num_transcoders;
17348
17349         struct intel_cursor_error_state {
17350                 u32 control;
17351                 u32 position;
17352                 u32 base;
17353                 u32 size;
17354         } cursor[I915_MAX_PIPES];
17355
17356         struct intel_pipe_error_state {
17357                 bool power_domain_on;
17358                 u32 source;
17359                 u32 stat;
17360         } pipe[I915_MAX_PIPES];
17361
17362         struct intel_plane_error_state {
17363                 u32 control;
17364                 u32 stride;
17365                 u32 size;
17366                 u32 pos;
17367                 u32 addr;
17368                 u32 surface;
17369                 u32 tile_offset;
17370         } plane[I915_MAX_PIPES];
17371
17372         struct intel_transcoder_error_state {
17373                 bool power_domain_on;
17374                 enum transcoder cpu_transcoder;
17375
17376                 u32 conf;
17377
17378                 u32 htotal;
17379                 u32 hblank;
17380                 u32 hsync;
17381                 u32 vtotal;
17382                 u32 vblank;
17383                 u32 vsync;
17384         } transcoder[4];
17385 };
17386
17387 struct intel_display_error_state *
17388 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
17389 {
17390         struct intel_display_error_state *error;
17391         int transcoders[] = {
17392                 TRANSCODER_A,
17393                 TRANSCODER_B,
17394                 TRANSCODER_C,
17395                 TRANSCODER_EDP,
17396         };
17397         int i;
17398
17399         if (INTEL_INFO(dev_priv)->num_pipes == 0)
17400                 return NULL;
17401
17402         error = kzalloc(sizeof(*error), GFP_ATOMIC);
17403         if (error == NULL)
17404                 return NULL;
17405
17406         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
17407                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
17408
17409         for_each_pipe(dev_priv, i) {
17410                 error->pipe[i].power_domain_on =
17411                         __intel_display_power_is_enabled(dev_priv,
17412                                                          POWER_DOMAIN_PIPE(i));
17413                 if (!error->pipe[i].power_domain_on)
17414                         continue;
17415
17416                 error->cursor[i].control = I915_READ(CURCNTR(i));
17417                 error->cursor[i].position = I915_READ(CURPOS(i));
17418                 error->cursor[i].base = I915_READ(CURBASE(i));
17419
17420                 error->plane[i].control = I915_READ(DSPCNTR(i));
17421                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
17422                 if (INTEL_GEN(dev_priv) <= 3) {
17423                         error->plane[i].size = I915_READ(DSPSIZE(i));
17424                         error->plane[i].pos = I915_READ(DSPPOS(i));
17425                 }
17426                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
17427                         error->plane[i].addr = I915_READ(DSPADDR(i));
17428                 if (INTEL_GEN(dev_priv) >= 4) {
17429                         error->plane[i].surface = I915_READ(DSPSURF(i));
17430                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
17431                 }
17432
17433                 error->pipe[i].source = I915_READ(PIPESRC(i));
17434
17435                 if (HAS_GMCH_DISPLAY(dev_priv))
17436                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
17437         }
17438
17439         /* Note: this does not include DSI transcoders. */
17440         error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
17441         if (HAS_DDI(dev_priv))
17442                 error->num_transcoders++; /* Account for eDP. */
17443
17444         for (i = 0; i < error->num_transcoders; i++) {
17445                 enum transcoder cpu_transcoder = transcoders[i];
17446
17447                 error->transcoder[i].power_domain_on =
17448                         __intel_display_power_is_enabled(dev_priv,
17449                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
17450                 if (!error->transcoder[i].power_domain_on)
17451                         continue;
17452
17453                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
17454
17455                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
17456                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
17457                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
17458                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
17459                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
17460                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
17461                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
17462         }
17463
17464         return error;
17465 }
17466
17467 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
17468
17469 void
17470 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
17471                                 struct drm_i915_private *dev_priv,
17472                                 struct intel_display_error_state *error)
17473 {
17474         int i;
17475
17476         if (!error)
17477                 return;
17478
17479         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes);
17480         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
17481                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
17482                            error->power_well_driver);
17483         for_each_pipe(dev_priv, i) {
17484                 err_printf(m, "Pipe [%d]:\n", i);
17485                 err_printf(m, "  Power: %s\n",
17486                            onoff(error->pipe[i].power_domain_on));
17487                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
17488                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
17489
17490                 err_printf(m, "Plane [%d]:\n", i);
17491                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
17492                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
17493                 if (INTEL_GEN(dev_priv) <= 3) {
17494                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
17495                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
17496                 }
17497                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
17498                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
17499                 if (INTEL_GEN(dev_priv) >= 4) {
17500                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
17501                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
17502                 }
17503
17504                 err_printf(m, "Cursor [%d]:\n", i);
17505                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
17506                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
17507                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
17508         }
17509
17510         for (i = 0; i < error->num_transcoders; i++) {
17511                 err_printf(m, "CPU transcoder: %s\n",
17512                            transcoder_name(error->transcoder[i].cpu_transcoder));
17513                 err_printf(m, "  Power: %s\n",
17514                            onoff(error->transcoder[i].power_domain_on));
17515                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
17516                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
17517                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
17518                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
17519                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
17520                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
17521                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
17522         }
17523 }
17524
17525 #endif