drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include "intel_frontbuffer.h"
  38 #include <drm/i915_drm.h>
  39 #include "i915_drv.h"
  40 #include "intel_dsi.h"
  41 #include "i915_trace.h"
  42 #include <drm/drm_atomic.h>
  43 #include <drm/drm_atomic_helper.h>
  44 #include <drm/drm_dp_helper.h>
  45 #include <drm/drm_crtc_helper.h>
  46 #include <drm/drm_plane_helper.h>
  47 #include <drm/drm_rect.h>
  48 #include <linux/dma_remapping.h>
  49 #include <linux/reservation.h>
  50
  51 static bool is_mmio_work(struct intel_flip_work *work)
  52 {
  53         return work->mmio_work.func;
  54 }
  55
  56 /* Primary plane formats for gen <= 3 */
  57 static const uint32_t i8xx_primary_formats[] = {
  58         DRM_FORMAT_C8,
  59         DRM_FORMAT_RGB565,
  60         DRM_FORMAT_XRGB1555,
  61         DRM_FORMAT_XRGB8888,
  62 };
  63
  64 /* Primary plane formats for gen >= 4 */
  65 static const uint32_t i965_primary_formats[] = {
  66         DRM_FORMAT_C8,
  67         DRM_FORMAT_RGB565,
  68         DRM_FORMAT_XRGB8888,
  69         DRM_FORMAT_XBGR8888,
  70         DRM_FORMAT_XRGB2101010,
  71         DRM_FORMAT_XBGR2101010,
  72 };
  73
  74 static const uint32_t skl_primary_formats[] = {
  75         DRM_FORMAT_C8,
  76         DRM_FORMAT_RGB565,
  77         DRM_FORMAT_XRGB8888,
  78         DRM_FORMAT_XBGR8888,
  79         DRM_FORMAT_ARGB8888,
  80         DRM_FORMAT_ABGR8888,
  81         DRM_FORMAT_XRGB2101010,
  82         DRM_FORMAT_XBGR2101010,
  83         DRM_FORMAT_YUYV,
  84         DRM_FORMAT_YVYU,
  85         DRM_FORMAT_UYVY,
  86         DRM_FORMAT_VYUY,
  87 };
  88
  89 /* Cursor formats */
  90 static const uint32_t intel_cursor_formats[] = {
  91         DRM_FORMAT_ARGB8888,
  92 };
  93
  94 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  95                                 struct intel_crtc_state *pipe_config);
  96 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  97                                    struct intel_crtc_state *pipe_config);
  98
  99 static int intel_framebuffer_init(struct drm_device *dev,
 100                                   struct intel_framebuffer *ifb,
 101                                   struct drm_mode_fb_cmd2 *mode_cmd,
 102                                   struct drm_i915_gem_object *obj);
 103 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
 104 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
 105 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
 106 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
 107                                          struct intel_link_m_n *m_n,
 108                                          struct intel_link_m_n *m2_n2);
 109 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 110 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 111 static void haswell_set_pipemisc(struct drm_crtc *crtc);
 112 static void vlv_prepare_pll(struct intel_crtc *crtc,
 113                             const struct intel_crtc_state *pipe_config);
 114 static void chv_prepare_pll(struct intel_crtc *crtc,
 115                             const struct intel_crtc_state *pipe_config);
 116 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 117 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 118 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
 119                                     struct intel_crtc_state *crtc_state);
 120 static void skylake_pfit_enable(struct intel_crtc *crtc);
 121 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
 122 static void ironlake_pfit_enable(struct intel_crtc *crtc);
 123 static void intel_modeset_setup_hw_state(struct drm_device *dev);
 124 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
 125 static int ilk_max_pixel_rate(struct drm_atomic_state *state);
 126 static int glk_calc_cdclk(int max_pixclk);
 127 static int bxt_calc_cdclk(int max_pixclk);
 128
 129 struct intel_limit {
 130         struct {
 131                 int min, max;
 132         } dot, vco, n, m, m1, m2, p, p1;
 133
 134         struct {
 135                 int dot_limit;
 136                 int p2_slow, p2_fast;
 137         } p2;
 138 };
 139
 140 /* returns HPLL frequency in kHz */
 141 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
 142 {
 143         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 144
 145         /* Obtain SKU information */
 146         mutex_lock(&dev_priv->sb_lock);
 147         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 148                 CCK_FUSE_HPLL_FREQ_MASK;
 149         mutex_unlock(&dev_priv->sb_lock);
 150
 151         return vco_freq[hpll_freq] * 1000;
 152 }
 153
 154 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
 155                       const char *name, u32 reg, int ref_freq)
 156 {
 157         u32 val;
 158         int divider;
 159
 160         mutex_lock(&dev_priv->sb_lock);
 161         val = vlv_cck_read(dev_priv, reg);
 162         mutex_unlock(&dev_priv->sb_lock);
 163
 164         divider = val & CCK_FREQUENCY_VALUES;
 165
 166         WARN((val & CCK_FREQUENCY_STATUS) !=
 167              (divider << CCK_FREQUENCY_STATUS_SHIFT),
 168              "%s change in progress\n", name);
 169
 170         return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
 171 }
 172
 173 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 174                                   const char *name, u32 reg)
 175 {
 176         if (dev_priv->hpll_freq == 0)
 177                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
 178
 179         return vlv_get_cck_clock(dev_priv, name, reg,
 180                                  dev_priv->hpll_freq);
 181 }
 182
 183 static int
 184 intel_pch_rawclk(struct drm_i915_private *dev_priv)
 185 {
 186         return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
 187 }
 188
 189 static int
 190 intel_vlv_hrawclk(struct drm_i915_private *dev_priv)
 191 {
 192         /* RAWCLK_FREQ_VLV register updated from power well code */
 193         return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
 194                                       CCK_DISPLAY_REF_CLOCK_CONTROL);
 195 }
 196
 197 static int
 198 intel_g4x_hrawclk(struct drm_i915_private *dev_priv)
 199 {
 200         uint32_t clkcfg;
 201
 202         /* hrawclock is 1/4 the FSB frequency */
 203         clkcfg = I915_READ(CLKCFG);
 204         switch (clkcfg & CLKCFG_FSB_MASK) {
 205         case CLKCFG_FSB_400:
 206                 return 100000;
 207         case CLKCFG_FSB_533:
 208                 return 133333;
 209         case CLKCFG_FSB_667:
 210                 return 166667;
 211         case CLKCFG_FSB_800:
 212                 return 200000;
 213         case CLKCFG_FSB_1067:
 214                 return 266667;
 215         case CLKCFG_FSB_1333:
 216                 return 333333;
 217         /* these two are just a guess; one of them might be right */
 218         case CLKCFG_FSB_1600:
 219         case CLKCFG_FSB_1600_ALT:
 220                 return 400000;
 221         default:
 222                 return 133333;
 223         }
 224 }
 225
 226 void intel_update_rawclk(struct drm_i915_private *dev_priv)
 227 {
 228         if (HAS_PCH_SPLIT(dev_priv))
 229                 dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv);
 230         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 231                 dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv);
 232         else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
 233                 dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv);
 234         else
 235                 return; /* no rawclk on other platforms, or no need to know it */
 236
 237         DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
 238 }
 239
 240 static void intel_update_czclk(struct drm_i915_private *dev_priv)
 241 {
 242         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
 243                 return;
 244
 245         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 246                                                       CCK_CZ_CLOCK_CONTROL);
 247
 248         DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
 249 }
 250
 251 static inline u32 /* units of 100MHz */
 252 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
 253                     const struct intel_crtc_state *pipe_config)
 254 {
 255         if (HAS_DDI(dev_priv))
 256                 return pipe_config->port_clock; /* SPLL */
 257         else if (IS_GEN5(dev_priv))
 258                 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
 259         else
 260                 return 270000;
 261 }
 262
 263 static const struct intel_limit intel_limits_i8xx_dac = {
 264         .dot = { .min = 25000, .max = 350000 },
 265         .vco = { .min = 908000, .max = 1512000 },
 266         .n = { .min = 2, .max = 16 },
 267         .m = { .min = 96, .max = 140 },
 268         .m1 = { .min = 18, .max = 26 },
 269         .m2 = { .min = 6, .max = 16 },
 270         .p = { .min = 4, .max = 128 },
 271         .p1 = { .min = 2, .max = 33 },
 272         .p2 = { .dot_limit = 165000,
 273                 .p2_slow = 4, .p2_fast = 2 },
 274 };
 275
 276 static const struct intel_limit intel_limits_i8xx_dvo = {
 277         .dot = { .min = 25000, .max = 350000 },
 278         .vco = { .min = 908000, .max = 1512000 },
 279         .n = { .min = 2, .max = 16 },
 280         .m = { .min = 96, .max = 140 },
 281         .m1 = { .min = 18, .max = 26 },
 282         .m2 = { .min = 6, .max = 16 },
 283         .p = { .min = 4, .max = 128 },
 284         .p1 = { .min = 2, .max = 33 },
 285         .p2 = { .dot_limit = 165000,
 286                 .p2_slow = 4, .p2_fast = 4 },
 287 };
 288
 289 static const struct intel_limit intel_limits_i8xx_lvds = {
 290         .dot = { .min = 25000, .max = 350000 },
 291         .vco = { .min = 908000, .max = 1512000 },
 292         .n = { .min = 2, .max = 16 },
 293         .m = { .min = 96, .max = 140 },
 294         .m1 = { .min = 18, .max = 26 },
 295         .m2 = { .min = 6, .max = 16 },
 296         .p = { .min = 4, .max = 128 },
 297         .p1 = { .min = 1, .max = 6 },
 298         .p2 = { .dot_limit = 165000,
 299                 .p2_slow = 14, .p2_fast = 7 },
 300 };
 301
 302 static const struct intel_limit intel_limits_i9xx_sdvo = {
 303         .dot = { .min = 20000, .max = 400000 },
 304         .vco = { .min = 1400000, .max = 2800000 },
 305         .n = { .min = 1, .max = 6 },
 306         .m = { .min = 70, .max = 120 },
 307         .m1 = { .min = 8, .max = 18 },
 308         .m2 = { .min = 3, .max = 7 },
 309         .p = { .min = 5, .max = 80 },
 310         .p1 = { .min = 1, .max = 8 },
 311         .p2 = { .dot_limit = 200000,
 312                 .p2_slow = 10, .p2_fast = 5 },
 313 };
 314
 315 static const struct intel_limit intel_limits_i9xx_lvds = {
 316         .dot = { .min = 20000, .max = 400000 },
 317         .vco = { .min = 1400000, .max = 2800000 },
 318         .n = { .min = 1, .max = 6 },
 319         .m = { .min = 70, .max = 120 },
 320         .m1 = { .min = 8, .max = 18 },
 321         .m2 = { .min = 3, .max = 7 },
 322         .p = { .min = 7, .max = 98 },
 323         .p1 = { .min = 1, .max = 8 },
 324         .p2 = { .dot_limit = 112000,
 325                 .p2_slow = 14, .p2_fast = 7 },
 326 };
 327
 328
 329 static const struct intel_limit intel_limits_g4x_sdvo = {
 330         .dot = { .min = 25000, .max = 270000 },
 331         .vco = { .min = 1750000, .max = 3500000},
 332         .n = { .min = 1, .max = 4 },
 333         .m = { .min = 104, .max = 138 },
 334         .m1 = { .min = 17, .max = 23 },
 335         .m2 = { .min = 5, .max = 11 },
 336         .p = { .min = 10, .max = 30 },
 337         .p1 = { .min = 1, .max = 3},
 338         .p2 = { .dot_limit = 270000,
 339                 .p2_slow = 10,
 340                 .p2_fast = 10
 341         },
 342 };
 343
 344 static const struct intel_limit intel_limits_g4x_hdmi = {
 345         .dot = { .min = 22000, .max = 400000 },
 346         .vco = { .min = 1750000, .max = 3500000},
 347         .n = { .min = 1, .max = 4 },
 348         .m = { .min = 104, .max = 138 },
 349         .m1 = { .min = 16, .max = 23 },
 350         .m2 = { .min = 5, .max = 11 },
 351         .p = { .min = 5, .max = 80 },
 352         .p1 = { .min = 1, .max = 8},
 353         .p2 = { .dot_limit = 165000,
 354                 .p2_slow = 10, .p2_fast = 5 },
 355 };
 356
 357 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
 358         .dot = { .min = 20000, .max = 115000 },
 359         .vco = { .min = 1750000, .max = 3500000 },
 360         .n = { .min = 1, .max = 3 },
 361         .m = { .min = 104, .max = 138 },
 362         .m1 = { .min = 17, .max = 23 },
 363         .m2 = { .min = 5, .max = 11 },
 364         .p = { .min = 28, .max = 112 },
 365         .p1 = { .min = 2, .max = 8 },
 366         .p2 = { .dot_limit = 0,
 367                 .p2_slow = 14, .p2_fast = 14
 368         },
 369 };
 370
 371 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
 372         .dot = { .min = 80000, .max = 224000 },
 373         .vco = { .min = 1750000, .max = 3500000 },
 374         .n = { .min = 1, .max = 3 },
 375         .m = { .min = 104, .max = 138 },
 376         .m1 = { .min = 17, .max = 23 },
 377         .m2 = { .min = 5, .max = 11 },
 378         .p = { .min = 14, .max = 42 },
 379         .p1 = { .min = 2, .max = 6 },
 380         .p2 = { .dot_limit = 0,
 381                 .p2_slow = 7, .p2_fast = 7
 382         },
 383 };
 384
 385 static const struct intel_limit intel_limits_pineview_sdvo = {
 386         .dot = { .min = 20000, .max = 400000},
 387         .vco = { .min = 1700000, .max = 3500000 },
 388         /* Pineview's Ncounter is a ring counter */
 389         .n = { .min = 3, .max = 6 },
 390         .m = { .min = 2, .max = 256 },
 391         /* Pineview only has one combined m divider, which we treat as m2. */
 392         .m1 = { .min = 0, .max = 0 },
 393         .m2 = { .min = 0, .max = 254 },
 394         .p = { .min = 5, .max = 80 },
 395         .p1 = { .min = 1, .max = 8 },
 396         .p2 = { .dot_limit = 200000,
 397                 .p2_slow = 10, .p2_fast = 5 },
 398 };
 399
 400 static const struct intel_limit intel_limits_pineview_lvds = {
 401         .dot = { .min = 20000, .max = 400000 },
 402         .vco = { .min = 1700000, .max = 3500000 },
 403         .n = { .min = 3, .max = 6 },
 404         .m = { .min = 2, .max = 256 },
 405         .m1 = { .min = 0, .max = 0 },
 406         .m2 = { .min = 0, .max = 254 },
 407         .p = { .min = 7, .max = 112 },
 408         .p1 = { .min = 1, .max = 8 },
 409         .p2 = { .dot_limit = 112000,
 410                 .p2_slow = 14, .p2_fast = 14 },
 411 };
 412
 413 /* Ironlake / Sandybridge
 414  *
 415  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 416  * the range value for them is (actual_value - 2).
 417  */
 418 static const struct intel_limit intel_limits_ironlake_dac = {
 419         .dot = { .min = 25000, .max = 350000 },
 420         .vco = { .min = 1760000, .max = 3510000 },
 421         .n = { .min = 1, .max = 5 },
 422         .m = { .min = 79, .max = 127 },
 423         .m1 = { .min = 12, .max = 22 },
 424         .m2 = { .min = 5, .max = 9 },
 425         .p = { .min = 5, .max = 80 },
 426         .p1 = { .min = 1, .max = 8 },
 427         .p2 = { .dot_limit = 225000,
 428                 .p2_slow = 10, .p2_fast = 5 },
 429 };
 430
 431 static const struct intel_limit intel_limits_ironlake_single_lvds = {
 432         .dot = { .min = 25000, .max = 350000 },
 433         .vco = { .min = 1760000, .max = 3510000 },
 434         .n = { .min = 1, .max = 3 },
 435         .m = { .min = 79, .max = 118 },
 436         .m1 = { .min = 12, .max = 22 },
 437         .m2 = { .min = 5, .max = 9 },
 438         .p = { .min = 28, .max = 112 },
 439         .p1 = { .min = 2, .max = 8 },
 440         .p2 = { .dot_limit = 225000,
 441                 .p2_slow = 14, .p2_fast = 14 },
 442 };
 443
 444 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
 445         .dot = { .min = 25000, .max = 350000 },
 446         .vco = { .min = 1760000, .max = 3510000 },
 447         .n = { .min = 1, .max = 3 },
 448         .m = { .min = 79, .max = 127 },
 449         .m1 = { .min = 12, .max = 22 },
 450         .m2 = { .min = 5, .max = 9 },
 451         .p = { .min = 14, .max = 56 },
 452         .p1 = { .min = 2, .max = 8 },
 453         .p2 = { .dot_limit = 225000,
 454                 .p2_slow = 7, .p2_fast = 7 },
 455 };
 456
 457 /* LVDS 100mhz refclk limits. */
 458 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
 459         .dot = { .min = 25000, .max = 350000 },
 460         .vco = { .min = 1760000, .max = 3510000 },
 461         .n = { .min = 1, .max = 2 },
 462         .m = { .min = 79, .max = 126 },
 463         .m1 = { .min = 12, .max = 22 },
 464         .m2 = { .min = 5, .max = 9 },
 465         .p = { .min = 28, .max = 112 },
 466         .p1 = { .min = 2, .max = 8 },
 467         .p2 = { .dot_limit = 225000,
 468                 .p2_slow = 14, .p2_fast = 14 },
 469 };
 470
 471 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
 472         .dot = { .min = 25000, .max = 350000 },
 473         .vco = { .min = 1760000, .max = 3510000 },
 474         .n = { .min = 1, .max = 3 },
 475         .m = { .min = 79, .max = 126 },
 476         .m1 = { .min = 12, .max = 22 },
 477         .m2 = { .min = 5, .max = 9 },
 478         .p = { .min = 14, .max = 42 },
 479         .p1 = { .min = 2, .max = 6 },
 480         .p2 = { .dot_limit = 225000,
 481                 .p2_slow = 7, .p2_fast = 7 },
 482 };
 483
 484 static const struct intel_limit intel_limits_vlv = {
 485          /*
 486           * These are the data rate limits (measured in fast clocks)
 487           * since those are the strictest limits we have. The fast
 488           * clock and actual rate limits are more relaxed, so checking
 489           * them would make no difference.
 490           */
 491         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 492         .vco = { .min = 4000000, .max = 6000000 },
 493         .n = { .min = 1, .max = 7 },
 494         .m1 = { .min = 2, .max = 3 },
 495         .m2 = { .min = 11, .max = 156 },
 496         .p1 = { .min = 2, .max = 3 },
 497         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 498 };
 499
 500 static const struct intel_limit intel_limits_chv = {
 501         /*
 502          * These are the data rate limits (measured in fast clocks)
 503          * since those are the strictest limits we have.  The fast
 504          * clock and actual rate limits are more relaxed, so checking
 505          * them would make no difference.
 506          */
 507         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 508         .vco = { .min = 4800000, .max = 6480000 },
 509         .n = { .min = 1, .max = 1 },
 510         .m1 = { .min = 2, .max = 2 },
 511         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 512         .p1 = { .min = 2, .max = 4 },
 513         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 514 };
 515
 516 static const struct intel_limit intel_limits_bxt = {
 517         /* FIXME: find real dot limits */
 518         .dot = { .min = 0, .max = INT_MAX },
 519         .vco = { .min = 4800000, .max = 6700000 },
 520         .n = { .min = 1, .max = 1 },
 521         .m1 = { .min = 2, .max = 2 },
 522         /* FIXME: find real m2 limits */
 523         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 524         .p1 = { .min = 2, .max = 4 },
 525         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 526 };
 527
 528 static bool
 529 needs_modeset(struct drm_crtc_state *state)
 530 {
 531         return drm_atomic_crtc_needs_modeset(state);
 532 }
 533
 534 /*
 535  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 536  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 537  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 538  * The helpers' return value is the rate of the clock that is fed to the
 539  * display engine's pipe which can be the above fast dot clock rate or a
 540  * divided-down version of it.
 541  */
 542 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 543 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
 544 {
 545         clock->m = clock->m2 + 2;
 546         clock->p = clock->p1 * clock->p2;
 547         if (WARN_ON(clock->n == 0 || clock->p == 0))
 548                 return 0;
 549         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 550         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 551
 552         return clock->dot;
 553 }
 554
 555 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 556 {
 557         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 558 }
 559
 560 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
 561 {
 562         clock->m = i9xx_dpll_compute_m(clock);
 563         clock->p = clock->p1 * clock->p2;
 564         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 565                 return 0;
 566         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 567         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 568
 569         return clock->dot;
 570 }
 571
 572 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
 573 {
 574         clock->m = clock->m1 * clock->m2;
 575         clock->p = clock->p1 * clock->p2;
 576         if (WARN_ON(clock->n == 0 || clock->p == 0))
 577                 return 0;
 578         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 579         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 580
 581         return clock->dot / 5;
 582 }
 583
 584 int chv_calc_dpll_params(int refclk, struct dpll *clock)
 585 {
 586         clock->m = clock->m1 * clock->m2;
 587         clock->p = clock->p1 * clock->p2;
 588         if (WARN_ON(clock->n == 0 || clock->p == 0))
 589                 return 0;
 590         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 591                         clock->n << 22);
 592         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 593
 594         return clock->dot / 5;
 595 }
 596
 597 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 598 /**
 599  * Returns whether the given set of divisors are valid for a given refclk with
 600  * the given connectors.
 601  */
 602
 603 static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
 604                                const struct intel_limit *limit,
 605                                const struct dpll *clock)
 606 {
 607         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 608                 INTELPllInvalid("n out of range\n");
 609         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 610                 INTELPllInvalid("p1 out of range\n");
 611         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 612                 INTELPllInvalid("m2 out of range\n");
 613         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 614                 INTELPllInvalid("m1 out of range\n");
 615
 616         if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
 617             !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
 618                 if (clock->m1 <= clock->m2)
 619                         INTELPllInvalid("m1 <= m2\n");
 620
 621         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
 622             !IS_GEN9_LP(dev_priv)) {
 623                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 624                         INTELPllInvalid("p out of range\n");
 625                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 626                         INTELPllInvalid("m out of range\n");
 627         }
 628
 629         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 630                 INTELPllInvalid("vco out of range\n");
 631         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 632          * connector, etc., rather than just a single range.
 633          */
 634         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 635                 INTELPllInvalid("dot out of range\n");
 636
 637         return true;
 638 }
 639
 640 static int
 641 i9xx_select_p2_div(const struct intel_limit *limit,
 642                    const struct intel_crtc_state *crtc_state,
 643                    int target)
 644 {
 645         struct drm_device *dev = crtc_state->base.crtc->dev;
 646
 647         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 648                 /*
 649                  * For LVDS just rely on its current settings for dual-channel.
 650                  * We haven't figured out how to reliably set up different
 651                  * single/dual channel state, if we even can.
 652                  */
 653                 if (intel_is_dual_link_lvds(dev))
 654                         return limit->p2.p2_fast;
 655                 else
 656                         return limit->p2.p2_slow;
 657         } else {
 658                 if (target < limit->p2.dot_limit)
 659                         return limit->p2.p2_slow;
 660                 else
 661                         return limit->p2.p2_fast;
 662         }
 663 }
 664
 665 /*
 666  * Returns a set of divisors for the desired target clock with the given
 667  * refclk, or FALSE.  The returned values represent the clock equation:
 668  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 669  *
 670  * Target and reference clocks are specified in kHz.
 671  *
 672  * If match_clock is provided, then best_clock P divider must match the P
 673  * divider from @match_clock used for LVDS downclocking.
 674  */
 675 static bool
 676 i9xx_find_best_dpll(const struct intel_limit *limit,
 677                     struct intel_crtc_state *crtc_state,
 678                     int target, int refclk, struct dpll *match_clock,
 679                     struct dpll *best_clock)
 680 {
 681         struct drm_device *dev = crtc_state->base.crtc->dev;
 682         struct dpll clock;
 683         int err = target;
 684
 685         memset(best_clock, 0, sizeof(*best_clock));
 686
 687         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 688
 689         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 690              clock.m1++) {
 691                 for (clock.m2 = limit->m2.min;
 692                      clock.m2 <= limit->m2.max; clock.m2++) {
 693                         if (clock.m2 >= clock.m1)
 694                                 break;
 695                         for (clock.n = limit->n.min;
 696                              clock.n <= limit->n.max; clock.n++) {
 697                                 for (clock.p1 = limit->p1.min;
 698                                         clock.p1 <= limit->p1.max; clock.p1++) {
 699                                         int this_err;
 700
 701                                         i9xx_calc_dpll_params(refclk, &clock);
 702                                         if (!intel_PLL_is_valid(to_i915(dev),
 703                                                                 limit,
 704                                                                 &clock))
 705                                                 continue;
 706                                         if (match_clock &&
 707                                             clock.p != match_clock->p)
 708                                                 continue;
 709
 710                                         this_err = abs(clock.dot - target);
 711                                         if (this_err < err) {
 712                                                 *best_clock = clock;
 713                                                 err = this_err;
 714                                         }
 715                                 }
 716                         }
 717                 }
 718         }
 719
 720         return (err != target);
 721 }
 722
 723 /*
 724  * Returns a set of divisors for the desired target clock with the given
 725  * refclk, or FALSE.  The returned values represent the clock equation:
 726  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 727  *
 728  * Target and reference clocks are specified in kHz.
 729  *
 730  * If match_clock is provided, then best_clock P divider must match the P
 731  * divider from @match_clock used for LVDS downclocking.
 732  */
 733 static bool
 734 pnv_find_best_dpll(const struct intel_limit *limit,
 735                    struct intel_crtc_state *crtc_state,
 736                    int target, int refclk, struct dpll *match_clock,
 737                    struct dpll *best_clock)
 738 {
 739         struct drm_device *dev = crtc_state->base.crtc->dev;
 740         struct dpll clock;
 741         int err = target;
 742
 743         memset(best_clock, 0, sizeof(*best_clock));
 744
 745         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 746
 747         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 748              clock.m1++) {
 749                 for (clock.m2 = limit->m2.min;
 750                      clock.m2 <= limit->m2.max; clock.m2++) {
 751                         for (clock.n = limit->n.min;
 752                              clock.n <= limit->n.max; clock.n++) {
 753                                 for (clock.p1 = limit->p1.min;
 754                                         clock.p1 <= limit->p1.max; clock.p1++) {
 755                                         int this_err;
 756
 757                                         pnv_calc_dpll_params(refclk, &clock);
 758                                         if (!intel_PLL_is_valid(to_i915(dev),
 759                                                                 limit,
 760                                                                 &clock))
 761                                                 continue;
 762                                         if (match_clock &&
 763                                             clock.p != match_clock->p)
 764                                                 continue;
 765
 766                                         this_err = abs(clock.dot - target);
 767                                         if (this_err < err) {
 768                                                 *best_clock = clock;
 769                                                 err = this_err;
 770                                         }
 771                                 }
 772                         }
 773                 }
 774         }
 775
 776         return (err != target);
 777 }
 778
 779 /*
 780  * Returns a set of divisors for the desired target clock with the given
 781  * refclk, or FALSE.  The returned values represent the clock equation:
 782  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 783  *
 784  * Target and reference clocks are specified in kHz.
 785  *
 786  * If match_clock is provided, then best_clock P divider must match the P
 787  * divider from @match_clock used for LVDS downclocking.
 788  */
 789 static bool
 790 g4x_find_best_dpll(const struct intel_limit *limit,
 791                    struct intel_crtc_state *crtc_state,
 792                    int target, int refclk, struct dpll *match_clock,
 793                    struct dpll *best_clock)
 794 {
 795         struct drm_device *dev = crtc_state->base.crtc->dev;
 796         struct dpll clock;
 797         int max_n;
 798         bool found = false;
 799         /* approximately equals target * 0.00585 */
 800         int err_most = (target >> 8) + (target >> 9);
 801
 802         memset(best_clock, 0, sizeof(*best_clock));
 803
 804         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 805
 806         max_n = limit->n.max;
 807         /* based on hardware requirement, prefer smaller n to precision */
 808         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 809                 /* based on hardware requirement, prefere larger m1,m2 */
 810                 for (clock.m1 = limit->m1.max;
 811                      clock.m1 >= limit->m1.min; clock.m1--) {
 812                         for (clock.m2 = limit->m2.max;
 813                              clock.m2 >= limit->m2.min; clock.m2--) {
 814                                 for (clock.p1 = limit->p1.max;
 815                                      clock.p1 >= limit->p1.min; clock.p1--) {
 816                                         int this_err;
 817
 818                                         i9xx_calc_dpll_params(refclk, &clock);
 819                                         if (!intel_PLL_is_valid(to_i915(dev),
 820                                                                 limit,
 821                                                                 &clock))
 822                                                 continue;
 823
 824                                         this_err = abs(clock.dot - target);
 825                                         if (this_err < err_most) {
 826                                                 *best_clock = clock;
 827                                                 err_most = this_err;
 828                                                 max_n = clock.n;
 829                                                 found = true;
 830                                         }
 831                                 }
 832                         }
 833                 }
 834         }
 835         return found;
 836 }
 837
 838 /*
 839  * Check if the calculated PLL configuration is more optimal compared to the
 840  * best configuration and error found so far. Return the calculated error.
 841  */
 842 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 843                                const struct dpll *calculated_clock,
 844                                const struct dpll *best_clock,
 845                                unsigned int best_error_ppm,
 846                                unsigned int *error_ppm)
 847 {
 848         /*
 849          * For CHV ignore the error and consider only the P value.
 850          * Prefer a bigger P value based on HW requirements.
 851          */
 852         if (IS_CHERRYVIEW(to_i915(dev))) {
 853                 *error_ppm = 0;
 854
 855                 return calculated_clock->p > best_clock->p;
 856         }
 857
 858         if (WARN_ON_ONCE(!target_freq))
 859                 return false;
 860
 861         *error_ppm = div_u64(1000000ULL *
 862                                 abs(target_freq - calculated_clock->dot),
 863                              target_freq);
 864         /*
 865          * Prefer a better P value over a better (smaller) error if the error
 866          * is small. Ensure this preference for future configurations too by
 867          * setting the error to 0.
 868          */
 869         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 870                 *error_ppm = 0;
 871
 872                 return true;
 873         }
 874
 875         return *error_ppm + 10 < best_error_ppm;
 876 }
 877
 878 /*
 879  * Returns a set of divisors for the desired target clock with the given
 880  * refclk, or FALSE.  The returned values represent the clock equation:
 881  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 882  */
 883 static bool
 884 vlv_find_best_dpll(const struct intel_limit *limit,
 885                    struct intel_crtc_state *crtc_state,
 886                    int target, int refclk, struct dpll *match_clock,
 887                    struct dpll *best_clock)
 888 {
 889         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 890         struct drm_device *dev = crtc->base.dev;
 891         struct dpll clock;
 892         unsigned int bestppm = 1000000;
 893         /* min update 19.2 MHz */
 894         int max_n = min(limit->n.max, refclk / 19200);
 895         bool found = false;
 896
 897         target *= 5; /* fast clock */
 898
 899         memset(best_clock, 0, sizeof(*best_clock));
 900
 901         /* based on hardware requirement, prefer smaller n to precision */
 902         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 903                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 904                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 905                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 906                                 clock.p = clock.p1 * clock.p2;
 907                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 908                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 909                                         unsigned int ppm;
 910
 911                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 912                                                                      refclk * clock.m1);
 913
 914                                         vlv_calc_dpll_params(refclk, &clock);
 915
 916                                         if (!intel_PLL_is_valid(to_i915(dev),
 917                                                                 limit,
 918                                                                 &clock))
 919                                                 continue;
 920
 921                                         if (!vlv_PLL_is_optimal(dev, target,
 922                                                                 &clock,
 923                                                                 best_clock,
 924                                                                 bestppm, &ppm))
 925                                                 continue;
 926
 927                                         *best_clock = clock;
 928                                         bestppm = ppm;
 929                                         found = true;
 930                                 }
 931                         }
 932                 }
 933         }
 934
 935         return found;
 936 }
 937
 938 /*
 939  * Returns a set of divisors for the desired target clock with the given
 940  * refclk, or FALSE.  The returned values represent the clock equation:
 941  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 942  */
 943 static bool
 944 chv_find_best_dpll(const struct intel_limit *limit,
 945                    struct intel_crtc_state *crtc_state,
 946                    int target, int refclk, struct dpll *match_clock,
 947                    struct dpll *best_clock)
 948 {
 949         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 950         struct drm_device *dev = crtc->base.dev;
 951         unsigned int best_error_ppm;
 952         struct dpll clock;
 953         uint64_t m2;
 954         int found = false;
 955
 956         memset(best_clock, 0, sizeof(*best_clock));
 957         best_error_ppm = 1000000;
 958
 959         /*
 960          * Based on hardware doc, the n always set to 1, and m1 always
 961          * set to 2.  If requires to support 200Mhz refclk, we need to
 962          * revisit this because n may not 1 anymore.
 963          */
 964         clock.n = 1, clock.m1 = 2;
 965         target *= 5;    /* fast clock */
 966
 967         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 968                 for (clock.p2 = limit->p2.p2_fast;
 969                                 clock.p2 >= limit->p2.p2_slow;
 970                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 971                         unsigned int error_ppm;
 972
 973                         clock.p = clock.p1 * clock.p2;
 974
 975                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 976                                         clock.n) << 22, refclk * clock.m1);
 977
 978                         if (m2 > INT_MAX/clock.m1)
 979                                 continue;
 980
 981                         clock.m2 = m2;
 982
 983                         chv_calc_dpll_params(refclk, &clock);
 984
 985                         if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))
 986                                 continue;
 987
 988                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
 989                                                 best_error_ppm, &error_ppm))
 990                                 continue;
 991
 992                         *best_clock = clock;
 993                         best_error_ppm = error_ppm;
 994                         found = true;
 995                 }
 996         }
 997
 998         return found;
 999 }
1000
1001 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1002                         struct dpll *best_clock)
1003 {
1004         int refclk = 100000;
1005         const struct intel_limit *limit = &intel_limits_bxt;
1006
1007         return chv_find_best_dpll(limit, crtc_state,
1008                                   target_clock, refclk, NULL, best_clock);
1009 }
1010
1011 bool intel_crtc_active(struct intel_crtc *crtc)
1012 {
1013         /* Be paranoid as we can arrive here with only partial
1014          * state retrieved from the hardware during setup.
1015          *
1016          * We can ditch the adjusted_mode.crtc_clock check as soon
1017          * as Haswell has gained clock readout/fastboot support.
1018          *
1019          * We can ditch the crtc->primary->fb check as soon as we can
1020          * properly reconstruct framebuffers.
1021          *
1022          * FIXME: The intel_crtc->active here should be switched to
1023          * crtc->state->active once we have proper CRTC states wired up
1024          * for atomic.
1025          */
1026         return crtc->active && crtc->base.primary->state->fb &&
1027                 crtc->config->base.adjusted_mode.crtc_clock;
1028 }
1029
1030 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1031                                              enum pipe pipe)
1032 {
1033         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1034
1035         return crtc->config->cpu_transcoder;
1036 }
1037
1038 static bool pipe_dsl_stopped(struct drm_i915_private *dev_priv, enum pipe pipe)
1039 {
1040         i915_reg_t reg = PIPEDSL(pipe);
1041         u32 line1, line2;
1042         u32 line_mask;
1043
1044         if (IS_GEN2(dev_priv))
1045                 line_mask = DSL_LINEMASK_GEN2;
1046         else
1047                 line_mask = DSL_LINEMASK_GEN3;
1048
1049         line1 = I915_READ(reg) & line_mask;
1050         msleep(5);
1051         line2 = I915_READ(reg) & line_mask;
1052
1053         return line1 == line2;
1054 }
1055
1056 /*
1057  * intel_wait_for_pipe_off - wait for pipe to turn off
1058  * @crtc: crtc whose pipe to wait for
1059  *
1060  * After disabling a pipe, we can't wait for vblank in the usual way,
1061  * spinning on the vblank interrupt status bit, since we won't actually
1062  * see an interrupt when the pipe is disabled.
1063  *
1064  * On Gen4 and above:
1065  *   wait for the pipe register state bit to turn off
1066  *
1067  * Otherwise:
1068  *   wait for the display line value to settle (it usually
1069  *   ends up stopping at the start of the next frame).
1070  *
1071  */
1072 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1073 {
1074         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1075         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1076         enum pipe pipe = crtc->pipe;
1077
1078         if (INTEL_GEN(dev_priv) >= 4) {
1079                 i915_reg_t reg = PIPECONF(cpu_transcoder);
1080
1081                 /* Wait for the Pipe State to go off */
1082                 if (intel_wait_for_register(dev_priv,
1083                                             reg, I965_PIPECONF_ACTIVE, 0,
1084                                             100))
1085                         WARN(1, "pipe_off wait timed out\n");
1086         } else {
1087                 /* Wait for the display line to settle */
1088                 if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100))
1089                         WARN(1, "pipe_off wait timed out\n");
1090         }
1091 }
1092
1093 /* Only for pre-ILK configs */
1094 void assert_pll(struct drm_i915_private *dev_priv,
1095                 enum pipe pipe, bool state)
1096 {
1097         u32 val;
1098         bool cur_state;
1099
1100         val = I915_READ(DPLL(pipe));
1101         cur_state = !!(val & DPLL_VCO_ENABLE);
1102         I915_STATE_WARN(cur_state != state,
1103              "PLL state assertion failure (expected %s, current %s)\n",
1104                         onoff(state), onoff(cur_state));
1105 }
1106
1107 /* XXX: the dsi pll is shared between MIPI DSI ports */
1108 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1109 {
1110         u32 val;
1111         bool cur_state;
1112
1113         mutex_lock(&dev_priv->sb_lock);
1114         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1115         mutex_unlock(&dev_priv->sb_lock);
1116
1117         cur_state = val & DSI_PLL_VCO_EN;
1118         I915_STATE_WARN(cur_state != state,
1119              "DSI PLL state assertion failure (expected %s, current %s)\n",
1120                         onoff(state), onoff(cur_state));
1121 }
1122
1123 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1124                           enum pipe pipe, bool state)
1125 {
1126         bool cur_state;
1127         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1128                                                                       pipe);
1129
1130         if (HAS_DDI(dev_priv)) {
1131                 /* DDI does not have a specific FDI_TX register */
1132                 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1133                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1134         } else {
1135                 u32 val = I915_READ(FDI_TX_CTL(pipe));
1136                 cur_state = !!(val & FDI_TX_ENABLE);
1137         }
1138         I915_STATE_WARN(cur_state != state,
1139              "FDI TX state assertion failure (expected %s, current %s)\n",
1140                         onoff(state), onoff(cur_state));
1141 }
1142 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1143 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1144
1145 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1146                           enum pipe pipe, bool state)
1147 {
1148         u32 val;
1149         bool cur_state;
1150
1151         val = I915_READ(FDI_RX_CTL(pipe));
1152         cur_state = !!(val & FDI_RX_ENABLE);
1153         I915_STATE_WARN(cur_state != state,
1154              "FDI RX state assertion failure (expected %s, current %s)\n",
1155                         onoff(state), onoff(cur_state));
1156 }
1157 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1158 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1159
1160 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1161                                       enum pipe pipe)
1162 {
1163         u32 val;
1164
1165         /* ILK FDI PLL is always enabled */
1166         if (IS_GEN5(dev_priv))
1167                 return;
1168
1169         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1170         if (HAS_DDI(dev_priv))
1171                 return;
1172
1173         val = I915_READ(FDI_TX_CTL(pipe));
1174         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1175 }
1176
1177 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1178                        enum pipe pipe, bool state)
1179 {
1180         u32 val;
1181         bool cur_state;
1182
1183         val = I915_READ(FDI_RX_CTL(pipe));
1184         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1185         I915_STATE_WARN(cur_state != state,
1186              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1187                         onoff(state), onoff(cur_state));
1188 }
1189
1190 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1191 {
1192         i915_reg_t pp_reg;
1193         u32 val;
1194         enum pipe panel_pipe = PIPE_A;
1195         bool locked = true;
1196
1197         if (WARN_ON(HAS_DDI(dev_priv)))
1198                 return;
1199
1200         if (HAS_PCH_SPLIT(dev_priv)) {
1201                 u32 port_sel;
1202
1203                 pp_reg = PP_CONTROL(0);
1204                 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1205
1206                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1207                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1208                         panel_pipe = PIPE_B;
1209                 /* XXX: else fix for eDP */
1210         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1211                 /* presumably write lock depends on pipe, not port select */
1212                 pp_reg = PP_CONTROL(pipe);
1213                 panel_pipe = pipe;
1214         } else {
1215                 pp_reg = PP_CONTROL(0);
1216                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1217                         panel_pipe = PIPE_B;
1218         }
1219
1220         val = I915_READ(pp_reg);
1221         if (!(val & PANEL_POWER_ON) ||
1222             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1223                 locked = false;
1224
1225         I915_STATE_WARN(panel_pipe == pipe && locked,
1226              "panel assertion failure, pipe %c regs locked\n",
1227              pipe_name(pipe));
1228 }
1229
1230 static void assert_cursor(struct drm_i915_private *dev_priv,
1231                           enum pipe pipe, bool state)
1232 {
1233         bool cur_state;
1234
1235         if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
1236                 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1237         else
1238                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1239
1240         I915_STATE_WARN(cur_state != state,
1241              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1242                         pipe_name(pipe), onoff(state), onoff(cur_state));
1243 }
1244 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1245 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1246
1247 void assert_pipe(struct drm_i915_private *dev_priv,
1248                  enum pipe pipe, bool state)
1249 {
1250         bool cur_state;
1251         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1252                                                                       pipe);
1253         enum intel_display_power_domain power_domain;
1254
1255         /* if we need the pipe quirk it must be always on */
1256         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1257             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1258                 state = true;
1259
1260         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1261         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1262                 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1263                 cur_state = !!(val & PIPECONF_ENABLE);
1264
1265                 intel_display_power_put(dev_priv, power_domain);
1266         } else {
1267                 cur_state = false;
1268         }
1269
1270         I915_STATE_WARN(cur_state != state,
1271              "pipe %c assertion failure (expected %s, current %s)\n",
1272                         pipe_name(pipe), onoff(state), onoff(cur_state));
1273 }
1274
1275 static void assert_plane(struct drm_i915_private *dev_priv,
1276                          enum plane plane, bool state)
1277 {
1278         u32 val;
1279         bool cur_state;
1280
1281         val = I915_READ(DSPCNTR(plane));
1282         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1283         I915_STATE_WARN(cur_state != state,
1284              "plane %c assertion failure (expected %s, current %s)\n",
1285                         plane_name(plane), onoff(state), onoff(cur_state));
1286 }
1287
1288 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1289 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1290
1291 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1292                                    enum pipe pipe)
1293 {
1294         int i;
1295
1296         /* Primary planes are fixed to pipes on gen4+ */
1297         if (INTEL_GEN(dev_priv) >= 4) {
1298                 u32 val = I915_READ(DSPCNTR(pipe));
1299                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1300                      "plane %c assertion failure, should be disabled but not\n",
1301                      plane_name(pipe));
1302                 return;
1303         }
1304
1305         /* Need to check both planes against the pipe */
1306         for_each_pipe(dev_priv, i) {
1307                 u32 val = I915_READ(DSPCNTR(i));
1308                 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1309                         DISPPLANE_SEL_PIPE_SHIFT;
1310                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1311                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1312                      plane_name(i), pipe_name(pipe));
1313         }
1314 }
1315
1316 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1317                                     enum pipe pipe)
1318 {
1319         int sprite;
1320
1321         if (INTEL_GEN(dev_priv) >= 9) {
1322                 for_each_sprite(dev_priv, pipe, sprite) {
1323                         u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1324                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1325                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1326                              sprite, pipe_name(pipe));
1327                 }
1328         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1329                 for_each_sprite(dev_priv, pipe, sprite) {
1330                         u32 val = I915_READ(SPCNTR(pipe, PLANE_SPRITE0 + sprite));
1331                         I915_STATE_WARN(val & SP_ENABLE,
1332                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1333                              sprite_name(pipe, sprite), pipe_name(pipe));
1334                 }
1335         } else if (INTEL_GEN(dev_priv) >= 7) {
1336                 u32 val = I915_READ(SPRCTL(pipe));
1337                 I915_STATE_WARN(val & SPRITE_ENABLE,
1338                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1339                      plane_name(pipe), pipe_name(pipe));
1340         } else if (INTEL_GEN(dev_priv) >= 5) {
1341                 u32 val = I915_READ(DVSCNTR(pipe));
1342                 I915_STATE_WARN(val & DVS_ENABLE,
1343                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1344                      plane_name(pipe), pipe_name(pipe));
1345         }
1346 }
1347
1348 static void assert_vblank_disabled(struct drm_crtc *crtc)
1349 {
1350         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1351                 drm_crtc_vblank_put(crtc);
1352 }
1353
1354 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1355                                     enum pipe pipe)
1356 {
1357         u32 val;
1358         bool enabled;
1359
1360         val = I915_READ(PCH_TRANSCONF(pipe));
1361         enabled = !!(val & TRANS_ENABLE);
1362         I915_STATE_WARN(enabled,
1363              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1364              pipe_name(pipe));
1365 }
1366
1367 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1368                             enum pipe pipe, u32 port_sel, u32 val)
1369 {
1370         if ((val & DP_PORT_EN) == 0)
1371                 return false;
1372
1373         if (HAS_PCH_CPT(dev_priv)) {
1374                 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1375                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1376                         return false;
1377         } else if (IS_CHERRYVIEW(dev_priv)) {
1378                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1379                         return false;
1380         } else {
1381                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1382                         return false;
1383         }
1384         return true;
1385 }
1386
1387 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1388                               enum pipe pipe, u32 val)
1389 {
1390         if ((val & SDVO_ENABLE) == 0)
1391                 return false;
1392
1393         if (HAS_PCH_CPT(dev_priv)) {
1394                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1395                         return false;
1396         } else if (IS_CHERRYVIEW(dev_priv)) {
1397                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1398                         return false;
1399         } else {
1400                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1401                         return false;
1402         }
1403         return true;
1404 }
1405
1406 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1407                               enum pipe pipe, u32 val)
1408 {
1409         if ((val & LVDS_PORT_EN) == 0)
1410                 return false;
1411
1412         if (HAS_PCH_CPT(dev_priv)) {
1413                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1414                         return false;
1415         } else {
1416                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1417                         return false;
1418         }
1419         return true;
1420 }
1421
1422 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1423                               enum pipe pipe, u32 val)
1424 {
1425         if ((val & ADPA_DAC_ENABLE) == 0)
1426                 return false;
1427         if (HAS_PCH_CPT(dev_priv)) {
1428                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1429                         return false;
1430         } else {
1431                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1432                         return false;
1433         }
1434         return true;
1435 }
1436
1437 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1438                                    enum pipe pipe, i915_reg_t reg,
1439                                    u32 port_sel)
1440 {
1441         u32 val = I915_READ(reg);
1442         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1443              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1444              i915_mmio_reg_offset(reg), pipe_name(pipe));
1445
1446         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1447              && (val & DP_PIPEB_SELECT),
1448              "IBX PCH dp port still using transcoder B\n");
1449 }
1450
1451 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1452                                      enum pipe pipe, i915_reg_t reg)
1453 {
1454         u32 val = I915_READ(reg);
1455         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1456              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1457              i915_mmio_reg_offset(reg), pipe_name(pipe));
1458
1459         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1460              && (val & SDVO_PIPE_B_SELECT),
1461              "IBX PCH hdmi port still using transcoder B\n");
1462 }
1463
1464 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1465                                       enum pipe pipe)
1466 {
1467         u32 val;
1468
1469         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1470         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1471         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1472
1473         val = I915_READ(PCH_ADPA);
1474         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1475              "PCH VGA enabled on transcoder %c, should be disabled\n",
1476              pipe_name(pipe));
1477
1478         val = I915_READ(PCH_LVDS);
1479         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1480              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1481              pipe_name(pipe));
1482
1483         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1484         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1485         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1486 }
1487
1488 static void _vlv_enable_pll(struct intel_crtc *crtc,
1489                             const struct intel_crtc_state *pipe_config)
1490 {
1491         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1492         enum pipe pipe = crtc->pipe;
1493
1494         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1495         POSTING_READ(DPLL(pipe));
1496         udelay(150);
1497
1498         if (intel_wait_for_register(dev_priv,
1499                                     DPLL(pipe),
1500                                     DPLL_LOCK_VLV,
1501                                     DPLL_LOCK_VLV,
1502                                     1))
1503                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1504 }
1505
1506 static void vlv_enable_pll(struct intel_crtc *crtc,
1507                            const struct intel_crtc_state *pipe_config)
1508 {
1509         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1510         enum pipe pipe = crtc->pipe;
1511
1512         assert_pipe_disabled(dev_priv, pipe);
1513
1514         /* PLL is protected by panel, make sure we can write it */
1515         assert_panel_unlocked(dev_priv, pipe);
1516
1517         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1518                 _vlv_enable_pll(crtc, pipe_config);
1519
1520         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1521         POSTING_READ(DPLL_MD(pipe));
1522 }
1523
1524
1525 static void _chv_enable_pll(struct intel_crtc *crtc,
1526                             const struct intel_crtc_state *pipe_config)
1527 {
1528         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1529         enum pipe pipe = crtc->pipe;
1530         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1531         u32 tmp;
1532
1533         mutex_lock(&dev_priv->sb_lock);
1534
1535         /* Enable back the 10bit clock to display controller */
1536         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1537         tmp |= DPIO_DCLKP_EN;
1538         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1539
1540         mutex_unlock(&dev_priv->sb_lock);
1541
1542         /*
1543          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1544          */
1545         udelay(1);
1546
1547         /* Enable PLL */
1548         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1549
1550         /* Check PLL is locked */
1551         if (intel_wait_for_register(dev_priv,
1552                                     DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1553                                     1))
1554                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1555 }
1556
1557 static void chv_enable_pll(struct intel_crtc *crtc,
1558                            const struct intel_crtc_state *pipe_config)
1559 {
1560         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1561         enum pipe pipe = crtc->pipe;
1562
1563         assert_pipe_disabled(dev_priv, pipe);
1564
1565         /* PLL is protected by panel, make sure we can write it */
1566         assert_panel_unlocked(dev_priv, pipe);
1567
1568         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1569                 _chv_enable_pll(crtc, pipe_config);
1570
1571         if (pipe != PIPE_A) {
1572                 /*
1573                  * WaPixelRepeatModeFixForC0:chv
1574                  *
1575                  * DPLLCMD is AWOL. Use chicken bits to propagate
1576                  * the value from DPLLBMD to either pipe B or C.
1577                  */
1578                 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1579                 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1580                 I915_WRITE(CBR4_VLV, 0);
1581                 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1582
1583                 /*
1584                  * DPLLB VGA mode also seems to cause problems.
1585                  * We should always have it disabled.
1586                  */
1587                 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1588         } else {
1589                 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1590                 POSTING_READ(DPLL_MD(pipe));
1591         }
1592 }
1593
1594 static int intel_num_dvo_pipes(struct drm_i915_private *dev_priv)
1595 {
1596         struct intel_crtc *crtc;
1597         int count = 0;
1598
1599         for_each_intel_crtc(&dev_priv->drm, crtc) {
1600                 count += crtc->base.state->active &&
1601                         intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO);
1602         }
1603
1604         return count;
1605 }
1606
1607 static void i9xx_enable_pll(struct intel_crtc *crtc)
1608 {
1609         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1610         i915_reg_t reg = DPLL(crtc->pipe);
1611         u32 dpll = crtc->config->dpll_hw_state.dpll;
1612
1613         assert_pipe_disabled(dev_priv, crtc->pipe);
1614
1615         /* PLL is protected by panel, make sure we can write it */
1616         if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
1617                 assert_panel_unlocked(dev_priv, crtc->pipe);
1618
1619         /* Enable DVO 2x clock on both PLLs if necessary */
1620         if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev_priv) > 0) {
1621                 /*
1622                  * It appears to be important that we don't enable this
1623                  * for the current pipe before otherwise configuring the
1624                  * PLL. No idea how this should be handled if multiple
1625                  * DVO outputs are enabled simultaneosly.
1626                  */
1627                 dpll |= DPLL_DVO_2X_MODE;
1628                 I915_WRITE(DPLL(!crtc->pipe),
1629                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1630         }
1631
1632         /*
1633          * Apparently we need to have VGA mode enabled prior to changing
1634          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1635          * dividers, even though the register value does change.
1636          */
1637         I915_WRITE(reg, 0);
1638
1639         I915_WRITE(reg, dpll);
1640
1641         /* Wait for the clocks to stabilize. */
1642         POSTING_READ(reg);
1643         udelay(150);
1644
1645         if (INTEL_GEN(dev_priv) >= 4) {
1646                 I915_WRITE(DPLL_MD(crtc->pipe),
1647                            crtc->config->dpll_hw_state.dpll_md);
1648         } else {
1649                 /* The pixel multiplier can only be updated once the
1650                  * DPLL is enabled and the clocks are stable.
1651                  *
1652                  * So write it again.
1653                  */
1654                 I915_WRITE(reg, dpll);
1655         }
1656
1657         /* We do this three times for luck */
1658         I915_WRITE(reg, dpll);
1659         POSTING_READ(reg);
1660         udelay(150); /* wait for warmup */
1661         I915_WRITE(reg, dpll);
1662         POSTING_READ(reg);
1663         udelay(150); /* wait for warmup */
1664         I915_WRITE(reg, dpll);
1665         POSTING_READ(reg);
1666         udelay(150); /* wait for warmup */
1667 }
1668
1669 /**
1670  * i9xx_disable_pll - disable a PLL
1671  * @dev_priv: i915 private structure
1672  * @pipe: pipe PLL to disable
1673  *
1674  * Disable the PLL for @pipe, making sure the pipe is off first.
1675  *
1676  * Note!  This is for pre-ILK only.
1677  */
1678 static void i9xx_disable_pll(struct intel_crtc *crtc)
1679 {
1680         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1681         enum pipe pipe = crtc->pipe;
1682
1683         /* Disable DVO 2x clock on both PLLs if necessary */
1684         if (IS_I830(dev_priv) &&
1685             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
1686             !intel_num_dvo_pipes(dev_priv)) {
1687                 I915_WRITE(DPLL(PIPE_B),
1688                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1689                 I915_WRITE(DPLL(PIPE_A),
1690                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1691         }
1692
1693         /* Don't disable pipe or pipe PLLs if needed */
1694         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1695             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1696                 return;
1697
1698         /* Make sure the pipe isn't still relying on us */
1699         assert_pipe_disabled(dev_priv, pipe);
1700
1701         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1702         POSTING_READ(DPLL(pipe));
1703 }
1704
1705 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1706 {
1707         u32 val;
1708
1709         /* Make sure the pipe isn't still relying on us */
1710         assert_pipe_disabled(dev_priv, pipe);
1711
1712         val = DPLL_INTEGRATED_REF_CLK_VLV |
1713                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1714         if (pipe != PIPE_A)
1715                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1716
1717         I915_WRITE(DPLL(pipe), val);
1718         POSTING_READ(DPLL(pipe));
1719 }
1720
1721 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1722 {
1723         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1724         u32 val;
1725
1726         /* Make sure the pipe isn't still relying on us */
1727         assert_pipe_disabled(dev_priv, pipe);
1728
1729         val = DPLL_SSC_REF_CLK_CHV |
1730                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1731         if (pipe != PIPE_A)
1732                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1733
1734         I915_WRITE(DPLL(pipe), val);
1735         POSTING_READ(DPLL(pipe));
1736
1737         mutex_lock(&dev_priv->sb_lock);
1738
1739         /* Disable 10bit clock to display controller */
1740         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1741         val &= ~DPIO_DCLKP_EN;
1742         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1743
1744         mutex_unlock(&dev_priv->sb_lock);
1745 }
1746
1747 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1748                          struct intel_digital_port *dport,
1749                          unsigned int expected_mask)
1750 {
1751         u32 port_mask;
1752         i915_reg_t dpll_reg;
1753
1754         switch (dport->port) {
1755         case PORT_B:
1756                 port_mask = DPLL_PORTB_READY_MASK;
1757                 dpll_reg = DPLL(0);
1758                 break;
1759         case PORT_C:
1760                 port_mask = DPLL_PORTC_READY_MASK;
1761                 dpll_reg = DPLL(0);
1762                 expected_mask <<= 4;
1763                 break;
1764         case PORT_D:
1765                 port_mask = DPLL_PORTD_READY_MASK;
1766                 dpll_reg = DPIO_PHY_STATUS;
1767                 break;
1768         default:
1769                 BUG();
1770         }
1771
1772         if (intel_wait_for_register(dev_priv,
1773                                     dpll_reg, port_mask, expected_mask,
1774                                     1000))
1775                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1776                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1777 }
1778
1779 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1780                                            enum pipe pipe)
1781 {
1782         struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
1783                                                                 pipe);
1784         i915_reg_t reg;
1785         uint32_t val, pipeconf_val;
1786
1787         /* Make sure PCH DPLL is enabled */
1788         assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1789
1790         /* FDI must be feeding us bits for PCH ports */
1791         assert_fdi_tx_enabled(dev_priv, pipe);
1792         assert_fdi_rx_enabled(dev_priv, pipe);
1793
1794         if (HAS_PCH_CPT(dev_priv)) {
1795                 /* Workaround: Set the timing override bit before enabling the
1796                  * pch transcoder. */
1797                 reg = TRANS_CHICKEN2(pipe);
1798                 val = I915_READ(reg);
1799                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1800                 I915_WRITE(reg, val);
1801         }
1802
1803         reg = PCH_TRANSCONF(pipe);
1804         val = I915_READ(reg);
1805         pipeconf_val = I915_READ(PIPECONF(pipe));
1806
1807         if (HAS_PCH_IBX(dev_priv)) {
1808                 /*
1809                  * Make the BPC in transcoder be consistent with
1810                  * that in pipeconf reg. For HDMI we must use 8bpc
1811                  * here for both 8bpc and 12bpc.
1812                  */
1813                 val &= ~PIPECONF_BPC_MASK;
1814                 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI))
1815                         val |= PIPECONF_8BPC;
1816                 else
1817                         val |= pipeconf_val & PIPECONF_BPC_MASK;
1818         }
1819
1820         val &= ~TRANS_INTERLACE_MASK;
1821         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1822                 if (HAS_PCH_IBX(dev_priv) &&
1823                     intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
1824                         val |= TRANS_LEGACY_INTERLACED_ILK;
1825                 else
1826                         val |= TRANS_INTERLACED;
1827         else
1828                 val |= TRANS_PROGRESSIVE;
1829
1830         I915_WRITE(reg, val | TRANS_ENABLE);
1831         if (intel_wait_for_register(dev_priv,
1832                                     reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1833                                     100))
1834                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1835 }
1836
1837 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1838                                       enum transcoder cpu_transcoder)
1839 {
1840         u32 val, pipeconf_val;
1841
1842         /* FDI must be feeding us bits for PCH ports */
1843         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1844         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1845
1846         /* Workaround: set timing override bit. */
1847         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1848         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1849         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1850
1851         val = TRANS_ENABLE;
1852         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1853
1854         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1855             PIPECONF_INTERLACED_ILK)
1856                 val |= TRANS_INTERLACED;
1857         else
1858                 val |= TRANS_PROGRESSIVE;
1859
1860         I915_WRITE(LPT_TRANSCONF, val);
1861         if (intel_wait_for_register(dev_priv,
1862                                     LPT_TRANSCONF,
1863                                     TRANS_STATE_ENABLE,
1864                                     TRANS_STATE_ENABLE,
1865                                     100))
1866                 DRM_ERROR("Failed to enable PCH transcoder\n");
1867 }
1868
1869 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1870                                             enum pipe pipe)
1871 {
1872         i915_reg_t reg;
1873         uint32_t val;
1874
1875         /* FDI relies on the transcoder */
1876         assert_fdi_tx_disabled(dev_priv, pipe);
1877         assert_fdi_rx_disabled(dev_priv, pipe);
1878
1879         /* Ports must be off as well */
1880         assert_pch_ports_disabled(dev_priv, pipe);
1881
1882         reg = PCH_TRANSCONF(pipe);
1883         val = I915_READ(reg);
1884         val &= ~TRANS_ENABLE;
1885         I915_WRITE(reg, val);
1886         /* wait for PCH transcoder off, transcoder state */
1887         if (intel_wait_for_register(dev_priv,
1888                                     reg, TRANS_STATE_ENABLE, 0,
1889                                     50))
1890                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1891
1892         if (HAS_PCH_CPT(dev_priv)) {
1893                 /* Workaround: Clear the timing override chicken bit again. */
1894                 reg = TRANS_CHICKEN2(pipe);
1895                 val = I915_READ(reg);
1896                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1897                 I915_WRITE(reg, val);
1898         }
1899 }
1900
1901 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1902 {
1903         u32 val;
1904
1905         val = I915_READ(LPT_TRANSCONF);
1906         val &= ~TRANS_ENABLE;
1907         I915_WRITE(LPT_TRANSCONF, val);
1908         /* wait for PCH transcoder off, transcoder state */
1909         if (intel_wait_for_register(dev_priv,
1910                                     LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1911                                     50))
1912                 DRM_ERROR("Failed to disable PCH transcoder\n");
1913
1914         /* Workaround: clear timing override bit. */
1915         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1916         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1917         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1918 }
1919
1920 enum transcoder intel_crtc_pch_transcoder(struct intel_crtc *crtc)
1921 {
1922         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1923
1924         WARN_ON(!crtc->config->has_pch_encoder);
1925
1926         if (HAS_PCH_LPT(dev_priv))
1927                 return TRANSCODER_A;
1928         else
1929                 return (enum transcoder) crtc->pipe;
1930 }
1931
1932 /**
1933  * intel_enable_pipe - enable a pipe, asserting requirements
1934  * @crtc: crtc responsible for the pipe
1935  *
1936  * Enable @crtc's pipe, making sure that various hardware specific requirements
1937  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1938  */
1939 static void intel_enable_pipe(struct intel_crtc *crtc)
1940 {
1941         struct drm_device *dev = crtc->base.dev;
1942         struct drm_i915_private *dev_priv = to_i915(dev);
1943         enum pipe pipe = crtc->pipe;
1944         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1945         i915_reg_t reg;
1946         u32 val;
1947
1948         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1949
1950         assert_planes_disabled(dev_priv, pipe);
1951         assert_cursor_disabled(dev_priv, pipe);
1952         assert_sprites_disabled(dev_priv, pipe);
1953
1954         /*
1955          * A pipe without a PLL won't actually be able to drive bits from
1956          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1957          * need the check.
1958          */
1959         if (HAS_GMCH_DISPLAY(dev_priv)) {
1960                 if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI))
1961                         assert_dsi_pll_enabled(dev_priv);
1962                 else
1963                         assert_pll_enabled(dev_priv, pipe);
1964         } else {
1965                 if (crtc->config->has_pch_encoder) {
1966                         /* if driving the PCH, we need FDI enabled */
1967                         assert_fdi_rx_pll_enabled(dev_priv,
1968                                                   (enum pipe) intel_crtc_pch_transcoder(crtc));
1969                         assert_fdi_tx_pll_enabled(dev_priv,
1970                                                   (enum pipe) cpu_transcoder);
1971                 }
1972                 /* FIXME: assert CPU port conditions for SNB+ */
1973         }
1974
1975         reg = PIPECONF(cpu_transcoder);
1976         val = I915_READ(reg);
1977         if (val & PIPECONF_ENABLE) {
1978                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1979                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
1980                 return;
1981         }
1982
1983         I915_WRITE(reg, val | PIPECONF_ENABLE);
1984         POSTING_READ(reg);
1985
1986         /*
1987          * Until the pipe starts DSL will read as 0, which would cause
1988          * an apparent vblank timestamp jump, which messes up also the
1989          * frame count when it's derived from the timestamps. So let's
1990          * wait for the pipe to start properly before we call
1991          * drm_crtc_vblank_on()
1992          */
1993         if (dev->max_vblank_count == 0 &&
1994             wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
1995                 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
1996 }
1997
1998 /**
1999  * intel_disable_pipe - disable a pipe, asserting requirements
2000  * @crtc: crtc whose pipes is to be disabled
2001  *
2002  * Disable the pipe of @crtc, making sure that various hardware
2003  * specific requirements are met, if applicable, e.g. plane
2004  * disabled, panel fitter off, etc.
2005  *
2006  * Will wait until the pipe has shut down before returning.
2007  */
2008 static void intel_disable_pipe(struct intel_crtc *crtc)
2009 {
2010         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2011         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2012         enum pipe pipe = crtc->pipe;
2013         i915_reg_t reg;
2014         u32 val;
2015
2016         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2017
2018         /*
2019          * Make sure planes won't keep trying to pump pixels to us,
2020          * or we might hang the display.
2021          */
2022         assert_planes_disabled(dev_priv, pipe);
2023         assert_cursor_disabled(dev_priv, pipe);
2024         assert_sprites_disabled(dev_priv, pipe);
2025
2026         reg = PIPECONF(cpu_transcoder);
2027         val = I915_READ(reg);
2028         if ((val & PIPECONF_ENABLE) == 0)
2029                 return;
2030
2031         /*
2032          * Double wide has implications for planes
2033          * so best keep it disabled when not needed.
2034          */
2035         if (crtc->config->double_wide)
2036                 val &= ~PIPECONF_DOUBLE_WIDE;
2037
2038         /* Don't disable pipe or pipe PLLs if needed */
2039         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2040             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2041                 val &= ~PIPECONF_ENABLE;
2042
2043         I915_WRITE(reg, val);
2044         if ((val & PIPECONF_ENABLE) == 0)
2045                 intel_wait_for_pipe_off(crtc);
2046 }
2047
2048 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
2049 {
2050         return IS_GEN2(dev_priv) ? 2048 : 4096;
2051 }
2052
2053 static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv,
2054                                            uint64_t fb_modifier, unsigned int cpp)
2055 {
2056         switch (fb_modifier) {
2057         case DRM_FORMAT_MOD_NONE:
2058                 return cpp;
2059         case I915_FORMAT_MOD_X_TILED:
2060                 if (IS_GEN2(dev_priv))
2061                         return 128;
2062                 else
2063                         return 512;
2064         case I915_FORMAT_MOD_Y_TILED:
2065                 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2066                         return 128;
2067                 else
2068                         return 512;
2069         case I915_FORMAT_MOD_Yf_TILED:
2070                 switch (cpp) {
2071                 case 1:
2072                         return 64;
2073                 case 2:
2074                 case 4:
2075                         return 128;
2076                 case 8:
2077                 case 16:
2078                         return 256;
2079                 default:
2080                         MISSING_CASE(cpp);
2081                         return cpp;
2082                 }
2083                 break;
2084         default:
2085                 MISSING_CASE(fb_modifier);
2086                 return cpp;
2087         }
2088 }
2089
2090 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
2091                                uint64_t fb_modifier, unsigned int cpp)
2092 {
2093         if (fb_modifier == DRM_FORMAT_MOD_NONE)
2094                 return 1;
2095         else
2096                 return intel_tile_size(dev_priv) /
2097                         intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2098 }
2099
2100 /* Return the tile dimensions in pixel units */
2101 static void intel_tile_dims(const struct drm_i915_private *dev_priv,
2102                             unsigned int *tile_width,
2103                             unsigned int *tile_height,
2104                             uint64_t fb_modifier,
2105                             unsigned int cpp)
2106 {
2107         unsigned int tile_width_bytes =
2108                 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2109
2110         *tile_width = tile_width_bytes / cpp;
2111         *tile_height = intel_tile_size(dev_priv) / tile_width_bytes;
2112 }
2113
2114 unsigned int
2115 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2116                       uint32_t pixel_format, uint64_t fb_modifier)
2117 {
2118         unsigned int cpp = drm_format_plane_cpp(pixel_format, 0);
2119         unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp);
2120
2121         return ALIGN(height, tile_height);
2122 }
2123
2124 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2125 {
2126         unsigned int size = 0;
2127         int i;
2128
2129         for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2130                 size += rot_info->plane[i].width * rot_info->plane[i].height;
2131
2132         return size;
2133 }
2134
2135 static void
2136 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2137                         const struct drm_framebuffer *fb,
2138                         unsigned int rotation)
2139 {
2140         view->type = I915_GGTT_VIEW_NORMAL;
2141         if (drm_rotation_90_or_270(rotation)) {
2142                 view->type = I915_GGTT_VIEW_ROTATED;
2143                 view->rotated = to_intel_framebuffer(fb)->rot_info;
2144         }
2145 }
2146
2147 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2148 {
2149         if (INTEL_INFO(dev_priv)->gen >= 9)
2150                 return 256 * 1024;
2151         else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
2152                  IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2153                 return 128 * 1024;
2154         else if (INTEL_INFO(dev_priv)->gen >= 4)
2155                 return 4 * 1024;
2156         else
2157                 return 0;
2158 }
2159
2160 static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv,
2161                                          uint64_t fb_modifier)
2162 {
2163         switch (fb_modifier) {
2164         case DRM_FORMAT_MOD_NONE:
2165                 return intel_linear_alignment(dev_priv);
2166         case I915_FORMAT_MOD_X_TILED:
2167                 if (INTEL_INFO(dev_priv)->gen >= 9)
2168                         return 256 * 1024;
2169                 return 0;
2170         case I915_FORMAT_MOD_Y_TILED:
2171         case I915_FORMAT_MOD_Yf_TILED:
2172                 return 1 * 1024 * 1024;
2173         default:
2174                 MISSING_CASE(fb_modifier);
2175                 return 0;
2176         }
2177 }
2178
2179 struct i915_vma *
2180 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2181 {
2182         struct drm_device *dev = fb->dev;
2183         struct drm_i915_private *dev_priv = to_i915(dev);
2184         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2185         struct i915_ggtt_view view;
2186         struct i915_vma *vma;
2187         u32 alignment;
2188
2189         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2190
2191         alignment = intel_surf_alignment(dev_priv, fb->modifier);
2192
2193         intel_fill_fb_ggtt_view(&view, fb, rotation);
2194
2195         /* Note that the w/a also requires 64 PTE of padding following the
2196          * bo. We currently fill all unused PTE with the shadow page and so
2197          * we should always have valid PTE following the scanout preventing
2198          * the VT-d warning.
2199          */
2200         if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2201                 alignment = 256 * 1024;
2202
2203         /*
2204          * Global gtt pte registers are special registers which actually forward
2205          * writes to a chunk of system memory. Which means that there is no risk
2206          * that the register values disappear as soon as we call
2207          * intel_runtime_pm_put(), so it is correct to wrap only the
2208          * pin/unpin/fence and not more.
2209          */
2210         intel_runtime_pm_get(dev_priv);
2211
2212         vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view);
2213         if (IS_ERR(vma))
2214                 goto err;
2215
2216         if (i915_vma_is_map_and_fenceable(vma)) {
2217                 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2218                  * fence, whereas 965+ only requires a fence if using
2219                  * framebuffer compression.  For simplicity, we always, when
2220                  * possible, install a fence as the cost is not that onerous.
2221                  *
2222                  * If we fail to fence the tiled scanout, then either the
2223                  * modeset will reject the change (which is highly unlikely as
2224                  * the affected systems, all but one, do not have unmappable
2225                  * space) or we will not be able to enable full powersaving
2226                  * techniques (also likely not to apply due to various limits
2227                  * FBC and the like impose on the size of the buffer, which
2228                  * presumably we violated anyway with this unmappable buffer).
2229                  * Anyway, it is presumably better to stumble onwards with
2230                  * something and try to run the system in a "less than optimal"
2231                  * mode that matches the user configuration.
2232                  */
2233                 if (i915_vma_get_fence(vma) == 0)
2234                         i915_vma_pin_fence(vma);
2235         }
2236
2237         i915_vma_get(vma);
2238 err:
2239         intel_runtime_pm_put(dev_priv);
2240         return vma;
2241 }
2242
2243 void intel_unpin_fb_vma(struct i915_vma *vma)
2244 {
2245         lockdep_assert_held(&vma->vm->i915->drm.struct_mutex);
2246
2247         i915_vma_unpin_fence(vma);
2248         i915_gem_object_unpin_from_display_plane(vma);
2249         i915_vma_put(vma);
2250 }
2251
2252 static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane,
2253                           unsigned int rotation)
2254 {
2255         if (drm_rotation_90_or_270(rotation))
2256                 return to_intel_framebuffer(fb)->rotated[plane].pitch;
2257         else
2258                 return fb->pitches[plane];
2259 }
2260
2261 /*
2262  * Convert the x/y offsets into a linear offset.
2263  * Only valid with 0/180 degree rotation, which is fine since linear
2264  * offset is only used with linear buffers on pre-hsw and tiled buffers
2265  * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2266  */
2267 u32 intel_fb_xy_to_linear(int x, int y,
2268                           const struct intel_plane_state *state,
2269                           int plane)
2270 {
2271         const struct drm_framebuffer *fb = state->base.fb;
2272         unsigned int cpp = fb->format->cpp[plane];
2273         unsigned int pitch = fb->pitches[plane];
2274
2275         return y * pitch + x * cpp;
2276 }
2277
2278 /*
2279  * Add the x/y offsets derived from fb->offsets[] to the user
2280  * specified plane src x/y offsets. The resulting x/y offsets
2281  * specify the start of scanout from the beginning of the gtt mapping.
2282  */
2283 void intel_add_fb_offsets(int *x, int *y,
2284                           const struct intel_plane_state *state,
2285                           int plane)
2286
2287 {
2288         const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
2289         unsigned int rotation = state->base.rotation;
2290
2291         if (drm_rotation_90_or_270(rotation)) {
2292                 *x += intel_fb->rotated[plane].x;
2293                 *y += intel_fb->rotated[plane].y;
2294         } else {
2295                 *x += intel_fb->normal[plane].x;
2296                 *y += intel_fb->normal[plane].y;
2297         }
2298 }
2299
2300 /*
2301  * Input tile dimensions and pitch must already be
2302  * rotated to match x and y, and in pixel units.
2303  */
2304 static u32 _intel_adjust_tile_offset(int *x, int *y,
2305                                      unsigned int tile_width,
2306                                      unsigned int tile_height,
2307                                      unsigned int tile_size,
2308                                      unsigned int pitch_tiles,
2309                                      u32 old_offset,
2310                                      u32 new_offset)
2311 {
2312         unsigned int pitch_pixels = pitch_tiles * tile_width;
2313         unsigned int tiles;
2314
2315         WARN_ON(old_offset & (tile_size - 1));
2316         WARN_ON(new_offset & (tile_size - 1));
2317         WARN_ON(new_offset > old_offset);
2318
2319         tiles = (old_offset - new_offset) / tile_size;
2320
2321         *y += tiles / pitch_tiles * tile_height;
2322         *x += tiles % pitch_tiles * tile_width;
2323
2324         /* minimize x in case it got needlessly big */
2325         *y += *x / pitch_pixels * tile_height;
2326         *x %= pitch_pixels;
2327
2328         return new_offset;
2329 }
2330
2331 /*
2332  * Adjust the tile offset by moving the difference into
2333  * the x/y offsets.
2334  */
2335 static u32 intel_adjust_tile_offset(int *x, int *y,
2336                                     const struct intel_plane_state *state, int plane,
2337                                     u32 old_offset, u32 new_offset)
2338 {
2339         const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2340         const struct drm_framebuffer *fb = state->base.fb;
2341         unsigned int cpp = fb->format->cpp[plane];
2342         unsigned int rotation = state->base.rotation;
2343         unsigned int pitch = intel_fb_pitch(fb, plane, rotation);
2344
2345         WARN_ON(new_offset > old_offset);
2346
2347         if (fb->modifier != DRM_FORMAT_MOD_NONE) {
2348                 unsigned int tile_size, tile_width, tile_height;
2349                 unsigned int pitch_tiles;
2350
2351                 tile_size = intel_tile_size(dev_priv);
2352                 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2353                                 fb->modifier, cpp);
2354
2355                 if (drm_rotation_90_or_270(rotation)) {
2356                         pitch_tiles = pitch / tile_height;
2357                         swap(tile_width, tile_height);
2358                 } else {
2359                         pitch_tiles = pitch / (tile_width * cpp);
2360                 }
2361
2362                 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2363                                           tile_size, pitch_tiles,
2364                                           old_offset, new_offset);
2365         } else {
2366                 old_offset += *y * pitch + *x * cpp;
2367
2368                 *y = (old_offset - new_offset) / pitch;
2369                 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2370         }
2371
2372         return new_offset;
2373 }
2374
2375 /*
2376  * Computes the linear offset to the base tile and adjusts
2377  * x, y. bytes per pixel is assumed to be a power-of-two.
2378  *
2379  * In the 90/270 rotated case, x and y are assumed
2380  * to be already rotated to match the rotated GTT view, and
2381  * pitch is the tile_height aligned framebuffer height.
2382  *
2383  * This function is used when computing the derived information
2384  * under intel_framebuffer, so using any of that information
2385  * here is not allowed. Anything under drm_framebuffer can be
2386  * used. This is why the user has to pass in the pitch since it
2387  * is specified in the rotated orientation.
2388  */
2389 static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv,
2390                                       int *x, int *y,
2391                                       const struct drm_framebuffer *fb, int plane,
2392                                       unsigned int pitch,
2393                                       unsigned int rotation,
2394                                       u32 alignment)
2395 {
2396         uint64_t fb_modifier = fb->modifier;
2397         unsigned int cpp = fb->format->cpp[plane];
2398         u32 offset, offset_aligned;
2399
2400         if (alignment)
2401                 alignment--;
2402
2403         if (fb_modifier != DRM_FORMAT_MOD_NONE) {
2404                 unsigned int tile_size, tile_width, tile_height;
2405                 unsigned int tile_rows, tiles, pitch_tiles;
2406
2407                 tile_size = intel_tile_size(dev_priv);
2408                 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2409                                 fb_modifier, cpp);
2410
2411                 if (drm_rotation_90_or_270(rotation)) {
2412                         pitch_tiles = pitch / tile_height;
2413                         swap(tile_width, tile_height);
2414                 } else {
2415                         pitch_tiles = pitch / (tile_width * cpp);
2416                 }
2417
2418                 tile_rows = *y / tile_height;
2419                 *y %= tile_height;
2420
2421                 tiles = *x / tile_width;
2422                 *x %= tile_width;
2423
2424                 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2425                 offset_aligned = offset & ~alignment;
2426
2427                 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2428                                           tile_size, pitch_tiles,
2429                                           offset, offset_aligned);
2430         } else {
2431                 offset = *y * pitch + *x * cpp;
2432                 offset_aligned = offset & ~alignment;
2433
2434                 *y = (offset & alignment) / pitch;
2435                 *x = ((offset & alignment) - *y * pitch) / cpp;
2436         }
2437
2438         return offset_aligned;
2439 }
2440
2441 u32 intel_compute_tile_offset(int *x, int *y,
2442                               const struct intel_plane_state *state,
2443                               int plane)
2444 {
2445         const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2446         const struct drm_framebuffer *fb = state->base.fb;
2447         unsigned int rotation = state->base.rotation;
2448         int pitch = intel_fb_pitch(fb, plane, rotation);
2449         u32 alignment;
2450
2451         /* AUX_DIST needs only 4K alignment */
2452         if (fb->format->format == DRM_FORMAT_NV12 && plane == 1)
2453                 alignment = 4096;
2454         else
2455                 alignment = intel_surf_alignment(dev_priv, fb->modifier);
2456
2457         return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch,
2458                                           rotation, alignment);
2459 }
2460
2461 /* Convert the fb->offset[] linear offset into x/y offsets */
2462 static void intel_fb_offset_to_xy(int *x, int *y,
2463                                   const struct drm_framebuffer *fb, int plane)
2464 {
2465         unsigned int cpp = fb->format->cpp[plane];
2466         unsigned int pitch = fb->pitches[plane];
2467         u32 linear_offset = fb->offsets[plane];
2468
2469         *y = linear_offset / pitch;
2470         *x = linear_offset % pitch / cpp;
2471 }
2472
2473 static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier)
2474 {
2475         switch (fb_modifier) {
2476         case I915_FORMAT_MOD_X_TILED:
2477                 return I915_TILING_X;
2478         case I915_FORMAT_MOD_Y_TILED:
2479                 return I915_TILING_Y;
2480         default:
2481                 return I915_TILING_NONE;
2482         }
2483 }
2484
2485 static int
2486 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2487                    struct drm_framebuffer *fb)
2488 {
2489         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2490         struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2491         u32 gtt_offset_rotated = 0;
2492         unsigned int max_size = 0;
2493         int i, num_planes = fb->format->num_planes;
2494         unsigned int tile_size = intel_tile_size(dev_priv);
2495
2496         for (i = 0; i < num_planes; i++) {
2497                 unsigned int width, height;
2498                 unsigned int cpp, size;
2499                 u32 offset;
2500                 int x, y;
2501
2502                 cpp = fb->format->cpp[i];
2503                 width = drm_framebuffer_plane_width(fb->width, fb, i);
2504                 height = drm_framebuffer_plane_height(fb->height, fb, i);
2505
2506                 intel_fb_offset_to_xy(&x, &y, fb, i);
2507
2508                 /*
2509                  * The fence (if used) is aligned to the start of the object
2510                  * so having the framebuffer wrap around across the edge of the
2511                  * fenced region doesn't really work. We have no API to configure
2512                  * the fence start offset within the object (nor could we probably
2513                  * on gen2/3). So it's just easier if we just require that the
2514                  * fb layout agrees with the fence layout. We already check that the
2515                  * fb stride matches the fence stride elsewhere.
2516                  */
2517                 if (i915_gem_object_is_tiled(intel_fb->obj) &&
2518                     (x + width) * cpp > fb->pitches[i]) {
2519                         DRM_DEBUG("bad fb plane %d offset: 0x%x\n",
2520                                   i, fb->offsets[i]);
2521                         return -EINVAL;
2522                 }
2523
2524                 /*
2525                  * First pixel of the framebuffer from
2526                  * the start of the normal gtt mapping.
2527                  */
2528                 intel_fb->normal[i].x = x;
2529                 intel_fb->normal[i].y = y;
2530
2531                 offset = _intel_compute_tile_offset(dev_priv, &x, &y,
2532                                                     fb, 0, fb->pitches[i],
2533                                                     DRM_ROTATE_0, tile_size);
2534                 offset /= tile_size;
2535
2536                 if (fb->modifier != DRM_FORMAT_MOD_NONE) {
2537                         unsigned int tile_width, tile_height;
2538                         unsigned int pitch_tiles;
2539                         struct drm_rect r;
2540
2541                         intel_tile_dims(dev_priv, &tile_width, &tile_height,
2542                                         fb->modifier, cpp);
2543
2544                         rot_info->plane[i].offset = offset;
2545                         rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2546                         rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2547                         rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2548
2549                         intel_fb->rotated[i].pitch =
2550                                 rot_info->plane[i].height * tile_height;
2551
2552                         /* how many tiles does this plane need */
2553                         size = rot_info->plane[i].stride * rot_info->plane[i].height;
2554                         /*
2555                          * If the plane isn't horizontally tile aligned,
2556                          * we need one more tile.
2557                          */
2558                         if (x != 0)
2559                                 size++;
2560
2561                         /* rotate the x/y offsets to match the GTT view */
2562                         r.x1 = x;
2563                         r.y1 = y;
2564                         r.x2 = x + width;
2565                         r.y2 = y + height;
2566                         drm_rect_rotate(&r,
2567                                         rot_info->plane[i].width * tile_width,
2568                                         rot_info->plane[i].height * tile_height,
2569                                         DRM_ROTATE_270);
2570                         x = r.x1;
2571                         y = r.y1;
2572
2573                         /* rotate the tile dimensions to match the GTT view */
2574                         pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2575                         swap(tile_width, tile_height);
2576
2577                         /*
2578                          * We only keep the x/y offsets, so push all of the
2579                          * gtt offset into the x/y offsets.
2580                          */
2581                         _intel_adjust_tile_offset(&x, &y, tile_size,
2582                                                   tile_width, tile_height, pitch_tiles,
2583                                                   gtt_offset_rotated * tile_size, 0);
2584
2585                         gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2586
2587                         /*
2588                          * First pixel of the framebuffer from
2589                          * the start of the rotated gtt mapping.
2590                          */
2591                         intel_fb->rotated[i].x = x;
2592                         intel_fb->rotated[i].y = y;
2593                 } else {
2594                         size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2595                                             x * cpp, tile_size);
2596                 }
2597
2598                 /* how many tiles in total needed in the bo */
2599                 max_size = max(max_size, offset + size);
2600         }
2601
2602         if (max_size * tile_size > to_intel_framebuffer(fb)->obj->base.size) {
2603                 DRM_DEBUG("fb too big for bo (need %u bytes, have %zu bytes)\n",
2604                           max_size * tile_size, to_intel_framebuffer(fb)->obj->base.size);
2605                 return -EINVAL;
2606         }
2607
2608         return 0;
2609 }
2610
2611 static int i9xx_format_to_fourcc(int format)
2612 {
2613         switch (format) {
2614         case DISPPLANE_8BPP:
2615                 return DRM_FORMAT_C8;
2616         case DISPPLANE_BGRX555:
2617                 return DRM_FORMAT_XRGB1555;
2618         case DISPPLANE_BGRX565:
2619                 return DRM_FORMAT_RGB565;
2620         default:
2621         case DISPPLANE_BGRX888:
2622                 return DRM_FORMAT_XRGB8888;
2623         case DISPPLANE_RGBX888:
2624                 return DRM_FORMAT_XBGR8888;
2625         case DISPPLANE_BGRX101010:
2626                 return DRM_FORMAT_XRGB2101010;
2627         case DISPPLANE_RGBX101010:
2628                 return DRM_FORMAT_XBGR2101010;
2629         }
2630 }
2631
2632 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2633 {
2634         switch (format) {
2635         case PLANE_CTL_FORMAT_RGB_565:
2636                 return DRM_FORMAT_RGB565;
2637         default:
2638         case PLANE_CTL_FORMAT_XRGB_8888:
2639                 if (rgb_order) {
2640                         if (alpha)
2641                                 return DRM_FORMAT_ABGR8888;
2642                         else
2643                                 return DRM_FORMAT_XBGR8888;
2644                 } else {
2645                         if (alpha)
2646                                 return DRM_FORMAT_ARGB8888;
2647                         else
2648                                 return DRM_FORMAT_XRGB8888;
2649                 }
2650         case PLANE_CTL_FORMAT_XRGB_2101010:
2651                 if (rgb_order)
2652                         return DRM_FORMAT_XBGR2101010;
2653                 else
2654                         return DRM_FORMAT_XRGB2101010;
2655         }
2656 }
2657
2658 static bool
2659 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2660                               struct intel_initial_plane_config *plane_config)
2661 {
2662         struct drm_device *dev = crtc->base.dev;
2663         struct drm_i915_private *dev_priv = to_i915(dev);
2664         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2665         struct drm_i915_gem_object *obj = NULL;
2666         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2667         struct drm_framebuffer *fb = &plane_config->fb->base;
2668         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2669         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2670                                     PAGE_SIZE);
2671
2672         size_aligned -= base_aligned;
2673
2674         if (plane_config->size == 0)
2675                 return false;
2676
2677         /* If the FB is too big, just don't use it since fbdev is not very
2678          * important and we should probably use that space with FBC or other
2679          * features. */
2680         if (size_aligned * 2 > ggtt->stolen_usable_size)
2681                 return false;
2682
2683         mutex_lock(&dev->struct_mutex);
2684
2685         obj = i915_gem_object_create_stolen_for_preallocated(dev_priv,
2686                                                              base_aligned,
2687                                                              base_aligned,
2688                                                              size_aligned);
2689         if (!obj) {
2690                 mutex_unlock(&dev->struct_mutex);
2691                 return false;
2692         }
2693
2694         if (plane_config->tiling == I915_TILING_X)
2695                 obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X;
2696
2697         mode_cmd.pixel_format = fb->format->format;
2698         mode_cmd.width = fb->width;
2699         mode_cmd.height = fb->height;
2700         mode_cmd.pitches[0] = fb->pitches[0];
2701         mode_cmd.modifier[0] = fb->modifier;
2702         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2703
2704         if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2705                                    &mode_cmd, obj)) {
2706                 DRM_DEBUG_KMS("intel fb init failed\n");
2707                 goto out_unref_obj;
2708         }
2709
2710         mutex_unlock(&dev->struct_mutex);
2711
2712         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2713         return true;
2714
2715 out_unref_obj:
2716         i915_gem_object_put(obj);
2717         mutex_unlock(&dev->struct_mutex);
2718         return false;
2719 }
2720
2721 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2722 static void
2723 update_state_fb(struct drm_plane *plane)
2724 {
2725         if (plane->fb == plane->state->fb)
2726                 return;
2727
2728         if (plane->state->fb)
2729                 drm_framebuffer_unreference(plane->state->fb);
2730         plane->state->fb = plane->fb;
2731         if (plane->state->fb)
2732                 drm_framebuffer_reference(plane->state->fb);
2733 }
2734
2735 static void
2736 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2737                              struct intel_initial_plane_config *plane_config)
2738 {
2739         struct drm_device *dev = intel_crtc->base.dev;
2740         struct drm_i915_private *dev_priv = to_i915(dev);
2741         struct drm_crtc *c;
2742         struct drm_i915_gem_object *obj;
2743         struct drm_plane *primary = intel_crtc->base.primary;
2744         struct drm_plane_state *plane_state = primary->state;
2745         struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2746         struct intel_plane *intel_plane = to_intel_plane(primary);
2747         struct intel_plane_state *intel_state =
2748                 to_intel_plane_state(plane_state);
2749         struct drm_framebuffer *fb;
2750
2751         if (!plane_config->fb)
2752                 return;
2753
2754         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2755                 fb = &plane_config->fb->base;
2756                 goto valid_fb;
2757         }
2758
2759         kfree(plane_config->fb);
2760
2761         /*
2762          * Failed to alloc the obj, check to see if we should share
2763          * an fb with another CRTC instead
2764          */
2765         for_each_crtc(dev, c) {
2766                 struct intel_plane_state *state;
2767
2768                 if (c == &intel_crtc->base)
2769                         continue;
2770
2771                 if (!to_intel_crtc(c)->active)
2772                         continue;
2773
2774                 state = to_intel_plane_state(c->primary->state);
2775                 if (!state->vma)
2776                         continue;
2777
2778                 if (intel_plane_ggtt_offset(state) == plane_config->base) {
2779                         fb = c->primary->fb;
2780                         drm_framebuffer_reference(fb);
2781                         goto valid_fb;
2782                 }
2783         }
2784
2785         /*
2786          * We've failed to reconstruct the BIOS FB.  Current display state
2787          * indicates that the primary plane is visible, but has a NULL FB,
2788          * which will lead to problems later if we don't fix it up.  The
2789          * simplest solution is to just disable the primary plane now and
2790          * pretend the BIOS never had it enabled.
2791          */
2792         plane_state->visible = false;
2793         crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
2794         intel_pre_disable_primary_noatomic(&intel_crtc->base);
2795         intel_plane->disable_plane(primary, &intel_crtc->base);
2796
2797         return;
2798
2799 valid_fb:
2800         mutex_lock(&dev->struct_mutex);
2801         intel_state->vma =
2802                 intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
2803         mutex_unlock(&dev->struct_mutex);
2804         if (IS_ERR(intel_state->vma)) {
2805                 DRM_ERROR("failed to pin boot fb on pipe %d: %li\n",
2806                           intel_crtc->pipe, PTR_ERR(intel_state->vma));
2807
2808                 intel_state->vma = NULL;
2809                 drm_framebuffer_unreference(fb);
2810                 return;
2811         }
2812
2813         plane_state->src_x = 0;
2814         plane_state->src_y = 0;
2815         plane_state->src_w = fb->width << 16;
2816         plane_state->src_h = fb->height << 16;
2817
2818         plane_state->crtc_x = 0;
2819         plane_state->crtc_y = 0;
2820         plane_state->crtc_w = fb->width;
2821         plane_state->crtc_h = fb->height;
2822
2823         intel_state->base.src = drm_plane_state_src(plane_state);
2824         intel_state->base.dst = drm_plane_state_dest(plane_state);
2825
2826         obj = intel_fb_obj(fb);
2827         if (i915_gem_object_is_tiled(obj))
2828                 dev_priv->preserve_bios_swizzle = true;
2829
2830         drm_framebuffer_reference(fb);
2831         primary->fb = primary->state->fb = fb;
2832         primary->crtc = primary->state->crtc = &intel_crtc->base;
2833         intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2834         atomic_or(to_intel_plane(primary)->frontbuffer_bit,
2835                   &obj->frontbuffer_bits);
2836 }
2837
2838 static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane,
2839                                unsigned int rotation)
2840 {
2841         int cpp = fb->format->cpp[plane];
2842
2843         switch (fb->modifier) {
2844         case DRM_FORMAT_MOD_NONE:
2845         case I915_FORMAT_MOD_X_TILED:
2846                 switch (cpp) {
2847                 case 8:
2848                         return 4096;
2849                 case 4:
2850                 case 2:
2851                 case 1:
2852                         return 8192;
2853                 default:
2854                         MISSING_CASE(cpp);
2855                         break;
2856                 }
2857                 break;
2858         case I915_FORMAT_MOD_Y_TILED:
2859         case I915_FORMAT_MOD_Yf_TILED:
2860                 switch (cpp) {
2861                 case 8:
2862                         return 2048;
2863                 case 4:
2864                         return 4096;
2865                 case 2:
2866                 case 1:
2867                         return 8192;
2868                 default:
2869                         MISSING_CASE(cpp);
2870                         break;
2871                 }
2872                 break;
2873         default:
2874                 MISSING_CASE(fb->modifier);
2875         }
2876
2877         return 2048;
2878 }
2879
2880 static int skl_check_main_surface(struct intel_plane_state *plane_state)
2881 {
2882         const struct drm_i915_private *dev_priv = to_i915(plane_state->base.plane->dev);
2883         const struct drm_framebuffer *fb = plane_state->base.fb;
2884         unsigned int rotation = plane_state->base.rotation;
2885         int x = plane_state->base.src.x1 >> 16;
2886         int y = plane_state->base.src.y1 >> 16;
2887         int w = drm_rect_width(&plane_state->base.src) >> 16;
2888         int h = drm_rect_height(&plane_state->base.src) >> 16;
2889         int max_width = skl_max_plane_width(fb, 0, rotation);
2890         int max_height = 4096;
2891         u32 alignment, offset, aux_offset = plane_state->aux.offset;
2892
2893         if (w > max_width || h > max_height) {
2894                 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
2895                               w, h, max_width, max_height);
2896                 return -EINVAL;
2897         }
2898
2899         intel_add_fb_offsets(&x, &y, plane_state, 0);
2900         offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
2901
2902         alignment = intel_surf_alignment(dev_priv, fb->modifier);
2903
2904         /*
2905          * AUX surface offset is specified as the distance from the
2906          * main surface offset, and it must be non-negative. Make
2907          * sure that is what we will get.
2908          */
2909         if (offset > aux_offset)
2910                 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2911                                                   offset, aux_offset & ~(alignment - 1));
2912
2913         /*
2914          * When using an X-tiled surface, the plane blows up
2915          * if the x offset + width exceed the stride.
2916          *
2917          * TODO: linear and Y-tiled seem fine, Yf untested,
2918          */
2919         if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
2920                 int cpp = fb->format->cpp[0];
2921
2922                 while ((x + w) * cpp > fb->pitches[0]) {
2923                         if (offset == 0) {
2924                                 DRM_DEBUG_KMS("Unable to find suitable display surface offset\n");
2925                                 return -EINVAL;
2926                         }
2927
2928                         offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2929                                                           offset, offset - alignment);
2930                 }
2931         }
2932
2933         plane_state->main.offset = offset;
2934         plane_state->main.x = x;
2935         plane_state->main.y = y;
2936
2937         return 0;
2938 }
2939
2940 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
2941 {
2942         const struct drm_framebuffer *fb = plane_state->base.fb;
2943         unsigned int rotation = plane_state->base.rotation;
2944         int max_width = skl_max_plane_width(fb, 1, rotation);
2945         int max_height = 4096;
2946         int x = plane_state->base.src.x1 >> 17;
2947         int y = plane_state->base.src.y1 >> 17;
2948         int w = drm_rect_width(&plane_state->base.src) >> 17;
2949         int h = drm_rect_height(&plane_state->base.src) >> 17;
2950         u32 offset;
2951
2952         intel_add_fb_offsets(&x, &y, plane_state, 1);
2953         offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
2954
2955         /* FIXME not quite sure how/if these apply to the chroma plane */
2956         if (w > max_width || h > max_height) {
2957                 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
2958                               w, h, max_width, max_height);
2959                 return -EINVAL;
2960         }
2961
2962         plane_state->aux.offset = offset;
2963         plane_state->aux.x = x;
2964         plane_state->aux.y = y;
2965
2966         return 0;
2967 }
2968
2969 int skl_check_plane_surface(struct intel_plane_state *plane_state)
2970 {
2971         const struct drm_framebuffer *fb = plane_state->base.fb;
2972         unsigned int rotation = plane_state->base.rotation;
2973         int ret;
2974
2975         if (!plane_state->base.visible)
2976                 return 0;
2977
2978         /* Rotate src coordinates to match rotated GTT view */
2979         if (drm_rotation_90_or_270(rotation))
2980                 drm_rect_rotate(&plane_state->base.src,
2981                                 fb->width << 16, fb->height << 16,
2982                                 DRM_ROTATE_270);
2983
2984         /*
2985          * Handle the AUX surface first since
2986          * the main surface setup depends on it.
2987          */
2988         if (fb->format->format == DRM_FORMAT_NV12) {
2989                 ret = skl_check_nv12_aux_surface(plane_state);
2990                 if (ret)
2991                         return ret;
2992         } else {
2993                 plane_state->aux.offset = ~0xfff;
2994                 plane_state->aux.x = 0;
2995                 plane_state->aux.y = 0;
2996         }
2997
2998         ret = skl_check_main_surface(plane_state);
2999         if (ret)
3000                 return ret;
3001
3002         return 0;
3003 }
3004
3005 static void i9xx_update_primary_plane(struct drm_plane *primary,
3006                                       const struct intel_crtc_state *crtc_state,
3007                                       const struct intel_plane_state *plane_state)
3008 {
3009         struct drm_i915_private *dev_priv = to_i915(primary->dev);
3010         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3011         struct drm_framebuffer *fb = plane_state->base.fb;
3012         int plane = intel_crtc->plane;
3013         u32 linear_offset;
3014         u32 dspcntr;
3015         i915_reg_t reg = DSPCNTR(plane);
3016         unsigned int rotation = plane_state->base.rotation;
3017         int x = plane_state->base.src.x1 >> 16;
3018         int y = plane_state->base.src.y1 >> 16;
3019
3020         dspcntr = DISPPLANE_GAMMA_ENABLE;
3021
3022         dspcntr |= DISPLAY_PLANE_ENABLE;
3023
3024         if (INTEL_GEN(dev_priv) < 4) {
3025                 if (intel_crtc->pipe == PIPE_B)
3026                         dspcntr |= DISPPLANE_SEL_PIPE_B;
3027
3028                 /* pipesrc and dspsize control the size that is scaled from,
3029                  * which should always be the user's requested size.
3030                  */
3031                 I915_WRITE(DSPSIZE(plane),
3032                            ((crtc_state->pipe_src_h - 1) << 16) |
3033                            (crtc_state->pipe_src_w - 1));
3034                 I915_WRITE(DSPPOS(plane), 0);
3035         } else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) {
3036                 I915_WRITE(PRIMSIZE(plane),
3037                            ((crtc_state->pipe_src_h - 1) << 16) |
3038                            (crtc_state->pipe_src_w - 1));
3039                 I915_WRITE(PRIMPOS(plane), 0);
3040                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
3041         }
3042
3043         switch (fb->format->format) {
3044         case DRM_FORMAT_C8:
3045                 dspcntr |= DISPPLANE_8BPP;
3046                 break;
3047         case DRM_FORMAT_XRGB1555:
3048                 dspcntr |= DISPPLANE_BGRX555;
3049                 break;
3050         case DRM_FORMAT_RGB565:
3051                 dspcntr |= DISPPLANE_BGRX565;
3052                 break;
3053         case DRM_FORMAT_XRGB8888:
3054                 dspcntr |= DISPPLANE_BGRX888;
3055                 break;
3056         case DRM_FORMAT_XBGR8888:
3057                 dspcntr |= DISPPLANE_RGBX888;
3058                 break;
3059         case DRM_FORMAT_XRGB2101010:
3060                 dspcntr |= DISPPLANE_BGRX101010;
3061                 break;
3062         case DRM_FORMAT_XBGR2101010:
3063                 dspcntr |= DISPPLANE_RGBX101010;
3064                 break;
3065         default:
3066                 BUG();
3067         }
3068
3069         if (INTEL_GEN(dev_priv) >= 4 &&
3070             fb->modifier == I915_FORMAT_MOD_X_TILED)
3071                 dspcntr |= DISPPLANE_TILED;
3072
3073         if (rotation & DRM_ROTATE_180)
3074                 dspcntr |= DISPPLANE_ROTATE_180;
3075
3076         if (rotation & DRM_REFLECT_X)
3077                 dspcntr |= DISPPLANE_MIRROR;
3078
3079         if (IS_G4X(dev_priv))
3080                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3081
3082         intel_add_fb_offsets(&x, &y, plane_state, 0);
3083
3084         if (INTEL_GEN(dev_priv) >= 4)
3085                 intel_crtc->dspaddr_offset =
3086                         intel_compute_tile_offset(&x, &y, plane_state, 0);
3087
3088         if (rotation & DRM_ROTATE_180) {
3089                 x += crtc_state->pipe_src_w - 1;
3090                 y += crtc_state->pipe_src_h - 1;
3091         } else if (rotation & DRM_REFLECT_X) {
3092                 x += crtc_state->pipe_src_w - 1;
3093         }
3094
3095         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3096
3097         if (INTEL_GEN(dev_priv) < 4)
3098                 intel_crtc->dspaddr_offset = linear_offset;
3099
3100         intel_crtc->adjusted_x = x;
3101         intel_crtc->adjusted_y = y;
3102
3103         I915_WRITE(reg, dspcntr);
3104
3105         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
3106         if (INTEL_GEN(dev_priv) >= 4) {
3107                 I915_WRITE(DSPSURF(plane),
3108                            intel_plane_ggtt_offset(plane_state) +
3109                            intel_crtc->dspaddr_offset);
3110                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
3111                 I915_WRITE(DSPLINOFF(plane), linear_offset);
3112         } else {
3113                 I915_WRITE(DSPADDR(plane),
3114                            intel_plane_ggtt_offset(plane_state) +
3115                            intel_crtc->dspaddr_offset);
3116         }
3117         POSTING_READ(reg);
3118 }
3119
3120 static void i9xx_disable_primary_plane(struct drm_plane *primary,
3121                                        struct drm_crtc *crtc)
3122 {
3123         struct drm_device *dev = crtc->dev;
3124         struct drm_i915_private *dev_priv = to_i915(dev);
3125         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3126         int plane = intel_crtc->plane;
3127
3128         I915_WRITE(DSPCNTR(plane), 0);
3129         if (INTEL_INFO(dev_priv)->gen >= 4)
3130                 I915_WRITE(DSPSURF(plane), 0);
3131         else
3132                 I915_WRITE(DSPADDR(plane), 0);
3133         POSTING_READ(DSPCNTR(plane));
3134 }
3135
3136 static void ironlake_update_primary_plane(struct drm_plane *primary,
3137                                           const struct intel_crtc_state *crtc_state,
3138                                           const struct intel_plane_state *plane_state)
3139 {
3140         struct drm_device *dev = primary->dev;
3141         struct drm_i915_private *dev_priv = to_i915(dev);
3142         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3143         struct drm_framebuffer *fb = plane_state->base.fb;
3144         int plane = intel_crtc->plane;
3145         u32 linear_offset;
3146         u32 dspcntr;
3147         i915_reg_t reg = DSPCNTR(plane);
3148         unsigned int rotation = plane_state->base.rotation;
3149         int x = plane_state->base.src.x1 >> 16;
3150         int y = plane_state->base.src.y1 >> 16;
3151
3152         dspcntr = DISPPLANE_GAMMA_ENABLE;
3153         dspcntr |= DISPLAY_PLANE_ENABLE;
3154
3155         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
3156                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
3157
3158         switch (fb->format->format) {
3159         case DRM_FORMAT_C8:
3160                 dspcntr |= DISPPLANE_8BPP;
3161                 break;
3162         case DRM_FORMAT_RGB565:
3163                 dspcntr |= DISPPLANE_BGRX565;
3164                 break;
3165         case DRM_FORMAT_XRGB8888:
3166                 dspcntr |= DISPPLANE_BGRX888;
3167                 break;
3168         case DRM_FORMAT_XBGR8888:
3169                 dspcntr |= DISPPLANE_RGBX888;
3170                 break;
3171         case DRM_FORMAT_XRGB2101010:
3172                 dspcntr |= DISPPLANE_BGRX101010;
3173                 break;
3174         case DRM_FORMAT_XBGR2101010:
3175                 dspcntr |= DISPPLANE_RGBX101010;
3176                 break;
3177         default:
3178                 BUG();
3179         }
3180
3181         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
3182                 dspcntr |= DISPPLANE_TILED;
3183
3184         if (rotation & DRM_ROTATE_180)
3185                 dspcntr |= DISPPLANE_ROTATE_180;
3186
3187         if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv))
3188                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3189
3190         intel_add_fb_offsets(&x, &y, plane_state, 0);
3191
3192         intel_crtc->dspaddr_offset =
3193                 intel_compute_tile_offset(&x, &y, plane_state, 0);
3194
3195         /* HSW+ does this automagically in hardware */
3196         if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv) &&
3197             rotation & DRM_ROTATE_180) {
3198                 x += crtc_state->pipe_src_w - 1;
3199                 y += crtc_state->pipe_src_h - 1;
3200         }
3201
3202         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3203
3204         intel_crtc->adjusted_x = x;
3205         intel_crtc->adjusted_y = y;
3206
3207         I915_WRITE(reg, dspcntr);
3208
3209         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
3210         I915_WRITE(DSPSURF(plane),
3211                    intel_plane_ggtt_offset(plane_state) +
3212                    intel_crtc->dspaddr_offset);
3213         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3214                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
3215         } else {
3216                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
3217                 I915_WRITE(DSPLINOFF(plane), linear_offset);
3218         }
3219         POSTING_READ(reg);
3220 }
3221
3222 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
3223                               uint64_t fb_modifier, uint32_t pixel_format)
3224 {
3225         if (fb_modifier == DRM_FORMAT_MOD_NONE) {
3226                 return 64;
3227         } else {
3228                 int cpp = drm_format_plane_cpp(pixel_format, 0);
3229
3230                 return intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
3231         }
3232 }
3233
3234 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
3235 {
3236         struct drm_device *dev = intel_crtc->base.dev;
3237         struct drm_i915_private *dev_priv = to_i915(dev);
3238
3239         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
3240         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
3241         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
3242 }
3243
3244 /*
3245  * This function detaches (aka. unbinds) unused scalers in hardware
3246  */
3247 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
3248 {
3249         struct intel_crtc_scaler_state *scaler_state;
3250         int i;
3251
3252         scaler_state = &intel_crtc->config->scaler_state;
3253
3254         /* loop through and disable scalers that aren't in use */
3255         for (i = 0; i < intel_crtc->num_scalers; i++) {
3256                 if (!scaler_state->scalers[i].in_use)
3257                         skl_detach_scaler(intel_crtc, i);
3258         }
3259 }
3260
3261 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
3262                      unsigned int rotation)
3263 {
3264         const struct drm_i915_private *dev_priv = to_i915(fb->dev);
3265         u32 stride = intel_fb_pitch(fb, plane, rotation);
3266
3267         /*
3268          * The stride is either expressed as a multiple of 64 bytes chunks for
3269          * linear buffers or in number of tiles for tiled buffers.
3270          */
3271         if (drm_rotation_90_or_270(rotation)) {
3272                 int cpp = fb->format->cpp[plane];
3273
3274                 stride /= intel_tile_height(dev_priv, fb->modifier, cpp);
3275         } else {
3276                 stride /= intel_fb_stride_alignment(dev_priv, fb->modifier,
3277                                                     fb->format->format);
3278         }
3279
3280         return stride;
3281 }
3282
3283 u32 skl_plane_ctl_format(uint32_t pixel_format)
3284 {
3285         switch (pixel_format) {
3286         case DRM_FORMAT_C8:
3287                 return PLANE_CTL_FORMAT_INDEXED;
3288         case DRM_FORMAT_RGB565:
3289                 return PLANE_CTL_FORMAT_RGB_565;
3290         case DRM_FORMAT_XBGR8888:
3291                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3292         case DRM_FORMAT_XRGB8888:
3293                 return PLANE_CTL_FORMAT_XRGB_8888;
3294         /*
3295          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3296          * to be already pre-multiplied. We need to add a knob (or a different
3297          * DRM_FORMAT) for user-space to configure that.
3298          */
3299         case DRM_FORMAT_ABGR8888:
3300                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3301                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3302         case DRM_FORMAT_ARGB8888:
3303                 return PLANE_CTL_FORMAT_XRGB_8888 |
3304                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3305         case DRM_FORMAT_XRGB2101010:
3306                 return PLANE_CTL_FORMAT_XRGB_2101010;
3307         case DRM_FORMAT_XBGR2101010:
3308                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3309         case DRM_FORMAT_YUYV:
3310                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3311         case DRM_FORMAT_YVYU:
3312                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3313         case DRM_FORMAT_UYVY:
3314                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3315         case DRM_FORMAT_VYUY:
3316                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3317         default:
3318                 MISSING_CASE(pixel_format);
3319         }
3320
3321         return 0;
3322 }
3323
3324 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3325 {
3326         switch (fb_modifier) {
3327         case DRM_FORMAT_MOD_NONE:
3328                 break;
3329         case I915_FORMAT_MOD_X_TILED:
3330                 return PLANE_CTL_TILED_X;
3331         case I915_FORMAT_MOD_Y_TILED:
3332                 return PLANE_CTL_TILED_Y;
3333         case I915_FORMAT_MOD_Yf_TILED:
3334                 return PLANE_CTL_TILED_YF;
3335         default:
3336                 MISSING_CASE(fb_modifier);
3337         }
3338
3339         return 0;
3340 }
3341
3342 u32 skl_plane_ctl_rotation(unsigned int rotation)
3343 {
3344         switch (rotation) {
3345         case DRM_ROTATE_0:
3346                 break;
3347         /*
3348          * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3349          * while i915 HW rotation is clockwise, thats why this swapping.
3350          */
3351         case DRM_ROTATE_90:
3352                 return PLANE_CTL_ROTATE_270;
3353         case DRM_ROTATE_180:
3354                 return PLANE_CTL_ROTATE_180;
3355         case DRM_ROTATE_270:
3356                 return PLANE_CTL_ROTATE_90;
3357         default:
3358                 MISSING_CASE(rotation);
3359         }
3360
3361         return 0;
3362 }
3363
3364 static void skylake_update_primary_plane(struct drm_plane *plane,
3365                                          const struct intel_crtc_state *crtc_state,
3366                                          const struct intel_plane_state *plane_state)
3367 {
3368         struct drm_device *dev = plane->dev;
3369         struct drm_i915_private *dev_priv = to_i915(dev);
3370         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3371         struct drm_framebuffer *fb = plane_state->base.fb;
3372         enum plane_id plane_id = to_intel_plane(plane)->id;
3373         enum pipe pipe = to_intel_plane(plane)->pipe;
3374         u32 plane_ctl;
3375         unsigned int rotation = plane_state->base.rotation;
3376         u32 stride = skl_plane_stride(fb, 0, rotation);
3377         u32 surf_addr = plane_state->main.offset;
3378         int scaler_id = plane_state->scaler_id;
3379         int src_x = plane_state->main.x;
3380         int src_y = plane_state->main.y;
3381         int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3382         int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3383         int dst_x = plane_state->base.dst.x1;
3384         int dst_y = plane_state->base.dst.y1;
3385         int dst_w = drm_rect_width(&plane_state->base.dst);
3386         int dst_h = drm_rect_height(&plane_state->base.dst);
3387
3388         plane_ctl = PLANE_CTL_ENABLE |
3389                     PLANE_CTL_PIPE_GAMMA_ENABLE |
3390                     PLANE_CTL_PIPE_CSC_ENABLE;
3391
3392         plane_ctl |= skl_plane_ctl_format(fb->format->format);
3393         plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
3394         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3395         plane_ctl |= skl_plane_ctl_rotation(rotation);
3396
3397         /* Sizes are 0 based */
3398         src_w--;
3399         src_h--;
3400         dst_w--;
3401         dst_h--;
3402
3403         intel_crtc->dspaddr_offset = surf_addr;
3404
3405         intel_crtc->adjusted_x = src_x;
3406         intel_crtc->adjusted_y = src_y;
3407
3408         I915_WRITE(PLANE_CTL(pipe, plane_id), plane_ctl);
3409         I915_WRITE(PLANE_OFFSET(pipe, plane_id), (src_y << 16) | src_x);
3410         I915_WRITE(PLANE_STRIDE(pipe, plane_id), stride);
3411         I915_WRITE(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
3412
3413         if (scaler_id >= 0) {
3414                 uint32_t ps_ctrl = 0;
3415
3416                 WARN_ON(!dst_w || !dst_h);
3417                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane_id) |
3418                         crtc_state->scaler_state.scalers[scaler_id].mode;
3419                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3420                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3421                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3422                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3423                 I915_WRITE(PLANE_POS(pipe, plane_id), 0);
3424         } else {
3425                 I915_WRITE(PLANE_POS(pipe, plane_id), (dst_y << 16) | dst_x);
3426         }
3427
3428         I915_WRITE(PLANE_SURF(pipe, plane_id),
3429                    intel_plane_ggtt_offset(plane_state) + surf_addr);
3430
3431         POSTING_READ(PLANE_SURF(pipe, plane_id));
3432 }
3433
3434 static void skylake_disable_primary_plane(struct drm_plane *primary,
3435                                           struct drm_crtc *crtc)
3436 {
3437         struct drm_device *dev = crtc->dev;
3438         struct drm_i915_private *dev_priv = to_i915(dev);
3439         enum plane_id plane_id = to_intel_plane(primary)->id;
3440         enum pipe pipe = to_intel_plane(primary)->pipe;
3441
3442         I915_WRITE(PLANE_CTL(pipe, plane_id), 0);
3443         I915_WRITE(PLANE_SURF(pipe, plane_id), 0);
3444         POSTING_READ(PLANE_SURF(pipe, plane_id));
3445 }
3446
3447 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3448 static int
3449 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3450                            int x, int y, enum mode_set_atomic state)
3451 {
3452         /* Support for kgdboc is disabled, this needs a major rework. */
3453         DRM_ERROR("legacy panic handler not supported any more.\n");
3454
3455         return -ENODEV;
3456 }
3457
3458 static void intel_complete_page_flips(struct drm_i915_private *dev_priv)
3459 {
3460         struct intel_crtc *crtc;
3461
3462         for_each_intel_crtc(&dev_priv->drm, crtc)
3463                 intel_finish_page_flip_cs(dev_priv, crtc->pipe);
3464 }
3465
3466 static void intel_update_primary_planes(struct drm_device *dev)
3467 {
3468         struct drm_crtc *crtc;
3469
3470         for_each_crtc(dev, crtc) {
3471                 struct intel_plane *plane = to_intel_plane(crtc->primary);
3472                 struct intel_plane_state *plane_state =
3473                         to_intel_plane_state(plane->base.state);
3474
3475                 if (plane_state->base.visible)
3476                         plane->update_plane(&plane->base,
3477                                             to_intel_crtc_state(crtc->state),
3478                                             plane_state);
3479         }
3480 }
3481
3482 static int
3483 __intel_display_resume(struct drm_device *dev,
3484                        struct drm_atomic_state *state)
3485 {
3486         struct drm_crtc_state *crtc_state;
3487         struct drm_crtc *crtc;
3488         int i, ret;
3489
3490         intel_modeset_setup_hw_state(dev);
3491         i915_redisable_vga(to_i915(dev));
3492
3493         if (!state)
3494                 return 0;
3495
3496         for_each_crtc_in_state(state, crtc, crtc_state, i) {
3497                 /*
3498                  * Force recalculation even if we restore
3499                  * current state. With fast modeset this may not result
3500                  * in a modeset when the state is compatible.
3501                  */
3502                 crtc_state->mode_changed = true;
3503         }
3504
3505         /* ignore any reset values/BIOS leftovers in the WM registers */
3506         to_intel_atomic_state(state)->skip_intermediate_wm = true;
3507
3508         ret = drm_atomic_commit(state);
3509
3510         WARN_ON(ret == -EDEADLK);
3511         return ret;
3512 }
3513
3514 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
3515 {
3516         return intel_has_gpu_reset(dev_priv) &&
3517                 INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv);
3518 }
3519
3520 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3521 {
3522         struct drm_device *dev = &dev_priv->drm;
3523         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3524         struct drm_atomic_state *state;
3525         int ret;
3526
3527         /*
3528          * Need mode_config.mutex so that we don't
3529          * trample ongoing ->detect() and whatnot.
3530          */
3531         mutex_lock(&dev->mode_config.mutex);
3532         drm_modeset_acquire_init(ctx, 0);
3533         while (1) {
3534                 ret = drm_modeset_lock_all_ctx(dev, ctx);
3535                 if (ret != -EDEADLK)
3536                         break;
3537
3538                 drm_modeset_backoff(ctx);
3539         }
3540
3541         /* reset doesn't touch the display, but flips might get nuked anyway, */
3542         if (!i915.force_reset_modeset_test &&
3543             !gpu_reset_clobbers_display(dev_priv))
3544                 return;
3545
3546         /*
3547          * Disabling the crtcs gracefully seems nicer. Also the
3548          * g33 docs say we should at least disable all the planes.
3549          */
3550         state = drm_atomic_helper_duplicate_state(dev, ctx);
3551         if (IS_ERR(state)) {
3552                 ret = PTR_ERR(state);
3553                 DRM_ERROR("Duplicating state failed with %i\n", ret);
3554                 return;
3555         }
3556
3557         ret = drm_atomic_helper_disable_all(dev, ctx);
3558         if (ret) {
3559                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
3560                 drm_atomic_state_put(state);
3561                 return;
3562         }
3563
3564         dev_priv->modeset_restore_state = state;
3565         state->acquire_ctx = ctx;
3566 }
3567
3568 void intel_finish_reset(struct drm_i915_private *dev_priv)
3569 {
3570         struct drm_device *dev = &dev_priv->drm;
3571         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3572         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
3573         int ret;
3574
3575         /*
3576          * Flips in the rings will be nuked by the reset,
3577          * so complete all pending flips so that user space
3578          * will get its events and not get stuck.
3579          */
3580         intel_complete_page_flips(dev_priv);
3581
3582         dev_priv->modeset_restore_state = NULL;
3583
3584         /* reset doesn't touch the display */
3585         if (!gpu_reset_clobbers_display(dev_priv)) {
3586                 if (!state) {
3587                         /*
3588                          * Flips in the rings have been nuked by the reset,
3589                          * so update the base address of all primary
3590                          * planes to the the last fb to make sure we're
3591                          * showing the correct fb after a reset.
3592                          *
3593                          * FIXME: Atomic will make this obsolete since we won't schedule
3594                          * CS-based flips (which might get lost in gpu resets) any more.
3595                          */
3596                         intel_update_primary_planes(dev);
3597                 } else {
3598                         ret = __intel_display_resume(dev, state);
3599                         if (ret)
3600                                 DRM_ERROR("Restoring old state failed with %i\n", ret);
3601                 }
3602         } else {
3603                 /*
3604                  * The display has been reset as well,
3605                  * so need a full re-initialization.
3606                  */
3607                 intel_runtime_pm_disable_interrupts(dev_priv);
3608                 intel_runtime_pm_enable_interrupts(dev_priv);
3609
3610                 intel_pps_unlock_regs_wa(dev_priv);
3611                 intel_modeset_init_hw(dev);
3612
3613                 spin_lock_irq(&dev_priv->irq_lock);
3614                 if (dev_priv->display.hpd_irq_setup)
3615                         dev_priv->display.hpd_irq_setup(dev_priv);
3616                 spin_unlock_irq(&dev_priv->irq_lock);
3617
3618                 ret = __intel_display_resume(dev, state);
3619                 if (ret)
3620                         DRM_ERROR("Restoring old state failed with %i\n", ret);
3621
3622                 intel_hpd_init(dev_priv);
3623         }
3624
3625         if (state)
3626                 drm_atomic_state_put(state);
3627         drm_modeset_drop_locks(ctx);
3628         drm_modeset_acquire_fini(ctx);
3629         mutex_unlock(&dev->mode_config.mutex);
3630 }
3631
3632 static bool abort_flip_on_reset(struct intel_crtc *crtc)
3633 {
3634         struct i915_gpu_error *error = &to_i915(crtc->base.dev)->gpu_error;
3635
3636         if (i915_reset_in_progress(error))
3637                 return true;
3638
3639         if (crtc->reset_count != i915_reset_count(error))
3640                 return true;
3641
3642         return false;
3643 }
3644
3645 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3646 {
3647         struct drm_device *dev = crtc->dev;
3648         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3649         bool pending;
3650
3651         if (abort_flip_on_reset(intel_crtc))
3652                 return false;
3653
3654         spin_lock_irq(&dev->event_lock);
3655         pending = to_intel_crtc(crtc)->flip_work != NULL;
3656         spin_unlock_irq(&dev->event_lock);
3657
3658         return pending;
3659 }
3660
3661 static void intel_update_pipe_config(struct intel_crtc *crtc,
3662                                      struct intel_crtc_state *old_crtc_state)
3663 {
3664         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3665         struct intel_crtc_state *pipe_config =
3666                 to_intel_crtc_state(crtc->base.state);
3667
3668         /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3669         crtc->base.mode = crtc->base.state->mode;
3670
3671         DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3672                       old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3673                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3674
3675         /*
3676          * Update pipe size and adjust fitter if needed: the reason for this is
3677          * that in compute_mode_changes we check the native mode (not the pfit
3678          * mode) to see if we can flip rather than do a full mode set. In the
3679          * fastboot case, we'll flip, but if we don't update the pipesrc and
3680          * pfit state, we'll end up with a big fb scanned out into the wrong
3681          * sized surface.
3682          */
3683
3684         I915_WRITE(PIPESRC(crtc->pipe),
3685                    ((pipe_config->pipe_src_w - 1) << 16) |
3686                    (pipe_config->pipe_src_h - 1));
3687
3688         /* on skylake this is done by detaching scalers */
3689         if (INTEL_GEN(dev_priv) >= 9) {
3690                 skl_detach_scalers(crtc);
3691
3692                 if (pipe_config->pch_pfit.enabled)
3693                         skylake_pfit_enable(crtc);
3694         } else if (HAS_PCH_SPLIT(dev_priv)) {
3695                 if (pipe_config->pch_pfit.enabled)
3696                         ironlake_pfit_enable(crtc);
3697                 else if (old_crtc_state->pch_pfit.enabled)
3698                         ironlake_pfit_disable(crtc, true);
3699         }
3700 }
3701
3702 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3703 {
3704         struct drm_device *dev = crtc->dev;
3705         struct drm_i915_private *dev_priv = to_i915(dev);
3706         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3707         int pipe = intel_crtc->pipe;
3708         i915_reg_t reg;
3709         u32 temp;
3710
3711         /* enable normal train */
3712         reg = FDI_TX_CTL(pipe);
3713         temp = I915_READ(reg);
3714         if (IS_IVYBRIDGE(dev_priv)) {
3715                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3716                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3717         } else {
3718                 temp &= ~FDI_LINK_TRAIN_NONE;
3719                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3720         }
3721         I915_WRITE(reg, temp);
3722
3723         reg = FDI_RX_CTL(pipe);
3724         temp = I915_READ(reg);
3725         if (HAS_PCH_CPT(dev_priv)) {
3726                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3727                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3728         } else {
3729                 temp &= ~FDI_LINK_TRAIN_NONE;
3730                 temp |= FDI_LINK_TRAIN_NONE;
3731         }
3732         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3733
3734         /* wait one idle pattern time */
3735         POSTING_READ(reg);
3736         udelay(1000);
3737
3738         /* IVB wants error correction enabled */
3739         if (IS_IVYBRIDGE(dev_priv))
3740                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3741                            FDI_FE_ERRC_ENABLE);
3742 }
3743
3744 /* The FDI link training functions for ILK/Ibexpeak. */
3745 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3746 {
3747         struct drm_device *dev = crtc->dev;
3748         struct drm_i915_private *dev_priv = to_i915(dev);
3749         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3750         int pipe = intel_crtc->pipe;
3751         i915_reg_t reg;
3752         u32 temp, tries;
3753
3754         /* FDI needs bits from pipe first */
3755         assert_pipe_enabled(dev_priv, pipe);
3756
3757         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3758            for train result */
3759         reg = FDI_RX_IMR(pipe);
3760         temp = I915_READ(reg);
3761         temp &= ~FDI_RX_SYMBOL_LOCK;
3762         temp &= ~FDI_RX_BIT_LOCK;
3763         I915_WRITE(reg, temp);
3764         I915_READ(reg);
3765         udelay(150);
3766
3767         /* enable CPU FDI TX and PCH FDI RX */
3768         reg = FDI_TX_CTL(pipe);
3769         temp = I915_READ(reg);
3770         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3771         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3772         temp &= ~FDI_LINK_TRAIN_NONE;
3773         temp |= FDI_LINK_TRAIN_PATTERN_1;
3774         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3775
3776         reg = FDI_RX_CTL(pipe);
3777         temp = I915_READ(reg);
3778         temp &= ~FDI_LINK_TRAIN_NONE;
3779         temp |= FDI_LINK_TRAIN_PATTERN_1;
3780         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3781
3782         POSTING_READ(reg);
3783         udelay(150);
3784
3785         /* Ironlake workaround, enable clock pointer after FDI enable*/
3786         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3787         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3788                    FDI_RX_PHASE_SYNC_POINTER_EN);
3789
3790         reg = FDI_RX_IIR(pipe);
3791         for (tries = 0; tries < 5; tries++) {
3792                 temp = I915_READ(reg);
3793                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3794
3795                 if ((temp & FDI_RX_BIT_LOCK)) {
3796                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3797                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3798                         break;
3799                 }
3800         }
3801         if (tries == 5)
3802                 DRM_ERROR("FDI train 1 fail!\n");
3803
3804         /* Train 2 */
3805         reg = FDI_TX_CTL(pipe);
3806         temp = I915_READ(reg);
3807         temp &= ~FDI_LINK_TRAIN_NONE;
3808         temp |= FDI_LINK_TRAIN_PATTERN_2;
3809         I915_WRITE(reg, temp);
3810
3811         reg = FDI_RX_CTL(pipe);
3812         temp = I915_READ(reg);
3813         temp &= ~FDI_LINK_TRAIN_NONE;
3814         temp |= FDI_LINK_TRAIN_PATTERN_2;
3815         I915_WRITE(reg, temp);
3816
3817         POSTING_READ(reg);
3818         udelay(150);
3819
3820         reg = FDI_RX_IIR(pipe);
3821         for (tries = 0; tries < 5; tries++) {
3822                 temp = I915_READ(reg);
3823                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3824
3825                 if (temp & FDI_RX_SYMBOL_LOCK) {
3826                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3827                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3828                         break;
3829                 }
3830         }
3831         if (tries == 5)
3832                 DRM_ERROR("FDI train 2 fail!\n");
3833
3834         DRM_DEBUG_KMS("FDI train done\n");
3835
3836 }
3837
3838 static const int snb_b_fdi_train_param[] = {
3839         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3840         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3841         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3842         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3843 };
3844
3845 /* The FDI link training functions for SNB/Cougarpoint. */
3846 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3847 {
3848         struct drm_device *dev = crtc->dev;
3849         struct drm_i915_private *dev_priv = to_i915(dev);
3850         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3851         int pipe = intel_crtc->pipe;
3852         i915_reg_t reg;
3853         u32 temp, i, retry;
3854
3855         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3856            for train result */
3857         reg = FDI_RX_IMR(pipe);
3858         temp = I915_READ(reg);
3859         temp &= ~FDI_RX_SYMBOL_LOCK;
3860         temp &= ~FDI_RX_BIT_LOCK;
3861         I915_WRITE(reg, temp);
3862
3863         POSTING_READ(reg);
3864         udelay(150);
3865
3866         /* enable CPU FDI TX and PCH FDI RX */
3867         reg = FDI_TX_CTL(pipe);
3868         temp = I915_READ(reg);
3869         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3870         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3871         temp &= ~FDI_LINK_TRAIN_NONE;
3872         temp |= FDI_LINK_TRAIN_PATTERN_1;
3873         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3874         /* SNB-B */
3875         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3876         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3877
3878         I915_WRITE(FDI_RX_MISC(pipe),
3879                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3880
3881         reg = FDI_RX_CTL(pipe);
3882         temp = I915_READ(reg);
3883         if (HAS_PCH_CPT(dev_priv)) {
3884                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3885                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3886         } else {
3887                 temp &= ~FDI_LINK_TRAIN_NONE;
3888                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3889         }
3890         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3891
3892         POSTING_READ(reg);
3893         udelay(150);
3894
3895         for (i = 0; i < 4; i++) {
3896                 reg = FDI_TX_CTL(pipe);
3897                 temp = I915_READ(reg);
3898                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3899                 temp |= snb_b_fdi_train_param[i];
3900                 I915_WRITE(reg, temp);
3901
3902                 POSTING_READ(reg);
3903                 udelay(500);
3904
3905                 for (retry = 0; retry < 5; retry++) {
3906                         reg = FDI_RX_IIR(pipe);
3907                         temp = I915_READ(reg);
3908                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3909                         if (temp & FDI_RX_BIT_LOCK) {
3910                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3911                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3912                                 break;
3913                         }
3914                         udelay(50);
3915                 }
3916                 if (retry < 5)
3917                         break;
3918         }
3919         if (i == 4)
3920                 DRM_ERROR("FDI train 1 fail!\n");
3921
3922         /* Train 2 */
3923         reg = FDI_TX_CTL(pipe);
3924         temp = I915_READ(reg);
3925         temp &= ~FDI_LINK_TRAIN_NONE;
3926         temp |= FDI_LINK_TRAIN_PATTERN_2;
3927         if (IS_GEN6(dev_priv)) {
3928                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3929                 /* SNB-B */
3930                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3931         }
3932         I915_WRITE(reg, temp);
3933
3934         reg = FDI_RX_CTL(pipe);
3935         temp = I915_READ(reg);
3936         if (HAS_PCH_CPT(dev_priv)) {
3937                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3938                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3939         } else {
3940                 temp &= ~FDI_LINK_TRAIN_NONE;
3941                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3942         }
3943         I915_WRITE(reg, temp);
3944
3945         POSTING_READ(reg);
3946         udelay(150);
3947
3948         for (i = 0; i < 4; i++) {
3949                 reg = FDI_TX_CTL(pipe);
3950                 temp = I915_READ(reg);
3951                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3952                 temp |= snb_b_fdi_train_param[i];
3953                 I915_WRITE(reg, temp);
3954
3955                 POSTING_READ(reg);
3956                 udelay(500);
3957
3958                 for (retry = 0; retry < 5; retry++) {
3959                         reg = FDI_RX_IIR(pipe);
3960                         temp = I915_READ(reg);
3961                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3962                         if (temp & FDI_RX_SYMBOL_LOCK) {
3963                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3964                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3965                                 break;
3966                         }
3967                         udelay(50);
3968                 }
3969                 if (retry < 5)
3970                         break;
3971         }
3972         if (i == 4)
3973                 DRM_ERROR("FDI train 2 fail!\n");
3974
3975         DRM_DEBUG_KMS("FDI train done.\n");
3976 }
3977
3978 /* Manual link training for Ivy Bridge A0 parts */
3979 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3980 {
3981         struct drm_device *dev = crtc->dev;
3982         struct drm_i915_private *dev_priv = to_i915(dev);
3983         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3984         int pipe = intel_crtc->pipe;
3985         i915_reg_t reg;
3986         u32 temp, i, j;
3987
3988         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3989            for train result */
3990         reg = FDI_RX_IMR(pipe);
3991         temp = I915_READ(reg);
3992         temp &= ~FDI_RX_SYMBOL_LOCK;
3993         temp &= ~FDI_RX_BIT_LOCK;
3994         I915_WRITE(reg, temp);
3995
3996         POSTING_READ(reg);
3997         udelay(150);
3998
3999         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
4000                       I915_READ(FDI_RX_IIR(pipe)));
4001
4002         /* Try each vswing and preemphasis setting twice before moving on */
4003         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
4004                 /* disable first in case we need to retry */
4005                 reg = FDI_TX_CTL(pipe);
4006                 temp = I915_READ(reg);
4007                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
4008                 temp &= ~FDI_TX_ENABLE;
4009                 I915_WRITE(reg, temp);
4010
4011                 reg = FDI_RX_CTL(pipe);
4012                 temp = I915_READ(reg);
4013                 temp &= ~FDI_LINK_TRAIN_AUTO;
4014                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4015                 temp &= ~FDI_RX_ENABLE;
4016                 I915_WRITE(reg, temp);
4017
4018                 /* enable CPU FDI TX and PCH FDI RX */
4019                 reg = FDI_TX_CTL(pipe);
4020                 temp = I915_READ(reg);
4021                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
4022                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4023                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
4024                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4025                 temp |= snb_b_fdi_train_param[j/2];
4026                 temp |= FDI_COMPOSITE_SYNC;
4027                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4028
4029                 I915_WRITE(FDI_RX_MISC(pipe),
4030                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4031
4032                 reg = FDI_RX_CTL(pipe);
4033                 temp = I915_READ(reg);
4034                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4035                 temp |= FDI_COMPOSITE_SYNC;
4036                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4037
4038                 POSTING_READ(reg);
4039                 udelay(1); /* should be 0.5us */
4040
4041                 for (i = 0; i < 4; i++) {
4042                         reg = FDI_RX_IIR(pipe);
4043                         temp = I915_READ(reg);
4044                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4045
4046                         if (temp & FDI_RX_BIT_LOCK ||
4047                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
4048                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4049                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4050                                               i);
4051                                 break;
4052                         }
4053                         udelay(1); /* should be 0.5us */
4054                 }
4055                 if (i == 4) {
4056                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
4057                         continue;
4058                 }
4059
4060                 /* Train 2 */
4061                 reg = FDI_TX_CTL(pipe);
4062                 temp = I915_READ(reg);
4063                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4064                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
4065                 I915_WRITE(reg, temp);
4066
4067                 reg = FDI_RX_CTL(pipe);
4068                 temp = I915_READ(reg);
4069                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4070                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4071                 I915_WRITE(reg, temp);
4072
4073                 POSTING_READ(reg);
4074                 udelay(2); /* should be 1.5us */
4075
4076                 for (i = 0; i < 4; i++) {
4077                         reg = FDI_RX_IIR(pipe);
4078                         temp = I915_READ(reg);
4079                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4080
4081                         if (temp & FDI_RX_SYMBOL_LOCK ||
4082                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
4083                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4084                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4085                                               i);
4086                                 goto train_done;
4087                         }
4088                         udelay(2); /* should be 1.5us */
4089                 }
4090                 if (i == 4)
4091                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
4092         }
4093
4094 train_done:
4095         DRM_DEBUG_KMS("FDI train done.\n");
4096 }
4097
4098 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
4099 {
4100         struct drm_device *dev = intel_crtc->base.dev;
4101         struct drm_i915_private *dev_priv = to_i915(dev);
4102         int pipe = intel_crtc->pipe;
4103         i915_reg_t reg;
4104         u32 temp;
4105
4106         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
4107         reg = FDI_RX_CTL(pipe);
4108         temp = I915_READ(reg);
4109         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
4110         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4111         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4112         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4113
4114         POSTING_READ(reg);
4115         udelay(200);
4116
4117         /* Switch from Rawclk to PCDclk */
4118         temp = I915_READ(reg);
4119         I915_WRITE(reg, temp | FDI_PCDCLK);
4120
4121         POSTING_READ(reg);
4122         udelay(200);
4123
4124         /* Enable CPU FDI TX PLL, always on for Ironlake */
4125         reg = FDI_TX_CTL(pipe);
4126         temp = I915_READ(reg);
4127         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
4128                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
4129
4130                 POSTING_READ(reg);
4131                 udelay(100);
4132         }
4133 }
4134
4135 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
4136 {
4137         struct drm_device *dev = intel_crtc->base.dev;
4138         struct drm_i915_private *dev_priv = to_i915(dev);
4139         int pipe = intel_crtc->pipe;
4140         i915_reg_t reg;
4141         u32 temp;
4142
4143         /* Switch from PCDclk to Rawclk */
4144         reg = FDI_RX_CTL(pipe);
4145         temp = I915_READ(reg);
4146         I915_WRITE(reg, temp & ~FDI_PCDCLK);
4147
4148         /* Disable CPU FDI TX PLL */
4149         reg = FDI_TX_CTL(pipe);
4150         temp = I915_READ(reg);
4151         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
4152
4153         POSTING_READ(reg);
4154         udelay(100);
4155
4156         reg = FDI_RX_CTL(pipe);
4157         temp = I915_READ(reg);
4158         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
4159
4160         /* Wait for the clocks to turn off. */
4161         POSTING_READ(reg);
4162         udelay(100);
4163 }
4164
4165 static void ironlake_fdi_disable(struct drm_crtc *crtc)
4166 {
4167         struct drm_device *dev = crtc->dev;
4168         struct drm_i915_private *dev_priv = to_i915(dev);
4169         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4170         int pipe = intel_crtc->pipe;
4171         i915_reg_t reg;
4172         u32 temp;
4173
4174         /* disable CPU FDI tx and PCH FDI rx */
4175         reg = FDI_TX_CTL(pipe);
4176         temp = I915_READ(reg);
4177         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
4178         POSTING_READ(reg);
4179
4180         reg = FDI_RX_CTL(pipe);
4181         temp = I915_READ(reg);
4182         temp &= ~(0x7 << 16);
4183         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4184         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
4185
4186         POSTING_READ(reg);
4187         udelay(100);
4188
4189         /* Ironlake workaround, disable clock pointer after downing FDI */
4190         if (HAS_PCH_IBX(dev_priv))
4191                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4192
4193         /* still set train pattern 1 */
4194         reg = FDI_TX_CTL(pipe);
4195         temp = I915_READ(reg);
4196         temp &= ~FDI_LINK_TRAIN_NONE;
4197         temp |= FDI_LINK_TRAIN_PATTERN_1;
4198         I915_WRITE(reg, temp);
4199
4200         reg = FDI_RX_CTL(pipe);
4201         temp = I915_READ(reg);
4202         if (HAS_PCH_CPT(dev_priv)) {
4203                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4204                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4205         } else {
4206                 temp &= ~FDI_LINK_TRAIN_NONE;
4207                 temp |= FDI_LINK_TRAIN_PATTERN_1;
4208         }
4209         /* BPC in FDI rx is consistent with that in PIPECONF */
4210         temp &= ~(0x07 << 16);
4211         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4212         I915_WRITE(reg, temp);
4213
4214         POSTING_READ(reg);
4215         udelay(100);
4216 }
4217
4218 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
4219 {
4220         struct intel_crtc *crtc;
4221
4222         /* Note that we don't need to be called with mode_config.lock here
4223          * as our list of CRTC objects is static for the lifetime of the
4224          * device and so cannot disappear as we iterate. Similarly, we can
4225          * happily treat the predicates as racy, atomic checks as userspace
4226          * cannot claim and pin a new fb without at least acquring the
4227          * struct_mutex and so serialising with us.
4228          */
4229         for_each_intel_crtc(&dev_priv->drm, crtc) {
4230                 if (atomic_read(&crtc->unpin_work_count) == 0)
4231                         continue;
4232
4233                 if (crtc->flip_work)
4234                         intel_wait_for_vblank(dev_priv, crtc->pipe);
4235
4236                 return true;
4237         }
4238
4239         return false;
4240 }
4241
4242 static void page_flip_completed(struct intel_crtc *intel_crtc)
4243 {
4244         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4245         struct intel_flip_work *work = intel_crtc->flip_work;
4246
4247         intel_crtc->flip_work = NULL;
4248
4249         if (work->event)
4250                 drm_crtc_send_vblank_event(&intel_crtc->base, work->event);
4251
4252         drm_crtc_vblank_put(&intel_crtc->base);
4253
4254         wake_up_all(&dev_priv->pending_flip_queue);
4255         queue_work(dev_priv->wq, &work->unpin_work);
4256
4257         trace_i915_flip_complete(intel_crtc->plane,
4258                                  work->pending_flip_obj);
4259 }
4260
4261 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
4262 {
4263         struct drm_device *dev = crtc->dev;
4264         struct drm_i915_private *dev_priv = to_i915(dev);
4265         long ret;
4266
4267         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
4268
4269         ret = wait_event_interruptible_timeout(
4270                                         dev_priv->pending_flip_queue,
4271                                         !intel_crtc_has_pending_flip(crtc),
4272                                         60*HZ);
4273
4274         if (ret < 0)
4275                 return ret;
4276
4277         if (ret == 0) {
4278                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4279                 struct intel_flip_work *work;
4280
4281                 spin_lock_irq(&dev->event_lock);
4282                 work = intel_crtc->flip_work;
4283                 if (work && !is_mmio_work(work)) {
4284                         WARN_ONCE(1, "Removing stuck page flip\n");
4285                         page_flip_completed(intel_crtc);
4286                 }
4287                 spin_unlock_irq(&dev->event_lock);
4288         }
4289
4290         return 0;
4291 }
4292
4293 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
4294 {
4295         u32 temp;
4296
4297         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
4298
4299         mutex_lock(&dev_priv->sb_lock);
4300
4301         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4302         temp |= SBI_SSCCTL_DISABLE;
4303         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4304
4305         mutex_unlock(&dev_priv->sb_lock);
4306 }
4307
4308 /* Program iCLKIP clock to the desired frequency */
4309 static void lpt_program_iclkip(struct drm_crtc *crtc)
4310 {
4311         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
4312         int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
4313         u32 divsel, phaseinc, auxdiv, phasedir = 0;
4314         u32 temp;
4315
4316         lpt_disable_iclkip(dev_priv);
4317
4318         /* The iCLK virtual clock root frequency is in MHz,
4319          * but the adjusted_mode->crtc_clock in in KHz. To get the
4320          * divisors, it is necessary to divide one by another, so we
4321          * convert the virtual clock precision to KHz here for higher
4322          * precision.
4323          */
4324         for (auxdiv = 0; auxdiv < 2; auxdiv++) {
4325                 u32 iclk_virtual_root_freq = 172800 * 1000;
4326                 u32 iclk_pi_range = 64;
4327                 u32 desired_divisor;
4328
4329                 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4330                                                     clock << auxdiv);
4331                 divsel = (desired_divisor / iclk_pi_range) - 2;
4332                 phaseinc = desired_divisor % iclk_pi_range;
4333
4334                 /*
4335                  * Near 20MHz is a corner case which is
4336                  * out of range for the 7-bit divisor
4337                  */
4338                 if (divsel <= 0x7f)
4339                         break;
4340         }
4341
4342         /* This should not happen with any sane values */
4343         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4344                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4345         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4346                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4347
4348         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4349                         clock,
4350                         auxdiv,
4351                         divsel,
4352                         phasedir,
4353                         phaseinc);
4354
4355         mutex_lock(&dev_priv->sb_lock);
4356
4357         /* Program SSCDIVINTPHASE6 */
4358         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4359         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4360         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4361         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4362         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4363         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4364         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4365         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4366
4367         /* Program SSCAUXDIV */
4368         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4369         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4370         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4371         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4372
4373         /* Enable modulator and associated divider */
4374         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4375         temp &= ~SBI_SSCCTL_DISABLE;
4376         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4377
4378         mutex_unlock(&dev_priv->sb_lock);
4379
4380         /* Wait for initialization time */
4381         udelay(24);
4382
4383         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4384 }
4385
4386 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
4387 {
4388         u32 divsel, phaseinc, auxdiv;
4389         u32 iclk_virtual_root_freq = 172800 * 1000;
4390         u32 iclk_pi_range = 64;
4391         u32 desired_divisor;
4392         u32 temp;
4393
4394         if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
4395                 return 0;
4396
4397         mutex_lock(&dev_priv->sb_lock);
4398
4399         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4400         if (temp & SBI_SSCCTL_DISABLE) {
4401                 mutex_unlock(&dev_priv->sb_lock);
4402                 return 0;
4403         }
4404
4405         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4406         divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
4407                 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
4408         phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
4409                 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
4410
4411         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4412         auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4413                 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4414
4415         mutex_unlock(&dev_priv->sb_lock);
4416
4417         desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4418
4419         return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4420                                  desired_divisor << auxdiv);
4421 }
4422
4423 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4424                                                 enum pipe pch_transcoder)
4425 {
4426         struct drm_device *dev = crtc->base.dev;
4427         struct drm_i915_private *dev_priv = to_i915(dev);
4428         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4429
4430         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4431                    I915_READ(HTOTAL(cpu_transcoder)));
4432         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4433                    I915_READ(HBLANK(cpu_transcoder)));
4434         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4435                    I915_READ(HSYNC(cpu_transcoder)));
4436
4437         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4438                    I915_READ(VTOTAL(cpu_transcoder)));
4439         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4440                    I915_READ(VBLANK(cpu_transcoder)));
4441         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4442                    I915_READ(VSYNC(cpu_transcoder)));
4443         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4444                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
4445 }
4446
4447 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4448 {
4449         struct drm_i915_private *dev_priv = to_i915(dev);
4450         uint32_t temp;
4451
4452         temp = I915_READ(SOUTH_CHICKEN1);
4453         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4454                 return;
4455
4456         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4457         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4458
4459         temp &= ~FDI_BC_BIFURCATION_SELECT;
4460         if (enable)
4461                 temp |= FDI_BC_BIFURCATION_SELECT;
4462
4463         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4464         I915_WRITE(SOUTH_CHICKEN1, temp);
4465         POSTING_READ(SOUTH_CHICKEN1);
4466 }
4467
4468 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4469 {
4470         struct drm_device *dev = intel_crtc->base.dev;
4471
4472         switch (intel_crtc->pipe) {
4473         case PIPE_A:
4474                 break;
4475         case PIPE_B:
4476                 if (intel_crtc->config->fdi_lanes > 2)
4477                         cpt_set_fdi_bc_bifurcation(dev, false);
4478                 else
4479                         cpt_set_fdi_bc_bifurcation(dev, true);
4480
4481                 break;
4482         case PIPE_C:
4483                 cpt_set_fdi_bc_bifurcation(dev, true);
4484
4485                 break;
4486         default:
4487                 BUG();
4488         }
4489 }
4490
4491 /* Return which DP Port should be selected for Transcoder DP control */
4492 static enum port
4493 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4494 {
4495         struct drm_device *dev = crtc->dev;
4496         struct intel_encoder *encoder;
4497
4498         for_each_encoder_on_crtc(dev, crtc, encoder) {
4499                 if (encoder->type == INTEL_OUTPUT_DP ||
4500                     encoder->type == INTEL_OUTPUT_EDP)
4501                         return enc_to_dig_port(&encoder->base)->port;
4502         }
4503
4504         return -1;
4505 }
4506
4507 /*
4508  * Enable PCH resources required for PCH ports:
4509  *   - PCH PLLs
4510  *   - FDI training & RX/TX
4511  *   - update transcoder timings
4512  *   - DP transcoding bits
4513  *   - transcoder
4514  */
4515 static void ironlake_pch_enable(struct drm_crtc *crtc)
4516 {
4517         struct drm_device *dev = crtc->dev;
4518         struct drm_i915_private *dev_priv = to_i915(dev);
4519         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4520         int pipe = intel_crtc->pipe;
4521         u32 temp;
4522
4523         assert_pch_transcoder_disabled(dev_priv, pipe);
4524
4525         if (IS_IVYBRIDGE(dev_priv))
4526                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4527
4528         /* Write the TU size bits before fdi link training, so that error
4529          * detection works. */
4530         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4531                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4532
4533         /* For PCH output, training FDI link */
4534         dev_priv->display.fdi_link_train(crtc);
4535
4536         /* We need to program the right clock selection before writing the pixel
4537          * mutliplier into the DPLL. */
4538         if (HAS_PCH_CPT(dev_priv)) {
4539                 u32 sel;
4540
4541                 temp = I915_READ(PCH_DPLL_SEL);
4542                 temp |= TRANS_DPLL_ENABLE(pipe);
4543                 sel = TRANS_DPLLB_SEL(pipe);
4544                 if (intel_crtc->config->shared_dpll ==
4545                     intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4546                         temp |= sel;
4547                 else
4548                         temp &= ~sel;
4549                 I915_WRITE(PCH_DPLL_SEL, temp);
4550         }
4551
4552         /* XXX: pch pll's can be enabled any time before we enable the PCH
4553          * transcoder, and we actually should do this to not upset any PCH
4554          * transcoder that already use the clock when we share it.
4555          *
4556          * Note that enable_shared_dpll tries to do the right thing, but
4557          * get_shared_dpll unconditionally resets the pll - we need that to have
4558          * the right LVDS enable sequence. */
4559         intel_enable_shared_dpll(intel_crtc);
4560
4561         /* set transcoder timing, panel must allow it */
4562         assert_panel_unlocked(dev_priv, pipe);
4563         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4564
4565         intel_fdi_normal_train(crtc);
4566
4567         /* For PCH DP, enable TRANS_DP_CTL */
4568         if (HAS_PCH_CPT(dev_priv) &&
4569             intel_crtc_has_dp_encoder(intel_crtc->config)) {
4570                 const struct drm_display_mode *adjusted_mode =
4571                         &intel_crtc->config->base.adjusted_mode;
4572                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4573                 i915_reg_t reg = TRANS_DP_CTL(pipe);
4574                 temp = I915_READ(reg);
4575                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4576                           TRANS_DP_SYNC_MASK |
4577                           TRANS_DP_BPC_MASK);
4578                 temp |= TRANS_DP_OUTPUT_ENABLE;
4579                 temp |= bpc << 9; /* same format but at 11:9 */
4580
4581                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4582                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4583                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4584                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4585
4586                 switch (intel_trans_dp_port_sel(crtc)) {
4587                 case PORT_B:
4588                         temp |= TRANS_DP_PORT_SEL_B;
4589                         break;
4590                 case PORT_C:
4591                         temp |= TRANS_DP_PORT_SEL_C;
4592                         break;
4593                 case PORT_D:
4594                         temp |= TRANS_DP_PORT_SEL_D;
4595                         break;
4596                 default:
4597                         BUG();
4598                 }
4599
4600                 I915_WRITE(reg, temp);
4601         }
4602
4603         ironlake_enable_pch_transcoder(dev_priv, pipe);
4604 }
4605
4606 static void lpt_pch_enable(struct drm_crtc *crtc)
4607 {
4608         struct drm_device *dev = crtc->dev;
4609         struct drm_i915_private *dev_priv = to_i915(dev);
4610         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4611         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4612
4613         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4614
4615         lpt_program_iclkip(crtc);
4616
4617         /* Set transcoder timing. */
4618         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4619
4620         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4621 }
4622
4623 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4624 {
4625         struct drm_i915_private *dev_priv = to_i915(dev);
4626         i915_reg_t dslreg = PIPEDSL(pipe);
4627         u32 temp;
4628
4629         temp = I915_READ(dslreg);
4630         udelay(500);
4631         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4632                 if (wait_for(I915_READ(dslreg) != temp, 5))
4633                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4634         }
4635 }
4636
4637 static int
4638 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4639                   unsigned scaler_user, int *scaler_id, unsigned int rotation,
4640                   int src_w, int src_h, int dst_w, int dst_h)
4641 {
4642         struct intel_crtc_scaler_state *scaler_state =
4643                 &crtc_state->scaler_state;
4644         struct intel_crtc *intel_crtc =
4645                 to_intel_crtc(crtc_state->base.crtc);
4646         int need_scaling;
4647
4648         need_scaling = drm_rotation_90_or_270(rotation) ?
4649                 (src_h != dst_w || src_w != dst_h):
4650                 (src_w != dst_w || src_h != dst_h);
4651
4652         /*
4653          * if plane is being disabled or scaler is no more required or force detach
4654          *  - free scaler binded to this plane/crtc
4655          *  - in order to do this, update crtc->scaler_usage
4656          *
4657          * Here scaler state in crtc_state is set free so that
4658          * scaler can be assigned to other user. Actual register
4659          * update to free the scaler is done in plane/panel-fit programming.
4660          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4661          */
4662         if (force_detach || !need_scaling) {
4663                 if (*scaler_id >= 0) {
4664                         scaler_state->scaler_users &= ~(1 << scaler_user);
4665                         scaler_state->scalers[*scaler_id].in_use = 0;
4666
4667                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4668                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4669                                 intel_crtc->pipe, scaler_user, *scaler_id,
4670                                 scaler_state->scaler_users);
4671                         *scaler_id = -1;
4672                 }
4673                 return 0;
4674         }
4675
4676         /* range checks */
4677         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4678                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4679
4680                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4681                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4682                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4683                         "size is out of scaler range\n",
4684                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4685                 return -EINVAL;
4686         }
4687
4688         /* mark this plane as a scaler user in crtc_state */
4689         scaler_state->scaler_users |= (1 << scaler_user);
4690         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4691                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4692                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4693                 scaler_state->scaler_users);
4694
4695         return 0;
4696 }
4697
4698 /**
4699  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4700  *
4701  * @state: crtc's scaler state
4702  *
4703  * Return
4704  *     0 - scaler_usage updated successfully
4705  *    error - requested scaling cannot be supported or other error condition
4706  */
4707 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4708 {
4709         const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4710
4711         return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4712                 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4713                 state->pipe_src_w, state->pipe_src_h,
4714                 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4715 }
4716
4717 /**
4718  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4719  *
4720  * @state: crtc's scaler state
4721  * @plane_state: atomic plane state to update
4722  *
4723  * Return
4724  *     0 - scaler_usage updated successfully
4725  *    error - requested scaling cannot be supported or other error condition
4726  */
4727 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4728                                    struct intel_plane_state *plane_state)
4729 {
4730
4731         struct intel_plane *intel_plane =
4732                 to_intel_plane(plane_state->base.plane);
4733         struct drm_framebuffer *fb = plane_state->base.fb;
4734         int ret;
4735
4736         bool force_detach = !fb || !plane_state->base.visible;
4737
4738         ret = skl_update_scaler(crtc_state, force_detach,
4739                                 drm_plane_index(&intel_plane->base),
4740                                 &plane_state->scaler_id,
4741                                 plane_state->base.rotation,
4742                                 drm_rect_width(&plane_state->base.src) >> 16,
4743                                 drm_rect_height(&plane_state->base.src) >> 16,
4744                                 drm_rect_width(&plane_state->base.dst),
4745                                 drm_rect_height(&plane_state->base.dst));
4746
4747         if (ret || plane_state->scaler_id < 0)
4748                 return ret;
4749
4750         /* check colorkey */
4751         if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4752                 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4753                               intel_plane->base.base.id,
4754                               intel_plane->base.name);
4755                 return -EINVAL;
4756         }
4757
4758         /* Check src format */
4759         switch (fb->format->format) {
4760         case DRM_FORMAT_RGB565:
4761         case DRM_FORMAT_XBGR8888:
4762         case DRM_FORMAT_XRGB8888:
4763         case DRM_FORMAT_ABGR8888:
4764         case DRM_FORMAT_ARGB8888:
4765         case DRM_FORMAT_XRGB2101010:
4766         case DRM_FORMAT_XBGR2101010:
4767         case DRM_FORMAT_YUYV:
4768         case DRM_FORMAT_YVYU:
4769         case DRM_FORMAT_UYVY:
4770         case DRM_FORMAT_VYUY:
4771                 break;
4772         default:
4773                 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4774                               intel_plane->base.base.id, intel_plane->base.name,
4775                               fb->base.id, fb->format->format);
4776                 return -EINVAL;
4777         }
4778
4779         return 0;
4780 }
4781
4782 static void skylake_scaler_disable(struct intel_crtc *crtc)
4783 {
4784         int i;
4785
4786         for (i = 0; i < crtc->num_scalers; i++)
4787                 skl_detach_scaler(crtc, i);
4788 }
4789
4790 static void skylake_pfit_enable(struct intel_crtc *crtc)
4791 {
4792         struct drm_device *dev = crtc->base.dev;
4793         struct drm_i915_private *dev_priv = to_i915(dev);
4794         int pipe = crtc->pipe;
4795         struct intel_crtc_scaler_state *scaler_state =
4796                 &crtc->config->scaler_state;
4797
4798         DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4799
4800         if (crtc->config->pch_pfit.enabled) {
4801                 int id;
4802
4803                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4804                         DRM_ERROR("Requesting pfit without getting a scaler first\n");
4805                         return;
4806                 }
4807
4808                 id = scaler_state->scaler_id;
4809                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4810                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4811                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4812                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4813
4814                 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4815         }
4816 }
4817
4818 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4819 {
4820         struct drm_device *dev = crtc->base.dev;
4821         struct drm_i915_private *dev_priv = to_i915(dev);
4822         int pipe = crtc->pipe;
4823
4824         if (crtc->config->pch_pfit.enabled) {
4825                 /* Force use of hard-coded filter coefficients
4826                  * as some pre-programmed values are broken,
4827                  * e.g. x201.
4828                  */
4829                 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
4830                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4831                                                  PF_PIPE_SEL_IVB(pipe));
4832                 else
4833                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4834                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4835                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4836         }
4837 }
4838
4839 void hsw_enable_ips(struct intel_crtc *crtc)
4840 {
4841         struct drm_device *dev = crtc->base.dev;
4842         struct drm_i915_private *dev_priv = to_i915(dev);
4843
4844         if (!crtc->config->ips_enabled)
4845                 return;
4846
4847         /*
4848          * We can only enable IPS after we enable a plane and wait for a vblank
4849          * This function is called from post_plane_update, which is run after
4850          * a vblank wait.
4851          */
4852
4853         assert_plane_enabled(dev_priv, crtc->plane);
4854         if (IS_BROADWELL(dev_priv)) {
4855                 mutex_lock(&dev_priv->rps.hw_lock);
4856                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4857                 mutex_unlock(&dev_priv->rps.hw_lock);
4858                 /* Quoting Art Runyan: "its not safe to expect any particular
4859                  * value in IPS_CTL bit 31 after enabling IPS through the
4860                  * mailbox." Moreover, the mailbox may return a bogus state,
4861                  * so we need to just enable it and continue on.
4862                  */
4863         } else {
4864                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4865                 /* The bit only becomes 1 in the next vblank, so this wait here
4866                  * is essentially intel_wait_for_vblank. If we don't have this
4867                  * and don't wait for vblanks until the end of crtc_enable, then
4868                  * the HW state readout code will complain that the expected
4869                  * IPS_CTL value is not the one we read. */
4870                 if (intel_wait_for_register(dev_priv,
4871                                             IPS_CTL, IPS_ENABLE, IPS_ENABLE,
4872                                             50))
4873                         DRM_ERROR("Timed out waiting for IPS enable\n");
4874         }
4875 }
4876
4877 void hsw_disable_ips(struct intel_crtc *crtc)
4878 {
4879         struct drm_device *dev = crtc->base.dev;
4880         struct drm_i915_private *dev_priv = to_i915(dev);
4881
4882         if (!crtc->config->ips_enabled)
4883                 return;
4884
4885         assert_plane_enabled(dev_priv, crtc->plane);
4886         if (IS_BROADWELL(dev_priv)) {
4887                 mutex_lock(&dev_priv->rps.hw_lock);
4888                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4889                 mutex_unlock(&dev_priv->rps.hw_lock);
4890                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4891                 if (intel_wait_for_register(dev_priv,
4892                                             IPS_CTL, IPS_ENABLE, 0,
4893                                             42))
4894                         DRM_ERROR("Timed out waiting for IPS disable\n");
4895         } else {
4896                 I915_WRITE(IPS_CTL, 0);
4897                 POSTING_READ(IPS_CTL);
4898         }
4899
4900         /* We need to wait for a vblank before we can disable the plane. */
4901         intel_wait_for_vblank(dev_priv, crtc->pipe);
4902 }
4903
4904 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4905 {
4906         if (intel_crtc->overlay) {
4907                 struct drm_device *dev = intel_crtc->base.dev;
4908                 struct drm_i915_private *dev_priv = to_i915(dev);
4909
4910                 mutex_lock(&dev->struct_mutex);
4911                 dev_priv->mm.interruptible = false;
4912                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4913                 dev_priv->mm.interruptible = true;
4914                 mutex_unlock(&dev->struct_mutex);
4915         }
4916
4917         /* Let userspace switch the overlay on again. In most cases userspace
4918          * has to recompute where to put it anyway.
4919          */
4920 }
4921
4922 /**
4923  * intel_post_enable_primary - Perform operations after enabling primary plane
4924  * @crtc: the CRTC whose primary plane was just enabled
4925  *
4926  * Performs potentially sleeping operations that must be done after the primary
4927  * plane is enabled, such as updating FBC and IPS.  Note that this may be
4928  * called due to an explicit primary plane update, or due to an implicit
4929  * re-enable that is caused when a sprite plane is updated to no longer
4930  * completely hide the primary plane.
4931  */
4932 static void
4933 intel_post_enable_primary(struct drm_crtc *crtc)
4934 {
4935         struct drm_device *dev = crtc->dev;
4936         struct drm_i915_private *dev_priv = to_i915(dev);
4937         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4938         int pipe = intel_crtc->pipe;
4939
4940         /*
4941          * FIXME IPS should be fine as long as one plane is
4942          * enabled, but in practice it seems to have problems
4943          * when going from primary only to sprite only and vice
4944          * versa.
4945          */
4946         hsw_enable_ips(intel_crtc);
4947
4948         /*
4949          * Gen2 reports pipe underruns whenever all planes are disabled.
4950          * So don't enable underrun reporting before at least some planes
4951          * are enabled.
4952          * FIXME: Need to fix the logic to work when we turn off all planes
4953          * but leave the pipe running.
4954          */
4955         if (IS_GEN2(dev_priv))
4956                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4957
4958         /* Underruns don't always raise interrupts, so check manually. */
4959         intel_check_cpu_fifo_underruns(dev_priv);
4960         intel_check_pch_fifo_underruns(dev_priv);
4961 }
4962
4963 /* FIXME move all this to pre_plane_update() with proper state tracking */
4964 static void
4965 intel_pre_disable_primary(struct drm_crtc *crtc)
4966 {
4967         struct drm_device *dev = crtc->dev;
4968         struct drm_i915_private *dev_priv = to_i915(dev);
4969         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4970         int pipe = intel_crtc->pipe;
4971
4972         /*
4973          * Gen2 reports pipe underruns whenever all planes are disabled.
4974          * So diasble underrun reporting before all the planes get disabled.
4975          * FIXME: Need to fix the logic to work when we turn off all planes
4976          * but leave the pipe running.
4977          */
4978         if (IS_GEN2(dev_priv))
4979                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4980
4981         /*
4982          * FIXME IPS should be fine as long as one plane is
4983          * enabled, but in practice it seems to have problems
4984          * when going from primary only to sprite only and vice
4985          * versa.
4986          */
4987         hsw_disable_ips(intel_crtc);
4988 }
4989
4990 /* FIXME get rid of this and use pre_plane_update */
4991 static void
4992 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
4993 {
4994         struct drm_device *dev = crtc->dev;
4995         struct drm_i915_private *dev_priv = to_i915(dev);
4996         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4997         int pipe = intel_crtc->pipe;
4998
4999         intel_pre_disable_primary(crtc);
5000
5001         /*
5002          * Vblank time updates from the shadow to live plane control register
5003          * are blocked if the memory self-refresh mode is active at that
5004          * moment. So to make sure the plane gets truly disabled, disable
5005          * first the self-refresh mode. The self-refresh enable bit in turn
5006          * will be checked/applied by the HW only at the next frame start
5007          * event which is after the vblank start event, so we need to have a
5008          * wait-for-vblank between disabling the plane and the pipe.
5009          */
5010         if (HAS_GMCH_DISPLAY(dev_priv) &&
5011             intel_set_memory_cxsr(dev_priv, false))
5012                 intel_wait_for_vblank(dev_priv, pipe);
5013 }
5014
5015 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
5016 {
5017         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5018         struct drm_atomic_state *old_state = old_crtc_state->base.state;
5019         struct intel_crtc_state *pipe_config =
5020                 to_intel_crtc_state(crtc->base.state);
5021         struct drm_plane *primary = crtc->base.primary;
5022         struct drm_plane_state *old_pri_state =
5023                 drm_atomic_get_existing_plane_state(old_state, primary);
5024
5025         intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
5026
5027         crtc->wm.cxsr_allowed = true;
5028
5029         if (pipe_config->update_wm_post && pipe_config->base.active)
5030                 intel_update_watermarks(crtc);
5031
5032         if (old_pri_state) {
5033                 struct intel_plane_state *primary_state =
5034                         to_intel_plane_state(primary->state);
5035                 struct intel_plane_state *old_primary_state =
5036                         to_intel_plane_state(old_pri_state);
5037
5038                 intel_fbc_post_update(crtc);
5039
5040                 if (primary_state->base.visible &&
5041                     (needs_modeset(&pipe_config->base) ||
5042                      !old_primary_state->base.visible))
5043                         intel_post_enable_primary(&crtc->base);
5044         }
5045 }
5046
5047 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
5048 {
5049         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5050         struct drm_device *dev = crtc->base.dev;
5051         struct drm_i915_private *dev_priv = to_i915(dev);
5052         struct intel_crtc_state *pipe_config =
5053                 to_intel_crtc_state(crtc->base.state);
5054         struct drm_atomic_state *old_state = old_crtc_state->base.state;
5055         struct drm_plane *primary = crtc->base.primary;
5056         struct drm_plane_state *old_pri_state =
5057                 drm_atomic_get_existing_plane_state(old_state, primary);
5058         bool modeset = needs_modeset(&pipe_config->base);
5059         struct intel_atomic_state *old_intel_state =
5060                 to_intel_atomic_state(old_state);
5061
5062         if (old_pri_state) {
5063                 struct intel_plane_state *primary_state =
5064                         to_intel_plane_state(primary->state);
5065                 struct intel_plane_state *old_primary_state =
5066                         to_intel_plane_state(old_pri_state);
5067
5068                 intel_fbc_pre_update(crtc, pipe_config, primary_state);
5069
5070                 if (old_primary_state->base.visible &&
5071                     (modeset || !primary_state->base.visible))
5072                         intel_pre_disable_primary(&crtc->base);
5073         }
5074
5075         if (pipe_config->disable_cxsr && HAS_GMCH_DISPLAY(dev_priv)) {
5076                 crtc->wm.cxsr_allowed = false;
5077
5078                 /*
5079                  * Vblank time updates from the shadow to live plane control register
5080                  * are blocked if the memory self-refresh mode is active at that
5081                  * moment. So to make sure the plane gets truly disabled, disable
5082                  * first the self-refresh mode. The self-refresh enable bit in turn
5083                  * will be checked/applied by the HW only at the next frame start
5084                  * event which is after the vblank start event, so we need to have a
5085                  * wait-for-vblank between disabling the plane and the pipe.
5086                  */
5087                 if (old_crtc_state->base.active &&
5088                     intel_set_memory_cxsr(dev_priv, false))
5089                         intel_wait_for_vblank(dev_priv, crtc->pipe);
5090         }
5091
5092         /*
5093          * IVB workaround: must disable low power watermarks for at least
5094          * one frame before enabling scaling.  LP watermarks can be re-enabled
5095          * when scaling is disabled.
5096          *
5097          * WaCxSRDisabledForSpriteScaling:ivb
5098          */
5099         if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev))
5100                 intel_wait_for_vblank(dev_priv, crtc->pipe);
5101
5102         /*
5103          * If we're doing a modeset, we're done.  No need to do any pre-vblank
5104          * watermark programming here.
5105          */
5106         if (needs_modeset(&pipe_config->base))
5107                 return;
5108
5109         /*
5110          * For platforms that support atomic watermarks, program the
5111          * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
5112          * will be the intermediate values that are safe for both pre- and
5113          * post- vblank; when vblank happens, the 'active' values will be set
5114          * to the final 'target' values and we'll do this again to get the
5115          * optimal watermarks.  For gen9+ platforms, the values we program here
5116          * will be the final target values which will get automatically latched
5117          * at vblank time; no further programming will be necessary.
5118          *
5119          * If a platform hasn't been transitioned to atomic watermarks yet,
5120          * we'll continue to update watermarks the old way, if flags tell
5121          * us to.
5122          */
5123         if (dev_priv->display.initial_watermarks != NULL)
5124                 dev_priv->display.initial_watermarks(old_intel_state,
5125                                                      pipe_config);
5126         else if (pipe_config->update_wm_pre)
5127                 intel_update_watermarks(crtc);
5128 }
5129
5130 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
5131 {
5132         struct drm_device *dev = crtc->dev;
5133         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5134         struct drm_plane *p;
5135         int pipe = intel_crtc->pipe;
5136
5137         intel_crtc_dpms_overlay_disable(intel_crtc);
5138
5139         drm_for_each_plane_mask(p, dev, plane_mask)
5140                 to_intel_plane(p)->disable_plane(p, crtc);
5141
5142         /*
5143          * FIXME: Once we grow proper nuclear flip support out of this we need
5144          * to compute the mask of flip planes precisely. For the time being
5145          * consider this a flip to a NULL plane.
5146          */
5147         intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe));
5148 }
5149
5150 static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc,
5151                                           struct intel_crtc_state *crtc_state,
5152                                           struct drm_atomic_state *old_state)
5153 {
5154         struct drm_connector_state *old_conn_state;
5155         struct drm_connector *conn;
5156         int i;
5157
5158         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5159                 struct drm_connector_state *conn_state = conn->state;
5160                 struct intel_encoder *encoder =
5161                         to_intel_encoder(conn_state->best_encoder);
5162
5163                 if (conn_state->crtc != crtc)
5164                         continue;
5165
5166                 if (encoder->pre_pll_enable)
5167                         encoder->pre_pll_enable(encoder, crtc_state, conn_state);
5168         }
5169 }
5170
5171 static void intel_encoders_pre_enable(struct drm_crtc *crtc,
5172                                       struct intel_crtc_state *crtc_state,
5173                                       struct drm_atomic_state *old_state)
5174 {
5175         struct drm_connector_state *old_conn_state;
5176         struct drm_connector *conn;
5177         int i;
5178
5179         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5180                 struct drm_connector_state *conn_state = conn->state;
5181                 struct intel_encoder *encoder =
5182                         to_intel_encoder(conn_state->best_encoder);
5183
5184                 if (conn_state->crtc != crtc)
5185                         continue;
5186
5187                 if (encoder->pre_enable)
5188                         encoder->pre_enable(encoder, crtc_state, conn_state);
5189         }
5190 }
5191
5192 static void intel_encoders_enable(struct drm_crtc *crtc,
5193                                   struct intel_crtc_state *crtc_state,
5194                                   struct drm_atomic_state *old_state)
5195 {
5196         struct drm_connector_state *old_conn_state;
5197         struct drm_connector *conn;
5198         int i;
5199
5200         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5201                 struct drm_connector_state *conn_state = conn->state;
5202                 struct intel_encoder *encoder =
5203                         to_intel_encoder(conn_state->best_encoder);
5204
5205                 if (conn_state->crtc != crtc)
5206                         continue;
5207
5208                 encoder->enable(encoder, crtc_state, conn_state);
5209                 intel_opregion_notify_encoder(encoder, true);
5210         }
5211 }
5212
5213 static void intel_encoders_disable(struct drm_crtc *crtc,
5214                                    struct intel_crtc_state *old_crtc_state,
5215                                    struct drm_atomic_state *old_state)
5216 {
5217         struct drm_connector_state *old_conn_state;
5218         struct drm_connector *conn;
5219         int i;
5220
5221         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5222                 struct intel_encoder *encoder =
5223                         to_intel_encoder(old_conn_state->best_encoder);
5224
5225                 if (old_conn_state->crtc != crtc)
5226                         continue;
5227
5228                 intel_opregion_notify_encoder(encoder, false);
5229                 encoder->disable(encoder, old_crtc_state, old_conn_state);
5230         }
5231 }
5232
5233 static void intel_encoders_post_disable(struct drm_crtc *crtc,
5234                                         struct intel_crtc_state *old_crtc_state,
5235                                         struct drm_atomic_state *old_state)
5236 {
5237         struct drm_connector_state *old_conn_state;
5238         struct drm_connector *conn;
5239         int i;
5240
5241         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5242                 struct intel_encoder *encoder =
5243                         to_intel_encoder(old_conn_state->best_encoder);
5244
5245                 if (old_conn_state->crtc != crtc)
5246                         continue;
5247
5248                 if (encoder->post_disable)
5249                         encoder->post_disable(encoder, old_crtc_state, old_conn_state);
5250         }
5251 }
5252
5253 static void intel_encoders_post_pll_disable(struct drm_crtc *crtc,
5254                                             struct intel_crtc_state *old_crtc_state,
5255                                             struct drm_atomic_state *old_state)
5256 {
5257         struct drm_connector_state *old_conn_state;
5258         struct drm_connector *conn;
5259         int i;
5260
5261         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5262                 struct intel_encoder *encoder =
5263                         to_intel_encoder(old_conn_state->best_encoder);
5264
5265                 if (old_conn_state->crtc != crtc)
5266                         continue;
5267
5268                 if (encoder->post_pll_disable)
5269                         encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state);
5270         }
5271 }
5272
5273 static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
5274                                  struct drm_atomic_state *old_state)
5275 {
5276         struct drm_crtc *crtc = pipe_config->base.crtc;
5277         struct drm_device *dev = crtc->dev;
5278         struct drm_i915_private *dev_priv = to_i915(dev);
5279         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5280         int pipe = intel_crtc->pipe;
5281         struct intel_atomic_state *old_intel_state =
5282                 to_intel_atomic_state(old_state);
5283
5284         if (WARN_ON(intel_crtc->active))
5285                 return;
5286
5287         /*
5288          * Sometimes spurious CPU pipe underruns happen during FDI
5289          * training, at least with VGA+HDMI cloning. Suppress them.
5290          *
5291          * On ILK we get an occasional spurious CPU pipe underruns
5292          * between eDP port A enable and vdd enable. Also PCH port
5293          * enable seems to result in the occasional CPU pipe underrun.
5294          *
5295          * Spurious PCH underruns also occur during PCH enabling.
5296          */
5297         if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
5298                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5299         if (intel_crtc->config->has_pch_encoder)
5300                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5301
5302         if (intel_crtc->config->has_pch_encoder)
5303                 intel_prepare_shared_dpll(intel_crtc);
5304
5305         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5306                 intel_dp_set_m_n(intel_crtc, M1_N1);
5307
5308         intel_set_pipe_timings(intel_crtc);
5309         intel_set_pipe_src_size(intel_crtc);
5310
5311         if (intel_crtc->config->has_pch_encoder) {
5312                 intel_cpu_transcoder_set_m_n(intel_crtc,
5313                                      &intel_crtc->config->fdi_m_n, NULL);
5314         }
5315
5316         ironlake_set_pipeconf(crtc);
5317
5318         intel_crtc->active = true;
5319
5320         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5321
5322         if (intel_crtc->config->has_pch_encoder) {
5323                 /* Note: FDI PLL enabling _must_ be done before we enable the
5324                  * cpu pipes, hence this is separate from all the other fdi/pch
5325                  * enabling. */
5326                 ironlake_fdi_pll_enable(intel_crtc);
5327         } else {
5328                 assert_fdi_tx_disabled(dev_priv, pipe);
5329                 assert_fdi_rx_disabled(dev_priv, pipe);
5330         }
5331
5332         ironlake_pfit_enable(intel_crtc);
5333
5334         /*
5335          * On ILK+ LUT must be loaded before the pipe is running but with
5336          * clocks enabled
5337          */
5338         intel_color_load_luts(&pipe_config->base);
5339
5340         if (dev_priv->display.initial_watermarks != NULL)
5341                 dev_priv->display.initial_watermarks(old_intel_state, intel_crtc->config);
5342         intel_enable_pipe(intel_crtc);
5343
5344         if (intel_crtc->config->has_pch_encoder)
5345                 ironlake_pch_enable(crtc);
5346
5347         assert_vblank_disabled(crtc);
5348         drm_crtc_vblank_on(crtc);
5349
5350         intel_encoders_enable(crtc, pipe_config, old_state);
5351
5352         if (HAS_PCH_CPT(dev_priv))
5353                 cpt_verify_modeset(dev, intel_crtc->pipe);
5354
5355         /* Must wait for vblank to avoid spurious PCH FIFO underruns */
5356         if (intel_crtc->config->has_pch_encoder)
5357                 intel_wait_for_vblank(dev_priv, pipe);
5358         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5359         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5360 }
5361
5362 /* IPS only exists on ULT machines and is tied to pipe A. */
5363 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
5364 {
5365         return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
5366 }
5367
5368 static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
5369                                 struct drm_atomic_state *old_state)
5370 {
5371         struct drm_crtc *crtc = pipe_config->base.crtc;
5372         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5373         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5374         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
5375         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5376         struct intel_atomic_state *old_intel_state =
5377                 to_intel_atomic_state(old_state);
5378
5379         if (WARN_ON(intel_crtc->active))
5380                 return;
5381
5382         if (intel_crtc->config->has_pch_encoder)
5383                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5384                                                       false);
5385
5386         intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5387
5388         if (intel_crtc->config->shared_dpll)
5389                 intel_enable_shared_dpll(intel_crtc);
5390
5391         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5392                 intel_dp_set_m_n(intel_crtc, M1_N1);
5393
5394         if (!transcoder_is_dsi(cpu_transcoder))
5395                 intel_set_pipe_timings(intel_crtc);
5396
5397         intel_set_pipe_src_size(intel_crtc);
5398
5399         if (cpu_transcoder != TRANSCODER_EDP &&
5400             !transcoder_is_dsi(cpu_transcoder)) {
5401                 I915_WRITE(PIPE_MULT(cpu_transcoder),
5402                            intel_crtc->config->pixel_multiplier - 1);
5403         }
5404
5405         if (intel_crtc->config->has_pch_encoder) {
5406                 intel_cpu_transcoder_set_m_n(intel_crtc,
5407                                      &intel_crtc->config->fdi_m_n, NULL);
5408         }
5409
5410         if (!transcoder_is_dsi(cpu_transcoder))
5411                 haswell_set_pipeconf(crtc);
5412
5413         haswell_set_pipemisc(crtc);
5414
5415         intel_color_set_csc(&pipe_config->base);
5416
5417         intel_crtc->active = true;
5418
5419         if (intel_crtc->config->has_pch_encoder)
5420                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5421         else
5422                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5423
5424         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5425
5426         if (intel_crtc->config->has_pch_encoder)
5427                 dev_priv->display.fdi_link_train(crtc);
5428
5429         if (!transcoder_is_dsi(cpu_transcoder))
5430                 intel_ddi_enable_pipe_clock(intel_crtc);
5431
5432         if (INTEL_GEN(dev_priv) >= 9)
5433                 skylake_pfit_enable(intel_crtc);
5434         else
5435                 ironlake_pfit_enable(intel_crtc);
5436
5437         /*
5438          * On ILK+ LUT must be loaded before the pipe is running but with
5439          * clocks enabled
5440          */
5441         intel_color_load_luts(&pipe_config->base);
5442
5443         intel_ddi_set_pipe_settings(crtc);
5444         if (!transcoder_is_dsi(cpu_transcoder))
5445                 intel_ddi_enable_transcoder_func(crtc);
5446
5447         if (dev_priv->display.initial_watermarks != NULL)
5448                 dev_priv->display.initial_watermarks(old_intel_state, pipe_config);
5449
5450         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5451         if (!transcoder_is_dsi(cpu_transcoder))
5452                 intel_enable_pipe(intel_crtc);
5453
5454         if (intel_crtc->config->has_pch_encoder)
5455                 lpt_pch_enable(crtc);
5456
5457         if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5458                 intel_ddi_set_vc_payload_alloc(crtc, true);
5459
5460         assert_vblank_disabled(crtc);
5461         drm_crtc_vblank_on(crtc);
5462
5463         intel_encoders_enable(crtc, pipe_config, old_state);
5464
5465         if (intel_crtc->config->has_pch_encoder) {
5466                 intel_wait_for_vblank(dev_priv, pipe);
5467                 intel_wait_for_vblank(dev_priv, pipe);
5468                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5469                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5470                                                       true);
5471         }
5472
5473         /* If we change the relative order between pipe/planes enabling, we need
5474          * to change the workaround. */
5475         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5476         if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
5477                 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5478                 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5479         }
5480 }
5481
5482 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5483 {
5484         struct drm_device *dev = crtc->base.dev;
5485         struct drm_i915_private *dev_priv = to_i915(dev);
5486         int pipe = crtc->pipe;
5487
5488         /* To avoid upsetting the power well on haswell only disable the pfit if
5489          * it's in use. The hw state code will make sure we get this right. */
5490         if (force || crtc->config->pch_pfit.enabled) {
5491                 I915_WRITE(PF_CTL(pipe), 0);
5492                 I915_WRITE(PF_WIN_POS(pipe), 0);
5493                 I915_WRITE(PF_WIN_SZ(pipe), 0);
5494         }
5495 }
5496
5497 static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
5498                                   struct drm_atomic_state *old_state)
5499 {
5500         struct drm_crtc *crtc = old_crtc_state->base.crtc;
5501         struct drm_device *dev = crtc->dev;
5502         struct drm_i915_private *dev_priv = to_i915(dev);
5503         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5504         int pipe = intel_crtc->pipe;
5505
5506         /*
5507          * Sometimes spurious CPU pipe underruns happen when the
5508          * pipe is already disabled, but FDI RX/TX is still enabled.
5509          * Happens at least with VGA+HDMI cloning. Suppress them.
5510          */
5511         if (intel_crtc->config->has_pch_encoder) {
5512                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5513                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5514         }
5515
5516         intel_encoders_disable(crtc, old_crtc_state, old_state);
5517
5518         drm_crtc_vblank_off(crtc);
5519         assert_vblank_disabled(crtc);
5520
5521         intel_disable_pipe(intel_crtc);
5522
5523         ironlake_pfit_disable(intel_crtc, false);
5524
5525         if (intel_crtc->config->has_pch_encoder)
5526                 ironlake_fdi_disable(crtc);
5527
5528         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5529
5530         if (intel_crtc->config->has_pch_encoder) {
5531                 ironlake_disable_pch_transcoder(dev_priv, pipe);
5532
5533                 if (HAS_PCH_CPT(dev_priv)) {
5534                         i915_reg_t reg;
5535                         u32 temp;
5536
5537                         /* disable TRANS_DP_CTL */
5538                         reg = TRANS_DP_CTL(pipe);
5539                         temp = I915_READ(reg);
5540                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5541                                   TRANS_DP_PORT_SEL_MASK);
5542                         temp |= TRANS_DP_PORT_SEL_NONE;
5543                         I915_WRITE(reg, temp);
5544
5545                         /* disable DPLL_SEL */
5546                         temp = I915_READ(PCH_DPLL_SEL);
5547                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5548                         I915_WRITE(PCH_DPLL_SEL, temp);
5549                 }
5550
5551                 ironlake_fdi_pll_disable(intel_crtc);
5552         }
5553
5554         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5555         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5556 }
5557
5558 static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
5559                                  struct drm_atomic_state *old_state)
5560 {
5561         struct drm_crtc *crtc = old_crtc_state->base.crtc;
5562         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5563         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5564         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5565
5566         if (intel_crtc->config->has_pch_encoder)
5567                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5568                                                       false);
5569
5570         intel_encoders_disable(crtc, old_crtc_state, old_state);
5571
5572         drm_crtc_vblank_off(crtc);
5573         assert_vblank_disabled(crtc);
5574
5575         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5576         if (!transcoder_is_dsi(cpu_transcoder))
5577                 intel_disable_pipe(intel_crtc);
5578
5579         if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5580                 intel_ddi_set_vc_payload_alloc(crtc, false);
5581
5582         if (!transcoder_is_dsi(cpu_transcoder))
5583                 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5584
5585         if (INTEL_GEN(dev_priv) >= 9)
5586                 skylake_scaler_disable(intel_crtc);
5587         else
5588                 ironlake_pfit_disable(intel_crtc, false);
5589
5590         if (!transcoder_is_dsi(cpu_transcoder))
5591                 intel_ddi_disable_pipe_clock(intel_crtc);
5592
5593         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5594
5595         if (old_crtc_state->has_pch_encoder)
5596                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5597                                                       true);
5598 }
5599
5600 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5601 {
5602         struct drm_device *dev = crtc->base.dev;
5603         struct drm_i915_private *dev_priv = to_i915(dev);
5604         struct intel_crtc_state *pipe_config = crtc->config;
5605
5606         if (!pipe_config->gmch_pfit.control)
5607                 return;
5608
5609         /*
5610          * The panel fitter should only be adjusted whilst the pipe is disabled,
5611          * according to register description and PRM.
5612          */
5613         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5614         assert_pipe_disabled(dev_priv, crtc->pipe);
5615
5616         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5617         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5618
5619         /* Border color in case we don't scale up to the full screen. Black by
5620          * default, change to something else for debugging. */
5621         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5622 }
5623
5624 static enum intel_display_power_domain port_to_power_domain(enum port port)
5625 {
5626         switch (port) {
5627         case PORT_A:
5628                 return POWER_DOMAIN_PORT_DDI_A_LANES;
5629         case PORT_B:
5630                 return POWER_DOMAIN_PORT_DDI_B_LANES;
5631         case PORT_C:
5632                 return POWER_DOMAIN_PORT_DDI_C_LANES;
5633         case PORT_D:
5634                 return POWER_DOMAIN_PORT_DDI_D_LANES;
5635         case PORT_E:
5636                 return POWER_DOMAIN_PORT_DDI_E_LANES;
5637         default:
5638                 MISSING_CASE(port);
5639                 return POWER_DOMAIN_PORT_OTHER;
5640         }
5641 }
5642
5643 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5644 {
5645         switch (port) {
5646         case PORT_A:
5647                 return POWER_DOMAIN_AUX_A;
5648         case PORT_B:
5649                 return POWER_DOMAIN_AUX_B;
5650         case PORT_C:
5651                 return POWER_DOMAIN_AUX_C;
5652         case PORT_D:
5653                 return POWER_DOMAIN_AUX_D;
5654         case PORT_E:
5655                 /* FIXME: Check VBT for actual wiring of PORT E */
5656                 return POWER_DOMAIN_AUX_D;
5657         default:
5658                 MISSING_CASE(port);
5659                 return POWER_DOMAIN_AUX_A;
5660         }
5661 }
5662
5663 enum intel_display_power_domain
5664 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5665 {
5666         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
5667         struct intel_digital_port *intel_dig_port;
5668
5669         switch (intel_encoder->type) {
5670         case INTEL_OUTPUT_UNKNOWN:
5671                 /* Only DDI platforms should ever use this output type */
5672                 WARN_ON_ONCE(!HAS_DDI(dev_priv));
5673         case INTEL_OUTPUT_DP:
5674         case INTEL_OUTPUT_HDMI:
5675         case INTEL_OUTPUT_EDP:
5676                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5677                 return port_to_power_domain(intel_dig_port->port);
5678         case INTEL_OUTPUT_DP_MST:
5679                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5680                 return port_to_power_domain(intel_dig_port->port);
5681         case INTEL_OUTPUT_ANALOG:
5682                 return POWER_DOMAIN_PORT_CRT;
5683         case INTEL_OUTPUT_DSI:
5684                 return POWER_DOMAIN_PORT_DSI;
5685         default:
5686                 return POWER_DOMAIN_PORT_OTHER;
5687         }
5688 }
5689
5690 enum intel_display_power_domain
5691 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5692 {
5693         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
5694         struct intel_digital_port *intel_dig_port;
5695
5696         switch (intel_encoder->type) {
5697         case INTEL_OUTPUT_UNKNOWN:
5698         case INTEL_OUTPUT_HDMI:
5699                 /*
5700                  * Only DDI platforms should ever use these output types.
5701                  * We can get here after the HDMI detect code has already set
5702                  * the type of the shared encoder. Since we can't be sure
5703                  * what's the status of the given connectors, play safe and
5704                  * run the DP detection too.
5705                  */
5706                 WARN_ON_ONCE(!HAS_DDI(dev_priv));
5707         case INTEL_OUTPUT_DP:
5708         case INTEL_OUTPUT_EDP:
5709                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5710                 return port_to_aux_power_domain(intel_dig_port->port);
5711         case INTEL_OUTPUT_DP_MST:
5712                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5713                 return port_to_aux_power_domain(intel_dig_port->port);
5714         default:
5715                 MISSING_CASE(intel_encoder->type);
5716                 return POWER_DOMAIN_AUX_A;
5717         }
5718 }
5719
5720 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc,
5721                                             struct intel_crtc_state *crtc_state)
5722 {
5723         struct drm_device *dev = crtc->dev;
5724         struct drm_encoder *encoder;
5725         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5726         enum pipe pipe = intel_crtc->pipe;
5727         unsigned long mask;
5728         enum transcoder transcoder = crtc_state->cpu_transcoder;
5729
5730         if (!crtc_state->base.active)
5731                 return 0;
5732
5733         mask = BIT(POWER_DOMAIN_PIPE(pipe));
5734         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5735         if (crtc_state->pch_pfit.enabled ||
5736             crtc_state->pch_pfit.force_thru)
5737                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5738
5739         drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5740                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5741
5742                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5743         }
5744
5745         if (crtc_state->shared_dpll)
5746                 mask |= BIT(POWER_DOMAIN_PLLS);
5747
5748         return mask;
5749 }
5750
5751 static unsigned long
5752 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5753                                struct intel_crtc_state *crtc_state)
5754 {
5755         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5756         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5757         enum intel_display_power_domain domain;
5758         unsigned long domains, new_domains, old_domains;
5759
5760         old_domains = intel_crtc->enabled_power_domains;
5761         intel_crtc->enabled_power_domains = new_domains =
5762                 get_crtc_power_domains(crtc, crtc_state);
5763
5764         domains = new_domains & ~old_domains;
5765
5766         for_each_power_domain(domain, domains)
5767                 intel_display_power_get(dev_priv, domain);
5768
5769         return old_domains & ~new_domains;
5770 }
5771
5772 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5773                                       unsigned long domains)
5774 {
5775         enum intel_display_power_domain domain;
5776
5777         for_each_power_domain(domain, domains)
5778                 intel_display_power_put(dev_priv, domain);
5779 }
5780
5781 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5782 {
5783         int max_cdclk_freq = dev_priv->max_cdclk_freq;
5784
5785         if (IS_GEMINILAKE(dev_priv))
5786                 return 2 * max_cdclk_freq;
5787         else if (INTEL_INFO(dev_priv)->gen >= 9 ||
5788                  IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5789                 return max_cdclk_freq;
5790         else if (IS_CHERRYVIEW(dev_priv))
5791                 return max_cdclk_freq*95/100;
5792         else if (INTEL_INFO(dev_priv)->gen < 4)
5793                 return 2*max_cdclk_freq*90/100;
5794         else
5795                 return max_cdclk_freq*90/100;
5796 }
5797
5798 static int skl_calc_cdclk(int max_pixclk, int vco);
5799
5800 static void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
5801 {
5802         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5803                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5804                 int max_cdclk, vco;
5805
5806                 vco = dev_priv->skl_preferred_vco_freq;
5807                 WARN_ON(vco != 8100000 && vco != 8640000);
5808
5809                 /*
5810                  * Use the lower (vco 8640) cdclk values as a
5811                  * first guess. skl_calc_cdclk() will correct it
5812                  * if the preferred vco is 8100 instead.
5813                  */
5814                 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5815                         max_cdclk = 617143;
5816                 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5817                         max_cdclk = 540000;
5818                 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5819                         max_cdclk = 432000;
5820                 else
5821                         max_cdclk = 308571;
5822
5823                 dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
5824         } else if (IS_GEMINILAKE(dev_priv)) {
5825                 dev_priv->max_cdclk_freq = 316800;
5826         } else if (IS_BROXTON(dev_priv)) {
5827                 dev_priv->max_cdclk_freq = 624000;
5828         } else if (IS_BROADWELL(dev_priv))  {
5829                 /*
5830                  * FIXME with extra cooling we can allow
5831                  * 540 MHz for ULX and 675 Mhz for ULT.
5832                  * How can we know if extra cooling is
5833                  * available? PCI ID, VTB, something else?
5834                  */
5835                 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5836                         dev_priv->max_cdclk_freq = 450000;
5837                 else if (IS_BDW_ULX(dev_priv))
5838                         dev_priv->max_cdclk_freq = 450000;
5839                 else if (IS_BDW_ULT(dev_priv))
5840                         dev_priv->max_cdclk_freq = 540000;
5841                 else
5842                         dev_priv->max_cdclk_freq = 675000;
5843         } else if (IS_CHERRYVIEW(dev_priv)) {
5844                 dev_priv->max_cdclk_freq = 320000;
5845         } else if (IS_VALLEYVIEW(dev_priv)) {
5846                 dev_priv->max_cdclk_freq = 400000;
5847         } else {
5848                 /* otherwise assume cdclk is fixed */
5849                 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5850         }
5851
5852         dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5853
5854         DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5855                          dev_priv->max_cdclk_freq);
5856
5857         DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5858                          dev_priv->max_dotclk_freq);
5859 }
5860
5861 static void intel_update_cdclk(struct drm_i915_private *dev_priv)
5862 {
5863         dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev_priv);
5864
5865         if (INTEL_GEN(dev_priv) >= 9)
5866                 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n",
5867                                  dev_priv->cdclk_freq, dev_priv->cdclk_pll.vco,
5868                                  dev_priv->cdclk_pll.ref);
5869         else
5870                 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5871                                  dev_priv->cdclk_freq);
5872
5873         /*
5874          * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
5875          * Programmng [sic] note: bit[9:2] should be programmed to the number
5876          * of cdclk that generates 4MHz reference clock freq which is used to
5877          * generate GMBus clock. This will vary with the cdclk freq.
5878          */
5879         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5880                 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5881 }
5882
5883 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5884 static int skl_cdclk_decimal(int cdclk)
5885 {
5886         return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
5887 }
5888
5889 static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
5890 {
5891         int ratio;
5892
5893         if (cdclk == dev_priv->cdclk_pll.ref)
5894                 return 0;
5895
5896         switch (cdclk) {
5897         default:
5898                 MISSING_CASE(cdclk);
5899         case 144000:
5900         case 288000:
5901         case 384000:
5902         case 576000:
5903                 ratio = 60;
5904                 break;
5905         case 624000:
5906                 ratio = 65;
5907                 break;
5908         }
5909
5910         return dev_priv->cdclk_pll.ref * ratio;
5911 }
5912
5913 static int glk_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
5914 {
5915         int ratio;
5916
5917         if (cdclk == dev_priv->cdclk_pll.ref)
5918                 return 0;
5919
5920         switch (cdclk) {
5921         default:
5922                 MISSING_CASE(cdclk);
5923         case  79200:
5924         case 158400:
5925         case 316800:
5926                 ratio = 33;
5927                 break;
5928         }
5929
5930         return dev_priv->cdclk_pll.ref * ratio;
5931 }
5932
5933 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
5934 {
5935         I915_WRITE(BXT_DE_PLL_ENABLE, 0);
5936
5937         /* Timeout 200us */
5938         if (intel_wait_for_register(dev_priv,
5939                                     BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 0,
5940                                     1))
5941                 DRM_ERROR("timeout waiting for DE PLL unlock\n");
5942
5943         dev_priv->cdclk_pll.vco = 0;
5944 }
5945
5946 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
5947 {
5948         int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk_pll.ref);
5949         u32 val;
5950
5951         val = I915_READ(BXT_DE_PLL_CTL);
5952         val &= ~BXT_DE_PLL_RATIO_MASK;
5953         val |= BXT_DE_PLL_RATIO(ratio);
5954         I915_WRITE(BXT_DE_PLL_CTL, val);
5955
5956         I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5957
5958         /* Timeout 200us */
5959         if (intel_wait_for_register(dev_priv,
5960                                     BXT_DE_PLL_ENABLE,
5961                                     BXT_DE_PLL_LOCK,
5962                                     BXT_DE_PLL_LOCK,
5963                                     1))
5964                 DRM_ERROR("timeout waiting for DE PLL lock\n");
5965
5966         dev_priv->cdclk_pll.vco = vco;
5967 }
5968
5969 static void bxt_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
5970 {
5971         u32 val, divider;
5972         int vco, ret;
5973
5974         if (IS_GEMINILAKE(dev_priv))
5975                 vco = glk_de_pll_vco(dev_priv, cdclk);
5976         else
5977                 vco = bxt_de_pll_vco(dev_priv, cdclk);
5978
5979         DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
5980
5981         /* cdclk = vco / 2 / div{1,1.5,2,4} */
5982         switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
5983         case 8:
5984                 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5985                 break;
5986         case 4:
5987                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5988                 break;
5989         case 3:
5990                 WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n");
5991                 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5992                 break;
5993         case 2:
5994                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5995                 break;
5996         default:
5997                 WARN_ON(cdclk != dev_priv->cdclk_pll.ref);
5998                 WARN_ON(vco != 0);
5999
6000                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
6001                 break;
6002         }
6003
6004         /* Inform power controller of upcoming frequency change */
6005         mutex_lock(&dev_priv->rps.hw_lock);
6006         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
6007                                       0x80000000);
6008         mutex_unlock(&dev_priv->rps.hw_lock);
6009
6010         if (ret) {
6011                 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
6012                           ret, cdclk);
6013                 return;
6014         }
6015
6016         if (dev_priv->cdclk_pll.vco != 0 &&
6017             dev_priv->cdclk_pll.vco != vco)
6018                 bxt_de_pll_disable(dev_priv);
6019
6020         if (dev_priv->cdclk_pll.vco != vco)
6021                 bxt_de_pll_enable(dev_priv, vco);
6022
6023         val = divider | skl_cdclk_decimal(cdclk);
6024         /*
6025          * FIXME if only the cd2x divider needs changing, it could be done
6026          * without shutting off the pipe (if only one pipe is active).
6027          */
6028         val |= BXT_CDCLK_CD2X_PIPE_NONE;
6029         /*
6030          * Disable SSA Precharge when CD clock frequency < 500 MHz,
6031          * enable otherwise.
6032          */
6033         if (cdclk >= 500000)
6034                 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
6035         I915_WRITE(CDCLK_CTL, val);
6036
6037         mutex_lock(&dev_priv->rps.hw_lock);
6038         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
6039                                       DIV_ROUND_UP(cdclk, 25000));
6040         mutex_unlock(&dev_priv->rps.hw_lock);
6041
6042         if (ret) {
6043                 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
6044                           ret, cdclk);
6045                 return;
6046         }
6047
6048         intel_update_cdclk(dev_priv);
6049 }
6050
6051 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
6052 {
6053         u32 cdctl, expected;
6054
6055         intel_update_cdclk(dev_priv);
6056
6057         if (dev_priv->cdclk_pll.vco == 0 ||
6058             dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
6059                 goto sanitize;
6060
6061         /* DPLL okay; verify the cdclock
6062          *
6063          * Some BIOS versions leave an incorrect decimal frequency value and
6064          * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
6065          * so sanitize this register.
6066          */
6067         cdctl = I915_READ(CDCLK_CTL);
6068         /*
6069          * Let's ignore the pipe field, since BIOS could have configured the
6070          * dividers both synching to an active pipe, or asynchronously
6071          * (PIPE_NONE).
6072          */
6073         cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
6074
6075         expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
6076                    skl_cdclk_decimal(dev_priv->cdclk_freq);
6077         /*
6078          * Disable SSA Precharge when CD clock frequency < 500 MHz,
6079          * enable otherwise.
6080          */
6081         if (dev_priv->cdclk_freq >= 500000)
6082                 expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
6083
6084         if (cdctl == expected)
6085                 /* All well; nothing to sanitize */
6086                 return;
6087
6088 sanitize:
6089         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
6090
6091         /* force cdclk programming */
6092         dev_priv->cdclk_freq = 0;
6093
6094         /* force full PLL disable + enable */
6095         dev_priv->cdclk_pll.vco = -1;
6096 }
6097
6098 void bxt_init_cdclk(struct drm_i915_private *dev_priv)
6099 {
6100         int cdclk;
6101
6102         bxt_sanitize_cdclk(dev_priv);
6103
6104         if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0)
6105                 return;
6106
6107         /*
6108          * FIXME:
6109          * - The initial CDCLK needs to be read from VBT.
6110          *   Need to make this change after VBT has changes for BXT.
6111          */
6112         if (IS_GEMINILAKE(dev_priv))
6113                 cdclk = glk_calc_cdclk(0);
6114         else
6115                 cdclk = bxt_calc_cdclk(0);
6116
6117         bxt_set_cdclk(dev_priv, cdclk);
6118 }
6119
6120 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
6121 {
6122         bxt_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref);
6123 }
6124
6125 static int skl_calc_cdclk(int max_pixclk, int vco)
6126 {
6127         if (vco == 8640000) {
6128                 if (max_pixclk > 540000)
6129                         return 617143;
6130                 else if (max_pixclk > 432000)
6131                         return 540000;
6132                 else if (max_pixclk > 308571)
6133                         return 432000;
6134                 else
6135                         return 308571;
6136         } else {
6137                 if (max_pixclk > 540000)
6138                         return 675000;
6139                 else if (max_pixclk > 450000)
6140                         return 540000;
6141                 else if (max_pixclk > 337500)
6142                         return 450000;
6143                 else
6144                         return 337500;
6145         }
6146 }
6147
6148 static void
6149 skl_dpll0_update(struct drm_i915_private *dev_priv)
6150 {
6151         u32 val;
6152
6153         dev_priv->cdclk_pll.ref = 24000;
6154         dev_priv->cdclk_pll.vco = 0;
6155
6156         val = I915_READ(LCPLL1_CTL);
6157         if ((val & LCPLL_PLL_ENABLE) == 0)
6158                 return;
6159
6160         if (WARN_ON((val & LCPLL_PLL_LOCK) == 0))
6161                 return;
6162
6163         val = I915_READ(DPLL_CTRL1);
6164
6165         if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
6166                             DPLL_CTRL1_SSC(SKL_DPLL0) |
6167                             DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
6168                     DPLL_CTRL1_OVERRIDE(SKL_DPLL0)))
6169                 return;
6170
6171         switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
6172         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
6173         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
6174         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
6175         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
6176                 dev_priv->cdclk_pll.vco = 8100000;
6177                 break;
6178         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
6179         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
6180                 dev_priv->cdclk_pll.vco = 8640000;
6181                 break;
6182         default:
6183                 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
6184                 break;
6185         }
6186 }
6187
6188 void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco)
6189 {
6190         bool changed = dev_priv->skl_preferred_vco_freq != vco;
6191
6192         dev_priv->skl_preferred_vco_freq = vco;
6193
6194         if (changed)
6195                 intel_update_max_cdclk(dev_priv);
6196 }
6197
6198 static void
6199 skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
6200 {
6201         int min_cdclk = skl_calc_cdclk(0, vco);
6202         u32 val;
6203
6204         WARN_ON(vco != 8100000 && vco != 8640000);
6205
6206         /* select the minimum CDCLK before enabling DPLL 0 */
6207         val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk);
6208         I915_WRITE(CDCLK_CTL, val);
6209         POSTING_READ(CDCLK_CTL);
6210
6211         /*
6212          * We always enable DPLL0 with the lowest link rate possible, but still
6213          * taking into account the VCO required to operate the eDP panel at the
6214          * desired frequency. The usual DP link rates operate with a VCO of
6215          * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
6216          * The modeset code is responsible for the selection of the exact link
6217          * rate later on, with the constraint of choosing a frequency that
6218          * works with vco.
6219          */
6220         val = I915_READ(DPLL_CTRL1);
6221
6222         val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
6223                  DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
6224         val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
6225         if (vco == 8640000)
6226                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
6227                                             SKL_DPLL0);
6228         else
6229                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
6230                                             SKL_DPLL0);
6231
6232         I915_WRITE(DPLL_CTRL1, val);
6233         POSTING_READ(DPLL_CTRL1);
6234
6235         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
6236
6237         if (intel_wait_for_register(dev_priv,
6238                                     LCPLL1_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
6239                                     5))
6240                 DRM_ERROR("DPLL0 not locked\n");
6241
6242         dev_priv->cdclk_pll.vco = vco;
6243
6244         /* We'll want to keep using the current vco from now on. */
6245         skl_set_preferred_cdclk_vco(dev_priv, vco);
6246 }
6247
6248 static void
6249 skl_dpll0_disable(struct drm_i915_private *dev_priv)
6250 {
6251         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
6252         if (intel_wait_for_register(dev_priv,
6253                                    LCPLL1_CTL, LCPLL_PLL_LOCK, 0,
6254                                    1))
6255                 DRM_ERROR("Couldn't disable DPLL0\n");
6256
6257         dev_priv->cdclk_pll.vco = 0;
6258 }
6259
6260 static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco)
6261 {
6262         u32 freq_select, pcu_ack;
6263         int ret;
6264
6265         WARN_ON((cdclk == 24000) != (vco == 0));
6266
6267         DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
6268
6269         mutex_lock(&dev_priv->rps.hw_lock);
6270         ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
6271                                 SKL_CDCLK_PREPARE_FOR_CHANGE,
6272                                 SKL_CDCLK_READY_FOR_CHANGE,
6273                                 SKL_CDCLK_READY_FOR_CHANGE, 3);
6274         mutex_unlock(&dev_priv->rps.hw_lock);
6275         if (ret) {
6276                 DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
6277                           ret);
6278                 return;
6279         }
6280
6281         /* set CDCLK_CTL */
6282         switch (cdclk) {
6283         case 450000:
6284         case 432000:
6285                 freq_select = CDCLK_FREQ_450_432;
6286                 pcu_ack = 1;
6287                 break;
6288         case 540000:
6289                 freq_select = CDCLK_FREQ_540;
6290                 pcu_ack = 2;
6291                 break;
6292         case 308571:
6293         case 337500:
6294         default:
6295                 freq_select = CDCLK_FREQ_337_308;
6296                 pcu_ack = 0;
6297                 break;
6298         case 617143:
6299         case 675000:
6300                 freq_select = CDCLK_FREQ_675_617;
6301                 pcu_ack = 3;
6302                 break;
6303         }
6304
6305         if (dev_priv->cdclk_pll.vco != 0 &&
6306             dev_priv->cdclk_pll.vco != vco)
6307                 skl_dpll0_disable(dev_priv);
6308
6309         if (dev_priv->cdclk_pll.vco != vco)
6310                 skl_dpll0_enable(dev_priv, vco);
6311
6312         I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk));
6313         POSTING_READ(CDCLK_CTL);
6314
6315         /* inform PCU of the change */
6316         mutex_lock(&dev_priv->rps.hw_lock);
6317         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
6318         mutex_unlock(&dev_priv->rps.hw_lock);
6319
6320         intel_update_cdclk(dev_priv);
6321 }
6322
6323 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
6324
6325 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
6326 {
6327         skl_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref, 0);
6328 }
6329
6330 void skl_init_cdclk(struct drm_i915_private *dev_priv)
6331 {
6332         int cdclk, vco;
6333
6334         skl_sanitize_cdclk(dev_priv);
6335
6336         if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0) {
6337                 /*
6338                  * Use the current vco as our initial
6339                  * guess as to what the preferred vco is.
6340                  */
6341                 if (dev_priv->skl_preferred_vco_freq == 0)
6342                         skl_set_preferred_cdclk_vco(dev_priv,
6343                                                     dev_priv->cdclk_pll.vco);
6344                 return;
6345         }
6346
6347         vco = dev_priv->skl_preferred_vco_freq;
6348         if (vco == 0)
6349                 vco = 8100000;
6350         cdclk = skl_calc_cdclk(0, vco);
6351
6352         skl_set_cdclk(dev_priv, cdclk, vco);
6353 }
6354
6355 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
6356 {
6357         uint32_t cdctl, expected;
6358
6359         /*
6360          * check if the pre-os intialized the display
6361          * There is SWF18 scratchpad register defined which is set by the
6362          * pre-os which can be used by the OS drivers to check the status
6363          */
6364         if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
6365                 goto sanitize;
6366
6367         intel_update_cdclk(dev_priv);
6368         /* Is PLL enabled and locked ? */
6369         if (dev_priv->cdclk_pll.vco == 0 ||
6370             dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
6371                 goto sanitize;
6372
6373         /* DPLL okay; verify the cdclock
6374          *
6375          * Noticed in some instances that the freq selection is correct but
6376          * decimal part is programmed wrong from BIOS where pre-os does not
6377          * enable display. Verify the same as well.
6378          */
6379         cdctl = I915_READ(CDCLK_CTL);
6380         expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
6381                 skl_cdclk_decimal(dev_priv->cdclk_freq);
6382         if (cdctl == expected)
6383                 /* All well; nothing to sanitize */
6384                 return;
6385
6386 sanitize:
6387         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
6388
6389         /* force cdclk programming */
6390         dev_priv->cdclk_freq = 0;
6391         /* force full PLL disable + enable */
6392         dev_priv->cdclk_pll.vco = -1;
6393 }
6394
6395 /* Adjust CDclk dividers to allow high res or save power if possible */
6396 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
6397 {
6398         struct drm_i915_private *dev_priv = to_i915(dev);
6399         u32 val, cmd;
6400
6401         WARN_ON(dev_priv->display.get_display_clock_speed(dev_priv)
6402                                         != dev_priv->cdclk_freq);
6403
6404         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
6405                 cmd = 2;
6406         else if (cdclk == 266667)
6407                 cmd = 1;
6408         else
6409                 cmd = 0;
6410
6411         mutex_lock(&dev_priv->rps.hw_lock);
6412         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
6413         val &= ~DSPFREQGUAR_MASK;
6414         val |= (cmd << DSPFREQGUAR_SHIFT);
6415         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
6416         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
6417                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
6418                      50)) {
6419                 DRM_ERROR("timed out waiting for CDclk change\n");
6420         }
6421         mutex_unlock(&dev_priv->rps.hw_lock);
6422
6423         mutex_lock(&dev_priv->sb_lock);
6424
6425         if (cdclk == 400000) {
6426                 u32 divider;
6427
6428                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
6429
6430                 /* adjust cdclk divider */
6431                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6432                 val &= ~CCK_FREQUENCY_VALUES;
6433                 val |= divider;
6434                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
6435
6436                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
6437                               CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
6438                              50))
6439                         DRM_ERROR("timed out waiting for CDclk change\n");
6440         }
6441
6442         /* adjust self-refresh exit latency value */
6443         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
6444         val &= ~0x7f;
6445
6446         /*
6447          * For high bandwidth configs, we set a higher latency in the bunit
6448          * so that the core display fetch happens in time to avoid underruns.
6449          */
6450         if (cdclk == 400000)
6451                 val |= 4500 / 250; /* 4.5 usec */
6452         else
6453                 val |= 3000 / 250; /* 3.0 usec */
6454         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
6455
6456         mutex_unlock(&dev_priv->sb_lock);
6457
6458         intel_update_cdclk(dev_priv);
6459 }
6460
6461 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
6462 {
6463         struct drm_i915_private *dev_priv = to_i915(dev);
6464         u32 val, cmd;
6465
6466         WARN_ON(dev_priv->display.get_display_clock_speed(dev_priv)
6467                                                 != dev_priv->cdclk_freq);
6468
6469         switch (cdclk) {
6470         case 333333:
6471         case 320000:
6472         case 266667:
6473         case 200000:
6474                 break;
6475         default:
6476                 MISSING_CASE(cdclk);
6477                 return;
6478         }
6479
6480         /*
6481          * Specs are full of misinformation, but testing on actual
6482          * hardware has shown that we just need to write the desired
6483          * CCK divider into the Punit register.
6484          */
6485         cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
6486
6487         mutex_lock(&dev_priv->rps.hw_lock);
6488         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
6489         val &= ~DSPFREQGUAR_MASK_CHV;
6490         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
6491         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
6492         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
6493                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
6494                      50)) {
6495                 DRM_ERROR("timed out waiting for CDclk change\n");
6496         }
6497         mutex_unlock(&dev_priv->rps.hw_lock);
6498
6499         intel_update_cdclk(dev_priv);
6500 }
6501
6502 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
6503                                  int max_pixclk)
6504 {
6505         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
6506         int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
6507
6508         /*
6509          * Really only a few cases to deal with, as only 4 CDclks are supported:
6510          *   200MHz
6511          *   267MHz
6512          *   320/333MHz (depends on HPLL freq)
6513          *   400MHz (VLV only)
6514          * So we check to see whether we're above 90% (VLV) or 95% (CHV)
6515          * of the lower bin and adjust if needed.
6516          *
6517          * We seem to get an unstable or solid color picture at 200MHz.
6518          * Not sure what's wrong. For now use 200MHz only when all pipes
6519          * are off.
6520          */
6521         if (!IS_CHERRYVIEW(dev_priv) &&
6522             max_pixclk > freq_320*limit/100)
6523                 return 400000;
6524         else if (max_pixclk > 266667*limit/100)
6525                 return freq_320;
6526         else if (max_pixclk > 0)
6527                 return 266667;
6528         else
6529                 return 200000;
6530 }
6531
6532 static int glk_calc_cdclk(int max_pixclk)
6533 {
6534         if (max_pixclk > 2 * 158400)
6535                 return 316800;
6536         else if (max_pixclk > 2 * 79200)
6537                 return 158400;
6538         else
6539                 return 79200;
6540 }
6541
6542 static int bxt_calc_cdclk(int max_pixclk)
6543 {
6544         if (max_pixclk > 576000)
6545                 return 624000;
6546         else if (max_pixclk > 384000)
6547                 return 576000;
6548         else if (max_pixclk > 288000)
6549                 return 384000;
6550         else if (max_pixclk > 144000)
6551                 return 288000;
6552         else
6553                 return 144000;
6554 }
6555
6556 /* Compute the max pixel clock for new configuration. */
6557 static int intel_mode_max_pixclk(struct drm_device *dev,
6558                                  struct drm_atomic_state *state)
6559 {
6560         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
6561         struct drm_i915_private *dev_priv = to_i915(dev);
6562         struct drm_crtc *crtc;
6563         struct drm_crtc_state *crtc_state;
6564         unsigned max_pixclk = 0, i;
6565         enum pipe pipe;
6566
6567         memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
6568                sizeof(intel_state->min_pixclk));
6569
6570         for_each_crtc_in_state(state, crtc, crtc_state, i) {
6571                 int pixclk = 0;
6572
6573                 if (crtc_state->enable)
6574                         pixclk = crtc_state->adjusted_mode.crtc_clock;
6575
6576                 intel_state->min_pixclk[i] = pixclk;
6577         }
6578
6579         for_each_pipe(dev_priv, pipe)
6580                 max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk);
6581
6582         return max_pixclk;
6583 }
6584
6585 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
6586 {
6587         struct drm_device *dev = state->dev;
6588         struct drm_i915_private *dev_priv = to_i915(dev);
6589         int max_pixclk = intel_mode_max_pixclk(dev, state);
6590         struct intel_atomic_state *intel_state =
6591                 to_intel_atomic_state(state);
6592
6593         intel_state->cdclk = intel_state->dev_cdclk =
6594                 valleyview_calc_cdclk(dev_priv, max_pixclk);
6595
6596         if (!intel_state->active_crtcs)
6597                 intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0);
6598
6599         return 0;
6600 }
6601
6602 static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
6603 {
6604         struct drm_i915_private *dev_priv = to_i915(state->dev);
6605         int max_pixclk = ilk_max_pixel_rate(state);
6606         struct intel_atomic_state *intel_state =
6607                 to_intel_atomic_state(state);
6608         int cdclk;
6609
6610         if (IS_GEMINILAKE(dev_priv))
6611                 cdclk = glk_calc_cdclk(max_pixclk);
6612         else
6613                 cdclk = bxt_calc_cdclk(max_pixclk);
6614
6615         intel_state->cdclk = intel_state->dev_cdclk = cdclk;
6616
6617         if (!intel_state->active_crtcs) {
6618                 if (IS_GEMINILAKE(dev_priv))
6619                         cdclk = glk_calc_cdclk(0);
6620                 else
6621                         cdclk = bxt_calc_cdclk(0);
6622
6623                 intel_state->dev_cdclk = cdclk;
6624         }
6625
6626         return 0;
6627 }
6628
6629 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6630 {
6631         unsigned int credits, default_credits;
6632
6633         if (IS_CHERRYVIEW(dev_priv))
6634                 default_credits = PFI_CREDIT(12);
6635         else
6636                 default_credits = PFI_CREDIT(8);
6637
6638         if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
6639                 /* CHV suggested value is 31 or 63 */
6640                 if (IS_CHERRYVIEW(dev_priv))
6641                         credits = PFI_CREDIT_63;
6642                 else
6643                         credits = PFI_CREDIT(15);
6644         } else {
6645                 credits = default_credits;
6646         }
6647
6648         /*
6649          * WA - write default credits before re-programming
6650          * FIXME: should we also set the resend bit here?
6651          */
6652         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6653                    default_credits);
6654
6655         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6656                    credits | PFI_CREDIT_RESEND);
6657
6658         /*
6659          * FIXME is this guaranteed to clear
6660          * immediately or should we poll for it?
6661          */
6662         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6663 }
6664
6665 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6666 {
6667         struct drm_device *dev = old_state->dev;
6668         struct drm_i915_private *dev_priv = to_i915(dev);
6669         struct intel_atomic_state *old_intel_state =
6670                 to_intel_atomic_state(old_state);
6671         unsigned req_cdclk = old_intel_state->dev_cdclk;
6672
6673         /*
6674          * FIXME: We can end up here with all power domains off, yet
6675          * with a CDCLK frequency other than the minimum. To account
6676          * for this take the PIPE-A power domain, which covers the HW
6677          * blocks needed for the following programming. This can be
6678          * removed once it's guaranteed that we get here either with
6679          * the minimum CDCLK set, or the required power domains
6680          * enabled.
6681          */
6682         intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6683
6684         if (IS_CHERRYVIEW(dev_priv))
6685                 cherryview_set_cdclk(dev, req_cdclk);
6686         else
6687                 valleyview_set_cdclk(dev, req_cdclk);
6688
6689         vlv_program_pfi_credits(dev_priv);
6690
6691         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6692 }
6693
6694 static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
6695                                    struct drm_atomic_state *old_state)
6696 {
6697         struct drm_crtc *crtc = pipe_config->base.crtc;
6698         struct drm_device *dev = crtc->dev;
6699         struct drm_i915_private *dev_priv = to_i915(dev);
6700         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6701         int pipe = intel_crtc->pipe;
6702
6703         if (WARN_ON(intel_crtc->active))
6704                 return;
6705
6706         if (intel_crtc_has_dp_encoder(intel_crtc->config))
6707                 intel_dp_set_m_n(intel_crtc, M1_N1);
6708
6709         intel_set_pipe_timings(intel_crtc);
6710         intel_set_pipe_src_size(intel_crtc);
6711
6712         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
6713                 struct drm_i915_private *dev_priv = to_i915(dev);
6714
6715                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6716                 I915_WRITE(CHV_CANVAS(pipe), 0);
6717         }
6718
6719         i9xx_set_pipeconf(intel_crtc);
6720
6721         intel_crtc->active = true;
6722
6723         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6724
6725         intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
6726
6727         if (IS_CHERRYVIEW(dev_priv)) {
6728                 chv_prepare_pll(intel_crtc, intel_crtc->config);
6729                 chv_enable_pll(intel_crtc, intel_crtc->config);
6730         } else {
6731                 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6732                 vlv_enable_pll(intel_crtc, intel_crtc->config);
6733         }
6734
6735         intel_encoders_pre_enable(crtc, pipe_config, old_state);
6736
6737         i9xx_pfit_enable(intel_crtc);
6738
6739         intel_color_load_luts(&pipe_config->base);
6740
6741         intel_update_watermarks(intel_crtc);
6742         intel_enable_pipe(intel_crtc);
6743
6744         assert_vblank_disabled(crtc);
6745         drm_crtc_vblank_on(crtc);
6746
6747         intel_encoders_enable(crtc, pipe_config, old_state);
6748 }
6749
6750 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6751 {
6752         struct drm_device *dev = crtc->base.dev;
6753         struct drm_i915_private *dev_priv = to_i915(dev);
6754
6755         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6756         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6757 }
6758
6759 static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
6760                              struct drm_atomic_state *old_state)
6761 {
6762         struct drm_crtc *crtc = pipe_config->base.crtc;
6763         struct drm_device *dev = crtc->dev;
6764         struct drm_i915_private *dev_priv = to_i915(dev);
6765         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6766         enum pipe pipe = intel_crtc->pipe;
6767
6768         if (WARN_ON(intel_crtc->active))
6769                 return;
6770
6771         i9xx_set_pll_dividers(intel_crtc);
6772
6773         if (intel_crtc_has_dp_encoder(intel_crtc->config))
6774                 intel_dp_set_m_n(intel_crtc, M1_N1);
6775
6776         intel_set_pipe_timings(intel_crtc);
6777         intel_set_pipe_src_size(intel_crtc);
6778
6779         i9xx_set_pipeconf(intel_crtc);
6780
6781         intel_crtc->active = true;
6782
6783         if (!IS_GEN2(dev_priv))
6784                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6785
6786         intel_encoders_pre_enable(crtc, pipe_config, old_state);
6787
6788         i9xx_enable_pll(intel_crtc);
6789
6790         i9xx_pfit_enable(intel_crtc);
6791
6792         intel_color_load_luts(&pipe_config->base);
6793
6794         intel_update_watermarks(intel_crtc);
6795         intel_enable_pipe(intel_crtc);
6796
6797         assert_vblank_disabled(crtc);
6798         drm_crtc_vblank_on(crtc);
6799
6800         intel_encoders_enable(crtc, pipe_config, old_state);
6801 }
6802
6803 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6804 {
6805         struct drm_device *dev = crtc->base.dev;
6806         struct drm_i915_private *dev_priv = to_i915(dev);
6807
6808         if (!crtc->config->gmch_pfit.control)
6809                 return;
6810
6811         assert_pipe_disabled(dev_priv, crtc->pipe);
6812
6813         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6814                          I915_READ(PFIT_CONTROL));
6815         I915_WRITE(PFIT_CONTROL, 0);
6816 }
6817
6818 static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
6819                               struct drm_atomic_state *old_state)
6820 {
6821         struct drm_crtc *crtc = old_crtc_state->base.crtc;
6822         struct drm_device *dev = crtc->dev;
6823         struct drm_i915_private *dev_priv = to_i915(dev);
6824         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6825         int pipe = intel_crtc->pipe;
6826
6827         /*
6828          * On gen2 planes are double buffered but the pipe isn't, so we must
6829          * wait for planes to fully turn off before disabling the pipe.
6830          */
6831         if (IS_GEN2(dev_priv))
6832                 intel_wait_for_vblank(dev_priv, pipe);
6833
6834         intel_encoders_disable(crtc, old_crtc_state, old_state);
6835
6836         drm_crtc_vblank_off(crtc);
6837         assert_vblank_disabled(crtc);
6838
6839         intel_disable_pipe(intel_crtc);
6840
6841         i9xx_pfit_disable(intel_crtc);
6842
6843         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
6844
6845         if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) {
6846                 if (IS_CHERRYVIEW(dev_priv))
6847                         chv_disable_pll(dev_priv, pipe);
6848                 else if (IS_VALLEYVIEW(dev_priv))
6849                         vlv_disable_pll(dev_priv, pipe);
6850                 else
6851                         i9xx_disable_pll(intel_crtc);
6852         }
6853
6854         intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
6855
6856         if (!IS_GEN2(dev_priv))
6857                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6858 }
6859
6860 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6861 {
6862         struct intel_encoder *encoder;
6863         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6864         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6865         enum intel_display_power_domain domain;
6866         unsigned long domains;
6867         struct drm_atomic_state *state;
6868         struct intel_crtc_state *crtc_state;
6869         int ret;
6870
6871         if (!intel_crtc->active)
6872                 return;
6873
6874         if (crtc->primary->state->visible) {
6875                 WARN_ON(intel_crtc->flip_work);
6876
6877                 intel_pre_disable_primary_noatomic(crtc);
6878
6879                 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
6880                 crtc->primary->state->visible = false;
6881         }
6882
6883         state = drm_atomic_state_alloc(crtc->dev);
6884         state->acquire_ctx = crtc->dev->mode_config.acquire_ctx;
6885
6886         /* Everything's already locked, -EDEADLK can't happen. */
6887         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
6888         ret = drm_atomic_add_affected_connectors(state, crtc);
6889
6890         WARN_ON(IS_ERR(crtc_state) || ret);
6891
6892         dev_priv->display.crtc_disable(crtc_state, state);
6893
6894         drm_atomic_state_put(state);
6895
6896         DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
6897                       crtc->base.id, crtc->name);
6898
6899         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
6900         crtc->state->active = false;
6901         intel_crtc->active = false;
6902         crtc->enabled = false;
6903         crtc->state->connector_mask = 0;
6904         crtc->state->encoder_mask = 0;
6905
6906         for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
6907                 encoder->base.crtc = NULL;
6908
6909         intel_fbc_disable(intel_crtc);
6910         intel_update_watermarks(intel_crtc);
6911         intel_disable_shared_dpll(intel_crtc);
6912
6913         domains = intel_crtc->enabled_power_domains;
6914         for_each_power_domain(domain, domains)
6915                 intel_display_power_put(dev_priv, domain);
6916         intel_crtc->enabled_power_domains = 0;
6917
6918         dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6919         dev_priv->min_pixclk[intel_crtc->pipe] = 0;
6920 }
6921
6922 /*
6923  * turn all crtc's off, but do not adjust state
6924  * This has to be paired with a call to intel_modeset_setup_hw_state.
6925  */
6926 int intel_display_suspend(struct drm_device *dev)
6927 {
6928         struct drm_i915_private *dev_priv = to_i915(dev);
6929         struct drm_atomic_state *state;
6930         int ret;
6931
6932         state = drm_atomic_helper_suspend(dev);
6933         ret = PTR_ERR_OR_ZERO(state);
6934         if (ret)
6935                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6936         else
6937                 dev_priv->modeset_restore_state = state;
6938         return ret;
6939 }
6940
6941 void intel_encoder_destroy(struct drm_encoder *encoder)
6942 {
6943         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6944
6945         drm_encoder_cleanup(encoder);
6946         kfree(intel_encoder);
6947 }
6948
6949 /* Cross check the actual hw state with our own modeset state tracking (and it's
6950  * internal consistency). */
6951 static void intel_connector_verify_state(struct intel_connector *connector)
6952 {
6953         struct drm_crtc *crtc = connector->base.state->crtc;
6954
6955         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6956                       connector->base.base.id,
6957                       connector->base.name);
6958
6959         if (connector->get_hw_state(connector)) {
6960                 struct intel_encoder *encoder = connector->encoder;
6961                 struct drm_connector_state *conn_state = connector->base.state;
6962
6963                 I915_STATE_WARN(!crtc,
6964                          "connector enabled without attached crtc\n");
6965
6966                 if (!crtc)
6967                         return;
6968
6969                 I915_STATE_WARN(!crtc->state->active,
6970                       "connector is active, but attached crtc isn't\n");
6971
6972                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6973                         return;
6974
6975                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6976                         "atomic encoder doesn't match attached encoder\n");
6977
6978                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6979                         "attached encoder crtc differs from connector crtc\n");
6980         } else {
6981                 I915_STATE_WARN(crtc && crtc->state->active,
6982                         "attached crtc is active, but connector isn't\n");
6983                 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6984                         "best encoder set without crtc!\n");
6985         }
6986 }
6987
6988 int intel_connector_init(struct intel_connector *connector)
6989 {
6990         drm_atomic_helper_connector_reset(&connector->base);
6991
6992         if (!connector->base.state)
6993                 return -ENOMEM;
6994
6995         return 0;
6996 }
6997
6998 struct intel_connector *intel_connector_alloc(void)
6999 {
7000         struct intel_connector *connector;
7001
7002         connector = kzalloc(sizeof *connector, GFP_KERNEL);
7003         if (!connector)
7004                 return NULL;
7005
7006         if (intel_connector_init(connector) < 0) {
7007                 kfree(connector);
7008                 return NULL;
7009         }
7010
7011         return connector;
7012 }
7013
7014 /* Simple connector->get_hw_state implementation for encoders that support only
7015  * one connector and no cloning and hence the encoder state determines the state
7016  * of the connector. */
7017 bool intel_connector_get_hw_state(struct intel_connector *connector)
7018 {
7019         enum pipe pipe = 0;
7020         struct intel_encoder *encoder = connector->encoder;
7021
7022         return encoder->get_hw_state(encoder, &pipe);
7023 }
7024
7025 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
7026 {
7027         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
7028                 return crtc_state->fdi_lanes;
7029
7030         return 0;
7031 }
7032
7033 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
7034                                      struct intel_crtc_state *pipe_config)
7035 {
7036         struct drm_i915_private *dev_priv = to_i915(dev);
7037         struct drm_atomic_state *state = pipe_config->base.state;
7038         struct intel_crtc *other_crtc;
7039         struct intel_crtc_state *other_crtc_state;
7040
7041         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
7042                       pipe_name(pipe), pipe_config->fdi_lanes);
7043         if (pipe_config->fdi_lanes > 4) {
7044                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
7045                               pipe_name(pipe), pipe_config->fdi_lanes);
7046                 return -EINVAL;
7047         }
7048
7049         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
7050                 if (pipe_config->fdi_lanes > 2) {
7051                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
7052                                       pipe_config->fdi_lanes);
7053                         return -EINVAL;
7054                 } else {
7055                         return 0;
7056                 }
7057         }
7058
7059         if (INTEL_INFO(dev_priv)->num_pipes == 2)
7060                 return 0;
7061
7062         /* Ivybridge 3 pipe is really complicated */
7063         switch (pipe) {
7064         case PIPE_A:
7065                 return 0;
7066         case PIPE_B:
7067                 if (pipe_config->fdi_lanes <= 2)
7068                         return 0;
7069
7070                 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C);
7071                 other_crtc_state =
7072                         intel_atomic_get_crtc_state(state, other_crtc);
7073                 if (IS_ERR(other_crtc_state))
7074                         return PTR_ERR(other_crtc_state);
7075
7076                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
7077                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
7078                                       pipe_name(pipe), pipe_config->fdi_lanes);
7079                         return -EINVAL;
7080                 }
7081                 return 0;
7082         case PIPE_C:
7083                 if (pipe_config->fdi_lanes > 2) {
7084                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
7085                                       pipe_name(pipe), pipe_config->fdi_lanes);
7086                         return -EINVAL;
7087                 }
7088
7089                 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B);
7090                 other_crtc_state =
7091                         intel_atomic_get_crtc_state(state, other_crtc);
7092                 if (IS_ERR(other_crtc_state))
7093                         return PTR_ERR(other_crtc_state);
7094
7095                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
7096                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
7097                         return -EINVAL;
7098                 }
7099                 return 0;
7100         default:
7101                 BUG();
7102         }
7103 }
7104
7105 #define RETRY 1
7106 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
7107                                        struct intel_crtc_state *pipe_config)
7108 {
7109         struct drm_device *dev = intel_crtc->base.dev;
7110         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
7111         int lane, link_bw, fdi_dotclock, ret;
7112         bool needs_recompute = false;
7113
7114 retry:
7115         /* FDI is a binary signal running at ~2.7GHz, encoding
7116          * each output octet as 10 bits. The actual frequency
7117          * is stored as a divider into a 100MHz clock, and the
7118          * mode pixel clock is stored in units of 1KHz.
7119          * Hence the bw of each lane in terms of the mode signal
7120          * is:
7121          */
7122         link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
7123
7124         fdi_dotclock = adjusted_mode->crtc_clock;
7125
7126         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
7127                                            pipe_config->pipe_bpp);
7128
7129         pipe_config->fdi_lanes = lane;
7130
7131         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
7132                                link_bw, &pipe_config->fdi_m_n);
7133
7134         ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
7135         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
7136                 pipe_config->pipe_bpp -= 2*3;
7137                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
7138                               pipe_config->pipe_bpp);
7139                 needs_recompute = true;
7140                 pipe_config->bw_constrained = true;
7141
7142                 goto retry;
7143         }
7144
7145         if (needs_recompute)
7146                 return RETRY;
7147
7148         return ret;
7149 }
7150
7151 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
7152                                      struct intel_crtc_state *pipe_config)
7153 {
7154         if (pipe_config->pipe_bpp > 24)
7155                 return false;
7156
7157         /* HSW can handle pixel rate up to cdclk? */
7158         if (IS_HASWELL(dev_priv))
7159                 return true;
7160
7161         /*
7162          * We compare against max which means we must take
7163          * the increased cdclk requirement into account when
7164          * calculating the new cdclk.
7165          *
7166          * Should measure whether using a lower cdclk w/o IPS
7167          */
7168         return ilk_pipe_pixel_rate(pipe_config) <=
7169                 dev_priv->max_cdclk_freq * 95 / 100;
7170 }
7171
7172 static void hsw_compute_ips_config(struct intel_crtc *crtc,
7173                                    struct intel_crtc_state *pipe_config)
7174 {
7175         struct drm_device *dev = crtc->base.dev;
7176         struct drm_i915_private *dev_priv = to_i915(dev);
7177
7178         pipe_config->ips_enabled = i915.enable_ips &&
7179                 hsw_crtc_supports_ips(crtc) &&
7180                 pipe_config_supports_ips(dev_priv, pipe_config);
7181 }
7182
7183 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
7184 {
7185         const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7186
7187         /* GDG double wide on either pipe, otherwise pipe A only */
7188         return INTEL_INFO(dev_priv)->gen < 4 &&
7189                 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
7190 }
7191
7192 static int intel_crtc_compute_config(struct intel_crtc *crtc,
7193                                      struct intel_crtc_state *pipe_config)
7194 {
7195         struct drm_device *dev = crtc->base.dev;
7196         struct drm_i915_private *dev_priv = to_i915(dev);
7197         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
7198         int clock_limit = dev_priv->max_dotclk_freq;
7199
7200         if (INTEL_GEN(dev_priv) < 4) {
7201                 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
7202
7203                 /*
7204                  * Enable double wide mode when the dot clock
7205                  * is > 90% of the (display) core speed.
7206                  */
7207                 if (intel_crtc_supports_double_wide(crtc) &&
7208                     adjusted_mode->crtc_clock > clock_limit) {
7209                         clock_limit = dev_priv->max_dotclk_freq;
7210                         pipe_config->double_wide = true;
7211                 }
7212         }
7213
7214         if (adjusted_mode->crtc_clock > clock_limit) {
7215                 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
7216                               adjusted_mode->crtc_clock, clock_limit,
7217                               yesno(pipe_config->double_wide));
7218                 return -EINVAL;
7219         }
7220
7221         /*
7222          * Pipe horizontal size must be even in:
7223          * - DVO ganged mode
7224          * - LVDS dual channel mode
7225          * - Double wide pipe
7226          */
7227         if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
7228              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
7229                 pipe_config->pipe_src_w &= ~1;
7230
7231         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
7232          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
7233          */
7234         if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
7235                 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
7236                 return -EINVAL;
7237
7238         if (HAS_IPS(dev_priv))
7239                 hsw_compute_ips_config(crtc, pipe_config);
7240
7241         if (pipe_config->has_pch_encoder)
7242                 return ironlake_fdi_compute_config(crtc, pipe_config);
7243
7244         return 0;
7245 }
7246
7247 static int skylake_get_display_clock_speed(struct drm_i915_private *dev_priv)
7248 {
7249         u32 cdctl;
7250
7251         skl_dpll0_update(dev_priv);
7252
7253         if (dev_priv->cdclk_pll.vco == 0)
7254                 return dev_priv->cdclk_pll.ref;
7255
7256         cdctl = I915_READ(CDCLK_CTL);
7257
7258         if (dev_priv->cdclk_pll.vco == 8640000) {
7259                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
7260                 case CDCLK_FREQ_450_432:
7261                         return 432000;
7262                 case CDCLK_FREQ_337_308:
7263                         return 308571;
7264                 case CDCLK_FREQ_540:
7265                         return 540000;
7266                 case CDCLK_FREQ_675_617:
7267                         return 617143;
7268                 default:
7269                         MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
7270                 }
7271         } else {
7272                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
7273                 case CDCLK_FREQ_450_432:
7274                         return 450000;
7275                 case CDCLK_FREQ_337_308:
7276                         return 337500;
7277                 case CDCLK_FREQ_540:
7278                         return 540000;
7279                 case CDCLK_FREQ_675_617:
7280                         return 675000;
7281                 default:
7282                         MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
7283                 }
7284         }
7285
7286         return dev_priv->cdclk_pll.ref;
7287 }
7288
7289 static void bxt_de_pll_update(struct drm_i915_private *dev_priv)
7290 {
7291         u32 val;
7292
7293         dev_priv->cdclk_pll.ref = 19200;
7294         dev_priv->cdclk_pll.vco = 0;
7295
7296         val = I915_READ(BXT_DE_PLL_ENABLE);
7297         if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
7298                 return;
7299
7300         if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
7301                 return;
7302
7303         val = I915_READ(BXT_DE_PLL_CTL);
7304         dev_priv->cdclk_pll.vco = (val & BXT_DE_PLL_RATIO_MASK) *
7305                 dev_priv->cdclk_pll.ref;
7306 }
7307
7308 static int broxton_get_display_clock_speed(struct drm_i915_private *dev_priv)
7309 {
7310         u32 divider;
7311         int div, vco;
7312
7313         bxt_de_pll_update(dev_priv);
7314
7315         vco = dev_priv->cdclk_pll.vco;
7316         if (vco == 0)
7317                 return dev_priv->cdclk_pll.ref;
7318
7319         divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
7320
7321         switch (divider) {
7322         case BXT_CDCLK_CD2X_DIV_SEL_1:
7323                 div = 2;
7324                 break;
7325         case BXT_CDCLK_CD2X_DIV_SEL_1_5:
7326                 WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n");
7327                 div = 3;
7328                 break;
7329         case BXT_CDCLK_CD2X_DIV_SEL_2:
7330                 div = 4;
7331                 break;
7332         case BXT_CDCLK_CD2X_DIV_SEL_4:
7333                 div = 8;
7334                 break;
7335         default:
7336                 MISSING_CASE(divider);
7337                 return dev_priv->cdclk_pll.ref;
7338         }
7339
7340         return DIV_ROUND_CLOSEST(vco, div);
7341 }
7342
7343 static int broadwell_get_display_clock_speed(struct drm_i915_private *dev_priv)
7344 {
7345         uint32_t lcpll = I915_READ(LCPLL_CTL);
7346         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
7347
7348         if (lcpll & LCPLL_CD_SOURCE_FCLK)
7349                 return 800000;
7350         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
7351                 return 450000;
7352         else if (freq == LCPLL_CLK_FREQ_450)
7353                 return 450000;
7354         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
7355                 return 540000;
7356         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
7357                 return 337500;
7358         else
7359                 return 675000;
7360 }
7361
7362 static int haswell_get_display_clock_speed(struct drm_i915_private *dev_priv)
7363 {
7364         uint32_t lcpll = I915_READ(LCPLL_CTL);
7365         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
7366
7367         if (lcpll & LCPLL_CD_SOURCE_FCLK)
7368                 return 800000;
7369         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
7370                 return 450000;
7371         else if (freq == LCPLL_CLK_FREQ_450)
7372                 return 450000;
7373         else if (IS_HSW_ULT(dev_priv))
7374                 return 337500;
7375         else
7376                 return 540000;
7377 }
7378
7379 static int valleyview_get_display_clock_speed(struct drm_i915_private *dev_priv)
7380 {
7381         return vlv_get_cck_clock_hpll(dev_priv, "cdclk",
7382                                       CCK_DISPLAY_CLOCK_CONTROL);
7383 }
7384
7385 static int ilk_get_display_clock_speed(struct drm_i915_private *dev_priv)
7386 {
7387         return 450000;
7388 }
7389
7390 static int i945_get_display_clock_speed(struct drm_i915_private *dev_priv)
7391 {
7392         return 400000;
7393 }
7394
7395 static int i915_get_display_clock_speed(struct drm_i915_private *dev_priv)
7396 {
7397         return 333333;
7398 }
7399
7400 static int i9xx_misc_get_display_clock_speed(struct drm_i915_private *dev_priv)
7401 {
7402         return 200000;
7403 }
7404
7405 static int pnv_get_display_clock_speed(struct drm_i915_private *dev_priv)
7406 {
7407         struct pci_dev *pdev = dev_priv->drm.pdev;
7408         u16 gcfgc = 0;
7409
7410         pci_read_config_word(pdev, GCFGC, &gcfgc);
7411
7412         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
7413         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
7414                 return 266667;
7415         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
7416                 return 333333;
7417         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
7418                 return 444444;
7419         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
7420                 return 200000;
7421         default:
7422                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
7423         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
7424                 return 133333;
7425         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
7426                 return 166667;
7427         }
7428 }
7429
7430 static int i915gm_get_display_clock_speed(struct drm_i915_private *dev_priv)
7431 {
7432         struct pci_dev *pdev = dev_priv->drm.pdev;
7433         u16 gcfgc = 0;
7434
7435         pci_read_config_word(pdev, GCFGC, &gcfgc);
7436
7437         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
7438                 return 133333;
7439         else {
7440                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
7441                 case GC_DISPLAY_CLOCK_333_MHZ:
7442                         return 333333;
7443                 default:
7444                 case GC_DISPLAY_CLOCK_190_200_MHZ:
7445                         return 190000;
7446                 }
7447         }
7448 }
7449
7450 static int i865_get_display_clock_speed(struct drm_i915_private *dev_priv)
7451 {
7452         return 266667;
7453 }
7454
7455 static int i85x_get_display_clock_speed(struct drm_i915_private *dev_priv)
7456 {
7457         struct pci_dev *pdev = dev_priv->drm.pdev;
7458         u16 hpllcc = 0;
7459
7460         /*
7461          * 852GM/852GMV only supports 133 MHz and the HPLLCC
7462          * encoding is different :(
7463          * FIXME is this the right way to detect 852GM/852GMV?
7464          */
7465         if (pdev->revision == 0x1)
7466                 return 133333;
7467
7468         pci_bus_read_config_word(pdev->bus,
7469                                  PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
7470
7471         /* Assume that the hardware is in the high speed state.  This
7472          * should be the default.
7473          */
7474         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
7475         case GC_CLOCK_133_200:
7476         case GC_CLOCK_133_200_2:
7477         case GC_CLOCK_100_200:
7478                 return 200000;
7479         case GC_CLOCK_166_250:
7480                 return 250000;
7481         case GC_CLOCK_100_133:
7482                 return 133333;
7483         case GC_CLOCK_133_266:
7484         case GC_CLOCK_133_266_2:
7485         case GC_CLOCK_166_266:
7486                 return 266667;
7487         }
7488
7489         /* Shouldn't happen */
7490         return 0;
7491 }
7492
7493 static int i830_get_display_clock_speed(struct drm_i915_private *dev_priv)
7494 {
7495         return 133333;
7496 }
7497
7498 static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv)
7499 {
7500         static const unsigned int blb_vco[8] = {
7501                 [0] = 3200000,
7502                 [1] = 4000000,
7503                 [2] = 5333333,
7504                 [3] = 4800000,
7505                 [4] = 6400000,
7506         };
7507         static const unsigned int pnv_vco[8] = {
7508                 [0] = 3200000,
7509                 [1] = 4000000,
7510                 [2] = 5333333,
7511                 [3] = 4800000,
7512                 [4] = 2666667,
7513         };
7514         static const unsigned int cl_vco[8] = {
7515                 [0] = 3200000,
7516                 [1] = 4000000,
7517                 [2] = 5333333,
7518                 [3] = 6400000,
7519                 [4] = 3333333,
7520                 [5] = 3566667,
7521                 [6] = 4266667,
7522         };
7523         static const unsigned int elk_vco[8] = {
7524                 [0] = 3200000,
7525                 [1] = 4000000,
7526                 [2] = 5333333,
7527                 [3] = 4800000,
7528         };
7529         static const unsigned int ctg_vco[8] = {
7530                 [0] = 3200000,
7531                 [1] = 4000000,
7532                 [2] = 5333333,
7533                 [3] = 6400000,
7534                 [4] = 2666667,
7535                 [5] = 4266667,
7536         };
7537         const unsigned int *vco_table;
7538         unsigned int vco;
7539         uint8_t tmp = 0;
7540
7541         /* FIXME other chipsets? */
7542         if (IS_GM45(dev_priv))
7543                 vco_table = ctg_vco;
7544         else if (IS_G4X(dev_priv))
7545                 vco_table = elk_vco;
7546         else if (IS_I965GM(dev_priv))
7547                 vco_table = cl_vco;
7548         else if (IS_PINEVIEW(dev_priv))
7549                 vco_table = pnv_vco;
7550         else if (IS_G33(dev_priv))
7551                 vco_table = blb_vco;
7552         else
7553                 return 0;
7554
7555         tmp = I915_READ(IS_MOBILE(dev_priv) ? HPLLVCO_MOBILE : HPLLVCO);
7556
7557         vco = vco_table[tmp & 0x7];
7558         if (vco == 0)
7559                 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
7560         else
7561                 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
7562
7563         return vco;
7564 }
7565
7566 static int gm45_get_display_clock_speed(struct drm_i915_private *dev_priv)
7567 {
7568         struct pci_dev *pdev = dev_priv->drm.pdev;
7569         unsigned int cdclk_sel, vco = intel_hpll_vco(dev_priv);
7570         uint16_t tmp = 0;
7571
7572         pci_read_config_word(pdev, GCFGC, &tmp);
7573
7574         cdclk_sel = (tmp >> 12) & 0x1;
7575
7576         switch (vco) {
7577         case 2666667:
7578         case 4000000:
7579         case 5333333:
7580                 return cdclk_sel ? 333333 : 222222;
7581         case 3200000:
7582                 return cdclk_sel ? 320000 : 228571;
7583         default:
7584                 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
7585                 return 222222;
7586         }
7587 }
7588
7589 static int i965gm_get_display_clock_speed(struct drm_i915_private *dev_priv)
7590 {
7591         struct pci_dev *pdev = dev_priv->drm.pdev;
7592         static const uint8_t div_3200[] = { 16, 10,  8 };
7593         static const uint8_t div_4000[] = { 20, 12, 10 };
7594         static const uint8_t div_5333[] = { 24, 16, 14 };
7595         const uint8_t *div_table;
7596         unsigned int cdclk_sel, vco = intel_hpll_vco(dev_priv);
7597         uint16_t tmp = 0;
7598
7599         pci_read_config_word(pdev, GCFGC, &tmp);
7600
7601         cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
7602
7603         if (cdclk_sel >= ARRAY_SIZE(div_3200))
7604                 goto fail;
7605
7606         switch (vco) {
7607         case 3200000:
7608                 div_table = div_3200;
7609                 break;
7610         case 4000000:
7611                 div_table = div_4000;
7612                 break;
7613         case 5333333:
7614                 div_table = div_5333;
7615                 break;
7616         default:
7617                 goto fail;
7618         }
7619
7620         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7621
7622 fail:
7623         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
7624         return 200000;
7625 }
7626
7627 static int g33_get_display_clock_speed(struct drm_i915_private *dev_priv)
7628 {
7629         struct pci_dev *pdev = dev_priv->drm.pdev;
7630         static const uint8_t div_3200[] = { 12, 10,  8,  7, 5, 16 };
7631         static const uint8_t div_4000[] = { 14, 12, 10,  8, 6, 20 };
7632         static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7633         static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7634         const uint8_t *div_table;
7635         unsigned int cdclk_sel, vco = intel_hpll_vco(dev_priv);
7636         uint16_t tmp = 0;
7637
7638         pci_read_config_word(pdev, GCFGC, &tmp);
7639
7640         cdclk_sel = (tmp >> 4) & 0x7;
7641
7642         if (cdclk_sel >= ARRAY_SIZE(div_3200))
7643                 goto fail;
7644
7645         switch (vco) {
7646         case 3200000:
7647                 div_table = div_3200;
7648                 break;
7649         case 4000000:
7650                 div_table = div_4000;
7651                 break;
7652         case 4800000:
7653                 div_table = div_4800;
7654                 break;
7655         case 5333333:
7656                 div_table = div_5333;
7657                 break;
7658         default:
7659                 goto fail;
7660         }
7661
7662         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7663
7664 fail:
7665         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7666         return 190476;
7667 }
7668
7669 static void
7670 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7671 {
7672         while (*num > DATA_LINK_M_N_MASK ||
7673                *den > DATA_LINK_M_N_MASK) {
7674                 *num >>= 1;
7675                 *den >>= 1;
7676         }
7677 }
7678
7679 static void compute_m_n(unsigned int m, unsigned int n,
7680                         uint32_t *ret_m, uint32_t *ret_n)
7681 {
7682         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7683         *ret_m = div_u64((uint64_t) m * *ret_n, n);
7684         intel_reduce_m_n_ratio(ret_m, ret_n);
7685 }
7686
7687 void
7688 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7689                        int pixel_clock, int link_clock,
7690                        struct intel_link_m_n *m_n)
7691 {
7692         m_n->tu = 64;
7693
7694         compute_m_n(bits_per_pixel * pixel_clock,
7695                     link_clock * nlanes * 8,
7696                     &m_n->gmch_m, &m_n->gmch_n);
7697
7698         compute_m_n(pixel_clock, link_clock,
7699                     &m_n->link_m, &m_n->link_n);
7700 }
7701
7702 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7703 {
7704         if (i915.panel_use_ssc >= 0)
7705                 return i915.panel_use_ssc != 0;
7706         return dev_priv->vbt.lvds_use_ssc
7707                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7708 }
7709
7710 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7711 {
7712         return (1 << dpll->n) << 16 | dpll->m2;
7713 }
7714
7715 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7716 {
7717         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7718 }
7719
7720 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7721                                      struct intel_crtc_state *crtc_state,
7722                                      struct dpll *reduced_clock)
7723 {
7724         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7725         u32 fp, fp2 = 0;
7726
7727         if (IS_PINEVIEW(dev_priv)) {
7728                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7729                 if (reduced_clock)
7730                         fp2 = pnv_dpll_compute_fp(reduced_clock);
7731         } else {
7732                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7733                 if (reduced_clock)
7734                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
7735         }
7736
7737         crtc_state->dpll_hw_state.fp0 = fp;
7738
7739         crtc->lowfreq_avail = false;
7740         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7741             reduced_clock) {
7742                 crtc_state->dpll_hw_state.fp1 = fp2;
7743                 crtc->lowfreq_avail = true;
7744         } else {
7745                 crtc_state->dpll_hw_state.fp1 = fp;
7746         }
7747 }
7748
7749 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7750                 pipe)
7751 {
7752         u32 reg_val;
7753
7754         /*
7755          * PLLB opamp always calibrates to max value of 0x3f, force enable it
7756          * and set it to a reasonable value instead.
7757          */
7758         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7759         reg_val &= 0xffffff00;
7760         reg_val |= 0x00000030;
7761         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7762
7763         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7764         reg_val &= 0x8cffffff;
7765         reg_val = 0x8c000000;
7766         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7767
7768         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7769         reg_val &= 0xffffff00;
7770         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7771
7772         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7773         reg_val &= 0x00ffffff;
7774         reg_val |= 0xb0000000;
7775         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7776 }
7777
7778 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7779                                          struct intel_link_m_n *m_n)
7780 {
7781         struct drm_device *dev = crtc->base.dev;
7782         struct drm_i915_private *dev_priv = to_i915(dev);
7783         int pipe = crtc->pipe;
7784
7785         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7786         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7787         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7788         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7789 }
7790
7791 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7792                                          struct intel_link_m_n *m_n,
7793                                          struct intel_link_m_n *m2_n2)
7794 {
7795         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7796         int pipe = crtc->pipe;
7797         enum transcoder transcoder = crtc->config->cpu_transcoder;
7798
7799         if (INTEL_GEN(dev_priv) >= 5) {
7800                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7801                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7802                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7803                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7804                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7805                  * for gen < 8) and if DRRS is supported (to make sure the
7806                  * registers are not unnecessarily accessed).
7807                  */
7808                 if (m2_n2 && (IS_CHERRYVIEW(dev_priv) ||
7809                     INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) {
7810                         I915_WRITE(PIPE_DATA_M2(transcoder),
7811                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7812                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7813                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7814                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7815                 }
7816         } else {
7817                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7818                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7819                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7820                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7821         }
7822 }
7823
7824 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7825 {
7826         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7827
7828         if (m_n == M1_N1) {
7829                 dp_m_n = &crtc->config->dp_m_n;
7830                 dp_m2_n2 = &crtc->config->dp_m2_n2;
7831         } else if (m_n == M2_N2) {
7832
7833                 /*
7834                  * M2_N2 registers are not supported. Hence m2_n2 divider value
7835                  * needs to be programmed into M1_N1.
7836                  */
7837                 dp_m_n = &crtc->config->dp_m2_n2;
7838         } else {
7839                 DRM_ERROR("Unsupported divider value\n");
7840                 return;
7841         }
7842
7843         if (crtc->config->has_pch_encoder)
7844                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7845         else
7846                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7847 }
7848
7849 static void vlv_compute_dpll(struct intel_crtc *crtc,
7850                              struct intel_crtc_state *pipe_config)
7851 {
7852         pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
7853                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7854         if (crtc->pipe != PIPE_A)
7855                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7856
7857         /* DPLL not used with DSI, but still need the rest set up */
7858         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
7859                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
7860                         DPLL_EXT_BUFFER_ENABLE_VLV;
7861
7862         pipe_config->dpll_hw_state.dpll_md =
7863                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7864 }
7865
7866 static void chv_compute_dpll(struct intel_crtc *crtc,
7867                              struct intel_crtc_state *pipe_config)
7868 {
7869         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7870                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7871         if (crtc->pipe != PIPE_A)
7872                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7873
7874         /* DPLL not used with DSI, but still need the rest set up */
7875         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
7876                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
7877
7878         pipe_config->dpll_hw_state.dpll_md =
7879                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7880 }
7881
7882 static void vlv_prepare_pll(struct intel_crtc *crtc,
7883                             const struct intel_crtc_state *pipe_config)
7884 {
7885         struct drm_device *dev = crtc->base.dev;
7886         struct drm_i915_private *dev_priv = to_i915(dev);
7887         enum pipe pipe = crtc->pipe;
7888         u32 mdiv;
7889         u32 bestn, bestm1, bestm2, bestp1, bestp2;
7890         u32 coreclk, reg_val;
7891
7892         /* Enable Refclk */
7893         I915_WRITE(DPLL(pipe),
7894                    pipe_config->dpll_hw_state.dpll &
7895                    ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
7896
7897         /* No need to actually set up the DPLL with DSI */
7898         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7899                 return;
7900
7901         mutex_lock(&dev_priv->sb_lock);
7902
7903         bestn = pipe_config->dpll.n;
7904         bestm1 = pipe_config->dpll.m1;
7905         bestm2 = pipe_config->dpll.m2;
7906         bestp1 = pipe_config->dpll.p1;
7907         bestp2 = pipe_config->dpll.p2;
7908
7909         /* See eDP HDMI DPIO driver vbios notes doc */
7910
7911         /* PLL B needs special handling */
7912         if (pipe == PIPE_B)
7913                 vlv_pllb_recal_opamp(dev_priv, pipe);
7914
7915         /* Set up Tx target for periodic Rcomp update */
7916         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7917
7918         /* Disable target IRef on PLL */
7919         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7920         reg_val &= 0x00ffffff;
7921         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7922
7923         /* Disable fast lock */
7924         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7925
7926         /* Set idtafcrecal before PLL is enabled */
7927         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7928         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7929         mdiv |= ((bestn << DPIO_N_SHIFT));
7930         mdiv |= (1 << DPIO_K_SHIFT);
7931
7932         /*
7933          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7934          * but we don't support that).
7935          * Note: don't use the DAC post divider as it seems unstable.
7936          */
7937         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7938         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7939
7940         mdiv |= DPIO_ENABLE_CALIBRATION;
7941         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7942
7943         /* Set HBR and RBR LPF coefficients */
7944         if (pipe_config->port_clock == 162000 ||
7945             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) ||
7946             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI))
7947                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7948                                  0x009f0003);
7949         else
7950                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7951                                  0x00d0000f);
7952
7953         if (intel_crtc_has_dp_encoder(pipe_config)) {
7954                 /* Use SSC source */
7955                 if (pipe == PIPE_A)
7956                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7957                                          0x0df40000);
7958                 else
7959                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7960                                          0x0df70000);
7961         } else { /* HDMI or VGA */
7962                 /* Use bend source */
7963                 if (pipe == PIPE_A)
7964                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7965                                          0x0df70000);
7966                 else
7967                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7968                                          0x0df40000);
7969         }
7970
7971         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7972         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7973         if (intel_crtc_has_dp_encoder(crtc->config))
7974                 coreclk |= 0x01000000;
7975         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7976
7977         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7978         mutex_unlock(&dev_priv->sb_lock);
7979 }
7980
7981 static void chv_prepare_pll(struct intel_crtc *crtc,
7982                             const struct intel_crtc_state *pipe_config)
7983 {
7984         struct drm_device *dev = crtc->base.dev;
7985         struct drm_i915_private *dev_priv = to_i915(dev);
7986         enum pipe pipe = crtc->pipe;
7987         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7988         u32 loopfilter, tribuf_calcntr;
7989         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7990         u32 dpio_val;
7991         int vco;
7992
7993         /* Enable Refclk and SSC */
7994         I915_WRITE(DPLL(pipe),
7995                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7996
7997         /* No need to actually set up the DPLL with DSI */
7998         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7999                 return;
8000
8001         bestn = pipe_config->dpll.n;
8002         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
8003         bestm1 = pipe_config->dpll.m1;
8004         bestm2 = pipe_config->dpll.m2 >> 22;
8005         bestp1 = pipe_config->dpll.p1;
8006         bestp2 = pipe_config->dpll.p2;
8007         vco = pipe_config->dpll.vco;
8008         dpio_val = 0;
8009         loopfilter = 0;
8010
8011         mutex_lock(&dev_priv->sb_lock);
8012
8013         /* p1 and p2 divider */
8014         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
8015                         5 << DPIO_CHV_S1_DIV_SHIFT |
8016                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
8017                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
8018                         1 << DPIO_CHV_K_DIV_SHIFT);
8019
8020         /* Feedback post-divider - m2 */
8021         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
8022
8023         /* Feedback refclk divider - n and m1 */
8024         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
8025                         DPIO_CHV_M1_DIV_BY_2 |
8026                         1 << DPIO_CHV_N_DIV_SHIFT);
8027
8028         /* M2 fraction division */
8029         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
8030
8031         /* M2 fraction division enable */
8032         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8033         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
8034         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
8035         if (bestm2_frac)
8036                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
8037         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
8038
8039         /* Program digital lock detect threshold */
8040         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
8041         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
8042                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
8043         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
8044         if (!bestm2_frac)
8045                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
8046         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
8047
8048         /* Loop filter */
8049         if (vco == 5400000) {
8050                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
8051                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
8052                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
8053                 tribuf_calcntr = 0x9;
8054         } else if (vco <= 6200000) {
8055                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
8056                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
8057                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8058                 tribuf_calcntr = 0x9;
8059         } else if (vco <= 6480000) {
8060                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
8061                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
8062                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8063                 tribuf_calcntr = 0x8;
8064         } else {
8065                 /* Not supported. Apply the same limits as in the max case */
8066                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
8067                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
8068                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8069                 tribuf_calcntr = 0;
8070         }
8071         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
8072
8073         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
8074         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
8075         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
8076         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
8077
8078         /* AFC Recal */
8079         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
8080                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
8081                         DPIO_AFC_RECAL);
8082
8083         mutex_unlock(&dev_priv->sb_lock);
8084 }
8085
8086 /**
8087  * vlv_force_pll_on - forcibly enable just the PLL
8088  * @dev_priv: i915 private structure
8089  * @pipe: pipe PLL to enable
8090  * @dpll: PLL configuration
8091  *
8092  * Enable the PLL for @pipe using the supplied @dpll config. To be used
8093  * in cases where we need the PLL enabled even when @pipe is not going to
8094  * be enabled.
8095  */
8096 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
8097                      const struct dpll *dpll)
8098 {
8099         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
8100         struct intel_crtc_state *pipe_config;
8101
8102         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8103         if (!pipe_config)
8104                 return -ENOMEM;
8105
8106         pipe_config->base.crtc = &crtc->base;
8107         pipe_config->pixel_multiplier = 1;
8108         pipe_config->dpll = *dpll;
8109
8110         if (IS_CHERRYVIEW(dev_priv)) {
8111                 chv_compute_dpll(crtc, pipe_config);
8112                 chv_prepare_pll(crtc, pipe_config);
8113                 chv_enable_pll(crtc, pipe_config);
8114         } else {
8115                 vlv_compute_dpll(crtc, pipe_config);
8116                 vlv_prepare_pll(crtc, pipe_config);
8117                 vlv_enable_pll(crtc, pipe_config);
8118         }
8119
8120         kfree(pipe_config);
8121
8122         return 0;
8123 }
8124
8125 /**
8126  * vlv_force_pll_off - forcibly disable just the PLL
8127  * @dev_priv: i915 private structure
8128  * @pipe: pipe PLL to disable
8129  *
8130  * Disable the PLL for @pipe. To be used in cases where we need
8131  * the PLL enabled even when @pipe is not going to be enabled.
8132  */
8133 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
8134 {
8135         if (IS_CHERRYVIEW(dev_priv))
8136                 chv_disable_pll(dev_priv, pipe);
8137         else
8138                 vlv_disable_pll(dev_priv, pipe);
8139 }
8140
8141 static void i9xx_compute_dpll(struct intel_crtc *crtc,
8142                               struct intel_crtc_state *crtc_state,
8143                               struct dpll *reduced_clock)
8144 {
8145         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8146         u32 dpll;
8147         struct dpll *clock = &crtc_state->dpll;
8148
8149         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8150
8151         dpll = DPLL_VGA_MODE_DIS;
8152
8153         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8154                 dpll |= DPLLB_MODE_LVDS;
8155         else
8156                 dpll |= DPLLB_MODE_DAC_SERIAL;
8157
8158         if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
8159             IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
8160                 dpll |= (crtc_state->pixel_multiplier - 1)
8161                         << SDVO_MULTIPLIER_SHIFT_HIRES;
8162         }
8163
8164         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8165             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8166                 dpll |= DPLL_SDVO_HIGH_SPEED;
8167
8168         if (intel_crtc_has_dp_encoder(crtc_state))
8169                 dpll |= DPLL_SDVO_HIGH_SPEED;
8170
8171         /* compute bitmask from p1 value */
8172         if (IS_PINEVIEW(dev_priv))
8173                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
8174         else {
8175                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8176                 if (IS_G4X(dev_priv) && reduced_clock)
8177                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8178         }
8179         switch (clock->p2) {
8180         case 5:
8181                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8182                 break;
8183         case 7:
8184                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8185                 break;
8186         case 10:
8187                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8188                 break;
8189         case 14:
8190                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8191                 break;
8192         }
8193         if (INTEL_GEN(dev_priv) >= 4)
8194                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
8195
8196         if (crtc_state->sdvo_tv_clock)
8197                 dpll |= PLL_REF_INPUT_TVCLKINBC;
8198         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8199                  intel_panel_use_ssc(dev_priv))
8200                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8201         else
8202                 dpll |= PLL_REF_INPUT_DREFCLK;
8203
8204         dpll |= DPLL_VCO_ENABLE;
8205         crtc_state->dpll_hw_state.dpll = dpll;
8206
8207         if (INTEL_GEN(dev_priv) >= 4) {
8208                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
8209                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8210                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
8211         }
8212 }
8213
8214 static void i8xx_compute_dpll(struct intel_crtc *crtc,
8215                               struct intel_crtc_state *crtc_state,
8216                               struct dpll *reduced_clock)
8217 {
8218         struct drm_device *dev = crtc->base.dev;
8219         struct drm_i915_private *dev_priv = to_i915(dev);
8220         u32 dpll;
8221         struct dpll *clock = &crtc_state->dpll;
8222
8223         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8224
8225         dpll = DPLL_VGA_MODE_DIS;
8226
8227         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8228                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8229         } else {
8230                 if (clock->p1 == 2)
8231                         dpll |= PLL_P1_DIVIDE_BY_TWO;
8232                 else
8233                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8234                 if (clock->p2 == 4)
8235                         dpll |= PLL_P2_DIVIDE_BY_4;
8236         }
8237
8238         if (!IS_I830(dev_priv) &&
8239             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
8240                 dpll |= DPLL_DVO_2X_MODE;
8241
8242         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8243             intel_panel_use_ssc(dev_priv))
8244                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8245         else
8246                 dpll |= PLL_REF_INPUT_DREFCLK;
8247
8248         dpll |= DPLL_VCO_ENABLE;
8249         crtc_state->dpll_hw_state.dpll = dpll;
8250 }
8251
8252 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
8253 {
8254         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
8255         enum pipe pipe = intel_crtc->pipe;
8256         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8257         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
8258         uint32_t crtc_vtotal, crtc_vblank_end;
8259         int vsyncshift = 0;
8260
8261         /* We need to be careful not to changed the adjusted mode, for otherwise
8262          * the hw state checker will get angry at the mismatch. */
8263         crtc_vtotal = adjusted_mode->crtc_vtotal;
8264         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
8265
8266         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
8267                 /* the chip adds 2 halflines automatically */
8268                 crtc_vtotal -= 1;
8269                 crtc_vblank_end -= 1;
8270
8271                 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
8272                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
8273                 else
8274                         vsyncshift = adjusted_mode->crtc_hsync_start -
8275                                 adjusted_mode->crtc_htotal / 2;
8276                 if (vsyncshift < 0)
8277                         vsyncshift += adjusted_mode->crtc_htotal;
8278         }
8279
8280         if (INTEL_GEN(dev_priv) > 3)
8281                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
8282
8283         I915_WRITE(HTOTAL(cpu_transcoder),
8284                    (adjusted_mode->crtc_hdisplay - 1) |
8285                    ((adjusted_mode->crtc_htotal - 1) << 16));
8286         I915_WRITE(HBLANK(cpu_transcoder),
8287                    (adjusted_mode->crtc_hblank_start - 1) |
8288                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
8289         I915_WRITE(HSYNC(cpu_transcoder),
8290                    (adjusted_mode->crtc_hsync_start - 1) |
8291                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
8292
8293         I915_WRITE(VTOTAL(cpu_transcoder),
8294                    (adjusted_mode->crtc_vdisplay - 1) |
8295                    ((crtc_vtotal - 1) << 16));
8296         I915_WRITE(VBLANK(cpu_transcoder),
8297                    (adjusted_mode->crtc_vblank_start - 1) |
8298                    ((crtc_vblank_end - 1) << 16));
8299         I915_WRITE(VSYNC(cpu_transcoder),
8300                    (adjusted_mode->crtc_vsync_start - 1) |
8301                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
8302
8303         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
8304          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
8305          * documented on the DDI_FUNC_CTL register description, EDP Input Select
8306          * bits. */
8307         if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
8308             (pipe == PIPE_B || pipe == PIPE_C))
8309                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
8310
8311 }
8312
8313 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
8314 {
8315         struct drm_device *dev = intel_crtc->base.dev;
8316         struct drm_i915_private *dev_priv = to_i915(dev);
8317         enum pipe pipe = intel_crtc->pipe;
8318
8319         /* pipesrc controls the size that is scaled from, which should
8320          * always be the user's requested size.
8321          */
8322         I915_WRITE(PIPESRC(pipe),
8323                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
8324                    (intel_crtc->config->pipe_src_h - 1));
8325 }
8326
8327 static void intel_get_pipe_timings(struct intel_crtc *crtc,
8328                                    struct intel_crtc_state *pipe_config)
8329 {
8330         struct drm_device *dev = crtc->base.dev;
8331         struct drm_i915_private *dev_priv = to_i915(dev);
8332         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
8333         uint32_t tmp;
8334
8335         tmp = I915_READ(HTOTAL(cpu_transcoder));
8336         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
8337         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
8338         tmp = I915_READ(HBLANK(cpu_transcoder));
8339         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
8340         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
8341         tmp = I915_READ(HSYNC(cpu_transcoder));
8342         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
8343         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
8344
8345         tmp = I915_READ(VTOTAL(cpu_transcoder));
8346         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
8347         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
8348         tmp = I915_READ(VBLANK(cpu_transcoder));
8349         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
8350         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
8351         tmp = I915_READ(VSYNC(cpu_transcoder));
8352         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
8353         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
8354
8355         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
8356                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
8357                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
8358                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
8359         }
8360 }
8361
8362 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
8363                                     struct intel_crtc_state *pipe_config)
8364 {
8365         struct drm_device *dev = crtc->base.dev;
8366         struct drm_i915_private *dev_priv = to_i915(dev);
8367         u32 tmp;
8368
8369         tmp = I915_READ(PIPESRC(crtc->pipe));
8370         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
8371         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
8372
8373         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
8374         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
8375 }
8376
8377 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
8378                                  struct intel_crtc_state *pipe_config)
8379 {
8380         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
8381         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
8382         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
8383         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
8384
8385         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
8386         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
8387         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
8388         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
8389
8390         mode->flags = pipe_config->base.adjusted_mode.flags;
8391         mode->type = DRM_MODE_TYPE_DRIVER;
8392
8393         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
8394         mode->flags |= pipe_config->base.adjusted_mode.flags;
8395
8396         mode->hsync = drm_mode_hsync(mode);
8397         mode->vrefresh = drm_mode_vrefresh(mode);
8398         drm_mode_set_name(mode);
8399 }
8400
8401 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
8402 {
8403         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
8404         uint32_t pipeconf;
8405
8406         pipeconf = 0;
8407
8408         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
8409             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
8410                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
8411
8412         if (intel_crtc->config->double_wide)
8413                 pipeconf |= PIPECONF_DOUBLE_WIDE;
8414
8415         /* only g4x and later have fancy bpc/dither controls */
8416         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
8417             IS_CHERRYVIEW(dev_priv)) {
8418                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
8419                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
8420                         pipeconf |= PIPECONF_DITHER_EN |
8421                                     PIPECONF_DITHER_TYPE_SP;
8422
8423                 switch (intel_crtc->config->pipe_bpp) {
8424                 case 18:
8425                         pipeconf |= PIPECONF_6BPC;
8426                         break;
8427                 case 24:
8428                         pipeconf |= PIPECONF_8BPC;
8429                         break;
8430                 case 30:
8431                         pipeconf |= PIPECONF_10BPC;
8432                         break;
8433                 default:
8434                         /* Case prevented by intel_choose_pipe_bpp_dither. */
8435                         BUG();
8436                 }
8437         }
8438
8439         if (HAS_PIPE_CXSR(dev_priv)) {
8440                 if (intel_crtc->lowfreq_avail) {
8441                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
8442                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
8443                 } else {
8444                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
8445                 }
8446         }
8447
8448         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
8449                 if (INTEL_GEN(dev_priv) < 4 ||
8450                     intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
8451                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
8452                 else
8453                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
8454         } else
8455                 pipeconf |= PIPECONF_PROGRESSIVE;
8456
8457         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
8458              intel_crtc->config->limited_color_range)
8459                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
8460
8461         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
8462         POSTING_READ(PIPECONF(intel_crtc->pipe));
8463 }
8464
8465 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
8466                                    struct intel_crtc_state *crtc_state)
8467 {
8468         struct drm_device *dev = crtc->base.dev;
8469         struct drm_i915_private *dev_priv = to_i915(dev);
8470         const struct intel_limit *limit;
8471         int refclk = 48000;
8472
8473         memset(&crtc_state->dpll_hw_state, 0,
8474                sizeof(crtc_state->dpll_hw_state));
8475
8476         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8477                 if (intel_panel_use_ssc(dev_priv)) {
8478                         refclk = dev_priv->vbt.lvds_ssc_freq;
8479                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8480                 }
8481
8482                 limit = &intel_limits_i8xx_lvds;
8483         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
8484                 limit = &intel_limits_i8xx_dvo;
8485         } else {
8486                 limit = &intel_limits_i8xx_dac;
8487         }
8488
8489         if (!crtc_state->clock_set &&
8490             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8491                                  refclk, NULL, &crtc_state->dpll)) {
8492                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8493                 return -EINVAL;
8494         }
8495
8496         i8xx_compute_dpll(crtc, crtc_state, NULL);
8497
8498         return 0;
8499 }
8500
8501 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
8502                                   struct intel_crtc_state *crtc_state)
8503 {
8504         struct drm_device *dev = crtc->base.dev;
8505         struct drm_i915_private *dev_priv = to_i915(dev);
8506         const struct intel_limit *limit;
8507         int refclk = 96000;
8508
8509         memset(&crtc_state->dpll_hw_state, 0,
8510                sizeof(crtc_state->dpll_hw_state));
8511
8512         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8513                 if (intel_panel_use_ssc(dev_priv)) {
8514                         refclk = dev_priv->vbt.lvds_ssc_freq;
8515                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8516                 }
8517
8518                 if (intel_is_dual_link_lvds(dev))
8519                         limit = &intel_limits_g4x_dual_channel_lvds;
8520                 else
8521                         limit = &intel_limits_g4x_single_channel_lvds;
8522         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
8523                    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
8524                 limit = &intel_limits_g4x_hdmi;
8525         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
8526                 limit = &intel_limits_g4x_sdvo;
8527         } else {
8528                 /* The option is for other outputs */
8529                 limit = &intel_limits_i9xx_sdvo;
8530         }
8531
8532         if (!crtc_state->clock_set &&
8533             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8534                                 refclk, NULL, &crtc_state->dpll)) {
8535                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8536                 return -EINVAL;
8537         }
8538
8539         i9xx_compute_dpll(crtc, crtc_state, NULL);
8540
8541         return 0;
8542 }
8543
8544 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
8545                                   struct intel_crtc_state *crtc_state)
8546 {
8547         struct drm_device *dev = crtc->base.dev;
8548         struct drm_i915_private *dev_priv = to_i915(dev);
8549         const struct intel_limit *limit;
8550         int refclk = 96000;
8551
8552         memset(&crtc_state->dpll_hw_state, 0,
8553                sizeof(crtc_state->dpll_hw_state));
8554
8555         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8556                 if (intel_panel_use_ssc(dev_priv)) {
8557                         refclk = dev_priv->vbt.lvds_ssc_freq;
8558                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8559                 }
8560
8561                 limit = &intel_limits_pineview_lvds;
8562         } else {
8563                 limit = &intel_limits_pineview_sdvo;
8564         }
8565
8566         if (!crtc_state->clock_set &&
8567             !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8568                                 refclk, NULL, &crtc_state->dpll)) {
8569                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8570                 return -EINVAL;
8571         }
8572
8573         i9xx_compute_dpll(crtc, crtc_state, NULL);
8574
8575         return 0;
8576 }
8577
8578 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
8579                                    struct intel_crtc_state *crtc_state)
8580 {
8581         struct drm_device *dev = crtc->base.dev;
8582         struct drm_i915_private *dev_priv = to_i915(dev);
8583         const struct intel_limit *limit;
8584         int refclk = 96000;
8585
8586         memset(&crtc_state->dpll_hw_state, 0,
8587                sizeof(crtc_state->dpll_hw_state));
8588
8589         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8590                 if (intel_panel_use_ssc(dev_priv)) {
8591                         refclk = dev_priv->vbt.lvds_ssc_freq;
8592                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8593                 }
8594
8595                 limit = &intel_limits_i9xx_lvds;
8596         } else {
8597                 limit = &intel_limits_i9xx_sdvo;
8598         }
8599
8600         if (!crtc_state->clock_set &&
8601             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8602                                  refclk, NULL, &crtc_state->dpll)) {
8603                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8604                 return -EINVAL;
8605         }
8606
8607         i9xx_compute_dpll(crtc, crtc_state, NULL);
8608
8609         return 0;
8610 }
8611
8612 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
8613                                   struct intel_crtc_state *crtc_state)
8614 {
8615         int refclk = 100000;
8616         const struct intel_limit *limit = &intel_limits_chv;
8617
8618         memset(&crtc_state->dpll_hw_state, 0,
8619                sizeof(crtc_state->dpll_hw_state));
8620
8621         if (!crtc_state->clock_set &&
8622             !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8623                                 refclk, NULL, &crtc_state->dpll)) {
8624                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8625                 return -EINVAL;
8626         }
8627
8628         chv_compute_dpll(crtc, crtc_state);
8629
8630         return 0;
8631 }
8632
8633 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
8634                                   struct intel_crtc_state *crtc_state)
8635 {
8636         int refclk = 100000;
8637         const struct intel_limit *limit = &intel_limits_vlv;
8638
8639         memset(&crtc_state->dpll_hw_state, 0,
8640                sizeof(crtc_state->dpll_hw_state));
8641
8642         if (!crtc_state->clock_set &&
8643             !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8644                                 refclk, NULL, &crtc_state->dpll)) {
8645                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8646                 return -EINVAL;
8647         }
8648
8649         vlv_compute_dpll(crtc, crtc_state);
8650
8651         return 0;
8652 }
8653
8654 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
8655                                  struct intel_crtc_state *pipe_config)
8656 {
8657         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8658         uint32_t tmp;
8659
8660         if (INTEL_GEN(dev_priv) <= 3 &&
8661             (IS_I830(dev_priv) || !IS_MOBILE(dev_priv)))
8662                 return;
8663
8664         tmp = I915_READ(PFIT_CONTROL);
8665         if (!(tmp & PFIT_ENABLE))
8666                 return;
8667
8668         /* Check whether the pfit is attached to our pipe. */
8669         if (INTEL_GEN(dev_priv) < 4) {
8670                 if (crtc->pipe != PIPE_B)
8671                         return;
8672         } else {
8673                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
8674                         return;
8675         }
8676
8677         pipe_config->gmch_pfit.control = tmp;
8678         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
8679 }
8680
8681 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8682                                struct intel_crtc_state *pipe_config)
8683 {
8684         struct drm_device *dev = crtc->base.dev;
8685         struct drm_i915_private *dev_priv = to_i915(dev);
8686         int pipe = pipe_config->cpu_transcoder;
8687         struct dpll clock;
8688         u32 mdiv;
8689         int refclk = 100000;
8690
8691         /* In case of DSI, DPLL will not be used */
8692         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8693                 return;
8694
8695         mutex_lock(&dev_priv->sb_lock);
8696         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8697         mutex_unlock(&dev_priv->sb_lock);
8698
8699         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8700         clock.m2 = mdiv & DPIO_M2DIV_MASK;
8701         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8702         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8703         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8704
8705         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8706 }
8707
8708 static void
8709 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8710                               struct intel_initial_plane_config *plane_config)
8711 {
8712         struct drm_device *dev = crtc->base.dev;
8713         struct drm_i915_private *dev_priv = to_i915(dev);
8714         u32 val, base, offset;
8715         int pipe = crtc->pipe, plane = crtc->plane;
8716         int fourcc, pixel_format;
8717         unsigned int aligned_height;
8718         struct drm_framebuffer *fb;
8719         struct intel_framebuffer *intel_fb;
8720
8721         val = I915_READ(DSPCNTR(plane));
8722         if (!(val & DISPLAY_PLANE_ENABLE))
8723                 return;
8724
8725         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8726         if (!intel_fb) {
8727                 DRM_DEBUG_KMS("failed to alloc fb\n");
8728                 return;
8729         }
8730
8731         fb = &intel_fb->base;
8732
8733         fb->dev = dev;
8734
8735         if (INTEL_GEN(dev_priv) >= 4) {
8736                 if (val & DISPPLANE_TILED) {
8737                         plane_config->tiling = I915_TILING_X;
8738                         fb->modifier = I915_FORMAT_MOD_X_TILED;
8739                 }
8740         }
8741
8742         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8743         fourcc = i9xx_format_to_fourcc(pixel_format);
8744         fb->format = drm_format_info(fourcc);
8745
8746         if (INTEL_GEN(dev_priv) >= 4) {
8747                 if (plane_config->tiling)
8748                         offset = I915_READ(DSPTILEOFF(plane));
8749                 else
8750                         offset = I915_READ(DSPLINOFF(plane));
8751                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8752         } else {
8753                 base = I915_READ(DSPADDR(plane));
8754         }
8755         plane_config->base = base;
8756
8757         val = I915_READ(PIPESRC(pipe));
8758         fb->width = ((val >> 16) & 0xfff) + 1;
8759         fb->height = ((val >> 0) & 0xfff) + 1;
8760
8761         val = I915_READ(DSPSTRIDE(pipe));
8762         fb->pitches[0] = val & 0xffffffc0;
8763
8764         aligned_height = intel_fb_align_height(dev, fb->height,
8765                                                fb->format->format,
8766                                                fb->modifier);
8767
8768         plane_config->size = fb->pitches[0] * aligned_height;
8769
8770         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8771                       pipe_name(pipe), plane, fb->width, fb->height,
8772                       fb->format->cpp[0] * 8, base, fb->pitches[0],
8773                       plane_config->size);
8774
8775         plane_config->fb = intel_fb;
8776 }
8777
8778 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8779                                struct intel_crtc_state *pipe_config)
8780 {
8781         struct drm_device *dev = crtc->base.dev;
8782         struct drm_i915_private *dev_priv = to_i915(dev);
8783         int pipe = pipe_config->cpu_transcoder;
8784         enum dpio_channel port = vlv_pipe_to_channel(pipe);
8785         struct dpll clock;
8786         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8787         int refclk = 100000;
8788
8789         /* In case of DSI, DPLL will not be used */
8790         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8791                 return;
8792
8793         mutex_lock(&dev_priv->sb_lock);
8794         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8795         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8796         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8797         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8798         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8799         mutex_unlock(&dev_priv->sb_lock);
8800
8801         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8802         clock.m2 = (pll_dw0 & 0xff) << 22;
8803         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8804                 clock.m2 |= pll_dw2 & 0x3fffff;
8805         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8806         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8807         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8808
8809         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8810 }
8811
8812 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8813                                  struct intel_crtc_state *pipe_config)
8814 {
8815         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8816         enum intel_display_power_domain power_domain;
8817         uint32_t tmp;
8818         bool ret;
8819
8820         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8821         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8822                 return false;
8823
8824         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8825         pipe_config->shared_dpll = NULL;
8826
8827         ret = false;
8828
8829         tmp = I915_READ(PIPECONF(crtc->pipe));
8830         if (!(tmp & PIPECONF_ENABLE))
8831                 goto out;
8832
8833         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
8834             IS_CHERRYVIEW(dev_priv)) {
8835                 switch (tmp & PIPECONF_BPC_MASK) {
8836                 case PIPECONF_6BPC:
8837                         pipe_config->pipe_bpp = 18;
8838                         break;
8839                 case PIPECONF_8BPC:
8840                         pipe_config->pipe_bpp = 24;
8841                         break;
8842                 case PIPECONF_10BPC:
8843                         pipe_config->pipe_bpp = 30;
8844                         break;
8845                 default:
8846                         break;
8847                 }
8848         }
8849
8850         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
8851             (tmp & PIPECONF_COLOR_RANGE_SELECT))
8852                 pipe_config->limited_color_range = true;
8853
8854         if (INTEL_GEN(dev_priv) < 4)
8855                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8856
8857         intel_get_pipe_timings(crtc, pipe_config);
8858         intel_get_pipe_src_size(crtc, pipe_config);
8859
8860         i9xx_get_pfit_config(crtc, pipe_config);
8861
8862         if (INTEL_GEN(dev_priv) >= 4) {
8863                 /* No way to read it out on pipes B and C */
8864                 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
8865                         tmp = dev_priv->chv_dpll_md[crtc->pipe];
8866                 else
8867                         tmp = I915_READ(DPLL_MD(crtc->pipe));
8868                 pipe_config->pixel_multiplier =
8869                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8870                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8871                 pipe_config->dpll_hw_state.dpll_md = tmp;
8872         } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
8873                    IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
8874                 tmp = I915_READ(DPLL(crtc->pipe));
8875                 pipe_config->pixel_multiplier =
8876                         ((tmp & SDVO_MULTIPLIER_MASK)
8877                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8878         } else {
8879                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8880                  * port and will be fixed up in the encoder->get_config
8881                  * function. */
8882                 pipe_config->pixel_multiplier = 1;
8883         }
8884         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8885         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
8886                 /*
8887                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8888                  * on 830. Filter it out here so that we don't
8889                  * report errors due to that.
8890                  */
8891                 if (IS_I830(dev_priv))
8892                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8893
8894                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8895                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8896         } else {
8897                 /* Mask out read-only status bits. */
8898                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8899                                                      DPLL_PORTC_READY_MASK |
8900                                                      DPLL_PORTB_READY_MASK);
8901         }
8902
8903         if (IS_CHERRYVIEW(dev_priv))
8904                 chv_crtc_clock_get(crtc, pipe_config);
8905         else if (IS_VALLEYVIEW(dev_priv))
8906                 vlv_crtc_clock_get(crtc, pipe_config);
8907         else
8908                 i9xx_crtc_clock_get(crtc, pipe_config);
8909
8910         /*
8911          * Normally the dotclock is filled in by the encoder .get_config()
8912          * but in case the pipe is enabled w/o any ports we need a sane
8913          * default.
8914          */
8915         pipe_config->base.adjusted_mode.crtc_clock =
8916                 pipe_config->port_clock / pipe_config->pixel_multiplier;
8917
8918         ret = true;
8919
8920 out:
8921         intel_display_power_put(dev_priv, power_domain);
8922
8923         return ret;
8924 }
8925
8926 static void ironlake_init_pch_refclk(struct drm_i915_private *dev_priv)
8927 {
8928         struct intel_encoder *encoder;
8929         int i;
8930         u32 val, final;
8931         bool has_lvds = false;
8932         bool has_cpu_edp = false;
8933         bool has_panel = false;
8934         bool has_ck505 = false;
8935         bool can_ssc = false;
8936         bool using_ssc_source = false;
8937
8938         /* We need to take the global config into account */
8939         for_each_intel_encoder(&dev_priv->drm, encoder) {
8940                 switch (encoder->type) {
8941                 case INTEL_OUTPUT_LVDS:
8942                         has_panel = true;
8943                         has_lvds = true;
8944                         break;
8945                 case INTEL_OUTPUT_EDP:
8946                         has_panel = true;
8947                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8948                                 has_cpu_edp = true;
8949                         break;
8950                 default:
8951                         break;
8952                 }
8953         }
8954
8955         if (HAS_PCH_IBX(dev_priv)) {
8956                 has_ck505 = dev_priv->vbt.display_clock_mode;
8957                 can_ssc = has_ck505;
8958         } else {
8959                 has_ck505 = false;
8960                 can_ssc = true;
8961         }
8962
8963         /* Check if any DPLLs are using the SSC source */
8964         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8965                 u32 temp = I915_READ(PCH_DPLL(i));
8966
8967                 if (!(temp & DPLL_VCO_ENABLE))
8968                         continue;
8969
8970                 if ((temp & PLL_REF_INPUT_MASK) ==
8971                     PLLB_REF_INPUT_SPREADSPECTRUMIN) {
8972                         using_ssc_source = true;
8973                         break;
8974                 }
8975         }
8976
8977         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
8978                       has_panel, has_lvds, has_ck505, using_ssc_source);
8979
8980         /* Ironlake: try to setup display ref clock before DPLL
8981          * enabling. This is only under driver's control after
8982          * PCH B stepping, previous chipset stepping should be
8983          * ignoring this setting.
8984          */
8985         val = I915_READ(PCH_DREF_CONTROL);
8986
8987         /* As we must carefully and slowly disable/enable each source in turn,
8988          * compute the final state we want first and check if we need to
8989          * make any changes at all.
8990          */
8991         final = val;
8992         final &= ~DREF_NONSPREAD_SOURCE_MASK;
8993         if (has_ck505)
8994                 final |= DREF_NONSPREAD_CK505_ENABLE;
8995         else
8996                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8997
8998         final &= ~DREF_SSC_SOURCE_MASK;
8999         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9000         final &= ~DREF_SSC1_ENABLE;
9001
9002         if (has_panel) {
9003                 final |= DREF_SSC_SOURCE_ENABLE;
9004
9005                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
9006                         final |= DREF_SSC1_ENABLE;
9007
9008                 if (has_cpu_edp) {
9009                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
9010                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
9011                         else
9012                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
9013                 } else
9014                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9015         } else if (using_ssc_source) {
9016                 final |= DREF_SSC_SOURCE_ENABLE;
9017                 final |= DREF_SSC1_ENABLE;
9018         }
9019
9020         if (final == val)
9021                 return;
9022
9023         /* Always enable nonspread source */
9024         val &= ~DREF_NONSPREAD_SOURCE_MASK;
9025
9026         if (has_ck505)
9027                 val |= DREF_NONSPREAD_CK505_ENABLE;
9028         else
9029                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
9030
9031         if (has_panel) {
9032                 val &= ~DREF_SSC_SOURCE_MASK;
9033                 val |= DREF_SSC_SOURCE_ENABLE;
9034
9035                 /* SSC must be turned on before enabling the CPU output  */
9036                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
9037                         DRM_DEBUG_KMS("Using SSC on panel\n");
9038                         val |= DREF_SSC1_ENABLE;
9039                 } else
9040                         val &= ~DREF_SSC1_ENABLE;
9041
9042                 /* Get SSC going before enabling the outputs */
9043                 I915_WRITE(PCH_DREF_CONTROL, val);
9044                 POSTING_READ(PCH_DREF_CONTROL);
9045                 udelay(200);
9046
9047                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9048
9049                 /* Enable CPU source on CPU attached eDP */
9050                 if (has_cpu_edp) {
9051                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
9052                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
9053                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
9054                         } else
9055                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
9056                 } else
9057                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9058
9059                 I915_WRITE(PCH_DREF_CONTROL, val);
9060                 POSTING_READ(PCH_DREF_CONTROL);
9061                 udelay(200);
9062         } else {
9063                 DRM_DEBUG_KMS("Disabling CPU source output\n");
9064
9065                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9066
9067                 /* Turn off CPU output */
9068                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9069
9070                 I915_WRITE(PCH_DREF_CONTROL, val);
9071                 POSTING_READ(PCH_DREF_CONTROL);
9072                 udelay(200);
9073
9074                 if (!using_ssc_source) {
9075                         DRM_DEBUG_KMS("Disabling SSC source\n");
9076
9077                         /* Turn off the SSC source */
9078                         val &= ~DREF_SSC_SOURCE_MASK;
9079                         val |= DREF_SSC_SOURCE_DISABLE;
9080
9081                         /* Turn off SSC1 */
9082                         val &= ~DREF_SSC1_ENABLE;
9083
9084                         I915_WRITE(PCH_DREF_CONTROL, val);
9085                         POSTING_READ(PCH_DREF_CONTROL);
9086                         udelay(200);
9087                 }
9088         }
9089
9090         BUG_ON(val != final);
9091 }
9092
9093 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
9094 {
9095         uint32_t tmp;
9096
9097         tmp = I915_READ(SOUTH_CHICKEN2);
9098         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
9099         I915_WRITE(SOUTH_CHICKEN2, tmp);
9100
9101         if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
9102                         FDI_MPHY_IOSFSB_RESET_STATUS, 100))
9103                 DRM_ERROR("FDI mPHY reset assert timeout\n");
9104
9105         tmp = I915_READ(SOUTH_CHICKEN2);
9106         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
9107         I915_WRITE(SOUTH_CHICKEN2, tmp);
9108
9109         if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
9110                          FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
9111                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
9112 }
9113
9114 /* WaMPhyProgramming:hsw */
9115 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
9116 {
9117         uint32_t tmp;
9118
9119         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
9120         tmp &= ~(0xFF << 24);
9121         tmp |= (0x12 << 24);
9122         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
9123
9124         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
9125         tmp |= (1 << 11);
9126         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
9127
9128         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
9129         tmp |= (1 << 11);
9130         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
9131
9132         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
9133         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9134         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
9135
9136         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
9137         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9138         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
9139
9140         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
9141         tmp &= ~(7 << 13);
9142         tmp |= (5 << 13);
9143         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
9144
9145         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
9146         tmp &= ~(7 << 13);
9147         tmp |= (5 << 13);
9148         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
9149
9150         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
9151         tmp &= ~0xFF;
9152         tmp |= 0x1C;
9153         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
9154
9155         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
9156         tmp &= ~0xFF;
9157         tmp |= 0x1C;
9158         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
9159
9160         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
9161         tmp &= ~(0xFF << 16);
9162         tmp |= (0x1C << 16);
9163         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
9164
9165         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
9166         tmp &= ~(0xFF << 16);
9167         tmp |= (0x1C << 16);
9168         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
9169
9170         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
9171         tmp |= (1 << 27);
9172         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
9173
9174         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
9175         tmp |= (1 << 27);
9176         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
9177
9178         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
9179         tmp &= ~(0xF << 28);
9180         tmp |= (4 << 28);
9181         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
9182
9183         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
9184         tmp &= ~(0xF << 28);
9185         tmp |= (4 << 28);
9186         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
9187 }
9188
9189 /* Implements 3 different sequences from BSpec chapter "Display iCLK
9190  * Programming" based on the parameters passed:
9191  * - Sequence to enable CLKOUT_DP
9192  * - Sequence to enable CLKOUT_DP without spread
9193  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
9194  */
9195 static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
9196                                  bool with_spread, bool with_fdi)
9197 {
9198         uint32_t reg, tmp;
9199
9200         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
9201                 with_spread = true;
9202         if (WARN(HAS_PCH_LPT_LP(dev_priv) &&
9203             with_fdi, "LP PCH doesn't have FDI\n"))
9204                 with_fdi = false;
9205
9206         mutex_lock(&dev_priv->sb_lock);
9207
9208         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9209         tmp &= ~SBI_SSCCTL_DISABLE;
9210         tmp |= SBI_SSCCTL_PATHALT;
9211         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9212
9213         udelay(24);
9214
9215         if (with_spread) {
9216                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9217                 tmp &= ~SBI_SSCCTL_PATHALT;
9218                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9219
9220                 if (with_fdi) {
9221                         lpt_reset_fdi_mphy(dev_priv);
9222                         lpt_program_fdi_mphy(dev_priv);
9223                 }
9224         }
9225
9226         reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
9227         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9228         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9229         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9230
9231         mutex_unlock(&dev_priv->sb_lock);
9232 }
9233
9234 /* Sequence to disable CLKOUT_DP */
9235 static void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
9236 {
9237         uint32_t reg, tmp;
9238
9239         mutex_lock(&dev_priv->sb_lock);
9240
9241         reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
9242         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9243         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9244         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9245
9246         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9247         if (!(tmp & SBI_SSCCTL_DISABLE)) {
9248                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
9249                         tmp |= SBI_SSCCTL_PATHALT;
9250                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9251                         udelay(32);
9252                 }
9253                 tmp |= SBI_SSCCTL_DISABLE;
9254                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9255         }
9256
9257         mutex_unlock(&dev_priv->sb_lock);
9258 }
9259
9260 #define BEND_IDX(steps) ((50 + (steps)) / 5)
9261
9262 static const uint16_t sscdivintphase[] = {
9263         [BEND_IDX( 50)] = 0x3B23,
9264         [BEND_IDX( 45)] = 0x3B23,
9265         [BEND_IDX( 40)] = 0x3C23,
9266         [BEND_IDX( 35)] = 0x3C23,
9267         [BEND_IDX( 30)] = 0x3D23,
9268         [BEND_IDX( 25)] = 0x3D23,
9269         [BEND_IDX( 20)] = 0x3E23,
9270         [BEND_IDX( 15)] = 0x3E23,
9271         [BEND_IDX( 10)] = 0x3F23,
9272         [BEND_IDX(  5)] = 0x3F23,
9273         [BEND_IDX(  0)] = 0x0025,
9274         [BEND_IDX( -5)] = 0x0025,
9275         [BEND_IDX(-10)] = 0x0125,
9276         [BEND_IDX(-15)] = 0x0125,
9277         [BEND_IDX(-20)] = 0x0225,
9278         [BEND_IDX(-25)] = 0x0225,
9279         [BEND_IDX(-30)] = 0x0325,
9280         [BEND_IDX(-35)] = 0x0325,
9281         [BEND_IDX(-40)] = 0x0425,
9282         [BEND_IDX(-45)] = 0x0425,
9283         [BEND_IDX(-50)] = 0x0525,
9284 };
9285
9286 /*
9287  * Bend CLKOUT_DP
9288  * steps -50 to 50 inclusive, in steps of 5
9289  * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
9290  * change in clock period = -(steps / 10) * 5.787 ps
9291  */
9292 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
9293 {
9294         uint32_t tmp;
9295         int idx = BEND_IDX(steps);
9296
9297         if (WARN_ON(steps % 5 != 0))
9298                 return;
9299
9300         if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
9301                 return;
9302
9303         mutex_lock(&dev_priv->sb_lock);
9304
9305         if (steps % 10 != 0)
9306                 tmp = 0xAAAAAAAB;
9307         else
9308                 tmp = 0x00000000;
9309         intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
9310
9311         tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
9312         tmp &= 0xffff0000;
9313         tmp |= sscdivintphase[idx];
9314         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
9315
9316         mutex_unlock(&dev_priv->sb_lock);
9317 }
9318
9319 #undef BEND_IDX
9320
9321 static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
9322 {
9323         struct intel_encoder *encoder;
9324         bool has_vga = false;
9325
9326         for_each_intel_encoder(&dev_priv->drm, encoder) {
9327                 switch (encoder->type) {
9328                 case INTEL_OUTPUT_ANALOG:
9329                         has_vga = true;
9330                         break;
9331                 default:
9332                         break;
9333                 }
9334         }
9335
9336         if (has_vga) {
9337                 lpt_bend_clkout_dp(dev_priv, 0);
9338                 lpt_enable_clkout_dp(dev_priv, true, true);
9339         } else {
9340                 lpt_disable_clkout_dp(dev_priv);
9341         }
9342 }
9343
9344 /*
9345  * Initialize reference clocks when the driver loads
9346  */
9347 void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
9348 {
9349         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
9350                 ironlake_init_pch_refclk(dev_priv);
9351         else if (HAS_PCH_LPT(dev_priv))
9352                 lpt_init_pch_refclk(dev_priv);
9353 }
9354
9355 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
9356 {
9357         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
9358         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9359         int pipe = intel_crtc->pipe;
9360         uint32_t val;
9361
9362         val = 0;
9363
9364         switch (intel_crtc->config->pipe_bpp) {
9365         case 18:
9366                 val |= PIPECONF_6BPC;
9367                 break;
9368         case 24:
9369                 val |= PIPECONF_8BPC;
9370                 break;
9371         case 30:
9372                 val |= PIPECONF_10BPC;
9373                 break;
9374         case 36:
9375                 val |= PIPECONF_12BPC;
9376                 break;
9377         default:
9378                 /* Case prevented by intel_choose_pipe_bpp_dither. */
9379                 BUG();
9380         }
9381
9382         if (intel_crtc->config->dither)
9383                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
9384
9385         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
9386                 val |= PIPECONF_INTERLACED_ILK;
9387         else
9388                 val |= PIPECONF_PROGRESSIVE;
9389
9390         if (intel_crtc->config->limited_color_range)
9391                 val |= PIPECONF_COLOR_RANGE_SELECT;
9392
9393         I915_WRITE(PIPECONF(pipe), val);
9394         POSTING_READ(PIPECONF(pipe));
9395 }
9396
9397 static void haswell_set_pipeconf(struct drm_crtc *crtc)
9398 {
9399         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
9400         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9401         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
9402         u32 val = 0;
9403
9404         if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
9405                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
9406
9407         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
9408                 val |= PIPECONF_INTERLACED_ILK;
9409         else
9410                 val |= PIPECONF_PROGRESSIVE;
9411
9412         I915_WRITE(PIPECONF(cpu_transcoder), val);
9413         POSTING_READ(PIPECONF(cpu_transcoder));
9414 }
9415
9416 static void haswell_set_pipemisc(struct drm_crtc *crtc)
9417 {
9418         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
9419         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9420
9421         if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
9422                 u32 val = 0;
9423
9424                 switch (intel_crtc->config->pipe_bpp) {
9425                 case 18:
9426                         val |= PIPEMISC_DITHER_6_BPC;
9427                         break;
9428                 case 24:
9429                         val |= PIPEMISC_DITHER_8_BPC;
9430                         break;
9431                 case 30:
9432                         val |= PIPEMISC_DITHER_10_BPC;
9433                         break;
9434                 case 36:
9435                         val |= PIPEMISC_DITHER_12_BPC;
9436                         break;
9437                 default:
9438                         /* Case prevented by pipe_config_set_bpp. */
9439                         BUG();
9440                 }
9441
9442                 if (intel_crtc->config->dither)
9443                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
9444
9445                 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
9446         }
9447 }
9448
9449 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
9450 {
9451         /*
9452          * Account for spread spectrum to avoid
9453          * oversubscribing the link. Max center spread
9454          * is 2.5%; use 5% for safety's sake.
9455          */
9456         u32 bps = target_clock * bpp * 21 / 20;
9457         return DIV_ROUND_UP(bps, link_bw * 8);
9458 }
9459
9460 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
9461 {
9462         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
9463 }
9464
9465 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
9466                                   struct intel_crtc_state *crtc_state,
9467                                   struct dpll *reduced_clock)
9468 {
9469         struct drm_crtc *crtc = &intel_crtc->base;
9470         struct drm_device *dev = crtc->dev;
9471         struct drm_i915_private *dev_priv = to_i915(dev);
9472         u32 dpll, fp, fp2;
9473         int factor;
9474
9475         /* Enable autotuning of the PLL clock (if permissible) */
9476         factor = 21;
9477         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9478                 if ((intel_panel_use_ssc(dev_priv) &&
9479                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
9480                     (HAS_PCH_IBX(dev_priv) && intel_is_dual_link_lvds(dev)))
9481                         factor = 25;
9482         } else if (crtc_state->sdvo_tv_clock)
9483                 factor = 20;
9484
9485         fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
9486
9487         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
9488                 fp |= FP_CB_TUNE;
9489
9490         if (reduced_clock) {
9491                 fp2 = i9xx_dpll_compute_fp(reduced_clock);
9492
9493                 if (reduced_clock->m < factor * reduced_clock->n)
9494                         fp2 |= FP_CB_TUNE;
9495         } else {
9496                 fp2 = fp;
9497         }
9498
9499         dpll = 0;
9500
9501         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
9502                 dpll |= DPLLB_MODE_LVDS;
9503         else
9504                 dpll |= DPLLB_MODE_DAC_SERIAL;
9505
9506         dpll |= (crtc_state->pixel_multiplier - 1)
9507                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
9508
9509         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
9510             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
9511                 dpll |= DPLL_SDVO_HIGH_SPEED;
9512
9513         if (intel_crtc_has_dp_encoder(crtc_state))
9514                 dpll |= DPLL_SDVO_HIGH_SPEED;
9515
9516         /*
9517          * The high speed IO clock is only really required for
9518          * SDVO/HDMI/DP, but we also enable it for CRT to make it
9519          * possible to share the DPLL between CRT and HDMI. Enabling
9520          * the clock needlessly does no real harm, except use up a
9521          * bit of power potentially.
9522          *
9523          * We'll limit this to IVB with 3 pipes, since it has only two
9524          * DPLLs and so DPLL sharing is the only way to get three pipes
9525          * driving PCH ports at the same time. On SNB we could do this,
9526          * and potentially avoid enabling the second DPLL, but it's not
9527          * clear if it''s a win or loss power wise. No point in doing
9528          * this on ILK at all since it has a fixed DPLL<->pipe mapping.
9529          */
9530         if (INTEL_INFO(dev_priv)->num_pipes == 3 &&
9531             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
9532                 dpll |= DPLL_SDVO_HIGH_SPEED;
9533
9534         /* compute bitmask from p1 value */
9535         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
9536         /* also FPA1 */
9537         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
9538
9539         switch (crtc_state->dpll.p2) {
9540         case 5:
9541                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
9542                 break;
9543         case 7:
9544                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
9545                 break;
9546         case 10:
9547                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
9548                 break;
9549         case 14:
9550                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
9551                 break;
9552         }
9553
9554         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
9555             intel_panel_use_ssc(dev_priv))
9556                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
9557         else
9558                 dpll |= PLL_REF_INPUT_DREFCLK;
9559
9560         dpll |= DPLL_VCO_ENABLE;
9561
9562         crtc_state->dpll_hw_state.dpll = dpll;
9563         crtc_state->dpll_hw_state.fp0 = fp;
9564         crtc_state->dpll_hw_state.fp1 = fp2;
9565 }
9566
9567 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
9568                                        struct intel_crtc_state *crtc_state)
9569 {
9570         struct drm_device *dev = crtc->base.dev;
9571         struct drm_i915_private *dev_priv = to_i915(dev);
9572         struct dpll reduced_clock;
9573         bool has_reduced_clock = false;
9574         struct intel_shared_dpll *pll;
9575         const struct intel_limit *limit;
9576         int refclk = 120000;
9577
9578         memset(&crtc_state->dpll_hw_state, 0,
9579                sizeof(crtc_state->dpll_hw_state));
9580
9581         crtc->lowfreq_avail = false;
9582
9583         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
9584         if (!crtc_state->has_pch_encoder)
9585                 return 0;
9586
9587         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9588                 if (intel_panel_use_ssc(dev_priv)) {
9589                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
9590                                       dev_priv->vbt.lvds_ssc_freq);
9591                         refclk = dev_priv->vbt.lvds_ssc_freq;
9592                 }
9593
9594                 if (intel_is_dual_link_lvds(dev)) {
9595                         if (refclk == 100000)
9596                                 limit = &intel_limits_ironlake_dual_lvds_100m;
9597                         else
9598                                 limit = &intel_limits_ironlake_dual_lvds;
9599                 } else {
9600                         if (refclk == 100000)
9601                                 limit = &intel_limits_ironlake_single_lvds_100m;
9602                         else
9603                                 limit = &intel_limits_ironlake_single_lvds;
9604                 }
9605         } else {
9606                 limit = &intel_limits_ironlake_dac;
9607         }
9608
9609         if (!crtc_state->clock_set &&
9610             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9611                                 refclk, NULL, &crtc_state->dpll)) {
9612                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
9613                 return -EINVAL;
9614         }
9615
9616         ironlake_compute_dpll(crtc, crtc_state,
9617                               has_reduced_clock ? &reduced_clock : NULL);
9618
9619         pll = intel_get_shared_dpll(crtc, crtc_state, NULL);
9620         if (pll == NULL) {
9621                 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
9622                                  pipe_name(crtc->pipe));
9623                 return -EINVAL;
9624         }
9625
9626         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
9627             has_reduced_clock)
9628                 crtc->lowfreq_avail = true;
9629
9630         return 0;
9631 }
9632
9633 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
9634                                          struct intel_link_m_n *m_n)
9635 {
9636         struct drm_device *dev = crtc->base.dev;
9637         struct drm_i915_private *dev_priv = to_i915(dev);
9638         enum pipe pipe = crtc->pipe;
9639
9640         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
9641         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
9642         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
9643                 & ~TU_SIZE_MASK;
9644         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
9645         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
9646                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9647 }
9648
9649 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
9650                                          enum transcoder transcoder,
9651                                          struct intel_link_m_n *m_n,
9652                                          struct intel_link_m_n *m2_n2)
9653 {
9654         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9655         enum pipe pipe = crtc->pipe;
9656
9657         if (INTEL_GEN(dev_priv) >= 5) {
9658                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
9659                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
9660                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
9661                         & ~TU_SIZE_MASK;
9662                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9663                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9664                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9665                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
9666                  * gen < 8) and if DRRS is supported (to make sure the
9667                  * registers are not unnecessarily read).
9668                  */
9669                 if (m2_n2 && INTEL_GEN(dev_priv) < 8 &&
9670                         crtc->config->has_drrs) {
9671                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9672                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9673                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9674                                         & ~TU_SIZE_MASK;
9675                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9676                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9677                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9678                 }
9679         } else {
9680                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9681                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9682                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9683                         & ~TU_SIZE_MASK;
9684                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9685                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9686                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9687         }
9688 }
9689
9690 void intel_dp_get_m_n(struct intel_crtc *crtc,
9691                       struct intel_crtc_state *pipe_config)
9692 {
9693         if (pipe_config->has_pch_encoder)
9694                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9695         else
9696                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9697                                              &pipe_config->dp_m_n,
9698                                              &pipe_config->dp_m2_n2);
9699 }
9700
9701 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9702                                         struct intel_crtc_state *pipe_config)
9703 {
9704         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9705                                      &pipe_config->fdi_m_n, NULL);
9706 }
9707
9708 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9709                                     struct intel_crtc_state *pipe_config)
9710 {
9711         struct drm_device *dev = crtc->base.dev;
9712         struct drm_i915_private *dev_priv = to_i915(dev);
9713         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9714         uint32_t ps_ctrl = 0;
9715         int id = -1;
9716         int i;
9717
9718         /* find scaler attached to this pipe */
9719         for (i = 0; i < crtc->num_scalers; i++) {
9720                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9721                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9722                         id = i;
9723                         pipe_config->pch_pfit.enabled = true;
9724                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9725                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9726                         break;
9727                 }
9728         }
9729
9730         scaler_state->scaler_id = id;
9731         if (id >= 0) {
9732                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9733         } else {
9734                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9735         }
9736 }
9737
9738 static void
9739 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9740                                  struct intel_initial_plane_config *plane_config)
9741 {
9742         struct drm_device *dev = crtc->base.dev;
9743         struct drm_i915_private *dev_priv = to_i915(dev);
9744         u32 val, base, offset, stride_mult, tiling;
9745         int pipe = crtc->pipe;
9746         int fourcc, pixel_format;
9747         unsigned int aligned_height;
9748         struct drm_framebuffer *fb;
9749         struct intel_framebuffer *intel_fb;
9750
9751         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9752         if (!intel_fb) {
9753                 DRM_DEBUG_KMS("failed to alloc fb\n");
9754                 return;
9755         }
9756
9757         fb = &intel_fb->base;
9758
9759         fb->dev = dev;
9760
9761         val = I915_READ(PLANE_CTL(pipe, 0));
9762         if (!(val & PLANE_CTL_ENABLE))
9763                 goto error;
9764
9765         pixel_format = val & PLANE_CTL_FORMAT_MASK;
9766         fourcc = skl_format_to_fourcc(pixel_format,
9767                                       val & PLANE_CTL_ORDER_RGBX,
9768                                       val & PLANE_CTL_ALPHA_MASK);
9769         fb->format = drm_format_info(fourcc);
9770
9771         tiling = val & PLANE_CTL_TILED_MASK;
9772         switch (tiling) {
9773         case PLANE_CTL_TILED_LINEAR:
9774                 fb->modifier = DRM_FORMAT_MOD_NONE;
9775                 break;
9776         case PLANE_CTL_TILED_X:
9777                 plane_config->tiling = I915_TILING_X;
9778                 fb->modifier = I915_FORMAT_MOD_X_TILED;
9779                 break;
9780         case PLANE_CTL_TILED_Y:
9781                 fb->modifier = I915_FORMAT_MOD_Y_TILED;
9782                 break;
9783         case PLANE_CTL_TILED_YF:
9784                 fb->modifier = I915_FORMAT_MOD_Yf_TILED;
9785                 break;
9786         default:
9787                 MISSING_CASE(tiling);
9788                 goto error;
9789         }
9790
9791         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9792         plane_config->base = base;
9793
9794         offset = I915_READ(PLANE_OFFSET(pipe, 0));
9795
9796         val = I915_READ(PLANE_SIZE(pipe, 0));
9797         fb->height = ((val >> 16) & 0xfff) + 1;
9798         fb->width = ((val >> 0) & 0x1fff) + 1;
9799
9800         val = I915_READ(PLANE_STRIDE(pipe, 0));
9801         stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier,
9802                                                 fb->format->format);
9803         fb->pitches[0] = (val & 0x3ff) * stride_mult;
9804
9805         aligned_height = intel_fb_align_height(dev, fb->height,
9806                                                fb->format->format,
9807                                                fb->modifier);
9808
9809         plane_config->size = fb->pitches[0] * aligned_height;
9810
9811         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9812                       pipe_name(pipe), fb->width, fb->height,
9813                       fb->format->cpp[0] * 8, base, fb->pitches[0],
9814                       plane_config->size);
9815
9816         plane_config->fb = intel_fb;
9817         return;
9818
9819 error:
9820         kfree(intel_fb);
9821 }
9822
9823 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9824                                      struct intel_crtc_state *pipe_config)
9825 {
9826         struct drm_device *dev = crtc->base.dev;
9827         struct drm_i915_private *dev_priv = to_i915(dev);
9828         uint32_t tmp;
9829
9830         tmp = I915_READ(PF_CTL(crtc->pipe));
9831
9832         if (tmp & PF_ENABLE) {
9833                 pipe_config->pch_pfit.enabled = true;
9834                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9835                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9836
9837                 /* We currently do not free assignements of panel fitters on
9838                  * ivb/hsw (since we don't use the higher upscaling modes which
9839                  * differentiates them) so just WARN about this case for now. */
9840                 if (IS_GEN7(dev_priv)) {
9841                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9842                                 PF_PIPE_SEL_IVB(crtc->pipe));
9843                 }
9844         }
9845 }
9846
9847 static void
9848 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9849                                   struct intel_initial_plane_config *plane_config)
9850 {
9851         struct drm_device *dev = crtc->base.dev;
9852         struct drm_i915_private *dev_priv = to_i915(dev);
9853         u32 val, base, offset;
9854         int pipe = crtc->pipe;
9855         int fourcc, pixel_format;
9856         unsigned int aligned_height;
9857         struct drm_framebuffer *fb;
9858         struct intel_framebuffer *intel_fb;
9859
9860         val = I915_READ(DSPCNTR(pipe));
9861         if (!(val & DISPLAY_PLANE_ENABLE))
9862                 return;
9863
9864         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9865         if (!intel_fb) {
9866                 DRM_DEBUG_KMS("failed to alloc fb\n");
9867                 return;
9868         }
9869
9870         fb = &intel_fb->base;
9871
9872         fb->dev = dev;
9873
9874         if (INTEL_GEN(dev_priv) >= 4) {
9875                 if (val & DISPPLANE_TILED) {
9876                         plane_config->tiling = I915_TILING_X;
9877                         fb->modifier = I915_FORMAT_MOD_X_TILED;
9878                 }
9879         }
9880
9881         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9882         fourcc = i9xx_format_to_fourcc(pixel_format);
9883         fb->format = drm_format_info(fourcc);
9884
9885         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9886         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
9887                 offset = I915_READ(DSPOFFSET(pipe));
9888         } else {
9889                 if (plane_config->tiling)
9890                         offset = I915_READ(DSPTILEOFF(pipe));
9891                 else
9892                         offset = I915_READ(DSPLINOFF(pipe));
9893         }
9894         plane_config->base = base;
9895
9896         val = I915_READ(PIPESRC(pipe));
9897         fb->width = ((val >> 16) & 0xfff) + 1;
9898         fb->height = ((val >> 0) & 0xfff) + 1;
9899
9900         val = I915_READ(DSPSTRIDE(pipe));
9901         fb->pitches[0] = val & 0xffffffc0;
9902
9903         aligned_height = intel_fb_align_height(dev, fb->height,
9904                                                fb->format->format,
9905                                                fb->modifier);
9906
9907         plane_config->size = fb->pitches[0] * aligned_height;
9908
9909         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9910                       pipe_name(pipe), fb->width, fb->height,
9911                       fb->format->cpp[0] * 8, base, fb->pitches[0],
9912                       plane_config->size);
9913
9914         plane_config->fb = intel_fb;
9915 }
9916
9917 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9918                                      struct intel_crtc_state *pipe_config)
9919 {
9920         struct drm_device *dev = crtc->base.dev;
9921         struct drm_i915_private *dev_priv = to_i915(dev);
9922         enum intel_display_power_domain power_domain;
9923         uint32_t tmp;
9924         bool ret;
9925
9926         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9927         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9928                 return false;
9929
9930         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9931         pipe_config->shared_dpll = NULL;
9932
9933         ret = false;
9934         tmp = I915_READ(PIPECONF(crtc->pipe));
9935         if (!(tmp & PIPECONF_ENABLE))
9936                 goto out;
9937
9938         switch (tmp & PIPECONF_BPC_MASK) {
9939         case PIPECONF_6BPC:
9940                 pipe_config->pipe_bpp = 18;
9941                 break;
9942         case PIPECONF_8BPC:
9943                 pipe_config->pipe_bpp = 24;
9944                 break;
9945         case PIPECONF_10BPC:
9946                 pipe_config->pipe_bpp = 30;
9947                 break;
9948         case PIPECONF_12BPC:
9949                 pipe_config->pipe_bpp = 36;
9950                 break;
9951         default:
9952                 break;
9953         }
9954
9955         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9956                 pipe_config->limited_color_range = true;
9957
9958         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9959                 struct intel_shared_dpll *pll;
9960                 enum intel_dpll_id pll_id;
9961
9962                 pipe_config->has_pch_encoder = true;
9963
9964                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9965                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9966                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9967
9968                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9969
9970                 if (HAS_PCH_IBX(dev_priv)) {
9971                         /*
9972                          * The pipe->pch transcoder and pch transcoder->pll
9973                          * mapping is fixed.
9974                          */
9975                         pll_id = (enum intel_dpll_id) crtc->pipe;
9976                 } else {
9977                         tmp = I915_READ(PCH_DPLL_SEL);
9978                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9979                                 pll_id = DPLL_ID_PCH_PLL_B;
9980                         else
9981                                 pll_id= DPLL_ID_PCH_PLL_A;
9982                 }
9983
9984                 pipe_config->shared_dpll =
9985                         intel_get_shared_dpll_by_id(dev_priv, pll_id);
9986                 pll = pipe_config->shared_dpll;
9987
9988                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9989                                                  &pipe_config->dpll_hw_state));
9990
9991                 tmp = pipe_config->dpll_hw_state.dpll;
9992                 pipe_config->pixel_multiplier =
9993                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9994                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9995
9996                 ironlake_pch_clock_get(crtc, pipe_config);
9997         } else {
9998                 pipe_config->pixel_multiplier = 1;
9999         }
10000
10001         intel_get_pipe_timings(crtc, pipe_config);
10002         intel_get_pipe_src_size(crtc, pipe_config);
10003
10004         ironlake_get_pfit_config(crtc, pipe_config);
10005
10006         ret = true;
10007
10008 out:
10009         intel_display_power_put(dev_priv, power_domain);
10010
10011         return ret;
10012 }
10013
10014 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
10015 {
10016         struct drm_device *dev = &dev_priv->drm;
10017         struct intel_crtc *crtc;
10018
10019         for_each_intel_crtc(dev, crtc)
10020                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
10021                      pipe_name(crtc->pipe));
10022
10023         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
10024         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
10025         I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
10026         I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
10027         I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n");
10028         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
10029              "CPU PWM1 enabled\n");
10030         if (IS_HASWELL(dev_priv))
10031                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
10032                      "CPU PWM2 enabled\n");
10033         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
10034              "PCH PWM1 enabled\n");
10035         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
10036              "Utility pin enabled\n");
10037         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
10038
10039         /*
10040          * In theory we can still leave IRQs enabled, as long as only the HPD
10041          * interrupts remain enabled. We used to check for that, but since it's
10042          * gen-specific and since we only disable LCPLL after we fully disable
10043          * the interrupts, the check below should be enough.
10044          */
10045         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
10046 }
10047
10048 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
10049 {
10050         if (IS_HASWELL(dev_priv))
10051                 return I915_READ(D_COMP_HSW);
10052         else
10053                 return I915_READ(D_COMP_BDW);
10054 }
10055
10056 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
10057 {
10058         if (IS_HASWELL(dev_priv)) {
10059                 mutex_lock(&dev_priv->rps.hw_lock);
10060                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
10061                                             val))
10062                         DRM_DEBUG_KMS("Failed to write to D_COMP\n");
10063                 mutex_unlock(&dev_priv->rps.hw_lock);
10064         } else {
10065                 I915_WRITE(D_COMP_BDW, val);
10066                 POSTING_READ(D_COMP_BDW);
10067         }
10068 }
10069
10070 /*
10071  * This function implements pieces of two sequences from BSpec:
10072  * - Sequence for display software to disable LCPLL
10073  * - Sequence for display software to allow package C8+
10074  * The steps implemented here are just the steps that actually touch the LCPLL
10075  * register. Callers should take care of disabling all the display engine
10076  * functions, doing the mode unset, fixing interrupts, etc.
10077  */
10078 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
10079                               bool switch_to_fclk, bool allow_power_down)
10080 {
10081         uint32_t val;
10082
10083         assert_can_disable_lcpll(dev_priv);
10084
10085         val = I915_READ(LCPLL_CTL);
10086
10087         if (switch_to_fclk) {
10088                 val |= LCPLL_CD_SOURCE_FCLK;
10089                 I915_WRITE(LCPLL_CTL, val);
10090
10091                 if (wait_for_us(I915_READ(LCPLL_CTL) &
10092                                 LCPLL_CD_SOURCE_FCLK_DONE, 1))
10093                         DRM_ERROR("Switching to FCLK failed\n");
10094
10095                 val = I915_READ(LCPLL_CTL);
10096         }
10097
10098         val |= LCPLL_PLL_DISABLE;
10099         I915_WRITE(LCPLL_CTL, val);
10100         POSTING_READ(LCPLL_CTL);
10101
10102         if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
10103                 DRM_ERROR("LCPLL still locked\n");
10104
10105         val = hsw_read_dcomp(dev_priv);
10106         val |= D_COMP_COMP_DISABLE;
10107         hsw_write_dcomp(dev_priv, val);
10108         ndelay(100);
10109
10110         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
10111                      1))
10112                 DRM_ERROR("D_COMP RCOMP still in progress\n");
10113
10114         if (allow_power_down) {
10115                 val = I915_READ(LCPLL_CTL);
10116                 val |= LCPLL_POWER_DOWN_ALLOW;
10117                 I915_WRITE(LCPLL_CTL, val);
10118                 POSTING_READ(LCPLL_CTL);
10119         }
10120 }
10121
10122 /*
10123  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
10124  * source.
10125  */
10126 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
10127 {
10128         uint32_t val;
10129
10130         val = I915_READ(LCPLL_CTL);
10131
10132         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
10133                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
10134                 return;
10135
10136         /*
10137          * Make sure we're not on PC8 state before disabling PC8, otherwise
10138          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
10139          */
10140         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
10141
10142         if (val & LCPLL_POWER_DOWN_ALLOW) {
10143                 val &= ~LCPLL_POWER_DOWN_ALLOW;
10144                 I915_WRITE(LCPLL_CTL, val);
10145                 POSTING_READ(LCPLL_CTL);
10146         }
10147
10148         val = hsw_read_dcomp(dev_priv);
10149         val |= D_COMP_COMP_FORCE;
10150         val &= ~D_COMP_COMP_DISABLE;
10151         hsw_write_dcomp(dev_priv, val);
10152
10153         val = I915_READ(LCPLL_CTL);
10154         val &= ~LCPLL_PLL_DISABLE;
10155         I915_WRITE(LCPLL_CTL, val);
10156
10157         if (intel_wait_for_register(dev_priv,
10158                                     LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
10159                                     5))
10160                 DRM_ERROR("LCPLL not locked yet\n");
10161
10162         if (val & LCPLL_CD_SOURCE_FCLK) {
10163                 val = I915_READ(LCPLL_CTL);
10164                 val &= ~LCPLL_CD_SOURCE_FCLK;
10165                 I915_WRITE(LCPLL_CTL, val);
10166
10167                 if (wait_for_us((I915_READ(LCPLL_CTL) &
10168                                  LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
10169                         DRM_ERROR("Switching back to LCPLL failed\n");
10170         }
10171
10172         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
10173         intel_update_cdclk(dev_priv);
10174 }
10175
10176 /*
10177  * Package states C8 and deeper are really deep PC states that can only be
10178  * reached when all the devices on the system allow it, so even if the graphics
10179  * device allows PC8+, it doesn't mean the system will actually get to these
10180  * states. Our driver only allows PC8+ when going into runtime PM.
10181  *
10182  * The requirements for PC8+ are that all the outputs are disabled, the power
10183  * well is disabled and most interrupts are disabled, and these are also
10184  * requirements for runtime PM. When these conditions are met, we manually do
10185  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
10186  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
10187  * hang the machine.
10188  *
10189  * When we really reach PC8 or deeper states (not just when we allow it) we lose
10190  * the state of some registers, so when we come back from PC8+ we need to
10191  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
10192  * need to take care of the registers kept by RC6. Notice that this happens even
10193  * if we don't put the device in PCI D3 state (which is what currently happens
10194  * because of the runtime PM support).
10195  *
10196  * For more, read "Display Sequences for Package C8" on the hardware
10197  * documentation.
10198  */
10199 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
10200 {
10201         uint32_t val;
10202
10203         DRM_DEBUG_KMS("Enabling package C8+\n");
10204
10205         if (HAS_PCH_LPT_LP(dev_priv)) {
10206                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
10207                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
10208                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
10209         }
10210
10211         lpt_disable_clkout_dp(dev_priv);
10212         hsw_disable_lcpll(dev_priv, true, true);
10213 }
10214
10215 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
10216 {
10217         uint32_t val;
10218
10219         DRM_DEBUG_KMS("Disabling package C8+\n");
10220
10221         hsw_restore_lcpll(dev_priv);
10222         lpt_init_pch_refclk(dev_priv);
10223
10224         if (HAS_PCH_LPT_LP(dev_priv)) {
10225                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
10226                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
10227                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
10228         }
10229 }
10230
10231 static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state)
10232 {
10233         struct drm_device *dev = old_state->dev;
10234         struct intel_atomic_state *old_intel_state =
10235                 to_intel_atomic_state(old_state);
10236         unsigned int req_cdclk = old_intel_state->dev_cdclk;
10237
10238         bxt_set_cdclk(to_i915(dev), req_cdclk);
10239 }
10240
10241 static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state,
10242                                           int pixel_rate)
10243 {
10244         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
10245
10246         /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
10247         if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
10248                 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
10249
10250         /* BSpec says "Do not use DisplayPort with CDCLK less than
10251          * 432 MHz, audio enabled, port width x4, and link rate
10252          * HBR2 (5.4 GHz), or else there may be audio corruption or
10253          * screen corruption."
10254          */
10255         if (intel_crtc_has_dp_encoder(crtc_state) &&
10256             crtc_state->has_audio &&
10257             crtc_state->port_clock >= 540000 &&
10258             crtc_state->lane_count == 4)
10259                 pixel_rate = max(432000, pixel_rate);
10260
10261         return pixel_rate;
10262 }
10263
10264 /* compute the max rate for new configuration */
10265 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
10266 {
10267         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
10268         struct drm_i915_private *dev_priv = to_i915(state->dev);
10269         struct drm_crtc *crtc;
10270         struct drm_crtc_state *cstate;
10271         struct intel_crtc_state *crtc_state;
10272         unsigned max_pixel_rate = 0, i;
10273         enum pipe pipe;
10274
10275         memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
10276                sizeof(intel_state->min_pixclk));
10277
10278         for_each_crtc_in_state(state, crtc, cstate, i) {
10279                 int pixel_rate;
10280
10281                 crtc_state = to_intel_crtc_state(cstate);
10282                 if (!crtc_state->base.enable) {
10283                         intel_state->min_pixclk[i] = 0;
10284                         continue;
10285                 }
10286
10287                 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
10288
10289                 if (IS_BROADWELL(dev_priv) || IS_GEN9(dev_priv))
10290                         pixel_rate = bdw_adjust_min_pipe_pixel_rate(crtc_state,
10291                                                                     pixel_rate);
10292
10293                 intel_state->min_pixclk[i] = pixel_rate;
10294         }
10295
10296         for_each_pipe(dev_priv, pipe)
10297                 max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate);
10298
10299         return max_pixel_rate;
10300 }
10301
10302 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
10303 {
10304         struct drm_i915_private *dev_priv = to_i915(dev);
10305         uint32_t val, data;
10306         int ret;
10307
10308         if (WARN((I915_READ(LCPLL_CTL) &
10309                   (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
10310                    LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
10311                    LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
10312                    LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
10313                  "trying to change cdclk frequency with cdclk not enabled\n"))
10314                 return;
10315
10316         mutex_lock(&dev_priv->rps.hw_lock);
10317         ret = sandybridge_pcode_write(dev_priv,
10318                                       BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
10319         mutex_unlock(&dev_priv->rps.hw_lock);
10320         if (ret) {
10321                 DRM_ERROR("failed to inform pcode about cdclk change\n");
10322                 return;
10323         }
10324
10325         val = I915_READ(LCPLL_CTL);
10326         val |= LCPLL_CD_SOURCE_FCLK;
10327         I915_WRITE(LCPLL_CTL, val);
10328
10329         if (wait_for_us(I915_READ(LCPLL_CTL) &
10330                         LCPLL_CD_SOURCE_FCLK_DONE, 1))
10331                 DRM_ERROR("Switching to FCLK failed\n");
10332
10333         val = I915_READ(LCPLL_CTL);
10334         val &= ~LCPLL_CLK_FREQ_MASK;
10335
10336         switch (cdclk) {
10337         case 450000:
10338                 val |= LCPLL_CLK_FREQ_450;
10339                 data = 0;
10340                 break;
10341         case 540000:
10342                 val |= LCPLL_CLK_FREQ_54O_BDW;
10343                 data = 1;
10344                 break;
10345         case 337500:
10346                 val |= LCPLL_CLK_FREQ_337_5_BDW;
10347                 data = 2;
10348                 break;
10349         case 675000:
10350                 val |= LCPLL_CLK_FREQ_675_BDW;
10351                 data = 3;
10352                 break;
10353         default:
10354                 WARN(1, "invalid cdclk frequency\n");
10355                 return;
10356         }
10357
10358         I915_WRITE(LCPLL_CTL, val);
10359
10360         val = I915_READ(LCPLL_CTL);
10361         val &= ~LCPLL_CD_SOURCE_FCLK;
10362         I915_WRITE(LCPLL_CTL, val);
10363
10364         if (wait_for_us((I915_READ(LCPLL_CTL) &
10365                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
10366                 DRM_ERROR("Switching back to LCPLL failed\n");
10367
10368         mutex_lock(&dev_priv->rps.hw_lock);
10369         sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
10370         mutex_unlock(&dev_priv->rps.hw_lock);
10371
10372         I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
10373
10374         intel_update_cdclk(dev_priv);
10375
10376         WARN(cdclk != dev_priv->cdclk_freq,
10377              "cdclk requested %d kHz but got %d kHz\n",
10378              cdclk, dev_priv->cdclk_freq);
10379 }
10380
10381 static int broadwell_calc_cdclk(int max_pixclk)
10382 {
10383         if (max_pixclk > 540000)
10384                 return 675000;
10385         else if (max_pixclk > 450000)
10386                 return 540000;
10387         else if (max_pixclk > 337500)
10388                 return 450000;
10389         else
10390                 return 337500;
10391 }
10392
10393 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
10394 {
10395         struct drm_i915_private *dev_priv = to_i915(state->dev);
10396         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
10397         int max_pixclk = ilk_max_pixel_rate(state);
10398         int cdclk;
10399
10400         /*
10401          * FIXME should also account for plane ratio
10402          * once 64bpp pixel formats are supported.
10403          */
10404         cdclk = broadwell_calc_cdclk(max_pixclk);
10405
10406         if (cdclk > dev_priv->max_cdclk_freq) {
10407                 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
10408                               cdclk, dev_priv->max_cdclk_freq);
10409                 return -EINVAL;
10410         }
10411
10412         intel_state->cdclk = intel_state->dev_cdclk = cdclk;
10413         if (!intel_state->active_crtcs)
10414                 intel_state->dev_cdclk = broadwell_calc_cdclk(0);
10415
10416         return 0;
10417 }
10418
10419 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
10420 {
10421         struct drm_device *dev = old_state->dev;
10422         struct intel_atomic_state *old_intel_state =
10423                 to_intel_atomic_state(old_state);
10424         unsigned req_cdclk = old_intel_state->dev_cdclk;
10425
10426         broadwell_set_cdclk(dev, req_cdclk);
10427 }
10428
10429 static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
10430 {
10431         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
10432         struct drm_i915_private *dev_priv = to_i915(state->dev);
10433         const int max_pixclk = ilk_max_pixel_rate(state);
10434         int vco = intel_state->cdclk_pll_vco;
10435         int cdclk;
10436
10437         /*
10438          * FIXME should also account for plane ratio
10439          * once 64bpp pixel formats are supported.
10440          */
10441         cdclk = skl_calc_cdclk(max_pixclk, vco);
10442
10443         /*
10444          * FIXME move the cdclk caclulation to
10445          * compute_config() so we can fail gracegully.
10446          */
10447         if (cdclk > dev_priv->max_cdclk_freq) {
10448                 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
10449                           cdclk, dev_priv->max_cdclk_freq);
10450                 cdclk = dev_priv->max_cdclk_freq;
10451         }
10452
10453         intel_state->cdclk = intel_state->dev_cdclk = cdclk;
10454         if (!intel_state->active_crtcs)
10455                 intel_state->dev_cdclk = skl_calc_cdclk(0, vco);
10456
10457         return 0;
10458 }
10459
10460 static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state)
10461 {
10462         struct drm_i915_private *dev_priv = to_i915(old_state->dev);
10463         struct intel_atomic_state *intel_state = to_intel_atomic_state(old_state);
10464         unsigned int req_cdclk = intel_state->dev_cdclk;
10465         unsigned int req_vco = intel_state->cdclk_pll_vco;
10466
10467         skl_set_cdclk(dev_priv, req_cdclk, req_vco);
10468 }
10469
10470 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
10471                                       struct intel_crtc_state *crtc_state)
10472 {
10473         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
10474                 if (!intel_ddi_pll_select(crtc, crtc_state))
10475                         return -EINVAL;
10476         }
10477
10478         crtc->lowfreq_avail = false;
10479
10480         return 0;
10481 }
10482
10483 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
10484                                 enum port port,
10485                                 struct intel_crtc_state *pipe_config)
10486 {
10487         enum intel_dpll_id id;
10488
10489         switch (port) {
10490         case PORT_A:
10491                 id = DPLL_ID_SKL_DPLL0;
10492                 break;
10493         case PORT_B:
10494                 id = DPLL_ID_SKL_DPLL1;
10495                 break;
10496         case PORT_C:
10497                 id = DPLL_ID_SKL_DPLL2;
10498                 break;
10499         default:
10500                 DRM_ERROR("Incorrect port type\n");
10501                 return;
10502         }
10503
10504         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10505 }
10506
10507 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
10508                                 enum port port,
10509                                 struct intel_crtc_state *pipe_config)
10510 {
10511         enum intel_dpll_id id;
10512         u32 temp;
10513
10514         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
10515         id = temp >> (port * 3 + 1);
10516
10517         if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3))
10518                 return;
10519
10520         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10521 }
10522
10523 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
10524                                 enum port port,
10525                                 struct intel_crtc_state *pipe_config)
10526 {
10527         enum intel_dpll_id id;
10528         uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
10529
10530         switch (ddi_pll_sel) {
10531         case PORT_CLK_SEL_WRPLL1:
10532                 id = DPLL_ID_WRPLL1;
10533                 break;
10534         case PORT_CLK_SEL_WRPLL2:
10535                 id = DPLL_ID_WRPLL2;
10536                 break;
10537         case PORT_CLK_SEL_SPLL:
10538                 id = DPLL_ID_SPLL;
10539                 break;
10540         case PORT_CLK_SEL_LCPLL_810:
10541                 id = DPLL_ID_LCPLL_810;
10542                 break;
10543         case PORT_CLK_SEL_LCPLL_1350:
10544                 id = DPLL_ID_LCPLL_1350;
10545                 break;
10546         case PORT_CLK_SEL_LCPLL_2700:
10547                 id = DPLL_ID_LCPLL_2700;
10548                 break;
10549         default:
10550                 MISSING_CASE(ddi_pll_sel);
10551                 /* fall through */
10552         case PORT_CLK_SEL_NONE:
10553                 return;
10554         }
10555
10556         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10557 }
10558
10559 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
10560                                      struct intel_crtc_state *pipe_config,
10561                                      unsigned long *power_domain_mask)
10562 {
10563         struct drm_device *dev = crtc->base.dev;
10564         struct drm_i915_private *dev_priv = to_i915(dev);
10565         enum intel_display_power_domain power_domain;
10566         u32 tmp;
10567
10568         /*
10569          * The pipe->transcoder mapping is fixed with the exception of the eDP
10570          * transcoder handled below.
10571          */
10572         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
10573
10574         /*
10575          * XXX: Do intel_display_power_get_if_enabled before reading this (for
10576          * consistency and less surprising code; it's in always on power).
10577          */
10578         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
10579         if (tmp & TRANS_DDI_FUNC_ENABLE) {
10580                 enum pipe trans_edp_pipe;
10581                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
10582                 default:
10583                         WARN(1, "unknown pipe linked to edp transcoder\n");
10584                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
10585                 case TRANS_DDI_EDP_INPUT_A_ON:
10586                         trans_edp_pipe = PIPE_A;
10587                         break;
10588                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
10589                         trans_edp_pipe = PIPE_B;
10590                         break;
10591                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
10592                         trans_edp_pipe = PIPE_C;
10593                         break;
10594                 }
10595
10596                 if (trans_edp_pipe == crtc->pipe)
10597                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
10598         }
10599
10600         power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
10601         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10602                 return false;
10603         *power_domain_mask |= BIT(power_domain);
10604
10605         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
10606
10607         return tmp & PIPECONF_ENABLE;
10608 }
10609
10610 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
10611                                          struct intel_crtc_state *pipe_config,
10612                                          unsigned long *power_domain_mask)
10613 {
10614         struct drm_device *dev = crtc->base.dev;
10615         struct drm_i915_private *dev_priv = to_i915(dev);
10616         enum intel_display_power_domain power_domain;
10617         enum port port;
10618         enum transcoder cpu_transcoder;
10619         u32 tmp;
10620
10621         for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
10622                 if (port == PORT_A)
10623                         cpu_transcoder = TRANSCODER_DSI_A;
10624                 else
10625                         cpu_transcoder = TRANSCODER_DSI_C;
10626
10627                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
10628                 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10629                         continue;
10630                 *power_domain_mask |= BIT(power_domain);
10631
10632                 /*
10633                  * The PLL needs to be enabled with a valid divider
10634                  * configuration, otherwise accessing DSI registers will hang
10635                  * the machine. See BSpec North Display Engine
10636                  * registers/MIPI[BXT]. We can break out here early, since we
10637                  * need the same DSI PLL to be enabled for both DSI ports.
10638                  */
10639                 if (!intel_dsi_pll_is_enabled(dev_priv))
10640                         break;
10641
10642                 /* XXX: this works for video mode only */
10643                 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
10644                 if (!(tmp & DPI_ENABLE))
10645                         continue;
10646
10647                 tmp = I915_READ(MIPI_CTRL(port));
10648                 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
10649                         continue;
10650
10651                 pipe_config->cpu_transcoder = cpu_transcoder;
10652                 break;
10653         }
10654
10655         return transcoder_is_dsi(pipe_config->cpu_transcoder);
10656 }
10657
10658 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
10659                                        struct intel_crtc_state *pipe_config)
10660 {
10661         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10662         struct intel_shared_dpll *pll;
10663         enum port port;
10664         uint32_t tmp;
10665
10666         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
10667
10668         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
10669
10670         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
10671                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
10672         else if (IS_GEN9_LP(dev_priv))
10673                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
10674         else
10675                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
10676
10677         pll = pipe_config->shared_dpll;
10678         if (pll) {
10679                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
10680                                                  &pipe_config->dpll_hw_state));
10681         }
10682
10683         /*
10684          * Haswell has only FDI/PCH transcoder A. It is which is connected to
10685          * DDI E. So just check whether this pipe is wired to DDI E and whether
10686          * the PCH transcoder is on.
10687          */
10688         if (INTEL_GEN(dev_priv) < 9 &&
10689             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
10690                 pipe_config->has_pch_encoder = true;
10691
10692                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
10693                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
10694                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
10695
10696                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
10697         }
10698 }
10699
10700 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
10701                                     struct intel_crtc_state *pipe_config)
10702 {
10703         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10704         enum intel_display_power_domain power_domain;
10705         unsigned long power_domain_mask;
10706         bool active;
10707
10708         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
10709         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10710                 return false;
10711         power_domain_mask = BIT(power_domain);
10712
10713         pipe_config->shared_dpll = NULL;
10714
10715         active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
10716
10717         if (IS_GEN9_LP(dev_priv) &&
10718             bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) {
10719                 WARN_ON(active);
10720                 active = true;
10721         }
10722
10723         if (!active)
10724                 goto out;
10725
10726         if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10727                 haswell_get_ddi_port_state(crtc, pipe_config);
10728                 intel_get_pipe_timings(crtc, pipe_config);
10729         }
10730
10731         intel_get_pipe_src_size(crtc, pipe_config);
10732
10733         pipe_config->gamma_mode =
10734                 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
10735
10736         if (INTEL_GEN(dev_priv) >= 9) {
10737                 intel_crtc_init_scalers(crtc, pipe_config);
10738
10739                 pipe_config->scaler_state.scaler_id = -1;
10740                 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
10741         }
10742
10743         power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
10744         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
10745                 power_domain_mask |= BIT(power_domain);
10746                 if (INTEL_GEN(dev_priv) >= 9)
10747                         skylake_get_pfit_config(crtc, pipe_config);
10748                 else
10749                         ironlake_get_pfit_config(crtc, pipe_config);
10750         }
10751
10752         if (IS_HASWELL(dev_priv))
10753                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
10754                         (I915_READ(IPS_CTL) & IPS_ENABLE);
10755
10756         if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
10757             !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10758                 pipe_config->pixel_multiplier =
10759                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
10760         } else {
10761                 pipe_config->pixel_multiplier = 1;
10762         }
10763
10764 out:
10765         for_each_power_domain(power_domain, power_domain_mask)
10766                 intel_display_power_put(dev_priv, power_domain);
10767
10768         return active;
10769 }
10770
10771 static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
10772                                const struct intel_plane_state *plane_state)
10773 {
10774         struct drm_device *dev = crtc->dev;
10775         struct drm_i915_private *dev_priv = to_i915(dev);
10776         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10777         uint32_t cntl = 0, size = 0;
10778
10779         if (plane_state && plane_state->base.visible) {
10780                 unsigned int width = plane_state->base.crtc_w;
10781                 unsigned int height = plane_state->base.crtc_h;
10782                 unsigned int stride = roundup_pow_of_two(width) * 4;
10783
10784                 switch (stride) {
10785                 default:
10786                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10787                                   width, stride);
10788                         stride = 256;
10789                         /* fallthrough */
10790                 case 256:
10791                 case 512:
10792                 case 1024:
10793                 case 2048:
10794                         break;
10795                 }
10796
10797                 cntl |= CURSOR_ENABLE |
10798                         CURSOR_GAMMA_ENABLE |
10799                         CURSOR_FORMAT_ARGB |
10800                         CURSOR_STRIDE(stride);
10801
10802                 size = (height << 12) | width;
10803         }
10804
10805         if (intel_crtc->cursor_cntl != 0 &&
10806             (intel_crtc->cursor_base != base ||
10807              intel_crtc->cursor_size != size ||
10808              intel_crtc->cursor_cntl != cntl)) {
10809                 /* On these chipsets we can only modify the base/size/stride
10810                  * whilst the cursor is disabled.
10811                  */
10812                 I915_WRITE(CURCNTR(PIPE_A), 0);
10813                 POSTING_READ(CURCNTR(PIPE_A));
10814                 intel_crtc->cursor_cntl = 0;
10815         }
10816
10817         if (intel_crtc->cursor_base != base) {
10818                 I915_WRITE(CURBASE(PIPE_A), base);
10819                 intel_crtc->cursor_base = base;
10820         }
10821
10822         if (intel_crtc->cursor_size != size) {
10823                 I915_WRITE(CURSIZE, size);
10824                 intel_crtc->cursor_size = size;
10825         }
10826
10827         if (intel_crtc->cursor_cntl != cntl) {
10828                 I915_WRITE(CURCNTR(PIPE_A), cntl);
10829                 POSTING_READ(CURCNTR(PIPE_A));
10830                 intel_crtc->cursor_cntl = cntl;
10831         }
10832 }
10833
10834 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
10835                                const struct intel_plane_state *plane_state)
10836 {
10837         struct drm_device *dev = crtc->dev;
10838         struct drm_i915_private *dev_priv = to_i915(dev);
10839         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10840         int pipe = intel_crtc->pipe;
10841         uint32_t cntl = 0;
10842
10843         if (plane_state && plane_state->base.visible) {
10844                 cntl = MCURSOR_GAMMA_ENABLE;
10845                 switch (plane_state->base.crtc_w) {
10846                         case 64:
10847                                 cntl |= CURSOR_MODE_64_ARGB_AX;
10848                                 break;
10849                         case 128:
10850                                 cntl |= CURSOR_MODE_128_ARGB_AX;
10851                                 break;
10852                         case 256:
10853                                 cntl |= CURSOR_MODE_256_ARGB_AX;
10854                                 break;
10855                         default:
10856                                 MISSING_CASE(plane_state->base.crtc_w);
10857                                 return;
10858                 }
10859                 cntl |= pipe << 28; /* Connect to correct pipe */
10860
10861                 if (HAS_DDI(dev_priv))
10862                         cntl |= CURSOR_PIPE_CSC_ENABLE;
10863
10864                 if (plane_state->base.rotation & DRM_ROTATE_180)
10865                         cntl |= CURSOR_ROTATE_180;
10866         }
10867
10868         if (intel_crtc->cursor_cntl != cntl) {
10869                 I915_WRITE(CURCNTR(pipe), cntl);
10870                 POSTING_READ(CURCNTR(pipe));
10871                 intel_crtc->cursor_cntl = cntl;
10872         }
10873
10874         /* and commit changes on next vblank */
10875         I915_WRITE(CURBASE(pipe), base);
10876         POSTING_READ(CURBASE(pipe));
10877
10878         intel_crtc->cursor_base = base;
10879 }
10880
10881 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10882 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10883                                      const struct intel_plane_state *plane_state)
10884 {
10885         struct drm_device *dev = crtc->dev;
10886         struct drm_i915_private *dev_priv = to_i915(dev);
10887         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10888         int pipe = intel_crtc->pipe;
10889         u32 base = intel_crtc->cursor_addr;
10890         u32 pos = 0;
10891
10892         if (plane_state) {
10893                 int x = plane_state->base.crtc_x;
10894                 int y = plane_state->base.crtc_y;
10895
10896                 if (x < 0) {
10897                         pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10898                         x = -x;
10899                 }
10900                 pos |= x << CURSOR_X_SHIFT;
10901
10902                 if (y < 0) {
10903                         pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10904                         y = -y;
10905                 }
10906                 pos |= y << CURSOR_Y_SHIFT;
10907
10908                 /* ILK+ do this automagically */
10909                 if (HAS_GMCH_DISPLAY(dev_priv) &&
10910                     plane_state->base.rotation & DRM_ROTATE_180) {
10911                         base += (plane_state->base.crtc_h *
10912                                  plane_state->base.crtc_w - 1) * 4;
10913                 }
10914         }
10915
10916         I915_WRITE(CURPOS(pipe), pos);
10917
10918         if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
10919                 i845_update_cursor(crtc, base, plane_state);
10920         else
10921                 i9xx_update_cursor(crtc, base, plane_state);
10922 }
10923
10924 static bool cursor_size_ok(struct drm_i915_private *dev_priv,
10925                            uint32_t width, uint32_t height)
10926 {
10927         if (width == 0 || height == 0)
10928                 return false;
10929
10930         /*
10931          * 845g/865g are special in that they are only limited by
10932          * the width of their cursors, the height is arbitrary up to
10933          * the precision of the register. Everything else requires
10934          * square cursors, limited to a few power-of-two sizes.
10935          */
10936         if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
10937                 if ((width & 63) != 0)
10938                         return false;
10939
10940                 if (width > (IS_I845G(dev_priv) ? 64 : 512))
10941                         return false;
10942
10943                 if (height > 1023)
10944                         return false;
10945         } else {
10946                 switch (width | height) {
10947                 case 256:
10948                 case 128:
10949                         if (IS_GEN2(dev_priv))
10950                                 return false;
10951                 case 64:
10952                         break;
10953                 default:
10954                         return false;
10955                 }
10956         }
10957
10958         return true;
10959 }
10960
10961 /* VESA 640x480x72Hz mode to set on the pipe */
10962 static struct drm_display_mode load_detect_mode = {
10963         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10964                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10965 };
10966
10967 struct drm_framebuffer *
10968 __intel_framebuffer_create(struct drm_device *dev,
10969                            struct drm_mode_fb_cmd2 *mode_cmd,
10970                            struct drm_i915_gem_object *obj)
10971 {
10972         struct intel_framebuffer *intel_fb;
10973         int ret;
10974
10975         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10976         if (!intel_fb)
10977                 return ERR_PTR(-ENOMEM);
10978
10979         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10980         if (ret)
10981                 goto err;
10982
10983         return &intel_fb->base;
10984
10985 err:
10986         kfree(intel_fb);
10987         return ERR_PTR(ret);
10988 }
10989
10990 static struct drm_framebuffer *
10991 intel_framebuffer_create(struct drm_device *dev,
10992                          struct drm_mode_fb_cmd2 *mode_cmd,
10993                          struct drm_i915_gem_object *obj)
10994 {
10995         struct drm_framebuffer *fb;
10996         int ret;
10997
10998         ret = i915_mutex_lock_interruptible(dev);
10999         if (ret)
11000                 return ERR_PTR(ret);
11001         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
11002         mutex_unlock(&dev->struct_mutex);
11003
11004         return fb;
11005 }
11006
11007 static u32
11008 intel_framebuffer_pitch_for_width(int width, int bpp)
11009 {
11010         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
11011         return ALIGN(pitch, 64);
11012 }
11013
11014 static u32
11015 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
11016 {
11017         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
11018         return PAGE_ALIGN(pitch * mode->vdisplay);
11019 }
11020
11021 static struct drm_framebuffer *
11022 intel_framebuffer_create_for_mode(struct drm_device *dev,
11023                                   struct drm_display_mode *mode,
11024                                   int depth, int bpp)
11025 {
11026         struct drm_framebuffer *fb;
11027         struct drm_i915_gem_object *obj;
11028         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
11029
11030         obj = i915_gem_object_create(to_i915(dev),
11031                                     intel_framebuffer_size_for_mode(mode, bpp));
11032         if (IS_ERR(obj))
11033                 return ERR_CAST(obj);
11034
11035         mode_cmd.width = mode->hdisplay;
11036         mode_cmd.height = mode->vdisplay;
11037         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
11038                                                                 bpp);
11039         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
11040
11041         fb = intel_framebuffer_create(dev, &mode_cmd, obj);
11042         if (IS_ERR(fb))
11043                 i915_gem_object_put(obj);
11044
11045         return fb;
11046 }
11047
11048 static struct drm_framebuffer *
11049 mode_fits_in_fbdev(struct drm_device *dev,
11050                    struct drm_display_mode *mode)
11051 {
11052 #ifdef CONFIG_DRM_FBDEV_EMULATION
11053         struct drm_i915_private *dev_priv = to_i915(dev);
11054         struct drm_i915_gem_object *obj;
11055         struct drm_framebuffer *fb;
11056
11057         if (!dev_priv->fbdev)
11058                 return NULL;
11059
11060         if (!dev_priv->fbdev->fb)
11061                 return NULL;
11062
11063         obj = dev_priv->fbdev->fb->obj;
11064         BUG_ON(!obj);
11065
11066         fb = &dev_priv->fbdev->fb->base;
11067         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
11068                                                                fb->format->cpp[0] * 8))
11069                 return NULL;
11070
11071         if (obj->base.size < mode->vdisplay * fb->pitches[0])
11072                 return NULL;
11073
11074         drm_framebuffer_reference(fb);
11075         return fb;
11076 #else
11077         return NULL;
11078 #endif
11079 }
11080
11081 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
11082                                            struct drm_crtc *crtc,
11083                                            struct drm_display_mode *mode,
11084                                            struct drm_framebuffer *fb,
11085                                            int x, int y)
11086 {
11087         struct drm_plane_state *plane_state;
11088         int hdisplay, vdisplay;
11089         int ret;
11090
11091         plane_state = drm_atomic_get_plane_state(state, crtc->primary);
11092         if (IS_ERR(plane_state))
11093                 return PTR_ERR(plane_state);
11094
11095         if (mode)
11096                 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
11097         else
11098                 hdisplay = vdisplay = 0;
11099
11100         ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
11101         if (ret)
11102                 return ret;
11103         drm_atomic_set_fb_for_plane(plane_state, fb);
11104         plane_state->crtc_x = 0;
11105         plane_state->crtc_y = 0;
11106         plane_state->crtc_w = hdisplay;
11107         plane_state->crtc_h = vdisplay;
11108         plane_state->src_x = x << 16;
11109         plane_state->src_y = y << 16;
11110         plane_state->src_w = hdisplay << 16;
11111         plane_state->src_h = vdisplay << 16;
11112
11113         return 0;
11114 }
11115
11116 bool intel_get_load_detect_pipe(struct drm_connector *connector,
11117                                 struct drm_display_mode *mode,
11118                                 struct intel_load_detect_pipe *old,
11119                                 struct drm_modeset_acquire_ctx *ctx)
11120 {
11121         struct intel_crtc *intel_crtc;
11122         struct intel_encoder *intel_encoder =
11123                 intel_attached_encoder(connector);
11124         struct drm_crtc *possible_crtc;
11125         struct drm_encoder *encoder = &intel_encoder->base;
11126         struct drm_crtc *crtc = NULL;
11127         struct drm_device *dev = encoder->dev;
11128         struct drm_i915_private *dev_priv = to_i915(dev);
11129         struct drm_framebuffer *fb;
11130         struct drm_mode_config *config = &dev->mode_config;
11131         struct drm_atomic_state *state = NULL, *restore_state = NULL;
11132         struct drm_connector_state *connector_state;
11133         struct intel_crtc_state *crtc_state;
11134         int ret, i = -1;
11135
11136         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
11137                       connector->base.id, connector->name,
11138                       encoder->base.id, encoder->name);
11139
11140         old->restore_state = NULL;
11141
11142 retry:
11143         ret = drm_modeset_lock(&config->connection_mutex, ctx);
11144         if (ret)
11145                 goto fail;
11146
11147         /*
11148          * Algorithm gets a little messy:
11149          *
11150          *   - if the connector already has an assigned crtc, use it (but make
11151          *     sure it's on first)
11152          *
11153          *   - try to find the first unused crtc that can drive this connector,
11154          *     and use that if we find one
11155          */
11156
11157         /* See if we already have a CRTC for this connector */
11158         if (connector->state->crtc) {
11159                 crtc = connector->state->crtc;
11160
11161                 ret = drm_modeset_lock(&crtc->mutex, ctx);
11162                 if (ret)
11163                         goto fail;
11164
11165                 /* Make sure the crtc and connector are running */
11166                 goto found;
11167         }
11168
11169         /* Find an unused one (if possible) */
11170         for_each_crtc(dev, possible_crtc) {
11171                 i++;
11172                 if (!(encoder->possible_crtcs & (1 << i)))
11173                         continue;
11174
11175                 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
11176                 if (ret)
11177                         goto fail;
11178
11179                 if (possible_crtc->state->enable) {
11180                         drm_modeset_unlock(&possible_crtc->mutex);
11181                         continue;
11182                 }
11183
11184                 crtc = possible_crtc;
11185                 break;
11186         }
11187
11188         /*
11189          * If we didn't find an unused CRTC, don't use any.
11190          */
11191         if (!crtc) {
11192                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
11193                 goto fail;
11194         }
11195
11196 found:
11197         intel_crtc = to_intel_crtc(crtc);
11198
11199         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
11200         if (ret)
11201                 goto fail;
11202
11203         state = drm_atomic_state_alloc(dev);
11204         restore_state = drm_atomic_state_alloc(dev);
11205         if (!state || !restore_state) {
11206                 ret = -ENOMEM;
11207                 goto fail;
11208         }
11209
11210         state->acquire_ctx = ctx;
11211         restore_state->acquire_ctx = ctx;
11212
11213         connector_state = drm_atomic_get_connector_state(state, connector);
11214         if (IS_ERR(connector_state)) {
11215                 ret = PTR_ERR(connector_state);
11216                 goto fail;
11217         }
11218
11219         ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
11220         if (ret)
11221                 goto fail;
11222
11223         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
11224         if (IS_ERR(crtc_state)) {
11225                 ret = PTR_ERR(crtc_state);
11226                 goto fail;
11227         }
11228
11229         crtc_state->base.active = crtc_state->base.enable = true;
11230
11231         if (!mode)
11232                 mode = &load_detect_mode;
11233
11234         /* We need a framebuffer large enough to accommodate all accesses
11235          * that the plane may generate whilst we perform load detection.
11236          * We can not rely on the fbcon either being present (we get called
11237          * during its initialisation to detect all boot displays, or it may
11238          * not even exist) or that it is large enough to satisfy the
11239          * requested mode.
11240          */
11241         fb = mode_fits_in_fbdev(dev, mode);
11242         if (fb == NULL) {
11243                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
11244                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
11245         } else
11246                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
11247         if (IS_ERR(fb)) {
11248                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
11249                 goto fail;
11250         }
11251
11252         ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
11253         if (ret)
11254                 goto fail;
11255
11256         drm_framebuffer_unreference(fb);
11257
11258         ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
11259         if (ret)
11260                 goto fail;
11261
11262         ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
11263         if (!ret)
11264                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
11265         if (!ret)
11266                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
11267         if (ret) {
11268                 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
11269                 goto fail;
11270         }
11271
11272         ret = drm_atomic_commit(state);
11273         if (ret) {
11274                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
11275                 goto fail;
11276         }
11277
11278         old->restore_state = restore_state;
11279
11280         /* let the connector get through one full cycle before testing */
11281         intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
11282         return true;
11283
11284 fail:
11285         if (state) {
11286                 drm_atomic_state_put(state);
11287                 state = NULL;
11288         }
11289         if (restore_state) {
11290                 drm_atomic_state_put(restore_state);
11291                 restore_state = NULL;
11292         }
11293
11294         if (ret == -EDEADLK) {
11295                 drm_modeset_backoff(ctx);
11296                 goto retry;
11297         }
11298
11299         return false;
11300 }
11301
11302 void intel_release_load_detect_pipe(struct drm_connector *connector,
11303                                     struct intel_load_detect_pipe *old,
11304                                     struct drm_modeset_acquire_ctx *ctx)
11305 {
11306         struct intel_encoder *intel_encoder =
11307                 intel_attached_encoder(connector);
11308         struct drm_encoder *encoder = &intel_encoder->base;
11309         struct drm_atomic_state *state = old->restore_state;
11310         int ret;
11311
11312         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
11313                       connector->base.id, connector->name,
11314                       encoder->base.id, encoder->name);
11315
11316         if (!state)
11317                 return;
11318
11319         ret = drm_atomic_commit(state);
11320         if (ret)
11321                 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
11322         drm_atomic_state_put(state);
11323 }
11324
11325 static int i9xx_pll_refclk(struct drm_device *dev,
11326                            const struct intel_crtc_state *pipe_config)
11327 {
11328         struct drm_i915_private *dev_priv = to_i915(dev);
11329         u32 dpll = pipe_config->dpll_hw_state.dpll;
11330
11331         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
11332                 return dev_priv->vbt.lvds_ssc_freq;
11333         else if (HAS_PCH_SPLIT(dev_priv))
11334                 return 120000;
11335         else if (!IS_GEN2(dev_priv))
11336                 return 96000;
11337         else
11338                 return 48000;
11339 }
11340
11341 /* Returns the clock of the currently programmed mode of the given pipe. */
11342 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
11343                                 struct intel_crtc_state *pipe_config)
11344 {
11345         struct drm_device *dev = crtc->base.dev;
11346         struct drm_i915_private *dev_priv = to_i915(dev);
11347         int pipe = pipe_config->cpu_transcoder;
11348         u32 dpll = pipe_config->dpll_hw_state.dpll;
11349         u32 fp;
11350         struct dpll clock;
11351         int port_clock;
11352         int refclk = i9xx_pll_refclk(dev, pipe_config);
11353
11354         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
11355                 fp = pipe_config->dpll_hw_state.fp0;
11356         else
11357                 fp = pipe_config->dpll_hw_state.fp1;
11358
11359         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
11360         if (IS_PINEVIEW(dev_priv)) {
11361                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
11362                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
11363         } else {
11364                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
11365                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
11366         }
11367
11368         if (!IS_GEN2(dev_priv)) {
11369                 if (IS_PINEVIEW(dev_priv))
11370                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
11371                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
11372                 else
11373                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
11374                                DPLL_FPA01_P1_POST_DIV_SHIFT);
11375
11376                 switch (dpll & DPLL_MODE_MASK) {
11377                 case DPLLB_MODE_DAC_SERIAL:
11378                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
11379                                 5 : 10;
11380                         break;
11381                 case DPLLB_MODE_LVDS:
11382                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
11383                                 7 : 14;
11384                         break;
11385                 default:
11386                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
11387                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
11388                         return;
11389                 }
11390
11391                 if (IS_PINEVIEW(dev_priv))
11392                         port_clock = pnv_calc_dpll_params(refclk, &clock);
11393                 else
11394                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
11395         } else {
11396                 u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS);
11397                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
11398
11399                 if (is_lvds) {
11400                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
11401                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
11402
11403                         if (lvds & LVDS_CLKB_POWER_UP)
11404                                 clock.p2 = 7;
11405                         else
11406                                 clock.p2 = 14;
11407                 } else {
11408                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
11409                                 clock.p1 = 2;
11410                         else {
11411                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
11412                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
11413                         }
11414                         if (dpll & PLL_P2_DIVIDE_BY_4)
11415                                 clock.p2 = 4;
11416                         else
11417                                 clock.p2 = 2;
11418                 }
11419
11420                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
11421         }
11422
11423         /*
11424          * This value includes pixel_multiplier. We will use
11425          * port_clock to compute adjusted_mode.crtc_clock in the
11426          * encoder's get_config() function.
11427          */
11428         pipe_config->port_clock = port_clock;
11429 }
11430
11431 int intel_dotclock_calculate(int link_freq,
11432                              const struct intel_link_m_n *m_n)
11433 {
11434         /*
11435          * The calculation for the data clock is:
11436          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
11437          * But we want to avoid losing precison if possible, so:
11438          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
11439          *
11440          * and the link clock is simpler:
11441          * link_clock = (m * link_clock) / n
11442          */
11443
11444         if (!m_n->link_n)
11445                 return 0;
11446
11447         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
11448 }
11449
11450 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
11451                                    struct intel_crtc_state *pipe_config)
11452 {
11453         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11454
11455         /* read out port_clock from the DPLL */
11456         i9xx_crtc_clock_get(crtc, pipe_config);
11457
11458         /*
11459          * In case there is an active pipe without active ports,
11460          * we may need some idea for the dotclock anyway.
11461          * Calculate one based on the FDI configuration.
11462          */
11463         pipe_config->base.adjusted_mode.crtc_clock =
11464                 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
11465                                          &pipe_config->fdi_m_n);
11466 }
11467
11468 /** Returns the currently programmed mode of the given pipe. */
11469 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
11470                                              struct drm_crtc *crtc)
11471 {
11472         struct drm_i915_private *dev_priv = to_i915(dev);
11473         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11474         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
11475         struct drm_display_mode *mode;
11476         struct intel_crtc_state *pipe_config;
11477         int htot = I915_READ(HTOTAL(cpu_transcoder));
11478         int hsync = I915_READ(HSYNC(cpu_transcoder));
11479         int vtot = I915_READ(VTOTAL(cpu_transcoder));
11480         int vsync = I915_READ(VSYNC(cpu_transcoder));
11481         enum pipe pipe = intel_crtc->pipe;
11482
11483         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
11484         if (!mode)
11485                 return NULL;
11486
11487         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
11488         if (!pipe_config) {
11489                 kfree(mode);
11490                 return NULL;
11491         }
11492
11493         /*
11494          * Construct a pipe_config sufficient for getting the clock info
11495          * back out of crtc_clock_get.
11496          *
11497          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
11498          * to use a real value here instead.
11499          */
11500         pipe_config->cpu_transcoder = (enum transcoder) pipe;
11501         pipe_config->pixel_multiplier = 1;
11502         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
11503         pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
11504         pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
11505         i9xx_crtc_clock_get(intel_crtc, pipe_config);
11506
11507         mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
11508         mode->hdisplay = (htot & 0xffff) + 1;
11509         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
11510         mode->hsync_start = (hsync & 0xffff) + 1;
11511         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
11512         mode->vdisplay = (vtot & 0xffff) + 1;
11513         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
11514         mode->vsync_start = (vsync & 0xffff) + 1;
11515         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
11516
11517         drm_mode_set_name(mode);
11518
11519         kfree(pipe_config);
11520
11521         return mode;
11522 }
11523
11524 static void intel_crtc_destroy(struct drm_crtc *crtc)
11525 {
11526         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11527         struct drm_device *dev = crtc->dev;
11528         struct intel_flip_work *work;
11529
11530         spin_lock_irq(&dev->event_lock);
11531         work = intel_crtc->flip_work;
11532         intel_crtc->flip_work = NULL;
11533         spin_unlock_irq(&dev->event_lock);
11534
11535         if (work) {
11536                 cancel_work_sync(&work->mmio_work);
11537                 cancel_work_sync(&work->unpin_work);
11538                 kfree(work);
11539         }
11540
11541         drm_crtc_cleanup(crtc);
11542
11543         kfree(intel_crtc);
11544 }
11545
11546 static void intel_unpin_work_fn(struct work_struct *__work)
11547 {
11548         struct intel_flip_work *work =
11549                 container_of(__work, struct intel_flip_work, unpin_work);
11550         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
11551         struct drm_device *dev = crtc->base.dev;
11552         struct drm_plane *primary = crtc->base.primary;
11553
11554         if (is_mmio_work(work))
11555                 flush_work(&work->mmio_work);
11556
11557         mutex_lock(&dev->struct_mutex);
11558         intel_unpin_fb_vma(work->old_vma);
11559         i915_gem_object_put(work->pending_flip_obj);
11560         mutex_unlock(&dev->struct_mutex);
11561
11562         i915_gem_request_put(work->flip_queued_req);
11563
11564         intel_frontbuffer_flip_complete(to_i915(dev),
11565                                         to_intel_plane(primary)->frontbuffer_bit);
11566         intel_fbc_post_update(crtc);
11567         drm_framebuffer_unreference(work->old_fb);
11568
11569         BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
11570         atomic_dec(&crtc->unpin_work_count);
11571
11572         kfree(work);
11573 }
11574
11575 /* Is 'a' after or equal to 'b'? */
11576 static bool g4x_flip_count_after_eq(u32 a, u32 b)
11577 {
11578         return !((a - b) & 0x80000000);
11579 }
11580
11581 static bool __pageflip_finished_cs(struct intel_crtc *crtc,
11582                                    struct intel_flip_work *work)
11583 {
11584         struct drm_device *dev = crtc->base.dev;
11585         struct drm_i915_private *dev_priv = to_i915(dev);
11586
11587         if (abort_flip_on_reset(crtc))
11588                 return true;
11589
11590         /*
11591          * The relevant registers doen't exist on pre-ctg.
11592          * As the flip done interrupt doesn't trigger for mmio
11593          * flips on gmch platforms, a flip count check isn't
11594          * really needed there. But since ctg has the registers,
11595          * include it in the check anyway.
11596          */
11597         if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
11598                 return true;
11599
11600         /*
11601          * BDW signals flip done immediately if the plane
11602          * is disabled, even if the plane enable is already
11603          * armed to occur at the next vblank :(
11604          */
11605
11606         /*
11607          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
11608          * used the same base address. In that case the mmio flip might
11609          * have completed, but the CS hasn't even executed the flip yet.
11610          *
11611          * A flip count check isn't enough as the CS might have updated
11612          * the base address just after start of vblank, but before we
11613          * managed to process the interrupt. This means we'd complete the
11614          * CS flip too soon.
11615          *
11616          * Combining both checks should get us a good enough result. It may
11617          * still happen that the CS flip has been executed, but has not
11618          * yet actually completed. But in case the base address is the same
11619          * anyway, we don't really care.
11620          */
11621         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
11622                 crtc->flip_work->gtt_offset &&
11623                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
11624                                     crtc->flip_work->flip_count);
11625 }
11626
11627 static bool
11628 __pageflip_finished_mmio(struct intel_crtc *crtc,
11629                                struct intel_flip_work *work)
11630 {
11631         /*
11632          * MMIO work completes when vblank is different from
11633          * flip_queued_vblank.
11634          *
11635          * Reset counter value doesn't matter, this is handled by
11636          * i915_wait_request finishing early, so no need to handle
11637          * reset here.
11638          */
11639         return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank;
11640 }
11641
11642
11643 static bool pageflip_finished(struct intel_crtc *crtc,
11644                               struct intel_flip_work *work)
11645 {
11646         if (!atomic_read(&work->pending))
11647                 return false;
11648
11649         smp_rmb();
11650
11651         if (is_mmio_work(work))
11652                 return __pageflip_finished_mmio(crtc, work);
11653         else
11654                 return __pageflip_finished_cs(crtc, work);
11655 }
11656
11657 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe)
11658 {
11659         struct drm_device *dev = &dev_priv->drm;
11660         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
11661         struct intel_flip_work *work;
11662         unsigned long flags;
11663
11664         /* Ignore early vblank irqs */
11665         if (!crtc)
11666                 return;
11667
11668         /*
11669          * This is called both by irq handlers and the reset code (to complete
11670          * lost pageflips) so needs the full irqsave spinlocks.
11671          */
11672         spin_lock_irqsave(&dev->event_lock, flags);
11673         work = crtc->flip_work;
11674
11675         if (work != NULL &&
11676             !is_mmio_work(work) &&
11677             pageflip_finished(crtc, work))
11678                 page_flip_completed(crtc);
11679
11680         spin_unlock_irqrestore(&dev->event_lock, flags);
11681 }
11682
11683 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe)
11684 {
11685         struct drm_device *dev = &dev_priv->drm;
11686         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
11687         struct intel_flip_work *work;
11688         unsigned long flags;
11689
11690         /* Ignore early vblank irqs */
11691         if (!crtc)
11692                 return;
11693
11694         /*
11695          * This is called both by irq handlers and the reset code (to complete
11696          * lost pageflips) so needs the full irqsave spinlocks.
11697          */
11698         spin_lock_irqsave(&dev->event_lock, flags);
11699         work = crtc->flip_work;
11700
11701         if (work != NULL &&
11702             is_mmio_work(work) &&
11703             pageflip_finished(crtc, work))
11704                 page_flip_completed(crtc);
11705
11706         spin_unlock_irqrestore(&dev->event_lock, flags);
11707 }
11708
11709 static inline void intel_mark_page_flip_active(struct intel_crtc *crtc,
11710                                                struct intel_flip_work *work)
11711 {
11712         work->flip_queued_vblank = intel_crtc_get_vblank_counter(crtc);
11713
11714         /* Ensure that the work item is consistent when activating it ... */
11715         smp_mb__before_atomic();
11716         atomic_set(&work->pending, 1);
11717 }
11718
11719 static int intel_gen2_queue_flip(struct drm_device *dev,
11720                                  struct drm_crtc *crtc,
11721                                  struct drm_framebuffer *fb,
11722                                  struct drm_i915_gem_object *obj,
11723                                  struct drm_i915_gem_request *req,
11724                                  uint32_t flags)
11725 {
11726         struct intel_ring *ring = req->ring;
11727         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11728         u32 flip_mask;
11729         int ret;
11730
11731         ret = intel_ring_begin(req, 6);
11732         if (ret)
11733                 return ret;
11734
11735         /* Can't queue multiple flips, so wait for the previous
11736          * one to finish before executing the next.
11737          */
11738         if (intel_crtc->plane)
11739                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11740         else
11741                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11742         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11743         intel_ring_emit(ring, MI_NOOP);
11744         intel_ring_emit(ring, MI_DISPLAY_FLIP |
11745                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11746         intel_ring_emit(ring, fb->pitches[0]);
11747         intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11748         intel_ring_emit(ring, 0); /* aux display base address, unused */
11749
11750         return 0;
11751 }
11752
11753 static int intel_gen3_queue_flip(struct drm_device *dev,
11754                                  struct drm_crtc *crtc,
11755                                  struct drm_framebuffer *fb,
11756                                  struct drm_i915_gem_object *obj,
11757                                  struct drm_i915_gem_request *req,
11758                                  uint32_t flags)
11759 {
11760         struct intel_ring *ring = req->ring;
11761         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11762         u32 flip_mask;
11763         int ret;
11764
11765         ret = intel_ring_begin(req, 6);
11766         if (ret)
11767                 return ret;
11768
11769         if (intel_crtc->plane)
11770                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11771         else
11772                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11773         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11774         intel_ring_emit(ring, MI_NOOP);
11775         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
11776                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11777         intel_ring_emit(ring, fb->pitches[0]);
11778         intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11779         intel_ring_emit(ring, MI_NOOP);
11780
11781         return 0;
11782 }
11783
11784 static int intel_gen4_queue_flip(struct drm_device *dev,
11785                                  struct drm_crtc *crtc,
11786                                  struct drm_framebuffer *fb,
11787                                  struct drm_i915_gem_object *obj,
11788                                  struct drm_i915_gem_request *req,
11789                                  uint32_t flags)
11790 {
11791         struct intel_ring *ring = req->ring;
11792         struct drm_i915_private *dev_priv = to_i915(dev);
11793         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11794         uint32_t pf, pipesrc;
11795         int ret;
11796
11797         ret = intel_ring_begin(req, 4);
11798         if (ret)
11799                 return ret;
11800
11801         /* i965+ uses the linear or tiled offsets from the
11802          * Display Registers (which do not change across a page-flip)
11803          * so we need only reprogram the base address.
11804          */
11805         intel_ring_emit(ring, MI_DISPLAY_FLIP |
11806                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11807         intel_ring_emit(ring, fb->pitches[0]);
11808         intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset |
11809                         intel_fb_modifier_to_tiling(fb->modifier));
11810
11811         /* XXX Enabling the panel-fitter across page-flip is so far
11812          * untested on non-native modes, so ignore it for now.
11813          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11814          */
11815         pf = 0;
11816         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11817         intel_ring_emit(ring, pf | pipesrc);
11818
11819         return 0;
11820 }
11821
11822 static int intel_gen6_queue_flip(struct drm_device *dev,
11823                                  struct drm_crtc *crtc,
11824                                  struct drm_framebuffer *fb,
11825                                  struct drm_i915_gem_object *obj,
11826                                  struct drm_i915_gem_request *req,
11827                                  uint32_t flags)
11828 {
11829         struct intel_ring *ring = req->ring;
11830         struct drm_i915_private *dev_priv = to_i915(dev);
11831         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11832         uint32_t pf, pipesrc;
11833         int ret;
11834
11835         ret = intel_ring_begin(req, 4);
11836         if (ret)
11837                 return ret;
11838
11839         intel_ring_emit(ring, MI_DISPLAY_FLIP |
11840                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11841         intel_ring_emit(ring, fb->pitches[0] |
11842                         intel_fb_modifier_to_tiling(fb->modifier));
11843         intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11844
11845         /* Contrary to the suggestions in the documentation,
11846          * "Enable Panel Fitter" does not seem to be required when page
11847          * flipping with a non-native mode, and worse causes a normal
11848          * modeset to fail.
11849          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11850          */
11851         pf = 0;
11852         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11853         intel_ring_emit(ring, pf | pipesrc);
11854
11855         return 0;
11856 }
11857
11858 static int intel_gen7_queue_flip(struct drm_device *dev,
11859                                  struct drm_crtc *crtc,
11860                                  struct drm_framebuffer *fb,
11861                                  struct drm_i915_gem_object *obj,
11862                                  struct drm_i915_gem_request *req,
11863                                  uint32_t flags)
11864 {
11865         struct drm_i915_private *dev_priv = to_i915(dev);
11866         struct intel_ring *ring = req->ring;
11867         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11868         uint32_t plane_bit = 0;
11869         int len, ret;
11870
11871         switch (intel_crtc->plane) {
11872         case PLANE_A:
11873                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11874                 break;
11875         case PLANE_B:
11876                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11877                 break;
11878         case PLANE_C:
11879                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11880                 break;
11881         default:
11882                 WARN_ONCE(1, "unknown plane in flip command\n");
11883                 return -ENODEV;
11884         }
11885
11886         len = 4;
11887         if (req->engine->id == RCS) {
11888                 len += 6;
11889                 /*
11890                  * On Gen 8, SRM is now taking an extra dword to accommodate
11891                  * 48bits addresses, and we need a NOOP for the batch size to
11892                  * stay even.
11893                  */
11894                 if (IS_GEN8(dev_priv))
11895                         len += 2;
11896         }
11897
11898         /*
11899          * BSpec MI_DISPLAY_FLIP for IVB:
11900          * "The full packet must be contained within the same cache line."
11901          *
11902          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11903          * cacheline, if we ever start emitting more commands before
11904          * the MI_DISPLAY_FLIP we may need to first emit everything else,
11905          * then do the cacheline alignment, and finally emit the
11906          * MI_DISPLAY_FLIP.
11907          */
11908         ret = intel_ring_cacheline_align(req);
11909         if (ret)
11910                 return ret;
11911
11912         ret = intel_ring_begin(req, len);
11913         if (ret)
11914                 return ret;
11915
11916         /* Unmask the flip-done completion message. Note that the bspec says that
11917          * we should do this for both the BCS and RCS, and that we must not unmask
11918          * more than one flip event at any time (or ensure that one flip message
11919          * can be sent by waiting for flip-done prior to queueing new flips).
11920          * Experimentation says that BCS works despite DERRMR masking all
11921          * flip-done completion events and that unmasking all planes at once
11922          * for the RCS also doesn't appear to drop events. Setting the DERRMR
11923          * to zero does lead to lockups within MI_DISPLAY_FLIP.
11924          */
11925         if (req->engine->id == RCS) {
11926                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11927                 intel_ring_emit_reg(ring, DERRMR);
11928                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11929                                           DERRMR_PIPEB_PRI_FLIP_DONE |
11930                                           DERRMR_PIPEC_PRI_FLIP_DONE));
11931                 if (IS_GEN8(dev_priv))
11932                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
11933                                               MI_SRM_LRM_GLOBAL_GTT);
11934                 else
11935                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
11936                                               MI_SRM_LRM_GLOBAL_GTT);
11937                 intel_ring_emit_reg(ring, DERRMR);
11938                 intel_ring_emit(ring,
11939                                 i915_ggtt_offset(req->engine->scratch) + 256);
11940                 if (IS_GEN8(dev_priv)) {
11941                         intel_ring_emit(ring, 0);
11942                         intel_ring_emit(ring, MI_NOOP);
11943                 }
11944         }
11945
11946         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11947         intel_ring_emit(ring, fb->pitches[0] |
11948                         intel_fb_modifier_to_tiling(fb->modifier));
11949         intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11950         intel_ring_emit(ring, (MI_NOOP));
11951
11952         return 0;
11953 }
11954
11955 static bool use_mmio_flip(struct intel_engine_cs *engine,
11956                           struct drm_i915_gem_object *obj)
11957 {
11958         /*
11959          * This is not being used for older platforms, because
11960          * non-availability of flip done interrupt forces us to use
11961          * CS flips. Older platforms derive flip done using some clever
11962          * tricks involving the flip_pending status bits and vblank irqs.
11963          * So using MMIO flips there would disrupt this mechanism.
11964          */
11965
11966         if (engine == NULL)
11967                 return true;
11968
11969         if (INTEL_GEN(engine->i915) < 5)
11970                 return false;
11971
11972         if (i915.use_mmio_flip < 0)
11973                 return false;
11974         else if (i915.use_mmio_flip > 0)
11975                 return true;
11976         else if (i915.enable_execlists)
11977                 return true;
11978
11979         return engine != i915_gem_object_last_write_engine(obj);
11980 }
11981
11982 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11983                              unsigned int rotation,
11984                              struct intel_flip_work *work)
11985 {
11986         struct drm_device *dev = intel_crtc->base.dev;
11987         struct drm_i915_private *dev_priv = to_i915(dev);
11988         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11989         const enum pipe pipe = intel_crtc->pipe;
11990         u32 ctl, stride = skl_plane_stride(fb, 0, rotation);
11991
11992         ctl = I915_READ(PLANE_CTL(pipe, 0));
11993         ctl &= ~PLANE_CTL_TILED_MASK;
11994         switch (fb->modifier) {
11995         case DRM_FORMAT_MOD_NONE:
11996                 break;
11997         case I915_FORMAT_MOD_X_TILED:
11998                 ctl |= PLANE_CTL_TILED_X;
11999                 break;
12000         case I915_FORMAT_MOD_Y_TILED:
12001                 ctl |= PLANE_CTL_TILED_Y;
12002                 break;
12003         case I915_FORMAT_MOD_Yf_TILED:
12004                 ctl |= PLANE_CTL_TILED_YF;
12005                 break;
12006         default:
12007                 MISSING_CASE(fb->modifier);
12008         }
12009
12010         /*
12011          * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
12012          * PLANE_SURF updates, the update is then guaranteed to be atomic.
12013          */
12014         I915_WRITE(PLANE_CTL(pipe, 0), ctl);
12015         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
12016
12017         I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
12018         POSTING_READ(PLANE_SURF(pipe, 0));
12019 }
12020
12021 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
12022                              struct intel_flip_work *work)
12023 {
12024         struct drm_device *dev = intel_crtc->base.dev;
12025         struct drm_i915_private *dev_priv = to_i915(dev);
12026         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
12027         i915_reg_t reg = DSPCNTR(intel_crtc->plane);
12028         u32 dspcntr;
12029
12030         dspcntr = I915_READ(reg);
12031
12032         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
12033                 dspcntr |= DISPPLANE_TILED;
12034         else
12035                 dspcntr &= ~DISPPLANE_TILED;
12036
12037         I915_WRITE(reg, dspcntr);
12038
12039         I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
12040         POSTING_READ(DSPSURF(intel_crtc->plane));
12041 }
12042
12043 static void intel_mmio_flip_work_func(struct work_struct *w)
12044 {
12045         struct intel_flip_work *work =
12046                 container_of(w, struct intel_flip_work, mmio_work);
12047         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
12048         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12049         struct intel_framebuffer *intel_fb =
12050                 to_intel_framebuffer(crtc->base.primary->fb);
12051         struct drm_i915_gem_object *obj = intel_fb->obj;
12052
12053         WARN_ON(i915_gem_object_wait(obj, 0, MAX_SCHEDULE_TIMEOUT, NULL) < 0);
12054
12055         intel_pipe_update_start(crtc);
12056
12057         if (INTEL_GEN(dev_priv) >= 9)
12058                 skl_do_mmio_flip(crtc, work->rotation, work);
12059         else
12060                 /* use_mmio_flip() retricts MMIO flips to ilk+ */
12061                 ilk_do_mmio_flip(crtc, work);
12062
12063         intel_pipe_update_end(crtc, work);
12064 }
12065
12066 static int intel_default_queue_flip(struct drm_device *dev,
12067                                     struct drm_crtc *crtc,
12068                                     struct drm_framebuffer *fb,
12069                                     struct drm_i915_gem_object *obj,
12070                                     struct drm_i915_gem_request *req,
12071                                     uint32_t flags)
12072 {
12073         return -ENODEV;
12074 }
12075
12076 static bool __pageflip_stall_check_cs(struct drm_i915_private *dev_priv,
12077                                       struct intel_crtc *intel_crtc,
12078                                       struct intel_flip_work *work)
12079 {
12080         u32 addr, vblank;
12081
12082         if (!atomic_read(&work->pending))
12083                 return false;
12084
12085         smp_rmb();
12086
12087         vblank = intel_crtc_get_vblank_counter(intel_crtc);
12088         if (work->flip_ready_vblank == 0) {
12089                 if (work->flip_queued_req &&
12090                     !i915_gem_request_completed(work->flip_queued_req))
12091                         return false;
12092
12093                 work->flip_ready_vblank = vblank;
12094         }
12095
12096         if (vblank - work->flip_ready_vblank < 3)
12097                 return false;
12098
12099         /* Potential stall - if we see that the flip has happened,
12100          * assume a missed interrupt. */
12101         if (INTEL_GEN(dev_priv) >= 4)
12102                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
12103         else
12104                 addr = I915_READ(DSPADDR(intel_crtc->plane));
12105
12106         /* There is a potential issue here with a false positive after a flip
12107          * to the same address. We could address this by checking for a
12108          * non-incrementing frame counter.
12109          */
12110         return addr == work->gtt_offset;
12111 }
12112
12113 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe)
12114 {
12115         struct drm_device *dev = &dev_priv->drm;
12116         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
12117         struct intel_flip_work *work;
12118
12119         WARN_ON(!in_interrupt());
12120
12121         if (crtc == NULL)
12122                 return;
12123
12124         spin_lock(&dev->event_lock);
12125         work = crtc->flip_work;
12126
12127         if (work != NULL && !is_mmio_work(work) &&
12128             __pageflip_stall_check_cs(dev_priv, crtc, work)) {
12129                 WARN_ONCE(1,
12130                           "Kicking stuck page flip: queued at %d, now %d\n",
12131                         work->flip_queued_vblank, intel_crtc_get_vblank_counter(crtc));
12132                 page_flip_completed(crtc);
12133                 work = NULL;
12134         }
12135
12136         if (work != NULL && !is_mmio_work(work) &&
12137             intel_crtc_get_vblank_counter(crtc) - work->flip_queued_vblank > 1)
12138                 intel_queue_rps_boost_for_request(work->flip_queued_req);
12139         spin_unlock(&dev->event_lock);
12140 }
12141
12142 static int intel_crtc_page_flip(struct drm_crtc *crtc,
12143                                 struct drm_framebuffer *fb,
12144                                 struct drm_pending_vblank_event *event,
12145                                 uint32_t page_flip_flags)
12146 {
12147         struct drm_device *dev = crtc->dev;
12148         struct drm_i915_private *dev_priv = to_i915(dev);
12149         struct drm_framebuffer *old_fb = crtc->primary->fb;
12150         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12151         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12152         struct drm_plane *primary = crtc->primary;
12153         enum pipe pipe = intel_crtc->pipe;
12154         struct intel_flip_work *work;
12155         struct intel_engine_cs *engine;
12156         bool mmio_flip;
12157         struct drm_i915_gem_request *request;
12158         struct i915_vma *vma;
12159         int ret;
12160
12161         /*
12162          * drm_mode_page_flip_ioctl() should already catch this, but double
12163          * check to be safe.  In the future we may enable pageflipping from
12164          * a disabled primary plane.
12165          */
12166         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
12167                 return -EBUSY;
12168
12169         /* Can't change pixel format via MI display flips. */
12170         if (fb->format != crtc->primary->fb->format)
12171                 return -EINVAL;
12172
12173         /*
12174          * TILEOFF/LINOFF registers can't be changed via MI display flips.
12175          * Note that pitch changes could also affect these register.
12176          */
12177         if (INTEL_GEN(dev_priv) > 3 &&
12178             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
12179              fb->pitches[0] != crtc->primary->fb->pitches[0]))
12180                 return -EINVAL;
12181
12182         if (i915_terminally_wedged(&dev_priv->gpu_error))
12183                 goto out_hang;
12184
12185         work = kzalloc(sizeof(*work), GFP_KERNEL);
12186         if (work == NULL)
12187                 return -ENOMEM;
12188
12189         work->event = event;
12190         work->crtc = crtc;
12191         work->old_fb = old_fb;
12192         INIT_WORK(&work->unpin_work, intel_unpin_work_fn);
12193
12194         ret = drm_crtc_vblank_get(crtc);
12195         if (ret)
12196                 goto free_work;
12197
12198         /* We borrow the event spin lock for protecting flip_work */
12199         spin_lock_irq(&dev->event_lock);
12200         if (intel_crtc->flip_work) {
12201                 /* Before declaring the flip queue wedged, check if
12202                  * the hardware completed the operation behind our backs.
12203                  */
12204                 if (pageflip_finished(intel_crtc, intel_crtc->flip_work)) {
12205                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
12206                         page_flip_completed(intel_crtc);
12207                 } else {
12208                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
12209                         spin_unlock_irq(&dev->event_lock);
12210
12211                         drm_crtc_vblank_put(crtc);
12212                         kfree(work);
12213                         return -EBUSY;
12214                 }
12215         }
12216         intel_crtc->flip_work = work;
12217         spin_unlock_irq(&dev->event_lock);
12218
12219         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
12220                 flush_workqueue(dev_priv->wq);
12221
12222         /* Reference the objects for the scheduled work. */
12223         drm_framebuffer_reference(work->old_fb);
12224
12225         crtc->primary->fb = fb;
12226         update_state_fb(crtc->primary);
12227
12228         work->pending_flip_obj = i915_gem_object_get(obj);
12229
12230         ret = i915_mutex_lock_interruptible(dev);
12231         if (ret)
12232                 goto cleanup;
12233
12234         intel_crtc->reset_count = i915_reset_count(&dev_priv->gpu_error);
12235         if (i915_reset_in_progress_or_wedged(&dev_priv->gpu_error)) {
12236                 ret = -EIO;
12237                 goto unlock;
12238         }
12239
12240         atomic_inc(&intel_crtc->unpin_work_count);
12241
12242         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
12243                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
12244
12245         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
12246                 engine = dev_priv->engine[BCS];
12247                 if (fb->modifier != old_fb->modifier)
12248                         /* vlv: DISPLAY_FLIP fails to change tiling */
12249                         engine = NULL;
12250         } else if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
12251                 engine = dev_priv->engine[BCS];
12252         } else if (INTEL_GEN(dev_priv) >= 7) {
12253                 engine = i915_gem_object_last_write_engine(obj);
12254                 if (engine == NULL || engine->id != RCS)
12255                         engine = dev_priv->engine[BCS];
12256         } else {
12257                 engine = dev_priv->engine[RCS];
12258         }
12259
12260         mmio_flip = use_mmio_flip(engine, obj);
12261
12262         vma = intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
12263         if (IS_ERR(vma)) {
12264                 ret = PTR_ERR(vma);
12265                 goto cleanup_pending;
12266         }
12267
12268         work->old_vma = to_intel_plane_state(primary->state)->vma;
12269         to_intel_plane_state(primary->state)->vma = vma;
12270
12271         work->gtt_offset = i915_ggtt_offset(vma) + intel_crtc->dspaddr_offset;
12272         work->rotation = crtc->primary->state->rotation;
12273
12274         /*
12275          * There's the potential that the next frame will not be compatible with
12276          * FBC, so we want to call pre_update() before the actual page flip.
12277          * The problem is that pre_update() caches some information about the fb
12278          * object, so we want to do this only after the object is pinned. Let's
12279          * be on the safe side and do this immediately before scheduling the
12280          * flip.
12281          */
12282         intel_fbc_pre_update(intel_crtc, intel_crtc->config,
12283                              to_intel_plane_state(primary->state));
12284
12285         if (mmio_flip) {
12286                 INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func);
12287                 queue_work(system_unbound_wq, &work->mmio_work);
12288         } else {
12289                 request = i915_gem_request_alloc(engine,
12290                                                  dev_priv->kernel_context);
12291                 if (IS_ERR(request)) {
12292                         ret = PTR_ERR(request);
12293                         goto cleanup_unpin;
12294                 }
12295
12296                 ret = i915_gem_request_await_object(request, obj, false);
12297                 if (ret)
12298                         goto cleanup_request;
12299
12300                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
12301                                                    page_flip_flags);
12302                 if (ret)
12303                         goto cleanup_request;
12304
12305                 intel_mark_page_flip_active(intel_crtc, work);
12306
12307                 work->flip_queued_req = i915_gem_request_get(request);
12308                 i915_add_request_no_flush(request);
12309         }
12310
12311         i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY);
12312         i915_gem_track_fb(intel_fb_obj(old_fb), obj,
12313                           to_intel_plane(primary)->frontbuffer_bit);
12314         mutex_unlock(&dev->struct_mutex);
12315
12316         intel_frontbuffer_flip_prepare(to_i915(dev),
12317                                        to_intel_plane(primary)->frontbuffer_bit);
12318
12319         trace_i915_flip_request(intel_crtc->plane, obj);
12320
12321         return 0;
12322
12323 cleanup_request:
12324         i915_add_request_no_flush(request);
12325 cleanup_unpin:
12326         to_intel_plane_state(primary->state)->vma = work->old_vma;
12327         intel_unpin_fb_vma(vma);
12328 cleanup_pending:
12329         atomic_dec(&intel_crtc->unpin_work_count);
12330 unlock:
12331         mutex_unlock(&dev->struct_mutex);
12332 cleanup:
12333         crtc->primary->fb = old_fb;
12334         update_state_fb(crtc->primary);
12335
12336         i915_gem_object_put(obj);
12337         drm_framebuffer_unreference(work->old_fb);
12338
12339         spin_lock_irq(&dev->event_lock);
12340         intel_crtc->flip_work = NULL;
12341         spin_unlock_irq(&dev->event_lock);
12342
12343         drm_crtc_vblank_put(crtc);
12344 free_work:
12345         kfree(work);
12346
12347         if (ret == -EIO) {
12348                 struct drm_atomic_state *state;
12349                 struct drm_plane_state *plane_state;
12350
12351 out_hang:
12352                 state = drm_atomic_state_alloc(dev);
12353                 if (!state)
12354                         return -ENOMEM;
12355                 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
12356
12357 retry:
12358                 plane_state = drm_atomic_get_plane_state(state, primary);
12359                 ret = PTR_ERR_OR_ZERO(plane_state);
12360                 if (!ret) {
12361                         drm_atomic_set_fb_for_plane(plane_state, fb);
12362
12363                         ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
12364                         if (!ret)
12365                                 ret = drm_atomic_commit(state);
12366                 }
12367
12368                 if (ret == -EDEADLK) {
12369                         drm_modeset_backoff(state->acquire_ctx);
12370                         drm_atomic_state_clear(state);
12371                         goto retry;
12372                 }
12373
12374                 drm_atomic_state_put(state);
12375
12376                 if (ret == 0 && event) {
12377                         spin_lock_irq(&dev->event_lock);
12378                         drm_crtc_send_vblank_event(crtc, event);
12379                         spin_unlock_irq(&dev->event_lock);
12380                 }
12381         }
12382         return ret;
12383 }
12384
12385
12386 /**
12387  * intel_wm_need_update - Check whether watermarks need updating
12388  * @plane: drm plane
12389  * @state: new plane state
12390  *
12391  * Check current plane state versus the new one to determine whether
12392  * watermarks need to be recalculated.
12393  *
12394  * Returns true or false.
12395  */
12396 static bool intel_wm_need_update(struct drm_plane *plane,
12397                                  struct drm_plane_state *state)
12398 {
12399         struct intel_plane_state *new = to_intel_plane_state(state);
12400         struct intel_plane_state *cur = to_intel_plane_state(plane->state);
12401
12402         /* Update watermarks on tiling or size changes. */
12403         if (new->base.visible != cur->base.visible)
12404                 return true;
12405
12406         if (!cur->base.fb || !new->base.fb)
12407                 return false;
12408
12409         if (cur->base.fb->modifier != new->base.fb->modifier ||
12410             cur->base.rotation != new->base.rotation ||
12411             drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) ||
12412             drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) ||
12413             drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) ||
12414             drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst))
12415                 return true;
12416
12417         return false;
12418 }
12419
12420 static bool needs_scaling(struct intel_plane_state *state)
12421 {
12422         int src_w = drm_rect_width(&state->base.src) >> 16;
12423         int src_h = drm_rect_height(&state->base.src) >> 16;
12424         int dst_w = drm_rect_width(&state->base.dst);
12425         int dst_h = drm_rect_height(&state->base.dst);
12426
12427         return (src_w != dst_w || src_h != dst_h);
12428 }
12429
12430 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
12431                                     struct drm_plane_state *plane_state)
12432 {
12433         struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
12434         struct drm_crtc *crtc = crtc_state->crtc;
12435         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12436         struct drm_plane *plane = plane_state->plane;
12437         struct drm_device *dev = crtc->dev;
12438         struct drm_i915_private *dev_priv = to_i915(dev);
12439         struct intel_plane_state *old_plane_state =
12440                 to_intel_plane_state(plane->state);
12441         bool mode_changed = needs_modeset(crtc_state);
12442         bool was_crtc_enabled = crtc->state->active;
12443         bool is_crtc_enabled = crtc_state->active;
12444         bool turn_off, turn_on, visible, was_visible;
12445         struct drm_framebuffer *fb = plane_state->fb;
12446         int ret;
12447
12448         if (INTEL_GEN(dev_priv) >= 9 && plane->type != DRM_PLANE_TYPE_CURSOR) {
12449                 ret = skl_update_scaler_plane(
12450                         to_intel_crtc_state(crtc_state),
12451                         to_intel_plane_state(plane_state));
12452                 if (ret)
12453                         return ret;
12454         }
12455
12456         was_visible = old_plane_state->base.visible;
12457         visible = plane_state->visible;
12458
12459         if (!was_crtc_enabled && WARN_ON(was_visible))
12460                 was_visible = false;
12461
12462         /*
12463          * Visibility is calculated as if the crtc was on, but
12464          * after scaler setup everything depends on it being off
12465          * when the crtc isn't active.
12466          *
12467          * FIXME this is wrong for watermarks. Watermarks should also
12468          * be computed as if the pipe would be active. Perhaps move
12469          * per-plane wm computation to the .check_plane() hook, and
12470          * only combine the results from all planes in the current place?
12471          */
12472         if (!is_crtc_enabled)
12473                 plane_state->visible = visible = false;
12474
12475         if (!was_visible && !visible)
12476                 return 0;
12477
12478         if (fb != old_plane_state->base.fb)
12479                 pipe_config->fb_changed = true;
12480
12481         turn_off = was_visible && (!visible || mode_changed);
12482         turn_on = visible && (!was_visible || mode_changed);
12483
12484         DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
12485                          intel_crtc->base.base.id,
12486                          intel_crtc->base.name,
12487                          plane->base.id, plane->name,
12488                          fb ? fb->base.id : -1);
12489
12490         DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
12491                          plane->base.id, plane->name,
12492                          was_visible, visible,
12493                          turn_off, turn_on, mode_changed);
12494
12495         if (turn_on) {
12496                 pipe_config->update_wm_pre = true;
12497
12498                 /* must disable cxsr around plane enable/disable */
12499                 if (plane->type != DRM_PLANE_TYPE_CURSOR)
12500                         pipe_config->disable_cxsr = true;
12501         } else if (turn_off) {
12502                 pipe_config->update_wm_post = true;
12503
12504                 /* must disable cxsr around plane enable/disable */
12505                 if (plane->type != DRM_PLANE_TYPE_CURSOR)
12506                         pipe_config->disable_cxsr = true;
12507         } else if (intel_wm_need_update(plane, plane_state)) {
12508                 /* FIXME bollocks */
12509                 pipe_config->update_wm_pre = true;
12510                 pipe_config->update_wm_post = true;
12511         }
12512
12513         /* Pre-gen9 platforms need two-step watermark updates */
12514         if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) &&
12515             INTEL_GEN(dev_priv) < 9 && dev_priv->display.optimize_watermarks)
12516                 to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true;
12517
12518         if (visible || was_visible)
12519                 pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit;
12520
12521         /*
12522          * WaCxSRDisabledForSpriteScaling:ivb
12523          *
12524          * cstate->update_wm was already set above, so this flag will
12525          * take effect when we commit and program watermarks.
12526          */
12527         if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev_priv) &&
12528             needs_scaling(to_intel_plane_state(plane_state)) &&
12529             !needs_scaling(old_plane_state))
12530                 pipe_config->disable_lp_wm = true;
12531
12532         return 0;
12533 }
12534
12535 static bool encoders_cloneable(const struct intel_encoder *a,
12536                                const struct intel_encoder *b)
12537 {
12538         /* masks could be asymmetric, so check both ways */
12539         return a == b || (a->cloneable & (1 << b->type) &&
12540                           b->cloneable & (1 << a->type));
12541 }
12542
12543 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
12544                                          struct intel_crtc *crtc,
12545                                          struct intel_encoder *encoder)
12546 {
12547         struct intel_encoder *source_encoder;
12548         struct drm_connector *connector;
12549         struct drm_connector_state *connector_state;
12550         int i;
12551
12552         for_each_connector_in_state(state, connector, connector_state, i) {
12553                 if (connector_state->crtc != &crtc->base)
12554                         continue;
12555
12556                 source_encoder =
12557                         to_intel_encoder(connector_state->best_encoder);
12558                 if (!encoders_cloneable(encoder, source_encoder))
12559                         return false;
12560         }
12561
12562         return true;
12563 }
12564
12565 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
12566                                    struct drm_crtc_state *crtc_state)
12567 {
12568         struct drm_device *dev = crtc->dev;
12569         struct drm_i915_private *dev_priv = to_i915(dev);
12570         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12571         struct intel_crtc_state *pipe_config =
12572                 to_intel_crtc_state(crtc_state);
12573         struct drm_atomic_state *state = crtc_state->state;
12574         int ret;
12575         bool mode_changed = needs_modeset(crtc_state);
12576
12577         if (mode_changed && !crtc_state->active)
12578                 pipe_config->update_wm_post = true;
12579
12580         if (mode_changed && crtc_state->enable &&
12581             dev_priv->display.crtc_compute_clock &&
12582             !WARN_ON(pipe_config->shared_dpll)) {
12583                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
12584                                                            pipe_config);
12585                 if (ret)
12586                         return ret;
12587         }
12588
12589         if (crtc_state->color_mgmt_changed) {
12590                 ret = intel_color_check(crtc, crtc_state);
12591                 if (ret)
12592                         return ret;
12593
12594                 /*
12595                  * Changing color management on Intel hardware is
12596                  * handled as part of planes update.
12597                  */
12598                 crtc_state->planes_changed = true;
12599         }
12600
12601         ret = 0;
12602         if (dev_priv->display.compute_pipe_wm) {
12603                 ret = dev_priv->display.compute_pipe_wm(pipe_config);
12604                 if (ret) {
12605                         DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
12606                         return ret;
12607                 }
12608         }
12609
12610         if (dev_priv->display.compute_intermediate_wm &&
12611             !to_intel_atomic_state(state)->skip_intermediate_wm) {
12612                 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
12613                         return 0;
12614
12615                 /*
12616                  * Calculate 'intermediate' watermarks that satisfy both the
12617                  * old state and the new state.  We can program these
12618                  * immediately.
12619                  */
12620                 ret = dev_priv->display.compute_intermediate_wm(dev,
12621                                                                 intel_crtc,
12622                                                                 pipe_config);
12623                 if (ret) {
12624                         DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
12625                         return ret;
12626                 }
12627         } else if (dev_priv->display.compute_intermediate_wm) {
12628                 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
12629                         pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
12630         }
12631
12632         if (INTEL_GEN(dev_priv) >= 9) {
12633                 if (mode_changed)
12634                         ret = skl_update_scaler_crtc(pipe_config);
12635
12636                 if (!ret)
12637                         ret = intel_atomic_setup_scalers(dev, intel_crtc,
12638                                                          pipe_config);
12639         }
12640
12641         return ret;
12642 }
12643
12644 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
12645         .mode_set_base_atomic = intel_pipe_set_base_atomic,
12646         .atomic_begin = intel_begin_crtc_commit,
12647         .atomic_flush = intel_finish_crtc_commit,
12648         .atomic_check = intel_crtc_atomic_check,
12649 };
12650
12651 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
12652 {
12653         struct intel_connector *connector;
12654
12655         for_each_intel_connector(dev, connector) {
12656                 if (connector->base.state->crtc)
12657                         drm_connector_unreference(&connector->base);
12658
12659                 if (connector->base.encoder) {
12660                         connector->base.state->best_encoder =
12661                                 connector->base.encoder;
12662                         connector->base.state->crtc =
12663                                 connector->base.encoder->crtc;
12664
12665                         drm_connector_reference(&connector->base);
12666                 } else {
12667                         connector->base.state->best_encoder = NULL;
12668                         connector->base.state->crtc = NULL;
12669                 }
12670         }
12671 }
12672
12673 static void
12674 connected_sink_compute_bpp(struct intel_connector *connector,
12675                            struct intel_crtc_state *pipe_config)
12676 {
12677         const struct drm_display_info *info = &connector->base.display_info;
12678         int bpp = pipe_config->pipe_bpp;
12679
12680         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
12681                       connector->base.base.id,
12682                       connector->base.name);
12683
12684         /* Don't use an invalid EDID bpc value */
12685         if (info->bpc != 0 && info->bpc * 3 < bpp) {
12686                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
12687                               bpp, info->bpc * 3);
12688                 pipe_config->pipe_bpp = info->bpc * 3;
12689         }
12690
12691         /* Clamp bpp to 8 on screens without EDID 1.4 */
12692         if (info->bpc == 0 && bpp > 24) {
12693                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
12694                               bpp);
12695                 pipe_config->pipe_bpp = 24;
12696         }
12697 }
12698
12699 static int
12700 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12701                           struct intel_crtc_state *pipe_config)
12702 {
12703         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12704         struct drm_atomic_state *state;
12705         struct drm_connector *connector;
12706         struct drm_connector_state *connector_state;
12707         int bpp, i;
12708
12709         if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
12710             IS_CHERRYVIEW(dev_priv)))
12711                 bpp = 10*3;
12712         else if (INTEL_GEN(dev_priv) >= 5)
12713                 bpp = 12*3;
12714         else
12715                 bpp = 8*3;
12716
12717
12718         pipe_config->pipe_bpp = bpp;
12719
12720         state = pipe_config->base.state;
12721
12722         /* Clamp display bpp to EDID value */
12723         for_each_connector_in_state(state, connector, connector_state, i) {
12724                 if (connector_state->crtc != &crtc->base)
12725                         continue;
12726
12727                 connected_sink_compute_bpp(to_intel_connector(connector),
12728                                            pipe_config);
12729         }
12730
12731         return bpp;
12732 }
12733
12734 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12735 {
12736         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12737                         "type: 0x%x flags: 0x%x\n",
12738                 mode->crtc_clock,
12739                 mode->crtc_hdisplay, mode->crtc_hsync_start,
12740                 mode->crtc_hsync_end, mode->crtc_htotal,
12741                 mode->crtc_vdisplay, mode->crtc_vsync_start,
12742                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
12743 }
12744
12745 static inline void
12746 intel_dump_m_n_config(struct intel_crtc_state *pipe_config, char *id,
12747                       unsigned int lane_count, struct intel_link_m_n *m_n)
12748 {
12749         DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12750                       id, lane_count,
12751                       m_n->gmch_m, m_n->gmch_n,
12752                       m_n->link_m, m_n->link_n, m_n->tu);
12753 }
12754
12755 static void intel_dump_pipe_config(struct intel_crtc *crtc,
12756                                    struct intel_crtc_state *pipe_config,
12757                                    const char *context)
12758 {
12759         struct drm_device *dev = crtc->base.dev;
12760         struct drm_i915_private *dev_priv = to_i915(dev);
12761         struct drm_plane *plane;
12762         struct intel_plane *intel_plane;
12763         struct intel_plane_state *state;
12764         struct drm_framebuffer *fb;
12765
12766         DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n",
12767                       crtc->base.base.id, crtc->base.name, context);
12768
12769         DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
12770                       transcoder_name(pipe_config->cpu_transcoder),
12771                       pipe_config->pipe_bpp, pipe_config->dither);
12772
12773         if (pipe_config->has_pch_encoder)
12774                 intel_dump_m_n_config(pipe_config, "fdi",
12775                                       pipe_config->fdi_lanes,
12776                                       &pipe_config->fdi_m_n);
12777
12778         if (intel_crtc_has_dp_encoder(pipe_config)) {
12779                 intel_dump_m_n_config(pipe_config, "dp m_n",
12780                                 pipe_config->lane_count, &pipe_config->dp_m_n);
12781                 if (pipe_config->has_drrs)
12782                         intel_dump_m_n_config(pipe_config, "dp m2_n2",
12783                                               pipe_config->lane_count,
12784                                               &pipe_config->dp_m2_n2);
12785         }
12786
12787         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12788                       pipe_config->has_audio, pipe_config->has_infoframe);
12789
12790         DRM_DEBUG_KMS("requested mode:\n");
12791         drm_mode_debug_printmodeline(&pipe_config->base.mode);
12792         DRM_DEBUG_KMS("adjusted mode:\n");
12793         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12794         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12795         DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d\n",
12796                       pipe_config->port_clock,
12797                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12798
12799         if (INTEL_GEN(dev_priv) >= 9)
12800                 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12801                               crtc->num_scalers,
12802                               pipe_config->scaler_state.scaler_users,
12803                               pipe_config->scaler_state.scaler_id);
12804
12805         if (HAS_GMCH_DISPLAY(dev_priv))
12806                 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12807                               pipe_config->gmch_pfit.control,
12808                               pipe_config->gmch_pfit.pgm_ratios,
12809                               pipe_config->gmch_pfit.lvds_border_bits);
12810         else
12811                 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12812                               pipe_config->pch_pfit.pos,
12813                               pipe_config->pch_pfit.size,
12814                               enableddisabled(pipe_config->pch_pfit.enabled));
12815
12816         DRM_DEBUG_KMS("ips: %i, double wide: %i\n",
12817                       pipe_config->ips_enabled, pipe_config->double_wide);
12818
12819         intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
12820
12821         DRM_DEBUG_KMS("planes on this crtc\n");
12822         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12823                 struct drm_format_name_buf format_name;
12824                 intel_plane = to_intel_plane(plane);
12825                 if (intel_plane->pipe != crtc->pipe)
12826                         continue;
12827
12828                 state = to_intel_plane_state(plane->state);
12829                 fb = state->base.fb;
12830                 if (!fb) {
12831                         DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
12832                                       plane->base.id, plane->name, state->scaler_id);
12833                         continue;
12834                 }
12835
12836                 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d, fb = %ux%u format = %s\n",
12837                               plane->base.id, plane->name,
12838                               fb->base.id, fb->width, fb->height,
12839                               drm_get_format_name(fb->format->format, &format_name));
12840                 if (INTEL_GEN(dev_priv) >= 9)
12841                         DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
12842                                       state->scaler_id,
12843                                       state->base.src.x1 >> 16,
12844                                       state->base.src.y1 >> 16,
12845                                       drm_rect_width(&state->base.src) >> 16,
12846                                       drm_rect_height(&state->base.src) >> 16,
12847                                       state->base.dst.x1, state->base.dst.y1,
12848                                       drm_rect_width(&state->base.dst),
12849                                       drm_rect_height(&state->base.dst));
12850         }
12851 }
12852
12853 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12854 {
12855         struct drm_device *dev = state->dev;
12856         struct drm_connector *connector;
12857         unsigned int used_ports = 0;
12858         unsigned int used_mst_ports = 0;
12859
12860         /*
12861          * Walk the connector list instead of the encoder
12862          * list to detect the problem on ddi platforms
12863          * where there's just one encoder per digital port.
12864          */
12865         drm_for_each_connector(connector, dev) {
12866                 struct drm_connector_state *connector_state;
12867                 struct intel_encoder *encoder;
12868
12869                 connector_state = drm_atomic_get_existing_connector_state(state, connector);
12870                 if (!connector_state)
12871                         connector_state = connector->state;
12872
12873                 if (!connector_state->best_encoder)
12874                         continue;
12875
12876                 encoder = to_intel_encoder(connector_state->best_encoder);
12877
12878                 WARN_ON(!connector_state->crtc);
12879
12880                 switch (encoder->type) {
12881                         unsigned int port_mask;
12882                 case INTEL_OUTPUT_UNKNOWN:
12883                         if (WARN_ON(!HAS_DDI(to_i915(dev))))
12884                                 break;
12885                 case INTEL_OUTPUT_DP:
12886                 case INTEL_OUTPUT_HDMI:
12887                 case INTEL_OUTPUT_EDP:
12888                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12889
12890                         /* the same port mustn't appear more than once */
12891                         if (used_ports & port_mask)
12892                                 return false;
12893
12894                         used_ports |= port_mask;
12895                         break;
12896                 case INTEL_OUTPUT_DP_MST:
12897                         used_mst_ports |=
12898                                 1 << enc_to_mst(&encoder->base)->primary->port;
12899                         break;
12900                 default:
12901                         break;
12902                 }
12903         }
12904
12905         /* can't mix MST and SST/HDMI on the same port */
12906         if (used_ports & used_mst_ports)
12907                 return false;
12908
12909         return true;
12910 }
12911
12912 static void
12913 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12914 {
12915         struct drm_crtc_state tmp_state;
12916         struct intel_crtc_scaler_state scaler_state;
12917         struct intel_dpll_hw_state dpll_hw_state;
12918         struct intel_shared_dpll *shared_dpll;
12919         bool force_thru;
12920
12921         /* FIXME: before the switch to atomic started, a new pipe_config was
12922          * kzalloc'd. Code that depends on any field being zero should be
12923          * fixed, so that the crtc_state can be safely duplicated. For now,
12924          * only fields that are know to not cause problems are preserved. */
12925
12926         tmp_state = crtc_state->base;
12927         scaler_state = crtc_state->scaler_state;
12928         shared_dpll = crtc_state->shared_dpll;
12929         dpll_hw_state = crtc_state->dpll_hw_state;
12930         force_thru = crtc_state->pch_pfit.force_thru;
12931
12932         memset(crtc_state, 0, sizeof *crtc_state);
12933
12934         crtc_state->base = tmp_state;
12935         crtc_state->scaler_state = scaler_state;
12936         crtc_state->shared_dpll = shared_dpll;
12937         crtc_state->dpll_hw_state = dpll_hw_state;
12938         crtc_state->pch_pfit.force_thru = force_thru;
12939 }
12940
12941 static int
12942 intel_modeset_pipe_config(struct drm_crtc *crtc,
12943                           struct intel_crtc_state *pipe_config)
12944 {
12945         struct drm_atomic_state *state = pipe_config->base.state;
12946         struct intel_encoder *encoder;
12947         struct drm_connector *connector;
12948         struct drm_connector_state *connector_state;
12949         int base_bpp, ret = -EINVAL;
12950         int i;
12951         bool retry = true;
12952
12953         clear_intel_crtc_state(pipe_config);
12954
12955         pipe_config->cpu_transcoder =
12956                 (enum transcoder) to_intel_crtc(crtc)->pipe;
12957
12958         /*
12959          * Sanitize sync polarity flags based on requested ones. If neither
12960          * positive or negative polarity is requested, treat this as meaning
12961          * negative polarity.
12962          */
12963         if (!(pipe_config->base.adjusted_mode.flags &
12964               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12965                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12966
12967         if (!(pipe_config->base.adjusted_mode.flags &
12968               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12969                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12970
12971         base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12972                                              pipe_config);
12973         if (base_bpp < 0)
12974                 goto fail;
12975
12976         /*
12977          * Determine the real pipe dimensions. Note that stereo modes can
12978          * increase the actual pipe size due to the frame doubling and
12979          * insertion of additional space for blanks between the frame. This
12980          * is stored in the crtc timings. We use the requested mode to do this
12981          * computation to clearly distinguish it from the adjusted mode, which
12982          * can be changed by the connectors in the below retry loop.
12983          */
12984         drm_crtc_get_hv_timing(&pipe_config->base.mode,
12985                                &pipe_config->pipe_src_w,
12986                                &pipe_config->pipe_src_h);
12987
12988         for_each_connector_in_state(state, connector, connector_state, i) {
12989                 if (connector_state->crtc != crtc)
12990                         continue;
12991
12992                 encoder = to_intel_encoder(connector_state->best_encoder);
12993
12994                 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
12995                         DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
12996                         goto fail;
12997                 }
12998
12999                 /*
13000                  * Determine output_types before calling the .compute_config()
13001                  * hooks so that the hooks can use this information safely.
13002                  */
13003                 pipe_config->output_types |= 1 << encoder->type;
13004         }
13005
13006 encoder_retry:
13007         /* Ensure the port clock defaults are reset when retrying. */
13008         pipe_config->port_clock = 0;
13009         pipe_config->pixel_multiplier = 1;
13010
13011         /* Fill in default crtc timings, allow encoders to overwrite them. */
13012         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
13013                               CRTC_STEREO_DOUBLE);
13014
13015         /* Pass our mode to the connectors and the CRTC to give them a chance to
13016          * adjust it according to limitations or connector properties, and also
13017          * a chance to reject the mode entirely.
13018          */
13019         for_each_connector_in_state(state, connector, connector_state, i) {
13020                 if (connector_state->crtc != crtc)
13021                         continue;
13022
13023                 encoder = to_intel_encoder(connector_state->best_encoder);
13024
13025                 if (!(encoder->compute_config(encoder, pipe_config, connector_state))) {
13026                         DRM_DEBUG_KMS("Encoder config failure\n");
13027                         goto fail;
13028                 }
13029         }
13030
13031         /* Set default port clock if not overwritten by the encoder. Needs to be
13032          * done afterwards in case the encoder adjusts the mode. */
13033         if (!pipe_config->port_clock)
13034                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
13035                         * pipe_config->pixel_multiplier;
13036
13037         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
13038         if (ret < 0) {
13039                 DRM_DEBUG_KMS("CRTC fixup failed\n");
13040                 goto fail;
13041         }
13042
13043         if (ret == RETRY) {
13044                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
13045                         ret = -EINVAL;
13046                         goto fail;
13047                 }
13048
13049                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
13050                 retry = false;
13051                 goto encoder_retry;
13052         }
13053
13054         /* Dithering seems to not pass-through bits correctly when it should, so
13055          * only enable it on 6bpc panels. */
13056         pipe_config->dither = pipe_config->pipe_bpp == 6*3;
13057         DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
13058                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
13059
13060 fail:
13061         return ret;
13062 }
13063
13064 static void
13065 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
13066 {
13067         struct drm_crtc *crtc;
13068         struct drm_crtc_state *crtc_state;
13069         int i;
13070
13071         /* Double check state. */
13072         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13073                 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
13074
13075                 /* Update hwmode for vblank functions */
13076                 if (crtc->state->active)
13077                         crtc->hwmode = crtc->state->adjusted_mode;
13078                 else
13079                         crtc->hwmode.crtc_clock = 0;
13080
13081                 /*
13082                  * Update legacy state to satisfy fbc code. This can
13083                  * be removed when fbc uses the atomic state.
13084                  */
13085                 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
13086                         struct drm_plane_state *plane_state = crtc->primary->state;
13087
13088                         crtc->primary->fb = plane_state->fb;
13089                         crtc->x = plane_state->src_x >> 16;
13090                         crtc->y = plane_state->src_y >> 16;
13091                 }
13092         }
13093 }
13094
13095 static bool intel_fuzzy_clock_check(int clock1, int clock2)
13096 {
13097         int diff;
13098
13099         if (clock1 == clock2)
13100                 return true;
13101
13102         if (!clock1 || !clock2)
13103                 return false;
13104
13105         diff = abs(clock1 - clock2);
13106
13107         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
13108                 return true;
13109
13110         return false;
13111 }
13112
13113 static bool
13114 intel_compare_m_n(unsigned int m, unsigned int n,
13115                   unsigned int m2, unsigned int n2,
13116                   bool exact)
13117 {
13118         if (m == m2 && n == n2)
13119                 return true;
13120
13121         if (exact || !m || !n || !m2 || !n2)
13122                 return false;
13123
13124         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
13125
13126         if (n > n2) {
13127                 while (n > n2) {
13128                         m2 <<= 1;
13129                         n2 <<= 1;
13130                 }
13131         } else if (n < n2) {
13132                 while (n < n2) {
13133                         m <<= 1;
13134                         n <<= 1;
13135                 }
13136         }
13137
13138         if (n != n2)
13139                 return false;
13140
13141         return intel_fuzzy_clock_check(m, m2);
13142 }
13143
13144 static bool
13145 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
13146                        struct intel_link_m_n *m2_n2,
13147                        bool adjust)
13148 {
13149         if (m_n->tu == m2_n2->tu &&
13150             intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
13151                               m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
13152             intel_compare_m_n(m_n->link_m, m_n->link_n,
13153                               m2_n2->link_m, m2_n2->link_n, !adjust)) {
13154                 if (adjust)
13155                         *m2_n2 = *m_n;
13156
13157                 return true;
13158         }
13159
13160         return false;
13161 }
13162
13163 static void __printf(3, 4)
13164 pipe_config_err(bool adjust, const char *name, const char *format, ...)
13165 {
13166         char *level;
13167         unsigned int category;
13168         struct va_format vaf;
13169         va_list args;
13170
13171         if (adjust) {
13172                 level = KERN_DEBUG;
13173                 category = DRM_UT_KMS;
13174         } else {
13175                 level = KERN_ERR;
13176                 category = DRM_UT_NONE;
13177         }
13178
13179         va_start(args, format);
13180         vaf.fmt = format;
13181         vaf.va = &args;
13182
13183         drm_printk(level, category, "mismatch in %s %pV", name, &vaf);
13184
13185         va_end(args);
13186 }
13187
13188 static bool
13189 intel_pipe_config_compare(struct drm_i915_private *dev_priv,
13190                           struct intel_crtc_state *current_config,
13191                           struct intel_crtc_state *pipe_config,
13192                           bool adjust)
13193 {
13194         bool ret = true;
13195
13196 #define PIPE_CONF_CHECK_X(name) \
13197         if (current_config->name != pipe_config->name) { \
13198                 pipe_config_err(adjust, __stringify(name), \
13199                           "(expected 0x%08x, found 0x%08x)\n", \
13200                           current_config->name, \
13201                           pipe_config->name); \
13202                 ret = false; \
13203         }
13204
13205 #define PIPE_CONF_CHECK_I(name) \
13206         if (current_config->name != pipe_config->name) { \
13207                 pipe_config_err(adjust, __stringify(name), \
13208                           "(expected %i, found %i)\n", \
13209                           current_config->name, \
13210                           pipe_config->name); \
13211                 ret = false; \
13212         }
13213
13214 #define PIPE_CONF_CHECK_P(name) \
13215         if (current_config->name != pipe_config->name) { \
13216                 pipe_config_err(adjust, __stringify(name), \
13217                           "(expected %p, found %p)\n", \
13218                           current_config->name, \
13219                           pipe_config->name); \
13220                 ret = false; \
13221         }
13222
13223 #define PIPE_CONF_CHECK_M_N(name) \
13224         if (!intel_compare_link_m_n(&current_config->name, \
13225                                     &pipe_config->name,\
13226                                     adjust)) { \
13227                 pipe_config_err(adjust, __stringify(name), \
13228                           "(expected tu %i gmch %i/%i link %i/%i, " \
13229                           "found tu %i, gmch %i/%i link %i/%i)\n", \
13230                           current_config->name.tu, \
13231                           current_config->name.gmch_m, \
13232                           current_config->name.gmch_n, \
13233                           current_config->name.link_m, \
13234                           current_config->name.link_n, \
13235                           pipe_config->name.tu, \
13236                           pipe_config->name.gmch_m, \
13237                           pipe_config->name.gmch_n, \
13238                           pipe_config->name.link_m, \
13239                           pipe_config->name.link_n); \
13240                 ret = false; \
13241         }
13242
13243 /* This is required for BDW+ where there is only one set of registers for
13244  * switching between high and low RR.
13245  * This macro can be used whenever a comparison has to be made between one
13246  * hw state and multiple sw state variables.
13247  */
13248 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
13249         if (!intel_compare_link_m_n(&current_config->name, \
13250                                     &pipe_config->name, adjust) && \
13251             !intel_compare_link_m_n(&current_config->alt_name, \
13252                                     &pipe_config->name, adjust)) { \
13253                 pipe_config_err(adjust, __stringify(name), \
13254                           "(expected tu %i gmch %i/%i link %i/%i, " \
13255                           "or tu %i gmch %i/%i link %i/%i, " \
13256                           "found tu %i, gmch %i/%i link %i/%i)\n", \
13257                           current_config->name.tu, \
13258                           current_config->name.gmch_m, \
13259                           current_config->name.gmch_n, \
13260                           current_config->name.link_m, \
13261                           current_config->name.link_n, \
13262                           current_config->alt_name.tu, \
13263                           current_config->alt_name.gmch_m, \
13264                           current_config->alt_name.gmch_n, \
13265                           current_config->alt_name.link_m, \
13266                           current_config->alt_name.link_n, \
13267                           pipe_config->name.tu, \
13268                           pipe_config->name.gmch_m, \
13269                           pipe_config->name.gmch_n, \
13270                           pipe_config->name.link_m, \
13271                           pipe_config->name.link_n); \
13272                 ret = false; \
13273         }
13274
13275 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
13276         if ((current_config->name ^ pipe_config->name) & (mask)) { \
13277                 pipe_config_err(adjust, __stringify(name), \
13278                           "(%x) (expected %i, found %i)\n", \
13279                           (mask), \
13280                           current_config->name & (mask), \
13281                           pipe_config->name & (mask)); \
13282                 ret = false; \
13283         }
13284
13285 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
13286         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
13287                 pipe_config_err(adjust, __stringify(name), \
13288                           "(expected %i, found %i)\n", \
13289                           current_config->name, \
13290                           pipe_config->name); \
13291                 ret = false; \
13292         }
13293
13294 #define PIPE_CONF_QUIRK(quirk)  \
13295         ((current_config->quirks | pipe_config->quirks) & (quirk))
13296
13297         PIPE_CONF_CHECK_I(cpu_transcoder);
13298
13299         PIPE_CONF_CHECK_I(has_pch_encoder);
13300         PIPE_CONF_CHECK_I(fdi_lanes);
13301         PIPE_CONF_CHECK_M_N(fdi_m_n);
13302
13303         PIPE_CONF_CHECK_I(lane_count);
13304         PIPE_CONF_CHECK_X(lane_lat_optim_mask);
13305
13306         if (INTEL_GEN(dev_priv) < 8) {
13307                 PIPE_CONF_CHECK_M_N(dp_m_n);
13308
13309                 if (current_config->has_drrs)
13310                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
13311         } else
13312                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
13313
13314         PIPE_CONF_CHECK_X(output_types);
13315
13316         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
13317         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
13318         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
13319         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
13320         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
13321         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
13322
13323         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
13324         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
13325         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
13326         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
13327         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
13328         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
13329
13330         PIPE_CONF_CHECK_I(pixel_multiplier);
13331         PIPE_CONF_CHECK_I(has_hdmi_sink);
13332         if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
13333             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13334                 PIPE_CONF_CHECK_I(limited_color_range);
13335         PIPE_CONF_CHECK_I(has_infoframe);
13336
13337         PIPE_CONF_CHECK_I(has_audio);
13338
13339         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13340                               DRM_MODE_FLAG_INTERLACE);
13341
13342         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
13343                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13344                                       DRM_MODE_FLAG_PHSYNC);
13345                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13346                                       DRM_MODE_FLAG_NHSYNC);
13347                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13348                                       DRM_MODE_FLAG_PVSYNC);
13349                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13350                                       DRM_MODE_FLAG_NVSYNC);
13351         }
13352
13353         PIPE_CONF_CHECK_X(gmch_pfit.control);
13354         /* pfit ratios are autocomputed by the hw on gen4+ */
13355         if (INTEL_GEN(dev_priv) < 4)
13356                 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
13357         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
13358
13359         if (!adjust) {
13360                 PIPE_CONF_CHECK_I(pipe_src_w);
13361                 PIPE_CONF_CHECK_I(pipe_src_h);
13362
13363                 PIPE_CONF_CHECK_I(pch_pfit.enabled);
13364                 if (current_config->pch_pfit.enabled) {
13365                         PIPE_CONF_CHECK_X(pch_pfit.pos);
13366                         PIPE_CONF_CHECK_X(pch_pfit.size);
13367                 }
13368
13369                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
13370         }
13371
13372         /* BDW+ don't expose a synchronous way to read the state */
13373         if (IS_HASWELL(dev_priv))
13374                 PIPE_CONF_CHECK_I(ips_enabled);
13375
13376         PIPE_CONF_CHECK_I(double_wide);
13377
13378         PIPE_CONF_CHECK_P(shared_dpll);
13379         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
13380         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
13381         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
13382         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
13383         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
13384         PIPE_CONF_CHECK_X(dpll_hw_state.spll);
13385         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
13386         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
13387         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
13388
13389         PIPE_CONF_CHECK_X(dsi_pll.ctrl);
13390         PIPE_CONF_CHECK_X(dsi_pll.div);
13391
13392         if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
13393                 PIPE_CONF_CHECK_I(pipe_bpp);
13394
13395         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
13396         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
13397
13398 #undef PIPE_CONF_CHECK_X
13399 #undef PIPE_CONF_CHECK_I
13400 #undef PIPE_CONF_CHECK_P
13401 #undef PIPE_CONF_CHECK_FLAGS
13402 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
13403 #undef PIPE_CONF_QUIRK
13404
13405         return ret;
13406 }
13407
13408 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
13409                                            const struct intel_crtc_state *pipe_config)
13410 {
13411         if (pipe_config->has_pch_encoder) {
13412                 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
13413                                                             &pipe_config->fdi_m_n);
13414                 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
13415
13416                 /*
13417                  * FDI already provided one idea for the dotclock.
13418                  * Yell if the encoder disagrees.
13419                  */
13420                 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
13421                      "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
13422                      fdi_dotclock, dotclock);
13423         }
13424 }
13425
13426 static void verify_wm_state(struct drm_crtc *crtc,
13427                             struct drm_crtc_state *new_state)
13428 {
13429         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
13430         struct skl_ddb_allocation hw_ddb, *sw_ddb;
13431         struct skl_pipe_wm hw_wm, *sw_wm;
13432         struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
13433         struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
13434         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13435         const enum pipe pipe = intel_crtc->pipe;
13436         int plane, level, max_level = ilk_wm_max_level(dev_priv);
13437
13438         if (INTEL_GEN(dev_priv) < 9 || !new_state->active)
13439                 return;
13440
13441         skl_pipe_wm_get_hw_state(crtc, &hw_wm);
13442         sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal;
13443
13444         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
13445         sw_ddb = &dev_priv->wm.skl_hw.ddb;
13446
13447         /* planes */
13448         for_each_universal_plane(dev_priv, pipe, plane) {
13449                 hw_plane_wm = &hw_wm.planes[plane];
13450                 sw_plane_wm = &sw_wm->planes[plane];
13451
13452                 /* Watermarks */
13453                 for (level = 0; level <= max_level; level++) {
13454                         if (skl_wm_level_equals(&hw_plane_wm->wm[level],
13455                                                 &sw_plane_wm->wm[level]))
13456                                 continue;
13457
13458                         DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
13459                                   pipe_name(pipe), plane + 1, level,
13460                                   sw_plane_wm->wm[level].plane_en,
13461                                   sw_plane_wm->wm[level].plane_res_b,
13462                                   sw_plane_wm->wm[level].plane_res_l,
13463                                   hw_plane_wm->wm[level].plane_en,
13464                                   hw_plane_wm->wm[level].plane_res_b,
13465                                   hw_plane_wm->wm[level].plane_res_l);
13466                 }
13467
13468                 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
13469                                          &sw_plane_wm->trans_wm)) {
13470                         DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
13471                                   pipe_name(pipe), plane + 1,
13472                                   sw_plane_wm->trans_wm.plane_en,
13473                                   sw_plane_wm->trans_wm.plane_res_b,
13474                                   sw_plane_wm->trans_wm.plane_res_l,
13475                                   hw_plane_wm->trans_wm.plane_en,
13476                                   hw_plane_wm->trans_wm.plane_res_b,
13477                                   hw_plane_wm->trans_wm.plane_res_l);
13478                 }
13479
13480                 /* DDB */
13481                 hw_ddb_entry = &hw_ddb.plane[pipe][plane];
13482                 sw_ddb_entry = &sw_ddb->plane[pipe][plane];
13483
13484                 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
13485                         DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
13486                                   pipe_name(pipe), plane + 1,
13487                                   sw_ddb_entry->start, sw_ddb_entry->end,
13488                                   hw_ddb_entry->start, hw_ddb_entry->end);
13489                 }
13490         }
13491
13492         /*
13493          * cursor
13494          * If the cursor plane isn't active, we may not have updated it's ddb
13495          * allocation. In that case since the ddb allocation will be updated
13496          * once the plane becomes visible, we can skip this check
13497          */
13498         if (intel_crtc->cursor_addr) {
13499                 hw_plane_wm = &hw_wm.planes[PLANE_CURSOR];
13500                 sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
13501
13502                 /* Watermarks */
13503                 for (level = 0; level <= max_level; level++) {
13504                         if (skl_wm_level_equals(&hw_plane_wm->wm[level],
13505                                                 &sw_plane_wm->wm[level]))
13506                                 continue;
13507
13508                         DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
13509                                   pipe_name(pipe), level,
13510                                   sw_plane_wm->wm[level].plane_en,
13511                                   sw_plane_wm->wm[level].plane_res_b,
13512                                   sw_plane_wm->wm[level].plane_res_l,
13513                                   hw_plane_wm->wm[level].plane_en,
13514                                   hw_plane_wm->wm[level].plane_res_b,
13515                                   hw_plane_wm->wm[level].plane_res_l);
13516                 }
13517
13518                 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
13519                                          &sw_plane_wm->trans_wm)) {
13520                         DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
13521                                   pipe_name(pipe),
13522                                   sw_plane_wm->trans_wm.plane_en,
13523                                   sw_plane_wm->trans_wm.plane_res_b,
13524                                   sw_plane_wm->trans_wm.plane_res_l,
13525                                   hw_plane_wm->trans_wm.plane_en,
13526                                   hw_plane_wm->trans_wm.plane_res_b,
13527                                   hw_plane_wm->trans_wm.plane_res_l);
13528                 }
13529
13530                 /* DDB */
13531                 hw_ddb_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
13532                 sw_ddb_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
13533
13534                 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
13535                         DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
13536                                   pipe_name(pipe),
13537                                   sw_ddb_entry->start, sw_ddb_entry->end,
13538                                   hw_ddb_entry->start, hw_ddb_entry->end);
13539                 }
13540         }
13541 }
13542
13543 static void
13544 verify_connector_state(struct drm_device *dev,
13545                        struct drm_atomic_state *state,
13546                        struct drm_crtc *crtc)
13547 {
13548         struct drm_connector *connector;
13549         struct drm_connector_state *old_conn_state;
13550         int i;
13551
13552         for_each_connector_in_state(state, connector, old_conn_state, i) {
13553                 struct drm_encoder *encoder = connector->encoder;
13554                 struct drm_connector_state *state = connector->state;
13555
13556                 if (state->crtc != crtc)
13557                         continue;
13558
13559                 intel_connector_verify_state(to_intel_connector(connector));
13560
13561                 I915_STATE_WARN(state->best_encoder != encoder,
13562                      "connector's atomic encoder doesn't match legacy encoder\n");
13563         }
13564 }
13565
13566 static void
13567 verify_encoder_state(struct drm_device *dev)
13568 {
13569         struct intel_encoder *encoder;
13570         struct intel_connector *connector;
13571
13572         for_each_intel_encoder(dev, encoder) {
13573                 bool enabled = false;
13574                 enum pipe pipe;
13575
13576                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
13577                               encoder->base.base.id,
13578                               encoder->base.name);
13579
13580                 for_each_intel_connector(dev, connector) {
13581                         if (connector->base.state->best_encoder != &encoder->base)
13582                                 continue;
13583                         enabled = true;
13584
13585                         I915_STATE_WARN(connector->base.state->crtc !=
13586                                         encoder->base.crtc,
13587                              "connector's crtc doesn't match encoder crtc\n");
13588                 }
13589
13590                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
13591                      "encoder's enabled state mismatch "
13592                      "(expected %i, found %i)\n",
13593                      !!encoder->base.crtc, enabled);
13594
13595                 if (!encoder->base.crtc) {
13596                         bool active;
13597
13598                         active = encoder->get_hw_state(encoder, &pipe);
13599                         I915_STATE_WARN(active,
13600                              "encoder detached but still enabled on pipe %c.\n",
13601                              pipe_name(pipe));
13602                 }
13603         }
13604 }
13605
13606 static void
13607 verify_crtc_state(struct drm_crtc *crtc,
13608                   struct drm_crtc_state *old_crtc_state,
13609                   struct drm_crtc_state *new_crtc_state)
13610 {
13611         struct drm_device *dev = crtc->dev;
13612         struct drm_i915_private *dev_priv = to_i915(dev);
13613         struct intel_encoder *encoder;
13614         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13615         struct intel_crtc_state *pipe_config, *sw_config;
13616         struct drm_atomic_state *old_state;
13617         bool active;
13618
13619         old_state = old_crtc_state->state;
13620         __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
13621         pipe_config = to_intel_crtc_state(old_crtc_state);
13622         memset(pipe_config, 0, sizeof(*pipe_config));
13623         pipe_config->base.crtc = crtc;
13624         pipe_config->base.state = old_state;
13625
13626         DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
13627
13628         active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
13629
13630         /* hw state is inconsistent with the pipe quirk */
13631         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
13632             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
13633                 active = new_crtc_state->active;
13634
13635         I915_STATE_WARN(new_crtc_state->active != active,
13636              "crtc active state doesn't match with hw state "
13637              "(expected %i, found %i)\n", new_crtc_state->active, active);
13638
13639         I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
13640              "transitional active state does not match atomic hw state "
13641              "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
13642
13643         for_each_encoder_on_crtc(dev, crtc, encoder) {
13644                 enum pipe pipe;
13645
13646                 active = encoder->get_hw_state(encoder, &pipe);
13647                 I915_STATE_WARN(active != new_crtc_state->active,
13648                         "[ENCODER:%i] active %i with crtc active %i\n",
13649                         encoder->base.base.id, active, new_crtc_state->active);
13650
13651                 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
13652                                 "Encoder connected to wrong pipe %c\n",
13653                                 pipe_name(pipe));
13654
13655                 if (active) {
13656                         pipe_config->output_types |= 1 << encoder->type;
13657                         encoder->get_config(encoder, pipe_config);
13658                 }
13659         }
13660
13661         if (!new_crtc_state->active)
13662                 return;
13663
13664         intel_pipe_config_sanity_check(dev_priv, pipe_config);
13665
13666         sw_config = to_intel_crtc_state(crtc->state);
13667         if (!intel_pipe_config_compare(dev_priv, sw_config,
13668                                        pipe_config, false)) {
13669                 I915_STATE_WARN(1, "pipe state doesn't match!\n");
13670                 intel_dump_pipe_config(intel_crtc, pipe_config,
13671                                        "[hw state]");
13672                 intel_dump_pipe_config(intel_crtc, sw_config,
13673                                        "[sw state]");
13674         }
13675 }
13676
13677 static void
13678 verify_single_dpll_state(struct drm_i915_private *dev_priv,
13679                          struct intel_shared_dpll *pll,
13680                          struct drm_crtc *crtc,
13681                          struct drm_crtc_state *new_state)
13682 {
13683         struct intel_dpll_hw_state dpll_hw_state;
13684         unsigned crtc_mask;
13685         bool active;
13686
13687         memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
13688
13689         DRM_DEBUG_KMS("%s\n", pll->name);
13690
13691         active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
13692
13693         if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
13694                 I915_STATE_WARN(!pll->on && pll->active_mask,
13695                      "pll in active use but not on in sw tracking\n");
13696                 I915_STATE_WARN(pll->on && !pll->active_mask,
13697                      "pll is on but not used by any active crtc\n");
13698                 I915_STATE_WARN(pll->on != active,
13699                      "pll on state mismatch (expected %i, found %i)\n",
13700                      pll->on, active);
13701         }
13702
13703         if (!crtc) {
13704                 I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask,
13705                                 "more active pll users than references: %x vs %x\n",
13706                                 pll->active_mask, pll->state.crtc_mask);
13707
13708                 return;
13709         }
13710
13711         crtc_mask = 1 << drm_crtc_index(crtc);
13712
13713         if (new_state->active)
13714                 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
13715                                 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
13716                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
13717         else
13718                 I915_STATE_WARN(pll->active_mask & crtc_mask,
13719                                 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
13720                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
13721
13722         I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),
13723                         "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
13724                         crtc_mask, pll->state.crtc_mask);
13725
13726         I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
13727                                           &dpll_hw_state,
13728                                           sizeof(dpll_hw_state)),
13729                         "pll hw state mismatch\n");
13730 }
13731
13732 static void
13733 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
13734                          struct drm_crtc_state *old_crtc_state,
13735                          struct drm_crtc_state *new_crtc_state)
13736 {
13737         struct drm_i915_private *dev_priv = to_i915(dev);
13738         struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
13739         struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
13740
13741         if (new_state->shared_dpll)
13742                 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
13743
13744         if (old_state->shared_dpll &&
13745             old_state->shared_dpll != new_state->shared_dpll) {
13746                 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
13747                 struct intel_shared_dpll *pll = old_state->shared_dpll;
13748
13749                 I915_STATE_WARN(pll->active_mask & crtc_mask,
13750                                 "pll active mismatch (didn't expect pipe %c in active mask)\n",
13751                                 pipe_name(drm_crtc_index(crtc)));
13752                 I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,
13753                                 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
13754                                 pipe_name(drm_crtc_index(crtc)));
13755         }
13756 }
13757
13758 static void
13759 intel_modeset_verify_crtc(struct drm_crtc *crtc,
13760                           struct drm_atomic_state *state,
13761                           struct drm_crtc_state *old_state,
13762                           struct drm_crtc_state *new_state)
13763 {
13764         if (!needs_modeset(new_state) &&
13765             !to_intel_crtc_state(new_state)->update_pipe)
13766                 return;
13767
13768         verify_wm_state(crtc, new_state);
13769         verify_connector_state(crtc->dev, state, crtc);
13770         verify_crtc_state(crtc, old_state, new_state);
13771         verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
13772 }
13773
13774 static void
13775 verify_disabled_dpll_state(struct drm_device *dev)
13776 {
13777         struct drm_i915_private *dev_priv = to_i915(dev);
13778         int i;
13779
13780         for (i = 0; i < dev_priv->num_shared_dpll; i++)
13781                 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
13782 }
13783
13784 static void
13785 intel_modeset_verify_disabled(struct drm_device *dev,
13786                               struct drm_atomic_state *state)
13787 {
13788         verify_encoder_state(dev);
13789         verify_connector_state(dev, state, NULL);
13790         verify_disabled_dpll_state(dev);
13791 }
13792
13793 static void update_scanline_offset(struct intel_crtc *crtc)
13794 {
13795         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13796
13797         /*
13798          * The scanline counter increments at the leading edge of hsync.
13799          *
13800          * On most platforms it starts counting from vtotal-1 on the
13801          * first active line. That means the scanline counter value is
13802          * always one less than what we would expect. Ie. just after
13803          * start of vblank, which also occurs at start of hsync (on the
13804          * last active line), the scanline counter will read vblank_start-1.
13805          *
13806          * On gen2 the scanline counter starts counting from 1 instead
13807          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13808          * to keep the value positive), instead of adding one.
13809          *
13810          * On HSW+ the behaviour of the scanline counter depends on the output
13811          * type. For DP ports it behaves like most other platforms, but on HDMI
13812          * there's an extra 1 line difference. So we need to add two instead of
13813          * one to the value.
13814          */
13815         if (IS_GEN2(dev_priv)) {
13816                 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
13817                 int vtotal;
13818
13819                 vtotal = adjusted_mode->crtc_vtotal;
13820                 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
13821                         vtotal /= 2;
13822
13823                 crtc->scanline_offset = vtotal - 1;
13824         } else if (HAS_DDI(dev_priv) &&
13825                    intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
13826                 crtc->scanline_offset = 2;
13827         } else
13828                 crtc->scanline_offset = 1;
13829 }
13830
13831 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
13832 {
13833         struct drm_device *dev = state->dev;
13834         struct drm_i915_private *dev_priv = to_i915(dev);
13835         struct drm_crtc *crtc;
13836         struct drm_crtc_state *crtc_state;
13837         int i;
13838
13839         if (!dev_priv->display.crtc_compute_clock)
13840                 return;
13841
13842         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13843                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13844                 struct intel_shared_dpll *old_dpll =
13845                         to_intel_crtc_state(crtc->state)->shared_dpll;
13846
13847                 if (!needs_modeset(crtc_state))
13848                         continue;
13849
13850                 to_intel_crtc_state(crtc_state)->shared_dpll = NULL;
13851
13852                 if (!old_dpll)
13853                         continue;
13854
13855                 intel_release_shared_dpll(old_dpll, intel_crtc, state);
13856         }
13857 }
13858
13859 /*
13860  * This implements the workaround described in the "notes" section of the mode
13861  * set sequence documentation. When going from no pipes or single pipe to
13862  * multiple pipes, and planes are enabled after the pipe, we need to wait at
13863  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13864  */
13865 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13866 {
13867         struct drm_crtc_state *crtc_state;
13868         struct intel_crtc *intel_crtc;
13869         struct drm_crtc *crtc;
13870         struct intel_crtc_state *first_crtc_state = NULL;
13871         struct intel_crtc_state *other_crtc_state = NULL;
13872         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13873         int i;
13874
13875         /* look at all crtc's that are going to be enabled in during modeset */
13876         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13877                 intel_crtc = to_intel_crtc(crtc);
13878
13879                 if (!crtc_state->active || !needs_modeset(crtc_state))
13880                         continue;
13881
13882                 if (first_crtc_state) {
13883                         other_crtc_state = to_intel_crtc_state(crtc_state);
13884                         break;
13885                 } else {
13886                         first_crtc_state = to_intel_crtc_state(crtc_state);
13887                         first_pipe = intel_crtc->pipe;
13888                 }
13889         }
13890
13891         /* No workaround needed? */
13892         if (!first_crtc_state)
13893                 return 0;
13894
13895         /* w/a possibly needed, check how many crtc's are already enabled. */
13896         for_each_intel_crtc(state->dev, intel_crtc) {
13897                 struct intel_crtc_state *pipe_config;
13898
13899                 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13900                 if (IS_ERR(pipe_config))
13901                         return PTR_ERR(pipe_config);
13902
13903                 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13904
13905                 if (!pipe_config->base.active ||
13906                     needs_modeset(&pipe_config->base))
13907                         continue;
13908
13909                 /* 2 or more enabled crtcs means no need for w/a */
13910                 if (enabled_pipe != INVALID_PIPE)
13911                         return 0;
13912
13913                 enabled_pipe = intel_crtc->pipe;
13914         }
13915
13916         if (enabled_pipe != INVALID_PIPE)
13917                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13918         else if (other_crtc_state)
13919                 other_crtc_state->hsw_workaround_pipe = first_pipe;
13920
13921         return 0;
13922 }
13923
13924 static int intel_lock_all_pipes(struct drm_atomic_state *state)
13925 {
13926         struct drm_crtc *crtc;
13927
13928         /* Add all pipes to the state */
13929         for_each_crtc(state->dev, crtc) {
13930                 struct drm_crtc_state *crtc_state;
13931
13932                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13933                 if (IS_ERR(crtc_state))
13934                         return PTR_ERR(crtc_state);
13935         }
13936
13937         return 0;
13938 }
13939
13940 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13941 {
13942         struct drm_crtc *crtc;
13943
13944         /*
13945          * Add all pipes to the state, and force
13946          * a modeset on all the active ones.
13947          */
13948         for_each_crtc(state->dev, crtc) {
13949                 struct drm_crtc_state *crtc_state;
13950                 int ret;
13951
13952                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13953                 if (IS_ERR(crtc_state))
13954                         return PTR_ERR(crtc_state);
13955
13956                 if (!crtc_state->active || needs_modeset(crtc_state))
13957                         continue;
13958
13959                 crtc_state->mode_changed = true;
13960
13961                 ret = drm_atomic_add_affected_connectors(state, crtc);
13962                 if (ret)
13963                         return ret;
13964
13965                 ret = drm_atomic_add_affected_planes(state, crtc);
13966                 if (ret)
13967                         return ret;
13968         }
13969
13970         return 0;
13971 }
13972
13973 static int intel_modeset_checks(struct drm_atomic_state *state)
13974 {
13975         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13976         struct drm_i915_private *dev_priv = to_i915(state->dev);
13977         struct drm_crtc *crtc;
13978         struct drm_crtc_state *crtc_state;
13979         int ret = 0, i;
13980
13981         if (!check_digital_port_conflicts(state)) {
13982                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13983                 return -EINVAL;
13984         }
13985
13986         intel_state->modeset = true;
13987         intel_state->active_crtcs = dev_priv->active_crtcs;
13988
13989         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13990                 if (crtc_state->active)
13991                         intel_state->active_crtcs |= 1 << i;
13992                 else
13993                         intel_state->active_crtcs &= ~(1 << i);
13994
13995                 if (crtc_state->active != crtc->state->active)
13996                         intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
13997         }
13998
13999         /*
14000          * See if the config requires any additional preparation, e.g.
14001          * to adjust global state with pipes off.  We need to do this
14002          * here so we can get the modeset_pipe updated config for the new
14003          * mode set on this crtc.  For other crtcs we need to use the
14004          * adjusted_mode bits in the crtc directly.
14005          */
14006         if (dev_priv->display.modeset_calc_cdclk) {
14007                 if (!intel_state->cdclk_pll_vco)
14008                         intel_state->cdclk_pll_vco = dev_priv->cdclk_pll.vco;
14009                 if (!intel_state->cdclk_pll_vco)
14010                         intel_state->cdclk_pll_vco = dev_priv->skl_preferred_vco_freq;
14011
14012                 ret = dev_priv->display.modeset_calc_cdclk(state);
14013                 if (ret < 0)
14014                         return ret;
14015
14016                 /*
14017                  * Writes to dev_priv->atomic_cdclk_freq must protected by
14018                  * holding all the crtc locks, even if we don't end up
14019                  * touching the hardware
14020                  */
14021                 if (intel_state->cdclk != dev_priv->atomic_cdclk_freq) {
14022                         ret = intel_lock_all_pipes(state);
14023                         if (ret < 0)
14024                                 return ret;
14025                 }
14026
14027                 /* All pipes must be switched off while we change the cdclk. */
14028                 if (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
14029                     intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco) {
14030                         ret = intel_modeset_all_pipes(state);
14031                         if (ret < 0)
14032                                 return ret;
14033                 }
14034
14035                 DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n",
14036                               intel_state->cdclk, intel_state->dev_cdclk);
14037         } else {
14038                 to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq;
14039         }
14040
14041         intel_modeset_clear_plls(state);
14042
14043         if (IS_HASWELL(dev_priv))
14044                 return haswell_mode_set_planes_workaround(state);
14045
14046         return 0;
14047 }
14048
14049 /*
14050  * Handle calculation of various watermark data at the end of the atomic check
14051  * phase.  The code here should be run after the per-crtc and per-plane 'check'
14052  * handlers to ensure that all derived state has been updated.
14053  */
14054 static int calc_watermark_data(struct drm_atomic_state *state)
14055 {
14056         struct drm_device *dev = state->dev;
14057         struct drm_i915_private *dev_priv = to_i915(dev);
14058
14059         /* Is there platform-specific watermark information to calculate? */
14060         if (dev_priv->display.compute_global_watermarks)
14061                 return dev_priv->display.compute_global_watermarks(state);
14062
14063         return 0;
14064 }
14065
14066 /**
14067  * intel_atomic_check - validate state object
14068  * @dev: drm device
14069  * @state: state to validate
14070  */
14071 static int intel_atomic_check(struct drm_device *dev,
14072                               struct drm_atomic_state *state)
14073 {
14074         struct drm_i915_private *dev_priv = to_i915(dev);
14075         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14076         struct drm_crtc *crtc;
14077         struct drm_crtc_state *crtc_state;
14078         int ret, i;
14079         bool any_ms = false;
14080
14081         ret = drm_atomic_helper_check_modeset(dev, state);
14082         if (ret)
14083                 return ret;
14084
14085         for_each_crtc_in_state(state, crtc, crtc_state, i) {
14086                 struct intel_crtc_state *pipe_config =
14087                         to_intel_crtc_state(crtc_state);
14088
14089                 /* Catch I915_MODE_FLAG_INHERITED */
14090                 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
14091                         crtc_state->mode_changed = true;
14092
14093                 if (!needs_modeset(crtc_state))
14094                         continue;
14095
14096                 if (!crtc_state->enable) {
14097                         any_ms = true;
14098                         continue;
14099                 }
14100
14101                 /* FIXME: For only active_changed we shouldn't need to do any
14102                  * state recomputation at all. */
14103
14104                 ret = drm_atomic_add_affected_connectors(state, crtc);
14105                 if (ret)
14106                         return ret;
14107
14108                 ret = intel_modeset_pipe_config(crtc, pipe_config);
14109                 if (ret) {
14110                         intel_dump_pipe_config(to_intel_crtc(crtc),
14111                                                pipe_config, "[failed]");
14112                         return ret;
14113                 }
14114
14115                 if (i915.fastboot &&
14116                     intel_pipe_config_compare(dev_priv,
14117                                         to_intel_crtc_state(crtc->state),
14118                                         pipe_config, true)) {
14119                         crtc_state->mode_changed = false;
14120                         to_intel_crtc_state(crtc_state)->update_pipe = true;
14121                 }
14122
14123                 if (needs_modeset(crtc_state))
14124                         any_ms = true;
14125
14126                 ret = drm_atomic_add_affected_planes(state, crtc);
14127                 if (ret)
14128                         return ret;
14129
14130                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
14131                                        needs_modeset(crtc_state) ?
14132                                        "[modeset]" : "[fastset]");
14133         }
14134
14135         if (any_ms) {
14136                 ret = intel_modeset_checks(state);
14137
14138                 if (ret)
14139                         return ret;
14140         } else {
14141                 intel_state->cdclk = dev_priv->atomic_cdclk_freq;
14142         }
14143
14144         ret = drm_atomic_helper_check_planes(dev, state);
14145         if (ret)
14146                 return ret;
14147
14148         intel_fbc_choose_crtc(dev_priv, state);
14149         return calc_watermark_data(state);
14150 }
14151
14152 static int intel_atomic_prepare_commit(struct drm_device *dev,
14153                                        struct drm_atomic_state *state)
14154 {
14155         struct drm_i915_private *dev_priv = to_i915(dev);
14156         struct drm_crtc_state *crtc_state;
14157         struct drm_crtc *crtc;
14158         int i, ret;
14159
14160         for_each_crtc_in_state(state, crtc, crtc_state, i) {
14161                 if (state->legacy_cursor_update)
14162                         continue;
14163
14164                 ret = intel_crtc_wait_for_pending_flips(crtc);
14165                 if (ret)
14166                         return ret;
14167
14168                 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
14169                         flush_workqueue(dev_priv->wq);
14170         }
14171
14172         ret = mutex_lock_interruptible(&dev->struct_mutex);
14173         if (ret)
14174                 return ret;
14175
14176         ret = drm_atomic_helper_prepare_planes(dev, state);
14177         mutex_unlock(&dev->struct_mutex);
14178
14179         return ret;
14180 }
14181
14182 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
14183 {
14184         struct drm_device *dev = crtc->base.dev;
14185
14186         if (!dev->max_vblank_count)
14187                 return drm_accurate_vblank_count(&crtc->base);
14188
14189         return dev->driver->get_vblank_counter(dev, crtc->pipe);
14190 }
14191
14192 static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
14193                                           struct drm_i915_private *dev_priv,
14194                                           unsigned crtc_mask)
14195 {
14196         unsigned last_vblank_count[I915_MAX_PIPES];
14197         enum pipe pipe;
14198         int ret;
14199
14200         if (!crtc_mask)
14201                 return;
14202
14203         for_each_pipe(dev_priv, pipe) {
14204                 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
14205                                                                   pipe);
14206
14207                 if (!((1 << pipe) & crtc_mask))
14208                         continue;
14209
14210                 ret = drm_crtc_vblank_get(&crtc->base);
14211                 if (WARN_ON(ret != 0)) {
14212                         crtc_mask &= ~(1 << pipe);
14213                         continue;
14214                 }
14215
14216                 last_vblank_count[pipe] = drm_crtc_vblank_count(&crtc->base);
14217         }
14218
14219         for_each_pipe(dev_priv, pipe) {
14220                 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
14221                                                                   pipe);
14222                 long lret;
14223
14224                 if (!((1 << pipe) & crtc_mask))
14225                         continue;
14226
14227                 lret = wait_event_timeout(dev->vblank[pipe].queue,
14228                                 last_vblank_count[pipe] !=
14229                                         drm_crtc_vblank_count(&crtc->base),
14230                                 msecs_to_jiffies(50));
14231
14232                 WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe));
14233
14234                 drm_crtc_vblank_put(&crtc->base);
14235         }
14236 }
14237
14238 static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
14239 {
14240         /* fb updated, need to unpin old fb */
14241         if (crtc_state->fb_changed)
14242                 return true;
14243
14244         /* wm changes, need vblank before final wm's */
14245         if (crtc_state->update_wm_post)
14246                 return true;
14247
14248         /*
14249          * cxsr is re-enabled after vblank.
14250          * This is already handled by crtc_state->update_wm_post,
14251          * but added for clarity.
14252          */
14253         if (crtc_state->disable_cxsr)
14254                 return true;
14255
14256         return false;
14257 }
14258
14259 static void intel_update_crtc(struct drm_crtc *crtc,
14260                               struct drm_atomic_state *state,
14261                               struct drm_crtc_state *old_crtc_state,
14262                               unsigned int *crtc_vblank_mask)
14263 {
14264         struct drm_device *dev = crtc->dev;
14265         struct drm_i915_private *dev_priv = to_i915(dev);
14266         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14267         struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc->state);
14268         bool modeset = needs_modeset(crtc->state);
14269
14270         if (modeset) {
14271                 update_scanline_offset(intel_crtc);
14272                 dev_priv->display.crtc_enable(pipe_config, state);
14273         } else {
14274                 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
14275         }
14276
14277         if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
14278                 intel_fbc_enable(
14279                     intel_crtc, pipe_config,
14280                     to_intel_plane_state(crtc->primary->state));
14281         }
14282
14283         drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
14284
14285         if (needs_vblank_wait(pipe_config))
14286                 *crtc_vblank_mask |= drm_crtc_mask(crtc);
14287 }
14288
14289 static void intel_update_crtcs(struct drm_atomic_state *state,
14290                                unsigned int *crtc_vblank_mask)
14291 {
14292         struct drm_crtc *crtc;
14293         struct drm_crtc_state *old_crtc_state;
14294         int i;
14295
14296         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14297                 if (!crtc->state->active)
14298                         continue;
14299
14300                 intel_update_crtc(crtc, state, old_crtc_state,
14301                                   crtc_vblank_mask);
14302         }
14303 }
14304
14305 static void skl_update_crtcs(struct drm_atomic_state *state,
14306                              unsigned int *crtc_vblank_mask)
14307 {
14308         struct drm_i915_private *dev_priv = to_i915(state->dev);
14309         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14310         struct drm_crtc *crtc;
14311         struct intel_crtc *intel_crtc;
14312         struct drm_crtc_state *old_crtc_state;
14313         struct intel_crtc_state *cstate;
14314         unsigned int updated = 0;
14315         bool progress;
14316         enum pipe pipe;
14317         int i;
14318
14319         const struct skl_ddb_entry *entries[I915_MAX_PIPES] = {};
14320
14321         for_each_crtc_in_state(state, crtc, old_crtc_state, i)
14322                 /* ignore allocations for crtc's that have been turned off. */
14323                 if (crtc->state->active)
14324                         entries[i] = &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb;
14325
14326         /*
14327          * Whenever the number of active pipes changes, we need to make sure we
14328          * update the pipes in the right order so that their ddb allocations
14329          * never overlap with eachother inbetween CRTC updates. Otherwise we'll
14330          * cause pipe underruns and other bad stuff.
14331          */
14332         do {
14333                 progress = false;
14334
14335                 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14336                         bool vbl_wait = false;
14337                         unsigned int cmask = drm_crtc_mask(crtc);
14338
14339                         intel_crtc = to_intel_crtc(crtc);
14340                         cstate = to_intel_crtc_state(crtc->state);
14341                         pipe = intel_crtc->pipe;
14342
14343                         if (updated & cmask || !cstate->base.active)
14344                                 continue;
14345
14346                         if (skl_ddb_allocation_overlaps(entries, &cstate->wm.skl.ddb, i))
14347                                 continue;
14348
14349                         updated |= cmask;
14350                         entries[i] = &cstate->wm.skl.ddb;
14351
14352                         /*
14353                          * If this is an already active pipe, it's DDB changed,
14354                          * and this isn't the last pipe that needs updating
14355                          * then we need to wait for a vblank to pass for the
14356                          * new ddb allocation to take effect.
14357                          */
14358                         if (!skl_ddb_entry_equal(&cstate->wm.skl.ddb,
14359                                                  &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb) &&
14360                             !crtc->state->active_changed &&
14361                             intel_state->wm_results.dirty_pipes != updated)
14362                                 vbl_wait = true;
14363
14364                         intel_update_crtc(crtc, state, old_crtc_state,
14365                                           crtc_vblank_mask);
14366
14367                         if (vbl_wait)
14368                                 intel_wait_for_vblank(dev_priv, pipe);
14369
14370                         progress = true;
14371                 }
14372         } while (progress);
14373 }
14374
14375 static void intel_atomic_commit_tail(struct drm_atomic_state *state)
14376 {
14377         struct drm_device *dev = state->dev;
14378         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14379         struct drm_i915_private *dev_priv = to_i915(dev);
14380         struct drm_crtc_state *old_crtc_state;
14381         struct drm_crtc *crtc;
14382         struct intel_crtc_state *intel_cstate;
14383         bool hw_check = intel_state->modeset;
14384         unsigned long put_domains[I915_MAX_PIPES] = {};
14385         unsigned crtc_vblank_mask = 0;
14386         int i;
14387
14388         drm_atomic_helper_wait_for_dependencies(state);
14389
14390         if (intel_state->modeset)
14391                 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
14392
14393         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14394                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14395
14396                 if (needs_modeset(crtc->state) ||
14397                     to_intel_crtc_state(crtc->state)->update_pipe) {
14398                         hw_check = true;
14399
14400                         put_domains[to_intel_crtc(crtc)->pipe] =
14401                                 modeset_get_crtc_power_domains(crtc,
14402                                         to_intel_crtc_state(crtc->state));
14403                 }
14404
14405                 if (!needs_modeset(crtc->state))
14406                         continue;
14407
14408                 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
14409
14410                 if (old_crtc_state->active) {
14411                         intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
14412                         dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state);
14413                         intel_crtc->active = false;
14414                         intel_fbc_disable(intel_crtc);
14415                         intel_disable_shared_dpll(intel_crtc);
14416
14417                         /*
14418                          * Underruns don't always raise
14419                          * interrupts, so check manually.
14420                          */
14421                         intel_check_cpu_fifo_underruns(dev_priv);
14422                         intel_check_pch_fifo_underruns(dev_priv);
14423
14424                         if (!crtc->state->active) {
14425                                 /*
14426                                  * Make sure we don't call initial_watermarks
14427                                  * for ILK-style watermark updates.
14428                                  */
14429                                 if (dev_priv->display.atomic_update_watermarks)
14430                                         dev_priv->display.initial_watermarks(intel_state,
14431                                                                              to_intel_crtc_state(crtc->state));
14432                                 else
14433                                         intel_update_watermarks(intel_crtc);
14434                         }
14435                 }
14436         }
14437
14438         /* Only after disabling all output pipelines that will be changed can we
14439          * update the the output configuration. */
14440         intel_modeset_update_crtc_state(state);
14441
14442         if (intel_state->modeset) {
14443                 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
14444
14445                 if (dev_priv->display.modeset_commit_cdclk &&
14446                     (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
14447                      intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco))
14448                         dev_priv->display.modeset_commit_cdclk(state);
14449
14450                 /*
14451                  * SKL workaround: bspec recommends we disable the SAGV when we
14452                  * have more then one pipe enabled
14453                  */
14454                 if (!intel_can_enable_sagv(state))
14455                         intel_disable_sagv(dev_priv);
14456
14457                 intel_modeset_verify_disabled(dev, state);
14458         }
14459
14460         /* Complete the events for pipes that have now been disabled */
14461         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14462                 bool modeset = needs_modeset(crtc->state);
14463
14464                 /* Complete events for now disable pipes here. */
14465                 if (modeset && !crtc->state->active && crtc->state->event) {
14466                         spin_lock_irq(&dev->event_lock);
14467                         drm_crtc_send_vblank_event(crtc, crtc->state->event);
14468                         spin_unlock_irq(&dev->event_lock);
14469
14470                         crtc->state->event = NULL;
14471                 }
14472         }
14473
14474         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
14475         dev_priv->display.update_crtcs(state, &crtc_vblank_mask);
14476
14477         /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
14478          * already, but still need the state for the delayed optimization. To
14479          * fix this:
14480          * - wrap the optimization/post_plane_update stuff into a per-crtc work.
14481          * - schedule that vblank worker _before_ calling hw_done
14482          * - at the start of commit_tail, cancel it _synchrously
14483          * - switch over to the vblank wait helper in the core after that since
14484          *   we don't need out special handling any more.
14485          */
14486         if (!state->legacy_cursor_update)
14487                 intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
14488
14489         /*
14490          * Now that the vblank has passed, we can go ahead and program the
14491          * optimal watermarks on platforms that need two-step watermark
14492          * programming.
14493          *
14494          * TODO: Move this (and other cleanup) to an async worker eventually.
14495          */
14496         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14497                 intel_cstate = to_intel_crtc_state(crtc->state);
14498
14499                 if (dev_priv->display.optimize_watermarks)
14500                         dev_priv->display.optimize_watermarks(intel_state,
14501                                                               intel_cstate);
14502         }
14503
14504         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14505                 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
14506
14507                 if (put_domains[i])
14508                         modeset_put_power_domains(dev_priv, put_domains[i]);
14509
14510                 intel_modeset_verify_crtc(crtc, state, old_crtc_state, crtc->state);
14511         }
14512
14513         if (intel_state->modeset && intel_can_enable_sagv(state))
14514                 intel_enable_sagv(dev_priv);
14515
14516         drm_atomic_helper_commit_hw_done(state);
14517
14518         if (intel_state->modeset)
14519                 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
14520
14521         mutex_lock(&dev->struct_mutex);
14522         drm_atomic_helper_cleanup_planes(dev, state);
14523         mutex_unlock(&dev->struct_mutex);
14524
14525         drm_atomic_helper_commit_cleanup_done(state);
14526
14527         drm_atomic_state_put(state);
14528
14529         /* As one of the primary mmio accessors, KMS has a high likelihood
14530          * of triggering bugs in unclaimed access. After we finish
14531          * modesetting, see if an error has been flagged, and if so
14532          * enable debugging for the next modeset - and hope we catch
14533          * the culprit.
14534          *
14535          * XXX note that we assume display power is on at this point.
14536          * This might hold true now but we need to add pm helper to check
14537          * unclaimed only when the hardware is on, as atomic commits
14538          * can happen also when the device is completely off.
14539          */
14540         intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
14541 }
14542
14543 static void intel_atomic_commit_work(struct work_struct *work)
14544 {
14545         struct drm_atomic_state *state =
14546                 container_of(work, struct drm_atomic_state, commit_work);
14547
14548         intel_atomic_commit_tail(state);
14549 }
14550
14551 static int __i915_sw_fence_call
14552 intel_atomic_commit_ready(struct i915_sw_fence *fence,
14553                           enum i915_sw_fence_notify notify)
14554 {
14555         struct intel_atomic_state *state =
14556                 container_of(fence, struct intel_atomic_state, commit_ready);
14557
14558         switch (notify) {
14559         case FENCE_COMPLETE:
14560                 if (state->base.commit_work.func)
14561                         queue_work(system_unbound_wq, &state->base.commit_work);
14562                 break;
14563
14564         case FENCE_FREE:
14565                 drm_atomic_state_put(&state->base);
14566                 break;
14567         }
14568
14569         return NOTIFY_DONE;
14570 }
14571
14572 static void intel_atomic_track_fbs(struct drm_atomic_state *state)
14573 {
14574         struct drm_plane_state *old_plane_state;
14575         struct drm_plane *plane;
14576         int i;
14577
14578         for_each_plane_in_state(state, plane, old_plane_state, i)
14579                 i915_gem_track_fb(intel_fb_obj(old_plane_state->fb),
14580                                   intel_fb_obj(plane->state->fb),
14581                                   to_intel_plane(plane)->frontbuffer_bit);
14582 }
14583
14584 /**
14585  * intel_atomic_commit - commit validated state object
14586  * @dev: DRM device
14587  * @state: the top-level driver state object
14588  * @nonblock: nonblocking commit
14589  *
14590  * This function commits a top-level state object that has been validated
14591  * with drm_atomic_helper_check().
14592  *
14593  * RETURNS
14594  * Zero for success or -errno.
14595  */
14596 static int intel_atomic_commit(struct drm_device *dev,
14597                                struct drm_atomic_state *state,
14598                                bool nonblock)
14599 {
14600         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14601         struct drm_i915_private *dev_priv = to_i915(dev);
14602         int ret = 0;
14603
14604         ret = drm_atomic_helper_setup_commit(state, nonblock);
14605         if (ret)
14606                 return ret;
14607
14608         drm_atomic_state_get(state);
14609         i915_sw_fence_init(&intel_state->commit_ready,
14610                            intel_atomic_commit_ready);
14611
14612         ret = intel_atomic_prepare_commit(dev, state);
14613         if (ret) {
14614                 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
14615                 i915_sw_fence_commit(&intel_state->commit_ready);
14616                 return ret;
14617         }
14618
14619         drm_atomic_helper_swap_state(state, true);
14620         dev_priv->wm.distrust_bios_wm = false;
14621         intel_shared_dpll_swap_state(state);
14622         intel_atomic_track_fbs(state);
14623
14624         if (intel_state->modeset) {
14625                 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
14626                        sizeof(intel_state->min_pixclk));
14627                 dev_priv->active_crtcs = intel_state->active_crtcs;
14628                 dev_priv->atomic_cdclk_freq = intel_state->cdclk;
14629         }
14630
14631         drm_atomic_state_get(state);
14632         INIT_WORK(&state->commit_work,
14633                   nonblock ? intel_atomic_commit_work : NULL);
14634
14635         i915_sw_fence_commit(&intel_state->commit_ready);
14636         if (!nonblock) {
14637                 i915_sw_fence_wait(&intel_state->commit_ready);
14638                 intel_atomic_commit_tail(state);
14639         }
14640
14641         return 0;
14642 }
14643
14644 void intel_crtc_restore_mode(struct drm_crtc *crtc)
14645 {
14646         struct drm_device *dev = crtc->dev;
14647         struct drm_atomic_state *state;
14648         struct drm_crtc_state *crtc_state;
14649         int ret;
14650
14651         state = drm_atomic_state_alloc(dev);
14652         if (!state) {
14653                 DRM_DEBUG_KMS("[CRTC:%d:%s] crtc restore failed, out of memory",
14654                               crtc->base.id, crtc->name);
14655                 return;
14656         }
14657
14658         state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
14659
14660 retry:
14661         crtc_state = drm_atomic_get_crtc_state(state, crtc);
14662         ret = PTR_ERR_OR_ZERO(crtc_state);
14663         if (!ret) {
14664                 if (!crtc_state->active)
14665                         goto out;
14666
14667                 crtc_state->mode_changed = true;
14668                 ret = drm_atomic_commit(state);
14669         }
14670
14671         if (ret == -EDEADLK) {
14672                 drm_atomic_state_clear(state);
14673                 drm_modeset_backoff(state->acquire_ctx);
14674                 goto retry;
14675         }
14676
14677 out:
14678         drm_atomic_state_put(state);
14679 }
14680
14681 /*
14682  * FIXME: Remove this once i915 is fully DRIVER_ATOMIC by calling
14683  *        drm_atomic_helper_legacy_gamma_set() directly.
14684  */
14685 static int intel_atomic_legacy_gamma_set(struct drm_crtc *crtc,
14686                                          u16 *red, u16 *green, u16 *blue,
14687                                          uint32_t size)
14688 {
14689         struct drm_device *dev = crtc->dev;
14690         struct drm_mode_config *config = &dev->mode_config;
14691         struct drm_crtc_state *state;
14692         int ret;
14693
14694         ret = drm_atomic_helper_legacy_gamma_set(crtc, red, green, blue, size);
14695         if (ret)
14696                 return ret;
14697
14698         /*
14699          * Make sure we update the legacy properties so this works when
14700          * atomic is not enabled.
14701          */
14702
14703         state = crtc->state;
14704
14705         drm_object_property_set_value(&crtc->base,
14706                                       config->degamma_lut_property,
14707                                       (state->degamma_lut) ?
14708                                       state->degamma_lut->base.id : 0);
14709
14710         drm_object_property_set_value(&crtc->base,
14711                                       config->ctm_property,
14712                                       (state->ctm) ?
14713                                       state->ctm->base.id : 0);
14714
14715         drm_object_property_set_value(&crtc->base,
14716                                       config->gamma_lut_property,
14717                                       (state->gamma_lut) ?
14718                                       state->gamma_lut->base.id : 0);
14719
14720         return 0;
14721 }
14722
14723 static const struct drm_crtc_funcs intel_crtc_funcs = {
14724         .gamma_set = intel_atomic_legacy_gamma_set,
14725         .set_config = drm_atomic_helper_set_config,
14726         .set_property = drm_atomic_helper_crtc_set_property,
14727         .destroy = intel_crtc_destroy,
14728         .page_flip = intel_crtc_page_flip,
14729         .atomic_duplicate_state = intel_crtc_duplicate_state,
14730         .atomic_destroy_state = intel_crtc_destroy_state,
14731         .set_crc_source = intel_crtc_set_crc_source,
14732 };
14733
14734 /**
14735  * intel_prepare_plane_fb - Prepare fb for usage on plane
14736  * @plane: drm plane to prepare for
14737  * @fb: framebuffer to prepare for presentation
14738  *
14739  * Prepares a framebuffer for usage on a display plane.  Generally this
14740  * involves pinning the underlying object and updating the frontbuffer tracking
14741  * bits.  Some older platforms need special physical address handling for
14742  * cursor planes.
14743  *
14744  * Must be called with struct_mutex held.
14745  *
14746  * Returns 0 on success, negative error code on failure.
14747  */
14748 int
14749 intel_prepare_plane_fb(struct drm_plane *plane,
14750                        struct drm_plane_state *new_state)
14751 {
14752         struct intel_atomic_state *intel_state =
14753                 to_intel_atomic_state(new_state->state);
14754         struct drm_i915_private *dev_priv = to_i915(plane->dev);
14755         struct drm_framebuffer *fb = new_state->fb;
14756         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14757         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
14758         int ret;
14759
14760         if (!obj && !old_obj)
14761                 return 0;
14762
14763         if (old_obj) {
14764                 struct drm_crtc_state *crtc_state =
14765                         drm_atomic_get_existing_crtc_state(new_state->state,
14766                                                            plane->state->crtc);
14767
14768                 /* Big Hammer, we also need to ensure that any pending
14769                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
14770                  * current scanout is retired before unpinning the old
14771                  * framebuffer. Note that we rely on userspace rendering
14772                  * into the buffer attached to the pipe they are waiting
14773                  * on. If not, userspace generates a GPU hang with IPEHR
14774                  * point to the MI_WAIT_FOR_EVENT.
14775                  *
14776                  * This should only fail upon a hung GPU, in which case we
14777                  * can safely continue.
14778                  */
14779                 if (needs_modeset(crtc_state)) {
14780                         ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
14781                                                               old_obj->resv, NULL,
14782                                                               false, 0,
14783                                                               GFP_KERNEL);
14784                         if (ret < 0)
14785                                 return ret;
14786                 }
14787         }
14788
14789         if (new_state->fence) { /* explicit fencing */
14790                 ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready,
14791                                                     new_state->fence,
14792                                                     I915_FENCE_TIMEOUT,
14793                                                     GFP_KERNEL);
14794                 if (ret < 0)
14795                         return ret;
14796         }
14797
14798         if (!obj)
14799                 return 0;
14800
14801         if (!new_state->fence) { /* implicit fencing */
14802                 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
14803                                                       obj->resv, NULL,
14804                                                       false, I915_FENCE_TIMEOUT,
14805                                                       GFP_KERNEL);
14806                 if (ret < 0)
14807                         return ret;
14808
14809                 i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY);
14810         }
14811
14812         if (plane->type == DRM_PLANE_TYPE_CURSOR &&
14813             INTEL_INFO(dev_priv)->cursor_needs_physical) {
14814                 int align = IS_I830(dev_priv) ? 16 * 1024 : 256;
14815                 ret = i915_gem_object_attach_phys(obj, align);
14816                 if (ret) {
14817                         DRM_DEBUG_KMS("failed to attach phys object\n");
14818                         return ret;
14819                 }
14820         } else {
14821                 struct i915_vma *vma;
14822
14823                 vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
14824                 if (IS_ERR(vma)) {
14825                         DRM_DEBUG_KMS("failed to pin object\n");
14826                         return PTR_ERR(vma);
14827                 }
14828
14829                 to_intel_plane_state(new_state)->vma = vma;
14830         }
14831
14832         return 0;
14833 }
14834
14835 /**
14836  * intel_cleanup_plane_fb - Cleans up an fb after plane use
14837  * @plane: drm plane to clean up for
14838  * @fb: old framebuffer that was on plane
14839  *
14840  * Cleans up a framebuffer that has just been removed from a plane.
14841  *
14842  * Must be called with struct_mutex held.
14843  */
14844 void
14845 intel_cleanup_plane_fb(struct drm_plane *plane,
14846                        struct drm_plane_state *old_state)
14847 {
14848         struct i915_vma *vma;
14849
14850         /* Should only be called after a successful intel_prepare_plane_fb()! */
14851         vma = fetch_and_zero(&to_intel_plane_state(old_state)->vma);
14852         if (vma)
14853                 intel_unpin_fb_vma(vma);
14854 }
14855
14856 int
14857 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
14858 {
14859         int max_scale;
14860         int crtc_clock, cdclk;
14861
14862         if (!intel_crtc || !crtc_state->base.enable)
14863                 return DRM_PLANE_HELPER_NO_SCALING;
14864
14865         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
14866         cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
14867
14868         if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
14869                 return DRM_PLANE_HELPER_NO_SCALING;
14870
14871         /*
14872          * skl max scale is lower of:
14873          *    close to 3 but not 3, -1 is for that purpose
14874          *            or
14875          *    cdclk/crtc_clock
14876          */
14877         max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
14878
14879         return max_scale;
14880 }
14881
14882 static int
14883 intel_check_primary_plane(struct drm_plane *plane,
14884                           struct intel_crtc_state *crtc_state,
14885                           struct intel_plane_state *state)
14886 {
14887         struct drm_i915_private *dev_priv = to_i915(plane->dev);
14888         struct drm_crtc *crtc = state->base.crtc;
14889         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
14890         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
14891         bool can_position = false;
14892         int ret;
14893
14894         if (INTEL_GEN(dev_priv) >= 9) {
14895                 /* use scaler when colorkey is not required */
14896                 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
14897                         min_scale = 1;
14898                         max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
14899                 }
14900                 can_position = true;
14901         }
14902
14903         ret = drm_plane_helper_check_state(&state->base,
14904                                            &state->clip,
14905                                            min_scale, max_scale,
14906                                            can_position, true);
14907         if (ret)
14908                 return ret;
14909
14910         if (!state->base.fb)
14911                 return 0;
14912
14913         if (INTEL_GEN(dev_priv) >= 9) {
14914                 ret = skl_check_plane_surface(state);
14915                 if (ret)
14916                         return ret;
14917         }
14918
14919         return 0;
14920 }
14921
14922 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
14923                                     struct drm_crtc_state *old_crtc_state)
14924 {
14925         struct drm_device *dev = crtc->dev;
14926         struct drm_i915_private *dev_priv = to_i915(dev);
14927         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14928         struct intel_crtc_state *intel_cstate =
14929                 to_intel_crtc_state(crtc->state);
14930         struct intel_crtc_state *old_intel_cstate =
14931                 to_intel_crtc_state(old_crtc_state);
14932         struct intel_atomic_state *old_intel_state =
14933                 to_intel_atomic_state(old_crtc_state->state);
14934         bool modeset = needs_modeset(crtc->state);
14935
14936         /* Perform vblank evasion around commit operation */
14937         intel_pipe_update_start(intel_crtc);
14938
14939         if (modeset)
14940                 goto out;
14941
14942         if (crtc->state->color_mgmt_changed || to_intel_crtc_state(crtc->state)->update_pipe) {
14943                 intel_color_set_csc(crtc->state);
14944                 intel_color_load_luts(crtc->state);
14945         }
14946
14947         if (intel_cstate->update_pipe)
14948                 intel_update_pipe_config(intel_crtc, old_intel_cstate);
14949         else if (INTEL_GEN(dev_priv) >= 9)
14950                 skl_detach_scalers(intel_crtc);
14951
14952 out:
14953         if (dev_priv->display.atomic_update_watermarks)
14954                 dev_priv->display.atomic_update_watermarks(old_intel_state,
14955                                                            intel_cstate);
14956 }
14957
14958 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
14959                                      struct drm_crtc_state *old_crtc_state)
14960 {
14961         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14962
14963         intel_pipe_update_end(intel_crtc, NULL);
14964 }
14965
14966 /**
14967  * intel_plane_destroy - destroy a plane
14968  * @plane: plane to destroy
14969  *
14970  * Common destruction function for all types of planes (primary, cursor,
14971  * sprite).
14972  */
14973 void intel_plane_destroy(struct drm_plane *plane)
14974 {
14975         drm_plane_cleanup(plane);
14976         kfree(to_intel_plane(plane));
14977 }
14978
14979 const struct drm_plane_funcs intel_plane_funcs = {
14980         .update_plane = drm_atomic_helper_update_plane,
14981         .disable_plane = drm_atomic_helper_disable_plane,
14982         .destroy = intel_plane_destroy,
14983         .set_property = drm_atomic_helper_plane_set_property,
14984         .atomic_get_property = intel_plane_atomic_get_property,
14985         .atomic_set_property = intel_plane_atomic_set_property,
14986         .atomic_duplicate_state = intel_plane_duplicate_state,
14987         .atomic_destroy_state = intel_plane_destroy_state,
14988 };
14989
14990 static int
14991 intel_legacy_cursor_update(struct drm_plane *plane,
14992                            struct drm_crtc *crtc,
14993                            struct drm_framebuffer *fb,
14994                            int crtc_x, int crtc_y,
14995                            unsigned int crtc_w, unsigned int crtc_h,
14996                            uint32_t src_x, uint32_t src_y,
14997                            uint32_t src_w, uint32_t src_h)
14998 {
14999         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
15000         int ret;
15001         struct drm_plane_state *old_plane_state, *new_plane_state;
15002         struct intel_plane *intel_plane = to_intel_plane(plane);
15003         struct drm_framebuffer *old_fb;
15004         struct drm_crtc_state *crtc_state = crtc->state;
15005         struct i915_vma *old_vma;
15006
15007         /*
15008          * When crtc is inactive or there is a modeset pending,
15009          * wait for it to complete in the slowpath
15010          */
15011         if (!crtc_state->active || needs_modeset(crtc_state) ||
15012             to_intel_crtc_state(crtc_state)->update_pipe)
15013                 goto slow;
15014
15015         old_plane_state = plane->state;
15016
15017         /*
15018          * If any parameters change that may affect watermarks,
15019          * take the slowpath. Only changing fb or position should be
15020          * in the fastpath.
15021          */
15022         if (old_plane_state->crtc != crtc ||
15023             old_plane_state->src_w != src_w ||
15024             old_plane_state->src_h != src_h ||
15025             old_plane_state->crtc_w != crtc_w ||
15026             old_plane_state->crtc_h != crtc_h ||
15027             !old_plane_state->visible ||
15028             old_plane_state->fb->modifier != fb->modifier)
15029                 goto slow;
15030
15031         new_plane_state = intel_plane_duplicate_state(plane);
15032         if (!new_plane_state)
15033                 return -ENOMEM;
15034
15035         drm_atomic_set_fb_for_plane(new_plane_state, fb);
15036
15037         new_plane_state->src_x = src_x;
15038         new_plane_state->src_y = src_y;
15039         new_plane_state->src_w = src_w;
15040         new_plane_state->src_h = src_h;
15041         new_plane_state->crtc_x = crtc_x;
15042         new_plane_state->crtc_y = crtc_y;
15043         new_plane_state->crtc_w = crtc_w;
15044         new_plane_state->crtc_h = crtc_h;
15045
15046         ret = intel_plane_atomic_check_with_state(to_intel_crtc_state(crtc->state),
15047                                                   to_intel_plane_state(new_plane_state));
15048         if (ret)
15049                 goto out_free;
15050
15051         /* Visibility changed, must take slowpath. */
15052         if (!new_plane_state->visible)
15053                 goto slow_free;
15054
15055         ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
15056         if (ret)
15057                 goto out_free;
15058
15059         if (INTEL_INFO(dev_priv)->cursor_needs_physical) {
15060                 int align = IS_I830(dev_priv) ? 16 * 1024 : 256;
15061
15062                 ret = i915_gem_object_attach_phys(intel_fb_obj(fb), align);
15063                 if (ret) {
15064                         DRM_DEBUG_KMS("failed to attach phys object\n");
15065                         goto out_unlock;
15066                 }
15067         } else {
15068                 struct i915_vma *vma;
15069
15070                 vma = intel_pin_and_fence_fb_obj(fb, new_plane_state->rotation);
15071                 if (IS_ERR(vma)) {
15072                         DRM_DEBUG_KMS("failed to pin object\n");
15073
15074                         ret = PTR_ERR(vma);
15075                         goto out_unlock;
15076                 }
15077
15078                 to_intel_plane_state(new_plane_state)->vma = vma;
15079         }
15080
15081         old_fb = old_plane_state->fb;
15082         old_vma = to_intel_plane_state(old_plane_state)->vma;
15083
15084         i915_gem_track_fb(intel_fb_obj(old_fb), intel_fb_obj(fb),
15085                           intel_plane->frontbuffer_bit);
15086
15087         /* Swap plane state */
15088         new_plane_state->fence = old_plane_state->fence;
15089         *to_intel_plane_state(old_plane_state) = *to_intel_plane_state(new_plane_state);
15090         new_plane_state->fence = NULL;
15091         new_plane_state->fb = old_fb;
15092         to_intel_plane_state(new_plane_state)->vma = old_vma;
15093
15094         intel_plane->update_plane(plane,
15095                                   to_intel_crtc_state(crtc->state),
15096                                   to_intel_plane_state(plane->state));
15097
15098         intel_cleanup_plane_fb(plane, new_plane_state);
15099
15100 out_unlock:
15101         mutex_unlock(&dev_priv->drm.struct_mutex);
15102 out_free:
15103         intel_plane_destroy_state(plane, new_plane_state);
15104         return ret;
15105
15106 slow_free:
15107         intel_plane_destroy_state(plane, new_plane_state);
15108 slow:
15109         return drm_atomic_helper_update_plane(plane, crtc, fb,
15110                                               crtc_x, crtc_y, crtc_w, crtc_h,
15111                                               src_x, src_y, src_w, src_h);
15112 }
15113
15114 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
15115         .update_plane = intel_legacy_cursor_update,
15116         .disable_plane = drm_atomic_helper_disable_plane,
15117         .destroy = intel_plane_destroy,
15118         .set_property = drm_atomic_helper_plane_set_property,
15119         .atomic_get_property = intel_plane_atomic_get_property,
15120         .atomic_set_property = intel_plane_atomic_set_property,
15121         .atomic_duplicate_state = intel_plane_duplicate_state,
15122         .atomic_destroy_state = intel_plane_destroy_state,
15123 };
15124
15125 static struct intel_plane *
15126 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
15127 {
15128         struct intel_plane *primary = NULL;
15129         struct intel_plane_state *state = NULL;
15130         const uint32_t *intel_primary_formats;
15131         unsigned int supported_rotations;
15132         unsigned int num_formats;
15133         int ret;
15134
15135         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
15136         if (!primary) {
15137                 ret = -ENOMEM;
15138                 goto fail;
15139         }
15140
15141         state = intel_create_plane_state(&primary->base);
15142         if (!state) {
15143                 ret = -ENOMEM;
15144                 goto fail;
15145         }
15146
15147         primary->base.state = &state->base;
15148
15149         primary->can_scale = false;
15150         primary->max_downscale = 1;
15151         if (INTEL_GEN(dev_priv) >= 9) {
15152                 primary->can_scale = true;
15153                 state->scaler_id = -1;
15154         }
15155         primary->pipe = pipe;
15156         /*
15157          * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
15158          * port is hooked to pipe B. Hence we want plane A feeding pipe B.
15159          */
15160         if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
15161                 primary->plane = (enum plane) !pipe;
15162         else
15163                 primary->plane = (enum plane) pipe;
15164         primary->id = PLANE_PRIMARY;
15165         primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
15166         primary->check_plane = intel_check_primary_plane;
15167
15168         if (INTEL_GEN(dev_priv) >= 9) {
15169                 intel_primary_formats = skl_primary_formats;
15170                 num_formats = ARRAY_SIZE(skl_primary_formats);
15171
15172                 primary->update_plane = skylake_update_primary_plane;
15173                 primary->disable_plane = skylake_disable_primary_plane;
15174         } else if (HAS_PCH_SPLIT(dev_priv)) {
15175                 intel_primary_formats = i965_primary_formats;
15176                 num_formats = ARRAY_SIZE(i965_primary_formats);
15177
15178                 primary->update_plane = ironlake_update_primary_plane;
15179                 primary->disable_plane = i9xx_disable_primary_plane;
15180         } else if (INTEL_GEN(dev_priv) >= 4) {
15181                 intel_primary_formats = i965_primary_formats;
15182                 num_formats = ARRAY_SIZE(i965_primary_formats);
15183
15184                 primary->update_plane = i9xx_update_primary_plane;
15185                 primary->disable_plane = i9xx_disable_primary_plane;
15186         } else {
15187                 intel_primary_formats = i8xx_primary_formats;
15188                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
15189
15190                 primary->update_plane = i9xx_update_primary_plane;
15191                 primary->disable_plane = i9xx_disable_primary_plane;
15192         }
15193
15194         if (INTEL_GEN(dev_priv) >= 9)
15195                 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
15196                                                0, &intel_plane_funcs,
15197                                                intel_primary_formats, num_formats,
15198                                                DRM_PLANE_TYPE_PRIMARY,
15199                                                "plane 1%c", pipe_name(pipe));
15200         else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
15201                 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
15202                                                0, &intel_plane_funcs,
15203                                                intel_primary_formats, num_formats,
15204                                                DRM_PLANE_TYPE_PRIMARY,
15205                                                "primary %c", pipe_name(pipe));
15206         else
15207                 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
15208                                                0, &intel_plane_funcs,
15209                                                intel_primary_formats, num_formats,
15210                                                DRM_PLANE_TYPE_PRIMARY,
15211                                                "plane %c", plane_name(primary->plane));
15212         if (ret)
15213                 goto fail;
15214
15215         if (INTEL_GEN(dev_priv) >= 9) {
15216                 supported_rotations =
15217                         DRM_ROTATE_0 | DRM_ROTATE_90 |
15218                         DRM_ROTATE_180 | DRM_ROTATE_270;
15219         } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
15220                 supported_rotations =
15221                         DRM_ROTATE_0 | DRM_ROTATE_180 |
15222                         DRM_REFLECT_X;
15223         } else if (INTEL_GEN(dev_priv) >= 4) {
15224                 supported_rotations =
15225                         DRM_ROTATE_0 | DRM_ROTATE_180;
15226         } else {
15227                 supported_rotations = DRM_ROTATE_0;
15228         }
15229
15230         if (INTEL_GEN(dev_priv) >= 4)
15231                 drm_plane_create_rotation_property(&primary->base,
15232                                                    DRM_ROTATE_0,
15233                                                    supported_rotations);
15234
15235         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
15236
15237         return primary;
15238
15239 fail:
15240         kfree(state);
15241         kfree(primary);
15242
15243         return ERR_PTR(ret);
15244 }
15245
15246 static int
15247 intel_check_cursor_plane(struct drm_plane *plane,
15248                          struct intel_crtc_state *crtc_state,
15249                          struct intel_plane_state *state)
15250 {
15251         struct drm_framebuffer *fb = state->base.fb;
15252         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
15253         enum pipe pipe = to_intel_plane(plane)->pipe;
15254         unsigned stride;
15255         int ret;
15256
15257         ret = drm_plane_helper_check_state(&state->base,
15258                                            &state->clip,
15259                                            DRM_PLANE_HELPER_NO_SCALING,
15260                                            DRM_PLANE_HELPER_NO_SCALING,
15261                                            true, true);
15262         if (ret)
15263                 return ret;
15264
15265         /* if we want to turn off the cursor ignore width and height */
15266         if (!obj)
15267                 return 0;
15268
15269         /* Check for which cursor types we support */
15270         if (!cursor_size_ok(to_i915(plane->dev), state->base.crtc_w,
15271                             state->base.crtc_h)) {
15272                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
15273                           state->base.crtc_w, state->base.crtc_h);
15274                 return -EINVAL;
15275         }
15276
15277         stride = roundup_pow_of_two(state->base.crtc_w) * 4;
15278         if (obj->base.size < stride * state->base.crtc_h) {
15279                 DRM_DEBUG_KMS("buffer is too small\n");
15280                 return -ENOMEM;
15281         }
15282
15283         if (fb->modifier != DRM_FORMAT_MOD_NONE) {
15284                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
15285                 return -EINVAL;
15286         }
15287
15288         /*
15289          * There's something wrong with the cursor on CHV pipe C.
15290          * If it straddles the left edge of the screen then
15291          * moving it away from the edge or disabling it often
15292          * results in a pipe underrun, and often that can lead to
15293          * dead pipe (constant underrun reported, and it scans
15294          * out just a solid color). To recover from that, the
15295          * display power well must be turned off and on again.
15296          * Refuse the put the cursor into that compromised position.
15297          */
15298         if (IS_CHERRYVIEW(to_i915(plane->dev)) && pipe == PIPE_C &&
15299             state->base.visible && state->base.crtc_x < 0) {
15300                 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
15301                 return -EINVAL;
15302         }
15303
15304         return 0;
15305 }
15306
15307 static void
15308 intel_disable_cursor_plane(struct drm_plane *plane,
15309                            struct drm_crtc *crtc)
15310 {
15311         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
15312
15313         intel_crtc->cursor_addr = 0;
15314         intel_crtc_update_cursor(crtc, NULL);
15315 }
15316
15317 static void
15318 intel_update_cursor_plane(struct drm_plane *plane,
15319                           const struct intel_crtc_state *crtc_state,
15320                           const struct intel_plane_state *state)
15321 {
15322         struct drm_crtc *crtc = crtc_state->base.crtc;
15323         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
15324         struct drm_i915_private *dev_priv = to_i915(plane->dev);
15325         struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
15326         uint32_t addr;
15327
15328         if (!obj)
15329                 addr = 0;
15330         else if (!INTEL_INFO(dev_priv)->cursor_needs_physical)
15331                 addr = intel_plane_ggtt_offset(state);
15332         else
15333                 addr = obj->phys_handle->busaddr;
15334
15335         intel_crtc->cursor_addr = addr;
15336         intel_crtc_update_cursor(crtc, state);
15337 }
15338
15339 static struct intel_plane *
15340 intel_cursor_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
15341 {
15342         struct intel_plane *cursor = NULL;
15343         struct intel_plane_state *state = NULL;
15344         int ret;
15345
15346         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
15347         if (!cursor) {
15348                 ret = -ENOMEM;
15349                 goto fail;
15350         }
15351
15352         state = intel_create_plane_state(&cursor->base);
15353         if (!state) {
15354                 ret = -ENOMEM;
15355                 goto fail;
15356         }
15357
15358         cursor->base.state = &state->base;
15359
15360         cursor->can_scale = false;
15361         cursor->max_downscale = 1;
15362         cursor->pipe = pipe;
15363         cursor->plane = pipe;
15364         cursor->id = PLANE_CURSOR;
15365         cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
15366         cursor->check_plane = intel_check_cursor_plane;
15367         cursor->update_plane = intel_update_cursor_plane;
15368         cursor->disable_plane = intel_disable_cursor_plane;
15369
15370         ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
15371                                        0, &intel_cursor_plane_funcs,
15372                                        intel_cursor_formats,
15373                                        ARRAY_SIZE(intel_cursor_formats),
15374                                        DRM_PLANE_TYPE_CURSOR,
15375                                        "cursor %c", pipe_name(pipe));
15376         if (ret)
15377                 goto fail;
15378
15379         if (INTEL_GEN(dev_priv) >= 4)
15380                 drm_plane_create_rotation_property(&cursor->base,
15381                                                    DRM_ROTATE_0,
15382                                                    DRM_ROTATE_0 |
15383                                                    DRM_ROTATE_180);
15384
15385         if (INTEL_GEN(dev_priv) >= 9)
15386                 state->scaler_id = -1;
15387
15388         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
15389
15390         return cursor;
15391
15392 fail:
15393         kfree(state);
15394         kfree(cursor);
15395
15396         return ERR_PTR(ret);
15397 }
15398
15399 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
15400                                     struct intel_crtc_state *crtc_state)
15401 {
15402         struct intel_crtc_scaler_state *scaler_state =
15403                 &crtc_state->scaler_state;
15404         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
15405         int i;
15406
15407         crtc->num_scalers = dev_priv->info.num_scalers[crtc->pipe];
15408         if (!crtc->num_scalers)
15409                 return;
15410
15411         for (i = 0; i < crtc->num_scalers; i++) {
15412                 struct intel_scaler *scaler = &scaler_state->scalers[i];
15413
15414                 scaler->in_use = 0;
15415                 scaler->mode = PS_SCALER_MODE_DYN;
15416         }
15417
15418         scaler_state->scaler_id = -1;
15419 }
15420
15421 static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
15422 {
15423         struct intel_crtc *intel_crtc;
15424         struct intel_crtc_state *crtc_state = NULL;
15425         struct intel_plane *primary = NULL;
15426         struct intel_plane *cursor = NULL;
15427         int sprite, ret;
15428
15429         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
15430         if (!intel_crtc)
15431                 return -ENOMEM;
15432
15433         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
15434         if (!crtc_state) {
15435                 ret = -ENOMEM;
15436                 goto fail;
15437         }
15438         intel_crtc->config = crtc_state;
15439         intel_crtc->base.state = &crtc_state->base;
15440         crtc_state->base.crtc = &intel_crtc->base;
15441
15442         primary = intel_primary_plane_create(dev_priv, pipe);
15443         if (IS_ERR(primary)) {
15444                 ret = PTR_ERR(primary);
15445                 goto fail;
15446         }
15447         intel_crtc->plane_ids_mask |= BIT(primary->id);
15448
15449         for_each_sprite(dev_priv, pipe, sprite) {
15450                 struct intel_plane *plane;
15451
15452                 plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
15453                 if (IS_ERR(plane)) {
15454                         ret = PTR_ERR(plane);
15455                         goto fail;
15456                 }
15457                 intel_crtc->plane_ids_mask |= BIT(plane->id);
15458         }
15459
15460         cursor = intel_cursor_plane_create(dev_priv, pipe);
15461         if (IS_ERR(cursor)) {
15462                 ret = PTR_ERR(cursor);
15463                 goto fail;
15464         }
15465         intel_crtc->plane_ids_mask |= BIT(cursor->id);
15466
15467         ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base,
15468                                         &primary->base, &cursor->base,
15469                                         &intel_crtc_funcs,
15470                                         "pipe %c", pipe_name(pipe));
15471         if (ret)
15472                 goto fail;
15473
15474         intel_crtc->pipe = pipe;
15475         intel_crtc->plane = primary->plane;
15476
15477         intel_crtc->cursor_base = ~0;
15478         intel_crtc->cursor_cntl = ~0;
15479         intel_crtc->cursor_size = ~0;
15480
15481         intel_crtc->wm.cxsr_allowed = true;
15482
15483         /* initialize shared scalers */
15484         intel_crtc_init_scalers(intel_crtc, crtc_state);
15485
15486         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
15487                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
15488         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = intel_crtc;
15489         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = intel_crtc;
15490
15491         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
15492
15493         intel_color_init(&intel_crtc->base);
15494
15495         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
15496
15497         return 0;
15498
15499 fail:
15500         /*
15501          * drm_mode_config_cleanup() will free up any
15502          * crtcs/planes already initialized.
15503          */
15504         kfree(crtc_state);
15505         kfree(intel_crtc);
15506
15507         return ret;
15508 }
15509
15510 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
15511 {
15512         struct drm_encoder *encoder = connector->base.encoder;
15513         struct drm_device *dev = connector->base.dev;
15514
15515         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
15516
15517         if (!encoder || WARN_ON(!encoder->crtc))
15518                 return INVALID_PIPE;
15519
15520         return to_intel_crtc(encoder->crtc)->pipe;
15521 }
15522
15523 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
15524                                 struct drm_file *file)
15525 {
15526         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
15527         struct drm_crtc *drmmode_crtc;
15528         struct intel_crtc *crtc;
15529
15530         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
15531         if (!drmmode_crtc)
15532                 return -ENOENT;
15533
15534         crtc = to_intel_crtc(drmmode_crtc);
15535         pipe_from_crtc_id->pipe = crtc->pipe;
15536
15537         return 0;
15538 }
15539
15540 static int intel_encoder_clones(struct intel_encoder *encoder)
15541 {
15542         struct drm_device *dev = encoder->base.dev;
15543         struct intel_encoder *source_encoder;
15544         int index_mask = 0;
15545         int entry = 0;
15546
15547         for_each_intel_encoder(dev, source_encoder) {
15548                 if (encoders_cloneable(encoder, source_encoder))
15549                         index_mask |= (1 << entry);
15550
15551                 entry++;
15552         }
15553
15554         return index_mask;
15555 }
15556
15557 static bool has_edp_a(struct drm_i915_private *dev_priv)
15558 {
15559         if (!IS_MOBILE(dev_priv))
15560                 return false;
15561
15562         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
15563                 return false;
15564
15565         if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
15566                 return false;
15567
15568         return true;
15569 }
15570
15571 static bool intel_crt_present(struct drm_i915_private *dev_priv)
15572 {
15573         if (INTEL_GEN(dev_priv) >= 9)
15574                 return false;
15575
15576         if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
15577                 return false;
15578
15579         if (IS_CHERRYVIEW(dev_priv))
15580                 return false;
15581
15582         if (HAS_PCH_LPT_H(dev_priv) &&
15583             I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
15584                 return false;
15585
15586         /* DDI E can't be used if DDI A requires 4 lanes */
15587         if (HAS_DDI(dev_priv) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
15588                 return false;
15589
15590         if (!dev_priv->vbt.int_crt_support)
15591                 return false;
15592
15593         return true;
15594 }
15595
15596 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
15597 {
15598         int pps_num;
15599         int pps_idx;
15600
15601         if (HAS_DDI(dev_priv))
15602                 return;
15603         /*
15604          * This w/a is needed at least on CPT/PPT, but to be sure apply it
15605          * everywhere where registers can be write protected.
15606          */
15607         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15608                 pps_num = 2;
15609         else
15610                 pps_num = 1;
15611
15612         for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
15613                 u32 val = I915_READ(PP_CONTROL(pps_idx));
15614
15615                 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
15616                 I915_WRITE(PP_CONTROL(pps_idx), val);
15617         }
15618 }
15619
15620 static void intel_pps_init(struct drm_i915_private *dev_priv)
15621 {
15622         if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv))
15623                 dev_priv->pps_mmio_base = PCH_PPS_BASE;
15624         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15625                 dev_priv->pps_mmio_base = VLV_PPS_BASE;
15626         else
15627                 dev_priv->pps_mmio_base = PPS_BASE;
15628
15629         intel_pps_unlock_regs_wa(dev_priv);
15630 }
15631
15632 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
15633 {
15634         struct intel_encoder *encoder;
15635         bool dpd_is_edp = false;
15636
15637         intel_pps_init(dev_priv);
15638
15639         /*
15640          * intel_edp_init_connector() depends on this completing first, to
15641          * prevent the registeration of both eDP and LVDS and the incorrect
15642          * sharing of the PPS.
15643          */
15644         intel_lvds_init(dev_priv);
15645
15646         if (intel_crt_present(dev_priv))
15647                 intel_crt_init(dev_priv);
15648
15649         if (IS_GEN9_LP(dev_priv)) {
15650                 /*
15651                  * FIXME: Broxton doesn't support port detection via the
15652                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
15653                  * detect the ports.
15654                  */
15655                 intel_ddi_init(dev_priv, PORT_A);
15656                 intel_ddi_init(dev_priv, PORT_B);
15657                 intel_ddi_init(dev_priv, PORT_C);
15658
15659                 intel_dsi_init(dev_priv);
15660         } else if (HAS_DDI(dev_priv)) {
15661                 int found;
15662
15663                 /*
15664                  * Haswell uses DDI functions to detect digital outputs.
15665                  * On SKL pre-D0 the strap isn't connected, so we assume
15666                  * it's there.
15667                  */
15668                 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
15669                 /* WaIgnoreDDIAStrap: skl */
15670                 if (found || IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
15671                         intel_ddi_init(dev_priv, PORT_A);
15672
15673                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
15674                  * register */
15675                 found = I915_READ(SFUSE_STRAP);
15676
15677                 if (found & SFUSE_STRAP_DDIB_DETECTED)
15678                         intel_ddi_init(dev_priv, PORT_B);
15679                 if (found & SFUSE_STRAP_DDIC_DETECTED)
15680                         intel_ddi_init(dev_priv, PORT_C);
15681                 if (found & SFUSE_STRAP_DDID_DETECTED)
15682                         intel_ddi_init(dev_priv, PORT_D);
15683                 /*
15684                  * On SKL we don't have a way to detect DDI-E so we rely on VBT.
15685                  */
15686                 if ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) &&
15687                     (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
15688                      dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
15689                      dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
15690                         intel_ddi_init(dev_priv, PORT_E);
15691
15692         } else if (HAS_PCH_SPLIT(dev_priv)) {
15693                 int found;
15694                 dpd_is_edp = intel_dp_is_edp(dev_priv, PORT_D);
15695
15696                 if (has_edp_a(dev_priv))
15697                         intel_dp_init(dev_priv, DP_A, PORT_A);
15698
15699                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
15700                         /* PCH SDVOB multiplex with HDMIB */
15701                         found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
15702                         if (!found)
15703                                 intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
15704                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
15705                                 intel_dp_init(dev_priv, PCH_DP_B, PORT_B);
15706                 }
15707
15708                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
15709                         intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
15710
15711                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
15712                         intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
15713
15714                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
15715                         intel_dp_init(dev_priv, PCH_DP_C, PORT_C);
15716
15717                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
15718                         intel_dp_init(dev_priv, PCH_DP_D, PORT_D);
15719         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15720                 bool has_edp, has_port;
15721
15722                 /*
15723                  * The DP_DETECTED bit is the latched state of the DDC
15724                  * SDA pin at boot. However since eDP doesn't require DDC
15725                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
15726                  * eDP ports may have been muxed to an alternate function.
15727                  * Thus we can't rely on the DP_DETECTED bit alone to detect
15728                  * eDP ports. Consult the VBT as well as DP_DETECTED to
15729                  * detect eDP ports.
15730                  *
15731                  * Sadly the straps seem to be missing sometimes even for HDMI
15732                  * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
15733                  * and VBT for the presence of the port. Additionally we can't
15734                  * trust the port type the VBT declares as we've seen at least
15735                  * HDMI ports that the VBT claim are DP or eDP.
15736                  */
15737                 has_edp = intel_dp_is_edp(dev_priv, PORT_B);
15738                 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
15739                 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
15740                         has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B);
15741                 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
15742                         intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
15743
15744                 has_edp = intel_dp_is_edp(dev_priv, PORT_C);
15745                 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
15746                 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
15747                         has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C);
15748                 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
15749                         intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
15750
15751                 if (IS_CHERRYVIEW(dev_priv)) {
15752                         /*
15753                          * eDP not supported on port D,
15754                          * so no need to worry about it
15755                          */
15756                         has_port = intel_bios_is_port_present(dev_priv, PORT_D);
15757                         if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
15758                                 intel_dp_init(dev_priv, CHV_DP_D, PORT_D);
15759                         if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
15760                                 intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
15761                 }
15762
15763                 intel_dsi_init(dev_priv);
15764         } else if (!IS_GEN2(dev_priv) && !IS_PINEVIEW(dev_priv)) {
15765                 bool found = false;
15766
15767                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
15768                         DRM_DEBUG_KMS("probing SDVOB\n");
15769                         found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
15770                         if (!found && IS_G4X(dev_priv)) {
15771                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
15772                                 intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
15773                         }
15774
15775                         if (!found && IS_G4X(dev_priv))
15776                                 intel_dp_init(dev_priv, DP_B, PORT_B);
15777                 }
15778
15779                 /* Before G4X SDVOC doesn't have its own detect register */
15780
15781                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
15782                         DRM_DEBUG_KMS("probing SDVOC\n");
15783                         found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
15784                 }
15785
15786                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
15787
15788                         if (IS_G4X(dev_priv)) {
15789                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
15790                                 intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
15791                         }
15792                         if (IS_G4X(dev_priv))
15793                                 intel_dp_init(dev_priv, DP_C, PORT_C);
15794                 }
15795
15796                 if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
15797                         intel_dp_init(dev_priv, DP_D, PORT_D);
15798         } else if (IS_GEN2(dev_priv))
15799                 intel_dvo_init(dev_priv);
15800
15801         if (SUPPORTS_TV(dev_priv))
15802                 intel_tv_init(dev_priv);
15803
15804         intel_psr_init(dev_priv);
15805
15806         for_each_intel_encoder(&dev_priv->drm, encoder) {
15807                 encoder->base.possible_crtcs = encoder->crtc_mask;
15808                 encoder->base.possible_clones =
15809                         intel_encoder_clones(encoder);
15810         }
15811
15812         intel_init_pch_refclk(dev_priv);
15813
15814         drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
15815 }
15816
15817 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
15818 {
15819         struct drm_device *dev = fb->dev;
15820         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
15821
15822         drm_framebuffer_cleanup(fb);
15823         mutex_lock(&dev->struct_mutex);
15824         WARN_ON(!intel_fb->obj->framebuffer_references--);
15825         i915_gem_object_put(intel_fb->obj);
15826         mutex_unlock(&dev->struct_mutex);
15827         kfree(intel_fb);
15828 }
15829
15830 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
15831                                                 struct drm_file *file,
15832                                                 unsigned int *handle)
15833 {
15834         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
15835         struct drm_i915_gem_object *obj = intel_fb->obj;
15836
15837         if (obj->userptr.mm) {
15838                 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
15839                 return -EINVAL;
15840         }
15841
15842         return drm_gem_handle_create(file, &obj->base, handle);
15843 }
15844
15845 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
15846                                         struct drm_file *file,
15847                                         unsigned flags, unsigned color,
15848                                         struct drm_clip_rect *clips,
15849                                         unsigned num_clips)
15850 {
15851         struct drm_device *dev = fb->dev;
15852         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
15853         struct drm_i915_gem_object *obj = intel_fb->obj;
15854
15855         mutex_lock(&dev->struct_mutex);
15856         if (obj->pin_display && obj->cache_dirty)
15857                 i915_gem_clflush_object(obj, true);
15858         intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
15859         mutex_unlock(&dev->struct_mutex);
15860
15861         return 0;
15862 }
15863
15864 static const struct drm_framebuffer_funcs intel_fb_funcs = {
15865         .destroy = intel_user_framebuffer_destroy,
15866         .create_handle = intel_user_framebuffer_create_handle,
15867         .dirty = intel_user_framebuffer_dirty,
15868 };
15869
15870 static
15871 u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv,
15872                          uint64_t fb_modifier, uint32_t pixel_format)
15873 {
15874         u32 gen = INTEL_INFO(dev_priv)->gen;
15875
15876         if (gen >= 9) {
15877                 int cpp = drm_format_plane_cpp(pixel_format, 0);
15878
15879                 /* "The stride in bytes must not exceed the of the size of 8K
15880                  *  pixels and 32K bytes."
15881                  */
15882                 return min(8192 * cpp, 32768);
15883         } else if (gen >= 5 && !IS_VALLEYVIEW(dev_priv) &&
15884                    !IS_CHERRYVIEW(dev_priv)) {
15885                 return 32*1024;
15886         } else if (gen >= 4) {
15887                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
15888                         return 16*1024;
15889                 else
15890                         return 32*1024;
15891         } else if (gen >= 3) {
15892                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
15893                         return 8*1024;
15894                 else
15895                         return 16*1024;
15896         } else {
15897                 /* XXX DSPC is limited to 4k tiled */
15898                 return 8*1024;
15899         }
15900 }
15901
15902 static int intel_framebuffer_init(struct drm_device *dev,
15903                                   struct intel_framebuffer *intel_fb,
15904                                   struct drm_mode_fb_cmd2 *mode_cmd,
15905                                   struct drm_i915_gem_object *obj)
15906 {
15907         struct drm_i915_private *dev_priv = to_i915(dev);
15908         unsigned int tiling = i915_gem_object_get_tiling(obj);
15909         int ret;
15910         u32 pitch_limit, stride_alignment;
15911         struct drm_format_name_buf format_name;
15912
15913         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
15914
15915         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
15916                 /*
15917                  * If there's a fence, enforce that
15918                  * the fb modifier and tiling mode match.
15919                  */
15920                 if (tiling != I915_TILING_NONE &&
15921                     tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
15922                         DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
15923                         return -EINVAL;
15924                 }
15925         } else {
15926                 if (tiling == I915_TILING_X) {
15927                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
15928                 } else if (tiling == I915_TILING_Y) {
15929                         DRM_DEBUG("No Y tiling for legacy addfb\n");
15930                         return -EINVAL;
15931                 }
15932         }
15933
15934         /* Passed in modifier sanity checking. */
15935         switch (mode_cmd->modifier[0]) {
15936         case I915_FORMAT_MOD_Y_TILED:
15937         case I915_FORMAT_MOD_Yf_TILED:
15938                 if (INTEL_GEN(dev_priv) < 9) {
15939                         DRM_DEBUG("Unsupported tiling 0x%llx!\n",
15940                                   mode_cmd->modifier[0]);
15941                         return -EINVAL;
15942                 }
15943         case DRM_FORMAT_MOD_NONE:
15944         case I915_FORMAT_MOD_X_TILED:
15945                 break;
15946         default:
15947                 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
15948                           mode_cmd->modifier[0]);
15949                 return -EINVAL;
15950         }
15951
15952         /*
15953          * gen2/3 display engine uses the fence if present,
15954          * so the tiling mode must match the fb modifier exactly.
15955          */
15956         if (INTEL_INFO(dev_priv)->gen < 4 &&
15957             tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
15958                 DRM_DEBUG("tiling_mode must match fb modifier exactly on gen2/3\n");
15959                 return -EINVAL;
15960         }
15961
15962         stride_alignment = intel_fb_stride_alignment(dev_priv,
15963                                                      mode_cmd->modifier[0],
15964                                                      mode_cmd->pixel_format);
15965         if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
15966                 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
15967                           mode_cmd->pitches[0], stride_alignment);
15968                 return -EINVAL;
15969         }
15970
15971         pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->modifier[0],
15972                                            mode_cmd->pixel_format);
15973         if (mode_cmd->pitches[0] > pitch_limit) {
15974                 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
15975                           mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
15976                           "tiled" : "linear",
15977                           mode_cmd->pitches[0], pitch_limit);
15978                 return -EINVAL;
15979         }
15980
15981         /*
15982          * If there's a fence, enforce that
15983          * the fb pitch and fence stride match.
15984          */
15985         if (tiling != I915_TILING_NONE &&
15986             mode_cmd->pitches[0] != i915_gem_object_get_stride(obj)) {
15987                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
15988                           mode_cmd->pitches[0],
15989                           i915_gem_object_get_stride(obj));
15990                 return -EINVAL;
15991         }
15992
15993         /* Reject formats not supported by any plane early. */
15994         switch (mode_cmd->pixel_format) {
15995         case DRM_FORMAT_C8:
15996         case DRM_FORMAT_RGB565:
15997         case DRM_FORMAT_XRGB8888:
15998         case DRM_FORMAT_ARGB8888:
15999                 break;
16000         case DRM_FORMAT_XRGB1555:
16001                 if (INTEL_GEN(dev_priv) > 3) {
16002                         DRM_DEBUG("unsupported pixel format: %s\n",
16003                                   drm_get_format_name(mode_cmd->pixel_format, &format_name));
16004                         return -EINVAL;
16005                 }
16006                 break;
16007         case DRM_FORMAT_ABGR8888:
16008                 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
16009                     INTEL_GEN(dev_priv) < 9) {
16010                         DRM_DEBUG("unsupported pixel format: %s\n",
16011                                   drm_get_format_name(mode_cmd->pixel_format, &format_name));
16012                         return -EINVAL;
16013                 }
16014                 break;
16015         case DRM_FORMAT_XBGR8888:
16016         case DRM_FORMAT_XRGB2101010:
16017         case DRM_FORMAT_XBGR2101010:
16018                 if (INTEL_GEN(dev_priv) < 4) {
16019                         DRM_DEBUG("unsupported pixel format: %s\n",
16020                                   drm_get_format_name(mode_cmd->pixel_format, &format_name));
16021                         return -EINVAL;
16022                 }
16023                 break;
16024         case DRM_FORMAT_ABGR2101010:
16025                 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
16026                         DRM_DEBUG("unsupported pixel format: %s\n",
16027                                   drm_get_format_name(mode_cmd->pixel_format, &format_name));
16028                         return -EINVAL;
16029                 }
16030                 break;
16031         case DRM_FORMAT_YUYV:
16032         case DRM_FORMAT_UYVY:
16033         case DRM_FORMAT_YVYU:
16034         case DRM_FORMAT_VYUY:
16035                 if (INTEL_GEN(dev_priv) < 5) {
16036                         DRM_DEBUG("unsupported pixel format: %s\n",
16037                                   drm_get_format_name(mode_cmd->pixel_format, &format_name));
16038                         return -EINVAL;
16039                 }
16040                 break;
16041         default:
16042                 DRM_DEBUG("unsupported pixel format: %s\n",
16043                           drm_get_format_name(mode_cmd->pixel_format, &format_name));
16044                 return -EINVAL;
16045         }
16046
16047         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
16048         if (mode_cmd->offsets[0] != 0)
16049                 return -EINVAL;
16050
16051         drm_helper_mode_fill_fb_struct(dev, &intel_fb->base, mode_cmd);
16052         intel_fb->obj = obj;
16053
16054         ret = intel_fill_fb_info(dev_priv, &intel_fb->base);
16055         if (ret)
16056                 return ret;
16057
16058         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
16059         if (ret) {
16060                 DRM_ERROR("framebuffer init failed %d\n", ret);
16061                 return ret;
16062         }
16063
16064         intel_fb->obj->framebuffer_references++;
16065
16066         return 0;
16067 }
16068
16069 static struct drm_framebuffer *
16070 intel_user_framebuffer_create(struct drm_device *dev,
16071                               struct drm_file *filp,
16072                               const struct drm_mode_fb_cmd2 *user_mode_cmd)
16073 {
16074         struct drm_framebuffer *fb;
16075         struct drm_i915_gem_object *obj;
16076         struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
16077
16078         obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
16079         if (!obj)
16080                 return ERR_PTR(-ENOENT);
16081
16082         fb = intel_framebuffer_create(dev, &mode_cmd, obj);
16083         if (IS_ERR(fb))
16084                 i915_gem_object_put(obj);
16085
16086         return fb;
16087 }
16088
16089 static void intel_atomic_state_free(struct drm_atomic_state *state)
16090 {
16091         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
16092
16093         drm_atomic_state_default_release(state);
16094
16095         i915_sw_fence_fini(&intel_state->commit_ready);
16096
16097         kfree(state);
16098 }
16099
16100 static const struct drm_mode_config_funcs intel_mode_funcs = {
16101         .fb_create = intel_user_framebuffer_create,
16102         .output_poll_changed = intel_fbdev_output_poll_changed,
16103         .atomic_check = intel_atomic_check,
16104         .atomic_commit = intel_atomic_commit,
16105         .atomic_state_alloc = intel_atomic_state_alloc,
16106         .atomic_state_clear = intel_atomic_state_clear,
16107         .atomic_state_free = intel_atomic_state_free,
16108 };
16109
16110 /**
16111  * intel_init_display_hooks - initialize the display modesetting hooks
16112  * @dev_priv: device private
16113  */
16114 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
16115 {
16116         if (INTEL_INFO(dev_priv)->gen >= 9) {
16117                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
16118                 dev_priv->display.get_initial_plane_config =
16119                         skylake_get_initial_plane_config;
16120                 dev_priv->display.crtc_compute_clock =
16121                         haswell_crtc_compute_clock;
16122                 dev_priv->display.crtc_enable = haswell_crtc_enable;
16123                 dev_priv->display.crtc_disable = haswell_crtc_disable;
16124         } else if (HAS_DDI(dev_priv)) {
16125                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
16126                 dev_priv->display.get_initial_plane_config =
16127                         ironlake_get_initial_plane_config;
16128                 dev_priv->display.crtc_compute_clock =
16129                         haswell_crtc_compute_clock;
16130                 dev_priv->display.crtc_enable = haswell_crtc_enable;
16131                 dev_priv->display.crtc_disable = haswell_crtc_disable;
16132         } else if (HAS_PCH_SPLIT(dev_priv)) {
16133                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
16134                 dev_priv->display.get_initial_plane_config =
16135                         ironlake_get_initial_plane_config;
16136                 dev_priv->display.crtc_compute_clock =
16137                         ironlake_crtc_compute_clock;
16138                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
16139                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
16140         } else if (IS_CHERRYVIEW(dev_priv)) {
16141                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
16142                 dev_priv->display.get_initial_plane_config =
16143                         i9xx_get_initial_plane_config;
16144                 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
16145                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
16146                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
16147         } else if (IS_VALLEYVIEW(dev_priv)) {
16148                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
16149                 dev_priv->display.get_initial_plane_config =
16150                         i9xx_get_initial_plane_config;
16151                 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
16152                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
16153                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
16154         } else if (IS_G4X(dev_priv)) {
16155                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
16156                 dev_priv->display.get_initial_plane_config =
16157                         i9xx_get_initial_plane_config;
16158                 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
16159                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
16160                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
16161         } else if (IS_PINEVIEW(dev_priv)) {
16162                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
16163                 dev_priv->display.get_initial_plane_config =
16164                         i9xx_get_initial_plane_config;
16165                 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
16166                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
16167                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
16168         } else if (!IS_GEN2(dev_priv)) {
16169                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
16170                 dev_priv->display.get_initial_plane_config =
16171                         i9xx_get_initial_plane_config;
16172                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
16173                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
16174                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
16175         } else {
16176                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
16177                 dev_priv->display.get_initial_plane_config =
16178                         i9xx_get_initial_plane_config;
16179                 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
16180                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
16181                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
16182         }
16183
16184         /* Returns the core display clock speed */
16185         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
16186                 dev_priv->display.get_display_clock_speed =
16187                         skylake_get_display_clock_speed;
16188         else if (IS_GEN9_LP(dev_priv))
16189                 dev_priv->display.get_display_clock_speed =
16190                         broxton_get_display_clock_speed;
16191         else if (IS_BROADWELL(dev_priv))
16192                 dev_priv->display.get_display_clock_speed =
16193                         broadwell_get_display_clock_speed;
16194         else if (IS_HASWELL(dev_priv))
16195                 dev_priv->display.get_display_clock_speed =
16196                         haswell_get_display_clock_speed;
16197         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
16198                 dev_priv->display.get_display_clock_speed =
16199                         valleyview_get_display_clock_speed;
16200         else if (IS_GEN5(dev_priv))
16201                 dev_priv->display.get_display_clock_speed =
16202                         ilk_get_display_clock_speed;
16203         else if (IS_I945G(dev_priv) || IS_I965G(dev_priv) ||
16204                  IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
16205                 dev_priv->display.get_display_clock_speed =
16206                         i945_get_display_clock_speed;
16207         else if (IS_GM45(dev_priv))
16208                 dev_priv->display.get_display_clock_speed =
16209                         gm45_get_display_clock_speed;
16210         else if (IS_I965GM(dev_priv))
16211                 dev_priv->display.get_display_clock_speed =
16212                         i965gm_get_display_clock_speed;
16213         else if (IS_PINEVIEW(dev_priv))
16214                 dev_priv->display.get_display_clock_speed =
16215                         pnv_get_display_clock_speed;
16216         else if (IS_G33(dev_priv) || IS_G4X(dev_priv))
16217                 dev_priv->display.get_display_clock_speed =
16218                         g33_get_display_clock_speed;
16219         else if (IS_I915G(dev_priv))
16220                 dev_priv->display.get_display_clock_speed =
16221                         i915_get_display_clock_speed;
16222         else if (IS_I945GM(dev_priv) || IS_I845G(dev_priv))
16223                 dev_priv->display.get_display_clock_speed =
16224                         i9xx_misc_get_display_clock_speed;
16225         else if (IS_I915GM(dev_priv))
16226                 dev_priv->display.get_display_clock_speed =
16227                         i915gm_get_display_clock_speed;
16228         else if (IS_I865G(dev_priv))
16229                 dev_priv->display.get_display_clock_speed =
16230                         i865_get_display_clock_speed;
16231         else if (IS_I85X(dev_priv))
16232                 dev_priv->display.get_display_clock_speed =
16233                         i85x_get_display_clock_speed;
16234         else { /* 830 */
16235                 WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n");
16236                 dev_priv->display.get_display_clock_speed =
16237                         i830_get_display_clock_speed;
16238         }
16239
16240         if (IS_GEN5(dev_priv)) {
16241                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
16242         } else if (IS_GEN6(dev_priv)) {
16243                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
16244         } else if (IS_IVYBRIDGE(dev_priv)) {
16245                 /* FIXME: detect B0+ stepping and use auto training */
16246                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
16247         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
16248                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
16249         }
16250
16251         if (IS_BROADWELL(dev_priv)) {
16252                 dev_priv->display.modeset_commit_cdclk =
16253                         broadwell_modeset_commit_cdclk;
16254                 dev_priv->display.modeset_calc_cdclk =
16255                         broadwell_modeset_calc_cdclk;
16256         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
16257                 dev_priv->display.modeset_commit_cdclk =
16258                         valleyview_modeset_commit_cdclk;
16259                 dev_priv->display.modeset_calc_cdclk =
16260                         valleyview_modeset_calc_cdclk;
16261         } else if (IS_GEN9_LP(dev_priv)) {
16262                 dev_priv->display.modeset_commit_cdclk =
16263                         bxt_modeset_commit_cdclk;
16264                 dev_priv->display.modeset_calc_cdclk =
16265                         bxt_modeset_calc_cdclk;
16266         } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
16267                 dev_priv->display.modeset_commit_cdclk =
16268                         skl_modeset_commit_cdclk;
16269                 dev_priv->display.modeset_calc_cdclk =
16270                         skl_modeset_calc_cdclk;
16271         }
16272
16273         if (dev_priv->info.gen >= 9)
16274                 dev_priv->display.update_crtcs = skl_update_crtcs;
16275         else
16276                 dev_priv->display.update_crtcs = intel_update_crtcs;
16277
16278         switch (INTEL_INFO(dev_priv)->gen) {
16279         case 2:
16280                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
16281                 break;
16282
16283         case 3:
16284                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
16285                 break;
16286
16287         case 4:
16288         case 5:
16289                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
16290                 break;
16291
16292         case 6:
16293                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
16294                 break;
16295         case 7:
16296         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
16297                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
16298                 break;
16299         case 9:
16300                 /* Drop through - unsupported since execlist only. */
16301         default:
16302                 /* Default just returns -ENODEV to indicate unsupported */
16303                 dev_priv->display.queue_flip = intel_default_queue_flip;
16304         }
16305 }
16306
16307 /*
16308  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
16309  * resume, or other times.  This quirk makes sure that's the case for
16310  * affected systems.
16311  */
16312 static void quirk_pipea_force(struct drm_device *dev)
16313 {
16314         struct drm_i915_private *dev_priv = to_i915(dev);
16315
16316         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
16317         DRM_INFO("applying pipe a force quirk\n");
16318 }
16319
16320 static void quirk_pipeb_force(struct drm_device *dev)
16321 {
16322         struct drm_i915_private *dev_priv = to_i915(dev);
16323
16324         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
16325         DRM_INFO("applying pipe b force quirk\n");
16326 }
16327
16328 /*
16329  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
16330  */
16331 static void quirk_ssc_force_disable(struct drm_device *dev)
16332 {
16333         struct drm_i915_private *dev_priv = to_i915(dev);
16334         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
16335         DRM_INFO("applying lvds SSC disable quirk\n");
16336 }
16337
16338 /*
16339  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
16340  * brightness value
16341  */
16342 static void quirk_invert_brightness(struct drm_device *dev)
16343 {
16344         struct drm_i915_private *dev_priv = to_i915(dev);
16345         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
16346         DRM_INFO("applying inverted panel brightness quirk\n");
16347 }
16348
16349 /* Some VBT's incorrectly indicate no backlight is present */
16350 static void quirk_backlight_present(struct drm_device *dev)
16351 {
16352         struct drm_i915_private *dev_priv = to_i915(dev);
16353         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
16354         DRM_INFO("applying backlight present quirk\n");
16355 }
16356
16357 struct intel_quirk {
16358         int device;
16359         int subsystem_vendor;
16360         int subsystem_device;
16361         void (*hook)(struct drm_device *dev);
16362 };
16363
16364 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
16365 struct intel_dmi_quirk {
16366         void (*hook)(struct drm_device *dev);
16367         const struct dmi_system_id (*dmi_id_list)[];
16368 };
16369
16370 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
16371 {
16372         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
16373         return 1;
16374 }
16375
16376 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
16377         {
16378                 .dmi_id_list = &(const struct dmi_system_id[]) {
16379                         {
16380                                 .callback = intel_dmi_reverse_brightness,
16381                                 .ident = "NCR Corporation",
16382                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
16383                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
16384                                 },
16385                         },
16386                         { }  /* terminating entry */
16387                 },
16388                 .hook = quirk_invert_brightness,
16389         },
16390 };
16391
16392 static struct intel_quirk intel_quirks[] = {
16393         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
16394         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
16395
16396         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
16397         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
16398
16399         /* 830 needs to leave pipe A & dpll A up */
16400         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
16401
16402         /* 830 needs to leave pipe B & dpll B up */
16403         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
16404
16405         /* Lenovo U160 cannot use SSC on LVDS */
16406         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
16407
16408         /* Sony Vaio Y cannot use SSC on LVDS */
16409         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
16410
16411         /* Acer Aspire 5734Z must invert backlight brightness */
16412         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
16413
16414         /* Acer/eMachines G725 */
16415         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
16416
16417         /* Acer/eMachines e725 */
16418         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
16419
16420         /* Acer/Packard Bell NCL20 */
16421         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
16422
16423         /* Acer Aspire 4736Z */
16424         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
16425
16426         /* Acer Aspire 5336 */
16427         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
16428
16429         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
16430         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
16431
16432         /* Acer C720 Chromebook (Core i3 4005U) */
16433         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
16434
16435         /* Apple Macbook 2,1 (Core 2 T7400) */
16436         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
16437
16438         /* Apple Macbook 4,1 */
16439         { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
16440
16441         /* Toshiba CB35 Chromebook (Celeron 2955U) */
16442         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
16443
16444         /* HP Chromebook 14 (Celeron 2955U) */
16445         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
16446
16447         /* Dell Chromebook 11 */
16448         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
16449
16450         /* Dell Chromebook 11 (2015 version) */
16451         { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
16452 };
16453
16454 static void intel_init_quirks(struct drm_device *dev)
16455 {
16456         struct pci_dev *d = dev->pdev;
16457         int i;
16458
16459         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
16460                 struct intel_quirk *q = &intel_quirks[i];
16461
16462                 if (d->device == q->device &&
16463                     (d->subsystem_vendor == q->subsystem_vendor ||
16464                      q->subsystem_vendor == PCI_ANY_ID) &&
16465                     (d->subsystem_device == q->subsystem_device ||
16466                      q->subsystem_device == PCI_ANY_ID))
16467                         q->hook(dev);
16468         }
16469         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
16470                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
16471                         intel_dmi_quirks[i].hook(dev);
16472         }
16473 }
16474
16475 /* Disable the VGA plane that we never use */
16476 static void i915_disable_vga(struct drm_i915_private *dev_priv)
16477 {
16478         struct pci_dev *pdev = dev_priv->drm.pdev;
16479         u8 sr1;
16480         i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
16481
16482         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
16483         vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
16484         outb(SR01, VGA_SR_INDEX);
16485         sr1 = inb(VGA_SR_DATA);
16486         outb(sr1 | 1<<5, VGA_SR_DATA);
16487         vga_put(pdev, VGA_RSRC_LEGACY_IO);
16488         udelay(300);
16489
16490         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
16491         POSTING_READ(vga_reg);
16492 }
16493
16494 void intel_modeset_init_hw(struct drm_device *dev)
16495 {
16496         struct drm_i915_private *dev_priv = to_i915(dev);
16497
16498         intel_update_cdclk(dev_priv);
16499
16500         dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
16501
16502         intel_init_clock_gating(dev_priv);
16503 }
16504
16505 /*
16506  * Calculate what we think the watermarks should be for the state we've read
16507  * out of the hardware and then immediately program those watermarks so that
16508  * we ensure the hardware settings match our internal state.
16509  *
16510  * We can calculate what we think WM's should be by creating a duplicate of the
16511  * current state (which was constructed during hardware readout) and running it
16512  * through the atomic check code to calculate new watermark values in the
16513  * state object.
16514  */
16515 static void sanitize_watermarks(struct drm_device *dev)
16516 {
16517         struct drm_i915_private *dev_priv = to_i915(dev);
16518         struct drm_atomic_state *state;
16519         struct intel_atomic_state *intel_state;
16520         struct drm_crtc *crtc;
16521         struct drm_crtc_state *cstate;
16522         struct drm_modeset_acquire_ctx ctx;
16523         int ret;
16524         int i;
16525
16526         /* Only supported on platforms that use atomic watermark design */
16527         if (!dev_priv->display.optimize_watermarks)
16528                 return;
16529
16530         /*
16531          * We need to hold connection_mutex before calling duplicate_state so
16532          * that the connector loop is protected.
16533          */
16534         drm_modeset_acquire_init(&ctx, 0);
16535 retry:
16536         ret = drm_modeset_lock_all_ctx(dev, &ctx);
16537         if (ret == -EDEADLK) {
16538                 drm_modeset_backoff(&ctx);
16539                 goto retry;
16540         } else if (WARN_ON(ret)) {
16541                 goto fail;
16542         }
16543
16544         state = drm_atomic_helper_duplicate_state(dev, &ctx);
16545         if (WARN_ON(IS_ERR(state)))
16546                 goto fail;
16547
16548         intel_state = to_intel_atomic_state(state);
16549
16550         /*
16551          * Hardware readout is the only time we don't want to calculate
16552          * intermediate watermarks (since we don't trust the current
16553          * watermarks).
16554          */
16555         intel_state->skip_intermediate_wm = true;
16556
16557         ret = intel_atomic_check(dev, state);
16558         if (ret) {
16559                 /*
16560                  * If we fail here, it means that the hardware appears to be
16561                  * programmed in a way that shouldn't be possible, given our
16562                  * understanding of watermark requirements.  This might mean a
16563                  * mistake in the hardware readout code or a mistake in the
16564                  * watermark calculations for a given platform.  Raise a WARN
16565                  * so that this is noticeable.
16566                  *
16567                  * If this actually happens, we'll have to just leave the
16568                  * BIOS-programmed watermarks untouched and hope for the best.
16569                  */
16570                 WARN(true, "Could not determine valid watermarks for inherited state\n");
16571                 goto put_state;
16572         }
16573
16574         /* Write calculated watermark values back */
16575         for_each_crtc_in_state(state, crtc, cstate, i) {
16576                 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
16577
16578                 cs->wm.need_postvbl_update = true;
16579                 dev_priv->display.optimize_watermarks(intel_state, cs);
16580         }
16581
16582 put_state:
16583         drm_atomic_state_put(state);
16584 fail:
16585         drm_modeset_drop_locks(&ctx);
16586         drm_modeset_acquire_fini(&ctx);
16587 }
16588
16589 int intel_modeset_init(struct drm_device *dev)
16590 {
16591         struct drm_i915_private *dev_priv = to_i915(dev);
16592         struct i915_ggtt *ggtt = &dev_priv->ggtt;
16593         enum pipe pipe;
16594         struct intel_crtc *crtc;
16595
16596         drm_mode_config_init(dev);
16597
16598         dev->mode_config.min_width = 0;
16599         dev->mode_config.min_height = 0;
16600
16601         dev->mode_config.preferred_depth = 24;
16602         dev->mode_config.prefer_shadow = 1;
16603
16604         dev->mode_config.allow_fb_modifiers = true;
16605
16606         dev->mode_config.funcs = &intel_mode_funcs;
16607
16608         intel_init_quirks(dev);
16609
16610         intel_init_pm(dev_priv);
16611
16612         if (INTEL_INFO(dev_priv)->num_pipes == 0)
16613                 return 0;
16614
16615         /*
16616          * There may be no VBT; and if the BIOS enabled SSC we can
16617          * just keep using it to avoid unnecessary flicker.  Whereas if the
16618          * BIOS isn't using it, don't assume it will work even if the VBT
16619          * indicates as much.
16620          */
16621         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
16622                 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
16623                                             DREF_SSC1_ENABLE);
16624
16625                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
16626                         DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
16627                                      bios_lvds_use_ssc ? "en" : "dis",
16628                                      dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
16629                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
16630                 }
16631         }
16632
16633         if (IS_GEN2(dev_priv)) {
16634                 dev->mode_config.max_width = 2048;
16635                 dev->mode_config.max_height = 2048;
16636         } else if (IS_GEN3(dev_priv)) {
16637                 dev->mode_config.max_width = 4096;
16638                 dev->mode_config.max_height = 4096;
16639         } else {
16640                 dev->mode_config.max_width = 8192;
16641                 dev->mode_config.max_height = 8192;
16642         }
16643
16644         if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
16645                 dev->mode_config.cursor_width = IS_I845G(dev_priv) ? 64 : 512;
16646                 dev->mode_config.cursor_height = 1023;
16647         } else if (IS_GEN2(dev_priv)) {
16648                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
16649                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
16650         } else {
16651                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
16652                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
16653         }
16654
16655         dev->mode_config.fb_base = ggtt->mappable_base;
16656
16657         DRM_DEBUG_KMS("%d display pipe%s available.\n",
16658                       INTEL_INFO(dev_priv)->num_pipes,
16659                       INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : "");
16660
16661         for_each_pipe(dev_priv, pipe) {
16662                 int ret;
16663
16664                 ret = intel_crtc_init(dev_priv, pipe);
16665                 if (ret) {
16666                         drm_mode_config_cleanup(dev);
16667                         return ret;
16668                 }
16669         }
16670
16671         intel_update_czclk(dev_priv);
16672         intel_update_cdclk(dev_priv);
16673         dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
16674
16675         intel_shared_dpll_init(dev);
16676
16677         if (dev_priv->max_cdclk_freq == 0)
16678                 intel_update_max_cdclk(dev_priv);
16679
16680         /* Just disable it once at startup */
16681         i915_disable_vga(dev_priv);
16682         intel_setup_outputs(dev_priv);
16683
16684         drm_modeset_lock_all(dev);
16685         intel_modeset_setup_hw_state(dev);
16686         drm_modeset_unlock_all(dev);
16687
16688         for_each_intel_crtc(dev, crtc) {
16689                 struct intel_initial_plane_config plane_config = {};
16690
16691                 if (!crtc->active)
16692                         continue;
16693
16694                 /*
16695                  * Note that reserving the BIOS fb up front prevents us
16696                  * from stuffing other stolen allocations like the ring
16697                  * on top.  This prevents some ugliness at boot time, and
16698                  * can even allow for smooth boot transitions if the BIOS
16699                  * fb is large enough for the active pipe configuration.
16700                  */
16701                 dev_priv->display.get_initial_plane_config(crtc,
16702                                                            &plane_config);
16703
16704                 /*
16705                  * If the fb is shared between multiple heads, we'll
16706                  * just get the first one.
16707                  */
16708                 intel_find_initial_plane_obj(crtc, &plane_config);
16709         }
16710
16711         /*
16712          * Make sure hardware watermarks really match the state we read out.
16713          * Note that we need to do this after reconstructing the BIOS fb's
16714          * since the watermark calculation done here will use pstate->fb.
16715          */
16716         sanitize_watermarks(dev);
16717
16718         return 0;
16719 }
16720
16721 static void intel_enable_pipe_a(struct drm_device *dev)
16722 {
16723         struct intel_connector *connector;
16724         struct drm_connector *crt = NULL;
16725         struct intel_load_detect_pipe load_detect_temp;
16726         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
16727
16728         /* We can't just switch on the pipe A, we need to set things up with a
16729          * proper mode and output configuration. As a gross hack, enable pipe A
16730          * by enabling the load detect pipe once. */
16731         for_each_intel_connector(dev, connector) {
16732                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
16733                         crt = &connector->base;
16734                         break;
16735                 }
16736         }
16737
16738         if (!crt)
16739                 return;
16740
16741         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
16742                 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
16743 }
16744
16745 static bool
16746 intel_check_plane_mapping(struct intel_crtc *crtc)
16747 {
16748         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
16749         u32 val;
16750
16751         if (INTEL_INFO(dev_priv)->num_pipes == 1)
16752                 return true;
16753
16754         val = I915_READ(DSPCNTR(!crtc->plane));
16755
16756         if ((val & DISPLAY_PLANE_ENABLE) &&
16757             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
16758                 return false;
16759
16760         return true;
16761 }
16762
16763 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
16764 {
16765         struct drm_device *dev = crtc->base.dev;
16766         struct intel_encoder *encoder;
16767
16768         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
16769                 return true;
16770
16771         return false;
16772 }
16773
16774 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
16775 {
16776         struct drm_device *dev = encoder->base.dev;
16777         struct intel_connector *connector;
16778
16779         for_each_connector_on_encoder(dev, &encoder->base, connector)
16780                 return connector;
16781
16782         return NULL;
16783 }
16784
16785 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
16786                               enum transcoder pch_transcoder)
16787 {
16788         return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
16789                 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == TRANSCODER_A);
16790 }
16791
16792 static void intel_sanitize_crtc(struct intel_crtc *crtc)
16793 {
16794         struct drm_device *dev = crtc->base.dev;
16795         struct drm_i915_private *dev_priv = to_i915(dev);
16796         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
16797
16798         /* Clear any frame start delays used for debugging left by the BIOS */
16799         if (!transcoder_is_dsi(cpu_transcoder)) {
16800                 i915_reg_t reg = PIPECONF(cpu_transcoder);
16801
16802                 I915_WRITE(reg,
16803                            I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
16804         }
16805
16806         /* restore vblank interrupts to correct state */
16807         drm_crtc_vblank_reset(&crtc->base);
16808         if (crtc->active) {
16809                 struct intel_plane *plane;
16810
16811                 drm_crtc_vblank_on(&crtc->base);
16812
16813                 /* Disable everything but the primary plane */
16814                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
16815                         if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
16816                                 continue;
16817
16818                         plane->disable_plane(&plane->base, &crtc->base);
16819                 }
16820         }
16821
16822         /* We need to sanitize the plane -> pipe mapping first because this will
16823          * disable the crtc (and hence change the state) if it is wrong. Note
16824          * that gen4+ has a fixed plane -> pipe mapping.  */
16825         if (INTEL_GEN(dev_priv) < 4 && !intel_check_plane_mapping(crtc)) {
16826                 bool plane;
16827
16828                 DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n",
16829                               crtc->base.base.id, crtc->base.name);
16830
16831                 /* Pipe has the wrong plane attached and the plane is active.
16832                  * Temporarily change the plane mapping and disable everything
16833                  * ...  */
16834                 plane = crtc->plane;
16835                 crtc->base.primary->state->visible = true;
16836                 crtc->plane = !plane;
16837                 intel_crtc_disable_noatomic(&crtc->base);
16838                 crtc->plane = plane;
16839         }
16840
16841         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
16842             crtc->pipe == PIPE_A && !crtc->active) {
16843                 /* BIOS forgot to enable pipe A, this mostly happens after
16844                  * resume. Force-enable the pipe to fix this, the update_dpms
16845                  * call below we restore the pipe to the right state, but leave
16846                  * the required bits on. */
16847                 intel_enable_pipe_a(dev);
16848         }
16849
16850         /* Adjust the state of the output pipe according to whether we
16851          * have active connectors/encoders. */
16852         if (crtc->active && !intel_crtc_has_encoders(crtc))
16853                 intel_crtc_disable_noatomic(&crtc->base);
16854
16855         if (crtc->active || HAS_GMCH_DISPLAY(dev_priv)) {
16856                 /*
16857                  * We start out with underrun reporting disabled to avoid races.
16858                  * For correct bookkeeping mark this on active crtcs.
16859                  *
16860                  * Also on gmch platforms we dont have any hardware bits to
16861                  * disable the underrun reporting. Which means we need to start
16862                  * out with underrun reporting disabled also on inactive pipes,
16863                  * since otherwise we'll complain about the garbage we read when
16864                  * e.g. coming up after runtime pm.
16865                  *
16866                  * No protection against concurrent access is required - at
16867                  * worst a fifo underrun happens which also sets this to false.
16868                  */
16869                 crtc->cpu_fifo_underrun_disabled = true;
16870                 /*
16871                  * We track the PCH trancoder underrun reporting state
16872                  * within the crtc. With crtc for pipe A housing the underrun
16873                  * reporting state for PCH transcoder A, crtc for pipe B housing
16874                  * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
16875                  * and marking underrun reporting as disabled for the non-existing
16876                  * PCH transcoders B and C would prevent enabling the south
16877                  * error interrupt (see cpt_can_enable_serr_int()).
16878                  */
16879                 if (has_pch_trancoder(dev_priv, (enum transcoder)crtc->pipe))
16880                         crtc->pch_fifo_underrun_disabled = true;
16881         }
16882 }
16883
16884 static void intel_sanitize_encoder(struct intel_encoder *encoder)
16885 {
16886         struct intel_connector *connector;
16887
16888         /* We need to check both for a crtc link (meaning that the
16889          * encoder is active and trying to read from a pipe) and the
16890          * pipe itself being active. */
16891         bool has_active_crtc = encoder->base.crtc &&
16892                 to_intel_crtc(encoder->base.crtc)->active;
16893
16894         connector = intel_encoder_find_connector(encoder);
16895         if (connector && !has_active_crtc) {
16896                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
16897                               encoder->base.base.id,
16898                               encoder->base.name);
16899
16900                 /* Connector is active, but has no active pipe. This is
16901                  * fallout from our resume register restoring. Disable
16902                  * the encoder manually again. */
16903                 if (encoder->base.crtc) {
16904                         struct drm_crtc_state *crtc_state = encoder->base.crtc->state;
16905
16906                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
16907                                       encoder->base.base.id,
16908                                       encoder->base.name);
16909                         encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
16910                         if (encoder->post_disable)
16911                                 encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
16912                 }
16913                 encoder->base.crtc = NULL;
16914
16915                 /* Inconsistent output/port/pipe state happens presumably due to
16916                  * a bug in one of the get_hw_state functions. Or someplace else
16917                  * in our code, like the register restore mess on resume. Clamp
16918                  * things to off as a safer default. */
16919
16920                 connector->base.dpms = DRM_MODE_DPMS_OFF;
16921                 connector->base.encoder = NULL;
16922         }
16923         /* Enabled encoders without active connectors will be fixed in
16924          * the crtc fixup. */
16925 }
16926
16927 void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv)
16928 {
16929         i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
16930
16931         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
16932                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
16933                 i915_disable_vga(dev_priv);
16934         }
16935 }
16936
16937 void i915_redisable_vga(struct drm_i915_private *dev_priv)
16938 {
16939         /* This function can be called both from intel_modeset_setup_hw_state or
16940          * at a very early point in our resume sequence, where the power well
16941          * structures are not yet restored. Since this function is at a very
16942          * paranoid "someone might have enabled VGA while we were not looking"
16943          * level, just check if the power well is enabled instead of trying to
16944          * follow the "don't touch the power well if we don't need it" policy
16945          * the rest of the driver uses. */
16946         if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
16947                 return;
16948
16949         i915_redisable_vga_power_on(dev_priv);
16950
16951         intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
16952 }
16953
16954 static bool primary_get_hw_state(struct intel_plane *plane)
16955 {
16956         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
16957
16958         return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
16959 }
16960
16961 /* FIXME read out full plane state for all planes */
16962 static void readout_plane_state(struct intel_crtc *crtc)
16963 {
16964         struct drm_plane *primary = crtc->base.primary;
16965         struct intel_plane_state *plane_state =
16966                 to_intel_plane_state(primary->state);
16967
16968         plane_state->base.visible = crtc->active &&
16969                 primary_get_hw_state(to_intel_plane(primary));
16970
16971         if (plane_state->base.visible)
16972                 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
16973 }
16974
16975 static void intel_modeset_readout_hw_state(struct drm_device *dev)
16976 {
16977         struct drm_i915_private *dev_priv = to_i915(dev);
16978         enum pipe pipe;
16979         struct intel_crtc *crtc;
16980         struct intel_encoder *encoder;
16981         struct intel_connector *connector;
16982         int i;
16983
16984         dev_priv->active_crtcs = 0;
16985
16986         for_each_intel_crtc(dev, crtc) {
16987                 struct intel_crtc_state *crtc_state = crtc->config;
16988
16989                 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
16990                 memset(crtc_state, 0, sizeof(*crtc_state));
16991                 crtc_state->base.crtc = &crtc->base;
16992
16993                 crtc_state->base.active = crtc_state->base.enable =
16994                         dev_priv->display.get_pipe_config(crtc, crtc_state);
16995
16996                 crtc->base.enabled = crtc_state->base.enable;
16997                 crtc->active = crtc_state->base.active;
16998
16999                 if (crtc_state->base.active)
17000                         dev_priv->active_crtcs |= 1 << crtc->pipe;
17001
17002                 readout_plane_state(crtc);
17003
17004                 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
17005                               crtc->base.base.id, crtc->base.name,
17006                               enableddisabled(crtc->active));
17007         }
17008
17009         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
17010                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
17011
17012                 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
17013                                                   &pll->state.hw_state);
17014                 pll->state.crtc_mask = 0;
17015                 for_each_intel_crtc(dev, crtc) {
17016                         if (crtc->active && crtc->config->shared_dpll == pll)
17017                                 pll->state.crtc_mask |= 1 << crtc->pipe;
17018                 }
17019                 pll->active_mask = pll->state.crtc_mask;
17020
17021                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
17022                               pll->name, pll->state.crtc_mask, pll->on);
17023         }
17024
17025         for_each_intel_encoder(dev, encoder) {
17026                 pipe = 0;
17027
17028                 if (encoder->get_hw_state(encoder, &pipe)) {
17029                         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
17030
17031                         encoder->base.crtc = &crtc->base;
17032                         crtc->config->output_types |= 1 << encoder->type;
17033                         encoder->get_config(encoder, crtc->config);
17034                 } else {
17035                         encoder->base.crtc = NULL;
17036                 }
17037
17038                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
17039                               encoder->base.base.id, encoder->base.name,
17040                               enableddisabled(encoder->base.crtc),
17041                               pipe_name(pipe));
17042         }
17043
17044         for_each_intel_connector(dev, connector) {
17045                 if (connector->get_hw_state(connector)) {
17046                         connector->base.dpms = DRM_MODE_DPMS_ON;
17047
17048                         encoder = connector->encoder;
17049                         connector->base.encoder = &encoder->base;
17050
17051                         if (encoder->base.crtc &&
17052                             encoder->base.crtc->state->active) {
17053                                 /*
17054                                  * This has to be done during hardware readout
17055                                  * because anything calling .crtc_disable may
17056                                  * rely on the connector_mask being accurate.
17057                                  */
17058                                 encoder->base.crtc->state->connector_mask |=
17059                                         1 << drm_connector_index(&connector->base);
17060                                 encoder->base.crtc->state->encoder_mask |=
17061                                         1 << drm_encoder_index(&encoder->base);
17062                         }
17063
17064                 } else {
17065                         connector->base.dpms = DRM_MODE_DPMS_OFF;
17066                         connector->base.encoder = NULL;
17067                 }
17068                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
17069                               connector->base.base.id, connector->base.name,
17070                               enableddisabled(connector->base.encoder));
17071         }
17072
17073         for_each_intel_crtc(dev, crtc) {
17074                 int pixclk = 0;
17075
17076                 crtc->base.hwmode = crtc->config->base.adjusted_mode;
17077
17078                 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
17079                 if (crtc->base.state->active) {
17080                         intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
17081                         intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
17082                         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
17083
17084                         /*
17085                          * The initial mode needs to be set in order to keep
17086                          * the atomic core happy. It wants a valid mode if the
17087                          * crtc's enabled, so we do the above call.
17088                          *
17089                          * But we don't set all the derived state fully, hence
17090                          * set a flag to indicate that a full recalculation is
17091                          * needed on the next commit.
17092                          */
17093                         crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
17094
17095                         if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
17096                                 pixclk = ilk_pipe_pixel_rate(crtc->config);
17097                         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
17098                                 pixclk = crtc->config->base.adjusted_mode.crtc_clock;
17099                         else
17100                                 WARN_ON(dev_priv->display.modeset_calc_cdclk);
17101
17102                         /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
17103                         if (IS_BROADWELL(dev_priv) && crtc->config->ips_enabled)
17104                                 pixclk = DIV_ROUND_UP(pixclk * 100, 95);
17105
17106                         drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
17107                         update_scanline_offset(crtc);
17108                 }
17109
17110                 dev_priv->min_pixclk[crtc->pipe] = pixclk;
17111
17112                 intel_pipe_config_sanity_check(dev_priv, crtc->config);
17113         }
17114 }
17115
17116 /* Scan out the current hw modeset state,
17117  * and sanitizes it to the current state
17118  */
17119 static void
17120 intel_modeset_setup_hw_state(struct drm_device *dev)
17121 {
17122         struct drm_i915_private *dev_priv = to_i915(dev);
17123         enum pipe pipe;
17124         struct intel_crtc *crtc;
17125         struct intel_encoder *encoder;
17126         int i;
17127
17128         intel_modeset_readout_hw_state(dev);
17129
17130         /* HW state is read out, now we need to sanitize this mess. */
17131         for_each_intel_encoder(dev, encoder) {
17132                 intel_sanitize_encoder(encoder);
17133         }
17134
17135         for_each_pipe(dev_priv, pipe) {
17136                 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
17137
17138                 intel_sanitize_crtc(crtc);
17139                 intel_dump_pipe_config(crtc, crtc->config,
17140                                        "[setup_hw_state]");
17141         }
17142
17143         intel_modeset_update_connector_atomic_state(dev);
17144
17145         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
17146                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
17147
17148                 if (!pll->on || pll->active_mask)
17149                         continue;
17150
17151                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
17152
17153                 pll->funcs.disable(dev_priv, pll);
17154                 pll->on = false;
17155         }
17156
17157         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
17158                 vlv_wm_get_hw_state(dev);
17159         else if (IS_GEN9(dev_priv))
17160                 skl_wm_get_hw_state(dev);
17161         else if (HAS_PCH_SPLIT(dev_priv))
17162                 ilk_wm_get_hw_state(dev);
17163
17164         for_each_intel_crtc(dev, crtc) {
17165                 unsigned long put_domains;
17166
17167                 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
17168                 if (WARN_ON(put_domains))
17169                         modeset_put_power_domains(dev_priv, put_domains);
17170         }
17171         intel_display_set_init_power(dev_priv, false);
17172
17173         intel_fbc_init_pipe_state(dev_priv);
17174 }
17175
17176 void intel_display_resume(struct drm_device *dev)
17177 {
17178         struct drm_i915_private *dev_priv = to_i915(dev);
17179         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
17180         struct drm_modeset_acquire_ctx ctx;
17181         int ret;
17182
17183         dev_priv->modeset_restore_state = NULL;
17184         if (state)
17185                 state->acquire_ctx = &ctx;
17186
17187         /*
17188          * This is a cludge because with real atomic modeset mode_config.mutex
17189          * won't be taken. Unfortunately some probed state like
17190          * audio_codec_enable is still protected by mode_config.mutex, so lock
17191          * it here for now.
17192          */
17193         mutex_lock(&dev->mode_config.mutex);
17194         drm_modeset_acquire_init(&ctx, 0);
17195
17196         while (1) {
17197                 ret = drm_modeset_lock_all_ctx(dev, &ctx);
17198                 if (ret != -EDEADLK)
17199                         break;
17200
17201                 drm_modeset_backoff(&ctx);
17202         }
17203
17204         if (!ret)
17205                 ret = __intel_display_resume(dev, state);
17206
17207         drm_modeset_drop_locks(&ctx);
17208         drm_modeset_acquire_fini(&ctx);
17209         mutex_unlock(&dev->mode_config.mutex);
17210
17211         if (ret)
17212                 DRM_ERROR("Restoring old state failed with %i\n", ret);
17213         if (state)
17214                 drm_atomic_state_put(state);
17215 }
17216
17217 void intel_modeset_gem_init(struct drm_device *dev)
17218 {
17219         struct drm_i915_private *dev_priv = to_i915(dev);
17220
17221         intel_init_gt_powersave(dev_priv);
17222
17223         intel_modeset_init_hw(dev);
17224
17225         intel_setup_overlay(dev_priv);
17226 }
17227
17228 int intel_connector_register(struct drm_connector *connector)
17229 {
17230         struct intel_connector *intel_connector = to_intel_connector(connector);
17231         int ret;
17232
17233         ret = intel_backlight_device_register(intel_connector);
17234         if (ret)
17235                 goto err;
17236
17237         return 0;
17238
17239 err:
17240         return ret;
17241 }
17242
17243 void intel_connector_unregister(struct drm_connector *connector)
17244 {
17245         struct intel_connector *intel_connector = to_intel_connector(connector);
17246
17247         intel_backlight_device_unregister(intel_connector);
17248         intel_panel_destroy_backlight(connector);
17249 }
17250
17251 void intel_modeset_cleanup(struct drm_device *dev)
17252 {
17253         struct drm_i915_private *dev_priv = to_i915(dev);
17254
17255         intel_disable_gt_powersave(dev_priv);
17256
17257         /*
17258          * Interrupts and polling as the first thing to avoid creating havoc.
17259          * Too much stuff here (turning of connectors, ...) would
17260          * experience fancy races otherwise.
17261          */
17262         intel_irq_uninstall(dev_priv);
17263
17264         /*
17265          * Due to the hpd irq storm handling the hotplug work can re-arm the
17266          * poll handlers. Hence disable polling after hpd handling is shut down.
17267          */
17268         drm_kms_helper_poll_fini(dev);
17269
17270         intel_unregister_dsm_handler();
17271
17272         intel_fbc_global_disable(dev_priv);
17273
17274         /* flush any delayed tasks or pending work */
17275         flush_scheduled_work();
17276
17277         drm_mode_config_cleanup(dev);
17278
17279         intel_cleanup_overlay(dev_priv);
17280
17281         intel_cleanup_gt_powersave(dev_priv);
17282
17283         intel_teardown_gmbus(dev_priv);
17284 }
17285
17286 void intel_connector_attach_encoder(struct intel_connector *connector,
17287                                     struct intel_encoder *encoder)
17288 {
17289         connector->encoder = encoder;
17290         drm_mode_connector_attach_encoder(&connector->base,
17291                                           &encoder->base);
17292 }
17293
17294 /*
17295  * set vga decode state - true == enable VGA decode
17296  */
17297 int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state)
17298 {
17299         unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
17300         u16 gmch_ctrl;
17301
17302         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
17303                 DRM_ERROR("failed to read control word\n");
17304                 return -EIO;
17305         }
17306
17307         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
17308                 return 0;
17309
17310         if (state)
17311                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
17312         else
17313                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
17314
17315         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
17316                 DRM_ERROR("failed to write control word\n");
17317                 return -EIO;
17318         }
17319
17320         return 0;
17321 }
17322
17323 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
17324
17325 struct intel_display_error_state {
17326
17327         u32 power_well_driver;
17328
17329         int num_transcoders;
17330
17331         struct intel_cursor_error_state {
17332                 u32 control;
17333                 u32 position;
17334                 u32 base;
17335                 u32 size;
17336         } cursor[I915_MAX_PIPES];
17337
17338         struct intel_pipe_error_state {
17339                 bool power_domain_on;
17340                 u32 source;
17341                 u32 stat;
17342         } pipe[I915_MAX_PIPES];
17343
17344         struct intel_plane_error_state {
17345                 u32 control;
17346                 u32 stride;
17347                 u32 size;
17348                 u32 pos;
17349                 u32 addr;
17350                 u32 surface;
17351                 u32 tile_offset;
17352         } plane[I915_MAX_PIPES];
17353
17354         struct intel_transcoder_error_state {
17355                 bool power_domain_on;
17356                 enum transcoder cpu_transcoder;
17357
17358                 u32 conf;
17359
17360                 u32 htotal;
17361                 u32 hblank;
17362                 u32 hsync;
17363                 u32 vtotal;
17364                 u32 vblank;
17365                 u32 vsync;
17366         } transcoder[4];
17367 };
17368
17369 struct intel_display_error_state *
17370 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
17371 {
17372         struct intel_display_error_state *error;
17373         int transcoders[] = {
17374                 TRANSCODER_A,
17375                 TRANSCODER_B,
17376                 TRANSCODER_C,
17377                 TRANSCODER_EDP,
17378         };
17379         int i;
17380
17381         if (INTEL_INFO(dev_priv)->num_pipes == 0)
17382                 return NULL;
17383
17384         error = kzalloc(sizeof(*error), GFP_ATOMIC);
17385         if (error == NULL)
17386                 return NULL;
17387
17388         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
17389                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
17390
17391         for_each_pipe(dev_priv, i) {
17392                 error->pipe[i].power_domain_on =
17393                         __intel_display_power_is_enabled(dev_priv,
17394                                                          POWER_DOMAIN_PIPE(i));
17395                 if (!error->pipe[i].power_domain_on)
17396                         continue;
17397
17398                 error->cursor[i].control = I915_READ(CURCNTR(i));
17399                 error->cursor[i].position = I915_READ(CURPOS(i));
17400                 error->cursor[i].base = I915_READ(CURBASE(i));
17401
17402                 error->plane[i].control = I915_READ(DSPCNTR(i));
17403                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
17404                 if (INTEL_GEN(dev_priv) <= 3) {
17405                         error->plane[i].size = I915_READ(DSPSIZE(i));
17406                         error->plane[i].pos = I915_READ(DSPPOS(i));
17407                 }
17408                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
17409                         error->plane[i].addr = I915_READ(DSPADDR(i));
17410                 if (INTEL_GEN(dev_priv) >= 4) {
17411                         error->plane[i].surface = I915_READ(DSPSURF(i));
17412                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
17413                 }
17414
17415                 error->pipe[i].source = I915_READ(PIPESRC(i));
17416
17417                 if (HAS_GMCH_DISPLAY(dev_priv))
17418                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
17419         }
17420
17421         /* Note: this does not include DSI transcoders. */
17422         error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
17423         if (HAS_DDI(dev_priv))
17424                 error->num_transcoders++; /* Account for eDP. */
17425
17426         for (i = 0; i < error->num_transcoders; i++) {
17427                 enum transcoder cpu_transcoder = transcoders[i];
17428
17429                 error->transcoder[i].power_domain_on =
17430                         __intel_display_power_is_enabled(dev_priv,
17431                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
17432                 if (!error->transcoder[i].power_domain_on)
17433                         continue;
17434
17435                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
17436
17437                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
17438                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
17439                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
17440                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
17441                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
17442                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
17443                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
17444         }
17445
17446         return error;
17447 }
17448
17449 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
17450
17451 void
17452 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
17453                                 struct drm_i915_private *dev_priv,
17454                                 struct intel_display_error_state *error)
17455 {
17456         int i;
17457
17458         if (!error)
17459                 return;
17460
17461         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes);
17462         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
17463                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
17464                            error->power_well_driver);
17465         for_each_pipe(dev_priv, i) {
17466                 err_printf(m, "Pipe [%d]:\n", i);
17467                 err_printf(m, "  Power: %s\n",
17468                            onoff(error->pipe[i].power_domain_on));
17469                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
17470                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
17471
17472                 err_printf(m, "Plane [%d]:\n", i);
17473                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
17474                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
17475                 if (INTEL_GEN(dev_priv) <= 3) {
17476                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
17477                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
17478                 }
17479                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
17480                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
17481                 if (INTEL_GEN(dev_priv) >= 4) {
17482                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
17483                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
17484                 }
17485
17486                 err_printf(m, "Cursor [%d]:\n", i);
17487                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
17488                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
17489                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
17490         }
17491
17492         for (i = 0; i < error->num_transcoders; i++) {
17493                 err_printf(m, "CPU transcoder: %s\n",
17494                            transcoder_name(error->transcoder[i].cpu_transcoder));
17495                 err_printf(m, "  Power: %s\n",
17496                            onoff(error->transcoder[i].power_domain_on));
17497                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
17498                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
17499                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
17500                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
17501                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
17502                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
17503                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
17504         }
17505 }
17506
17507 #endif