2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_edid.h>
35 #include "intel_drv.h"
36 #include <drm/i915_drm.h>
39 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
46 static const struct dp_link_dpll gen4_dpll[] = {
48 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
50 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
53 static const struct dp_link_dpll pch_dpll[] = {
55 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
57 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
60 static const struct dp_link_dpll vlv_dpll[] = {
62 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
64 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
68 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
69 * @intel_dp: DP struct
71 * If a CPU or PCH DP output is attached to an eDP panel, this function
72 * will return true, and false otherwise.
74 static bool is_edp(struct intel_dp *intel_dp)
76 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
78 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
81 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
83 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
85 return intel_dig_port->base.base.dev;
88 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
90 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
93 static void intel_dp_link_down(struct intel_dp *intel_dp);
96 intel_dp_max_link_bw(struct intel_dp *intel_dp)
98 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
100 switch (max_link_bw) {
101 case DP_LINK_BW_1_62:
104 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
105 max_link_bw = DP_LINK_BW_2_7;
108 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
110 max_link_bw = DP_LINK_BW_1_62;
117 * The units on the numbers in the next two are... bizarre. Examples will
118 * make it clearer; this one parallels an example in the eDP spec.
120 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
122 * 270000 * 1 * 8 / 10 == 216000
124 * The actual data capacity of that configuration is 2.16Gbit/s, so the
125 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
126 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
127 * 119000. At 18bpp that's 2142000 kilobits per second.
129 * Thus the strange-looking division by 10 in intel_dp_link_required, to
130 * get the result in decakilobits instead of kilobits.
134 intel_dp_link_required(int pixel_clock, int bpp)
136 return (pixel_clock * bpp + 9) / 10;
140 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
142 return (max_link_clock * max_lanes * 8) / 10;
146 intel_dp_mode_valid(struct drm_connector *connector,
147 struct drm_display_mode *mode)
149 struct intel_dp *intel_dp = intel_attached_dp(connector);
150 struct intel_connector *intel_connector = to_intel_connector(connector);
151 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
152 int target_clock = mode->clock;
153 int max_rate, mode_rate, max_lanes, max_link_clock;
155 if (is_edp(intel_dp) && fixed_mode) {
156 if (mode->hdisplay > fixed_mode->hdisplay)
159 if (mode->vdisplay > fixed_mode->vdisplay)
162 target_clock = fixed_mode->clock;
165 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
166 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
168 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
169 mode_rate = intel_dp_link_required(target_clock, 18);
171 if (mode_rate > max_rate)
172 return MODE_CLOCK_HIGH;
174 if (mode->clock < 10000)
175 return MODE_CLOCK_LOW;
177 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
178 return MODE_H_ILLEGAL;
184 pack_aux(uint8_t *src, int src_bytes)
191 for (i = 0; i < src_bytes; i++)
192 v |= ((uint32_t) src[i]) << ((3-i) * 8);
197 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
202 for (i = 0; i < dst_bytes; i++)
203 dst[i] = src >> ((3-i) * 8);
206 /* hrawclock is 1/4 the FSB frequency */
208 intel_hrawclk(struct drm_device *dev)
210 struct drm_i915_private *dev_priv = dev->dev_private;
213 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
214 if (IS_VALLEYVIEW(dev))
217 clkcfg = I915_READ(CLKCFG);
218 switch (clkcfg & CLKCFG_FSB_MASK) {
227 case CLKCFG_FSB_1067:
229 case CLKCFG_FSB_1333:
231 /* these two are just a guess; one of them might be right */
232 case CLKCFG_FSB_1600:
233 case CLKCFG_FSB_1600_ALT:
241 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
242 struct intel_dp *intel_dp,
243 struct edp_power_seq *out);
245 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
246 struct intel_dp *intel_dp,
247 struct edp_power_seq *out);
250 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
252 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
253 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
254 struct drm_device *dev = intel_dig_port->base.base.dev;
255 struct drm_i915_private *dev_priv = dev->dev_private;
256 enum port port = intel_dig_port->port;
259 /* modeset should have pipe */
261 return to_intel_crtc(crtc)->pipe;
263 /* init time, try to find a pipe with this port selected */
264 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
265 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
266 PANEL_PORT_SELECT_MASK;
267 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
269 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
277 static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
279 struct drm_device *dev = intel_dp_to_dev(intel_dp);
281 if (HAS_PCH_SPLIT(dev))
282 return PCH_PP_CONTROL;
284 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
287 static u32 _pp_stat_reg(struct intel_dp *intel_dp)
289 struct drm_device *dev = intel_dp_to_dev(intel_dp);
291 if (HAS_PCH_SPLIT(dev))
292 return PCH_PP_STATUS;
294 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
297 static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
299 struct drm_device *dev = intel_dp_to_dev(intel_dp);
300 struct drm_i915_private *dev_priv = dev->dev_private;
302 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
305 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
307 struct drm_device *dev = intel_dp_to_dev(intel_dp);
308 struct drm_i915_private *dev_priv = dev->dev_private;
310 return (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
314 intel_dp_check_edp(struct intel_dp *intel_dp)
316 struct drm_device *dev = intel_dp_to_dev(intel_dp);
317 struct drm_i915_private *dev_priv = dev->dev_private;
319 if (!is_edp(intel_dp))
322 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
323 WARN(1, "eDP powered off while attempting aux channel communication.\n");
324 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
325 I915_READ(_pp_stat_reg(intel_dp)),
326 I915_READ(_pp_ctrl_reg(intel_dp)));
331 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
333 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
334 struct drm_device *dev = intel_dig_port->base.base.dev;
335 struct drm_i915_private *dev_priv = dev->dev_private;
336 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
340 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
342 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
343 msecs_to_jiffies_timeout(10));
345 done = wait_for_atomic(C, 10) == 0;
347 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
354 static uint32_t get_aux_clock_divider(struct intel_dp *intel_dp,
357 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
358 struct drm_device *dev = intel_dig_port->base.base.dev;
359 struct drm_i915_private *dev_priv = dev->dev_private;
361 /* The clock divider is based off the hrawclk,
362 * and would like to run at 2MHz. So, take the
363 * hrawclk value and divide by 2 and use that
365 * Note that PCH attached eDP panels should use a 125MHz input
368 if (IS_VALLEYVIEW(dev)) {
369 return index ? 0 : 100;
370 } else if (intel_dig_port->port == PORT_A) {
374 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
375 else if (IS_GEN6(dev) || IS_GEN7(dev))
376 return 200; /* SNB & IVB eDP input clock at 400Mhz */
378 return 225; /* eDP input clock at 450Mhz */
379 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
380 /* Workaround for non-ULT HSW */
386 } else if (HAS_PCH_SPLIT(dev)) {
387 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
389 return index ? 0 :intel_hrawclk(dev) / 2;
394 intel_dp_aux_ch(struct intel_dp *intel_dp,
395 uint8_t *send, int send_bytes,
396 uint8_t *recv, int recv_size)
398 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
399 struct drm_device *dev = intel_dig_port->base.base.dev;
400 struct drm_i915_private *dev_priv = dev->dev_private;
401 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
402 uint32_t ch_data = ch_ctl + 4;
403 uint32_t aux_clock_divider;
404 int i, ret, recv_bytes;
406 int try, precharge, clock = 0;
407 bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);
409 /* dp aux is extremely sensitive to irq latency, hence request the
410 * lowest possible wakeup latency and so prevent the cpu from going into
413 pm_qos_update_request(&dev_priv->pm_qos, 0);
415 intel_dp_check_edp(intel_dp);
422 intel_aux_display_runtime_get(dev_priv);
424 /* Try to wait for any previous AUX channel activity */
425 for (try = 0; try < 3; try++) {
426 status = I915_READ_NOTRACE(ch_ctl);
427 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
433 WARN(1, "dp_aux_ch not started status 0x%08x\n",
439 /* Only 5 data registers! */
440 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
445 while ((aux_clock_divider = get_aux_clock_divider(intel_dp, clock++))) {
446 /* Must try at least 3 times according to DP spec */
447 for (try = 0; try < 5; try++) {
448 /* Load the send data into the aux channel data registers */
449 for (i = 0; i < send_bytes; i += 4)
450 I915_WRITE(ch_data + i,
451 pack_aux(send + i, send_bytes - i));
453 /* Send the command and wait for it to complete */
455 DP_AUX_CH_CTL_SEND_BUSY |
456 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
457 DP_AUX_CH_CTL_TIME_OUT_400us |
458 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
459 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
460 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
462 DP_AUX_CH_CTL_TIME_OUT_ERROR |
463 DP_AUX_CH_CTL_RECEIVE_ERROR);
465 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
467 /* Clear done status and any errors */
471 DP_AUX_CH_CTL_TIME_OUT_ERROR |
472 DP_AUX_CH_CTL_RECEIVE_ERROR);
474 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
475 DP_AUX_CH_CTL_RECEIVE_ERROR))
477 if (status & DP_AUX_CH_CTL_DONE)
480 if (status & DP_AUX_CH_CTL_DONE)
484 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
485 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
490 /* Check for timeout or receive error.
491 * Timeouts occur when the sink is not connected
493 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
494 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
499 /* Timeouts occur when the device isn't connected, so they're
500 * "normal" -- don't fill the kernel log with these */
501 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
502 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
507 /* Unload any bytes sent back from the other side */
508 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
509 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
510 if (recv_bytes > recv_size)
511 recv_bytes = recv_size;
513 for (i = 0; i < recv_bytes; i += 4)
514 unpack_aux(I915_READ(ch_data + i),
515 recv + i, recv_bytes - i);
519 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
520 intel_aux_display_runtime_put(dev_priv);
525 /* Write data to the aux channel in native mode */
527 intel_dp_aux_native_write(struct intel_dp *intel_dp,
528 uint16_t address, uint8_t *send, int send_bytes)
535 if (WARN_ON(send_bytes > 16))
538 intel_dp_check_edp(intel_dp);
539 msg[0] = AUX_NATIVE_WRITE << 4;
540 msg[1] = address >> 8;
541 msg[2] = address & 0xff;
542 msg[3] = send_bytes - 1;
543 memcpy(&msg[4], send, send_bytes);
544 msg_bytes = send_bytes + 4;
546 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
549 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
551 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
559 /* Write a single byte to the aux channel in native mode */
561 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
562 uint16_t address, uint8_t byte)
564 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
567 /* read bytes from a native aux channel */
569 intel_dp_aux_native_read(struct intel_dp *intel_dp,
570 uint16_t address, uint8_t *recv, int recv_bytes)
579 if (WARN_ON(recv_bytes > 19))
582 intel_dp_check_edp(intel_dp);
583 msg[0] = AUX_NATIVE_READ << 4;
584 msg[1] = address >> 8;
585 msg[2] = address & 0xff;
586 msg[3] = recv_bytes - 1;
589 reply_bytes = recv_bytes + 1;
592 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
599 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
600 memcpy(recv, reply + 1, ret - 1);
603 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
611 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
612 uint8_t write_byte, uint8_t *read_byte)
614 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
615 struct intel_dp *intel_dp = container_of(adapter,
618 uint16_t address = algo_data->address;
626 intel_dp_check_edp(intel_dp);
627 /* Set up the command byte */
628 if (mode & MODE_I2C_READ)
629 msg[0] = AUX_I2C_READ << 4;
631 msg[0] = AUX_I2C_WRITE << 4;
633 if (!(mode & MODE_I2C_STOP))
634 msg[0] |= AUX_I2C_MOT << 4;
636 msg[1] = address >> 8;
658 * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device is
659 * required to retry at least seven times upon receiving AUX_DEFER
660 * before giving up the AUX transaction.
662 for (retry = 0; retry < 7; retry++) {
663 ret = intel_dp_aux_ch(intel_dp,
667 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
671 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
672 case AUX_NATIVE_REPLY_ACK:
673 /* I2C-over-AUX Reply field is only valid
674 * when paired with AUX ACK.
677 case AUX_NATIVE_REPLY_NACK:
678 DRM_DEBUG_KMS("aux_ch native nack\n");
680 case AUX_NATIVE_REPLY_DEFER:
682 * For now, just give more slack to branch devices. We
683 * could check the DPCD for I2C bit rate capabilities,
684 * and if available, adjust the interval. We could also
685 * be more careful with DP-to-Legacy adapters where a
686 * long legacy cable may force very low I2C bit rates.
688 if (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
689 DP_DWN_STRM_PORT_PRESENT)
690 usleep_range(500, 600);
692 usleep_range(300, 400);
695 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
700 switch (reply[0] & AUX_I2C_REPLY_MASK) {
701 case AUX_I2C_REPLY_ACK:
702 if (mode == MODE_I2C_READ) {
703 *read_byte = reply[1];
705 return reply_bytes - 1;
706 case AUX_I2C_REPLY_NACK:
707 DRM_DEBUG_KMS("aux_i2c nack\n");
709 case AUX_I2C_REPLY_DEFER:
710 DRM_DEBUG_KMS("aux_i2c defer\n");
714 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
719 DRM_ERROR("too many retries, giving up\n");
724 intel_dp_i2c_init(struct intel_dp *intel_dp,
725 struct intel_connector *intel_connector, const char *name)
729 DRM_DEBUG_KMS("i2c_init %s\n", name);
730 intel_dp->algo.running = false;
731 intel_dp->algo.address = 0;
732 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
734 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
735 intel_dp->adapter.owner = THIS_MODULE;
736 intel_dp->adapter.class = I2C_CLASS_DDC;
737 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
738 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
739 intel_dp->adapter.algo_data = &intel_dp->algo;
740 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
742 ironlake_edp_panel_vdd_on(intel_dp);
743 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
744 ironlake_edp_panel_vdd_off(intel_dp, false);
749 intel_dp_set_clock(struct intel_encoder *encoder,
750 struct intel_crtc_config *pipe_config, int link_bw)
752 struct drm_device *dev = encoder->base.dev;
753 const struct dp_link_dpll *divisor = NULL;
758 count = ARRAY_SIZE(gen4_dpll);
759 } else if (IS_HASWELL(dev)) {
760 /* Haswell has special-purpose DP DDI clocks. */
761 } else if (HAS_PCH_SPLIT(dev)) {
763 count = ARRAY_SIZE(pch_dpll);
764 } else if (IS_VALLEYVIEW(dev)) {
766 count = ARRAY_SIZE(vlv_dpll);
769 if (divisor && count) {
770 for (i = 0; i < count; i++) {
771 if (link_bw == divisor[i].link_bw) {
772 pipe_config->dpll = divisor[i].dpll;
773 pipe_config->clock_set = true;
781 intel_dp_compute_config(struct intel_encoder *encoder,
782 struct intel_crtc_config *pipe_config)
784 struct drm_device *dev = encoder->base.dev;
785 struct drm_i915_private *dev_priv = dev->dev_private;
786 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
787 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
788 enum port port = dp_to_dig_port(intel_dp)->port;
789 struct intel_crtc *intel_crtc = encoder->new_crtc;
790 struct intel_connector *intel_connector = intel_dp->attached_connector;
791 int lane_count, clock;
792 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
793 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
795 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
796 int link_avail, link_clock;
798 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
799 pipe_config->has_pch_encoder = true;
801 pipe_config->has_dp_encoder = true;
803 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
804 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
806 if (!HAS_PCH_SPLIT(dev))
807 intel_gmch_panel_fitting(intel_crtc, pipe_config,
808 intel_connector->panel.fitting_mode);
810 intel_pch_panel_fitting(intel_crtc, pipe_config,
811 intel_connector->panel.fitting_mode);
814 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
817 DRM_DEBUG_KMS("DP link computation with max lane count %i "
818 "max bw %02x pixel clock %iKHz\n",
819 max_lane_count, bws[max_clock],
820 adjusted_mode->crtc_clock);
822 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
824 bpp = pipe_config->pipe_bpp;
825 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp) {
826 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
827 dev_priv->vbt.edp_bpp);
828 bpp = min_t(int, bpp, dev_priv->vbt.edp_bpp);
831 for (; bpp >= 6*3; bpp -= 2*3) {
832 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
835 for (clock = 0; clock <= max_clock; clock++) {
836 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
837 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
838 link_avail = intel_dp_max_data_rate(link_clock,
841 if (mode_rate <= link_avail) {
851 if (intel_dp->color_range_auto) {
854 * CEA-861-E - 5.1 Default Encoding Parameters
855 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
857 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
858 intel_dp->color_range = DP_COLOR_RANGE_16_235;
860 intel_dp->color_range = 0;
863 if (intel_dp->color_range)
864 pipe_config->limited_color_range = true;
866 intel_dp->link_bw = bws[clock];
867 intel_dp->lane_count = lane_count;
868 pipe_config->pipe_bpp = bpp;
869 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
871 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
872 intel_dp->link_bw, intel_dp->lane_count,
873 pipe_config->port_clock, bpp);
874 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
875 mode_rate, link_avail);
877 intel_link_compute_m_n(bpp, lane_count,
878 adjusted_mode->crtc_clock,
879 pipe_config->port_clock,
880 &pipe_config->dp_m_n);
882 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
887 static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
889 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
890 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
891 struct drm_device *dev = crtc->base.dev;
892 struct drm_i915_private *dev_priv = dev->dev_private;
895 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
896 dpa_ctl = I915_READ(DP_A);
897 dpa_ctl &= ~DP_PLL_FREQ_MASK;
899 if (crtc->config.port_clock == 162000) {
900 /* For a long time we've carried around a ILK-DevA w/a for the
901 * 160MHz clock. If we're really unlucky, it's still required.
903 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
904 dpa_ctl |= DP_PLL_FREQ_160MHZ;
905 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
907 dpa_ctl |= DP_PLL_FREQ_270MHZ;
908 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
911 I915_WRITE(DP_A, dpa_ctl);
917 static void intel_dp_mode_set(struct intel_encoder *encoder)
919 struct drm_device *dev = encoder->base.dev;
920 struct drm_i915_private *dev_priv = dev->dev_private;
921 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
922 enum port port = dp_to_dig_port(intel_dp)->port;
923 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
924 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
927 * There are four kinds of DP registers:
934 * IBX PCH and CPU are the same for almost everything,
935 * except that the CPU DP PLL is configured in this
938 * CPT PCH is quite different, having many bits moved
939 * to the TRANS_DP_CTL register instead. That
940 * configuration happens (oddly) in ironlake_pch_enable
943 /* Preserve the BIOS-computed detected bit. This is
944 * supposed to be read-only.
946 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
948 /* Handle DP bits in common between all three register formats */
949 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
950 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
952 if (intel_dp->has_audio) {
953 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
954 pipe_name(crtc->pipe));
955 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
956 intel_write_eld(&encoder->base, adjusted_mode);
959 /* Split out the IBX/CPU vs CPT settings */
961 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
962 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
963 intel_dp->DP |= DP_SYNC_HS_HIGH;
964 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
965 intel_dp->DP |= DP_SYNC_VS_HIGH;
966 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
968 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
969 intel_dp->DP |= DP_ENHANCED_FRAMING;
971 intel_dp->DP |= crtc->pipe << 29;
972 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
973 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
974 intel_dp->DP |= intel_dp->color_range;
976 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
977 intel_dp->DP |= DP_SYNC_HS_HIGH;
978 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
979 intel_dp->DP |= DP_SYNC_VS_HIGH;
980 intel_dp->DP |= DP_LINK_TRAIN_OFF;
982 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
983 intel_dp->DP |= DP_ENHANCED_FRAMING;
986 intel_dp->DP |= DP_PIPEB_SELECT;
988 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
991 if (port == PORT_A && !IS_VALLEYVIEW(dev))
992 ironlake_set_pll_cpu_edp(intel_dp);
995 #define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
996 #define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
998 #define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
999 #define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1001 #define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1002 #define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1004 static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
1008 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1009 struct drm_i915_private *dev_priv = dev->dev_private;
1010 u32 pp_stat_reg, pp_ctrl_reg;
1012 pp_stat_reg = _pp_stat_reg(intel_dp);
1013 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1015 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1017 I915_READ(pp_stat_reg),
1018 I915_READ(pp_ctrl_reg));
1020 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
1021 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1022 I915_READ(pp_stat_reg),
1023 I915_READ(pp_ctrl_reg));
1027 static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
1029 DRM_DEBUG_KMS("Wait for panel power on\n");
1030 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1033 static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
1035 DRM_DEBUG_KMS("Wait for panel power off time\n");
1036 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1039 static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
1041 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1042 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1046 /* Read the current pp_control value, unlocking the register if it
1050 static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1052 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1053 struct drm_i915_private *dev_priv = dev->dev_private;
1056 control = I915_READ(_pp_ctrl_reg(intel_dp));
1057 control &= ~PANEL_UNLOCK_MASK;
1058 control |= PANEL_UNLOCK_REGS;
1062 void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
1064 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1065 struct drm_i915_private *dev_priv = dev->dev_private;
1067 u32 pp_stat_reg, pp_ctrl_reg;
1069 if (!is_edp(intel_dp))
1071 DRM_DEBUG_KMS("Turn eDP VDD on\n");
1073 WARN(intel_dp->want_panel_vdd,
1074 "eDP VDD already requested on\n");
1076 intel_dp->want_panel_vdd = true;
1078 if (ironlake_edp_have_panel_vdd(intel_dp)) {
1079 DRM_DEBUG_KMS("eDP VDD already on\n");
1083 if (!ironlake_edp_have_panel_power(intel_dp))
1084 ironlake_wait_panel_power_cycle(intel_dp);
1086 pp = ironlake_get_pp_control(intel_dp);
1087 pp |= EDP_FORCE_VDD;
1089 pp_stat_reg = _pp_stat_reg(intel_dp);
1090 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1092 I915_WRITE(pp_ctrl_reg, pp);
1093 POSTING_READ(pp_ctrl_reg);
1094 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1095 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1097 * If the panel wasn't on, delay before accessing aux channel
1099 if (!ironlake_edp_have_panel_power(intel_dp)) {
1100 DRM_DEBUG_KMS("eDP was not running\n");
1101 msleep(intel_dp->panel_power_up_delay);
1105 static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
1107 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1108 struct drm_i915_private *dev_priv = dev->dev_private;
1110 u32 pp_stat_reg, pp_ctrl_reg;
1112 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1114 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
1115 pp = ironlake_get_pp_control(intel_dp);
1116 pp &= ~EDP_FORCE_VDD;
1118 pp_stat_reg = _pp_ctrl_reg(intel_dp);
1119 pp_ctrl_reg = _pp_stat_reg(intel_dp);
1121 I915_WRITE(pp_ctrl_reg, pp);
1122 POSTING_READ(pp_ctrl_reg);
1124 /* Make sure sequencer is idle before allowing subsequent activity */
1125 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1126 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1127 msleep(intel_dp->panel_power_down_delay);
1131 static void ironlake_panel_vdd_work(struct work_struct *__work)
1133 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1134 struct intel_dp, panel_vdd_work);
1135 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1137 mutex_lock(&dev->mode_config.mutex);
1138 ironlake_panel_vdd_off_sync(intel_dp);
1139 mutex_unlock(&dev->mode_config.mutex);
1142 void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1144 if (!is_edp(intel_dp))
1147 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1148 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1150 intel_dp->want_panel_vdd = false;
1153 ironlake_panel_vdd_off_sync(intel_dp);
1156 * Queue the timer to fire a long
1157 * time from now (relative to the power down delay)
1158 * to keep the panel power up across a sequence of operations
1160 schedule_delayed_work(&intel_dp->panel_vdd_work,
1161 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1165 void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1167 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1168 struct drm_i915_private *dev_priv = dev->dev_private;
1172 if (!is_edp(intel_dp))
1175 DRM_DEBUG_KMS("Turn eDP power on\n");
1177 if (ironlake_edp_have_panel_power(intel_dp)) {
1178 DRM_DEBUG_KMS("eDP power already on\n");
1182 ironlake_wait_panel_power_cycle(intel_dp);
1184 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1185 pp = ironlake_get_pp_control(intel_dp);
1187 /* ILK workaround: disable reset around power sequence */
1188 pp &= ~PANEL_POWER_RESET;
1189 I915_WRITE(pp_ctrl_reg, pp);
1190 POSTING_READ(pp_ctrl_reg);
1193 pp |= POWER_TARGET_ON;
1195 pp |= PANEL_POWER_RESET;
1197 I915_WRITE(pp_ctrl_reg, pp);
1198 POSTING_READ(pp_ctrl_reg);
1200 ironlake_wait_panel_on(intel_dp);
1203 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1204 I915_WRITE(pp_ctrl_reg, pp);
1205 POSTING_READ(pp_ctrl_reg);
1209 void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1211 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1212 struct drm_i915_private *dev_priv = dev->dev_private;
1216 if (!is_edp(intel_dp))
1219 DRM_DEBUG_KMS("Turn eDP power off\n");
1221 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1223 pp = ironlake_get_pp_control(intel_dp);
1224 /* We need to switch off panel power _and_ force vdd, for otherwise some
1225 * panels get very unhappy and cease to work. */
1226 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1228 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1230 I915_WRITE(pp_ctrl_reg, pp);
1231 POSTING_READ(pp_ctrl_reg);
1233 intel_dp->want_panel_vdd = false;
1235 ironlake_wait_panel_off(intel_dp);
1238 void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1240 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1241 struct drm_device *dev = intel_dig_port->base.base.dev;
1242 struct drm_i915_private *dev_priv = dev->dev_private;
1243 int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
1247 if (!is_edp(intel_dp))
1250 DRM_DEBUG_KMS("\n");
1252 * If we enable the backlight right away following a panel power
1253 * on, we may see slight flicker as the panel syncs with the eDP
1254 * link. So delay a bit to make sure the image is solid before
1255 * allowing it to appear.
1257 msleep(intel_dp->backlight_on_delay);
1258 pp = ironlake_get_pp_control(intel_dp);
1259 pp |= EDP_BLC_ENABLE;
1261 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1263 I915_WRITE(pp_ctrl_reg, pp);
1264 POSTING_READ(pp_ctrl_reg);
1266 intel_panel_enable_backlight(dev, pipe);
1269 void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1271 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1272 struct drm_i915_private *dev_priv = dev->dev_private;
1276 if (!is_edp(intel_dp))
1279 intel_panel_disable_backlight(dev);
1281 DRM_DEBUG_KMS("\n");
1282 pp = ironlake_get_pp_control(intel_dp);
1283 pp &= ~EDP_BLC_ENABLE;
1285 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1287 I915_WRITE(pp_ctrl_reg, pp);
1288 POSTING_READ(pp_ctrl_reg);
1289 msleep(intel_dp->backlight_off_delay);
1292 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1294 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1295 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1296 struct drm_device *dev = crtc->dev;
1297 struct drm_i915_private *dev_priv = dev->dev_private;
1300 assert_pipe_disabled(dev_priv,
1301 to_intel_crtc(crtc)->pipe);
1303 DRM_DEBUG_KMS("\n");
1304 dpa_ctl = I915_READ(DP_A);
1305 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1306 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1308 /* We don't adjust intel_dp->DP while tearing down the link, to
1309 * facilitate link retraining (e.g. after hotplug). Hence clear all
1310 * enable bits here to ensure that we don't enable too much. */
1311 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1312 intel_dp->DP |= DP_PLL_ENABLE;
1313 I915_WRITE(DP_A, intel_dp->DP);
1318 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1320 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1321 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1322 struct drm_device *dev = crtc->dev;
1323 struct drm_i915_private *dev_priv = dev->dev_private;
1326 assert_pipe_disabled(dev_priv,
1327 to_intel_crtc(crtc)->pipe);
1329 dpa_ctl = I915_READ(DP_A);
1330 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1331 "dp pll off, should be on\n");
1332 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1334 /* We can't rely on the value tracked for the DP register in
1335 * intel_dp->DP because link_down must not change that (otherwise link
1336 * re-training will fail. */
1337 dpa_ctl &= ~DP_PLL_ENABLE;
1338 I915_WRITE(DP_A, dpa_ctl);
1343 /* If the sink supports it, try to set the power state appropriately */
1344 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1348 /* Should have a valid DPCD by this point */
1349 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1352 if (mode != DRM_MODE_DPMS_ON) {
1353 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1356 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1359 * When turning on, we need to retry for 1ms to give the sink
1362 for (i = 0; i < 3; i++) {
1363 ret = intel_dp_aux_native_write_1(intel_dp,
1373 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1376 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1377 enum port port = dp_to_dig_port(intel_dp)->port;
1378 struct drm_device *dev = encoder->base.dev;
1379 struct drm_i915_private *dev_priv = dev->dev_private;
1380 u32 tmp = I915_READ(intel_dp->output_reg);
1382 if (!(tmp & DP_PORT_EN))
1385 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1386 *pipe = PORT_TO_PIPE_CPT(tmp);
1387 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1388 *pipe = PORT_TO_PIPE(tmp);
1394 switch (intel_dp->output_reg) {
1396 trans_sel = TRANS_DP_PORT_SEL_B;
1399 trans_sel = TRANS_DP_PORT_SEL_C;
1402 trans_sel = TRANS_DP_PORT_SEL_D;
1409 trans_dp = I915_READ(TRANS_DP_CTL(i));
1410 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1416 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1417 intel_dp->output_reg);
1423 static void intel_dp_get_config(struct intel_encoder *encoder,
1424 struct intel_crtc_config *pipe_config)
1426 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1428 struct drm_device *dev = encoder->base.dev;
1429 struct drm_i915_private *dev_priv = dev->dev_private;
1430 enum port port = dp_to_dig_port(intel_dp)->port;
1431 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1434 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1435 tmp = I915_READ(intel_dp->output_reg);
1436 if (tmp & DP_SYNC_HS_HIGH)
1437 flags |= DRM_MODE_FLAG_PHSYNC;
1439 flags |= DRM_MODE_FLAG_NHSYNC;
1441 if (tmp & DP_SYNC_VS_HIGH)
1442 flags |= DRM_MODE_FLAG_PVSYNC;
1444 flags |= DRM_MODE_FLAG_NVSYNC;
1446 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1447 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1448 flags |= DRM_MODE_FLAG_PHSYNC;
1450 flags |= DRM_MODE_FLAG_NHSYNC;
1452 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1453 flags |= DRM_MODE_FLAG_PVSYNC;
1455 flags |= DRM_MODE_FLAG_NVSYNC;
1458 pipe_config->adjusted_mode.flags |= flags;
1460 pipe_config->has_dp_encoder = true;
1462 intel_dp_get_m_n(crtc, pipe_config);
1464 if (port == PORT_A) {
1465 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1466 pipe_config->port_clock = 162000;
1468 pipe_config->port_clock = 270000;
1471 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1472 &pipe_config->dp_m_n);
1474 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1475 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1477 pipe_config->adjusted_mode.crtc_clock = dotclock;
1480 static bool is_edp_psr(struct drm_device *dev)
1482 struct drm_i915_private *dev_priv = dev->dev_private;
1484 return dev_priv->psr.sink_support;
1487 static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1489 struct drm_i915_private *dev_priv = dev->dev_private;
1494 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
1497 static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1498 struct edp_vsc_psr *vsc_psr)
1500 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1501 struct drm_device *dev = dig_port->base.base.dev;
1502 struct drm_i915_private *dev_priv = dev->dev_private;
1503 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1504 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1505 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1506 uint32_t *data = (uint32_t *) vsc_psr;
1509 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1510 the video DIP being updated before program video DIP data buffer
1511 registers for DIP being updated. */
1512 I915_WRITE(ctl_reg, 0);
1513 POSTING_READ(ctl_reg);
1515 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1516 if (i < sizeof(struct edp_vsc_psr))
1517 I915_WRITE(data_reg + i, *data++);
1519 I915_WRITE(data_reg + i, 0);
1522 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1523 POSTING_READ(ctl_reg);
1526 static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1528 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1529 struct drm_i915_private *dev_priv = dev->dev_private;
1530 struct edp_vsc_psr psr_vsc;
1532 if (intel_dp->psr_setup_done)
1535 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1536 memset(&psr_vsc, 0, sizeof(psr_vsc));
1537 psr_vsc.sdp_header.HB0 = 0;
1538 psr_vsc.sdp_header.HB1 = 0x7;
1539 psr_vsc.sdp_header.HB2 = 0x2;
1540 psr_vsc.sdp_header.HB3 = 0x8;
1541 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1543 /* Avoid continuous PSR exit by masking memup and hpd */
1544 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
1545 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
1547 intel_dp->psr_setup_done = true;
1550 static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1552 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1553 struct drm_i915_private *dev_priv = dev->dev_private;
1554 uint32_t aux_clock_divider = get_aux_clock_divider(intel_dp, 0);
1555 int precharge = 0x3;
1556 int msg_size = 5; /* Header(4) + Message(1) */
1558 /* Enable PSR in sink */
1559 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT)
1560 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1562 ~DP_PSR_MAIN_LINK_ACTIVE);
1564 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1566 DP_PSR_MAIN_LINK_ACTIVE);
1568 /* Setup AUX registers */
1569 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1570 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1571 I915_WRITE(EDP_PSR_AUX_CTL(dev),
1572 DP_AUX_CH_CTL_TIME_OUT_400us |
1573 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1574 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1575 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1578 static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1580 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1581 struct drm_i915_private *dev_priv = dev->dev_private;
1582 uint32_t max_sleep_time = 0x1f;
1583 uint32_t idle_frames = 1;
1586 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
1587 val |= EDP_PSR_LINK_STANDBY;
1588 val |= EDP_PSR_TP2_TP3_TIME_0us;
1589 val |= EDP_PSR_TP1_TIME_0us;
1590 val |= EDP_PSR_SKIP_AUX_EXIT;
1592 val |= EDP_PSR_LINK_DISABLE;
1594 I915_WRITE(EDP_PSR_CTL(dev), val |
1595 EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES |
1596 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1597 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1601 static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1603 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1604 struct drm_device *dev = dig_port->base.base.dev;
1605 struct drm_i915_private *dev_priv = dev->dev_private;
1606 struct drm_crtc *crtc = dig_port->base.base.crtc;
1607 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1608 struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->fb)->obj;
1609 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
1611 dev_priv->psr.source_ok = false;
1613 if (!HAS_PSR(dev)) {
1614 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1618 if ((intel_encoder->type != INTEL_OUTPUT_EDP) ||
1619 (dig_port->port != PORT_A)) {
1620 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
1624 if (!i915_enable_psr) {
1625 DRM_DEBUG_KMS("PSR disable by flag\n");
1629 crtc = dig_port->base.base.crtc;
1631 DRM_DEBUG_KMS("crtc not active for PSR\n");
1635 intel_crtc = to_intel_crtc(crtc);
1636 if (!intel_crtc_active(crtc)) {
1637 DRM_DEBUG_KMS("crtc not active for PSR\n");
1641 obj = to_intel_framebuffer(crtc->fb)->obj;
1642 if (obj->tiling_mode != I915_TILING_X ||
1643 obj->fence_reg == I915_FENCE_REG_NONE) {
1644 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
1648 if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
1649 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
1653 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1655 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
1659 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
1660 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
1664 dev_priv->psr.source_ok = true;
1668 static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
1670 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1672 if (!intel_edp_psr_match_conditions(intel_dp) ||
1673 intel_edp_is_psr_enabled(dev))
1676 /* Setup PSR once */
1677 intel_edp_psr_setup(intel_dp);
1679 /* Enable PSR on the panel */
1680 intel_edp_psr_enable_sink(intel_dp);
1682 /* Enable PSR on the host */
1683 intel_edp_psr_enable_source(intel_dp);
1686 void intel_edp_psr_enable(struct intel_dp *intel_dp)
1688 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1690 if (intel_edp_psr_match_conditions(intel_dp) &&
1691 !intel_edp_is_psr_enabled(dev))
1692 intel_edp_psr_do_enable(intel_dp);
1695 void intel_edp_psr_disable(struct intel_dp *intel_dp)
1697 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1698 struct drm_i915_private *dev_priv = dev->dev_private;
1700 if (!intel_edp_is_psr_enabled(dev))
1703 I915_WRITE(EDP_PSR_CTL(dev),
1704 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
1706 /* Wait till PSR is idle */
1707 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
1708 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1709 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1712 void intel_edp_psr_update(struct drm_device *dev)
1714 struct intel_encoder *encoder;
1715 struct intel_dp *intel_dp = NULL;
1717 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
1718 if (encoder->type == INTEL_OUTPUT_EDP) {
1719 intel_dp = enc_to_intel_dp(&encoder->base);
1721 if (!is_edp_psr(dev))
1724 if (!intel_edp_psr_match_conditions(intel_dp))
1725 intel_edp_psr_disable(intel_dp);
1727 if (!intel_edp_is_psr_enabled(dev))
1728 intel_edp_psr_do_enable(intel_dp);
1732 static void intel_disable_dp(struct intel_encoder *encoder)
1734 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1735 enum port port = dp_to_dig_port(intel_dp)->port;
1736 struct drm_device *dev = encoder->base.dev;
1738 /* Make sure the panel is off before trying to change the mode. But also
1739 * ensure that we have vdd while we switch off the panel. */
1740 ironlake_edp_panel_vdd_on(intel_dp);
1741 ironlake_edp_backlight_off(intel_dp);
1742 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1743 ironlake_edp_panel_off(intel_dp);
1745 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1746 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
1747 intel_dp_link_down(intel_dp);
1750 static void intel_post_disable_dp(struct intel_encoder *encoder)
1752 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1753 enum port port = dp_to_dig_port(intel_dp)->port;
1754 struct drm_device *dev = encoder->base.dev;
1756 if (port == PORT_A || IS_VALLEYVIEW(dev)) {
1757 intel_dp_link_down(intel_dp);
1758 if (!IS_VALLEYVIEW(dev))
1759 ironlake_edp_pll_off(intel_dp);
1763 static void intel_enable_dp(struct intel_encoder *encoder)
1765 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1766 struct drm_device *dev = encoder->base.dev;
1767 struct drm_i915_private *dev_priv = dev->dev_private;
1768 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1770 if (WARN_ON(dp_reg & DP_PORT_EN))
1773 ironlake_edp_panel_vdd_on(intel_dp);
1774 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1775 intel_dp_start_link_train(intel_dp);
1776 ironlake_edp_panel_on(intel_dp);
1777 ironlake_edp_panel_vdd_off(intel_dp, true);
1778 intel_dp_complete_link_train(intel_dp);
1779 intel_dp_stop_link_train(intel_dp);
1782 static void g4x_enable_dp(struct intel_encoder *encoder)
1784 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1786 intel_enable_dp(encoder);
1787 ironlake_edp_backlight_on(intel_dp);
1790 static void vlv_enable_dp(struct intel_encoder *encoder)
1792 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1794 ironlake_edp_backlight_on(intel_dp);
1797 static void g4x_pre_enable_dp(struct intel_encoder *encoder)
1799 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1800 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1802 if (dport->port == PORT_A)
1803 ironlake_edp_pll_on(intel_dp);
1806 static void vlv_pre_enable_dp(struct intel_encoder *encoder)
1808 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1809 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1810 struct drm_device *dev = encoder->base.dev;
1811 struct drm_i915_private *dev_priv = dev->dev_private;
1812 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1813 int port = vlv_dport_to_channel(dport);
1814 int pipe = intel_crtc->pipe;
1815 struct edp_power_seq power_seq;
1818 mutex_lock(&dev_priv->dpio_lock);
1820 val = vlv_dpio_read(dev_priv, pipe, DPIO_DATA_LANE_A(port));
1827 vlv_dpio_write(dev_priv, pipe, DPIO_DATA_CHANNEL(port), val);
1828 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLOCKBUF0(port), 0x00760018);
1829 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLOCKBUF8(port), 0x00400888);
1831 mutex_unlock(&dev_priv->dpio_lock);
1833 /* init power sequencer on this pipe and port */
1834 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
1835 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
1838 intel_enable_dp(encoder);
1840 vlv_wait_port_ready(dev_priv, port);
1843 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
1845 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1846 struct drm_device *dev = encoder->base.dev;
1847 struct drm_i915_private *dev_priv = dev->dev_private;
1848 struct intel_crtc *intel_crtc =
1849 to_intel_crtc(encoder->base.crtc);
1850 int port = vlv_dport_to_channel(dport);
1851 int pipe = intel_crtc->pipe;
1853 /* Program Tx lane resets to default */
1854 mutex_lock(&dev_priv->dpio_lock);
1855 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_TX(port),
1856 DPIO_PCS_TX_LANE2_RESET |
1857 DPIO_PCS_TX_LANE1_RESET);
1858 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLK(port),
1859 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1860 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1861 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1862 DPIO_PCS_CLK_SOFT_RESET);
1864 /* Fix up inter-pair skew failure */
1865 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_STAGGER1(port), 0x00750f00);
1866 vlv_dpio_write(dev_priv, pipe, DPIO_TX_CTL(port), 0x00001500);
1867 vlv_dpio_write(dev_priv, pipe, DPIO_TX_LANE(port), 0x40400000);
1868 mutex_unlock(&dev_priv->dpio_lock);
1872 * Native read with retry for link status and receiver capability reads for
1873 * cases where the sink may still be asleep.
1876 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1877 uint8_t *recv, int recv_bytes)
1882 * Sinks are *supposed* to come up within 1ms from an off state,
1883 * but we're also supposed to retry 3 times per the spec.
1885 for (i = 0; i < 3; i++) {
1886 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1888 if (ret == recv_bytes)
1897 * Fetch AUX CH registers 0x202 - 0x207 which contain
1898 * link status information
1901 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1903 return intel_dp_aux_native_read_retry(intel_dp,
1906 DP_LINK_STATUS_SIZE);
1910 static char *voltage_names[] = {
1911 "0.4V", "0.6V", "0.8V", "1.2V"
1913 static char *pre_emph_names[] = {
1914 "0dB", "3.5dB", "6dB", "9.5dB"
1916 static char *link_train_names[] = {
1917 "pattern 1", "pattern 2", "idle", "off"
1922 * These are source-specific values; current Intel hardware supports
1923 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1927 intel_dp_voltage_max(struct intel_dp *intel_dp)
1929 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1930 enum port port = dp_to_dig_port(intel_dp)->port;
1932 if (IS_VALLEYVIEW(dev))
1933 return DP_TRAIN_VOLTAGE_SWING_1200;
1934 else if (IS_GEN7(dev) && port == PORT_A)
1935 return DP_TRAIN_VOLTAGE_SWING_800;
1936 else if (HAS_PCH_CPT(dev) && port != PORT_A)
1937 return DP_TRAIN_VOLTAGE_SWING_1200;
1939 return DP_TRAIN_VOLTAGE_SWING_800;
1943 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1945 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1946 enum port port = dp_to_dig_port(intel_dp)->port;
1949 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1950 case DP_TRAIN_VOLTAGE_SWING_400:
1951 return DP_TRAIN_PRE_EMPHASIS_9_5;
1952 case DP_TRAIN_VOLTAGE_SWING_600:
1953 return DP_TRAIN_PRE_EMPHASIS_6;
1954 case DP_TRAIN_VOLTAGE_SWING_800:
1955 return DP_TRAIN_PRE_EMPHASIS_3_5;
1956 case DP_TRAIN_VOLTAGE_SWING_1200:
1958 return DP_TRAIN_PRE_EMPHASIS_0;
1960 } else if (IS_VALLEYVIEW(dev)) {
1961 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1962 case DP_TRAIN_VOLTAGE_SWING_400:
1963 return DP_TRAIN_PRE_EMPHASIS_9_5;
1964 case DP_TRAIN_VOLTAGE_SWING_600:
1965 return DP_TRAIN_PRE_EMPHASIS_6;
1966 case DP_TRAIN_VOLTAGE_SWING_800:
1967 return DP_TRAIN_PRE_EMPHASIS_3_5;
1968 case DP_TRAIN_VOLTAGE_SWING_1200:
1970 return DP_TRAIN_PRE_EMPHASIS_0;
1972 } else if (IS_GEN7(dev) && port == PORT_A) {
1973 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1974 case DP_TRAIN_VOLTAGE_SWING_400:
1975 return DP_TRAIN_PRE_EMPHASIS_6;
1976 case DP_TRAIN_VOLTAGE_SWING_600:
1977 case DP_TRAIN_VOLTAGE_SWING_800:
1978 return DP_TRAIN_PRE_EMPHASIS_3_5;
1980 return DP_TRAIN_PRE_EMPHASIS_0;
1983 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1984 case DP_TRAIN_VOLTAGE_SWING_400:
1985 return DP_TRAIN_PRE_EMPHASIS_6;
1986 case DP_TRAIN_VOLTAGE_SWING_600:
1987 return DP_TRAIN_PRE_EMPHASIS_6;
1988 case DP_TRAIN_VOLTAGE_SWING_800:
1989 return DP_TRAIN_PRE_EMPHASIS_3_5;
1990 case DP_TRAIN_VOLTAGE_SWING_1200:
1992 return DP_TRAIN_PRE_EMPHASIS_0;
1997 static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
1999 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2000 struct drm_i915_private *dev_priv = dev->dev_private;
2001 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2002 struct intel_crtc *intel_crtc =
2003 to_intel_crtc(dport->base.base.crtc);
2004 unsigned long demph_reg_value, preemph_reg_value,
2005 uniqtranscale_reg_value;
2006 uint8_t train_set = intel_dp->train_set[0];
2007 int port = vlv_dport_to_channel(dport);
2008 int pipe = intel_crtc->pipe;
2010 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2011 case DP_TRAIN_PRE_EMPHASIS_0:
2012 preemph_reg_value = 0x0004000;
2013 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2014 case DP_TRAIN_VOLTAGE_SWING_400:
2015 demph_reg_value = 0x2B405555;
2016 uniqtranscale_reg_value = 0x552AB83A;
2018 case DP_TRAIN_VOLTAGE_SWING_600:
2019 demph_reg_value = 0x2B404040;
2020 uniqtranscale_reg_value = 0x5548B83A;
2022 case DP_TRAIN_VOLTAGE_SWING_800:
2023 demph_reg_value = 0x2B245555;
2024 uniqtranscale_reg_value = 0x5560B83A;
2026 case DP_TRAIN_VOLTAGE_SWING_1200:
2027 demph_reg_value = 0x2B405555;
2028 uniqtranscale_reg_value = 0x5598DA3A;
2034 case DP_TRAIN_PRE_EMPHASIS_3_5:
2035 preemph_reg_value = 0x0002000;
2036 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2037 case DP_TRAIN_VOLTAGE_SWING_400:
2038 demph_reg_value = 0x2B404040;
2039 uniqtranscale_reg_value = 0x5552B83A;
2041 case DP_TRAIN_VOLTAGE_SWING_600:
2042 demph_reg_value = 0x2B404848;
2043 uniqtranscale_reg_value = 0x5580B83A;
2045 case DP_TRAIN_VOLTAGE_SWING_800:
2046 demph_reg_value = 0x2B404040;
2047 uniqtranscale_reg_value = 0x55ADDA3A;
2053 case DP_TRAIN_PRE_EMPHASIS_6:
2054 preemph_reg_value = 0x0000000;
2055 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2056 case DP_TRAIN_VOLTAGE_SWING_400:
2057 demph_reg_value = 0x2B305555;
2058 uniqtranscale_reg_value = 0x5570B83A;
2060 case DP_TRAIN_VOLTAGE_SWING_600:
2061 demph_reg_value = 0x2B2B4040;
2062 uniqtranscale_reg_value = 0x55ADDA3A;
2068 case DP_TRAIN_PRE_EMPHASIS_9_5:
2069 preemph_reg_value = 0x0006000;
2070 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2071 case DP_TRAIN_VOLTAGE_SWING_400:
2072 demph_reg_value = 0x1B405555;
2073 uniqtranscale_reg_value = 0x55ADDA3A;
2083 mutex_lock(&dev_priv->dpio_lock);
2084 vlv_dpio_write(dev_priv, pipe, DPIO_TX_OCALINIT(port), 0x00000000);
2085 vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL4(port), demph_reg_value);
2086 vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL2(port),
2087 uniqtranscale_reg_value);
2088 vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL3(port), 0x0C782040);
2089 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_STAGGER0(port), 0x00030000);
2090 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CTL_OVER1(port), preemph_reg_value);
2091 vlv_dpio_write(dev_priv, pipe, DPIO_TX_OCALINIT(port), 0x80000000);
2092 mutex_unlock(&dev_priv->dpio_lock);
2098 intel_get_adjust_train(struct intel_dp *intel_dp,
2099 const uint8_t link_status[DP_LINK_STATUS_SIZE])
2104 uint8_t voltage_max;
2105 uint8_t preemph_max;
2107 for (lane = 0; lane < intel_dp->lane_count; lane++) {
2108 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2109 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
2117 voltage_max = intel_dp_voltage_max(intel_dp);
2118 if (v >= voltage_max)
2119 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
2121 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2122 if (p >= preemph_max)
2123 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
2125 for (lane = 0; lane < 4; lane++)
2126 intel_dp->train_set[lane] = v | p;
2130 intel_gen4_signal_levels(uint8_t train_set)
2132 uint32_t signal_levels = 0;
2134 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2135 case DP_TRAIN_VOLTAGE_SWING_400:
2137 signal_levels |= DP_VOLTAGE_0_4;
2139 case DP_TRAIN_VOLTAGE_SWING_600:
2140 signal_levels |= DP_VOLTAGE_0_6;
2142 case DP_TRAIN_VOLTAGE_SWING_800:
2143 signal_levels |= DP_VOLTAGE_0_8;
2145 case DP_TRAIN_VOLTAGE_SWING_1200:
2146 signal_levels |= DP_VOLTAGE_1_2;
2149 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2150 case DP_TRAIN_PRE_EMPHASIS_0:
2152 signal_levels |= DP_PRE_EMPHASIS_0;
2154 case DP_TRAIN_PRE_EMPHASIS_3_5:
2155 signal_levels |= DP_PRE_EMPHASIS_3_5;
2157 case DP_TRAIN_PRE_EMPHASIS_6:
2158 signal_levels |= DP_PRE_EMPHASIS_6;
2160 case DP_TRAIN_PRE_EMPHASIS_9_5:
2161 signal_levels |= DP_PRE_EMPHASIS_9_5;
2164 return signal_levels;
2167 /* Gen6's DP voltage swing and pre-emphasis control */
2169 intel_gen6_edp_signal_levels(uint8_t train_set)
2171 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2172 DP_TRAIN_PRE_EMPHASIS_MASK);
2173 switch (signal_levels) {
2174 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2175 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2176 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2177 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2178 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
2179 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2180 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2181 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
2182 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2183 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2184 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
2185 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2186 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2187 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
2189 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2190 "0x%x\n", signal_levels);
2191 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2195 /* Gen7's DP voltage swing and pre-emphasis control */
2197 intel_gen7_edp_signal_levels(uint8_t train_set)
2199 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2200 DP_TRAIN_PRE_EMPHASIS_MASK);
2201 switch (signal_levels) {
2202 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2203 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2204 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2205 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2206 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2207 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2209 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2210 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2211 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2212 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2214 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2215 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2216 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2217 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2220 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2221 "0x%x\n", signal_levels);
2222 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2226 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2228 intel_hsw_signal_levels(uint8_t train_set)
2230 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2231 DP_TRAIN_PRE_EMPHASIS_MASK);
2232 switch (signal_levels) {
2233 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2234 return DDI_BUF_EMP_400MV_0DB_HSW;
2235 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2236 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2237 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2238 return DDI_BUF_EMP_400MV_6DB_HSW;
2239 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2240 return DDI_BUF_EMP_400MV_9_5DB_HSW;
2242 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2243 return DDI_BUF_EMP_600MV_0DB_HSW;
2244 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2245 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2246 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2247 return DDI_BUF_EMP_600MV_6DB_HSW;
2249 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2250 return DDI_BUF_EMP_800MV_0DB_HSW;
2251 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2252 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2254 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2255 "0x%x\n", signal_levels);
2256 return DDI_BUF_EMP_400MV_0DB_HSW;
2260 /* Properly updates "DP" with the correct signal levels. */
2262 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2264 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2265 enum port port = intel_dig_port->port;
2266 struct drm_device *dev = intel_dig_port->base.base.dev;
2267 uint32_t signal_levels, mask;
2268 uint8_t train_set = intel_dp->train_set[0];
2271 signal_levels = intel_hsw_signal_levels(train_set);
2272 mask = DDI_BUF_EMP_MASK;
2273 } else if (IS_VALLEYVIEW(dev)) {
2274 signal_levels = intel_vlv_signal_levels(intel_dp);
2276 } else if (IS_GEN7(dev) && port == PORT_A) {
2277 signal_levels = intel_gen7_edp_signal_levels(train_set);
2278 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
2279 } else if (IS_GEN6(dev) && port == PORT_A) {
2280 signal_levels = intel_gen6_edp_signal_levels(train_set);
2281 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2283 signal_levels = intel_gen4_signal_levels(train_set);
2284 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2287 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2289 *DP = (*DP & ~mask) | signal_levels;
2293 intel_dp_set_link_train(struct intel_dp *intel_dp,
2295 uint8_t dp_train_pat)
2297 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2298 struct drm_device *dev = intel_dig_port->base.base.dev;
2299 struct drm_i915_private *dev_priv = dev->dev_private;
2300 enum port port = intel_dig_port->port;
2301 uint8_t buf[sizeof(intel_dp->train_set) + 1];
2305 uint32_t temp = I915_READ(DP_TP_CTL(port));
2307 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2308 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2310 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2312 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2313 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2314 case DP_TRAINING_PATTERN_DISABLE:
2315 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2318 case DP_TRAINING_PATTERN_1:
2319 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2321 case DP_TRAINING_PATTERN_2:
2322 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2324 case DP_TRAINING_PATTERN_3:
2325 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2328 I915_WRITE(DP_TP_CTL(port), temp);
2330 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2331 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2333 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2334 case DP_TRAINING_PATTERN_DISABLE:
2335 *DP |= DP_LINK_TRAIN_OFF_CPT;
2337 case DP_TRAINING_PATTERN_1:
2338 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2340 case DP_TRAINING_PATTERN_2:
2341 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2343 case DP_TRAINING_PATTERN_3:
2344 DRM_ERROR("DP training pattern 3 not supported\n");
2345 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2350 *DP &= ~DP_LINK_TRAIN_MASK;
2352 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2353 case DP_TRAINING_PATTERN_DISABLE:
2354 *DP |= DP_LINK_TRAIN_OFF;
2356 case DP_TRAINING_PATTERN_1:
2357 *DP |= DP_LINK_TRAIN_PAT_1;
2359 case DP_TRAINING_PATTERN_2:
2360 *DP |= DP_LINK_TRAIN_PAT_2;
2362 case DP_TRAINING_PATTERN_3:
2363 DRM_ERROR("DP training pattern 3 not supported\n");
2364 *DP |= DP_LINK_TRAIN_PAT_2;
2369 I915_WRITE(intel_dp->output_reg, *DP);
2370 POSTING_READ(intel_dp->output_reg);
2372 buf[0] = dp_train_pat;
2373 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
2374 DP_TRAINING_PATTERN_DISABLE) {
2375 /* don't write DP_TRAINING_LANEx_SET on disable */
2378 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
2379 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
2380 len = intel_dp->lane_count + 1;
2383 ret = intel_dp_aux_native_write(intel_dp, DP_TRAINING_PATTERN_SET,
2390 intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2391 uint8_t dp_train_pat)
2393 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
2394 intel_dp_set_signal_levels(intel_dp, DP);
2395 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
2399 intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2400 const uint8_t link_status[DP_LINK_STATUS_SIZE])
2402 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2403 struct drm_device *dev = intel_dig_port->base.base.dev;
2404 struct drm_i915_private *dev_priv = dev->dev_private;
2407 intel_get_adjust_train(intel_dp, link_status);
2408 intel_dp_set_signal_levels(intel_dp, DP);
2410 I915_WRITE(intel_dp->output_reg, *DP);
2411 POSTING_READ(intel_dp->output_reg);
2413 ret = intel_dp_aux_native_write(intel_dp, DP_TRAINING_LANE0_SET,
2414 intel_dp->train_set,
2415 intel_dp->lane_count);
2417 return ret == intel_dp->lane_count;
2420 static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
2422 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2423 struct drm_device *dev = intel_dig_port->base.base.dev;
2424 struct drm_i915_private *dev_priv = dev->dev_private;
2425 enum port port = intel_dig_port->port;
2431 val = I915_READ(DP_TP_CTL(port));
2432 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2433 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
2434 I915_WRITE(DP_TP_CTL(port), val);
2437 * On PORT_A we can have only eDP in SST mode. There the only reason
2438 * we need to set idle transmission mode is to work around a HW issue
2439 * where we enable the pipe while not in idle link-training mode.
2440 * In this case there is requirement to wait for a minimum number of
2441 * idle patterns to be sent.
2446 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2448 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2451 /* Enable corresponding port and start training pattern 1 */
2453 intel_dp_start_link_train(struct intel_dp *intel_dp)
2455 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
2456 struct drm_device *dev = encoder->dev;
2459 int voltage_tries, loop_tries;
2460 uint32_t DP = intel_dp->DP;
2461 uint8_t link_config[2];
2464 intel_ddi_prepare_link_retrain(encoder);
2466 /* Write the link configuration data */
2467 link_config[0] = intel_dp->link_bw;
2468 link_config[1] = intel_dp->lane_count;
2469 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2470 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
2471 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, link_config, 2);
2474 link_config[1] = DP_SET_ANSI_8B10B;
2475 intel_dp_aux_native_write(intel_dp, DP_DOWNSPREAD_CTRL, link_config, 2);
2479 /* clock recovery */
2480 if (!intel_dp_reset_link_train(intel_dp, &DP,
2481 DP_TRAINING_PATTERN_1 |
2482 DP_LINK_SCRAMBLING_DISABLE)) {
2483 DRM_ERROR("failed to enable link training\n");
2491 uint8_t link_status[DP_LINK_STATUS_SIZE];
2493 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
2494 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2495 DRM_ERROR("failed to get link status\n");
2499 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2500 DRM_DEBUG_KMS("clock recovery OK\n");
2504 /* Check to see if we've tried the max voltage */
2505 for (i = 0; i < intel_dp->lane_count; i++)
2506 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
2508 if (i == intel_dp->lane_count) {
2510 if (loop_tries == 5) {
2511 DRM_ERROR("too many full retries, give up\n");
2514 intel_dp_reset_link_train(intel_dp, &DP,
2515 DP_TRAINING_PATTERN_1 |
2516 DP_LINK_SCRAMBLING_DISABLE);
2521 /* Check to see if we've tried the same voltage 5 times */
2522 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
2524 if (voltage_tries == 5) {
2525 DRM_ERROR("too many voltage retries, give up\n");
2530 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
2532 /* Update training set as requested by target */
2533 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2534 DRM_ERROR("failed to update link training\n");
2543 intel_dp_complete_link_train(struct intel_dp *intel_dp)
2545 bool channel_eq = false;
2546 int tries, cr_tries;
2547 uint32_t DP = intel_dp->DP;
2549 /* channel equalization */
2550 if (!intel_dp_set_link_train(intel_dp, &DP,
2551 DP_TRAINING_PATTERN_2 |
2552 DP_LINK_SCRAMBLING_DISABLE)) {
2553 DRM_ERROR("failed to start channel equalization\n");
2561 uint8_t link_status[DP_LINK_STATUS_SIZE];
2564 DRM_ERROR("failed to train DP, aborting\n");
2565 intel_dp_link_down(intel_dp);
2569 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
2570 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2571 DRM_ERROR("failed to get link status\n");
2575 /* Make sure clock is still ok */
2576 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2577 intel_dp_start_link_train(intel_dp);
2578 intel_dp_set_link_train(intel_dp, &DP,
2579 DP_TRAINING_PATTERN_2 |
2580 DP_LINK_SCRAMBLING_DISABLE);
2585 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2590 /* Try 5 times, then try clock recovery if that fails */
2592 intel_dp_link_down(intel_dp);
2593 intel_dp_start_link_train(intel_dp);
2594 intel_dp_set_link_train(intel_dp, &DP,
2595 DP_TRAINING_PATTERN_2 |
2596 DP_LINK_SCRAMBLING_DISABLE);
2602 /* Update training set as requested by target */
2603 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2604 DRM_ERROR("failed to update link training\n");
2610 intel_dp_set_idle_link_train(intel_dp);
2615 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
2619 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
2621 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2622 DP_TRAINING_PATTERN_DISABLE);
2626 intel_dp_link_down(struct intel_dp *intel_dp)
2628 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2629 enum port port = intel_dig_port->port;
2630 struct drm_device *dev = intel_dig_port->base.base.dev;
2631 struct drm_i915_private *dev_priv = dev->dev_private;
2632 struct intel_crtc *intel_crtc =
2633 to_intel_crtc(intel_dig_port->base.base.crtc);
2634 uint32_t DP = intel_dp->DP;
2637 * DDI code has a strict mode set sequence and we should try to respect
2638 * it, otherwise we might hang the machine in many different ways. So we
2639 * really should be disabling the port only on a complete crtc_disable
2640 * sequence. This function is just called under two conditions on DDI
2642 * - Link train failed while doing crtc_enable, and on this case we
2643 * really should respect the mode set sequence and wait for a
2645 * - Someone turned the monitor off and intel_dp_check_link_status
2646 * called us. We don't need to disable the whole port on this case, so
2647 * when someone turns the monitor on again,
2648 * intel_ddi_prepare_link_retrain will take care of redoing the link
2654 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
2657 DRM_DEBUG_KMS("\n");
2659 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2660 DP &= ~DP_LINK_TRAIN_MASK_CPT;
2661 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
2663 DP &= ~DP_LINK_TRAIN_MASK;
2664 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
2666 POSTING_READ(intel_dp->output_reg);
2668 /* We don't really know why we're doing this */
2669 intel_wait_for_vblank(dev, intel_crtc->pipe);
2671 if (HAS_PCH_IBX(dev) &&
2672 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
2673 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2675 /* Hardware workaround: leaving our transcoder select
2676 * set to transcoder B while it's off will prevent the
2677 * corresponding HDMI output on transcoder A.
2679 * Combine this with another hardware workaround:
2680 * transcoder select bit can only be cleared while the
2683 DP &= ~DP_PIPEB_SELECT;
2684 I915_WRITE(intel_dp->output_reg, DP);
2686 /* Changes to enable or select take place the vblank
2687 * after being written.
2689 if (WARN_ON(crtc == NULL)) {
2690 /* We should never try to disable a port without a crtc
2691 * attached. For paranoia keep the code around for a
2693 POSTING_READ(intel_dp->output_reg);
2696 intel_wait_for_vblank(dev, intel_crtc->pipe);
2699 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
2700 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2701 POSTING_READ(intel_dp->output_reg);
2702 msleep(intel_dp->panel_power_down_delay);
2706 intel_dp_get_dpcd(struct intel_dp *intel_dp)
2708 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2709 struct drm_device *dev = dig_port->base.base.dev;
2710 struct drm_i915_private *dev_priv = dev->dev_private;
2712 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2714 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
2715 sizeof(intel_dp->dpcd)) == 0)
2716 return false; /* aux transfer failed */
2718 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2719 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2720 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2722 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2723 return false; /* DPCD not present */
2725 /* Check if the panel supports PSR */
2726 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
2727 if (is_edp(intel_dp)) {
2728 intel_dp_aux_native_read_retry(intel_dp, DP_PSR_SUPPORT,
2730 sizeof(intel_dp->psr_dpcd));
2731 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
2732 dev_priv->psr.sink_support = true;
2733 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
2737 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2738 DP_DWN_STRM_PORT_PRESENT))
2739 return true; /* native DP sink */
2741 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2742 return true; /* no per-port downstream info */
2744 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2745 intel_dp->downstream_ports,
2746 DP_MAX_DOWNSTREAM_PORTS) == 0)
2747 return false; /* downstream port status fetch failed */
2753 intel_dp_probe_oui(struct intel_dp *intel_dp)
2757 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2760 ironlake_edp_panel_vdd_on(intel_dp);
2762 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2763 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2764 buf[0], buf[1], buf[2]);
2766 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2767 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2768 buf[0], buf[1], buf[2]);
2770 ironlake_edp_panel_vdd_off(intel_dp, false);
2774 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2778 ret = intel_dp_aux_native_read_retry(intel_dp,
2779 DP_DEVICE_SERVICE_IRQ_VECTOR,
2780 sink_irq_vector, 1);
2788 intel_dp_handle_test_request(struct intel_dp *intel_dp)
2790 /* NAK by default */
2791 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
2795 * According to DP spec
2798 * 2. Configure link according to Receiver Capabilities
2799 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2800 * 4. Check link status on receipt of hot-plug interrupt
2804 intel_dp_check_link_status(struct intel_dp *intel_dp)
2806 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
2808 u8 link_status[DP_LINK_STATUS_SIZE];
2810 if (!intel_encoder->connectors_active)
2813 if (WARN_ON(!intel_encoder->base.crtc))
2816 /* Try to read receiver status if the link appears to be up */
2817 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2818 intel_dp_link_down(intel_dp);
2822 /* Now read the DPCD to see if it's actually running */
2823 if (!intel_dp_get_dpcd(intel_dp)) {
2824 intel_dp_link_down(intel_dp);
2828 /* Try to read the source of the interrupt */
2829 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2830 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2831 /* Clear interrupt source */
2832 intel_dp_aux_native_write_1(intel_dp,
2833 DP_DEVICE_SERVICE_IRQ_VECTOR,
2836 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2837 intel_dp_handle_test_request(intel_dp);
2838 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2839 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2842 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2843 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2844 drm_get_encoder_name(&intel_encoder->base));
2845 intel_dp_start_link_train(intel_dp);
2846 intel_dp_complete_link_train(intel_dp);
2847 intel_dp_stop_link_train(intel_dp);
2851 /* XXX this is probably wrong for multiple downstream ports */
2852 static enum drm_connector_status
2853 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2855 uint8_t *dpcd = intel_dp->dpcd;
2858 if (!intel_dp_get_dpcd(intel_dp))
2859 return connector_status_disconnected;
2861 /* if there's no downstream port, we're done */
2862 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
2863 return connector_status_connected;
2865 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2866 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2867 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
2869 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
2871 return connector_status_unknown;
2872 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2873 : connector_status_disconnected;
2876 /* If no HPD, poke DDC gently */
2877 if (drm_probe_ddc(&intel_dp->adapter))
2878 return connector_status_connected;
2880 /* Well we tried, say unknown for unreliable port types */
2881 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
2882 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2883 if (type == DP_DS_PORT_TYPE_VGA ||
2884 type == DP_DS_PORT_TYPE_NON_EDID)
2885 return connector_status_unknown;
2887 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2888 DP_DWN_STRM_PORT_TYPE_MASK;
2889 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
2890 type == DP_DWN_STRM_PORT_TYPE_OTHER)
2891 return connector_status_unknown;
2894 /* Anything else is out of spec, warn and ignore */
2895 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2896 return connector_status_disconnected;
2899 static enum drm_connector_status
2900 ironlake_dp_detect(struct intel_dp *intel_dp)
2902 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2903 struct drm_i915_private *dev_priv = dev->dev_private;
2904 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2905 enum drm_connector_status status;
2907 /* Can't disconnect eDP, but you can close the lid... */
2908 if (is_edp(intel_dp)) {
2909 status = intel_panel_detect(dev);
2910 if (status == connector_status_unknown)
2911 status = connector_status_connected;
2915 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
2916 return connector_status_disconnected;
2918 return intel_dp_detect_dpcd(intel_dp);
2921 static enum drm_connector_status
2922 g4x_dp_detect(struct intel_dp *intel_dp)
2924 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2925 struct drm_i915_private *dev_priv = dev->dev_private;
2926 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2929 /* Can't disconnect eDP, but you can close the lid... */
2930 if (is_edp(intel_dp)) {
2931 enum drm_connector_status status;
2933 status = intel_panel_detect(dev);
2934 if (status == connector_status_unknown)
2935 status = connector_status_connected;
2939 switch (intel_dig_port->port) {
2941 bit = PORTB_HOTPLUG_LIVE_STATUS;
2944 bit = PORTC_HOTPLUG_LIVE_STATUS;
2947 bit = PORTD_HOTPLUG_LIVE_STATUS;
2950 return connector_status_unknown;
2953 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2954 return connector_status_disconnected;
2956 return intel_dp_detect_dpcd(intel_dp);
2959 static struct edid *
2960 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2962 struct intel_connector *intel_connector = to_intel_connector(connector);
2964 /* use cached edid if we have one */
2965 if (intel_connector->edid) {
2967 if (IS_ERR(intel_connector->edid))
2970 return drm_edid_duplicate(intel_connector->edid);
2973 return drm_get_edid(connector, adapter);
2977 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2979 struct intel_connector *intel_connector = to_intel_connector(connector);
2981 /* use cached edid if we have one */
2982 if (intel_connector->edid) {
2984 if (IS_ERR(intel_connector->edid))
2987 return intel_connector_update_modes(connector,
2988 intel_connector->edid);
2991 return intel_ddc_get_modes(connector, adapter);
2994 static enum drm_connector_status
2995 intel_dp_detect(struct drm_connector *connector, bool force)
2997 struct intel_dp *intel_dp = intel_attached_dp(connector);
2998 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2999 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3000 struct drm_device *dev = connector->dev;
3001 enum drm_connector_status status;
3002 struct edid *edid = NULL;
3004 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3005 connector->base.id, drm_get_connector_name(connector));
3007 intel_dp->has_audio = false;
3009 if (HAS_PCH_SPLIT(dev))
3010 status = ironlake_dp_detect(intel_dp);
3012 status = g4x_dp_detect(intel_dp);
3014 if (status != connector_status_connected)
3017 intel_dp_probe_oui(intel_dp);
3019 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
3020 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
3022 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
3024 intel_dp->has_audio = drm_detect_monitor_audio(edid);
3029 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3030 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3031 return connector_status_connected;
3034 static int intel_dp_get_modes(struct drm_connector *connector)
3036 struct intel_dp *intel_dp = intel_attached_dp(connector);
3037 struct intel_connector *intel_connector = to_intel_connector(connector);
3038 struct drm_device *dev = connector->dev;
3041 /* We should parse the EDID data and find out if it has an audio sink
3044 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
3048 /* if eDP has no EDID, fall back to fixed mode */
3049 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
3050 struct drm_display_mode *mode;
3051 mode = drm_mode_duplicate(dev,
3052 intel_connector->panel.fixed_mode);
3054 drm_mode_probed_add(connector, mode);
3062 intel_dp_detect_audio(struct drm_connector *connector)
3064 struct intel_dp *intel_dp = intel_attached_dp(connector);
3066 bool has_audio = false;
3068 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
3070 has_audio = drm_detect_monitor_audio(edid);
3078 intel_dp_set_property(struct drm_connector *connector,
3079 struct drm_property *property,
3082 struct drm_i915_private *dev_priv = connector->dev->dev_private;
3083 struct intel_connector *intel_connector = to_intel_connector(connector);
3084 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
3085 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3088 ret = drm_object_property_set_value(&connector->base, property, val);
3092 if (property == dev_priv->force_audio_property) {
3096 if (i == intel_dp->force_audio)
3099 intel_dp->force_audio = i;
3101 if (i == HDMI_AUDIO_AUTO)
3102 has_audio = intel_dp_detect_audio(connector);
3104 has_audio = (i == HDMI_AUDIO_ON);
3106 if (has_audio == intel_dp->has_audio)
3109 intel_dp->has_audio = has_audio;
3113 if (property == dev_priv->broadcast_rgb_property) {
3114 bool old_auto = intel_dp->color_range_auto;
3115 uint32_t old_range = intel_dp->color_range;
3118 case INTEL_BROADCAST_RGB_AUTO:
3119 intel_dp->color_range_auto = true;
3121 case INTEL_BROADCAST_RGB_FULL:
3122 intel_dp->color_range_auto = false;
3123 intel_dp->color_range = 0;
3125 case INTEL_BROADCAST_RGB_LIMITED:
3126 intel_dp->color_range_auto = false;
3127 intel_dp->color_range = DP_COLOR_RANGE_16_235;
3133 if (old_auto == intel_dp->color_range_auto &&
3134 old_range == intel_dp->color_range)
3140 if (is_edp(intel_dp) &&
3141 property == connector->dev->mode_config.scaling_mode_property) {
3142 if (val == DRM_MODE_SCALE_NONE) {
3143 DRM_DEBUG_KMS("no scaling not supported\n");
3147 if (intel_connector->panel.fitting_mode == val) {
3148 /* the eDP scaling property is not changed */
3151 intel_connector->panel.fitting_mode = val;
3159 if (intel_encoder->base.crtc)
3160 intel_crtc_restore_mode(intel_encoder->base.crtc);
3166 intel_dp_connector_destroy(struct drm_connector *connector)
3168 struct intel_connector *intel_connector = to_intel_connector(connector);
3170 if (!IS_ERR_OR_NULL(intel_connector->edid))
3171 kfree(intel_connector->edid);
3173 /* Can't call is_edp() since the encoder may have been destroyed
3175 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3176 intel_panel_fini(&intel_connector->panel);
3178 drm_connector_cleanup(connector);
3182 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
3184 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3185 struct intel_dp *intel_dp = &intel_dig_port->dp;
3186 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3188 i2c_del_adapter(&intel_dp->adapter);
3189 drm_encoder_cleanup(encoder);
3190 if (is_edp(intel_dp)) {
3191 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3192 mutex_lock(&dev->mode_config.mutex);
3193 ironlake_panel_vdd_off_sync(intel_dp);
3194 mutex_unlock(&dev->mode_config.mutex);
3196 kfree(intel_dig_port);
3199 static const struct drm_connector_funcs intel_dp_connector_funcs = {
3200 .dpms = intel_connector_dpms,
3201 .detect = intel_dp_detect,
3202 .fill_modes = drm_helper_probe_single_connector_modes,
3203 .set_property = intel_dp_set_property,
3204 .destroy = intel_dp_connector_destroy,
3207 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
3208 .get_modes = intel_dp_get_modes,
3209 .mode_valid = intel_dp_mode_valid,
3210 .best_encoder = intel_best_encoder,
3213 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
3214 .destroy = intel_dp_encoder_destroy,
3218 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
3220 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3222 intel_dp_check_link_status(intel_dp);
3225 /* Return which DP Port should be selected for Transcoder DP control */
3227 intel_trans_dp_port_sel(struct drm_crtc *crtc)
3229 struct drm_device *dev = crtc->dev;
3230 struct intel_encoder *intel_encoder;
3231 struct intel_dp *intel_dp;
3233 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3234 intel_dp = enc_to_intel_dp(&intel_encoder->base);
3236 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
3237 intel_encoder->type == INTEL_OUTPUT_EDP)
3238 return intel_dp->output_reg;
3244 /* check the VBT to see whether the eDP is on DP-D port */
3245 bool intel_dpd_is_edp(struct drm_device *dev)
3247 struct drm_i915_private *dev_priv = dev->dev_private;
3248 union child_device_config *p_child;
3251 if (!dev_priv->vbt.child_dev_num)
3254 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
3255 p_child = dev_priv->vbt.child_dev + i;
3257 if (p_child->common.dvo_port == PORT_IDPD &&
3258 p_child->common.device_type == DEVICE_TYPE_eDP)
3265 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
3267 struct intel_connector *intel_connector = to_intel_connector(connector);
3269 intel_attach_force_audio_property(connector);
3270 intel_attach_broadcast_rgb_property(connector);
3271 intel_dp->color_range_auto = true;
3273 if (is_edp(intel_dp)) {
3274 drm_mode_create_scaling_mode_property(connector->dev);
3275 drm_object_attach_property(
3277 connector->dev->mode_config.scaling_mode_property,
3278 DRM_MODE_SCALE_ASPECT);
3279 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
3284 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
3285 struct intel_dp *intel_dp,
3286 struct edp_power_seq *out)
3288 struct drm_i915_private *dev_priv = dev->dev_private;
3289 struct edp_power_seq cur, vbt, spec, final;
3290 u32 pp_on, pp_off, pp_div, pp;
3291 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
3293 if (HAS_PCH_SPLIT(dev)) {
3294 pp_ctrl_reg = PCH_PP_CONTROL;
3295 pp_on_reg = PCH_PP_ON_DELAYS;
3296 pp_off_reg = PCH_PP_OFF_DELAYS;
3297 pp_div_reg = PCH_PP_DIVISOR;
3299 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3301 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
3302 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3303 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3304 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
3307 /* Workaround: Need to write PP_CONTROL with the unlock key as
3308 * the very first thing. */
3309 pp = ironlake_get_pp_control(intel_dp);
3310 I915_WRITE(pp_ctrl_reg, pp);
3312 pp_on = I915_READ(pp_on_reg);
3313 pp_off = I915_READ(pp_off_reg);
3314 pp_div = I915_READ(pp_div_reg);
3316 /* Pull timing values out of registers */
3317 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
3318 PANEL_POWER_UP_DELAY_SHIFT;
3320 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
3321 PANEL_LIGHT_ON_DELAY_SHIFT;
3323 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
3324 PANEL_LIGHT_OFF_DELAY_SHIFT;
3326 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
3327 PANEL_POWER_DOWN_DELAY_SHIFT;
3329 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
3330 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
3332 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3333 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
3335 vbt = dev_priv->vbt.edp_pps;
3337 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3338 * our hw here, which are all in 100usec. */
3339 spec.t1_t3 = 210 * 10;
3340 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
3341 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
3342 spec.t10 = 500 * 10;
3343 /* This one is special and actually in units of 100ms, but zero
3344 * based in the hw (so we need to add 100 ms). But the sw vbt
3345 * table multiplies it with 1000 to make it in units of 100usec,
3347 spec.t11_t12 = (510 + 100) * 10;
3349 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3350 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
3352 /* Use the max of the register settings and vbt. If both are
3353 * unset, fall back to the spec limits. */
3354 #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
3356 max(cur.field, vbt.field))
3357 assign_final(t1_t3);
3361 assign_final(t11_t12);
3364 #define get_delay(field) (DIV_ROUND_UP(final.field, 10))
3365 intel_dp->panel_power_up_delay = get_delay(t1_t3);
3366 intel_dp->backlight_on_delay = get_delay(t8);
3367 intel_dp->backlight_off_delay = get_delay(t9);
3368 intel_dp->panel_power_down_delay = get_delay(t10);
3369 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
3372 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
3373 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
3374 intel_dp->panel_power_cycle_delay);
3376 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
3377 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
3384 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
3385 struct intel_dp *intel_dp,
3386 struct edp_power_seq *seq)
3388 struct drm_i915_private *dev_priv = dev->dev_private;
3389 u32 pp_on, pp_off, pp_div, port_sel = 0;
3390 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
3391 int pp_on_reg, pp_off_reg, pp_div_reg;
3393 if (HAS_PCH_SPLIT(dev)) {
3394 pp_on_reg = PCH_PP_ON_DELAYS;
3395 pp_off_reg = PCH_PP_OFF_DELAYS;
3396 pp_div_reg = PCH_PP_DIVISOR;
3398 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3400 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3401 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3402 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
3405 /* And finally store the new values in the power sequencer. */
3406 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
3407 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
3408 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
3409 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
3410 /* Compute the divisor for the pp clock, simply match the Bspec
3412 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
3413 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
3414 << PANEL_POWER_CYCLE_DELAY_SHIFT);
3416 /* Haswell doesn't have any port selection bits for the panel
3417 * power sequencer any more. */
3418 if (IS_VALLEYVIEW(dev)) {
3419 if (dp_to_dig_port(intel_dp)->port == PORT_B)
3420 port_sel = PANEL_PORT_SELECT_DPB_VLV;
3422 port_sel = PANEL_PORT_SELECT_DPC_VLV;
3423 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
3424 if (dp_to_dig_port(intel_dp)->port == PORT_A)
3425 port_sel = PANEL_PORT_SELECT_DPA;
3427 port_sel = PANEL_PORT_SELECT_DPD;
3432 I915_WRITE(pp_on_reg, pp_on);
3433 I915_WRITE(pp_off_reg, pp_off);
3434 I915_WRITE(pp_div_reg, pp_div);
3436 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
3437 I915_READ(pp_on_reg),
3438 I915_READ(pp_off_reg),
3439 I915_READ(pp_div_reg));
3442 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
3443 struct intel_connector *intel_connector)
3445 struct drm_connector *connector = &intel_connector->base;
3446 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3447 struct drm_device *dev = intel_dig_port->base.base.dev;
3448 struct drm_i915_private *dev_priv = dev->dev_private;
3449 struct drm_display_mode *fixed_mode = NULL;
3450 struct edp_power_seq power_seq = { 0 };
3452 struct drm_display_mode *scan;
3455 if (!is_edp(intel_dp))
3458 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
3460 /* Cache DPCD and EDID for edp. */
3461 ironlake_edp_panel_vdd_on(intel_dp);
3462 has_dpcd = intel_dp_get_dpcd(intel_dp);
3463 ironlake_edp_panel_vdd_off(intel_dp, false);
3466 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3467 dev_priv->no_aux_handshake =
3468 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3469 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3471 /* if this fails, presume the device is a ghost */
3472 DRM_INFO("failed to retrieve link info, disabling eDP\n");
3476 /* We now know it's not a ghost, init power sequence regs. */
3477 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
3480 ironlake_edp_panel_vdd_on(intel_dp);
3481 edid = drm_get_edid(connector, &intel_dp->adapter);
3483 if (drm_add_edid_modes(connector, edid)) {
3484 drm_mode_connector_update_edid_property(connector,
3486 drm_edid_to_eld(connector, edid);
3489 edid = ERR_PTR(-EINVAL);
3492 edid = ERR_PTR(-ENOENT);
3494 intel_connector->edid = edid;
3496 /* prefer fixed mode from EDID if available */
3497 list_for_each_entry(scan, &connector->probed_modes, head) {
3498 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3499 fixed_mode = drm_mode_duplicate(dev, scan);
3504 /* fallback to VBT if available for eDP */
3505 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
3506 fixed_mode = drm_mode_duplicate(dev,
3507 dev_priv->vbt.lfp_lvds_vbt_mode);
3509 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3512 ironlake_edp_panel_vdd_off(intel_dp, false);
3514 intel_panel_init(&intel_connector->panel, fixed_mode);
3515 intel_panel_setup_backlight(connector);
3521 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
3522 struct intel_connector *intel_connector)
3524 struct drm_connector *connector = &intel_connector->base;
3525 struct intel_dp *intel_dp = &intel_dig_port->dp;
3526 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3527 struct drm_device *dev = intel_encoder->base.dev;
3528 struct drm_i915_private *dev_priv = dev->dev_private;
3529 enum port port = intel_dig_port->port;
3530 const char *name = NULL;
3533 /* Preserve the current hw state. */
3534 intel_dp->DP = I915_READ(intel_dp->output_reg);
3535 intel_dp->attached_connector = intel_connector;
3537 type = DRM_MODE_CONNECTOR_DisplayPort;
3539 * FIXME : We need to initialize built-in panels before external panels.
3540 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
3544 type = DRM_MODE_CONNECTOR_eDP;
3547 if (IS_VALLEYVIEW(dev))
3548 type = DRM_MODE_CONNECTOR_eDP;
3551 if (HAS_PCH_SPLIT(dev) && intel_dpd_is_edp(dev))
3552 type = DRM_MODE_CONNECTOR_eDP;
3554 default: /* silence GCC warning */
3559 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
3560 * for DP the encoder type can be set by the caller to
3561 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3563 if (type == DRM_MODE_CONNECTOR_eDP)
3564 intel_encoder->type = INTEL_OUTPUT_EDP;
3566 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
3567 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
3570 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
3571 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
3573 connector->interlace_allowed = true;
3574 connector->doublescan_allowed = 0;
3576 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
3577 ironlake_panel_vdd_work);
3579 intel_connector_attach_encoder(intel_connector, intel_encoder);
3580 drm_sysfs_connector_add(connector);
3583 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3585 intel_connector->get_hw_state = intel_connector_get_hw_state;
3587 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
3589 switch (intel_dig_port->port) {
3591 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
3594 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
3597 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
3600 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
3607 /* Set up the DDC bus. */
3610 intel_encoder->hpd_pin = HPD_PORT_A;
3614 intel_encoder->hpd_pin = HPD_PORT_B;
3618 intel_encoder->hpd_pin = HPD_PORT_C;
3622 intel_encoder->hpd_pin = HPD_PORT_D;
3629 error = intel_dp_i2c_init(intel_dp, intel_connector, name);
3630 WARN(error, "intel_dp_i2c_init failed with error %d for port %c\n",
3631 error, port_name(port));
3633 intel_dp->psr_setup_done = false;
3635 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
3636 i2c_del_adapter(&intel_dp->adapter);
3637 if (is_edp(intel_dp)) {
3638 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3639 mutex_lock(&dev->mode_config.mutex);
3640 ironlake_panel_vdd_off_sync(intel_dp);
3641 mutex_unlock(&dev->mode_config.mutex);
3643 drm_sysfs_connector_remove(connector);
3644 drm_connector_cleanup(connector);
3648 intel_dp_add_properties(intel_dp, connector);
3650 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3651 * 0xd. Failure to do so will result in spurious interrupts being
3652 * generated on the port when a cable is not attached.
3654 if (IS_G4X(dev) && !IS_GM45(dev)) {
3655 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3656 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3663 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
3665 struct intel_digital_port *intel_dig_port;
3666 struct intel_encoder *intel_encoder;
3667 struct drm_encoder *encoder;
3668 struct intel_connector *intel_connector;
3670 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
3671 if (!intel_dig_port)
3674 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
3675 if (!intel_connector) {
3676 kfree(intel_dig_port);
3680 intel_encoder = &intel_dig_port->base;
3681 encoder = &intel_encoder->base;
3683 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
3684 DRM_MODE_ENCODER_TMDS);
3686 intel_encoder->compute_config = intel_dp_compute_config;
3687 intel_encoder->mode_set = intel_dp_mode_set;
3688 intel_encoder->disable = intel_disable_dp;
3689 intel_encoder->post_disable = intel_post_disable_dp;
3690 intel_encoder->get_hw_state = intel_dp_get_hw_state;
3691 intel_encoder->get_config = intel_dp_get_config;
3692 if (IS_VALLEYVIEW(dev)) {
3693 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
3694 intel_encoder->pre_enable = vlv_pre_enable_dp;
3695 intel_encoder->enable = vlv_enable_dp;
3697 intel_encoder->pre_enable = g4x_pre_enable_dp;
3698 intel_encoder->enable = g4x_enable_dp;
3701 intel_dig_port->port = port;
3702 intel_dig_port->dp.output_reg = output_reg;
3704 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3705 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3706 intel_encoder->cloneable = false;
3707 intel_encoder->hot_plug = intel_dp_hot_plug;
3709 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
3710 drm_encoder_cleanup(encoder);
3711 kfree(intel_dig_port);
3712 kfree(intel_connector);