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Merge branch 'linux-4.12' of git://github.com/skeggsb/linux into drm-next
[karo-tx-linux.git] / drivers / gpu / drm / i915 / intel_dp.c
1 /*
2  * Copyright © 2008 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21  * IN THE SOFTWARE.
22  *
23  * Authors:
24  *    Keith Packard <keithp@keithp.com>
25  *
26  */
27
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <linux/types.h>
32 #include <linux/notifier.h>
33 #include <linux/reboot.h>
34 #include <asm/byteorder.h>
35 #include <drm/drmP.h>
36 #include <drm/drm_atomic_helper.h>
37 #include <drm/drm_crtc.h>
38 #include <drm/drm_crtc_helper.h>
39 #include <drm/drm_edid.h>
40 #include "intel_drv.h"
41 #include <drm/i915_drm.h>
42 #include "i915_drv.h"
43
44 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
45
46 /* Compliance test status bits  */
47 #define INTEL_DP_RESOLUTION_SHIFT_MASK  0
48 #define INTEL_DP_RESOLUTION_PREFERRED   (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
49 #define INTEL_DP_RESOLUTION_STANDARD    (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
50 #define INTEL_DP_RESOLUTION_FAILSAFE    (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
51
52 struct dp_link_dpll {
53         int clock;
54         struct dpll dpll;
55 };
56
57 static const struct dp_link_dpll gen4_dpll[] = {
58         { 162000,
59                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
60         { 270000,
61                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
62 };
63
64 static const struct dp_link_dpll pch_dpll[] = {
65         { 162000,
66                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
67         { 270000,
68                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
69 };
70
71 static const struct dp_link_dpll vlv_dpll[] = {
72         { 162000,
73                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
74         { 270000,
75                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
76 };
77
78 /*
79  * CHV supports eDP 1.4 that have  more link rates.
80  * Below only provides the fixed rate but exclude variable rate.
81  */
82 static const struct dp_link_dpll chv_dpll[] = {
83         /*
84          * CHV requires to program fractional division for m2.
85          * m2 is stored in fixed point format using formula below
86          * (m2_int << 22) | m2_fraction
87          */
88         { 162000,       /* m2_int = 32, m2_fraction = 1677722 */
89                 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
90         { 270000,       /* m2_int = 27, m2_fraction = 0 */
91                 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
92         { 540000,       /* m2_int = 27, m2_fraction = 0 */
93                 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
94 };
95
96 static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
97                                   324000, 432000, 540000 };
98 static const int skl_rates[] = { 162000, 216000, 270000,
99                                   324000, 432000, 540000 };
100 static const int default_rates[] = { 162000, 270000, 540000 };
101
102 /**
103  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
104  * @intel_dp: DP struct
105  *
106  * If a CPU or PCH DP output is attached to an eDP panel, this function
107  * will return true, and false otherwise.
108  */
109 static bool is_edp(struct intel_dp *intel_dp)
110 {
111         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
112
113         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
114 }
115
116 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
117 {
118         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
119
120         return intel_dig_port->base.base.dev;
121 }
122
123 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
124 {
125         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
126 }
127
128 static void intel_dp_link_down(struct intel_dp *intel_dp);
129 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
130 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
131 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
132 static void vlv_steal_power_sequencer(struct drm_device *dev,
133                                       enum pipe pipe);
134 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
135
136 static int
137 intel_dp_max_link_bw(struct intel_dp  *intel_dp)
138 {
139         int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
140
141         switch (max_link_bw) {
142         case DP_LINK_BW_1_62:
143         case DP_LINK_BW_2_7:
144         case DP_LINK_BW_5_4:
145                 break;
146         default:
147                 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
148                      max_link_bw);
149                 max_link_bw = DP_LINK_BW_1_62;
150                 break;
151         }
152         return max_link_bw;
153 }
154
155 static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
156 {
157         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
158         u8 source_max, sink_max;
159
160         source_max = intel_dig_port->max_lanes;
161         sink_max = intel_dp->max_sink_lane_count;
162
163         return min(source_max, sink_max);
164 }
165
166 int
167 intel_dp_link_required(int pixel_clock, int bpp)
168 {
169         /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
170         return DIV_ROUND_UP(pixel_clock * bpp, 8);
171 }
172
173 int
174 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
175 {
176         /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
177          * link rate that is generally expressed in Gbps. Since, 8 bits of data
178          * is transmitted every LS_Clk per lane, there is no need to account for
179          * the channel encoding that is done in the PHY layer here.
180          */
181
182         return max_link_clock * max_lanes;
183 }
184
185 static int
186 intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
187 {
188         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
189         struct intel_encoder *encoder = &intel_dig_port->base;
190         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
191         int max_dotclk = dev_priv->max_dotclk_freq;
192         int ds_max_dotclk;
193
194         int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
195
196         if (type != DP_DS_PORT_TYPE_VGA)
197                 return max_dotclk;
198
199         ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd,
200                                                     intel_dp->downstream_ports);
201
202         if (ds_max_dotclk != 0)
203                 max_dotclk = min(max_dotclk, ds_max_dotclk);
204
205         return max_dotclk;
206 }
207
208 static int
209 intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
210 {
211         if (intel_dp->num_sink_rates) {
212                 *sink_rates = intel_dp->sink_rates;
213                 return intel_dp->num_sink_rates;
214         }
215
216         *sink_rates = default_rates;
217
218         return (intel_dp->max_sink_link_bw >> 3) + 1;
219 }
220
221 static int
222 intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates)
223 {
224         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
225         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
226         int size;
227
228         if (IS_GEN9_LP(dev_priv)) {
229                 *source_rates = bxt_rates;
230                 size = ARRAY_SIZE(bxt_rates);
231         } else if (IS_GEN9_BC(dev_priv)) {
232                 *source_rates = skl_rates;
233                 size = ARRAY_SIZE(skl_rates);
234         } else {
235                 *source_rates = default_rates;
236                 size = ARRAY_SIZE(default_rates);
237         }
238
239         /* This depends on the fact that 5.4 is last value in the array */
240         if (!intel_dp_source_supports_hbr2(intel_dp))
241                 size--;
242
243         return size;
244 }
245
246 static int intersect_rates(const int *source_rates, int source_len,
247                            const int *sink_rates, int sink_len,
248                            int *common_rates)
249 {
250         int i = 0, j = 0, k = 0;
251
252         while (i < source_len && j < sink_len) {
253                 if (source_rates[i] == sink_rates[j]) {
254                         if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
255                                 return k;
256                         common_rates[k] = source_rates[i];
257                         ++k;
258                         ++i;
259                         ++j;
260                 } else if (source_rates[i] < sink_rates[j]) {
261                         ++i;
262                 } else {
263                         ++j;
264                 }
265         }
266         return k;
267 }
268
269 static int intel_dp_common_rates(struct intel_dp *intel_dp,
270                                  int *common_rates)
271 {
272         const int *source_rates, *sink_rates;
273         int source_len, sink_len;
274
275         sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
276         source_len = intel_dp_source_rates(intel_dp, &source_rates);
277
278         return intersect_rates(source_rates, source_len,
279                                sink_rates, sink_len,
280                                common_rates);
281 }
282
283 static int intel_dp_link_rate_index(struct intel_dp *intel_dp,
284                                     int *common_rates, int link_rate)
285 {
286         int common_len;
287         int index;
288
289         common_len = intel_dp_common_rates(intel_dp, common_rates);
290         for (index = 0; index < common_len; index++) {
291                 if (link_rate == common_rates[common_len - index - 1])
292                         return common_len - index - 1;
293         }
294
295         return -1;
296 }
297
298 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
299                                             int link_rate, uint8_t lane_count)
300 {
301         int common_rates[DP_MAX_SUPPORTED_RATES];
302         int link_rate_index;
303
304         link_rate_index = intel_dp_link_rate_index(intel_dp,
305                                                    common_rates,
306                                                    link_rate);
307         if (link_rate_index > 0) {
308                 intel_dp->max_sink_link_bw = drm_dp_link_rate_to_bw_code(common_rates[link_rate_index - 1]);
309                 intel_dp->max_sink_lane_count = lane_count;
310         } else if (lane_count > 1) {
311                 intel_dp->max_sink_link_bw = intel_dp_max_link_bw(intel_dp);
312                 intel_dp->max_sink_lane_count = lane_count >> 1;
313         } else {
314                 DRM_ERROR("Link Training Unsuccessful\n");
315                 return -1;
316         }
317
318         return 0;
319 }
320
321 static enum drm_mode_status
322 intel_dp_mode_valid(struct drm_connector *connector,
323                     struct drm_display_mode *mode)
324 {
325         struct intel_dp *intel_dp = intel_attached_dp(connector);
326         struct intel_connector *intel_connector = to_intel_connector(connector);
327         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
328         int target_clock = mode->clock;
329         int max_rate, mode_rate, max_lanes, max_link_clock;
330         int max_dotclk;
331
332         max_dotclk = intel_dp_downstream_max_dotclock(intel_dp);
333
334         if (is_edp(intel_dp) && fixed_mode) {
335                 if (mode->hdisplay > fixed_mode->hdisplay)
336                         return MODE_PANEL;
337
338                 if (mode->vdisplay > fixed_mode->vdisplay)
339                         return MODE_PANEL;
340
341                 target_clock = fixed_mode->clock;
342         }
343
344         max_link_clock = intel_dp_max_link_rate(intel_dp);
345         max_lanes = intel_dp_max_lane_count(intel_dp);
346
347         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
348         mode_rate = intel_dp_link_required(target_clock, 18);
349
350         if (mode_rate > max_rate || target_clock > max_dotclk)
351                 return MODE_CLOCK_HIGH;
352
353         if (mode->clock < 10000)
354                 return MODE_CLOCK_LOW;
355
356         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
357                 return MODE_H_ILLEGAL;
358
359         return MODE_OK;
360 }
361
362 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
363 {
364         int     i;
365         uint32_t v = 0;
366
367         if (src_bytes > 4)
368                 src_bytes = 4;
369         for (i = 0; i < src_bytes; i++)
370                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
371         return v;
372 }
373
374 static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
375 {
376         int i;
377         if (dst_bytes > 4)
378                 dst_bytes = 4;
379         for (i = 0; i < dst_bytes; i++)
380                 dst[i] = src >> ((3-i) * 8);
381 }
382
383 static void
384 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
385                                     struct intel_dp *intel_dp);
386 static void
387 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
388                                               struct intel_dp *intel_dp,
389                                               bool force_disable_vdd);
390 static void
391 intel_dp_pps_init(struct drm_device *dev, struct intel_dp *intel_dp);
392
393 static void pps_lock(struct intel_dp *intel_dp)
394 {
395         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
396         struct intel_encoder *encoder = &intel_dig_port->base;
397         struct drm_device *dev = encoder->base.dev;
398         struct drm_i915_private *dev_priv = to_i915(dev);
399
400         /*
401          * See vlv_power_sequencer_reset() why we need
402          * a power domain reference here.
403          */
404         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
405
406         mutex_lock(&dev_priv->pps_mutex);
407 }
408
409 static void pps_unlock(struct intel_dp *intel_dp)
410 {
411         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
412         struct intel_encoder *encoder = &intel_dig_port->base;
413         struct drm_device *dev = encoder->base.dev;
414         struct drm_i915_private *dev_priv = to_i915(dev);
415
416         mutex_unlock(&dev_priv->pps_mutex);
417
418         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
419 }
420
421 static void
422 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
423 {
424         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
425         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
426         enum pipe pipe = intel_dp->pps_pipe;
427         bool pll_enabled, release_cl_override = false;
428         enum dpio_phy phy = DPIO_PHY(pipe);
429         enum dpio_channel ch = vlv_pipe_to_channel(pipe);
430         uint32_t DP;
431
432         if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
433                  "skipping pipe %c power seqeuncer kick due to port %c being active\n",
434                  pipe_name(pipe), port_name(intel_dig_port->port)))
435                 return;
436
437         DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
438                       pipe_name(pipe), port_name(intel_dig_port->port));
439
440         /* Preserve the BIOS-computed detected bit. This is
441          * supposed to be read-only.
442          */
443         DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
444         DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
445         DP |= DP_PORT_WIDTH(1);
446         DP |= DP_LINK_TRAIN_PAT_1;
447
448         if (IS_CHERRYVIEW(dev_priv))
449                 DP |= DP_PIPE_SELECT_CHV(pipe);
450         else if (pipe == PIPE_B)
451                 DP |= DP_PIPEB_SELECT;
452
453         pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
454
455         /*
456          * The DPLL for the pipe must be enabled for this to work.
457          * So enable temporarily it if it's not already enabled.
458          */
459         if (!pll_enabled) {
460                 release_cl_override = IS_CHERRYVIEW(dev_priv) &&
461                         !chv_phy_powergate_ch(dev_priv, phy, ch, true);
462
463                 if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ?
464                                      &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
465                         DRM_ERROR("Failed to force on pll for pipe %c!\n",
466                                   pipe_name(pipe));
467                         return;
468                 }
469         }
470
471         /*
472          * Similar magic as in intel_dp_enable_port().
473          * We _must_ do this port enable + disable trick
474          * to make this power seqeuencer lock onto the port.
475          * Otherwise even VDD force bit won't work.
476          */
477         I915_WRITE(intel_dp->output_reg, DP);
478         POSTING_READ(intel_dp->output_reg);
479
480         I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
481         POSTING_READ(intel_dp->output_reg);
482
483         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
484         POSTING_READ(intel_dp->output_reg);
485
486         if (!pll_enabled) {
487                 vlv_force_pll_off(dev_priv, pipe);
488
489                 if (release_cl_override)
490                         chv_phy_powergate_ch(dev_priv, phy, ch, false);
491         }
492 }
493
494 static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
495 {
496         struct intel_encoder *encoder;
497         unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
498
499         /*
500          * We don't have power sequencer currently.
501          * Pick one that's not used by other ports.
502          */
503         for_each_intel_encoder(&dev_priv->drm, encoder) {
504                 struct intel_dp *intel_dp;
505
506                 if (encoder->type != INTEL_OUTPUT_DP &&
507                     encoder->type != INTEL_OUTPUT_EDP)
508                         continue;
509
510                 intel_dp = enc_to_intel_dp(&encoder->base);
511
512                 if (encoder->type == INTEL_OUTPUT_EDP) {
513                         WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
514                                 intel_dp->active_pipe != intel_dp->pps_pipe);
515
516                         if (intel_dp->pps_pipe != INVALID_PIPE)
517                                 pipes &= ~(1 << intel_dp->pps_pipe);
518                 } else {
519                         WARN_ON(intel_dp->pps_pipe != INVALID_PIPE);
520
521                         if (intel_dp->active_pipe != INVALID_PIPE)
522                                 pipes &= ~(1 << intel_dp->active_pipe);
523                 }
524         }
525
526         if (pipes == 0)
527                 return INVALID_PIPE;
528
529         return ffs(pipes) - 1;
530 }
531
532 static enum pipe
533 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
534 {
535         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
536         struct drm_device *dev = intel_dig_port->base.base.dev;
537         struct drm_i915_private *dev_priv = to_i915(dev);
538         enum pipe pipe;
539
540         lockdep_assert_held(&dev_priv->pps_mutex);
541
542         /* We should never land here with regular DP ports */
543         WARN_ON(!is_edp(intel_dp));
544
545         WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
546                 intel_dp->active_pipe != intel_dp->pps_pipe);
547
548         if (intel_dp->pps_pipe != INVALID_PIPE)
549                 return intel_dp->pps_pipe;
550
551         pipe = vlv_find_free_pps(dev_priv);
552
553         /*
554          * Didn't find one. This should not happen since there
555          * are two power sequencers and up to two eDP ports.
556          */
557         if (WARN_ON(pipe == INVALID_PIPE))
558                 pipe = PIPE_A;
559
560         vlv_steal_power_sequencer(dev, pipe);
561         intel_dp->pps_pipe = pipe;
562
563         DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
564                       pipe_name(intel_dp->pps_pipe),
565                       port_name(intel_dig_port->port));
566
567         /* init power sequencer on this pipe and port */
568         intel_dp_init_panel_power_sequencer(dev, intel_dp);
569         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, true);
570
571         /*
572          * Even vdd force doesn't work until we've made
573          * the power sequencer lock in on the port.
574          */
575         vlv_power_sequencer_kick(intel_dp);
576
577         return intel_dp->pps_pipe;
578 }
579
580 static int
581 bxt_power_sequencer_idx(struct intel_dp *intel_dp)
582 {
583         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
584         struct drm_device *dev = intel_dig_port->base.base.dev;
585         struct drm_i915_private *dev_priv = to_i915(dev);
586
587         lockdep_assert_held(&dev_priv->pps_mutex);
588
589         /* We should never land here with regular DP ports */
590         WARN_ON(!is_edp(intel_dp));
591
592         /*
593          * TODO: BXT has 2 PPS instances. The correct port->PPS instance
594          * mapping needs to be retrieved from VBT, for now just hard-code to
595          * use instance #0 always.
596          */
597         if (!intel_dp->pps_reset)
598                 return 0;
599
600         intel_dp->pps_reset = false;
601
602         /*
603          * Only the HW needs to be reprogrammed, the SW state is fixed and
604          * has been setup during connector init.
605          */
606         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, false);
607
608         return 0;
609 }
610
611 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
612                                enum pipe pipe);
613
614 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
615                                enum pipe pipe)
616 {
617         return I915_READ(PP_STATUS(pipe)) & PP_ON;
618 }
619
620 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
621                                 enum pipe pipe)
622 {
623         return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD;
624 }
625
626 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
627                          enum pipe pipe)
628 {
629         return true;
630 }
631
632 static enum pipe
633 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
634                      enum port port,
635                      vlv_pipe_check pipe_check)
636 {
637         enum pipe pipe;
638
639         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
640                 u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) &
641                         PANEL_PORT_SELECT_MASK;
642
643                 if (port_sel != PANEL_PORT_SELECT_VLV(port))
644                         continue;
645
646                 if (!pipe_check(dev_priv, pipe))
647                         continue;
648
649                 return pipe;
650         }
651
652         return INVALID_PIPE;
653 }
654
655 static void
656 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
657 {
658         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
659         struct drm_device *dev = intel_dig_port->base.base.dev;
660         struct drm_i915_private *dev_priv = to_i915(dev);
661         enum port port = intel_dig_port->port;
662
663         lockdep_assert_held(&dev_priv->pps_mutex);
664
665         /* try to find a pipe with this port selected */
666         /* first pick one where the panel is on */
667         intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
668                                                   vlv_pipe_has_pp_on);
669         /* didn't find one? pick one where vdd is on */
670         if (intel_dp->pps_pipe == INVALID_PIPE)
671                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
672                                                           vlv_pipe_has_vdd_on);
673         /* didn't find one? pick one with just the correct port */
674         if (intel_dp->pps_pipe == INVALID_PIPE)
675                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
676                                                           vlv_pipe_any);
677
678         /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
679         if (intel_dp->pps_pipe == INVALID_PIPE) {
680                 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
681                               port_name(port));
682                 return;
683         }
684
685         DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
686                       port_name(port), pipe_name(intel_dp->pps_pipe));
687
688         intel_dp_init_panel_power_sequencer(dev, intel_dp);
689         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, false);
690 }
691
692 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
693 {
694         struct drm_device *dev = &dev_priv->drm;
695         struct intel_encoder *encoder;
696
697         if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
698                     !IS_GEN9_LP(dev_priv)))
699                 return;
700
701         /*
702          * We can't grab pps_mutex here due to deadlock with power_domain
703          * mutex when power_domain functions are called while holding pps_mutex.
704          * That also means that in order to use pps_pipe the code needs to
705          * hold both a power domain reference and pps_mutex, and the power domain
706          * reference get/put must be done while _not_ holding pps_mutex.
707          * pps_{lock,unlock}() do these steps in the correct order, so one
708          * should use them always.
709          */
710
711         for_each_intel_encoder(dev, encoder) {
712                 struct intel_dp *intel_dp;
713
714                 if (encoder->type != INTEL_OUTPUT_DP &&
715                     encoder->type != INTEL_OUTPUT_EDP)
716                         continue;
717
718                 intel_dp = enc_to_intel_dp(&encoder->base);
719
720                 WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
721
722                 if (encoder->type != INTEL_OUTPUT_EDP)
723                         continue;
724
725                 if (IS_GEN9_LP(dev_priv))
726                         intel_dp->pps_reset = true;
727                 else
728                         intel_dp->pps_pipe = INVALID_PIPE;
729         }
730 }
731
732 struct pps_registers {
733         i915_reg_t pp_ctrl;
734         i915_reg_t pp_stat;
735         i915_reg_t pp_on;
736         i915_reg_t pp_off;
737         i915_reg_t pp_div;
738 };
739
740 static void intel_pps_get_registers(struct drm_i915_private *dev_priv,
741                                     struct intel_dp *intel_dp,
742                                     struct pps_registers *regs)
743 {
744         int pps_idx = 0;
745
746         memset(regs, 0, sizeof(*regs));
747
748         if (IS_GEN9_LP(dev_priv))
749                 pps_idx = bxt_power_sequencer_idx(intel_dp);
750         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
751                 pps_idx = vlv_power_sequencer_pipe(intel_dp);
752
753         regs->pp_ctrl = PP_CONTROL(pps_idx);
754         regs->pp_stat = PP_STATUS(pps_idx);
755         regs->pp_on = PP_ON_DELAYS(pps_idx);
756         regs->pp_off = PP_OFF_DELAYS(pps_idx);
757         if (!IS_GEN9_LP(dev_priv))
758                 regs->pp_div = PP_DIVISOR(pps_idx);
759 }
760
761 static i915_reg_t
762 _pp_ctrl_reg(struct intel_dp *intel_dp)
763 {
764         struct pps_registers regs;
765
766         intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp,
767                                 &regs);
768
769         return regs.pp_ctrl;
770 }
771
772 static i915_reg_t
773 _pp_stat_reg(struct intel_dp *intel_dp)
774 {
775         struct pps_registers regs;
776
777         intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp,
778                                 &regs);
779
780         return regs.pp_stat;
781 }
782
783 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
784    This function only applicable when panel PM state is not to be tracked */
785 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
786                               void *unused)
787 {
788         struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
789                                                  edp_notifier);
790         struct drm_device *dev = intel_dp_to_dev(intel_dp);
791         struct drm_i915_private *dev_priv = to_i915(dev);
792
793         if (!is_edp(intel_dp) || code != SYS_RESTART)
794                 return 0;
795
796         pps_lock(intel_dp);
797
798         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
799                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
800                 i915_reg_t pp_ctrl_reg, pp_div_reg;
801                 u32 pp_div;
802
803                 pp_ctrl_reg = PP_CONTROL(pipe);
804                 pp_div_reg  = PP_DIVISOR(pipe);
805                 pp_div = I915_READ(pp_div_reg);
806                 pp_div &= PP_REFERENCE_DIVIDER_MASK;
807
808                 /* 0x1F write to PP_DIV_REG sets max cycle delay */
809                 I915_WRITE(pp_div_reg, pp_div | 0x1F);
810                 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
811                 msleep(intel_dp->panel_power_cycle_delay);
812         }
813
814         pps_unlock(intel_dp);
815
816         return 0;
817 }
818
819 static bool edp_have_panel_power(struct intel_dp *intel_dp)
820 {
821         struct drm_device *dev = intel_dp_to_dev(intel_dp);
822         struct drm_i915_private *dev_priv = to_i915(dev);
823
824         lockdep_assert_held(&dev_priv->pps_mutex);
825
826         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
827             intel_dp->pps_pipe == INVALID_PIPE)
828                 return false;
829
830         return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
831 }
832
833 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
834 {
835         struct drm_device *dev = intel_dp_to_dev(intel_dp);
836         struct drm_i915_private *dev_priv = to_i915(dev);
837
838         lockdep_assert_held(&dev_priv->pps_mutex);
839
840         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
841             intel_dp->pps_pipe == INVALID_PIPE)
842                 return false;
843
844         return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
845 }
846
847 static void
848 intel_dp_check_edp(struct intel_dp *intel_dp)
849 {
850         struct drm_device *dev = intel_dp_to_dev(intel_dp);
851         struct drm_i915_private *dev_priv = to_i915(dev);
852
853         if (!is_edp(intel_dp))
854                 return;
855
856         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
857                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
858                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
859                               I915_READ(_pp_stat_reg(intel_dp)),
860                               I915_READ(_pp_ctrl_reg(intel_dp)));
861         }
862 }
863
864 static uint32_t
865 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
866 {
867         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
868         struct drm_device *dev = intel_dig_port->base.base.dev;
869         struct drm_i915_private *dev_priv = to_i915(dev);
870         i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
871         uint32_t status;
872         bool done;
873
874 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
875         if (has_aux_irq)
876                 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
877                                           msecs_to_jiffies_timeout(10));
878         else
879                 done = wait_for(C, 10) == 0;
880         if (!done)
881                 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
882                           has_aux_irq);
883 #undef C
884
885         return status;
886 }
887
888 static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
889 {
890         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
891         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
892
893         if (index)
894                 return 0;
895
896         /*
897          * The clock divider is based off the hrawclk, and would like to run at
898          * 2MHz.  So, take the hrawclk value and divide by 2000 and use that
899          */
900         return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
901 }
902
903 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
904 {
905         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
906         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
907
908         if (index)
909                 return 0;
910
911         /*
912          * The clock divider is based off the cdclk or PCH rawclk, and would
913          * like to run at 2MHz.  So, take the cdclk or PCH rawclk value and
914          * divide by 2000 and use that
915          */
916         if (intel_dig_port->port == PORT_A)
917                 return DIV_ROUND_CLOSEST(dev_priv->cdclk.hw.cdclk, 2000);
918         else
919                 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
920 }
921
922 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
923 {
924         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
925         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
926
927         if (intel_dig_port->port != PORT_A && HAS_PCH_LPT_H(dev_priv)) {
928                 /* Workaround for non-ULT HSW */
929                 switch (index) {
930                 case 0: return 63;
931                 case 1: return 72;
932                 default: return 0;
933                 }
934         }
935
936         return ilk_get_aux_clock_divider(intel_dp, index);
937 }
938
939 static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
940 {
941         /*
942          * SKL doesn't need us to program the AUX clock divider (Hardware will
943          * derive the clock from CDCLK automatically). We still implement the
944          * get_aux_clock_divider vfunc to plug-in into the existing code.
945          */
946         return index ? 0 : 1;
947 }
948
949 static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
950                                      bool has_aux_irq,
951                                      int send_bytes,
952                                      uint32_t aux_clock_divider)
953 {
954         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
955         struct drm_i915_private *dev_priv =
956                         to_i915(intel_dig_port->base.base.dev);
957         uint32_t precharge, timeout;
958
959         if (IS_GEN6(dev_priv))
960                 precharge = 3;
961         else
962                 precharge = 5;
963
964         if (IS_BROADWELL(dev_priv) && intel_dig_port->port == PORT_A)
965                 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
966         else
967                 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
968
969         return DP_AUX_CH_CTL_SEND_BUSY |
970                DP_AUX_CH_CTL_DONE |
971                (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
972                DP_AUX_CH_CTL_TIME_OUT_ERROR |
973                timeout |
974                DP_AUX_CH_CTL_RECEIVE_ERROR |
975                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
976                (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
977                (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
978 }
979
980 static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
981                                       bool has_aux_irq,
982                                       int send_bytes,
983                                       uint32_t unused)
984 {
985         return DP_AUX_CH_CTL_SEND_BUSY |
986                DP_AUX_CH_CTL_DONE |
987                (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
988                DP_AUX_CH_CTL_TIME_OUT_ERROR |
989                DP_AUX_CH_CTL_TIME_OUT_1600us |
990                DP_AUX_CH_CTL_RECEIVE_ERROR |
991                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
992                DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
993                DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
994 }
995
996 static int
997 intel_dp_aux_ch(struct intel_dp *intel_dp,
998                 const uint8_t *send, int send_bytes,
999                 uint8_t *recv, int recv_size)
1000 {
1001         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1002         struct drm_i915_private *dev_priv =
1003                         to_i915(intel_dig_port->base.base.dev);
1004         i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
1005         uint32_t aux_clock_divider;
1006         int i, ret, recv_bytes;
1007         uint32_t status;
1008         int try, clock = 0;
1009         bool has_aux_irq = HAS_AUX_IRQ(dev_priv);
1010         bool vdd;
1011
1012         pps_lock(intel_dp);
1013
1014         /*
1015          * We will be called with VDD already enabled for dpcd/edid/oui reads.
1016          * In such cases we want to leave VDD enabled and it's up to upper layers
1017          * to turn it off. But for eg. i2c-dev access we need to turn it on/off
1018          * ourselves.
1019          */
1020         vdd = edp_panel_vdd_on(intel_dp);
1021
1022         /* dp aux is extremely sensitive to irq latency, hence request the
1023          * lowest possible wakeup latency and so prevent the cpu from going into
1024          * deep sleep states.
1025          */
1026         pm_qos_update_request(&dev_priv->pm_qos, 0);
1027
1028         intel_dp_check_edp(intel_dp);
1029
1030         /* Try to wait for any previous AUX channel activity */
1031         for (try = 0; try < 3; try++) {
1032                 status = I915_READ_NOTRACE(ch_ctl);
1033                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1034                         break;
1035                 msleep(1);
1036         }
1037
1038         if (try == 3) {
1039                 static u32 last_status = -1;
1040                 const u32 status = I915_READ(ch_ctl);
1041
1042                 if (status != last_status) {
1043                         WARN(1, "dp_aux_ch not started status 0x%08x\n",
1044                              status);
1045                         last_status = status;
1046                 }
1047
1048                 ret = -EBUSY;
1049                 goto out;
1050         }
1051
1052         /* Only 5 data registers! */
1053         if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
1054                 ret = -E2BIG;
1055                 goto out;
1056         }
1057
1058         while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
1059                 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
1060                                                           has_aux_irq,
1061                                                           send_bytes,
1062                                                           aux_clock_divider);
1063
1064                 /* Must try at least 3 times according to DP spec */
1065                 for (try = 0; try < 5; try++) {
1066                         /* Load the send data into the aux channel data registers */
1067                         for (i = 0; i < send_bytes; i += 4)
1068                                 I915_WRITE(intel_dp->aux_ch_data_reg[i >> 2],
1069                                            intel_dp_pack_aux(send + i,
1070                                                              send_bytes - i));
1071
1072                         /* Send the command and wait for it to complete */
1073                         I915_WRITE(ch_ctl, send_ctl);
1074
1075                         status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
1076
1077                         /* Clear done status and any errors */
1078                         I915_WRITE(ch_ctl,
1079                                    status |
1080                                    DP_AUX_CH_CTL_DONE |
1081                                    DP_AUX_CH_CTL_TIME_OUT_ERROR |
1082                                    DP_AUX_CH_CTL_RECEIVE_ERROR);
1083
1084                         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
1085                                 continue;
1086
1087                         /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
1088                          *   400us delay required for errors and timeouts
1089                          *   Timeout errors from the HW already meet this
1090                          *   requirement so skip to next iteration
1091                          */
1092                         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1093                                 usleep_range(400, 500);
1094                                 continue;
1095                         }
1096                         if (status & DP_AUX_CH_CTL_DONE)
1097                                 goto done;
1098                 }
1099         }
1100
1101         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1102                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
1103                 ret = -EBUSY;
1104                 goto out;
1105         }
1106
1107 done:
1108         /* Check for timeout or receive error.
1109          * Timeouts occur when the sink is not connected
1110          */
1111         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1112                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
1113                 ret = -EIO;
1114                 goto out;
1115         }
1116
1117         /* Timeouts occur when the device isn't connected, so they're
1118          * "normal" -- don't fill the kernel log with these */
1119         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
1120                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
1121                 ret = -ETIMEDOUT;
1122                 goto out;
1123         }
1124
1125         /* Unload any bytes sent back from the other side */
1126         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
1127                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
1128
1129         /*
1130          * By BSpec: "Message sizes of 0 or >20 are not allowed."
1131          * We have no idea of what happened so we return -EBUSY so
1132          * drm layer takes care for the necessary retries.
1133          */
1134         if (recv_bytes == 0 || recv_bytes > 20) {
1135                 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
1136                               recv_bytes);
1137                 /*
1138                  * FIXME: This patch was created on top of a series that
1139                  * organize the retries at drm level. There EBUSY should
1140                  * also take care for 1ms wait before retrying.
1141                  * That aux retries re-org is still needed and after that is
1142                  * merged we remove this sleep from here.
1143                  */
1144                 usleep_range(1000, 1500);
1145                 ret = -EBUSY;
1146                 goto out;
1147         }
1148
1149         if (recv_bytes > recv_size)
1150                 recv_bytes = recv_size;
1151
1152         for (i = 0; i < recv_bytes; i += 4)
1153                 intel_dp_unpack_aux(I915_READ(intel_dp->aux_ch_data_reg[i >> 2]),
1154                                     recv + i, recv_bytes - i);
1155
1156         ret = recv_bytes;
1157 out:
1158         pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
1159
1160         if (vdd)
1161                 edp_panel_vdd_off(intel_dp, false);
1162
1163         pps_unlock(intel_dp);
1164
1165         return ret;
1166 }
1167
1168 #define BARE_ADDRESS_SIZE       3
1169 #define HEADER_SIZE             (BARE_ADDRESS_SIZE + 1)
1170 static ssize_t
1171 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1172 {
1173         struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
1174         uint8_t txbuf[20], rxbuf[20];
1175         size_t txsize, rxsize;
1176         int ret;
1177
1178         txbuf[0] = (msg->request << 4) |
1179                 ((msg->address >> 16) & 0xf);
1180         txbuf[1] = (msg->address >> 8) & 0xff;
1181         txbuf[2] = msg->address & 0xff;
1182         txbuf[3] = msg->size - 1;
1183
1184         switch (msg->request & ~DP_AUX_I2C_MOT) {
1185         case DP_AUX_NATIVE_WRITE:
1186         case DP_AUX_I2C_WRITE:
1187         case DP_AUX_I2C_WRITE_STATUS_UPDATE:
1188                 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
1189                 rxsize = 2; /* 0 or 1 data bytes */
1190
1191                 if (WARN_ON(txsize > 20))
1192                         return -E2BIG;
1193
1194                 WARN_ON(!msg->buffer != !msg->size);
1195
1196                 if (msg->buffer)
1197                         memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
1198
1199                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1200                 if (ret > 0) {
1201                         msg->reply = rxbuf[0] >> 4;
1202
1203                         if (ret > 1) {
1204                                 /* Number of bytes written in a short write. */
1205                                 ret = clamp_t(int, rxbuf[1], 0, msg->size);
1206                         } else {
1207                                 /* Return payload size. */
1208                                 ret = msg->size;
1209                         }
1210                 }
1211                 break;
1212
1213         case DP_AUX_NATIVE_READ:
1214         case DP_AUX_I2C_READ:
1215                 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
1216                 rxsize = msg->size + 1;
1217
1218                 if (WARN_ON(rxsize > 20))
1219                         return -E2BIG;
1220
1221                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1222                 if (ret > 0) {
1223                         msg->reply = rxbuf[0] >> 4;
1224                         /*
1225                          * Assume happy day, and copy the data. The caller is
1226                          * expected to check msg->reply before touching it.
1227                          *
1228                          * Return payload size.
1229                          */
1230                         ret--;
1231                         memcpy(msg->buffer, rxbuf + 1, ret);
1232                 }
1233                 break;
1234
1235         default:
1236                 ret = -EINVAL;
1237                 break;
1238         }
1239
1240         return ret;
1241 }
1242
1243 static enum port intel_aux_port(struct drm_i915_private *dev_priv,
1244                                 enum port port)
1245 {
1246         const struct ddi_vbt_port_info *info =
1247                 &dev_priv->vbt.ddi_port_info[port];
1248         enum port aux_port;
1249
1250         if (!info->alternate_aux_channel) {
1251                 DRM_DEBUG_KMS("using AUX %c for port %c (platform default)\n",
1252                               port_name(port), port_name(port));
1253                 return port;
1254         }
1255
1256         switch (info->alternate_aux_channel) {
1257         case DP_AUX_A:
1258                 aux_port = PORT_A;
1259                 break;
1260         case DP_AUX_B:
1261                 aux_port = PORT_B;
1262                 break;
1263         case DP_AUX_C:
1264                 aux_port = PORT_C;
1265                 break;
1266         case DP_AUX_D:
1267                 aux_port = PORT_D;
1268                 break;
1269         default:
1270                 MISSING_CASE(info->alternate_aux_channel);
1271                 aux_port = PORT_A;
1272                 break;
1273         }
1274
1275         DRM_DEBUG_KMS("using AUX %c for port %c (VBT)\n",
1276                       port_name(aux_port), port_name(port));
1277
1278         return aux_port;
1279 }
1280
1281 static i915_reg_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv,
1282                                   enum port port)
1283 {
1284         switch (port) {
1285         case PORT_B:
1286         case PORT_C:
1287         case PORT_D:
1288                 return DP_AUX_CH_CTL(port);
1289         default:
1290                 MISSING_CASE(port);
1291                 return DP_AUX_CH_CTL(PORT_B);
1292         }
1293 }
1294
1295 static i915_reg_t g4x_aux_data_reg(struct drm_i915_private *dev_priv,
1296                                    enum port port, int index)
1297 {
1298         switch (port) {
1299         case PORT_B:
1300         case PORT_C:
1301         case PORT_D:
1302                 return DP_AUX_CH_DATA(port, index);
1303         default:
1304                 MISSING_CASE(port);
1305                 return DP_AUX_CH_DATA(PORT_B, index);
1306         }
1307 }
1308
1309 static i915_reg_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv,
1310                                   enum port port)
1311 {
1312         switch (port) {
1313         case PORT_A:
1314                 return DP_AUX_CH_CTL(port);
1315         case PORT_B:
1316         case PORT_C:
1317         case PORT_D:
1318                 return PCH_DP_AUX_CH_CTL(port);
1319         default:
1320                 MISSING_CASE(port);
1321                 return DP_AUX_CH_CTL(PORT_A);
1322         }
1323 }
1324
1325 static i915_reg_t ilk_aux_data_reg(struct drm_i915_private *dev_priv,
1326                                    enum port port, int index)
1327 {
1328         switch (port) {
1329         case PORT_A:
1330                 return DP_AUX_CH_DATA(port, index);
1331         case PORT_B:
1332         case PORT_C:
1333         case PORT_D:
1334                 return PCH_DP_AUX_CH_DATA(port, index);
1335         default:
1336                 MISSING_CASE(port);
1337                 return DP_AUX_CH_DATA(PORT_A, index);
1338         }
1339 }
1340
1341 static i915_reg_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv,
1342                                   enum port port)
1343 {
1344         switch (port) {
1345         case PORT_A:
1346         case PORT_B:
1347         case PORT_C:
1348         case PORT_D:
1349                 return DP_AUX_CH_CTL(port);
1350         default:
1351                 MISSING_CASE(port);
1352                 return DP_AUX_CH_CTL(PORT_A);
1353         }
1354 }
1355
1356 static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv,
1357                                    enum port port, int index)
1358 {
1359         switch (port) {
1360         case PORT_A:
1361         case PORT_B:
1362         case PORT_C:
1363         case PORT_D:
1364                 return DP_AUX_CH_DATA(port, index);
1365         default:
1366                 MISSING_CASE(port);
1367                 return DP_AUX_CH_DATA(PORT_A, index);
1368         }
1369 }
1370
1371 static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv,
1372                                     enum port port)
1373 {
1374         if (INTEL_INFO(dev_priv)->gen >= 9)
1375                 return skl_aux_ctl_reg(dev_priv, port);
1376         else if (HAS_PCH_SPLIT(dev_priv))
1377                 return ilk_aux_ctl_reg(dev_priv, port);
1378         else
1379                 return g4x_aux_ctl_reg(dev_priv, port);
1380 }
1381
1382 static i915_reg_t intel_aux_data_reg(struct drm_i915_private *dev_priv,
1383                                      enum port port, int index)
1384 {
1385         if (INTEL_INFO(dev_priv)->gen >= 9)
1386                 return skl_aux_data_reg(dev_priv, port, index);
1387         else if (HAS_PCH_SPLIT(dev_priv))
1388                 return ilk_aux_data_reg(dev_priv, port, index);
1389         else
1390                 return g4x_aux_data_reg(dev_priv, port, index);
1391 }
1392
1393 static void intel_aux_reg_init(struct intel_dp *intel_dp)
1394 {
1395         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1396         enum port port = intel_aux_port(dev_priv,
1397                                         dp_to_dig_port(intel_dp)->port);
1398         int i;
1399
1400         intel_dp->aux_ch_ctl_reg = intel_aux_ctl_reg(dev_priv, port);
1401         for (i = 0; i < ARRAY_SIZE(intel_dp->aux_ch_data_reg); i++)
1402                 intel_dp->aux_ch_data_reg[i] = intel_aux_data_reg(dev_priv, port, i);
1403 }
1404
1405 static void
1406 intel_dp_aux_fini(struct intel_dp *intel_dp)
1407 {
1408         kfree(intel_dp->aux.name);
1409 }
1410
1411 static void
1412 intel_dp_aux_init(struct intel_dp *intel_dp)
1413 {
1414         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1415         enum port port = intel_dig_port->port;
1416
1417         intel_aux_reg_init(intel_dp);
1418         drm_dp_aux_init(&intel_dp->aux);
1419
1420         /* Failure to allocate our preferred name is not critical */
1421         intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c", port_name(port));
1422         intel_dp->aux.transfer = intel_dp_aux_transfer;
1423 }
1424
1425 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
1426 {
1427         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1428         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
1429
1430         if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
1431             IS_BROADWELL(dev_priv) || (INTEL_GEN(dev_priv) >= 9))
1432                 return true;
1433         else
1434                 return false;
1435 }
1436
1437 static void
1438 intel_dp_set_clock(struct intel_encoder *encoder,
1439                    struct intel_crtc_state *pipe_config)
1440 {
1441         struct drm_device *dev = encoder->base.dev;
1442         struct drm_i915_private *dev_priv = to_i915(dev);
1443         const struct dp_link_dpll *divisor = NULL;
1444         int i, count = 0;
1445
1446         if (IS_G4X(dev_priv)) {
1447                 divisor = gen4_dpll;
1448                 count = ARRAY_SIZE(gen4_dpll);
1449         } else if (HAS_PCH_SPLIT(dev_priv)) {
1450                 divisor = pch_dpll;
1451                 count = ARRAY_SIZE(pch_dpll);
1452         } else if (IS_CHERRYVIEW(dev_priv)) {
1453                 divisor = chv_dpll;
1454                 count = ARRAY_SIZE(chv_dpll);
1455         } else if (IS_VALLEYVIEW(dev_priv)) {
1456                 divisor = vlv_dpll;
1457                 count = ARRAY_SIZE(vlv_dpll);
1458         }
1459
1460         if (divisor && count) {
1461                 for (i = 0; i < count; i++) {
1462                         if (pipe_config->port_clock == divisor[i].clock) {
1463                                 pipe_config->dpll = divisor[i].dpll;
1464                                 pipe_config->clock_set = true;
1465                                 break;
1466                         }
1467                 }
1468         }
1469 }
1470
1471 static void snprintf_int_array(char *str, size_t len,
1472                                const int *array, int nelem)
1473 {
1474         int i;
1475
1476         str[0] = '\0';
1477
1478         for (i = 0; i < nelem; i++) {
1479                 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1480                 if (r >= len)
1481                         return;
1482                 str += r;
1483                 len -= r;
1484         }
1485 }
1486
1487 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1488 {
1489         const int *source_rates, *sink_rates;
1490         int source_len, sink_len, common_len;
1491         int common_rates[DP_MAX_SUPPORTED_RATES];
1492         char str[128]; /* FIXME: too big for stack? */
1493
1494         if ((drm_debug & DRM_UT_KMS) == 0)
1495                 return;
1496
1497         source_len = intel_dp_source_rates(intel_dp, &source_rates);
1498         snprintf_int_array(str, sizeof(str), source_rates, source_len);
1499         DRM_DEBUG_KMS("source rates: %s\n", str);
1500
1501         sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
1502         snprintf_int_array(str, sizeof(str), sink_rates, sink_len);
1503         DRM_DEBUG_KMS("sink rates: %s\n", str);
1504
1505         common_len = intel_dp_common_rates(intel_dp, common_rates);
1506         snprintf_int_array(str, sizeof(str), common_rates, common_len);
1507         DRM_DEBUG_KMS("common rates: %s\n", str);
1508 }
1509
1510 bool
1511 __intel_dp_read_desc(struct intel_dp *intel_dp, struct intel_dp_desc *desc)
1512 {
1513         u32 base = drm_dp_is_branch(intel_dp->dpcd) ? DP_BRANCH_OUI :
1514                                                       DP_SINK_OUI;
1515
1516         return drm_dp_dpcd_read(&intel_dp->aux, base, desc, sizeof(*desc)) ==
1517                sizeof(*desc);
1518 }
1519
1520 bool intel_dp_read_desc(struct intel_dp *intel_dp)
1521 {
1522         struct intel_dp_desc *desc = &intel_dp->desc;
1523         bool oui_sup = intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] &
1524                        DP_OUI_SUPPORT;
1525         int dev_id_len;
1526
1527         if (!__intel_dp_read_desc(intel_dp, desc))
1528                 return false;
1529
1530         dev_id_len = strnlen(desc->device_id, sizeof(desc->device_id));
1531         DRM_DEBUG_KMS("DP %s: OUI %*phD%s dev-ID %*pE HW-rev %d.%d SW-rev %d.%d\n",
1532                       drm_dp_is_branch(intel_dp->dpcd) ? "branch" : "sink",
1533                       (int)sizeof(desc->oui), desc->oui, oui_sup ? "" : "(NS)",
1534                       dev_id_len, desc->device_id,
1535                       desc->hw_rev >> 4, desc->hw_rev & 0xf,
1536                       desc->sw_major_rev, desc->sw_minor_rev);
1537
1538         return true;
1539 }
1540
1541 static int rate_to_index(int find, const int *rates)
1542 {
1543         int i = 0;
1544
1545         for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i)
1546                 if (find == rates[i])
1547                         break;
1548
1549         return i;
1550 }
1551
1552 int
1553 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1554 {
1555         int rates[DP_MAX_SUPPORTED_RATES] = {};
1556         int len;
1557
1558         len = intel_dp_common_rates(intel_dp, rates);
1559         if (WARN_ON(len <= 0))
1560                 return 162000;
1561
1562         return rates[len - 1];
1563 }
1564
1565 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1566 {
1567         return rate_to_index(rate, intel_dp->sink_rates);
1568 }
1569
1570 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1571                            uint8_t *link_bw, uint8_t *rate_select)
1572 {
1573         if (intel_dp->num_sink_rates) {
1574                 *link_bw = 0;
1575                 *rate_select =
1576                         intel_dp_rate_select(intel_dp, port_clock);
1577         } else {
1578                 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1579                 *rate_select = 0;
1580         }
1581 }
1582
1583 static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
1584                                 struct intel_crtc_state *pipe_config)
1585 {
1586         int bpp, bpc;
1587
1588         bpp = pipe_config->pipe_bpp;
1589         bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports);
1590
1591         if (bpc > 0)
1592                 bpp = min(bpp, 3*bpc);
1593
1594         /* For DP Compliance we override the computed bpp for the pipe */
1595         if (intel_dp->compliance.test_data.bpc != 0) {
1596                 pipe_config->pipe_bpp = 3*intel_dp->compliance.test_data.bpc;
1597                 pipe_config->dither_force_disable = pipe_config->pipe_bpp == 6*3;
1598                 DRM_DEBUG_KMS("Setting pipe_bpp to %d\n",
1599                               pipe_config->pipe_bpp);
1600         }
1601         return bpp;
1602 }
1603
1604 bool
1605 intel_dp_compute_config(struct intel_encoder *encoder,
1606                         struct intel_crtc_state *pipe_config,
1607                         struct drm_connector_state *conn_state)
1608 {
1609         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1610         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1611         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1612         enum port port = dp_to_dig_port(intel_dp)->port;
1613         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
1614         struct intel_connector *intel_connector = intel_dp->attached_connector;
1615         int lane_count, clock;
1616         int min_lane_count = 1;
1617         int max_lane_count = intel_dp_max_lane_count(intel_dp);
1618         /* Conveniently, the link BW constants become indices with a shift...*/
1619         int min_clock = 0;
1620         int max_clock;
1621         int link_rate_index;
1622         int bpp, mode_rate;
1623         int link_avail, link_clock;
1624         int common_rates[DP_MAX_SUPPORTED_RATES] = {};
1625         int common_len;
1626         uint8_t link_bw, rate_select;
1627
1628         common_len = intel_dp_common_rates(intel_dp, common_rates);
1629
1630         /* No common link rates between source and sink */
1631         WARN_ON(common_len <= 0);
1632
1633         max_clock = common_len - 1;
1634
1635         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
1636                 pipe_config->has_pch_encoder = true;
1637
1638         pipe_config->has_drrs = false;
1639         pipe_config->has_audio = intel_dp->has_audio && port != PORT_A;
1640
1641         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1642                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1643                                        adjusted_mode);
1644
1645                 if (INTEL_GEN(dev_priv) >= 9) {
1646                         int ret;
1647                         ret = skl_update_scaler_crtc(pipe_config);
1648                         if (ret)
1649                                 return ret;
1650                 }
1651
1652                 if (HAS_GMCH_DISPLAY(dev_priv))
1653                         intel_gmch_panel_fitting(intel_crtc, pipe_config,
1654                                                  intel_connector->panel.fitting_mode);
1655                 else
1656                         intel_pch_panel_fitting(intel_crtc, pipe_config,
1657                                                 intel_connector->panel.fitting_mode);
1658         }
1659
1660         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
1661                 return false;
1662
1663         /* Use values requested by Compliance Test Request */
1664         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
1665                 link_rate_index = intel_dp_link_rate_index(intel_dp,
1666                                                            common_rates,
1667                                                            intel_dp->compliance.test_link_rate);
1668                 if (link_rate_index >= 0)
1669                         min_clock = max_clock = link_rate_index;
1670                 min_lane_count = max_lane_count = intel_dp->compliance.test_lane_count;
1671         }
1672         DRM_DEBUG_KMS("DP link computation with max lane count %i "
1673                       "max bw %d pixel clock %iKHz\n",
1674                       max_lane_count, common_rates[max_clock],
1675                       adjusted_mode->crtc_clock);
1676
1677         /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1678          * bpc in between. */
1679         bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
1680         if (is_edp(intel_dp)) {
1681
1682                 /* Get bpp from vbt only for panels that dont have bpp in edid */
1683                 if (intel_connector->base.display_info.bpc == 0 &&
1684                         (dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp)) {
1685                         DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1686                                       dev_priv->vbt.edp.bpp);
1687                         bpp = dev_priv->vbt.edp.bpp;
1688                 }
1689
1690                 /*
1691                  * Use the maximum clock and number of lanes the eDP panel
1692                  * advertizes being capable of. The panels are generally
1693                  * designed to support only a single clock and lane
1694                  * configuration, and typically these values correspond to the
1695                  * native resolution of the panel.
1696                  */
1697                 min_lane_count = max_lane_count;
1698                 min_clock = max_clock;
1699         }
1700
1701         for (; bpp >= 6*3; bpp -= 2*3) {
1702                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1703                                                    bpp);
1704
1705                 for (clock = min_clock; clock <= max_clock; clock++) {
1706                         for (lane_count = min_lane_count;
1707                                 lane_count <= max_lane_count;
1708                                 lane_count <<= 1) {
1709
1710                                 link_clock = common_rates[clock];
1711                                 link_avail = intel_dp_max_data_rate(link_clock,
1712                                                                     lane_count);
1713
1714                                 if (mode_rate <= link_avail) {
1715                                         goto found;
1716                                 }
1717                         }
1718                 }
1719         }
1720
1721         return false;
1722
1723 found:
1724         if (intel_dp->color_range_auto) {
1725                 /*
1726                  * See:
1727                  * CEA-861-E - 5.1 Default Encoding Parameters
1728                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1729                  */
1730                 pipe_config->limited_color_range =
1731                         bpp != 18 &&
1732                         drm_default_rgb_quant_range(adjusted_mode) ==
1733                         HDMI_QUANTIZATION_RANGE_LIMITED;
1734         } else {
1735                 pipe_config->limited_color_range =
1736                         intel_dp->limited_color_range;
1737         }
1738
1739         pipe_config->lane_count = lane_count;
1740
1741         pipe_config->pipe_bpp = bpp;
1742         pipe_config->port_clock = common_rates[clock];
1743
1744         intel_dp_compute_rate(intel_dp, pipe_config->port_clock,
1745                               &link_bw, &rate_select);
1746
1747         DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n",
1748                       link_bw, rate_select, pipe_config->lane_count,
1749                       pipe_config->port_clock, bpp);
1750         DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1751                       mode_rate, link_avail);
1752
1753         intel_link_compute_m_n(bpp, lane_count,
1754                                adjusted_mode->crtc_clock,
1755                                pipe_config->port_clock,
1756                                &pipe_config->dp_m_n);
1757
1758         if (intel_connector->panel.downclock_mode != NULL &&
1759                 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
1760                         pipe_config->has_drrs = true;
1761                         intel_link_compute_m_n(bpp, lane_count,
1762                                 intel_connector->panel.downclock_mode->clock,
1763                                 pipe_config->port_clock,
1764                                 &pipe_config->dp_m2_n2);
1765         }
1766
1767         /*
1768          * DPLL0 VCO may need to be adjusted to get the correct
1769          * clock for eDP. This will affect cdclk as well.
1770          */
1771         if (is_edp(intel_dp) && IS_GEN9_BC(dev_priv)) {
1772                 int vco;
1773
1774                 switch (pipe_config->port_clock / 2) {
1775                 case 108000:
1776                 case 216000:
1777                         vco = 8640000;
1778                         break;
1779                 default:
1780                         vco = 8100000;
1781                         break;
1782                 }
1783
1784                 to_intel_atomic_state(pipe_config->base.state)->cdclk.logical.vco = vco;
1785         }
1786
1787         if (!HAS_DDI(dev_priv))
1788                 intel_dp_set_clock(encoder, pipe_config);
1789
1790         return true;
1791 }
1792
1793 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1794                               int link_rate, uint8_t lane_count,
1795                               bool link_mst)
1796 {
1797         intel_dp->link_rate = link_rate;
1798         intel_dp->lane_count = lane_count;
1799         intel_dp->link_mst = link_mst;
1800 }
1801
1802 static void intel_dp_prepare(struct intel_encoder *encoder,
1803                              struct intel_crtc_state *pipe_config)
1804 {
1805         struct drm_device *dev = encoder->base.dev;
1806         struct drm_i915_private *dev_priv = to_i915(dev);
1807         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1808         enum port port = dp_to_dig_port(intel_dp)->port;
1809         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1810         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1811
1812         intel_dp_set_link_params(intel_dp, pipe_config->port_clock,
1813                                  pipe_config->lane_count,
1814                                  intel_crtc_has_type(pipe_config,
1815                                                      INTEL_OUTPUT_DP_MST));
1816
1817         /*
1818          * There are four kinds of DP registers:
1819          *
1820          *      IBX PCH
1821          *      SNB CPU
1822          *      IVB CPU
1823          *      CPT PCH
1824          *
1825          * IBX PCH and CPU are the same for almost everything,
1826          * except that the CPU DP PLL is configured in this
1827          * register
1828          *
1829          * CPT PCH is quite different, having many bits moved
1830          * to the TRANS_DP_CTL register instead. That
1831          * configuration happens (oddly) in ironlake_pch_enable
1832          */
1833
1834         /* Preserve the BIOS-computed detected bit. This is
1835          * supposed to be read-only.
1836          */
1837         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
1838
1839         /* Handle DP bits in common between all three register formats */
1840         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1841         intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
1842
1843         /* Split out the IBX/CPU vs CPT settings */
1844
1845         if (IS_GEN7(dev_priv) && port == PORT_A) {
1846                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1847                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1848                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1849                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1850                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1851
1852                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1853                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1854
1855                 intel_dp->DP |= crtc->pipe << 29;
1856         } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
1857                 u32 trans_dp;
1858
1859                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1860
1861                 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1862                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1863                         trans_dp |= TRANS_DP_ENH_FRAMING;
1864                 else
1865                         trans_dp &= ~TRANS_DP_ENH_FRAMING;
1866                 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
1867         } else {
1868                 if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
1869                         intel_dp->DP |= DP_COLOR_RANGE_16_235;
1870
1871                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1872                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1873                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1874                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1875                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1876
1877                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1878                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1879
1880                 if (IS_CHERRYVIEW(dev_priv))
1881                         intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1882                 else if (crtc->pipe == PIPE_B)
1883                         intel_dp->DP |= DP_PIPEB_SELECT;
1884         }
1885 }
1886
1887 #define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
1888 #define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
1889
1890 #define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
1891 #define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)
1892
1893 #define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1894 #define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
1895
1896 static void intel_pps_verify_state(struct drm_i915_private *dev_priv,
1897                                    struct intel_dp *intel_dp);
1898
1899 static void wait_panel_status(struct intel_dp *intel_dp,
1900                                        u32 mask,
1901                                        u32 value)
1902 {
1903         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1904         struct drm_i915_private *dev_priv = to_i915(dev);
1905         i915_reg_t pp_stat_reg, pp_ctrl_reg;
1906
1907         lockdep_assert_held(&dev_priv->pps_mutex);
1908
1909         intel_pps_verify_state(dev_priv, intel_dp);
1910
1911         pp_stat_reg = _pp_stat_reg(intel_dp);
1912         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1913
1914         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1915                         mask, value,
1916                         I915_READ(pp_stat_reg),
1917                         I915_READ(pp_ctrl_reg));
1918
1919         if (intel_wait_for_register(dev_priv,
1920                                     pp_stat_reg, mask, value,
1921                                     5000))
1922                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1923                                 I915_READ(pp_stat_reg),
1924                                 I915_READ(pp_ctrl_reg));
1925
1926         DRM_DEBUG_KMS("Wait complete\n");
1927 }
1928
1929 static void wait_panel_on(struct intel_dp *intel_dp)
1930 {
1931         DRM_DEBUG_KMS("Wait for panel power on\n");
1932         wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1933 }
1934
1935 static void wait_panel_off(struct intel_dp *intel_dp)
1936 {
1937         DRM_DEBUG_KMS("Wait for panel power off time\n");
1938         wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1939 }
1940
1941 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1942 {
1943         ktime_t panel_power_on_time;
1944         s64 panel_power_off_duration;
1945
1946         DRM_DEBUG_KMS("Wait for panel power cycle\n");
1947
1948         /* take the difference of currrent time and panel power off time
1949          * and then make panel wait for t11_t12 if needed. */
1950         panel_power_on_time = ktime_get_boottime();
1951         panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
1952
1953         /* When we disable the VDD override bit last we have to do the manual
1954          * wait. */
1955         if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
1956                 wait_remaining_ms_from_jiffies(jiffies,
1957                                        intel_dp->panel_power_cycle_delay - panel_power_off_duration);
1958
1959         wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1960 }
1961
1962 static void wait_backlight_on(struct intel_dp *intel_dp)
1963 {
1964         wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1965                                        intel_dp->backlight_on_delay);
1966 }
1967
1968 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
1969 {
1970         wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1971                                        intel_dp->backlight_off_delay);
1972 }
1973
1974 /* Read the current pp_control value, unlocking the register if it
1975  * is locked
1976  */
1977
1978 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1979 {
1980         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1981         struct drm_i915_private *dev_priv = to_i915(dev);
1982         u32 control;
1983
1984         lockdep_assert_held(&dev_priv->pps_mutex);
1985
1986         control = I915_READ(_pp_ctrl_reg(intel_dp));
1987         if (WARN_ON(!HAS_DDI(dev_priv) &&
1988                     (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
1989                 control &= ~PANEL_UNLOCK_MASK;
1990                 control |= PANEL_UNLOCK_REGS;
1991         }
1992         return control;
1993 }
1994
1995 /*
1996  * Must be paired with edp_panel_vdd_off().
1997  * Must hold pps_mutex around the whole on/off sequence.
1998  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1999  */
2000 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
2001 {
2002         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2003         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2004         struct drm_i915_private *dev_priv = to_i915(dev);
2005         u32 pp;
2006         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2007         bool need_to_disable = !intel_dp->want_panel_vdd;
2008
2009         lockdep_assert_held(&dev_priv->pps_mutex);
2010
2011         if (!is_edp(intel_dp))
2012                 return false;
2013
2014         cancel_delayed_work(&intel_dp->panel_vdd_work);
2015         intel_dp->want_panel_vdd = true;
2016
2017         if (edp_have_panel_vdd(intel_dp))
2018                 return need_to_disable;
2019
2020         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
2021
2022         DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
2023                       port_name(intel_dig_port->port));
2024
2025         if (!edp_have_panel_power(intel_dp))
2026                 wait_panel_power_cycle(intel_dp);
2027
2028         pp = ironlake_get_pp_control(intel_dp);
2029         pp |= EDP_FORCE_VDD;
2030
2031         pp_stat_reg = _pp_stat_reg(intel_dp);
2032         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2033
2034         I915_WRITE(pp_ctrl_reg, pp);
2035         POSTING_READ(pp_ctrl_reg);
2036         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2037                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2038         /*
2039          * If the panel wasn't on, delay before accessing aux channel
2040          */
2041         if (!edp_have_panel_power(intel_dp)) {
2042                 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
2043                               port_name(intel_dig_port->port));
2044                 msleep(intel_dp->panel_power_up_delay);
2045         }
2046
2047         return need_to_disable;
2048 }
2049
2050 /*
2051  * Must be paired with intel_edp_panel_vdd_off() or
2052  * intel_edp_panel_off().
2053  * Nested calls to these functions are not allowed since
2054  * we drop the lock. Caller must use some higher level
2055  * locking to prevent nested calls from other threads.
2056  */
2057 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
2058 {
2059         bool vdd;
2060
2061         if (!is_edp(intel_dp))
2062                 return;
2063
2064         pps_lock(intel_dp);
2065         vdd = edp_panel_vdd_on(intel_dp);
2066         pps_unlock(intel_dp);
2067
2068         I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
2069              port_name(dp_to_dig_port(intel_dp)->port));
2070 }
2071
2072 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
2073 {
2074         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2075         struct drm_i915_private *dev_priv = to_i915(dev);
2076         struct intel_digital_port *intel_dig_port =
2077                 dp_to_dig_port(intel_dp);
2078         u32 pp;
2079         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2080
2081         lockdep_assert_held(&dev_priv->pps_mutex);
2082
2083         WARN_ON(intel_dp->want_panel_vdd);
2084
2085         if (!edp_have_panel_vdd(intel_dp))
2086                 return;
2087
2088         DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
2089                       port_name(intel_dig_port->port));
2090
2091         pp = ironlake_get_pp_control(intel_dp);
2092         pp &= ~EDP_FORCE_VDD;
2093
2094         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2095         pp_stat_reg = _pp_stat_reg(intel_dp);
2096
2097         I915_WRITE(pp_ctrl_reg, pp);
2098         POSTING_READ(pp_ctrl_reg);
2099
2100         /* Make sure sequencer is idle before allowing subsequent activity */
2101         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2102         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2103
2104         if ((pp & PANEL_POWER_ON) == 0)
2105                 intel_dp->panel_power_off_time = ktime_get_boottime();
2106
2107         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
2108 }
2109
2110 static void edp_panel_vdd_work(struct work_struct *__work)
2111 {
2112         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
2113                                                  struct intel_dp, panel_vdd_work);
2114
2115         pps_lock(intel_dp);
2116         if (!intel_dp->want_panel_vdd)
2117                 edp_panel_vdd_off_sync(intel_dp);
2118         pps_unlock(intel_dp);
2119 }
2120
2121 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
2122 {
2123         unsigned long delay;
2124
2125         /*
2126          * Queue the timer to fire a long time from now (relative to the power
2127          * down delay) to keep the panel power up across a sequence of
2128          * operations.
2129          */
2130         delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
2131         schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
2132 }
2133
2134 /*
2135  * Must be paired with edp_panel_vdd_on().
2136  * Must hold pps_mutex around the whole on/off sequence.
2137  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2138  */
2139 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
2140 {
2141         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2142
2143         lockdep_assert_held(&dev_priv->pps_mutex);
2144
2145         if (!is_edp(intel_dp))
2146                 return;
2147
2148         I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
2149              port_name(dp_to_dig_port(intel_dp)->port));
2150
2151         intel_dp->want_panel_vdd = false;
2152
2153         if (sync)
2154                 edp_panel_vdd_off_sync(intel_dp);
2155         else
2156                 edp_panel_vdd_schedule_off(intel_dp);
2157 }
2158
2159 static void edp_panel_on(struct intel_dp *intel_dp)
2160 {
2161         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2162         struct drm_i915_private *dev_priv = to_i915(dev);
2163         u32 pp;
2164         i915_reg_t pp_ctrl_reg;
2165
2166         lockdep_assert_held(&dev_priv->pps_mutex);
2167
2168         if (!is_edp(intel_dp))
2169                 return;
2170
2171         DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2172                       port_name(dp_to_dig_port(intel_dp)->port));
2173
2174         if (WARN(edp_have_panel_power(intel_dp),
2175                  "eDP port %c panel power already on\n",
2176                  port_name(dp_to_dig_port(intel_dp)->port)))
2177                 return;
2178
2179         wait_panel_power_cycle(intel_dp);
2180
2181         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2182         pp = ironlake_get_pp_control(intel_dp);
2183         if (IS_GEN5(dev_priv)) {
2184                 /* ILK workaround: disable reset around power sequence */
2185                 pp &= ~PANEL_POWER_RESET;
2186                 I915_WRITE(pp_ctrl_reg, pp);
2187                 POSTING_READ(pp_ctrl_reg);
2188         }
2189
2190         pp |= PANEL_POWER_ON;
2191         if (!IS_GEN5(dev_priv))
2192                 pp |= PANEL_POWER_RESET;
2193
2194         I915_WRITE(pp_ctrl_reg, pp);
2195         POSTING_READ(pp_ctrl_reg);
2196
2197         wait_panel_on(intel_dp);
2198         intel_dp->last_power_on = jiffies;
2199
2200         if (IS_GEN5(dev_priv)) {
2201                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
2202                 I915_WRITE(pp_ctrl_reg, pp);
2203                 POSTING_READ(pp_ctrl_reg);
2204         }
2205 }
2206
2207 void intel_edp_panel_on(struct intel_dp *intel_dp)
2208 {
2209         if (!is_edp(intel_dp))
2210                 return;
2211
2212         pps_lock(intel_dp);
2213         edp_panel_on(intel_dp);
2214         pps_unlock(intel_dp);
2215 }
2216
2217
2218 static void edp_panel_off(struct intel_dp *intel_dp)
2219 {
2220         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2221         struct drm_i915_private *dev_priv = to_i915(dev);
2222         u32 pp;
2223         i915_reg_t pp_ctrl_reg;
2224
2225         lockdep_assert_held(&dev_priv->pps_mutex);
2226
2227         if (!is_edp(intel_dp))
2228                 return;
2229
2230         DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2231                       port_name(dp_to_dig_port(intel_dp)->port));
2232
2233         WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
2234              port_name(dp_to_dig_port(intel_dp)->port));
2235
2236         pp = ironlake_get_pp_control(intel_dp);
2237         /* We need to switch off panel power _and_ force vdd, for otherwise some
2238          * panels get very unhappy and cease to work. */
2239         pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
2240                 EDP_BLC_ENABLE);
2241
2242         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2243
2244         intel_dp->want_panel_vdd = false;
2245
2246         I915_WRITE(pp_ctrl_reg, pp);
2247         POSTING_READ(pp_ctrl_reg);
2248
2249         intel_dp->panel_power_off_time = ktime_get_boottime();
2250         wait_panel_off(intel_dp);
2251
2252         /* We got a reference when we enabled the VDD. */
2253         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
2254 }
2255
2256 void intel_edp_panel_off(struct intel_dp *intel_dp)
2257 {
2258         if (!is_edp(intel_dp))
2259                 return;
2260
2261         pps_lock(intel_dp);
2262         edp_panel_off(intel_dp);
2263         pps_unlock(intel_dp);
2264 }
2265
2266 /* Enable backlight in the panel power control. */
2267 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
2268 {
2269         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2270         struct drm_device *dev = intel_dig_port->base.base.dev;
2271         struct drm_i915_private *dev_priv = to_i915(dev);
2272         u32 pp;
2273         i915_reg_t pp_ctrl_reg;
2274
2275         /*
2276          * If we enable the backlight right away following a panel power
2277          * on, we may see slight flicker as the panel syncs with the eDP
2278          * link.  So delay a bit to make sure the image is solid before
2279          * allowing it to appear.
2280          */
2281         wait_backlight_on(intel_dp);
2282
2283         pps_lock(intel_dp);
2284
2285         pp = ironlake_get_pp_control(intel_dp);
2286         pp |= EDP_BLC_ENABLE;
2287
2288         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2289
2290         I915_WRITE(pp_ctrl_reg, pp);
2291         POSTING_READ(pp_ctrl_reg);
2292
2293         pps_unlock(intel_dp);
2294 }
2295
2296 /* Enable backlight PWM and backlight PP control. */
2297 void intel_edp_backlight_on(struct intel_dp *intel_dp)
2298 {
2299         if (!is_edp(intel_dp))
2300                 return;
2301
2302         DRM_DEBUG_KMS("\n");
2303
2304         intel_panel_enable_backlight(intel_dp->attached_connector);
2305         _intel_edp_backlight_on(intel_dp);
2306 }
2307
2308 /* Disable backlight in the panel power control. */
2309 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
2310 {
2311         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2312         struct drm_i915_private *dev_priv = to_i915(dev);
2313         u32 pp;
2314         i915_reg_t pp_ctrl_reg;
2315
2316         if (!is_edp(intel_dp))
2317                 return;
2318
2319         pps_lock(intel_dp);
2320
2321         pp = ironlake_get_pp_control(intel_dp);
2322         pp &= ~EDP_BLC_ENABLE;
2323
2324         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2325
2326         I915_WRITE(pp_ctrl_reg, pp);
2327         POSTING_READ(pp_ctrl_reg);
2328
2329         pps_unlock(intel_dp);
2330
2331         intel_dp->last_backlight_off = jiffies;
2332         edp_wait_backlight_off(intel_dp);
2333 }
2334
2335 /* Disable backlight PP control and backlight PWM. */
2336 void intel_edp_backlight_off(struct intel_dp *intel_dp)
2337 {
2338         if (!is_edp(intel_dp))
2339                 return;
2340
2341         DRM_DEBUG_KMS("\n");
2342
2343         _intel_edp_backlight_off(intel_dp);
2344         intel_panel_disable_backlight(intel_dp->attached_connector);
2345 }
2346
2347 /*
2348  * Hook for controlling the panel power control backlight through the bl_power
2349  * sysfs attribute. Take care to handle multiple calls.
2350  */
2351 static void intel_edp_backlight_power(struct intel_connector *connector,
2352                                       bool enable)
2353 {
2354         struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
2355         bool is_enabled;
2356
2357         pps_lock(intel_dp);
2358         is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
2359         pps_unlock(intel_dp);
2360
2361         if (is_enabled == enable)
2362                 return;
2363
2364         DRM_DEBUG_KMS("panel power control backlight %s\n",
2365                       enable ? "enable" : "disable");
2366
2367         if (enable)
2368                 _intel_edp_backlight_on(intel_dp);
2369         else
2370                 _intel_edp_backlight_off(intel_dp);
2371 }
2372
2373 static void assert_dp_port(struct intel_dp *intel_dp, bool state)
2374 {
2375         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2376         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2377         bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
2378
2379         I915_STATE_WARN(cur_state != state,
2380                         "DP port %c state assertion failure (expected %s, current %s)\n",
2381                         port_name(dig_port->port),
2382                         onoff(state), onoff(cur_state));
2383 }
2384 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
2385
2386 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
2387 {
2388         bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
2389
2390         I915_STATE_WARN(cur_state != state,
2391                         "eDP PLL state assertion failure (expected %s, current %s)\n",
2392                         onoff(state), onoff(cur_state));
2393 }
2394 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2395 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2396
2397 static void ironlake_edp_pll_on(struct intel_dp *intel_dp,
2398                                 struct intel_crtc_state *pipe_config)
2399 {
2400         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2401         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2402
2403         assert_pipe_disabled(dev_priv, crtc->pipe);
2404         assert_dp_port_disabled(intel_dp);
2405         assert_edp_pll_disabled(dev_priv);
2406
2407         DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2408                       pipe_config->port_clock);
2409
2410         intel_dp->DP &= ~DP_PLL_FREQ_MASK;
2411
2412         if (pipe_config->port_clock == 162000)
2413                 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
2414         else
2415                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
2416
2417         I915_WRITE(DP_A, intel_dp->DP);
2418         POSTING_READ(DP_A);
2419         udelay(500);
2420
2421         /*
2422          * [DevILK] Work around required when enabling DP PLL
2423          * while a pipe is enabled going to FDI:
2424          * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2425          * 2. Program DP PLL enable
2426          */
2427         if (IS_GEN5(dev_priv))
2428                 intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);
2429
2430         intel_dp->DP |= DP_PLL_ENABLE;
2431
2432         I915_WRITE(DP_A, intel_dp->DP);
2433         POSTING_READ(DP_A);
2434         udelay(200);
2435 }
2436
2437 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
2438 {
2439         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2440         struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
2441         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2442
2443         assert_pipe_disabled(dev_priv, crtc->pipe);
2444         assert_dp_port_disabled(intel_dp);
2445         assert_edp_pll_enabled(dev_priv);
2446
2447         DRM_DEBUG_KMS("disabling eDP PLL\n");
2448
2449         intel_dp->DP &= ~DP_PLL_ENABLE;
2450
2451         I915_WRITE(DP_A, intel_dp->DP);
2452         POSTING_READ(DP_A);
2453         udelay(200);
2454 }
2455
2456 /* If the sink supports it, try to set the power state appropriately */
2457 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
2458 {
2459         int ret, i;
2460
2461         /* Should have a valid DPCD by this point */
2462         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2463                 return;
2464
2465         if (mode != DRM_MODE_DPMS_ON) {
2466                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2467                                          DP_SET_POWER_D3);
2468         } else {
2469                 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
2470
2471                 /*
2472                  * When turning on, we need to retry for 1ms to give the sink
2473                  * time to wake up.
2474                  */
2475                 for (i = 0; i < 3; i++) {
2476                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2477                                                  DP_SET_POWER_D0);
2478                         if (ret == 1)
2479                                 break;
2480                         msleep(1);
2481                 }
2482
2483                 if (ret == 1 && lspcon->active)
2484                         lspcon_wait_pcon_mode(lspcon);
2485         }
2486
2487         if (ret != 1)
2488                 DRM_DEBUG_KMS("failed to %s sink power state\n",
2489                               mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
2490 }
2491
2492 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2493                                   enum pipe *pipe)
2494 {
2495         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2496         enum port port = dp_to_dig_port(intel_dp)->port;
2497         struct drm_device *dev = encoder->base.dev;
2498         struct drm_i915_private *dev_priv = to_i915(dev);
2499         u32 tmp;
2500         bool ret;
2501
2502         if (!intel_display_power_get_if_enabled(dev_priv,
2503                                                 encoder->power_domain))
2504                 return false;
2505
2506         ret = false;
2507
2508         tmp = I915_READ(intel_dp->output_reg);
2509
2510         if (!(tmp & DP_PORT_EN))
2511                 goto out;
2512
2513         if (IS_GEN7(dev_priv) && port == PORT_A) {
2514                 *pipe = PORT_TO_PIPE_CPT(tmp);
2515         } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2516                 enum pipe p;
2517
2518                 for_each_pipe(dev_priv, p) {
2519                         u32 trans_dp = I915_READ(TRANS_DP_CTL(p));
2520                         if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) {
2521                                 *pipe = p;
2522                                 ret = true;
2523
2524                                 goto out;
2525                         }
2526                 }
2527
2528                 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2529                               i915_mmio_reg_offset(intel_dp->output_reg));
2530         } else if (IS_CHERRYVIEW(dev_priv)) {
2531                 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
2532         } else {
2533                 *pipe = PORT_TO_PIPE(tmp);
2534         }
2535
2536         ret = true;
2537
2538 out:
2539         intel_display_power_put(dev_priv, encoder->power_domain);
2540
2541         return ret;
2542 }
2543
2544 static void intel_dp_get_config(struct intel_encoder *encoder,
2545                                 struct intel_crtc_state *pipe_config)
2546 {
2547         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2548         u32 tmp, flags = 0;
2549         struct drm_device *dev = encoder->base.dev;
2550         struct drm_i915_private *dev_priv = to_i915(dev);
2551         enum port port = dp_to_dig_port(intel_dp)->port;
2552         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2553
2554         tmp = I915_READ(intel_dp->output_reg);
2555
2556         pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
2557
2558         if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2559                 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2560
2561                 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
2562                         flags |= DRM_MODE_FLAG_PHSYNC;
2563                 else
2564                         flags |= DRM_MODE_FLAG_NHSYNC;
2565
2566                 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
2567                         flags |= DRM_MODE_FLAG_PVSYNC;
2568                 else
2569                         flags |= DRM_MODE_FLAG_NVSYNC;
2570         } else {
2571                 if (tmp & DP_SYNC_HS_HIGH)
2572                         flags |= DRM_MODE_FLAG_PHSYNC;
2573                 else
2574                         flags |= DRM_MODE_FLAG_NHSYNC;
2575
2576                 if (tmp & DP_SYNC_VS_HIGH)
2577                         flags |= DRM_MODE_FLAG_PVSYNC;
2578                 else
2579                         flags |= DRM_MODE_FLAG_NVSYNC;
2580         }
2581
2582         pipe_config->base.adjusted_mode.flags |= flags;
2583
2584         if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
2585                 pipe_config->limited_color_range = true;
2586
2587         pipe_config->lane_count =
2588                 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
2589
2590         intel_dp_get_m_n(crtc, pipe_config);
2591
2592         if (port == PORT_A) {
2593                 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
2594                         pipe_config->port_clock = 162000;
2595                 else
2596                         pipe_config->port_clock = 270000;
2597         }
2598
2599         pipe_config->base.adjusted_mode.crtc_clock =
2600                 intel_dotclock_calculate(pipe_config->port_clock,
2601                                          &pipe_config->dp_m_n);
2602
2603         if (is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
2604             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
2605                 /*
2606                  * This is a big fat ugly hack.
2607                  *
2608                  * Some machines in UEFI boot mode provide us a VBT that has 18
2609                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2610                  * unknown we fail to light up. Yet the same BIOS boots up with
2611                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2612                  * max, not what it tells us to use.
2613                  *
2614                  * Note: This will still be broken if the eDP panel is not lit
2615                  * up by the BIOS, and thus we can't get the mode at module
2616                  * load.
2617                  */
2618                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2619                               pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2620                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
2621         }
2622 }
2623
2624 static void intel_disable_dp(struct intel_encoder *encoder,
2625                              struct intel_crtc_state *old_crtc_state,
2626                              struct drm_connector_state *old_conn_state)
2627 {
2628         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2629         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2630
2631         if (old_crtc_state->has_audio)
2632                 intel_audio_codec_disable(encoder);
2633
2634         if (HAS_PSR(dev_priv) && !HAS_DDI(dev_priv))
2635                 intel_psr_disable(intel_dp);
2636
2637         /* Make sure the panel is off before trying to change the mode. But also
2638          * ensure that we have vdd while we switch off the panel. */
2639         intel_edp_panel_vdd_on(intel_dp);
2640         intel_edp_backlight_off(intel_dp);
2641         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2642         intel_edp_panel_off(intel_dp);
2643
2644         /* disable the port before the pipe on g4x */
2645         if (INTEL_GEN(dev_priv) < 5)
2646                 intel_dp_link_down(intel_dp);
2647 }
2648
2649 static void ilk_post_disable_dp(struct intel_encoder *encoder,
2650                                 struct intel_crtc_state *old_crtc_state,
2651                                 struct drm_connector_state *old_conn_state)
2652 {
2653         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2654         enum port port = dp_to_dig_port(intel_dp)->port;
2655
2656         intel_dp_link_down(intel_dp);
2657
2658         /* Only ilk+ has port A */
2659         if (port == PORT_A)
2660                 ironlake_edp_pll_off(intel_dp);
2661 }
2662
2663 static void vlv_post_disable_dp(struct intel_encoder *encoder,
2664                                 struct intel_crtc_state *old_crtc_state,
2665                                 struct drm_connector_state *old_conn_state)
2666 {
2667         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2668
2669         intel_dp_link_down(intel_dp);
2670 }
2671
2672 static void chv_post_disable_dp(struct intel_encoder *encoder,
2673                                 struct intel_crtc_state *old_crtc_state,
2674                                 struct drm_connector_state *old_conn_state)
2675 {
2676         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2677         struct drm_device *dev = encoder->base.dev;
2678         struct drm_i915_private *dev_priv = to_i915(dev);
2679
2680         intel_dp_link_down(intel_dp);
2681
2682         mutex_lock(&dev_priv->sb_lock);
2683
2684         /* Assert data lane reset */
2685         chv_data_lane_soft_reset(encoder, true);
2686
2687         mutex_unlock(&dev_priv->sb_lock);
2688 }
2689
2690 static void
2691 _intel_dp_set_link_train(struct intel_dp *intel_dp,
2692                          uint32_t *DP,
2693                          uint8_t dp_train_pat)
2694 {
2695         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2696         struct drm_device *dev = intel_dig_port->base.base.dev;
2697         struct drm_i915_private *dev_priv = to_i915(dev);
2698         enum port port = intel_dig_port->port;
2699
2700         if (dp_train_pat & DP_TRAINING_PATTERN_MASK)
2701                 DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",
2702                               dp_train_pat & DP_TRAINING_PATTERN_MASK);
2703
2704         if (HAS_DDI(dev_priv)) {
2705                 uint32_t temp = I915_READ(DP_TP_CTL(port));
2706
2707                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2708                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2709                 else
2710                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2711
2712                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2713                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2714                 case DP_TRAINING_PATTERN_DISABLE:
2715                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2716
2717                         break;
2718                 case DP_TRAINING_PATTERN_1:
2719                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2720                         break;
2721                 case DP_TRAINING_PATTERN_2:
2722                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2723                         break;
2724                 case DP_TRAINING_PATTERN_3:
2725                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2726                         break;
2727                 }
2728                 I915_WRITE(DP_TP_CTL(port), temp);
2729
2730         } else if ((IS_GEN7(dev_priv) && port == PORT_A) ||
2731                    (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
2732                 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2733
2734                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2735                 case DP_TRAINING_PATTERN_DISABLE:
2736                         *DP |= DP_LINK_TRAIN_OFF_CPT;
2737                         break;
2738                 case DP_TRAINING_PATTERN_1:
2739                         *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2740                         break;
2741                 case DP_TRAINING_PATTERN_2:
2742                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2743                         break;
2744                 case DP_TRAINING_PATTERN_3:
2745                         DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2746                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2747                         break;
2748                 }
2749
2750         } else {
2751                 if (IS_CHERRYVIEW(dev_priv))
2752                         *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2753                 else
2754                         *DP &= ~DP_LINK_TRAIN_MASK;
2755
2756                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2757                 case DP_TRAINING_PATTERN_DISABLE:
2758                         *DP |= DP_LINK_TRAIN_OFF;
2759                         break;
2760                 case DP_TRAINING_PATTERN_1:
2761                         *DP |= DP_LINK_TRAIN_PAT_1;
2762                         break;
2763                 case DP_TRAINING_PATTERN_2:
2764                         *DP |= DP_LINK_TRAIN_PAT_2;
2765                         break;
2766                 case DP_TRAINING_PATTERN_3:
2767                         if (IS_CHERRYVIEW(dev_priv)) {
2768                                 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2769                         } else {
2770                                 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2771                                 *DP |= DP_LINK_TRAIN_PAT_2;
2772                         }
2773                         break;
2774                 }
2775         }
2776 }
2777
2778 static void intel_dp_enable_port(struct intel_dp *intel_dp,
2779                                  struct intel_crtc_state *old_crtc_state)
2780 {
2781         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2782         struct drm_i915_private *dev_priv = to_i915(dev);
2783
2784         /* enable with pattern 1 (as per spec) */
2785
2786         intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1);
2787
2788         /*
2789          * Magic for VLV/CHV. We _must_ first set up the register
2790          * without actually enabling the port, and then do another
2791          * write to enable the port. Otherwise link training will
2792          * fail when the power sequencer is freshly used for this port.
2793          */
2794         intel_dp->DP |= DP_PORT_EN;
2795         if (old_crtc_state->has_audio)
2796                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
2797
2798         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2799         POSTING_READ(intel_dp->output_reg);
2800 }
2801
2802 static void intel_enable_dp(struct intel_encoder *encoder,
2803                             struct intel_crtc_state *pipe_config,
2804                             struct drm_connector_state *conn_state)
2805 {
2806         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2807         struct drm_device *dev = encoder->base.dev;
2808         struct drm_i915_private *dev_priv = to_i915(dev);
2809         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2810         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
2811         enum pipe pipe = crtc->pipe;
2812
2813         if (WARN_ON(dp_reg & DP_PORT_EN))
2814                 return;
2815
2816         pps_lock(intel_dp);
2817
2818         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2819                 vlv_init_panel_power_sequencer(intel_dp);
2820
2821         intel_dp_enable_port(intel_dp, pipe_config);
2822
2823         edp_panel_vdd_on(intel_dp);
2824         edp_panel_on(intel_dp);
2825         edp_panel_vdd_off(intel_dp, true);
2826
2827         pps_unlock(intel_dp);
2828
2829         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2830                 unsigned int lane_mask = 0x0;
2831
2832                 if (IS_CHERRYVIEW(dev_priv))
2833                         lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
2834
2835                 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
2836                                     lane_mask);
2837         }
2838
2839         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2840         intel_dp_start_link_train(intel_dp);
2841         intel_dp_stop_link_train(intel_dp);
2842
2843         if (pipe_config->has_audio) {
2844                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2845                                  pipe_name(pipe));
2846                 intel_audio_codec_enable(encoder, pipe_config, conn_state);
2847         }
2848 }
2849
2850 static void g4x_enable_dp(struct intel_encoder *encoder,
2851                           struct intel_crtc_state *pipe_config,
2852                           struct drm_connector_state *conn_state)
2853 {
2854         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2855
2856         intel_enable_dp(encoder, pipe_config, conn_state);
2857         intel_edp_backlight_on(intel_dp);
2858 }
2859
2860 static void vlv_enable_dp(struct intel_encoder *encoder,
2861                           struct intel_crtc_state *pipe_config,
2862                           struct drm_connector_state *conn_state)
2863 {
2864         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2865
2866         intel_edp_backlight_on(intel_dp);
2867         intel_psr_enable(intel_dp);
2868 }
2869
2870 static void g4x_pre_enable_dp(struct intel_encoder *encoder,
2871                               struct intel_crtc_state *pipe_config,
2872                               struct drm_connector_state *conn_state)
2873 {
2874         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2875         enum port port = dp_to_dig_port(intel_dp)->port;
2876
2877         intel_dp_prepare(encoder, pipe_config);
2878
2879         /* Only ilk+ has port A */
2880         if (port == PORT_A)
2881                 ironlake_edp_pll_on(intel_dp, pipe_config);
2882 }
2883
2884 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
2885 {
2886         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2887         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
2888         enum pipe pipe = intel_dp->pps_pipe;
2889         i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
2890
2891         WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
2892
2893         if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
2894                 return;
2895
2896         edp_panel_vdd_off_sync(intel_dp);
2897
2898         /*
2899          * VLV seems to get confused when multiple power seqeuencers
2900          * have the same port selected (even if only one has power/vdd
2901          * enabled). The failure manifests as vlv_wait_port_ready() failing
2902          * CHV on the other hand doesn't seem to mind having the same port
2903          * selected in multiple power seqeuencers, but let's clear the
2904          * port select always when logically disconnecting a power sequencer
2905          * from a port.
2906          */
2907         DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2908                       pipe_name(pipe), port_name(intel_dig_port->port));
2909         I915_WRITE(pp_on_reg, 0);
2910         POSTING_READ(pp_on_reg);
2911
2912         intel_dp->pps_pipe = INVALID_PIPE;
2913 }
2914
2915 static void vlv_steal_power_sequencer(struct drm_device *dev,
2916                                       enum pipe pipe)
2917 {
2918         struct drm_i915_private *dev_priv = to_i915(dev);
2919         struct intel_encoder *encoder;
2920
2921         lockdep_assert_held(&dev_priv->pps_mutex);
2922
2923         for_each_intel_encoder(dev, encoder) {
2924                 struct intel_dp *intel_dp;
2925                 enum port port;
2926
2927                 if (encoder->type != INTEL_OUTPUT_DP &&
2928                     encoder->type != INTEL_OUTPUT_EDP)
2929                         continue;
2930
2931                 intel_dp = enc_to_intel_dp(&encoder->base);
2932                 port = dp_to_dig_port(intel_dp)->port;
2933
2934                 WARN(intel_dp->active_pipe == pipe,
2935                      "stealing pipe %c power sequencer from active (e)DP port %c\n",
2936                      pipe_name(pipe), port_name(port));
2937
2938                 if (intel_dp->pps_pipe != pipe)
2939                         continue;
2940
2941                 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
2942                               pipe_name(pipe), port_name(port));
2943
2944                 /* make sure vdd is off before we steal it */
2945                 vlv_detach_power_sequencer(intel_dp);
2946         }
2947 }
2948
2949 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2950 {
2951         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2952         struct intel_encoder *encoder = &intel_dig_port->base;
2953         struct drm_device *dev = encoder->base.dev;
2954         struct drm_i915_private *dev_priv = to_i915(dev);
2955         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2956
2957         lockdep_assert_held(&dev_priv->pps_mutex);
2958
2959         WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
2960
2961         if (intel_dp->pps_pipe != INVALID_PIPE &&
2962             intel_dp->pps_pipe != crtc->pipe) {
2963                 /*
2964                  * If another power sequencer was being used on this
2965                  * port previously make sure to turn off vdd there while
2966                  * we still have control of it.
2967                  */
2968                 vlv_detach_power_sequencer(intel_dp);
2969         }
2970
2971         /*
2972          * We may be stealing the power
2973          * sequencer from another port.
2974          */
2975         vlv_steal_power_sequencer(dev, crtc->pipe);
2976
2977         intel_dp->active_pipe = crtc->pipe;
2978
2979         if (!is_edp(intel_dp))
2980                 return;
2981
2982         /* now it's all ours */
2983         intel_dp->pps_pipe = crtc->pipe;
2984
2985         DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2986                       pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2987
2988         /* init power sequencer on this pipe and port */
2989         intel_dp_init_panel_power_sequencer(dev, intel_dp);
2990         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, true);
2991 }
2992
2993 static void vlv_pre_enable_dp(struct intel_encoder *encoder,
2994                               struct intel_crtc_state *pipe_config,
2995                               struct drm_connector_state *conn_state)
2996 {
2997         vlv_phy_pre_encoder_enable(encoder);
2998
2999         intel_enable_dp(encoder, pipe_config, conn_state);
3000 }
3001
3002 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder,
3003                                   struct intel_crtc_state *pipe_config,
3004                                   struct drm_connector_state *conn_state)
3005 {
3006         intel_dp_prepare(encoder, pipe_config);
3007
3008         vlv_phy_pre_pll_enable(encoder);
3009 }
3010
3011 static void chv_pre_enable_dp(struct intel_encoder *encoder,
3012                               struct intel_crtc_state *pipe_config,
3013                               struct drm_connector_state *conn_state)
3014 {
3015         chv_phy_pre_encoder_enable(encoder);
3016
3017         intel_enable_dp(encoder, pipe_config, conn_state);
3018
3019         /* Second common lane will stay alive on its own now */
3020         chv_phy_release_cl2_override(encoder);
3021 }
3022
3023 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder,
3024                                   struct intel_crtc_state *pipe_config,
3025                                   struct drm_connector_state *conn_state)
3026 {
3027         intel_dp_prepare(encoder, pipe_config);
3028
3029         chv_phy_pre_pll_enable(encoder);
3030 }
3031
3032 static void chv_dp_post_pll_disable(struct intel_encoder *encoder,
3033                                     struct intel_crtc_state *pipe_config,
3034                                     struct drm_connector_state *conn_state)
3035 {
3036         chv_phy_post_pll_disable(encoder);
3037 }
3038
3039 /*
3040  * Fetch AUX CH registers 0x202 - 0x207 which contain
3041  * link status information
3042  */
3043 bool
3044 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
3045 {
3046         return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status,
3047                                 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
3048 }
3049
3050 static bool intel_dp_get_y_cord_status(struct intel_dp *intel_dp)
3051 {
3052         uint8_t psr_caps = 0;
3053
3054         drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_CAPS, &psr_caps);
3055         return psr_caps & DP_PSR2_SU_Y_COORDINATE_REQUIRED;
3056 }
3057
3058 static bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
3059 {
3060         uint8_t dprx = 0;
3061
3062         drm_dp_dpcd_readb(&intel_dp->aux,
3063                         DP_DPRX_FEATURE_ENUMERATION_LIST,
3064                         &dprx);
3065         return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
3066 }
3067
3068 static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp)
3069 {
3070         uint8_t alpm_caps = 0;
3071
3072         drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP, &alpm_caps);
3073         return alpm_caps & DP_ALPM_CAP;
3074 }
3075
3076 /* These are source-specific values. */
3077 uint8_t
3078 intel_dp_voltage_max(struct intel_dp *intel_dp)
3079 {
3080         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
3081         enum port port = dp_to_dig_port(intel_dp)->port;
3082
3083         if (IS_GEN9_LP(dev_priv))
3084                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3085         else if (INTEL_GEN(dev_priv) >= 9) {
3086                 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3087                 return intel_ddi_dp_voltage_max(encoder);
3088         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3089                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3090         else if (IS_GEN7(dev_priv) && port == PORT_A)
3091                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3092         else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
3093                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3094         else
3095                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3096 }
3097
3098 uint8_t
3099 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
3100 {
3101         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
3102         enum port port = dp_to_dig_port(intel_dp)->port;
3103
3104         if (INTEL_GEN(dev_priv) >= 9) {
3105                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3106                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3107                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3108                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3109                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3110                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3111                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3112                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3113                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3114                 default:
3115                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3116                 }
3117         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3118                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3119                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3120                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3121                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3122                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3123                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3124                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3125                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3126                 default:
3127                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3128                 }
3129         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3130                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3131                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3132                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3133                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3134                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3135                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3136                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3137                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3138                 default:
3139                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3140                 }
3141         } else if (IS_GEN7(dev_priv) && port == PORT_A) {
3142                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3143                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3144                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3145                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3146                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3147                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3148                 default:
3149                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3150                 }
3151         } else {
3152                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3153                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3154                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3155                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3156                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3157                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3158                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3159                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3160                 default:
3161                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3162                 }
3163         }
3164 }
3165
3166 static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
3167 {
3168         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3169         unsigned long demph_reg_value, preemph_reg_value,
3170                 uniqtranscale_reg_value;
3171         uint8_t train_set = intel_dp->train_set[0];
3172
3173         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3174         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3175                 preemph_reg_value = 0x0004000;
3176                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3177                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3178                         demph_reg_value = 0x2B405555;
3179                         uniqtranscale_reg_value = 0x552AB83A;
3180                         break;
3181                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3182                         demph_reg_value = 0x2B404040;
3183                         uniqtranscale_reg_value = 0x5548B83A;
3184                         break;
3185                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3186                         demph_reg_value = 0x2B245555;
3187                         uniqtranscale_reg_value = 0x5560B83A;
3188                         break;
3189                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3190                         demph_reg_value = 0x2B405555;
3191                         uniqtranscale_reg_value = 0x5598DA3A;
3192                         break;
3193                 default:
3194                         return 0;
3195                 }
3196                 break;
3197         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3198                 preemph_reg_value = 0x0002000;
3199                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3200                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3201                         demph_reg_value = 0x2B404040;
3202                         uniqtranscale_reg_value = 0x5552B83A;
3203                         break;
3204                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3205                         demph_reg_value = 0x2B404848;
3206                         uniqtranscale_reg_value = 0x5580B83A;
3207                         break;
3208                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3209                         demph_reg_value = 0x2B404040;
3210                         uniqtranscale_reg_value = 0x55ADDA3A;
3211                         break;
3212                 default:
3213                         return 0;
3214                 }
3215                 break;
3216         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3217                 preemph_reg_value = 0x0000000;
3218                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3219                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3220                         demph_reg_value = 0x2B305555;
3221                         uniqtranscale_reg_value = 0x5570B83A;
3222                         break;
3223                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3224                         demph_reg_value = 0x2B2B4040;
3225                         uniqtranscale_reg_value = 0x55ADDA3A;
3226                         break;
3227                 default:
3228                         return 0;
3229                 }
3230                 break;
3231         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3232                 preemph_reg_value = 0x0006000;
3233                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3234                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3235                         demph_reg_value = 0x1B405555;
3236                         uniqtranscale_reg_value = 0x55ADDA3A;
3237                         break;
3238                 default:
3239                         return 0;
3240                 }
3241                 break;
3242         default:
3243                 return 0;
3244         }
3245
3246         vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
3247                                  uniqtranscale_reg_value, 0);
3248
3249         return 0;
3250 }
3251
3252 static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
3253 {
3254         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3255         u32 deemph_reg_value, margin_reg_value;
3256         bool uniq_trans_scale = false;
3257         uint8_t train_set = intel_dp->train_set[0];
3258
3259         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3260         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3261                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3262                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3263                         deemph_reg_value = 128;
3264                         margin_reg_value = 52;
3265                         break;
3266                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3267                         deemph_reg_value = 128;
3268                         margin_reg_value = 77;
3269                         break;
3270                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3271                         deemph_reg_value = 128;
3272                         margin_reg_value = 102;
3273                         break;
3274                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3275                         deemph_reg_value = 128;
3276                         margin_reg_value = 154;
3277                         uniq_trans_scale = true;
3278                         break;
3279                 default:
3280                         return 0;
3281                 }
3282                 break;
3283         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3284                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3285                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3286                         deemph_reg_value = 85;
3287                         margin_reg_value = 78;
3288                         break;
3289                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3290                         deemph_reg_value = 85;
3291                         margin_reg_value = 116;
3292                         break;
3293                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3294                         deemph_reg_value = 85;
3295                         margin_reg_value = 154;
3296                         break;
3297                 default:
3298                         return 0;
3299                 }
3300                 break;
3301         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3302                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3303                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3304                         deemph_reg_value = 64;
3305                         margin_reg_value = 104;
3306                         break;
3307                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3308                         deemph_reg_value = 64;
3309                         margin_reg_value = 154;
3310                         break;
3311                 default:
3312                         return 0;
3313                 }
3314                 break;
3315         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3316                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3317                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3318                         deemph_reg_value = 43;
3319                         margin_reg_value = 154;
3320                         break;
3321                 default:
3322                         return 0;
3323                 }
3324                 break;
3325         default:
3326                 return 0;
3327         }
3328
3329         chv_set_phy_signal_level(encoder, deemph_reg_value,
3330                                  margin_reg_value, uniq_trans_scale);
3331
3332         return 0;
3333 }
3334
3335 static uint32_t
3336 gen4_signal_levels(uint8_t train_set)
3337 {
3338         uint32_t        signal_levels = 0;
3339
3340         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3341         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3342         default:
3343                 signal_levels |= DP_VOLTAGE_0_4;
3344                 break;
3345         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3346                 signal_levels |= DP_VOLTAGE_0_6;
3347                 break;
3348         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3349                 signal_levels |= DP_VOLTAGE_0_8;
3350                 break;
3351         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3352                 signal_levels |= DP_VOLTAGE_1_2;
3353                 break;
3354         }
3355         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3356         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3357         default:
3358                 signal_levels |= DP_PRE_EMPHASIS_0;
3359                 break;
3360         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3361                 signal_levels |= DP_PRE_EMPHASIS_3_5;
3362                 break;
3363         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3364                 signal_levels |= DP_PRE_EMPHASIS_6;
3365                 break;
3366         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3367                 signal_levels |= DP_PRE_EMPHASIS_9_5;
3368                 break;
3369         }
3370         return signal_levels;
3371 }
3372
3373 /* Gen6's DP voltage swing and pre-emphasis control */
3374 static uint32_t
3375 gen6_edp_signal_levels(uint8_t train_set)
3376 {
3377         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3378                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3379         switch (signal_levels) {
3380         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3381         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3382                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3383         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3384                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
3385         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3386         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3387                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
3388         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3389         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3390                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
3391         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3392         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3393                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
3394         default:
3395                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3396                               "0x%x\n", signal_levels);
3397                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3398         }
3399 }
3400
3401 /* Gen7's DP voltage swing and pre-emphasis control */
3402 static uint32_t
3403 gen7_edp_signal_levels(uint8_t train_set)
3404 {
3405         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3406                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3407         switch (signal_levels) {
3408         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3409                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
3410         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3411                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
3412         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3413                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3414
3415         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3416                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
3417         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3418                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3419
3420         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3421                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
3422         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3423                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3424
3425         default:
3426                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3427                               "0x%x\n", signal_levels);
3428                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3429         }
3430 }
3431
3432 void
3433 intel_dp_set_signal_levels(struct intel_dp *intel_dp)
3434 {
3435         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3436         enum port port = intel_dig_port->port;
3437         struct drm_device *dev = intel_dig_port->base.base.dev;
3438         struct drm_i915_private *dev_priv = to_i915(dev);
3439         uint32_t signal_levels, mask = 0;
3440         uint8_t train_set = intel_dp->train_set[0];
3441
3442         if (HAS_DDI(dev_priv)) {
3443                 signal_levels = ddi_signal_levels(intel_dp);
3444
3445                 if (IS_GEN9_LP(dev_priv))
3446                         signal_levels = 0;
3447                 else
3448                         mask = DDI_BUF_EMP_MASK;
3449         } else if (IS_CHERRYVIEW(dev_priv)) {
3450                 signal_levels = chv_signal_levels(intel_dp);
3451         } else if (IS_VALLEYVIEW(dev_priv)) {
3452                 signal_levels = vlv_signal_levels(intel_dp);
3453         } else if (IS_GEN7(dev_priv) && port == PORT_A) {
3454                 signal_levels = gen7_edp_signal_levels(train_set);
3455                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
3456         } else if (IS_GEN6(dev_priv) && port == PORT_A) {
3457                 signal_levels = gen6_edp_signal_levels(train_set);
3458                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3459         } else {
3460                 signal_levels = gen4_signal_levels(train_set);
3461                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3462         }
3463
3464         if (mask)
3465                 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3466
3467         DRM_DEBUG_KMS("Using vswing level %d\n",
3468                 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
3469         DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3470                 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
3471                         DP_TRAIN_PRE_EMPHASIS_SHIFT);
3472
3473         intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
3474
3475         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3476         POSTING_READ(intel_dp->output_reg);
3477 }
3478
3479 void
3480 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
3481                                        uint8_t dp_train_pat)
3482 {
3483         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3484         struct drm_i915_private *dev_priv =
3485                 to_i915(intel_dig_port->base.base.dev);
3486
3487         _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
3488
3489         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3490         POSTING_READ(intel_dp->output_reg);
3491 }
3492
3493 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3494 {
3495         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3496         struct drm_device *dev = intel_dig_port->base.base.dev;
3497         struct drm_i915_private *dev_priv = to_i915(dev);
3498         enum port port = intel_dig_port->port;
3499         uint32_t val;
3500
3501         if (!HAS_DDI(dev_priv))
3502                 return;
3503
3504         val = I915_READ(DP_TP_CTL(port));
3505         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3506         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3507         I915_WRITE(DP_TP_CTL(port), val);
3508
3509         /*
3510          * On PORT_A we can have only eDP in SST mode. There the only reason
3511          * we need to set idle transmission mode is to work around a HW issue
3512          * where we enable the pipe while not in idle link-training mode.
3513          * In this case there is requirement to wait for a minimum number of
3514          * idle patterns to be sent.
3515          */
3516         if (port == PORT_A)
3517                 return;
3518
3519         if (intel_wait_for_register(dev_priv,DP_TP_STATUS(port),
3520                                     DP_TP_STATUS_IDLE_DONE,
3521                                     DP_TP_STATUS_IDLE_DONE,
3522                                     1))
3523                 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3524 }
3525
3526 static void
3527 intel_dp_link_down(struct intel_dp *intel_dp)
3528 {
3529         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3530         struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
3531         enum port port = intel_dig_port->port;
3532         struct drm_device *dev = intel_dig_port->base.base.dev;
3533         struct drm_i915_private *dev_priv = to_i915(dev);
3534         uint32_t DP = intel_dp->DP;
3535
3536         if (WARN_ON(HAS_DDI(dev_priv)))
3537                 return;
3538
3539         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3540                 return;
3541
3542         DRM_DEBUG_KMS("\n");
3543
3544         if ((IS_GEN7(dev_priv) && port == PORT_A) ||
3545             (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
3546                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
3547                 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
3548         } else {
3549                 if (IS_CHERRYVIEW(dev_priv))
3550                         DP &= ~DP_LINK_TRAIN_MASK_CHV;
3551                 else
3552                         DP &= ~DP_LINK_TRAIN_MASK;
3553                 DP |= DP_LINK_TRAIN_PAT_IDLE;
3554         }
3555         I915_WRITE(intel_dp->output_reg, DP);
3556         POSTING_READ(intel_dp->output_reg);
3557
3558         DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
3559         I915_WRITE(intel_dp->output_reg, DP);
3560         POSTING_READ(intel_dp->output_reg);
3561
3562         /*
3563          * HW workaround for IBX, we need to move the port
3564          * to transcoder A after disabling it to allow the
3565          * matching HDMI port to be enabled on transcoder A.
3566          */
3567         if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) {
3568                 /*
3569                  * We get CPU/PCH FIFO underruns on the other pipe when
3570                  * doing the workaround. Sweep them under the rug.
3571                  */
3572                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3573                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3574
3575                 /* always enable with pattern 1 (as per spec) */
3576                 DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK);
3577                 DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1;
3578                 I915_WRITE(intel_dp->output_reg, DP);
3579                 POSTING_READ(intel_dp->output_reg);
3580
3581                 DP &= ~DP_PORT_EN;
3582                 I915_WRITE(intel_dp->output_reg, DP);
3583                 POSTING_READ(intel_dp->output_reg);
3584
3585                 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
3586                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3587                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3588         }
3589
3590         msleep(intel_dp->panel_power_down_delay);
3591
3592         intel_dp->DP = DP;
3593
3594         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3595                 pps_lock(intel_dp);
3596                 intel_dp->active_pipe = INVALID_PIPE;
3597                 pps_unlock(intel_dp);
3598         }
3599 }
3600
3601 bool
3602 intel_dp_read_dpcd(struct intel_dp *intel_dp)
3603 {
3604         if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd,
3605                              sizeof(intel_dp->dpcd)) < 0)
3606                 return false; /* aux transfer failed */
3607
3608         DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
3609
3610         return intel_dp->dpcd[DP_DPCD_REV] != 0;
3611 }
3612
3613 static bool
3614 intel_edp_init_dpcd(struct intel_dp *intel_dp)
3615 {
3616         struct drm_i915_private *dev_priv =
3617                 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
3618
3619         /* this function is meant to be called only once */
3620         WARN_ON(intel_dp->dpcd[DP_DPCD_REV] != 0);
3621
3622         if (!intel_dp_read_dpcd(intel_dp))
3623                 return false;
3624
3625         intel_dp_read_desc(intel_dp);
3626
3627         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3628                 dev_priv->no_aux_handshake = intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3629                         DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3630
3631         /* Check if the panel supports PSR */
3632         drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT,
3633                          intel_dp->psr_dpcd,
3634                          sizeof(intel_dp->psr_dpcd));
3635         if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3636                 dev_priv->psr.sink_support = true;
3637                 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3638         }
3639
3640         if (INTEL_GEN(dev_priv) >= 9 &&
3641             (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) {
3642                 uint8_t frame_sync_cap;
3643
3644                 dev_priv->psr.sink_support = true;
3645                 drm_dp_dpcd_read(&intel_dp->aux,
3646                                  DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP,
3647                                  &frame_sync_cap, 1);
3648                 dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false;
3649                 /* PSR2 needs frame sync as well */
3650                 dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
3651                 DRM_DEBUG_KMS("PSR2 %s on sink",
3652                               dev_priv->psr.psr2_support ? "supported" : "not supported");
3653
3654                 if (dev_priv->psr.psr2_support) {
3655                         dev_priv->psr.y_cord_support =
3656                                 intel_dp_get_y_cord_status(intel_dp);
3657                         dev_priv->psr.colorimetry_support =
3658                                 intel_dp_get_colorimetry_status(intel_dp);
3659                         dev_priv->psr.alpm =
3660                                 intel_dp_get_alpm_status(intel_dp);
3661                 }
3662
3663         }
3664
3665         /* Read the eDP Display control capabilities registers */
3666         if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
3667             drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
3668                              intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
3669                              sizeof(intel_dp->edp_dpcd))
3670                 DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) sizeof(intel_dp->edp_dpcd),
3671                               intel_dp->edp_dpcd);
3672
3673         /* Intermediate frequency support */
3674         if (intel_dp->edp_dpcd[0] >= 0x03) { /* eDp v1.4 or higher */
3675                 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
3676                 int i;
3677
3678                 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
3679                                 sink_rates, sizeof(sink_rates));
3680
3681                 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3682                         int val = le16_to_cpu(sink_rates[i]);
3683
3684                         if (val == 0)
3685                                 break;
3686
3687                         /* Value read multiplied by 200kHz gives the per-lane
3688                          * link rate in kHz. The source rates are, however,
3689                          * stored in terms of LS_Clk kHz. The full conversion
3690                          * back to symbols is
3691                          * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
3692                          */
3693                         intel_dp->sink_rates[i] = (val * 200) / 10;
3694                 }
3695                 intel_dp->num_sink_rates = i;
3696         }
3697
3698         return true;
3699 }
3700
3701
3702 static bool
3703 intel_dp_get_dpcd(struct intel_dp *intel_dp)
3704 {
3705         if (!intel_dp_read_dpcd(intel_dp))
3706                 return false;
3707
3708         if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT,
3709                              &intel_dp->sink_count, 1) < 0)
3710                 return false;
3711
3712         /*
3713          * Sink count can change between short pulse hpd hence
3714          * a member variable in intel_dp will track any changes
3715          * between short pulse interrupts.
3716          */
3717         intel_dp->sink_count = DP_GET_SINK_COUNT(intel_dp->sink_count);
3718
3719         /*
3720          * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
3721          * a dongle is present but no display. Unless we require to know
3722          * if a dongle is present or not, we don't need to update
3723          * downstream port information. So, an early return here saves
3724          * time from performing other operations which are not required.
3725          */
3726         if (!is_edp(intel_dp) && !intel_dp->sink_count)
3727                 return false;
3728
3729         if (!drm_dp_is_branch(intel_dp->dpcd))
3730                 return true; /* native DP sink */
3731
3732         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3733                 return true; /* no per-port downstream info */
3734
3735         if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3736                              intel_dp->downstream_ports,
3737                              DP_MAX_DOWNSTREAM_PORTS) < 0)
3738                 return false; /* downstream port status fetch failed */
3739
3740         return true;
3741 }
3742
3743 static bool
3744 intel_dp_can_mst(struct intel_dp *intel_dp)
3745 {
3746         u8 buf[1];
3747
3748         if (!i915.enable_dp_mst)
3749                 return false;
3750
3751         if (!intel_dp->can_mst)
3752                 return false;
3753
3754         if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3755                 return false;
3756
3757         if (drm_dp_dpcd_read(&intel_dp->aux, DP_MSTM_CAP, buf, 1) != 1)
3758                 return false;
3759
3760         return buf[0] & DP_MST_CAP;
3761 }
3762
3763 static void
3764 intel_dp_configure_mst(struct intel_dp *intel_dp)
3765 {
3766         if (!i915.enable_dp_mst)
3767                 return;
3768
3769         if (!intel_dp->can_mst)
3770                 return;
3771
3772         intel_dp->is_mst = intel_dp_can_mst(intel_dp);
3773
3774         if (intel_dp->is_mst)
3775                 DRM_DEBUG_KMS("Sink is MST capable\n");
3776         else
3777                 DRM_DEBUG_KMS("Sink is not MST capable\n");
3778
3779         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
3780                                         intel_dp->is_mst);
3781 }
3782
3783 static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp)
3784 {
3785         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3786         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3787         struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3788         u8 buf;
3789         int ret = 0;
3790         int count = 0;
3791         int attempts = 10;
3792
3793         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) {
3794                 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3795                 ret = -EIO;
3796                 goto out;
3797         }
3798
3799         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3800                                buf & ~DP_TEST_SINK_START) < 0) {
3801                 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3802                 ret = -EIO;
3803                 goto out;
3804         }
3805
3806         do {
3807                 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
3808
3809                 if (drm_dp_dpcd_readb(&intel_dp->aux,
3810                                       DP_TEST_SINK_MISC, &buf) < 0) {
3811                         ret = -EIO;
3812                         goto out;
3813                 }
3814                 count = buf & DP_TEST_COUNT_MASK;
3815         } while (--attempts && count);
3816
3817         if (attempts == 0) {
3818                 DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n");
3819                 ret = -ETIMEDOUT;
3820         }
3821
3822  out:
3823         hsw_enable_ips(intel_crtc);
3824         return ret;
3825 }
3826
3827 static int intel_dp_sink_crc_start(struct intel_dp *intel_dp)
3828 {
3829         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3830         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3831         struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3832         u8 buf;
3833         int ret;
3834
3835         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
3836                 return -EIO;
3837
3838         if (!(buf & DP_TEST_CRC_SUPPORTED))
3839                 return -ENOTTY;
3840
3841         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3842                 return -EIO;
3843
3844         if (buf & DP_TEST_SINK_START) {
3845                 ret = intel_dp_sink_crc_stop(intel_dp);
3846                 if (ret)
3847                         return ret;
3848         }
3849
3850         hsw_disable_ips(intel_crtc);
3851
3852         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3853                                buf | DP_TEST_SINK_START) < 0) {
3854                 hsw_enable_ips(intel_crtc);
3855                 return -EIO;
3856         }
3857
3858         intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
3859         return 0;
3860 }
3861
3862 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3863 {
3864         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3865         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3866         struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3867         u8 buf;
3868         int count, ret;
3869         int attempts = 6;
3870
3871         ret = intel_dp_sink_crc_start(intel_dp);
3872         if (ret)
3873                 return ret;
3874
3875         do {
3876                 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
3877
3878                 if (drm_dp_dpcd_readb(&intel_dp->aux,
3879                                       DP_TEST_SINK_MISC, &buf) < 0) {
3880                         ret = -EIO;
3881                         goto stop;
3882                 }
3883                 count = buf & DP_TEST_COUNT_MASK;
3884
3885         } while (--attempts && count == 0);
3886
3887         if (attempts == 0) {
3888                 DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n");
3889                 ret = -ETIMEDOUT;
3890                 goto stop;
3891         }
3892
3893         if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) {
3894                 ret = -EIO;
3895                 goto stop;
3896         }
3897
3898 stop:
3899         intel_dp_sink_crc_stop(intel_dp);
3900         return ret;
3901 }
3902
3903 static bool
3904 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3905 {
3906         return drm_dp_dpcd_read(&intel_dp->aux,
3907                                        DP_DEVICE_SERVICE_IRQ_VECTOR,
3908                                        sink_irq_vector, 1) == 1;
3909 }
3910
3911 static bool
3912 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3913 {
3914         int ret;
3915
3916         ret = drm_dp_dpcd_read(&intel_dp->aux,
3917                                              DP_SINK_COUNT_ESI,
3918                                              sink_irq_vector, 14);
3919         if (ret != 14)
3920                 return false;
3921
3922         return true;
3923 }
3924
3925 static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
3926 {
3927         int status = 0;
3928         int min_lane_count = 1;
3929         int common_rates[DP_MAX_SUPPORTED_RATES] = {};
3930         int link_rate_index, test_link_rate;
3931         uint8_t test_lane_count, test_link_bw;
3932         /* (DP CTS 1.2)
3933          * 4.3.1.11
3934          */
3935         /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
3936         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
3937                                    &test_lane_count);
3938
3939         if (status <= 0) {
3940                 DRM_DEBUG_KMS("Lane count read failed\n");
3941                 return DP_TEST_NAK;
3942         }
3943         test_lane_count &= DP_MAX_LANE_COUNT_MASK;
3944         /* Validate the requested lane count */
3945         if (test_lane_count < min_lane_count ||
3946             test_lane_count > intel_dp->max_sink_lane_count)
3947                 return DP_TEST_NAK;
3948
3949         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
3950                                    &test_link_bw);
3951         if (status <= 0) {
3952                 DRM_DEBUG_KMS("Link Rate read failed\n");
3953                 return DP_TEST_NAK;
3954         }
3955         /* Validate the requested link rate */
3956         test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
3957         link_rate_index = intel_dp_link_rate_index(intel_dp,
3958                                                    common_rates,
3959                                                    test_link_rate);
3960         if (link_rate_index < 0)
3961                 return DP_TEST_NAK;
3962
3963         intel_dp->compliance.test_lane_count = test_lane_count;
3964         intel_dp->compliance.test_link_rate = test_link_rate;
3965
3966         return DP_TEST_ACK;
3967 }
3968
3969 static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
3970 {
3971         uint8_t test_pattern;
3972         uint16_t test_misc;
3973         __be16 h_width, v_height;
3974         int status = 0;
3975
3976         /* Read the TEST_PATTERN (DP CTS 3.1.5) */
3977         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_PATTERN,
3978                                   &test_pattern, 1);
3979         if (status <= 0) {
3980                 DRM_DEBUG_KMS("Test pattern read failed\n");
3981                 return DP_TEST_NAK;
3982         }
3983         if (test_pattern != DP_COLOR_RAMP)
3984                 return DP_TEST_NAK;
3985
3986         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
3987                                   &h_width, 2);
3988         if (status <= 0) {
3989                 DRM_DEBUG_KMS("H Width read failed\n");
3990                 return DP_TEST_NAK;
3991         }
3992
3993         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
3994                                   &v_height, 2);
3995         if (status <= 0) {
3996                 DRM_DEBUG_KMS("V Height read failed\n");
3997                 return DP_TEST_NAK;
3998         }
3999
4000         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_MISC0,
4001                                   &test_misc, 1);
4002         if (status <= 0) {
4003                 DRM_DEBUG_KMS("TEST MISC read failed\n");
4004                 return DP_TEST_NAK;
4005         }
4006         if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
4007                 return DP_TEST_NAK;
4008         if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
4009                 return DP_TEST_NAK;
4010         switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
4011         case DP_TEST_BIT_DEPTH_6:
4012                 intel_dp->compliance.test_data.bpc = 6;
4013                 break;
4014         case DP_TEST_BIT_DEPTH_8:
4015                 intel_dp->compliance.test_data.bpc = 8;
4016                 break;
4017         default:
4018                 return DP_TEST_NAK;
4019         }
4020
4021         intel_dp->compliance.test_data.video_pattern = test_pattern;
4022         intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
4023         intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
4024         /* Set test active flag here so userspace doesn't interrupt things */
4025         intel_dp->compliance.test_active = 1;
4026
4027         return DP_TEST_ACK;
4028 }
4029
4030 static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
4031 {
4032         uint8_t test_result = DP_TEST_ACK;
4033         struct intel_connector *intel_connector = intel_dp->attached_connector;
4034         struct drm_connector *connector = &intel_connector->base;
4035
4036         if (intel_connector->detect_edid == NULL ||
4037             connector->edid_corrupt ||
4038             intel_dp->aux.i2c_defer_count > 6) {
4039                 /* Check EDID read for NACKs, DEFERs and corruption
4040                  * (DP CTS 1.2 Core r1.1)
4041                  *    4.2.2.4 : Failed EDID read, I2C_NAK
4042                  *    4.2.2.5 : Failed EDID read, I2C_DEFER
4043                  *    4.2.2.6 : EDID corruption detected
4044                  * Use failsafe mode for all cases
4045                  */
4046                 if (intel_dp->aux.i2c_nack_count > 0 ||
4047                         intel_dp->aux.i2c_defer_count > 0)
4048                         DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
4049                                       intel_dp->aux.i2c_nack_count,
4050                                       intel_dp->aux.i2c_defer_count);
4051                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
4052         } else {
4053                 struct edid *block = intel_connector->detect_edid;
4054
4055                 /* We have to write the checksum
4056                  * of the last block read
4057                  */
4058                 block += intel_connector->detect_edid->extensions;
4059
4060                 if (!drm_dp_dpcd_write(&intel_dp->aux,
4061                                         DP_TEST_EDID_CHECKSUM,
4062                                         &block->checksum,
4063                                         1))
4064                         DRM_DEBUG_KMS("Failed to write EDID checksum\n");
4065
4066                 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
4067                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
4068         }
4069
4070         /* Set test active flag here so userspace doesn't interrupt things */
4071         intel_dp->compliance.test_active = 1;
4072
4073         return test_result;
4074 }
4075
4076 static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
4077 {
4078         uint8_t test_result = DP_TEST_NAK;
4079         return test_result;
4080 }
4081
4082 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
4083 {
4084         uint8_t response = DP_TEST_NAK;
4085         uint8_t request = 0;
4086         int status;
4087
4088         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
4089         if (status <= 0) {
4090                 DRM_DEBUG_KMS("Could not read test request from sink\n");
4091                 goto update_status;
4092         }
4093
4094         switch (request) {
4095         case DP_TEST_LINK_TRAINING:
4096                 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
4097                 response = intel_dp_autotest_link_training(intel_dp);
4098                 break;
4099         case DP_TEST_LINK_VIDEO_PATTERN:
4100                 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
4101                 response = intel_dp_autotest_video_pattern(intel_dp);
4102                 break;
4103         case DP_TEST_LINK_EDID_READ:
4104                 DRM_DEBUG_KMS("EDID test requested\n");
4105                 response = intel_dp_autotest_edid(intel_dp);
4106                 break;
4107         case DP_TEST_LINK_PHY_TEST_PATTERN:
4108                 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
4109                 response = intel_dp_autotest_phy_pattern(intel_dp);
4110                 break;
4111         default:
4112                 DRM_DEBUG_KMS("Invalid test request '%02x'\n", request);
4113                 break;
4114         }
4115
4116         if (response & DP_TEST_ACK)
4117                 intel_dp->compliance.test_type = request;
4118
4119 update_status:
4120         status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
4121         if (status <= 0)
4122                 DRM_DEBUG_KMS("Could not write test response to sink\n");
4123 }
4124
4125 static int
4126 intel_dp_check_mst_status(struct intel_dp *intel_dp)
4127 {
4128         bool bret;
4129
4130         if (intel_dp->is_mst) {
4131                 u8 esi[16] = { 0 };
4132                 int ret = 0;
4133                 int retry;
4134                 bool handled;
4135                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4136 go_again:
4137                 if (bret == true) {
4138
4139                         /* check link status - esi[10] = 0x200c */
4140                         if (intel_dp->active_mst_links &&
4141                             !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
4142                                 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4143                                 intel_dp_start_link_train(intel_dp);
4144                                 intel_dp_stop_link_train(intel_dp);
4145                         }
4146
4147                         DRM_DEBUG_KMS("got esi %3ph\n", esi);
4148                         ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
4149
4150                         if (handled) {
4151                                 for (retry = 0; retry < 3; retry++) {
4152                                         int wret;
4153                                         wret = drm_dp_dpcd_write(&intel_dp->aux,
4154                                                                  DP_SINK_COUNT_ESI+1,
4155                                                                  &esi[1], 3);
4156                                         if (wret == 3) {
4157                                                 break;
4158                                         }
4159                                 }
4160
4161                                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4162                                 if (bret == true) {
4163                                         DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
4164                                         goto go_again;
4165                                 }
4166                         } else
4167                                 ret = 0;
4168
4169                         return ret;
4170                 } else {
4171                         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4172                         DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4173                         intel_dp->is_mst = false;
4174                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4175                         /* send a hotplug event */
4176                         drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
4177                 }
4178         }
4179         return -EINVAL;
4180 }
4181
4182 static void
4183 intel_dp_retrain_link(struct intel_dp *intel_dp)
4184 {
4185         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4186         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4187         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
4188
4189         /* Suppress underruns caused by re-training */
4190         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
4191         if (crtc->config->has_pch_encoder)
4192                 intel_set_pch_fifo_underrun_reporting(dev_priv,
4193                                                       intel_crtc_pch_transcoder(crtc), false);
4194
4195         intel_dp_start_link_train(intel_dp);
4196         intel_dp_stop_link_train(intel_dp);
4197
4198         /* Keep underrun reporting disabled until things are stable */
4199         intel_wait_for_vblank(dev_priv, crtc->pipe);
4200
4201         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
4202         if (crtc->config->has_pch_encoder)
4203                 intel_set_pch_fifo_underrun_reporting(dev_priv,
4204                                                       intel_crtc_pch_transcoder(crtc), true);
4205 }
4206
4207 static void
4208 intel_dp_check_link_status(struct intel_dp *intel_dp)
4209 {
4210         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4211         struct drm_device *dev = intel_dp_to_dev(intel_dp);
4212         u8 link_status[DP_LINK_STATUS_SIZE];
4213
4214         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
4215
4216         if (!intel_dp_get_link_status(intel_dp, link_status)) {
4217                 DRM_ERROR("Failed to get link status\n");
4218                 return;
4219         }
4220
4221         if (!intel_encoder->base.crtc)
4222                 return;
4223
4224         if (!to_intel_crtc(intel_encoder->base.crtc)->active)
4225                 return;
4226
4227         /* FIXME: we need to synchronize this sort of stuff with hardware
4228          * readout. Currently fast link training doesn't work on boot-up. */
4229         if (!intel_dp->lane_count)
4230                 return;
4231
4232         /* Retrain if Channel EQ or CR not ok */
4233         if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
4234                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
4235                               intel_encoder->base.name);
4236
4237                 intel_dp_retrain_link(intel_dp);
4238         }
4239 }
4240
4241 /*
4242  * According to DP spec
4243  * 5.1.2:
4244  *  1. Read DPCD
4245  *  2. Configure link according to Receiver Capabilities
4246  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
4247  *  4. Check link status on receipt of hot-plug interrupt
4248  *
4249  * intel_dp_short_pulse -  handles short pulse interrupts
4250  * when full detection is not required.
4251  * Returns %true if short pulse is handled and full detection
4252  * is NOT required and %false otherwise.
4253  */
4254 static bool
4255 intel_dp_short_pulse(struct intel_dp *intel_dp)
4256 {
4257         struct drm_device *dev = intel_dp_to_dev(intel_dp);
4258         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4259         u8 sink_irq_vector = 0;
4260         u8 old_sink_count = intel_dp->sink_count;
4261         bool ret;
4262
4263         /*
4264          * Clearing compliance test variables to allow capturing
4265          * of values for next automated test request.
4266          */
4267         memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4268
4269         /*
4270          * Now read the DPCD to see if it's actually running
4271          * If the current value of sink count doesn't match with
4272          * the value that was stored earlier or dpcd read failed
4273          * we need to do full detection
4274          */
4275         ret = intel_dp_get_dpcd(intel_dp);
4276
4277         if ((old_sink_count != intel_dp->sink_count) || !ret) {
4278                 /* No need to proceed if we are going to do full detect */
4279                 return false;
4280         }
4281
4282         /* Try to read the source of the interrupt */
4283         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4284             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) &&
4285             sink_irq_vector != 0) {
4286                 /* Clear interrupt source */
4287                 drm_dp_dpcd_writeb(&intel_dp->aux,
4288                                    DP_DEVICE_SERVICE_IRQ_VECTOR,
4289                                    sink_irq_vector);
4290
4291                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4292                         intel_dp_handle_test_request(intel_dp);
4293                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4294                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4295         }
4296
4297         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4298         intel_dp_check_link_status(intel_dp);
4299         drm_modeset_unlock(&dev->mode_config.connection_mutex);
4300         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
4301                 DRM_DEBUG_KMS("Link Training Compliance Test requested\n");
4302                 /* Send a Hotplug Uevent to userspace to start modeset */
4303                 drm_kms_helper_hotplug_event(intel_encoder->base.dev);
4304         }
4305
4306         return true;
4307 }
4308
4309 /* XXX this is probably wrong for multiple downstream ports */
4310 static enum drm_connector_status
4311 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
4312 {
4313         struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
4314         uint8_t *dpcd = intel_dp->dpcd;
4315         uint8_t type;
4316
4317         if (lspcon->active)
4318                 lspcon_resume(lspcon);
4319
4320         if (!intel_dp_get_dpcd(intel_dp))
4321                 return connector_status_disconnected;
4322
4323         if (is_edp(intel_dp))
4324                 return connector_status_connected;
4325
4326         /* if there's no downstream port, we're done */
4327         if (!drm_dp_is_branch(dpcd))
4328                 return connector_status_connected;
4329
4330         /* If we're HPD-aware, SINK_COUNT changes dynamically */
4331         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4332             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
4333
4334                 return intel_dp->sink_count ?
4335                 connector_status_connected : connector_status_disconnected;
4336         }
4337
4338         if (intel_dp_can_mst(intel_dp))
4339                 return connector_status_connected;
4340
4341         /* If no HPD, poke DDC gently */
4342         if (drm_probe_ddc(&intel_dp->aux.ddc))
4343                 return connector_status_connected;
4344
4345         /* Well we tried, say unknown for unreliable port types */
4346         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4347                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4348                 if (type == DP_DS_PORT_TYPE_VGA ||
4349                     type == DP_DS_PORT_TYPE_NON_EDID)
4350                         return connector_status_unknown;
4351         } else {
4352                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4353                         DP_DWN_STRM_PORT_TYPE_MASK;
4354                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4355                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
4356                         return connector_status_unknown;
4357         }
4358
4359         /* Anything else is out of spec, warn and ignore */
4360         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4361         return connector_status_disconnected;
4362 }
4363
4364 static enum drm_connector_status
4365 edp_detect(struct intel_dp *intel_dp)
4366 {
4367         struct drm_device *dev = intel_dp_to_dev(intel_dp);
4368         struct drm_i915_private *dev_priv = to_i915(dev);
4369         enum drm_connector_status status;
4370
4371         status = intel_panel_detect(dev_priv);
4372         if (status == connector_status_unknown)
4373                 status = connector_status_connected;
4374
4375         return status;
4376 }
4377
4378 static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
4379                                        struct intel_digital_port *port)
4380 {
4381         u32 bit;
4382
4383         switch (port->port) {
4384         case PORT_A:
4385                 return true;
4386         case PORT_B:
4387                 bit = SDE_PORTB_HOTPLUG;
4388                 break;
4389         case PORT_C:
4390                 bit = SDE_PORTC_HOTPLUG;
4391                 break;
4392         case PORT_D:
4393                 bit = SDE_PORTD_HOTPLUG;
4394                 break;
4395         default:
4396                 MISSING_CASE(port->port);
4397                 return false;
4398         }
4399
4400         return I915_READ(SDEISR) & bit;
4401 }
4402
4403 static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv,
4404                                        struct intel_digital_port *port)
4405 {
4406         u32 bit;
4407
4408         switch (port->port) {
4409         case PORT_A:
4410                 return true;
4411         case PORT_B:
4412                 bit = SDE_PORTB_HOTPLUG_CPT;
4413                 break;
4414         case PORT_C:
4415                 bit = SDE_PORTC_HOTPLUG_CPT;
4416                 break;
4417         case PORT_D:
4418                 bit = SDE_PORTD_HOTPLUG_CPT;
4419                 break;
4420         case PORT_E:
4421                 bit = SDE_PORTE_HOTPLUG_SPT;
4422                 break;
4423         default:
4424                 MISSING_CASE(port->port);
4425                 return false;
4426         }
4427
4428         return I915_READ(SDEISR) & bit;
4429 }
4430
4431 static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv,
4432                                        struct intel_digital_port *port)
4433 {
4434         u32 bit;
4435
4436         switch (port->port) {
4437         case PORT_B:
4438                 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4439                 break;
4440         case PORT_C:
4441                 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4442                 break;
4443         case PORT_D:
4444                 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4445                 break;
4446         default:
4447                 MISSING_CASE(port->port);
4448                 return false;
4449         }
4450
4451         return I915_READ(PORT_HOTPLUG_STAT) & bit;
4452 }
4453
4454 static bool gm45_digital_port_connected(struct drm_i915_private *dev_priv,
4455                                         struct intel_digital_port *port)
4456 {
4457         u32 bit;
4458
4459         switch (port->port) {
4460         case PORT_B:
4461                 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
4462                 break;
4463         case PORT_C:
4464                 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
4465                 break;
4466         case PORT_D:
4467                 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
4468                 break;
4469         default:
4470                 MISSING_CASE(port->port);
4471                 return false;
4472         }
4473
4474         return I915_READ(PORT_HOTPLUG_STAT) & bit;
4475 }
4476
4477 static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv,
4478                                        struct intel_digital_port *intel_dig_port)
4479 {
4480         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4481         enum port port;
4482         u32 bit;
4483
4484         intel_hpd_pin_to_port(intel_encoder->hpd_pin, &port);
4485         switch (port) {
4486         case PORT_A:
4487                 bit = BXT_DE_PORT_HP_DDIA;
4488                 break;
4489         case PORT_B:
4490                 bit = BXT_DE_PORT_HP_DDIB;
4491                 break;
4492         case PORT_C:
4493                 bit = BXT_DE_PORT_HP_DDIC;
4494                 break;
4495         default:
4496                 MISSING_CASE(port);
4497                 return false;
4498         }
4499
4500         return I915_READ(GEN8_DE_PORT_ISR) & bit;
4501 }
4502
4503 /*
4504  * intel_digital_port_connected - is the specified port connected?
4505  * @dev_priv: i915 private structure
4506  * @port: the port to test
4507  *
4508  * Return %true if @port is connected, %false otherwise.
4509  */
4510 bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
4511                                   struct intel_digital_port *port)
4512 {
4513         if (HAS_PCH_IBX(dev_priv))
4514                 return ibx_digital_port_connected(dev_priv, port);
4515         else if (HAS_PCH_SPLIT(dev_priv))
4516                 return cpt_digital_port_connected(dev_priv, port);
4517         else if (IS_GEN9_LP(dev_priv))
4518                 return bxt_digital_port_connected(dev_priv, port);
4519         else if (IS_GM45(dev_priv))
4520                 return gm45_digital_port_connected(dev_priv, port);
4521         else
4522                 return g4x_digital_port_connected(dev_priv, port);
4523 }
4524
4525 static struct edid *
4526 intel_dp_get_edid(struct intel_dp *intel_dp)
4527 {
4528         struct intel_connector *intel_connector = intel_dp->attached_connector;
4529
4530         /* use cached edid if we have one */
4531         if (intel_connector->edid) {
4532                 /* invalid edid */
4533                 if (IS_ERR(intel_connector->edid))
4534                         return NULL;
4535
4536                 return drm_edid_duplicate(intel_connector->edid);
4537         } else
4538                 return drm_get_edid(&intel_connector->base,
4539                                     &intel_dp->aux.ddc);
4540 }
4541
4542 static void
4543 intel_dp_set_edid(struct intel_dp *intel_dp)
4544 {
4545         struct intel_connector *intel_connector = intel_dp->attached_connector;
4546         struct edid *edid;
4547
4548         intel_dp_unset_edid(intel_dp);
4549         edid = intel_dp_get_edid(intel_dp);
4550         intel_connector->detect_edid = edid;
4551
4552         if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4553                 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4554         else
4555                 intel_dp->has_audio = drm_detect_monitor_audio(edid);
4556 }
4557
4558 static void
4559 intel_dp_unset_edid(struct intel_dp *intel_dp)
4560 {
4561         struct intel_connector *intel_connector = intel_dp->attached_connector;
4562
4563         kfree(intel_connector->detect_edid);
4564         intel_connector->detect_edid = NULL;
4565
4566         intel_dp->has_audio = false;
4567 }
4568
4569 static enum drm_connector_status
4570 intel_dp_long_pulse(struct intel_connector *intel_connector)
4571 {
4572         struct drm_connector *connector = &intel_connector->base;
4573         struct intel_dp *intel_dp = intel_attached_dp(connector);
4574         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4575         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4576         struct drm_device *dev = connector->dev;
4577         enum drm_connector_status status;
4578         u8 sink_irq_vector = 0;
4579
4580         intel_display_power_get(to_i915(dev), intel_dp->aux_power_domain);
4581
4582         /* Can't disconnect eDP, but you can close the lid... */
4583         if (is_edp(intel_dp))
4584                 status = edp_detect(intel_dp);
4585         else if (intel_digital_port_connected(to_i915(dev),
4586                                               dp_to_dig_port(intel_dp)))
4587                 status = intel_dp_detect_dpcd(intel_dp);
4588         else
4589                 status = connector_status_disconnected;
4590
4591         if (status == connector_status_disconnected) {
4592                 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4593
4594                 if (intel_dp->is_mst) {
4595                         DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4596                                       intel_dp->is_mst,
4597                                       intel_dp->mst_mgr.mst_state);
4598                         intel_dp->is_mst = false;
4599                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4600                                                         intel_dp->is_mst);
4601                 }
4602
4603                 goto out;
4604         }
4605
4606         if (intel_encoder->type != INTEL_OUTPUT_EDP)
4607                 intel_encoder->type = INTEL_OUTPUT_DP;
4608
4609         DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
4610                       yesno(intel_dp_source_supports_hbr2(intel_dp)),
4611                       yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
4612
4613         if (intel_dp->reset_link_params) {
4614                 /* Set the max lane count for sink */
4615                 intel_dp->max_sink_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
4616
4617                 /* Set the max link BW for sink */
4618                 intel_dp->max_sink_link_bw = intel_dp_max_link_bw(intel_dp);
4619
4620                 intel_dp->reset_link_params = false;
4621         }
4622
4623         intel_dp_print_rates(intel_dp);
4624
4625         intel_dp_read_desc(intel_dp);
4626
4627         intel_dp_configure_mst(intel_dp);
4628
4629         if (intel_dp->is_mst) {
4630                 /*
4631                  * If we are in MST mode then this connector
4632                  * won't appear connected or have anything
4633                  * with EDID on it
4634                  */
4635                 status = connector_status_disconnected;
4636                 goto out;
4637         } else if (connector->status == connector_status_connected) {
4638                 /*
4639                  * If display was connected already and is still connected
4640                  * check links status, there has been known issues of
4641                  * link loss triggerring long pulse!!!!
4642                  */
4643                 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4644                 intel_dp_check_link_status(intel_dp);
4645                 drm_modeset_unlock(&dev->mode_config.connection_mutex);
4646                 goto out;
4647         }
4648
4649         /*
4650          * Clearing NACK and defer counts to get their exact values
4651          * while reading EDID which are required by Compliance tests
4652          * 4.2.2.4 and 4.2.2.5
4653          */
4654         intel_dp->aux.i2c_nack_count = 0;
4655         intel_dp->aux.i2c_defer_count = 0;
4656
4657         intel_dp_set_edid(intel_dp);
4658         if (is_edp(intel_dp) || intel_connector->detect_edid)
4659                 status = connector_status_connected;
4660         intel_dp->detect_done = true;
4661
4662         /* Try to read the source of the interrupt */
4663         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4664             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) &&
4665             sink_irq_vector != 0) {
4666                 /* Clear interrupt source */
4667                 drm_dp_dpcd_writeb(&intel_dp->aux,
4668                                    DP_DEVICE_SERVICE_IRQ_VECTOR,
4669                                    sink_irq_vector);
4670
4671                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4672                         intel_dp_handle_test_request(intel_dp);
4673                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4674                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4675         }
4676
4677 out:
4678         if (status != connector_status_connected && !intel_dp->is_mst)
4679                 intel_dp_unset_edid(intel_dp);
4680
4681         intel_display_power_put(to_i915(dev), intel_dp->aux_power_domain);
4682         return status;
4683 }
4684
4685 static enum drm_connector_status
4686 intel_dp_detect(struct drm_connector *connector, bool force)
4687 {
4688         struct intel_dp *intel_dp = intel_attached_dp(connector);
4689         enum drm_connector_status status = connector->status;
4690
4691         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4692                       connector->base.id, connector->name);
4693
4694         /* If full detect is not performed yet, do a full detect */
4695         if (!intel_dp->detect_done)
4696                 status = intel_dp_long_pulse(intel_dp->attached_connector);
4697
4698         intel_dp->detect_done = false;
4699
4700         return status;
4701 }
4702
4703 static void
4704 intel_dp_force(struct drm_connector *connector)
4705 {
4706         struct intel_dp *intel_dp = intel_attached_dp(connector);
4707         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4708         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
4709
4710         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4711                       connector->base.id, connector->name);
4712         intel_dp_unset_edid(intel_dp);
4713
4714         if (connector->status != connector_status_connected)
4715                 return;
4716
4717         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
4718
4719         intel_dp_set_edid(intel_dp);
4720
4721         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
4722
4723         if (intel_encoder->type != INTEL_OUTPUT_EDP)
4724                 intel_encoder->type = INTEL_OUTPUT_DP;
4725 }
4726
4727 static int intel_dp_get_modes(struct drm_connector *connector)
4728 {
4729         struct intel_connector *intel_connector = to_intel_connector(connector);
4730         struct edid *edid;
4731
4732         edid = intel_connector->detect_edid;
4733         if (edid) {
4734                 int ret = intel_connector_update_modes(connector, edid);
4735                 if (ret)
4736                         return ret;
4737         }
4738
4739         /* if eDP has no EDID, fall back to fixed mode */
4740         if (is_edp(intel_attached_dp(connector)) &&
4741             intel_connector->panel.fixed_mode) {
4742                 struct drm_display_mode *mode;
4743
4744                 mode = drm_mode_duplicate(connector->dev,
4745                                           intel_connector->panel.fixed_mode);
4746                 if (mode) {
4747                         drm_mode_probed_add(connector, mode);
4748                         return 1;
4749                 }
4750         }
4751
4752         return 0;
4753 }
4754
4755 static bool
4756 intel_dp_detect_audio(struct drm_connector *connector)
4757 {
4758         bool has_audio = false;
4759         struct edid *edid;
4760
4761         edid = to_intel_connector(connector)->detect_edid;
4762         if (edid)
4763                 has_audio = drm_detect_monitor_audio(edid);
4764
4765         return has_audio;
4766 }
4767
4768 static int
4769 intel_dp_set_property(struct drm_connector *connector,
4770                       struct drm_property *property,
4771                       uint64_t val)
4772 {
4773         struct drm_i915_private *dev_priv = to_i915(connector->dev);
4774         struct intel_connector *intel_connector = to_intel_connector(connector);
4775         struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4776         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4777         int ret;
4778
4779         ret = drm_object_property_set_value(&connector->base, property, val);
4780         if (ret)
4781                 return ret;
4782
4783         if (property == dev_priv->force_audio_property) {
4784                 int i = val;
4785                 bool has_audio;
4786
4787                 if (i == intel_dp->force_audio)
4788                         return 0;
4789
4790                 intel_dp->force_audio = i;
4791
4792                 if (i == HDMI_AUDIO_AUTO)
4793                         has_audio = intel_dp_detect_audio(connector);
4794                 else
4795                         has_audio = (i == HDMI_AUDIO_ON);
4796
4797                 if (has_audio == intel_dp->has_audio)
4798                         return 0;
4799
4800                 intel_dp->has_audio = has_audio;
4801                 goto done;
4802         }
4803
4804         if (property == dev_priv->broadcast_rgb_property) {
4805                 bool old_auto = intel_dp->color_range_auto;
4806                 bool old_range = intel_dp->limited_color_range;
4807
4808                 switch (val) {
4809                 case INTEL_BROADCAST_RGB_AUTO:
4810                         intel_dp->color_range_auto = true;
4811                         break;
4812                 case INTEL_BROADCAST_RGB_FULL:
4813                         intel_dp->color_range_auto = false;
4814                         intel_dp->limited_color_range = false;
4815                         break;
4816                 case INTEL_BROADCAST_RGB_LIMITED:
4817                         intel_dp->color_range_auto = false;
4818                         intel_dp->limited_color_range = true;
4819                         break;
4820                 default:
4821                         return -EINVAL;
4822                 }
4823
4824                 if (old_auto == intel_dp->color_range_auto &&
4825                     old_range == intel_dp->limited_color_range)
4826                         return 0;
4827
4828                 goto done;
4829         }
4830
4831         if (is_edp(intel_dp) &&
4832             property == connector->dev->mode_config.scaling_mode_property) {
4833                 if (val == DRM_MODE_SCALE_NONE) {
4834                         DRM_DEBUG_KMS("no scaling not supported\n");
4835                         return -EINVAL;
4836                 }
4837                 if (HAS_GMCH_DISPLAY(dev_priv) &&
4838                     val == DRM_MODE_SCALE_CENTER) {
4839                         DRM_DEBUG_KMS("centering not supported\n");
4840                         return -EINVAL;
4841                 }
4842
4843                 if (intel_connector->panel.fitting_mode == val) {
4844                         /* the eDP scaling property is not changed */
4845                         return 0;
4846                 }
4847                 intel_connector->panel.fitting_mode = val;
4848
4849                 goto done;
4850         }
4851
4852         return -EINVAL;
4853
4854 done:
4855         if (intel_encoder->base.crtc)
4856                 intel_crtc_restore_mode(intel_encoder->base.crtc);
4857
4858         return 0;
4859 }
4860
4861 static int
4862 intel_dp_connector_register(struct drm_connector *connector)
4863 {
4864         struct intel_dp *intel_dp = intel_attached_dp(connector);
4865         int ret;
4866
4867         ret = intel_connector_register(connector);
4868         if (ret)
4869                 return ret;
4870
4871         i915_debugfs_connector_add(connector);
4872
4873         DRM_DEBUG_KMS("registering %s bus for %s\n",
4874                       intel_dp->aux.name, connector->kdev->kobj.name);
4875
4876         intel_dp->aux.dev = connector->kdev;
4877         return drm_dp_aux_register(&intel_dp->aux);
4878 }
4879
4880 static void
4881 intel_dp_connector_unregister(struct drm_connector *connector)
4882 {
4883         drm_dp_aux_unregister(&intel_attached_dp(connector)->aux);
4884         intel_connector_unregister(connector);
4885 }
4886
4887 static void
4888 intel_dp_connector_destroy(struct drm_connector *connector)
4889 {
4890         struct intel_connector *intel_connector = to_intel_connector(connector);
4891
4892         kfree(intel_connector->detect_edid);
4893
4894         if (!IS_ERR_OR_NULL(intel_connector->edid))
4895                 kfree(intel_connector->edid);
4896
4897         /* Can't call is_edp() since the encoder may have been destroyed
4898          * already. */
4899         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4900                 intel_panel_fini(&intel_connector->panel);
4901
4902         drm_connector_cleanup(connector);
4903         kfree(connector);
4904 }
4905
4906 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
4907 {
4908         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4909         struct intel_dp *intel_dp = &intel_dig_port->dp;
4910
4911         intel_dp_mst_encoder_cleanup(intel_dig_port);
4912         if (is_edp(intel_dp)) {
4913                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4914                 /*
4915                  * vdd might still be enabled do to the delayed vdd off.
4916                  * Make sure vdd is actually turned off here.
4917                  */
4918                 pps_lock(intel_dp);
4919                 edp_panel_vdd_off_sync(intel_dp);
4920                 pps_unlock(intel_dp);
4921
4922                 if (intel_dp->edp_notifier.notifier_call) {
4923                         unregister_reboot_notifier(&intel_dp->edp_notifier);
4924                         intel_dp->edp_notifier.notifier_call = NULL;
4925                 }
4926         }
4927
4928         intel_dp_aux_fini(intel_dp);
4929
4930         drm_encoder_cleanup(encoder);
4931         kfree(intel_dig_port);
4932 }
4933
4934 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4935 {
4936         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4937
4938         if (!is_edp(intel_dp))
4939                 return;
4940
4941         /*
4942          * vdd might still be enabled do to the delayed vdd off.
4943          * Make sure vdd is actually turned off here.
4944          */
4945         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4946         pps_lock(intel_dp);
4947         edp_panel_vdd_off_sync(intel_dp);
4948         pps_unlock(intel_dp);
4949 }
4950
4951 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
4952 {
4953         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4954         struct drm_device *dev = intel_dig_port->base.base.dev;
4955         struct drm_i915_private *dev_priv = to_i915(dev);
4956
4957         lockdep_assert_held(&dev_priv->pps_mutex);
4958
4959         if (!edp_have_panel_vdd(intel_dp))
4960                 return;
4961
4962         /*
4963          * The VDD bit needs a power domain reference, so if the bit is
4964          * already enabled when we boot or resume, grab this reference and
4965          * schedule a vdd off, so we don't hold on to the reference
4966          * indefinitely.
4967          */
4968         DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4969         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
4970
4971         edp_panel_vdd_schedule_off(intel_dp);
4972 }
4973
4974 static enum pipe vlv_active_pipe(struct intel_dp *intel_dp)
4975 {
4976         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
4977
4978         if ((intel_dp->DP & DP_PORT_EN) == 0)
4979                 return INVALID_PIPE;
4980
4981         if (IS_CHERRYVIEW(dev_priv))
4982                 return DP_PORT_TO_PIPE_CHV(intel_dp->DP);
4983         else
4984                 return PORT_TO_PIPE(intel_dp->DP);
4985 }
4986
4987 void intel_dp_encoder_reset(struct drm_encoder *encoder)
4988 {
4989         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
4990         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4991         struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
4992
4993         if (!HAS_DDI(dev_priv))
4994                 intel_dp->DP = I915_READ(intel_dp->output_reg);
4995
4996         if (lspcon->active)
4997                 lspcon_resume(lspcon);
4998
4999         intel_dp->reset_link_params = true;
5000
5001         pps_lock(intel_dp);
5002
5003         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5004                 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
5005
5006         if (is_edp(intel_dp)) {
5007                 /* Reinit the power sequencer, in case BIOS did something with it. */
5008                 intel_dp_pps_init(encoder->dev, intel_dp);
5009                 intel_edp_panel_vdd_sanitize(intel_dp);
5010         }
5011
5012         pps_unlock(intel_dp);
5013 }
5014
5015 static const struct drm_connector_funcs intel_dp_connector_funcs = {
5016         .dpms = drm_atomic_helper_connector_dpms,
5017         .detect = intel_dp_detect,
5018         .force = intel_dp_force,
5019         .fill_modes = drm_helper_probe_single_connector_modes,
5020         .set_property = intel_dp_set_property,
5021         .atomic_get_property = intel_connector_atomic_get_property,
5022         .late_register = intel_dp_connector_register,
5023         .early_unregister = intel_dp_connector_unregister,
5024         .destroy = intel_dp_connector_destroy,
5025         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
5026         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
5027 };
5028
5029 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
5030         .get_modes = intel_dp_get_modes,
5031         .mode_valid = intel_dp_mode_valid,
5032 };
5033
5034 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
5035         .reset = intel_dp_encoder_reset,
5036         .destroy = intel_dp_encoder_destroy,
5037 };
5038
5039 enum irqreturn
5040 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
5041 {
5042         struct intel_dp *intel_dp = &intel_dig_port->dp;
5043         struct drm_device *dev = intel_dig_port->base.base.dev;
5044         struct drm_i915_private *dev_priv = to_i915(dev);
5045         enum irqreturn ret = IRQ_NONE;
5046
5047         if (intel_dig_port->base.type != INTEL_OUTPUT_EDP &&
5048             intel_dig_port->base.type != INTEL_OUTPUT_HDMI)
5049                 intel_dig_port->base.type = INTEL_OUTPUT_DP;
5050
5051         if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
5052                 /*
5053                  * vdd off can generate a long pulse on eDP which
5054                  * would require vdd on to handle it, and thus we
5055                  * would end up in an endless cycle of
5056                  * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
5057                  */
5058                 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
5059                               port_name(intel_dig_port->port));
5060                 return IRQ_HANDLED;
5061         }
5062
5063         DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
5064                       port_name(intel_dig_port->port),
5065                       long_hpd ? "long" : "short");
5066
5067         if (long_hpd) {
5068                 intel_dp->reset_link_params = true;
5069                 intel_dp->detect_done = false;
5070                 return IRQ_NONE;
5071         }
5072
5073         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
5074
5075         if (intel_dp->is_mst) {
5076                 if (intel_dp_check_mst_status(intel_dp) == -EINVAL) {
5077                         /*
5078                          * If we were in MST mode, and device is not
5079                          * there, get out of MST mode
5080                          */
5081                         DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
5082                                       intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
5083                         intel_dp->is_mst = false;
5084                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5085                                                         intel_dp->is_mst);
5086                         intel_dp->detect_done = false;
5087                         goto put_power;
5088                 }
5089         }
5090
5091         if (!intel_dp->is_mst) {
5092                 if (!intel_dp_short_pulse(intel_dp)) {
5093                         intel_dp->detect_done = false;
5094                         goto put_power;
5095                 }
5096         }
5097
5098         ret = IRQ_HANDLED;
5099
5100 put_power:
5101         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
5102
5103         return ret;
5104 }
5105
5106 /* check the VBT to see whether the eDP is on another port */
5107 bool intel_dp_is_edp(struct drm_i915_private *dev_priv, enum port port)
5108 {
5109         /*
5110          * eDP not supported on g4x. so bail out early just
5111          * for a bit extra safety in case the VBT is bonkers.
5112          */
5113         if (INTEL_GEN(dev_priv) < 5)
5114                 return false;
5115
5116         if (INTEL_GEN(dev_priv) < 9 && port == PORT_A)
5117                 return true;
5118
5119         return intel_bios_is_port_edp(dev_priv, port);
5120 }
5121
5122 void
5123 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
5124 {
5125         struct intel_connector *intel_connector = to_intel_connector(connector);
5126
5127         intel_attach_force_audio_property(connector);
5128         intel_attach_broadcast_rgb_property(connector);
5129         intel_dp->color_range_auto = true;
5130
5131         if (is_edp(intel_dp)) {
5132                 drm_mode_create_scaling_mode_property(connector->dev);
5133                 drm_object_attach_property(
5134                         &connector->base,
5135                         connector->dev->mode_config.scaling_mode_property,
5136                         DRM_MODE_SCALE_ASPECT);
5137                 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
5138         }
5139 }
5140
5141 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
5142 {
5143         intel_dp->panel_power_off_time = ktime_get_boottime();
5144         intel_dp->last_power_on = jiffies;
5145         intel_dp->last_backlight_off = jiffies;
5146 }
5147
5148 static void
5149 intel_pps_readout_hw_state(struct drm_i915_private *dev_priv,
5150                            struct intel_dp *intel_dp, struct edp_power_seq *seq)
5151 {
5152         u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
5153         struct pps_registers regs;
5154
5155         intel_pps_get_registers(dev_priv, intel_dp, &regs);
5156
5157         /* Workaround: Need to write PP_CONTROL with the unlock key as
5158          * the very first thing. */
5159         pp_ctl = ironlake_get_pp_control(intel_dp);
5160
5161         pp_on = I915_READ(regs.pp_on);
5162         pp_off = I915_READ(regs.pp_off);
5163         if (!IS_GEN9_LP(dev_priv)) {
5164                 I915_WRITE(regs.pp_ctrl, pp_ctl);
5165                 pp_div = I915_READ(regs.pp_div);
5166         }
5167
5168         /* Pull timing values out of registers */
5169         seq->t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
5170                      PANEL_POWER_UP_DELAY_SHIFT;
5171
5172         seq->t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
5173                   PANEL_LIGHT_ON_DELAY_SHIFT;
5174
5175         seq->t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
5176                   PANEL_LIGHT_OFF_DELAY_SHIFT;
5177
5178         seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
5179                    PANEL_POWER_DOWN_DELAY_SHIFT;
5180
5181         if (IS_GEN9_LP(dev_priv)) {
5182                 u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
5183                         BXT_POWER_CYCLE_DELAY_SHIFT;
5184                 if (tmp > 0)
5185                         seq->t11_t12 = (tmp - 1) * 1000;
5186                 else
5187                         seq->t11_t12 = 0;
5188         } else {
5189                 seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
5190                        PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
5191         }
5192 }
5193
5194 static void
5195 intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
5196 {
5197         DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5198                       state_name,
5199                       seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
5200 }
5201
5202 static void
5203 intel_pps_verify_state(struct drm_i915_private *dev_priv,
5204                        struct intel_dp *intel_dp)
5205 {
5206         struct edp_power_seq hw;
5207         struct edp_power_seq *sw = &intel_dp->pps_delays;
5208
5209         intel_pps_readout_hw_state(dev_priv, intel_dp, &hw);
5210
5211         if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
5212             hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
5213                 DRM_ERROR("PPS state mismatch\n");
5214                 intel_pps_dump_state("sw", sw);
5215                 intel_pps_dump_state("hw", &hw);
5216         }
5217 }
5218
5219 static void
5220 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
5221                                     struct intel_dp *intel_dp)
5222 {
5223         struct drm_i915_private *dev_priv = to_i915(dev);
5224         struct edp_power_seq cur, vbt, spec,
5225                 *final = &intel_dp->pps_delays;
5226
5227         lockdep_assert_held(&dev_priv->pps_mutex);
5228
5229         /* already initialized? */
5230         if (final->t11_t12 != 0)
5231                 return;
5232
5233         intel_pps_readout_hw_state(dev_priv, intel_dp, &cur);
5234
5235         intel_pps_dump_state("cur", &cur);
5236
5237         vbt = dev_priv->vbt.edp.pps;
5238
5239         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
5240          * our hw here, which are all in 100usec. */
5241         spec.t1_t3 = 210 * 10;
5242         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
5243         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
5244         spec.t10 = 500 * 10;
5245         /* This one is special and actually in units of 100ms, but zero
5246          * based in the hw (so we need to add 100 ms). But the sw vbt
5247          * table multiplies it with 1000 to make it in units of 100usec,
5248          * too. */
5249         spec.t11_t12 = (510 + 100) * 10;
5250
5251         intel_pps_dump_state("vbt", &vbt);
5252
5253         /* Use the max of the register settings and vbt. If both are
5254          * unset, fall back to the spec limits. */
5255 #define assign_final(field)     final->field = (max(cur.field, vbt.field) == 0 ? \
5256                                        spec.field : \
5257                                        max(cur.field, vbt.field))
5258         assign_final(t1_t3);
5259         assign_final(t8);
5260         assign_final(t9);
5261         assign_final(t10);
5262         assign_final(t11_t12);
5263 #undef assign_final
5264
5265 #define get_delay(field)        (DIV_ROUND_UP(final->field, 10))
5266         intel_dp->panel_power_up_delay = get_delay(t1_t3);
5267         intel_dp->backlight_on_delay = get_delay(t8);
5268         intel_dp->backlight_off_delay = get_delay(t9);
5269         intel_dp->panel_power_down_delay = get_delay(t10);
5270         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
5271 #undef get_delay
5272
5273         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
5274                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
5275                       intel_dp->panel_power_cycle_delay);
5276
5277         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
5278                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
5279
5280         /*
5281          * We override the HW backlight delays to 1 because we do manual waits
5282          * on them. For T8, even BSpec recommends doing it. For T9, if we
5283          * don't do this, we'll end up waiting for the backlight off delay
5284          * twice: once when we do the manual sleep, and once when we disable
5285          * the panel and wait for the PP_STATUS bit to become zero.
5286          */
5287         final->t8 = 1;
5288         final->t9 = 1;
5289 }
5290
5291 static void
5292 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
5293                                               struct intel_dp *intel_dp,
5294                                               bool force_disable_vdd)
5295 {
5296         struct drm_i915_private *dev_priv = to_i915(dev);
5297         u32 pp_on, pp_off, pp_div, port_sel = 0;
5298         int div = dev_priv->rawclk_freq / 1000;
5299         struct pps_registers regs;
5300         enum port port = dp_to_dig_port(intel_dp)->port;
5301         const struct edp_power_seq *seq = &intel_dp->pps_delays;
5302
5303         lockdep_assert_held(&dev_priv->pps_mutex);
5304
5305         intel_pps_get_registers(dev_priv, intel_dp, &regs);
5306
5307         /*
5308          * On some VLV machines the BIOS can leave the VDD
5309          * enabled even on power seqeuencers which aren't
5310          * hooked up to any port. This would mess up the
5311          * power domain tracking the first time we pick
5312          * one of these power sequencers for use since
5313          * edp_panel_vdd_on() would notice that the VDD was
5314          * already on and therefore wouldn't grab the power
5315          * domain reference. Disable VDD first to avoid this.
5316          * This also avoids spuriously turning the VDD on as
5317          * soon as the new power seqeuencer gets initialized.
5318          */
5319         if (force_disable_vdd) {
5320                 u32 pp = ironlake_get_pp_control(intel_dp);
5321
5322                 WARN(pp & PANEL_POWER_ON, "Panel power already on\n");
5323
5324                 if (pp & EDP_FORCE_VDD)
5325                         DRM_DEBUG_KMS("VDD already on, disabling first\n");
5326
5327                 pp &= ~EDP_FORCE_VDD;
5328
5329                 I915_WRITE(regs.pp_ctrl, pp);
5330         }
5331
5332         pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
5333                 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
5334         pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
5335                  (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
5336         /* Compute the divisor for the pp clock, simply match the Bspec
5337          * formula. */
5338         if (IS_GEN9_LP(dev_priv)) {
5339                 pp_div = I915_READ(regs.pp_ctrl);
5340                 pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
5341                 pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
5342                                 << BXT_POWER_CYCLE_DELAY_SHIFT);
5343         } else {
5344                 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
5345                 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
5346                                 << PANEL_POWER_CYCLE_DELAY_SHIFT);
5347         }
5348
5349         /* Haswell doesn't have any port selection bits for the panel
5350          * power sequencer any more. */
5351         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5352                 port_sel = PANEL_PORT_SELECT_VLV(port);
5353         } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
5354                 if (port == PORT_A)
5355                         port_sel = PANEL_PORT_SELECT_DPA;
5356                 else
5357                         port_sel = PANEL_PORT_SELECT_DPD;
5358         }
5359
5360         pp_on |= port_sel;
5361
5362         I915_WRITE(regs.pp_on, pp_on);
5363         I915_WRITE(regs.pp_off, pp_off);
5364         if (IS_GEN9_LP(dev_priv))
5365                 I915_WRITE(regs.pp_ctrl, pp_div);
5366         else
5367                 I915_WRITE(regs.pp_div, pp_div);
5368
5369         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
5370                       I915_READ(regs.pp_on),
5371                       I915_READ(regs.pp_off),
5372                       IS_GEN9_LP(dev_priv) ?
5373                       (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
5374                       I915_READ(regs.pp_div));
5375 }
5376
5377 static void intel_dp_pps_init(struct drm_device *dev,
5378                               struct intel_dp *intel_dp)
5379 {
5380         struct drm_i915_private *dev_priv = to_i915(dev);
5381
5382         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5383                 vlv_initial_power_sequencer_setup(intel_dp);
5384         } else {
5385                 intel_dp_init_panel_power_sequencer(dev, intel_dp);
5386                 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, false);
5387         }
5388 }
5389
5390 /**
5391  * intel_dp_set_drrs_state - program registers for RR switch to take effect
5392  * @dev_priv: i915 device
5393  * @crtc_state: a pointer to the active intel_crtc_state
5394  * @refresh_rate: RR to be programmed
5395  *
5396  * This function gets called when refresh rate (RR) has to be changed from
5397  * one frequency to another. Switches can be between high and low RR
5398  * supported by the panel or to any other RR based on media playback (in
5399  * this case, RR value needs to be passed from user space).
5400  *
5401  * The caller of this function needs to take a lock on dev_priv->drrs.
5402  */
5403 static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
5404                                     struct intel_crtc_state *crtc_state,
5405                                     int refresh_rate)
5406 {
5407         struct intel_encoder *encoder;
5408         struct intel_digital_port *dig_port = NULL;
5409         struct intel_dp *intel_dp = dev_priv->drrs.dp;
5410         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
5411         enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
5412
5413         if (refresh_rate <= 0) {
5414                 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5415                 return;
5416         }
5417
5418         if (intel_dp == NULL) {
5419                 DRM_DEBUG_KMS("DRRS not supported.\n");
5420                 return;
5421         }
5422
5423         /*
5424          * FIXME: This needs proper synchronization with psr state for some
5425          * platforms that cannot have PSR and DRRS enabled at the same time.
5426          */
5427
5428         dig_port = dp_to_dig_port(intel_dp);
5429         encoder = &dig_port->base;
5430         intel_crtc = to_intel_crtc(encoder->base.crtc);
5431
5432         if (!intel_crtc) {
5433                 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5434                 return;
5435         }
5436
5437         if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
5438                 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5439                 return;
5440         }
5441
5442         if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
5443                         refresh_rate)
5444                 index = DRRS_LOW_RR;
5445
5446         if (index == dev_priv->drrs.refresh_rate_type) {
5447                 DRM_DEBUG_KMS(
5448                         "DRRS requested for previously set RR...ignoring\n");
5449                 return;
5450         }
5451
5452         if (!crtc_state->base.active) {
5453                 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5454                 return;
5455         }
5456
5457         if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
5458                 switch (index) {
5459                 case DRRS_HIGH_RR:
5460                         intel_dp_set_m_n(intel_crtc, M1_N1);
5461                         break;
5462                 case DRRS_LOW_RR:
5463                         intel_dp_set_m_n(intel_crtc, M2_N2);
5464                         break;
5465                 case DRRS_MAX_RR:
5466                 default:
5467                         DRM_ERROR("Unsupported refreshrate type\n");
5468                 }
5469         } else if (INTEL_GEN(dev_priv) > 6) {
5470                 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
5471                 u32 val;
5472
5473                 val = I915_READ(reg);
5474                 if (index > DRRS_HIGH_RR) {
5475                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5476                                 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5477                         else
5478                                 val |= PIPECONF_EDP_RR_MODE_SWITCH;
5479                 } else {
5480                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5481                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5482                         else
5483                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
5484                 }
5485                 I915_WRITE(reg, val);
5486         }
5487
5488         dev_priv->drrs.refresh_rate_type = index;
5489
5490         DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
5491 }
5492
5493 /**
5494  * intel_edp_drrs_enable - init drrs struct if supported
5495  * @intel_dp: DP struct
5496  * @crtc_state: A pointer to the active crtc state.
5497  *
5498  * Initializes frontbuffer_bits and drrs.dp
5499  */
5500 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
5501                            struct intel_crtc_state *crtc_state)
5502 {
5503         struct drm_device *dev = intel_dp_to_dev(intel_dp);
5504         struct drm_i915_private *dev_priv = to_i915(dev);
5505
5506         if (!crtc_state->has_drrs) {
5507                 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5508                 return;
5509         }
5510
5511         mutex_lock(&dev_priv->drrs.mutex);
5512         if (WARN_ON(dev_priv->drrs.dp)) {
5513                 DRM_ERROR("DRRS already enabled\n");
5514                 goto unlock;
5515         }
5516
5517         dev_priv->drrs.busy_frontbuffer_bits = 0;
5518
5519         dev_priv->drrs.dp = intel_dp;
5520
5521 unlock:
5522         mutex_unlock(&dev_priv->drrs.mutex);
5523 }
5524
5525 /**
5526  * intel_edp_drrs_disable - Disable DRRS
5527  * @intel_dp: DP struct
5528  * @old_crtc_state: Pointer to old crtc_state.
5529  *
5530  */
5531 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
5532                             struct intel_crtc_state *old_crtc_state)
5533 {
5534         struct drm_device *dev = intel_dp_to_dev(intel_dp);
5535         struct drm_i915_private *dev_priv = to_i915(dev);
5536
5537         if (!old_crtc_state->has_drrs)
5538                 return;
5539
5540         mutex_lock(&dev_priv->drrs.mutex);
5541         if (!dev_priv->drrs.dp) {
5542                 mutex_unlock(&dev_priv->drrs.mutex);
5543                 return;
5544         }
5545
5546         if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5547                 intel_dp_set_drrs_state(dev_priv, old_crtc_state,
5548                         intel_dp->attached_connector->panel.fixed_mode->vrefresh);
5549
5550         dev_priv->drrs.dp = NULL;
5551         mutex_unlock(&dev_priv->drrs.mutex);
5552
5553         cancel_delayed_work_sync(&dev_priv->drrs.work);
5554 }
5555
5556 static void intel_edp_drrs_downclock_work(struct work_struct *work)
5557 {
5558         struct drm_i915_private *dev_priv =
5559                 container_of(work, typeof(*dev_priv), drrs.work.work);
5560         struct intel_dp *intel_dp;
5561
5562         mutex_lock(&dev_priv->drrs.mutex);
5563
5564         intel_dp = dev_priv->drrs.dp;
5565
5566         if (!intel_dp)
5567                 goto unlock;
5568
5569         /*
5570          * The delayed work can race with an invalidate hence we need to
5571          * recheck.
5572          */
5573
5574         if (dev_priv->drrs.busy_frontbuffer_bits)
5575                 goto unlock;
5576
5577         if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
5578                 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
5579
5580                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5581                         intel_dp->attached_connector->panel.downclock_mode->vrefresh);
5582         }
5583
5584 unlock:
5585         mutex_unlock(&dev_priv->drrs.mutex);
5586 }
5587
5588 /**
5589  * intel_edp_drrs_invalidate - Disable Idleness DRRS
5590  * @dev_priv: i915 device
5591  * @frontbuffer_bits: frontbuffer plane tracking bits
5592  *
5593  * This function gets called everytime rendering on the given planes start.
5594  * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
5595  *
5596  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5597  */
5598 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
5599                                unsigned int frontbuffer_bits)
5600 {
5601         struct drm_crtc *crtc;
5602         enum pipe pipe;
5603
5604         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5605                 return;
5606
5607         cancel_delayed_work(&dev_priv->drrs.work);
5608
5609         mutex_lock(&dev_priv->drrs.mutex);
5610         if (!dev_priv->drrs.dp) {
5611                 mutex_unlock(&dev_priv->drrs.mutex);
5612                 return;
5613         }
5614
5615         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5616         pipe = to_intel_crtc(crtc)->pipe;
5617
5618         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5619         dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
5620
5621         /* invalidate means busy screen hence upclock */
5622         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5623                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5624                         dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
5625
5626         mutex_unlock(&dev_priv->drrs.mutex);
5627 }
5628
5629 /**
5630  * intel_edp_drrs_flush - Restart Idleness DRRS
5631  * @dev_priv: i915 device
5632  * @frontbuffer_bits: frontbuffer plane tracking bits
5633  *
5634  * This function gets called every time rendering on the given planes has
5635  * completed or flip on a crtc is completed. So DRRS should be upclocked
5636  * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5637  * if no other planes are dirty.
5638  *
5639  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5640  */
5641 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
5642                           unsigned int frontbuffer_bits)
5643 {
5644         struct drm_crtc *crtc;
5645         enum pipe pipe;
5646
5647         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5648                 return;
5649
5650         cancel_delayed_work(&dev_priv->drrs.work);
5651
5652         mutex_lock(&dev_priv->drrs.mutex);
5653         if (!dev_priv->drrs.dp) {
5654                 mutex_unlock(&dev_priv->drrs.mutex);
5655                 return;
5656         }
5657
5658         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5659         pipe = to_intel_crtc(crtc)->pipe;
5660
5661         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5662         dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
5663
5664         /* flush means busy screen hence upclock */
5665         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5666                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5667                                 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
5668
5669         /*
5670          * flush also means no more activity hence schedule downclock, if all
5671          * other fbs are quiescent too
5672          */
5673         if (!dev_priv->drrs.busy_frontbuffer_bits)
5674                 schedule_delayed_work(&dev_priv->drrs.work,
5675                                 msecs_to_jiffies(1000));
5676         mutex_unlock(&dev_priv->drrs.mutex);
5677 }
5678
5679 /**
5680  * DOC: Display Refresh Rate Switching (DRRS)
5681  *
5682  * Display Refresh Rate Switching (DRRS) is a power conservation feature
5683  * which enables swtching between low and high refresh rates,
5684  * dynamically, based on the usage scenario. This feature is applicable
5685  * for internal panels.
5686  *
5687  * Indication that the panel supports DRRS is given by the panel EDID, which
5688  * would list multiple refresh rates for one resolution.
5689  *
5690  * DRRS is of 2 types - static and seamless.
5691  * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5692  * (may appear as a blink on screen) and is used in dock-undock scenario.
5693  * Seamless DRRS involves changing RR without any visual effect to the user
5694  * and can be used during normal system usage. This is done by programming
5695  * certain registers.
5696  *
5697  * Support for static/seamless DRRS may be indicated in the VBT based on
5698  * inputs from the panel spec.
5699  *
5700  * DRRS saves power by switching to low RR based on usage scenarios.
5701  *
5702  * The implementation is based on frontbuffer tracking implementation.  When
5703  * there is a disturbance on the screen triggered by user activity or a periodic
5704  * system activity, DRRS is disabled (RR is changed to high RR).  When there is
5705  * no movement on screen, after a timeout of 1 second, a switch to low RR is
5706  * made.
5707  *
5708  * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
5709  * and intel_edp_drrs_flush() are called.
5710  *
5711  * DRRS can be further extended to support other internal panels and also
5712  * the scenario of video playback wherein RR is set based on the rate
5713  * requested by userspace.
5714  */
5715
5716 /**
5717  * intel_dp_drrs_init - Init basic DRRS work and mutex.
5718  * @intel_connector: eDP connector
5719  * @fixed_mode: preferred mode of panel
5720  *
5721  * This function is  called only once at driver load to initialize basic
5722  * DRRS stuff.
5723  *
5724  * Returns:
5725  * Downclock mode if panel supports it, else return NULL.
5726  * DRRS support is determined by the presence of downclock mode (apart
5727  * from VBT setting).
5728  */
5729 static struct drm_display_mode *
5730 intel_dp_drrs_init(struct intel_connector *intel_connector,
5731                 struct drm_display_mode *fixed_mode)
5732 {
5733         struct drm_connector *connector = &intel_connector->base;
5734         struct drm_device *dev = connector->dev;
5735         struct drm_i915_private *dev_priv = to_i915(dev);
5736         struct drm_display_mode *downclock_mode = NULL;
5737
5738         INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
5739         mutex_init(&dev_priv->drrs.mutex);
5740
5741         if (INTEL_GEN(dev_priv) <= 6) {
5742                 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5743                 return NULL;
5744         }
5745
5746         if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
5747                 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
5748                 return NULL;
5749         }
5750
5751         downclock_mode = intel_find_panel_downclock
5752                                         (dev_priv, fixed_mode, connector);
5753
5754         if (!downclock_mode) {
5755                 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
5756                 return NULL;
5757         }
5758
5759         dev_priv->drrs.type = dev_priv->vbt.drrs_type;
5760
5761         dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
5762         DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
5763         return downclock_mode;
5764 }
5765
5766 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
5767                                      struct intel_connector *intel_connector)
5768 {
5769         struct drm_connector *connector = &intel_connector->base;
5770         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5771         struct intel_encoder *intel_encoder = &intel_dig_port->base;
5772         struct drm_device *dev = intel_encoder->base.dev;
5773         struct drm_i915_private *dev_priv = to_i915(dev);
5774         struct drm_display_mode *fixed_mode = NULL;
5775         struct drm_display_mode *downclock_mode = NULL;
5776         bool has_dpcd;
5777         struct drm_display_mode *scan;
5778         struct edid *edid;
5779         enum pipe pipe = INVALID_PIPE;
5780
5781         if (!is_edp(intel_dp))
5782                 return true;
5783
5784         /*
5785          * On IBX/CPT we may get here with LVDS already registered. Since the
5786          * driver uses the only internal power sequencer available for both
5787          * eDP and LVDS bail out early in this case to prevent interfering
5788          * with an already powered-on LVDS power sequencer.
5789          */
5790         if (intel_get_lvds_encoder(dev)) {
5791                 WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
5792                 DRM_INFO("LVDS was detected, not registering eDP\n");
5793
5794                 return false;
5795         }
5796
5797         pps_lock(intel_dp);
5798
5799         intel_dp_init_panel_power_timestamps(intel_dp);
5800         intel_dp_pps_init(dev, intel_dp);
5801         intel_edp_panel_vdd_sanitize(intel_dp);
5802
5803         pps_unlock(intel_dp);
5804
5805         /* Cache DPCD and EDID for edp. */
5806         has_dpcd = intel_edp_init_dpcd(intel_dp);
5807
5808         if (!has_dpcd) {
5809                 /* if this fails, presume the device is a ghost */
5810                 DRM_INFO("failed to retrieve link info, disabling eDP\n");
5811                 goto out_vdd_off;
5812         }
5813
5814         mutex_lock(&dev->mode_config.mutex);
5815         edid = drm_get_edid(connector, &intel_dp->aux.ddc);
5816         if (edid) {
5817                 if (drm_add_edid_modes(connector, edid)) {
5818                         drm_mode_connector_update_edid_property(connector,
5819                                                                 edid);
5820                         drm_edid_to_eld(connector, edid);
5821                 } else {
5822                         kfree(edid);
5823                         edid = ERR_PTR(-EINVAL);
5824                 }
5825         } else {
5826                 edid = ERR_PTR(-ENOENT);
5827         }
5828         intel_connector->edid = edid;
5829
5830         /* prefer fixed mode from EDID if available */
5831         list_for_each_entry(scan, &connector->probed_modes, head) {
5832                 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5833                         fixed_mode = drm_mode_duplicate(dev, scan);
5834                         downclock_mode = intel_dp_drrs_init(
5835                                                 intel_connector, fixed_mode);
5836                         break;
5837                 }
5838         }
5839
5840         /* fallback to VBT if available for eDP */
5841         if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5842                 fixed_mode = drm_mode_duplicate(dev,
5843                                         dev_priv->vbt.lfp_lvds_vbt_mode);
5844                 if (fixed_mode) {
5845                         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
5846                         connector->display_info.width_mm = fixed_mode->width_mm;
5847                         connector->display_info.height_mm = fixed_mode->height_mm;
5848                 }
5849         }
5850         mutex_unlock(&dev->mode_config.mutex);
5851
5852         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5853                 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5854                 register_reboot_notifier(&intel_dp->edp_notifier);
5855
5856                 /*
5857                  * Figure out the current pipe for the initial backlight setup.
5858                  * If the current pipe isn't valid, try the PPS pipe, and if that
5859                  * fails just assume pipe A.
5860                  */
5861                 pipe = vlv_active_pipe(intel_dp);
5862
5863                 if (pipe != PIPE_A && pipe != PIPE_B)
5864                         pipe = intel_dp->pps_pipe;
5865
5866                 if (pipe != PIPE_A && pipe != PIPE_B)
5867                         pipe = PIPE_A;
5868
5869                 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5870                               pipe_name(pipe));
5871         }
5872
5873         intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
5874         intel_connector->panel.backlight.power = intel_edp_backlight_power;
5875         intel_panel_setup_backlight(connector, pipe);
5876
5877         return true;
5878
5879 out_vdd_off:
5880         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5881         /*
5882          * vdd might still be enabled do to the delayed vdd off.
5883          * Make sure vdd is actually turned off here.
5884          */
5885         pps_lock(intel_dp);
5886         edp_panel_vdd_off_sync(intel_dp);
5887         pps_unlock(intel_dp);
5888
5889         return false;
5890 }
5891
5892 /* Set up the hotplug pin and aux power domain. */
5893 static void
5894 intel_dp_init_connector_port_info(struct intel_digital_port *intel_dig_port)
5895 {
5896         struct intel_encoder *encoder = &intel_dig_port->base;
5897         struct intel_dp *intel_dp = &intel_dig_port->dp;
5898
5899         switch (intel_dig_port->port) {
5900         case PORT_A:
5901                 encoder->hpd_pin = HPD_PORT_A;
5902                 intel_dp->aux_power_domain = POWER_DOMAIN_AUX_A;
5903                 break;
5904         case PORT_B:
5905                 encoder->hpd_pin = HPD_PORT_B;
5906                 intel_dp->aux_power_domain = POWER_DOMAIN_AUX_B;
5907                 break;
5908         case PORT_C:
5909                 encoder->hpd_pin = HPD_PORT_C;
5910                 intel_dp->aux_power_domain = POWER_DOMAIN_AUX_C;
5911                 break;
5912         case PORT_D:
5913                 encoder->hpd_pin = HPD_PORT_D;
5914                 intel_dp->aux_power_domain = POWER_DOMAIN_AUX_D;
5915                 break;
5916         case PORT_E:
5917                 encoder->hpd_pin = HPD_PORT_E;
5918
5919                 /* FIXME: Check VBT for actual wiring of PORT E */
5920                 intel_dp->aux_power_domain = POWER_DOMAIN_AUX_D;
5921                 break;
5922         default:
5923                 MISSING_CASE(intel_dig_port->port);
5924         }
5925 }
5926
5927 bool
5928 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
5929                         struct intel_connector *intel_connector)
5930 {
5931         struct drm_connector *connector = &intel_connector->base;
5932         struct intel_dp *intel_dp = &intel_dig_port->dp;
5933         struct intel_encoder *intel_encoder = &intel_dig_port->base;
5934         struct drm_device *dev = intel_encoder->base.dev;
5935         struct drm_i915_private *dev_priv = to_i915(dev);
5936         enum port port = intel_dig_port->port;
5937         int type;
5938
5939         if (WARN(intel_dig_port->max_lanes < 1,
5940                  "Not enough lanes (%d) for DP on port %c\n",
5941                  intel_dig_port->max_lanes, port_name(port)))
5942                 return false;
5943
5944         intel_dp->reset_link_params = true;
5945         intel_dp->pps_pipe = INVALID_PIPE;
5946         intel_dp->active_pipe = INVALID_PIPE;
5947
5948         /* intel_dp vfuncs */
5949         if (INTEL_GEN(dev_priv) >= 9)
5950                 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
5951         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5952                 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
5953         else if (HAS_PCH_SPLIT(dev_priv))
5954                 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5955         else
5956                 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
5957
5958         if (INTEL_GEN(dev_priv) >= 9)
5959                 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
5960         else
5961                 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
5962
5963         if (HAS_DDI(dev_priv))
5964                 intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain;
5965
5966         /* Preserve the current hw state. */
5967         intel_dp->DP = I915_READ(intel_dp->output_reg);
5968         intel_dp->attached_connector = intel_connector;
5969
5970         if (intel_dp_is_edp(dev_priv, port))
5971                 type = DRM_MODE_CONNECTOR_eDP;
5972         else
5973                 type = DRM_MODE_CONNECTOR_DisplayPort;
5974
5975         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5976                 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
5977
5978         /*
5979          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5980          * for DP the encoder type can be set by the caller to
5981          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5982          */
5983         if (type == DRM_MODE_CONNECTOR_eDP)
5984                 intel_encoder->type = INTEL_OUTPUT_EDP;
5985
5986         /* eDP only on port B and/or C on vlv/chv */
5987         if (WARN_ON((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
5988                     is_edp(intel_dp) && port != PORT_B && port != PORT_C))
5989                 return false;
5990
5991         DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5992                         type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5993                         port_name(port));
5994
5995         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
5996         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5997
5998         connector->interlace_allowed = true;
5999         connector->doublescan_allowed = 0;
6000
6001         intel_dp_init_connector_port_info(intel_dig_port);
6002
6003         intel_dp_aux_init(intel_dp);
6004
6005         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
6006                           edp_panel_vdd_work);
6007
6008         intel_connector_attach_encoder(intel_connector, intel_encoder);
6009
6010         if (HAS_DDI(dev_priv))
6011                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
6012         else
6013                 intel_connector->get_hw_state = intel_connector_get_hw_state;
6014
6015         /* init MST on ports that can support it */
6016         if (HAS_DP_MST(dev_priv) && !is_edp(intel_dp) &&
6017             (port == PORT_B || port == PORT_C || port == PORT_D))
6018                 intel_dp_mst_encoder_init(intel_dig_port,
6019                                           intel_connector->base.base.id);
6020
6021         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
6022                 intel_dp_aux_fini(intel_dp);
6023                 intel_dp_mst_encoder_cleanup(intel_dig_port);
6024                 goto fail;
6025         }
6026
6027         intel_dp_add_properties(intel_dp, connector);
6028
6029         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
6030          * 0xd.  Failure to do so will result in spurious interrupts being
6031          * generated on the port when a cable is not attached.
6032          */
6033         if (IS_G4X(dev_priv) && !IS_GM45(dev_priv)) {
6034                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
6035                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
6036         }
6037
6038         return true;
6039
6040 fail:
6041         drm_connector_cleanup(connector);
6042
6043         return false;
6044 }
6045
6046 bool intel_dp_init(struct drm_i915_private *dev_priv,
6047                    i915_reg_t output_reg,
6048                    enum port port)
6049 {
6050         struct intel_digital_port *intel_dig_port;
6051         struct intel_encoder *intel_encoder;
6052         struct drm_encoder *encoder;
6053         struct intel_connector *intel_connector;
6054
6055         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
6056         if (!intel_dig_port)
6057                 return false;
6058
6059         intel_connector = intel_connector_alloc();
6060         if (!intel_connector)
6061                 goto err_connector_alloc;
6062
6063         intel_encoder = &intel_dig_port->base;
6064         encoder = &intel_encoder->base;
6065
6066         if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
6067                              &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS,
6068                              "DP %c", port_name(port)))
6069                 goto err_encoder_init;
6070
6071         intel_encoder->compute_config = intel_dp_compute_config;
6072         intel_encoder->disable = intel_disable_dp;
6073         intel_encoder->get_hw_state = intel_dp_get_hw_state;
6074         intel_encoder->get_config = intel_dp_get_config;
6075         intel_encoder->suspend = intel_dp_encoder_suspend;
6076         if (IS_CHERRYVIEW(dev_priv)) {
6077                 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
6078                 intel_encoder->pre_enable = chv_pre_enable_dp;
6079                 intel_encoder->enable = vlv_enable_dp;
6080                 intel_encoder->post_disable = chv_post_disable_dp;
6081                 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
6082         } else if (IS_VALLEYVIEW(dev_priv)) {
6083                 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
6084                 intel_encoder->pre_enable = vlv_pre_enable_dp;
6085                 intel_encoder->enable = vlv_enable_dp;
6086                 intel_encoder->post_disable = vlv_post_disable_dp;
6087         } else {
6088                 intel_encoder->pre_enable = g4x_pre_enable_dp;
6089                 intel_encoder->enable = g4x_enable_dp;
6090                 if (INTEL_GEN(dev_priv) >= 5)
6091                         intel_encoder->post_disable = ilk_post_disable_dp;
6092         }
6093
6094         intel_dig_port->port = port;
6095         intel_dig_port->dp.output_reg = output_reg;
6096         intel_dig_port->max_lanes = 4;
6097
6098         intel_encoder->type = INTEL_OUTPUT_DP;
6099         intel_encoder->power_domain = intel_port_to_power_domain(port);
6100         if (IS_CHERRYVIEW(dev_priv)) {
6101                 if (port == PORT_D)
6102                         intel_encoder->crtc_mask = 1 << 2;
6103                 else
6104                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
6105         } else {
6106                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
6107         }
6108         intel_encoder->cloneable = 0;
6109         intel_encoder->port = port;
6110
6111         intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
6112         dev_priv->hotplug.irq_port[port] = intel_dig_port;
6113
6114         if (!intel_dp_init_connector(intel_dig_port, intel_connector))
6115                 goto err_init_connector;
6116
6117         return true;
6118
6119 err_init_connector:
6120         drm_encoder_cleanup(encoder);
6121 err_encoder_init:
6122         kfree(intel_connector);
6123 err_connector_alloc:
6124         kfree(intel_dig_port);
6125         return false;
6126 }
6127
6128 void intel_dp_mst_suspend(struct drm_device *dev)
6129 {
6130         struct drm_i915_private *dev_priv = to_i915(dev);
6131         int i;
6132
6133         /* disable MST */
6134         for (i = 0; i < I915_MAX_PORTS; i++) {
6135                 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
6136
6137                 if (!intel_dig_port || !intel_dig_port->dp.can_mst)
6138                         continue;
6139
6140                 if (intel_dig_port->dp.is_mst)
6141                         drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
6142         }
6143 }
6144
6145 void intel_dp_mst_resume(struct drm_device *dev)
6146 {
6147         struct drm_i915_private *dev_priv = to_i915(dev);
6148         int i;
6149
6150         for (i = 0; i < I915_MAX_PORTS; i++) {
6151                 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
6152                 int ret;
6153
6154                 if (!intel_dig_port || !intel_dig_port->dp.can_mst)
6155                         continue;
6156
6157                 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
6158                 if (ret)
6159                         intel_dp_check_mst_status(&intel_dig_port->dp);
6160         }
6161 }