2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #ifndef __INTEL_DRV_H__
26 #define __INTEL_DRV_H__
28 #include <linux/async.h>
29 #include <linux/i2c.h>
30 #include <linux/hdmi.h>
31 #include <drm/i915_drm.h>
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_crtc_helper.h>
35 #include <drm/drm_fb_helper.h>
36 #include <drm/drm_dp_mst_helper.h>
37 #include <drm/drm_rect.h>
39 #define DIV_ROUND_CLOSEST_ULL(ll, d) \
40 ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
43 * _wait_for - magic (register) wait macro
45 * Does the right thing for modeset paths when run under kdgb or similar atomic
46 * contexts. Note that it's important that we check the condition again after
47 * having timed out, since the timeout could be due to preemption or similar and
48 * we've never had a chance to check the condition before the timeout.
50 #define _wait_for(COND, MS, W) ({ \
51 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \
54 if (time_after(jiffies, timeout__)) { \
59 if (W && drm_can_sleep()) { \
68 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
69 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
70 #define wait_for_atomic_us(COND, US) _wait_for((COND), \
71 DIV_ROUND_UP((US), 1000), 0)
73 #define KHz(x) (1000 * (x))
74 #define MHz(x) KHz(1000 * (x))
77 * Display related stuff
80 /* store information about an Ixxx DVO */
81 /* The i830->i865 use multiple DVOs with multiple i2cs */
82 /* the i915, i945 have a single sDVO i2c bus - which is different */
84 /* maximum connectors per crtcs in the mode set */
86 /* Maximum cursor sizes */
87 #define GEN2_CURSOR_WIDTH 64
88 #define GEN2_CURSOR_HEIGHT 64
89 #define MAX_CURSOR_WIDTH 256
90 #define MAX_CURSOR_HEIGHT 256
92 #define INTEL_I2C_BUS_DVO 1
93 #define INTEL_I2C_BUS_SDVO 2
95 /* these are outputs from the chip - integrated only
96 external chips are via DVO or SDVO output */
97 enum intel_output_type {
98 INTEL_OUTPUT_UNUSED = 0,
99 INTEL_OUTPUT_ANALOG = 1,
100 INTEL_OUTPUT_DVO = 2,
101 INTEL_OUTPUT_SDVO = 3,
102 INTEL_OUTPUT_LVDS = 4,
103 INTEL_OUTPUT_TVOUT = 5,
104 INTEL_OUTPUT_HDMI = 6,
105 INTEL_OUTPUT_DISPLAYPORT = 7,
106 INTEL_OUTPUT_EDP = 8,
107 INTEL_OUTPUT_DSI = 9,
108 INTEL_OUTPUT_UNKNOWN = 10,
109 INTEL_OUTPUT_DP_MST = 11,
112 #define INTEL_DVO_CHIP_NONE 0
113 #define INTEL_DVO_CHIP_LVDS 1
114 #define INTEL_DVO_CHIP_TMDS 2
115 #define INTEL_DVO_CHIP_TVOUT 4
117 #define INTEL_DSI_VIDEO_MODE 0
118 #define INTEL_DSI_COMMAND_MODE 1
120 struct intel_framebuffer {
121 struct drm_framebuffer base;
122 struct drm_i915_gem_object *obj;
126 struct drm_fb_helper helper;
127 struct intel_framebuffer *fb;
128 struct list_head fbdev_list;
129 struct drm_display_mode *our_mode;
133 struct intel_encoder {
134 struct drm_encoder base;
136 * The new crtc this encoder will be driven from. Only differs from
137 * base->crtc while a modeset is in progress.
139 struct intel_crtc *new_crtc;
141 enum intel_output_type type;
142 unsigned int cloneable;
143 bool connectors_active;
144 void (*hot_plug)(struct intel_encoder *);
145 bool (*compute_config)(struct intel_encoder *,
146 struct intel_crtc_config *);
147 void (*pre_pll_enable)(struct intel_encoder *);
148 void (*pre_enable)(struct intel_encoder *);
149 void (*enable)(struct intel_encoder *);
150 void (*mode_set)(struct intel_encoder *intel_encoder);
151 void (*disable)(struct intel_encoder *);
152 void (*post_disable)(struct intel_encoder *);
153 /* Read out the current hw state of this connector, returning true if
154 * the encoder is active. If the encoder is enabled it also set the pipe
155 * it is connected to in the pipe parameter. */
156 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
157 /* Reconstructs the equivalent mode flags for the current hardware
158 * state. This must be called _after_ display->get_pipe_config has
159 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
160 * be set correctly before calling this function. */
161 void (*get_config)(struct intel_encoder *,
162 struct intel_crtc_config *pipe_config);
164 * Called during system suspend after all pending requests for the
165 * encoder are flushed (for example for DP AUX transactions) and
166 * device interrupts are disabled.
168 void (*suspend)(struct intel_encoder *);
170 enum hpd_pin hpd_pin;
174 struct drm_display_mode *fixed_mode;
175 struct drm_display_mode *downclock_mode;
185 bool combination_mode; /* gen 2/4 only */
187 struct backlight_device *device;
190 void (*backlight_power)(struct intel_connector *, bool enable);
193 struct intel_connector {
194 struct drm_connector base;
196 * The fixed encoder this connector is connected to.
198 struct intel_encoder *encoder;
201 * The new encoder this connector will be driven. Only differs from
202 * encoder while a modeset is in progress.
204 struct intel_encoder *new_encoder;
206 /* Reads out the current hw, returning true if the connector is enabled
207 * and active (i.e. dpms ON state). */
208 bool (*get_hw_state)(struct intel_connector *);
211 * Removes all interfaces through which the connector is accessible
212 * - like sysfs, debugfs entries -, so that no new operations can be
213 * started on the connector. Also makes sure all currently pending
214 * operations finish before returing.
216 void (*unregister)(struct intel_connector *);
218 /* Panel info for eDP and LVDS */
219 struct intel_panel panel;
221 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
223 struct edid *detect_edid;
225 /* since POLL and HPD connectors may use the same HPD line keep the native
226 state of connector->polled in case hotplug storm detection changes it */
229 void *port; /* store this opaque as its illegal to dereference it */
231 struct intel_dp *mst_port;
234 typedef struct dpll {
246 struct intel_plane_state {
247 struct drm_crtc *crtc;
248 struct drm_framebuffer *fb;
251 struct drm_rect clip;
252 struct drm_rect orig_src;
253 struct drm_rect orig_dst;
257 struct intel_plane_config {
263 struct intel_crtc_config {
265 * quirks - bitfield with hw state readout quirks
267 * For various reasons the hw state readout code might not be able to
268 * completely faithfully read out the current state. These cases are
269 * tracked with quirk flags so that fastboot and state checker can act
272 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
273 #define PIPE_CONFIG_QUIRK_INHERITED_MODE (1<<1) /* mode inherited from firmware */
274 unsigned long quirks;
276 /* User requested mode, only valid as a starting point to
277 * compute adjusted_mode, except in the case of (S)DVO where
278 * it's also for the output timings of the (S)DVO chip.
279 * adjusted_mode will then correspond to the S(DVO) chip's
280 * preferred input timings. */
281 struct drm_display_mode requested_mode;
282 /* Actual pipe timings ie. what we program into the pipe timing
283 * registers. adjusted_mode.crtc_clock is the pipe pixel clock. */
284 struct drm_display_mode adjusted_mode;
286 /* Pipe source size (ie. panel fitter input size)
287 * All planes will be positioned inside this space,
288 * and get clipped at the edges. */
289 int pipe_src_w, pipe_src_h;
291 /* Whether to set up the PCH/FDI. Note that we never allow sharing
292 * between pch encoders and cpu encoders. */
293 bool has_pch_encoder;
295 /* Are we sending infoframes on the attached port */
298 /* CPU Transcoder for the pipe. Currently this can only differ from the
299 * pipe on Haswell (where we have a special eDP transcoder). */
300 enum transcoder cpu_transcoder;
303 * Use reduced/limited/broadcast rbg range, compressing from the full
304 * range fed into the crtcs.
306 bool limited_color_range;
308 /* DP has a bunch of special case unfortunately, so mark the pipe
312 /* Whether we should send NULL infoframes. Required for audio. */
315 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
316 * has_dp_encoder is set. */
320 * Enable dithering, used when the selected pipe bpp doesn't match the
325 /* Controls for the clock computation, to override various stages. */
328 /* SDVO TV has a bunch of special case. To make multifunction encoders
329 * work correctly, we need to track this at runtime.*/
333 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
334 * required. This is set in the 2nd loop of calling encoder's
335 * ->compute_config if the first pick doesn't work out.
339 /* Settings for the intel dpll used on pretty much everything but
343 /* Selected dpll when shared or DPLL_ID_PRIVATE. */
344 enum intel_dpll_id shared_dpll;
347 * - PORT_CLK_SEL for DDI ports on HSW/BDW.
348 * - enum skl_dpll on SKL
350 uint32_t ddi_pll_sel;
352 /* Actual register state of the dpll, for shared dpll cross-checking. */
353 struct intel_dpll_hw_state dpll_hw_state;
356 struct intel_link_m_n dp_m_n;
358 /* m2_n2 for eDP downclock */
359 struct intel_link_m_n dp_m2_n2;
363 * Frequence the dpll for the port should run at. Differs from the
364 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
365 * already multiplied by pixel_multiplier.
369 /* Used by SDVO (and if we ever fix it, HDMI). */
370 unsigned pixel_multiplier;
372 /* Panel fitter controls for gen2-gen4 + VLV */
376 u32 lvds_border_bits;
379 /* Panel fitter placement and size for Ironlake+ */
387 /* FDI configuration, only valid if has_pch_encoder is set. */
389 struct intel_link_m_n fdi_m_n;
395 bool dp_encoder_is_mst;
399 struct intel_pipe_wm {
400 struct intel_wm_level wm[5];
404 bool sprites_enabled;
408 struct intel_mmio_flip {
410 struct intel_engine_cs *ring;
411 struct work_struct work;
415 struct skl_wm_level wm[8];
416 struct skl_wm_level trans_wm;
421 struct drm_crtc base;
424 u8 lut_r[256], lut_g[256], lut_b[256];
426 * Whether the crtc and the connected output pipeline is active. Implies
427 * that crtc->enabled is set, i.e. the current mode configuration has
428 * some outputs connected to this crtc.
431 unsigned long enabled_power_domains;
432 bool primary_enabled; /* is the primary plane (partially) visible? */
434 struct intel_overlay *overlay;
435 struct intel_unpin_work *unpin_work;
437 atomic_t unpin_work_count;
439 /* Display surface base address adjustement for pageflips. Note that on
440 * gen4+ this only adjusts up to a tile, offsets within a tile are
441 * handled in the hw itself (with the TILEOFF register). */
442 unsigned long dspaddr_offset;
444 struct drm_i915_gem_object *cursor_bo;
445 uint32_t cursor_addr;
446 int16_t cursor_width, cursor_height;
447 uint32_t cursor_cntl;
448 uint32_t cursor_size;
449 uint32_t cursor_base;
451 struct intel_plane_config plane_config;
452 struct intel_crtc_config config;
453 struct intel_crtc_config *new_config;
456 /* reset counter value when the last flip was submitted */
457 unsigned int reset_counter;
459 /* Access to these should be protected by dev_priv->irq_lock. */
460 bool cpu_fifo_underrun_disabled;
461 bool pch_fifo_underrun_disabled;
463 /* per-pipe watermark state */
465 /* watermarks currently being used */
466 struct intel_pipe_wm active;
467 /* SKL wm values currently in use */
468 struct skl_pipe_wm skl_active;
472 struct intel_mmio_flip mmio_flip;
475 struct intel_plane_wm_parameters {
476 uint32_t horiz_pixels;
477 uint32_t vert_pixels;
478 uint8_t bytes_per_pixel;
484 struct drm_plane base;
487 struct drm_i915_gem_object *obj;
491 unsigned int crtc_w, crtc_h;
492 uint32_t src_x, src_y;
493 uint32_t src_w, src_h;
494 unsigned int rotation;
496 /* Since we need to change the watermarks before/after
497 * enabling/disabling the planes, we need to store the parameters here
498 * as the other pieces of the struct may not reflect the values we want
499 * for the watermark calculations. Currently only Haswell uses this.
501 struct intel_plane_wm_parameters wm;
503 void (*update_plane)(struct drm_plane *plane,
504 struct drm_crtc *crtc,
505 struct drm_framebuffer *fb,
506 struct drm_i915_gem_object *obj,
507 int crtc_x, int crtc_y,
508 unsigned int crtc_w, unsigned int crtc_h,
509 uint32_t x, uint32_t y,
510 uint32_t src_w, uint32_t src_h);
511 void (*disable_plane)(struct drm_plane *plane,
512 struct drm_crtc *crtc);
513 int (*update_colorkey)(struct drm_plane *plane,
514 struct drm_intel_sprite_colorkey *key);
515 void (*get_colorkey)(struct drm_plane *plane,
516 struct drm_intel_sprite_colorkey *key);
519 struct intel_watermark_params {
520 unsigned long fifo_size;
521 unsigned long max_wm;
522 unsigned long default_wm;
523 unsigned long guard_size;
524 unsigned long cacheline_size;
527 struct cxsr_latency {
530 unsigned long fsb_freq;
531 unsigned long mem_freq;
532 unsigned long display_sr;
533 unsigned long display_hpll_disable;
534 unsigned long cursor_sr;
535 unsigned long cursor_hpll_disable;
538 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
539 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
540 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
541 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
542 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
543 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
548 uint32_t color_range;
549 bool color_range_auto;
552 enum hdmi_force_audio force_audio;
553 bool rgb_quant_range_selectable;
554 enum hdmi_picture_aspect aspect_ratio;
555 void (*write_infoframe)(struct drm_encoder *encoder,
556 enum hdmi_infoframe_type type,
557 const void *frame, ssize_t len);
558 void (*set_infoframes)(struct drm_encoder *encoder,
560 struct drm_display_mode *adjusted_mode);
561 bool (*infoframe_enabled)(struct drm_encoder *encoder);
564 struct intel_dp_mst_encoder;
565 #define DP_MAX_DOWNSTREAM_PORTS 0x10
568 * HIGH_RR is the highest eDP panel refresh rate read from EDID
569 * LOW_RR is the lowest eDP panel refresh rate found from EDID
570 * parsing for same resolution.
572 enum edp_drrs_refresh_rate_type {
575 DRRS_MAX_RR, /* RR count */
580 uint32_t aux_ch_ctl_reg;
583 enum hdmi_force_audio force_audio;
584 uint32_t color_range;
585 bool color_range_auto;
588 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
589 uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
590 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
591 struct drm_dp_aux aux;
592 uint8_t train_set[4];
593 int panel_power_up_delay;
594 int panel_power_down_delay;
595 int panel_power_cycle_delay;
596 int backlight_on_delay;
597 int backlight_off_delay;
598 struct delayed_work panel_vdd_work;
600 unsigned long last_power_cycle;
601 unsigned long last_power_on;
602 unsigned long last_backlight_off;
604 struct notifier_block edp_notifier;
607 * Pipe whose power sequencer is currently locked into
608 * this port. Only relevant on VLV/CHV.
611 struct edp_power_seq pps_delays;
614 bool can_mst; /* this port supports mst */
616 int active_mst_links;
617 /* connector directly attached - won't be use for modeset in mst world */
618 struct intel_connector *attached_connector;
620 /* mst connector list */
621 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
622 struct drm_dp_mst_topology_mgr mst_mgr;
624 uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
626 * This function returns the value we have to program the AUX_CTL
627 * register with to kick off an AUX transaction.
629 uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
632 uint32_t aux_clock_divider);
634 enum drrs_support_type type;
635 enum edp_drrs_refresh_rate_type refresh_rate_type;
641 struct intel_digital_port {
642 struct intel_encoder base;
646 struct intel_hdmi hdmi;
647 bool (*hpd_pulse)(struct intel_digital_port *, bool);
650 struct intel_dp_mst_encoder {
651 struct intel_encoder base;
653 struct intel_digital_port *primary;
654 void *port; /* store this opaque as its illegal to dereference it */
658 vlv_dport_to_channel(struct intel_digital_port *dport)
660 switch (dport->port) {
672 vlv_pipe_to_channel(enum pipe pipe)
685 static inline struct drm_crtc *
686 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
688 struct drm_i915_private *dev_priv = dev->dev_private;
689 return dev_priv->pipe_to_crtc_mapping[pipe];
692 static inline struct drm_crtc *
693 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
695 struct drm_i915_private *dev_priv = dev->dev_private;
696 return dev_priv->plane_to_crtc_mapping[plane];
699 struct intel_unpin_work {
700 struct work_struct work;
701 struct drm_crtc *crtc;
702 struct drm_i915_gem_object *old_fb_obj;
703 struct drm_i915_gem_object *pending_flip_obj;
704 struct drm_pending_vblank_event *event;
706 #define INTEL_FLIP_INACTIVE 0
707 #define INTEL_FLIP_PENDING 1
708 #define INTEL_FLIP_COMPLETE 2
711 struct intel_engine_cs *flip_queued_ring;
712 u32 flip_queued_seqno;
713 int flip_queued_vblank;
714 int flip_ready_vblank;
715 bool enable_stall_check;
718 struct intel_set_config {
719 struct drm_encoder **save_connector_encoders;
720 struct drm_crtc **save_encoder_crtcs;
721 bool *save_crtc_enabled;
727 struct intel_load_detect_pipe {
728 struct drm_framebuffer *release_fb;
729 bool load_detect_temp;
733 static inline struct intel_encoder *
734 intel_attached_encoder(struct drm_connector *connector)
736 return to_intel_connector(connector)->encoder;
739 static inline struct intel_digital_port *
740 enc_to_dig_port(struct drm_encoder *encoder)
742 return container_of(encoder, struct intel_digital_port, base.base);
745 static inline struct intel_dp_mst_encoder *
746 enc_to_mst(struct drm_encoder *encoder)
748 return container_of(encoder, struct intel_dp_mst_encoder, base.base);
751 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
753 return &enc_to_dig_port(encoder)->dp;
756 static inline struct intel_digital_port *
757 dp_to_dig_port(struct intel_dp *intel_dp)
759 return container_of(intel_dp, struct intel_digital_port, dp);
762 static inline struct intel_digital_port *
763 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
765 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
769 * Returns the number of planes for this pipe, ie the number of sprites + 1
770 * (primary plane). This doesn't count the cursor plane then.
772 static inline unsigned int intel_num_planes(struct intel_crtc *crtc)
774 return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1;
777 /* intel_fifo_underrun.c */
778 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
779 enum pipe pipe, bool enable);
780 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
781 enum transcoder pch_transcoder,
783 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
785 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
786 enum transcoder pch_transcoder);
787 void i9xx_check_fifo_underruns(struct drm_i915_private *dev_priv);
790 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
791 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
792 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
793 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
794 void gen6_reset_rps_interrupts(struct drm_device *dev);
795 void gen6_enable_rps_interrupts(struct drm_device *dev);
796 void gen6_disable_rps_interrupts(struct drm_device *dev);
797 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask);
798 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
799 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
800 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
803 * We only use drm_irq_uninstall() at unload and VT switch, so
804 * this is the only thing we need to check.
806 return dev_priv->pm.irqs_enabled;
809 int intel_get_crtc_scanline(struct intel_crtc *crtc);
810 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv);
813 void intel_crt_init(struct drm_device *dev);
817 void intel_prepare_ddi(struct drm_device *dev);
818 void hsw_fdi_link_train(struct drm_crtc *crtc);
819 void intel_ddi_init(struct drm_device *dev, enum port port);
820 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
821 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
822 int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
823 void intel_ddi_pll_init(struct drm_device *dev);
824 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
825 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
826 enum transcoder cpu_transcoder);
827 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
828 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
829 bool intel_ddi_pll_select(struct intel_crtc *crtc);
830 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
831 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
832 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
833 void intel_ddi_fdi_disable(struct drm_crtc *crtc);
834 void intel_ddi_get_config(struct intel_encoder *encoder,
835 struct intel_crtc_config *pipe_config);
837 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
838 void intel_ddi_clock_get(struct intel_encoder *encoder,
839 struct intel_crtc_config *pipe_config);
840 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
842 /* intel_frontbuffer.c */
843 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
844 struct intel_engine_cs *ring);
845 void intel_frontbuffer_flip_prepare(struct drm_device *dev,
846 unsigned frontbuffer_bits);
847 void intel_frontbuffer_flip_complete(struct drm_device *dev,
848 unsigned frontbuffer_bits);
849 void intel_frontbuffer_flush(struct drm_device *dev,
850 unsigned frontbuffer_bits);
852 * intel_frontbuffer_flip - synchronous frontbuffer flip
854 * @frontbuffer_bits: frontbuffer plane tracking bits
856 * This function gets called after scheduling a flip on @obj. This is for
857 * synchronous plane updates which will happen on the next vblank and which will
858 * not get delayed by pending gpu rendering.
860 * Can be called without any locks held.
863 void intel_frontbuffer_flip(struct drm_device *dev,
864 unsigned frontbuffer_bits)
866 intel_frontbuffer_flush(dev, frontbuffer_bits);
869 void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire);
873 void intel_init_audio(struct drm_device *dev);
874 void intel_audio_codec_enable(struct intel_encoder *encoder);
875 void intel_audio_codec_disable(struct intel_encoder *encoder);
877 /* intel_display.c */
878 const char *intel_output_name(int output);
879 bool intel_has_pending_fb_unpin(struct drm_device *dev);
880 int intel_pch_rawclk(struct drm_device *dev);
881 void intel_mark_busy(struct drm_device *dev);
882 void intel_mark_idle(struct drm_device *dev);
883 void intel_crtc_restore_mode(struct drm_crtc *crtc);
884 void intel_crtc_control(struct drm_crtc *crtc, bool enable);
885 void intel_crtc_update_dpms(struct drm_crtc *crtc);
886 void intel_encoder_destroy(struct drm_encoder *encoder);
887 void intel_connector_dpms(struct drm_connector *, int mode);
888 bool intel_connector_get_hw_state(struct intel_connector *connector);
889 void intel_modeset_check_state(struct drm_device *dev);
890 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
891 struct intel_digital_port *port);
892 void intel_connector_attach_encoder(struct intel_connector *connector,
893 struct intel_encoder *encoder);
894 struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
895 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
896 struct drm_crtc *crtc);
897 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
898 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
899 struct drm_file *file_priv);
900 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
902 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type);
904 intel_wait_for_vblank(struct drm_device *dev, int pipe)
906 drm_wait_one_vblank(dev, pipe);
908 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
909 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
910 struct intel_digital_port *dport);
911 bool intel_get_load_detect_pipe(struct drm_connector *connector,
912 struct drm_display_mode *mode,
913 struct intel_load_detect_pipe *old,
914 struct drm_modeset_acquire_ctx *ctx);
915 void intel_release_load_detect_pipe(struct drm_connector *connector,
916 struct intel_load_detect_pipe *old);
917 int intel_pin_and_fence_fb_obj(struct drm_plane *plane,
918 struct drm_framebuffer *fb,
919 struct intel_engine_cs *pipelined);
920 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
921 struct drm_framebuffer *
922 __intel_framebuffer_create(struct drm_device *dev,
923 struct drm_mode_fb_cmd2 *mode_cmd,
924 struct drm_i915_gem_object *obj);
925 void intel_prepare_page_flip(struct drm_device *dev, int plane);
926 void intel_finish_page_flip(struct drm_device *dev, int pipe);
927 void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
928 void intel_check_page_flip(struct drm_device *dev, int pipe);
930 /* shared dpll functions */
931 struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
932 void assert_shared_dpll(struct drm_i915_private *dev_priv,
933 struct intel_shared_dpll *pll,
935 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
936 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
937 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc);
938 void intel_put_shared_dpll(struct intel_crtc *crtc);
940 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
941 const struct dpll *dpll);
942 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe);
944 /* modesetting asserts */
945 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
947 void assert_pll(struct drm_i915_private *dev_priv,
948 enum pipe pipe, bool state);
949 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
950 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
951 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
952 enum pipe pipe, bool state);
953 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
954 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
955 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
956 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
957 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
958 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
959 unsigned int tiling_mode,
962 void intel_prepare_reset(struct drm_device *dev);
963 void intel_finish_reset(struct drm_device *dev);
964 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
965 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
966 void intel_dp_get_m_n(struct intel_crtc *crtc,
967 struct intel_crtc_config *pipe_config);
968 void intel_dp_set_m_n(struct intel_crtc *crtc);
969 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
971 ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
973 bool intel_crtc_active(struct drm_crtc *crtc);
974 void hsw_enable_ips(struct intel_crtc *crtc);
975 void hsw_disable_ips(struct intel_crtc *crtc);
976 enum intel_display_power_domain
977 intel_display_port_power_domain(struct intel_encoder *intel_encoder);
978 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
979 struct intel_crtc_config *pipe_config);
980 int intel_format_to_fourcc(int format);
981 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc);
982 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file);
985 void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
986 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
987 struct intel_connector *intel_connector);
988 void intel_dp_start_link_train(struct intel_dp *intel_dp);
989 void intel_dp_complete_link_train(struct intel_dp *intel_dp);
990 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
991 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
992 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
993 void intel_dp_check_link_status(struct intel_dp *intel_dp);
994 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
995 bool intel_dp_compute_config(struct intel_encoder *encoder,
996 struct intel_crtc_config *pipe_config);
997 bool intel_dp_is_edp(struct drm_device *dev, enum port port);
998 bool intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1000 void intel_edp_backlight_on(struct intel_dp *intel_dp);
1001 void intel_edp_backlight_off(struct intel_dp *intel_dp);
1002 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1003 void intel_edp_panel_on(struct intel_dp *intel_dp);
1004 void intel_edp_panel_off(struct intel_dp *intel_dp);
1005 void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate);
1006 void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
1007 void intel_dp_mst_suspend(struct drm_device *dev);
1008 void intel_dp_mst_resume(struct drm_device *dev);
1009 int intel_dp_max_link_bw(struct intel_dp *intel_dp);
1010 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1011 void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv);
1012 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1013 void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes);
1015 /* intel_dp_mst.c */
1016 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1017 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1019 void intel_dsi_init(struct drm_device *dev);
1023 void intel_dvo_init(struct drm_device *dev);
1026 /* legacy fbdev emulation in intel_fbdev.c */
1027 #ifdef CONFIG_DRM_I915_FBDEV
1028 extern int intel_fbdev_init(struct drm_device *dev);
1029 extern void intel_fbdev_initial_config(void *data, async_cookie_t cookie);
1030 extern void intel_fbdev_fini(struct drm_device *dev);
1031 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1032 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1033 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1035 static inline int intel_fbdev_init(struct drm_device *dev)
1040 static inline void intel_fbdev_initial_config(void *data, async_cookie_t cookie)
1044 static inline void intel_fbdev_fini(struct drm_device *dev)
1048 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1052 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1058 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port);
1059 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1060 struct intel_connector *intel_connector);
1061 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1062 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1063 struct intel_crtc_config *pipe_config);
1067 void intel_lvds_init(struct drm_device *dev);
1068 bool intel_is_dual_link_lvds(struct drm_device *dev);
1072 int intel_connector_update_modes(struct drm_connector *connector,
1074 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1075 void intel_attach_force_audio_property(struct drm_connector *connector);
1076 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1079 /* intel_overlay.c */
1080 void intel_setup_overlay(struct drm_device *dev);
1081 void intel_cleanup_overlay(struct drm_device *dev);
1082 int intel_overlay_switch_off(struct intel_overlay *overlay);
1083 int intel_overlay_put_image(struct drm_device *dev, void *data,
1084 struct drm_file *file_priv);
1085 int intel_overlay_attrs(struct drm_device *dev, void *data,
1086 struct drm_file *file_priv);
1090 int intel_panel_init(struct intel_panel *panel,
1091 struct drm_display_mode *fixed_mode,
1092 struct drm_display_mode *downclock_mode);
1093 void intel_panel_fini(struct intel_panel *panel);
1094 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1095 struct drm_display_mode *adjusted_mode);
1096 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1097 struct intel_crtc_config *pipe_config,
1099 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1100 struct intel_crtc_config *pipe_config,
1102 void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1103 u32 level, u32 max);
1104 int intel_panel_setup_backlight(struct drm_connector *connector, enum pipe pipe);
1105 void intel_panel_enable_backlight(struct intel_connector *connector);
1106 void intel_panel_disable_backlight(struct intel_connector *connector);
1107 void intel_panel_destroy_backlight(struct drm_connector *connector);
1108 void intel_panel_init_backlight_funcs(struct drm_device *dev);
1109 enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1110 extern struct drm_display_mode *intel_find_panel_downclock(
1111 struct drm_device *dev,
1112 struct drm_display_mode *fixed_mode,
1113 struct drm_connector *connector);
1114 void intel_backlight_register(struct drm_device *dev);
1115 void intel_backlight_unregister(struct drm_device *dev);
1119 bool intel_psr_is_enabled(struct drm_device *dev);
1120 void intel_psr_enable(struct intel_dp *intel_dp);
1121 void intel_psr_disable(struct intel_dp *intel_dp);
1122 void intel_psr_invalidate(struct drm_device *dev,
1123 unsigned frontbuffer_bits);
1124 void intel_psr_flush(struct drm_device *dev,
1125 unsigned frontbuffer_bits);
1126 void intel_psr_init(struct drm_device *dev);
1128 /* intel_runtime_pm.c */
1129 int intel_power_domains_init(struct drm_i915_private *);
1130 void intel_power_domains_fini(struct drm_i915_private *);
1131 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv);
1132 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1134 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1135 enum intel_display_power_domain domain);
1136 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1137 enum intel_display_power_domain domain);
1138 void intel_display_power_get(struct drm_i915_private *dev_priv,
1139 enum intel_display_power_domain domain);
1140 void intel_display_power_put(struct drm_i915_private *dev_priv,
1141 enum intel_display_power_domain domain);
1142 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv);
1143 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv);
1144 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1145 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1146 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1148 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1151 void intel_init_clock_gating(struct drm_device *dev);
1152 void intel_suspend_hw(struct drm_device *dev);
1153 int ilk_wm_max_level(const struct drm_device *dev);
1154 void intel_update_watermarks(struct drm_crtc *crtc);
1155 void intel_update_sprite_watermarks(struct drm_plane *plane,
1156 struct drm_crtc *crtc,
1157 uint32_t sprite_width,
1158 uint32_t sprite_height,
1160 bool enabled, bool scaled);
1161 void intel_init_pm(struct drm_device *dev);
1162 void intel_pm_setup(struct drm_device *dev);
1163 bool intel_fbc_enabled(struct drm_device *dev);
1164 void intel_update_fbc(struct drm_device *dev);
1165 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1166 void intel_gpu_ips_teardown(void);
1167 void intel_init_gt_powersave(struct drm_device *dev);
1168 void intel_cleanup_gt_powersave(struct drm_device *dev);
1169 void intel_enable_gt_powersave(struct drm_device *dev);
1170 void intel_disable_gt_powersave(struct drm_device *dev);
1171 void intel_suspend_gt_powersave(struct drm_device *dev);
1172 void intel_reset_gt_powersave(struct drm_device *dev);
1173 void ironlake_teardown_rc6(struct drm_device *dev);
1174 void gen6_update_ring_freq(struct drm_device *dev);
1175 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1176 void gen6_rps_boost(struct drm_i915_private *dev_priv);
1177 void ilk_wm_get_hw_state(struct drm_device *dev);
1178 void skl_wm_get_hw_state(struct drm_device *dev);
1179 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1180 struct skl_ddb_allocation *ddb /* out */);
1184 bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob);
1187 /* intel_sprite.c */
1188 int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
1189 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
1191 int intel_plane_set_property(struct drm_plane *plane,
1192 struct drm_property *prop,
1194 int intel_plane_restore(struct drm_plane *plane);
1195 void intel_plane_disable(struct drm_plane *plane);
1196 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1197 struct drm_file *file_priv);
1198 int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
1199 struct drm_file *file_priv);
1200 bool intel_pipe_update_start(struct intel_crtc *crtc,
1201 uint32_t *start_vbl_count);
1202 void intel_pipe_update_end(struct intel_crtc *crtc, u32 start_vbl_count);
1205 void intel_tv_init(struct drm_device *dev);
1207 #endif /* __INTEL_DRV_H__ */